2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
38 #include "mini-amd64.h"
39 #include "cpu-amd64.h"
40 #include "debugger-agent.h"
44 static gboolean optimize_for_xen = TRUE;
46 #define optimize_for_xen 0
49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
56 /* Under windows, the calling convention is never stdcall */
57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
62 /* This mutex protects architecture specific caches */
63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
65 static mono_mutex_t mini_arch_mutex;
68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
71 * The code generated for sequence points reads from this location, which is
72 * made read-only when single stepping is enabled.
74 static gpointer ss_trigger_page;
76 /* Enabled breakpoints read from this trigger page */
77 static gpointer bp_trigger_page;
79 /* The size of the breakpoint sequence */
80 static int breakpoint_size;
82 /* The size of the breakpoint instruction causing the actual fault */
83 static int breakpoint_fault_size;
85 /* The size of the single step instruction causing the actual fault */
86 static int single_step_fault_size;
88 /* The single step trampoline */
89 static gpointer ss_trampoline;
91 /* Offset between fp and the first argument in the callee */
92 #define ARGS_OFFSET 16
93 #define GP_SCRATCH_REG AMD64_R11
96 * AMD64 register usage:
97 * - callee saved registers are used for global register allocation
98 * - %r11 is used for materializing 64 bit constants in opcodes
99 * - the rest is used for local allocation
103 * Floating point comparison results:
113 mono_arch_regname (int reg)
116 case AMD64_RAX: return "%rax";
117 case AMD64_RBX: return "%rbx";
118 case AMD64_RCX: return "%rcx";
119 case AMD64_RDX: return "%rdx";
120 case AMD64_RSP: return "%rsp";
121 case AMD64_RBP: return "%rbp";
122 case AMD64_RDI: return "%rdi";
123 case AMD64_RSI: return "%rsi";
124 case AMD64_R8: return "%r8";
125 case AMD64_R9: return "%r9";
126 case AMD64_R10: return "%r10";
127 case AMD64_R11: return "%r11";
128 case AMD64_R12: return "%r12";
129 case AMD64_R13: return "%r13";
130 case AMD64_R14: return "%r14";
131 case AMD64_R15: return "%r15";
136 static const char * packed_xmmregs [] = {
137 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
138 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
141 static const char * single_xmmregs [] = {
142 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
143 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
147 mono_arch_fregname (int reg)
149 if (reg < AMD64_XMM_NREG)
150 return single_xmmregs [reg];
156 mono_arch_xregname (int reg)
158 if (reg < AMD64_XMM_NREG)
159 return packed_xmmregs [reg];
168 return mono_debug_count ();
174 static inline gboolean
175 amd64_is_near_call (guint8 *code)
178 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
181 return code [0] == 0xe8;
184 #ifdef __native_client_codegen__
186 /* Keep track of instruction "depth", that is, the level of sub-instruction */
187 /* for any given instruction. For instance, amd64_call_reg resolves to */
188 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
189 /* We only want to force bundle alignment for the top level instruction, */
190 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
191 static MonoNativeTlsKey nacl_instruction_depth;
193 static MonoNativeTlsKey nacl_rex_tag;
194 static MonoNativeTlsKey nacl_legacy_prefix_tag;
197 amd64_nacl_clear_legacy_prefix_tag ()
199 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
203 amd64_nacl_tag_legacy_prefix (guint8* code)
205 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
206 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
210 amd64_nacl_tag_rex (guint8* code)
212 mono_native_tls_set_value (nacl_rex_tag, code);
216 amd64_nacl_get_legacy_prefix_tag ()
218 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
222 amd64_nacl_get_rex_tag ()
224 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
227 /* Increment the instruction "depth" described above */
229 amd64_nacl_instruction_pre ()
231 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
233 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
236 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
237 /* alignment if depth == 0 (top level instruction) */
238 /* IN: start, end pointers to instruction beginning and end */
239 /* OUT: start, end pointers to beginning and end after possible alignment */
240 /* GLOBALS: nacl_instruction_depth defined above */
242 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
244 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
246 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
248 g_assert ( depth >= 0 );
250 uintptr_t space_in_block;
252 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
253 /* if legacy prefix is present, and if it was emitted before */
254 /* the start of the instruction sequence, adjust the start */
255 if (prefix != NULL && prefix < *start) {
256 g_assert (*start - prefix <= 3);/* only 3 are allowed */
259 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
260 instlen = (uintptr_t)(*end - *start);
261 /* Only check for instructions which are less than */
262 /* kNaClAlignment. The only instructions that should ever */
263 /* be that long are call sequences, which are already */
264 /* padded out to align the return to the next bundle. */
265 if (instlen > space_in_block && instlen < kNaClAlignment) {
266 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
267 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
268 const size_t length = (size_t)((*end)-(*start));
269 g_assert (length < MAX_NACL_INST_LENGTH);
271 memcpy (copy_of_instruction, *start, length);
272 *start = mono_arch_nacl_pad (*start, space_in_block);
273 memcpy (*start, copy_of_instruction, length);
274 *end = *start + length;
276 amd64_nacl_clear_legacy_prefix_tag ();
277 amd64_nacl_tag_rex (NULL);
281 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
282 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
283 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
284 /* make sure the upper 32-bits are cleared, and use that register in the */
285 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
287 /* pointer to current instruction stream (in the */
288 /* middle of an instruction, after opcode is emitted) */
289 /* basereg/offset/dreg */
290 /* operands of normal membase address */
292 /* pointer to the end of the membase/memindex emit */
293 /* GLOBALS: nacl_rex_tag */
294 /* position in instruction stream that rex prefix was emitted */
295 /* nacl_legacy_prefix_tag */
296 /* (possibly NULL) position in instruction of legacy x86 prefix */
298 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
300 gint8 true_basereg = basereg;
302 /* Cache these values, they might change */
303 /* as new instructions are emitted below. */
304 guint8* rex_tag = amd64_nacl_get_rex_tag ();
305 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
307 /* 'basereg' is given masked to 0x7 at this point, so check */
308 /* the rex prefix to see if this is an extended register. */
309 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
313 #define X86_LEA_OPCODE (0x8D)
315 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
316 guint8* old_instruction_start;
318 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
319 /* 32-bits of the old base register (new index register) */
321 guint8* buf_ptr = buf;
324 g_assert (rex_tag != NULL);
326 if (IS_REX(*rex_tag)) {
327 /* The old rex.B should be the new rex.X */
328 if (*rex_tag & AMD64_REX_B) {
329 *rex_tag |= AMD64_REX_X;
331 /* Since our new base is %r15 set rex.B */
332 *rex_tag |= AMD64_REX_B;
334 /* Shift the instruction by one byte */
335 /* so we can insert a rex prefix */
336 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
338 /* New rex prefix only needs rex.B for %r15 base */
339 *rex_tag = AMD64_REX(AMD64_REX_B);
342 if (legacy_prefix_tag) {
343 old_instruction_start = legacy_prefix_tag;
345 old_instruction_start = rex_tag;
348 /* Clears the upper 32-bits of the previous base register */
349 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
350 insert_len = buf_ptr - buf;
352 /* Move the old instruction forward to make */
353 /* room for 'mov' stored in 'buf_ptr' */
354 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
356 memcpy (old_instruction_start, buf, insert_len);
358 /* Sandboxed replacement for the normal membase_emit */
359 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
362 /* Normal default behavior, emit membase memory location */
363 x86_membase_emit_body (*code, dreg, basereg, offset);
368 static inline unsigned char*
369 amd64_skip_nops (unsigned char* code)
374 if ( code[0] == 0x90) {
378 if ( code[0] == 0x66 && code[1] == 0x90) {
382 if (code[0] == 0x0f && code[1] == 0x1f
383 && code[2] == 0x00) {
387 if (code[0] == 0x0f && code[1] == 0x1f
388 && code[2] == 0x40 && code[3] == 0x00) {
392 if (code[0] == 0x0f && code[1] == 0x1f
393 && code[2] == 0x44 && code[3] == 0x00
394 && code[4] == 0x00) {
398 if (code[0] == 0x66 && code[1] == 0x0f
399 && code[2] == 0x1f && code[3] == 0x44
400 && code[4] == 0x00 && code[5] == 0x00) {
404 if (code[0] == 0x0f && code[1] == 0x1f
405 && code[2] == 0x80 && code[3] == 0x00
406 && code[4] == 0x00 && code[5] == 0x00
407 && code[6] == 0x00) {
411 if (code[0] == 0x0f && code[1] == 0x1f
412 && code[2] == 0x84 && code[3] == 0x00
413 && code[4] == 0x00 && code[5] == 0x00
414 && code[6] == 0x00 && code[7] == 0x00) {
423 mono_arch_nacl_skip_nops (guint8* code)
425 return amd64_skip_nops(code);
428 #endif /*__native_client_codegen__*/
431 amd64_patch (unsigned char* code, gpointer target)
435 #ifdef __native_client_codegen__
436 code = amd64_skip_nops (code);
438 #if defined(__native_client_codegen__) && defined(__native_client__)
439 if (nacl_is_code_address (code)) {
440 /* For tail calls, code is patched after being installed */
441 /* but not through the normal "patch callsite" method. */
442 unsigned char buf[kNaClAlignment];
443 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
445 memcpy (buf, aligned_code, kNaClAlignment);
446 /* Patch a temp buffer of bundle size, */
447 /* then install to actual location. */
448 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
449 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
453 target = nacl_modify_patch_target (target);
457 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
462 if ((code [0] & 0xf8) == 0xb8) {
463 /* amd64_set_reg_template */
464 *(guint64*)(code + 1) = (guint64)target;
466 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
467 /* mov 0(%rip), %dreg */
468 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
470 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
471 /* call *<OFFSET>(%rip) */
472 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
474 else if (code [0] == 0xe8) {
476 gint64 disp = (guint8*)target - (guint8*)code;
477 g_assert (amd64_is_imm32 (disp));
478 x86_patch (code, (unsigned char*)target);
481 x86_patch (code, (unsigned char*)target);
485 mono_amd64_patch (unsigned char* code, gpointer target)
487 amd64_patch (code, target);
496 ArgValuetypeAddrInIReg,
497 ArgNone /* only in pair_storage */
505 /* Only if storage == ArgValuetypeInReg */
506 ArgStorage pair_storage [2];
508 /* The size of each pair */
518 gboolean need_stack_align;
519 gboolean vtype_retaddr;
520 /* The index of the vret arg in the argument list */
527 #define DEBUG(a) if (cfg->verbose_level > 1) a
530 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
532 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
534 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
536 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
540 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
542 ainfo->offset = *stack_size;
544 if (*gr >= PARAM_REGS) {
545 ainfo->storage = ArgOnStack;
546 /* Since the same stack slot size is used for all arg */
547 /* types, it needs to be big enough to hold them all */
548 (*stack_size) += sizeof(mgreg_t);
551 ainfo->storage = ArgInIReg;
552 ainfo->reg = param_regs [*gr];
558 #define FLOAT_PARAM_REGS 4
560 #define FLOAT_PARAM_REGS 8
564 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
566 ainfo->offset = *stack_size;
568 if (*gr >= FLOAT_PARAM_REGS) {
569 ainfo->storage = ArgOnStack;
570 /* Since the same stack slot size is used for both float */
571 /* types, it needs to be big enough to hold them both */
572 (*stack_size) += sizeof(mgreg_t);
575 /* A double register */
577 ainfo->storage = ArgInDoubleSSEReg;
579 ainfo->storage = ArgInFloatSSEReg;
585 typedef enum ArgumentClass {
593 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
595 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
598 ptype = mini_type_get_underlying_type (gsctx, type);
599 switch (ptype->type) {
608 case MONO_TYPE_STRING:
609 case MONO_TYPE_OBJECT:
610 case MONO_TYPE_CLASS:
611 case MONO_TYPE_SZARRAY:
613 case MONO_TYPE_FNPTR:
614 case MONO_TYPE_ARRAY:
617 class2 = ARG_CLASS_INTEGER;
622 class2 = ARG_CLASS_INTEGER;
624 class2 = ARG_CLASS_SSE;
628 case MONO_TYPE_TYPEDBYREF:
629 g_assert_not_reached ();
631 case MONO_TYPE_GENERICINST:
632 if (!mono_type_generic_inst_is_valuetype (ptype)) {
633 class2 = ARG_CLASS_INTEGER;
637 case MONO_TYPE_VALUETYPE: {
638 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
641 for (i = 0; i < info->num_fields; ++i) {
643 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
648 g_assert_not_reached ();
652 if (class1 == class2)
654 else if (class1 == ARG_CLASS_NO_CLASS)
656 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
657 class1 = ARG_CLASS_MEMORY;
658 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
659 class1 = ARG_CLASS_INTEGER;
661 class1 = ARG_CLASS_SSE;
665 #ifdef __native_client_codegen__
667 /* Default alignment for Native Client is 32-byte. */
668 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
670 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
671 /* Check that alignment doesn't cross an alignment boundary. */
673 mono_arch_nacl_pad(guint8 *code, int pad)
675 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
677 if (pad == 0) return code;
678 /* assertion: alignment cannot cross a block boundary */
679 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
680 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
681 while (pad >= kMaxPadding) {
682 amd64_padding (code, kMaxPadding);
685 if (pad != 0) amd64_padding (code, pad);
691 count_fields_nested (MonoClass *klass)
693 MonoMarshalType *info;
696 info = mono_marshal_load_type_info (klass);
699 for (i = 0; i < info->num_fields; ++i) {
700 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
701 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
709 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
711 MonoMarshalType *info;
714 info = mono_marshal_load_type_info (klass);
716 for (i = 0; i < info->num_fields; ++i) {
717 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
718 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
720 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
721 fields [index].offset += offset;
729 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
731 guint32 *gr, guint32 *fr, guint32 *stack_size)
733 guint32 size, quad, nquads, i, nfields;
734 /* Keep track of the size used in each quad so we can */
735 /* use the right size when copying args/return vars. */
736 guint32 quadsize [2] = {8, 8};
737 ArgumentClass args [2];
738 MonoMarshalType *info = NULL;
739 MonoMarshalField *fields = NULL;
741 MonoGenericSharingContext tmp_gsctx;
742 gboolean pass_on_stack = FALSE;
745 * The gsctx currently contains no data, it is only used for checking whenever
746 * open types are allowed, some callers like mono_arch_get_argument_info ()
747 * don't pass it to us, so work around that.
752 klass = mono_class_from_mono_type (type);
753 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
755 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
756 /* We pass and return vtypes of size 8 in a register */
757 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
758 pass_on_stack = TRUE;
762 pass_on_stack = TRUE;
766 /* If this struct can't be split up naturally into 8-byte */
767 /* chunks (registers), pass it on the stack. */
768 if (sig->pinvoke && !pass_on_stack) {
772 info = mono_marshal_load_type_info (klass);
776 * Collect field information recursively to be able to
777 * handle nested structures.
779 nfields = count_fields_nested (klass);
780 fields = g_new0 (MonoMarshalField, nfields);
781 collect_field_info_nested (klass, fields, 0, 0);
783 for (i = 0; i < nfields; ++i) {
784 field_size = mono_marshal_type_size (fields [i].field->type,
786 &align, TRUE, klass->unicode);
787 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
788 pass_on_stack = TRUE;
795 /* Allways pass in memory */
796 ainfo->offset = *stack_size;
797 *stack_size += ALIGN_TO (size, 8);
798 ainfo->storage = ArgOnStack;
804 /* FIXME: Handle structs smaller than 8 bytes */
805 //if ((size % 8) != 0)
814 int n = mono_class_value_size (klass, NULL);
816 quadsize [0] = n >= 8 ? 8 : n;
817 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
819 /* Always pass in 1 or 2 integer registers */
820 args [0] = ARG_CLASS_INTEGER;
821 args [1] = ARG_CLASS_INTEGER;
822 /* Only the simplest cases are supported */
823 if (is_return && nquads != 1) {
824 args [0] = ARG_CLASS_MEMORY;
825 args [1] = ARG_CLASS_MEMORY;
829 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
830 * The X87 and SSEUP stuff is left out since there are no such types in
837 if (info->native_size > 16) {
838 ainfo->offset = *stack_size;
839 *stack_size += ALIGN_TO (info->native_size, 8);
840 ainfo->storage = ArgOnStack;
846 switch (info->native_size) {
847 case 1: case 2: case 4: case 8:
851 ainfo->storage = ArgOnStack;
852 ainfo->offset = *stack_size;
853 *stack_size += ALIGN_TO (info->native_size, 8);
856 ainfo->storage = ArgValuetypeAddrInIReg;
858 if (*gr < PARAM_REGS) {
859 ainfo->pair_storage [0] = ArgInIReg;
860 ainfo->pair_regs [0] = param_regs [*gr];
864 ainfo->pair_storage [0] = ArgOnStack;
865 ainfo->offset = *stack_size;
875 args [0] = ARG_CLASS_NO_CLASS;
876 args [1] = ARG_CLASS_NO_CLASS;
877 for (quad = 0; quad < nquads; ++quad) {
880 ArgumentClass class1;
883 class1 = ARG_CLASS_MEMORY;
885 class1 = ARG_CLASS_NO_CLASS;
886 for (i = 0; i < nfields; ++i) {
887 size = mono_marshal_type_size (fields [i].field->type,
889 &align, TRUE, klass->unicode);
890 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
891 /* Unaligned field */
895 /* Skip fields in other quad */
896 if ((quad == 0) && (fields [i].offset >= 8))
898 if ((quad == 1) && (fields [i].offset < 8))
901 /* How far into this quad this data extends.*/
902 /* (8 is size of quad) */
903 quadsize [quad] = fields [i].offset + size - (quad * 8);
905 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
907 g_assert (class1 != ARG_CLASS_NO_CLASS);
908 args [quad] = class1;
914 /* Post merger cleanup */
915 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
916 args [0] = args [1] = ARG_CLASS_MEMORY;
918 /* Allocate registers */
923 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
925 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
928 ainfo->storage = ArgValuetypeInReg;
929 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
930 g_assert (quadsize [0] <= 8);
931 g_assert (quadsize [1] <= 8);
932 ainfo->pair_size [0] = quadsize [0];
933 ainfo->pair_size [1] = quadsize [1];
934 ainfo->nregs = nquads;
935 for (quad = 0; quad < nquads; ++quad) {
936 switch (args [quad]) {
937 case ARG_CLASS_INTEGER:
938 if (*gr >= PARAM_REGS)
939 args [quad] = ARG_CLASS_MEMORY;
941 ainfo->pair_storage [quad] = ArgInIReg;
943 ainfo->pair_regs [quad] = return_regs [*gr];
945 ainfo->pair_regs [quad] = param_regs [*gr];
950 if (*fr >= FLOAT_PARAM_REGS)
951 args [quad] = ARG_CLASS_MEMORY;
953 if (quadsize[quad] <= 4)
954 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
955 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
956 ainfo->pair_regs [quad] = *fr;
960 case ARG_CLASS_MEMORY:
963 g_assert_not_reached ();
967 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
968 /* Revert possible register assignments */
972 ainfo->offset = *stack_size;
974 *stack_size += ALIGN_TO (info->native_size, 8);
976 *stack_size += nquads * sizeof(mgreg_t);
977 ainfo->storage = ArgOnStack;
985 * Obtain information about a call according to the calling convention.
986 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
987 * Draft Version 0.23" document for more information.
990 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
992 guint32 i, gr, fr, pstart;
994 int n = sig->hasthis + sig->param_count;
995 guint32 stack_size = 0;
997 gboolean is_pinvoke = sig->pinvoke;
1000 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1010 /* Reserve space where the callee can save the argument registers */
1011 stack_size = 4 * sizeof (mgreg_t);
1015 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016 switch (ret_type->type) {
1026 case MONO_TYPE_FNPTR:
1027 case MONO_TYPE_CLASS:
1028 case MONO_TYPE_OBJECT:
1029 case MONO_TYPE_SZARRAY:
1030 case MONO_TYPE_ARRAY:
1031 case MONO_TYPE_STRING:
1032 cinfo->ret.storage = ArgInIReg;
1033 cinfo->ret.reg = AMD64_RAX;
1037 cinfo->ret.storage = ArgInIReg;
1038 cinfo->ret.reg = AMD64_RAX;
1041 cinfo->ret.storage = ArgInFloatSSEReg;
1042 cinfo->ret.reg = AMD64_XMM0;
1045 cinfo->ret.storage = ArgInDoubleSSEReg;
1046 cinfo->ret.reg = AMD64_XMM0;
1048 case MONO_TYPE_GENERICINST:
1049 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1050 cinfo->ret.storage = ArgInIReg;
1051 cinfo->ret.reg = AMD64_RAX;
1055 #if defined( __native_client_codegen__ )
1056 case MONO_TYPE_TYPEDBYREF:
1058 case MONO_TYPE_VALUETYPE: {
1059 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1061 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1062 if (cinfo->ret.storage == ArgOnStack) {
1063 cinfo->vtype_retaddr = TRUE;
1064 /* The caller passes the address where the value is stored */
1068 #if !defined( __native_client_codegen__ )
1069 case MONO_TYPE_TYPEDBYREF:
1070 /* Same as a valuetype with size 24 */
1071 cinfo->vtype_retaddr = TRUE;
1074 case MONO_TYPE_VOID:
1077 g_error ("Can't handle as return value 0x%x", ret_type->type);
1082 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1083 * the first argument, allowing 'this' to be always passed in the first arg reg.
1084 * Also do this if the first argument is a reference type, since virtual calls
1085 * are sometimes made using calli without sig->hasthis set, like in the delegate
1088 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1090 add_general (&gr, &stack_size, cinfo->args + 0);
1092 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1095 add_general (&gr, &stack_size, &cinfo->ret);
1096 cinfo->vret_arg_index = 1;
1100 add_general (&gr, &stack_size, cinfo->args + 0);
1102 if (cinfo->vtype_retaddr)
1103 add_general (&gr, &stack_size, &cinfo->ret);
1106 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1108 fr = FLOAT_PARAM_REGS;
1110 /* Emit the signature cookie just before the implicit arguments */
1111 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1114 for (i = pstart; i < sig->param_count; ++i) {
1115 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119 /* The float param registers and other param registers must be the same index on Windows x64.*/
1126 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1127 /* We allways pass the sig cookie on the stack for simplicity */
1129 * Prevent implicit arguments + the sig cookie from being passed
1133 fr = FLOAT_PARAM_REGS;
1135 /* Emit the signature cookie just before the implicit arguments */
1136 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1139 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1140 switch (ptype->type) {
1143 add_general (&gr, &stack_size, ainfo);
1147 add_general (&gr, &stack_size, ainfo);
1151 add_general (&gr, &stack_size, ainfo);
1156 case MONO_TYPE_FNPTR:
1157 case MONO_TYPE_CLASS:
1158 case MONO_TYPE_OBJECT:
1159 case MONO_TYPE_STRING:
1160 case MONO_TYPE_SZARRAY:
1161 case MONO_TYPE_ARRAY:
1162 add_general (&gr, &stack_size, ainfo);
1164 case MONO_TYPE_GENERICINST:
1165 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1166 add_general (&gr, &stack_size, ainfo);
1170 case MONO_TYPE_VALUETYPE:
1171 case MONO_TYPE_TYPEDBYREF:
1172 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1177 add_general (&gr, &stack_size, ainfo);
1180 add_float (&fr, &stack_size, ainfo, FALSE);
1183 add_float (&fr, &stack_size, ainfo, TRUE);
1186 g_assert_not_reached ();
1190 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1192 fr = FLOAT_PARAM_REGS;
1194 /* Emit the signature cookie just before the implicit arguments */
1195 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1198 cinfo->stack_usage = stack_size;
1199 cinfo->reg_usage = gr;
1200 cinfo->freg_usage = fr;
1205 * mono_arch_get_argument_info:
1206 * @csig: a method signature
1207 * @param_count: the number of parameters to consider
1208 * @arg_info: an array to store the result infos
1210 * Gathers information on parameters such as size, alignment and
1211 * padding. arg_info should be large enought to hold param_count + 1 entries.
1213 * Returns the size of the argument area on the stack.
1216 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1219 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1220 guint32 args_size = cinfo->stack_usage;
1222 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1223 if (csig->hasthis) {
1224 arg_info [0].offset = 0;
1227 for (k = 0; k < param_count; k++) {
1228 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1230 arg_info [k + 1].size = 0;
1239 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1243 MonoType *callee_ret;
1245 c1 = get_call_info (NULL, NULL, caller_sig);
1246 c2 = get_call_info (NULL, NULL, callee_sig);
1247 res = c1->stack_usage >= c2->stack_usage;
1248 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1249 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1250 /* An address on the callee's stack is passed as the first argument */
1260 * Initialize the cpu to execute managed code.
1263 mono_arch_cpu_init (void)
1268 /* spec compliance requires running with double precision */
1269 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1270 fpcw &= ~X86_FPCW_PRECC_MASK;
1271 fpcw |= X86_FPCW_PREC_DOUBLE;
1272 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1273 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 /* TODO: This is crashing on Win64 right now.
1276 * _control87 (_PC_53, MCW_PC);
1282 * Initialize architecture specific code.
1285 mono_arch_init (void)
1289 mono_mutex_init_recursive (&mini_arch_mutex);
1290 #if defined(__native_client_codegen__)
1291 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1292 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1293 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1294 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1297 #ifdef MONO_ARCH_NOMAP32BIT
1298 flags = MONO_MMAP_READ;
1299 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1300 breakpoint_size = 13;
1301 breakpoint_fault_size = 3;
1303 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1304 /* amd64_mov_reg_mem () */
1305 breakpoint_size = 8;
1306 breakpoint_fault_size = 8;
1309 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1310 single_step_fault_size = 4;
1312 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1313 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1316 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1317 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1318 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1322 * Cleanup architecture specific code.
1325 mono_arch_cleanup (void)
1327 mono_mutex_destroy (&mini_arch_mutex);
1328 #if defined(__native_client_codegen__)
1329 mono_native_tls_free (nacl_instruction_depth);
1330 mono_native_tls_free (nacl_rex_tag);
1331 mono_native_tls_free (nacl_legacy_prefix_tag);
1336 * This function returns the optimizations supported on this cpu.
1339 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 if (mono_hwcap_x86_has_cmov) {
1346 opts |= MONO_OPT_CMOV;
1348 if (mono_hwcap_x86_has_fcmov)
1349 opts |= MONO_OPT_FCMOV;
1351 *exclude_mask |= MONO_OPT_FCMOV;
1353 *exclude_mask |= MONO_OPT_CMOV;
1360 * This function test for all SSE functions supported.
1362 * Returns a bitmask corresponding to all supported versions.
1366 mono_arch_cpu_enumerate_simd_versions (void)
1368 guint32 sse_opts = 0;
1370 if (mono_hwcap_x86_has_sse1)
1371 sse_opts |= SIMD_VERSION_SSE1;
1373 if (mono_hwcap_x86_has_sse2)
1374 sse_opts |= SIMD_VERSION_SSE2;
1376 if (mono_hwcap_x86_has_sse3)
1377 sse_opts |= SIMD_VERSION_SSE3;
1379 if (mono_hwcap_x86_has_ssse3)
1380 sse_opts |= SIMD_VERSION_SSSE3;
1382 if (mono_hwcap_x86_has_sse41)
1383 sse_opts |= SIMD_VERSION_SSE41;
1385 if (mono_hwcap_x86_has_sse42)
1386 sse_opts |= SIMD_VERSION_SSE42;
1388 if (mono_hwcap_x86_has_sse4a)
1389 sse_opts |= SIMD_VERSION_SSE4a;
1397 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1402 for (i = 0; i < cfg->num_varinfo; i++) {
1403 MonoInst *ins = cfg->varinfo [i];
1404 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1407 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1410 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1411 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1414 if (mono_is_regsize_var (ins->inst_vtype)) {
1415 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1416 g_assert (i == vmv->idx);
1417 vars = g_list_prepend (vars, vmv);
1421 vars = mono_varlist_sort (cfg, vars, 0);
1427 * mono_arch_compute_omit_fp:
1429 * Determine whenever the frame pointer can be eliminated.
1432 mono_arch_compute_omit_fp (MonoCompile *cfg)
1434 MonoMethodSignature *sig;
1435 MonoMethodHeader *header;
1439 if (cfg->arch.omit_fp_computed)
1442 header = cfg->header;
1444 sig = mono_method_signature (cfg->method);
1446 if (!cfg->arch.cinfo)
1447 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1448 cinfo = cfg->arch.cinfo;
1451 * FIXME: Remove some of the restrictions.
1453 cfg->arch.omit_fp = TRUE;
1454 cfg->arch.omit_fp_computed = TRUE;
1456 #ifdef __native_client_codegen__
1457 /* NaCl modules may not change the value of RBP, so it cannot be */
1458 /* used as a normal register, but it can be used as a frame pointer*/
1459 cfg->disable_omit_fp = TRUE;
1460 cfg->arch.omit_fp = FALSE;
1463 if (cfg->disable_omit_fp)
1464 cfg->arch.omit_fp = FALSE;
1466 if (!debug_omit_fp ())
1467 cfg->arch.omit_fp = FALSE;
1469 if (cfg->method->save_lmf)
1470 cfg->arch.omit_fp = FALSE;
1472 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1473 cfg->arch.omit_fp = FALSE;
1474 if (header->num_clauses)
1475 cfg->arch.omit_fp = FALSE;
1476 if (cfg->param_area)
1477 cfg->arch.omit_fp = FALSE;
1478 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1479 cfg->arch.omit_fp = FALSE;
1480 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1481 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1482 cfg->arch.omit_fp = FALSE;
1483 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1484 ArgInfo *ainfo = &cinfo->args [i];
1486 if (ainfo->storage == ArgOnStack) {
1488 * The stack offset can only be determined when the frame
1491 cfg->arch.omit_fp = FALSE;
1496 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1497 MonoInst *ins = cfg->varinfo [i];
1500 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1505 mono_arch_get_global_int_regs (MonoCompile *cfg)
1509 mono_arch_compute_omit_fp (cfg);
1511 if (cfg->globalra) {
1512 if (cfg->arch.omit_fp)
1513 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1515 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1516 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1517 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1518 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1519 #ifndef __native_client_codegen__
1520 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1523 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1524 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1526 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1527 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1528 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1529 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1530 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1532 if (cfg->arch.omit_fp)
1533 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1535 /* We use the callee saved registers for global allocation */
1536 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1537 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1538 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1539 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1540 #ifndef __native_client_codegen__
1541 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1544 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1545 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1553 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1558 /* All XMM registers */
1559 for (i = 0; i < 16; ++i)
1560 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1568 static GList *r = NULL;
1573 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1574 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1575 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1576 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1577 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1578 #ifndef __native_client_codegen__
1579 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1582 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1583 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1584 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1585 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1586 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1587 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1588 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1589 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1591 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1598 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1601 static GList *r = NULL;
1606 for (i = 0; i < AMD64_XMM_NREG; ++i)
1607 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1609 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1616 * mono_arch_regalloc_cost:
1618 * Return the cost, in number of memory references, of the action of
1619 * allocating the variable VMV into a register during global register
1623 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1625 MonoInst *ins = cfg->varinfo [vmv->idx];
1627 if (cfg->method->save_lmf)
1628 /* The register is already saved */
1629 /* substract 1 for the invisible store in the prolog */
1630 return (ins->opcode == OP_ARG) ? 0 : 1;
1633 return (ins->opcode == OP_ARG) ? 1 : 2;
1637 * mono_arch_fill_argument_info:
1639 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1643 mono_arch_fill_argument_info (MonoCompile *cfg)
1646 MonoMethodSignature *sig;
1651 sig = mono_method_signature (cfg->method);
1653 cinfo = cfg->arch.cinfo;
1654 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1657 * Contrary to mono_arch_allocate_vars (), the information should describe
1658 * where the arguments are at the beginning of the method, not where they can be
1659 * accessed during the execution of the method. The later makes no sense for the
1660 * global register allocator, since a variable can be in more than one location.
1662 if (sig_ret->type != MONO_TYPE_VOID) {
1663 switch (cinfo->ret.storage) {
1665 case ArgInFloatSSEReg:
1666 case ArgInDoubleSSEReg:
1667 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1668 cfg->vret_addr->opcode = OP_REGVAR;
1669 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1672 cfg->ret->opcode = OP_REGVAR;
1673 cfg->ret->inst_c0 = cinfo->ret.reg;
1676 case ArgValuetypeInReg:
1677 cfg->ret->opcode = OP_REGOFFSET;
1678 cfg->ret->inst_basereg = -1;
1679 cfg->ret->inst_offset = -1;
1682 g_assert_not_reached ();
1686 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1687 ArgInfo *ainfo = &cinfo->args [i];
1689 ins = cfg->args [i];
1691 switch (ainfo->storage) {
1693 case ArgInFloatSSEReg:
1694 case ArgInDoubleSSEReg:
1695 ins->opcode = OP_REGVAR;
1696 ins->inst_c0 = ainfo->reg;
1699 ins->opcode = OP_REGOFFSET;
1700 ins->inst_basereg = -1;
1701 ins->inst_offset = -1;
1703 case ArgValuetypeInReg:
1705 ins->opcode = OP_NOP;
1708 g_assert_not_reached ();
1714 mono_arch_allocate_vars (MonoCompile *cfg)
1717 MonoMethodSignature *sig;
1720 guint32 locals_stack_size, locals_stack_align;
1724 sig = mono_method_signature (cfg->method);
1726 cinfo = cfg->arch.cinfo;
1727 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1729 mono_arch_compute_omit_fp (cfg);
1732 * We use the ABI calling conventions for managed code as well.
1733 * Exception: valuetypes are only sometimes passed or returned in registers.
1737 * The stack looks like this:
1738 * <incoming arguments passed on the stack>
1740 * <lmf/caller saved registers>
1743 * <localloc area> -> grows dynamically
1747 if (cfg->arch.omit_fp) {
1748 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1749 cfg->frame_reg = AMD64_RSP;
1752 /* Locals are allocated backwards from %fp */
1753 cfg->frame_reg = AMD64_RBP;
1757 cfg->arch.saved_iregs = cfg->used_int_regs;
1758 if (cfg->method->save_lmf)
1759 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1760 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1762 if (cfg->arch.omit_fp)
1763 cfg->arch.reg_save_area_offset = offset;
1764 /* Reserve space for callee saved registers */
1765 for (i = 0; i < AMD64_NREG; ++i)
1766 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1767 offset += sizeof(mgreg_t);
1769 if (!cfg->arch.omit_fp)
1770 cfg->arch.reg_save_area_offset = -offset;
1772 if (sig_ret->type != MONO_TYPE_VOID) {
1773 switch (cinfo->ret.storage) {
1775 case ArgInFloatSSEReg:
1776 case ArgInDoubleSSEReg:
1777 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1778 if (cfg->globalra) {
1779 cfg->vret_addr->opcode = OP_REGVAR;
1780 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1782 /* The register is volatile */
1783 cfg->vret_addr->opcode = OP_REGOFFSET;
1784 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1785 if (cfg->arch.omit_fp) {
1786 cfg->vret_addr->inst_offset = offset;
1790 cfg->vret_addr->inst_offset = -offset;
1792 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1793 printf ("vret_addr =");
1794 mono_print_ins (cfg->vret_addr);
1799 cfg->ret->opcode = OP_REGVAR;
1800 cfg->ret->inst_c0 = cinfo->ret.reg;
1803 case ArgValuetypeInReg:
1804 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1805 cfg->ret->opcode = OP_REGOFFSET;
1806 cfg->ret->inst_basereg = cfg->frame_reg;
1807 if (cfg->arch.omit_fp) {
1808 cfg->ret->inst_offset = offset;
1809 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1811 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1812 cfg->ret->inst_offset = - offset;
1816 g_assert_not_reached ();
1819 cfg->ret->dreg = cfg->ret->inst_c0;
1822 /* Allocate locals */
1823 if (!cfg->globalra) {
1824 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1825 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1826 char *mname = mono_method_full_name (cfg->method, TRUE);
1827 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1828 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1833 if (locals_stack_align) {
1834 offset += (locals_stack_align - 1);
1835 offset &= ~(locals_stack_align - 1);
1837 if (cfg->arch.omit_fp) {
1838 cfg->locals_min_stack_offset = offset;
1839 cfg->locals_max_stack_offset = offset + locals_stack_size;
1841 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1842 cfg->locals_max_stack_offset = - offset;
1845 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1846 if (offsets [i] != -1) {
1847 MonoInst *ins = cfg->varinfo [i];
1848 ins->opcode = OP_REGOFFSET;
1849 ins->inst_basereg = cfg->frame_reg;
1850 if (cfg->arch.omit_fp)
1851 ins->inst_offset = (offset + offsets [i]);
1853 ins->inst_offset = - (offset + offsets [i]);
1854 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1857 offset += locals_stack_size;
1860 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1861 g_assert (!cfg->arch.omit_fp);
1862 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1863 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1866 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1867 ins = cfg->args [i];
1868 if (ins->opcode != OP_REGVAR) {
1869 ArgInfo *ainfo = &cinfo->args [i];
1870 gboolean inreg = TRUE;
1872 if (cfg->globalra) {
1873 /* The new allocator needs info about the original locations of the arguments */
1874 switch (ainfo->storage) {
1876 case ArgInFloatSSEReg:
1877 case ArgInDoubleSSEReg:
1878 ins->opcode = OP_REGVAR;
1879 ins->inst_c0 = ainfo->reg;
1882 g_assert (!cfg->arch.omit_fp);
1883 ins->opcode = OP_REGOFFSET;
1884 ins->inst_basereg = cfg->frame_reg;
1885 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1887 case ArgValuetypeInReg:
1888 ins->opcode = OP_REGOFFSET;
1889 ins->inst_basereg = cfg->frame_reg;
1890 /* These arguments are saved to the stack in the prolog */
1891 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1892 if (cfg->arch.omit_fp) {
1893 ins->inst_offset = offset;
1894 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1896 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1897 ins->inst_offset = - offset;
1901 g_assert_not_reached ();
1907 /* FIXME: Allocate volatile arguments to registers */
1908 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1912 * Under AMD64, all registers used to pass arguments to functions
1913 * are volatile across calls.
1914 * FIXME: Optimize this.
1916 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1919 ins->opcode = OP_REGOFFSET;
1921 switch (ainfo->storage) {
1923 case ArgInFloatSSEReg:
1924 case ArgInDoubleSSEReg:
1926 ins->opcode = OP_REGVAR;
1927 ins->dreg = ainfo->reg;
1931 g_assert (!cfg->arch.omit_fp);
1932 ins->opcode = OP_REGOFFSET;
1933 ins->inst_basereg = cfg->frame_reg;
1934 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1936 case ArgValuetypeInReg:
1938 case ArgValuetypeAddrInIReg: {
1940 g_assert (!cfg->arch.omit_fp);
1942 MONO_INST_NEW (cfg, indir, 0);
1943 indir->opcode = OP_REGOFFSET;
1944 if (ainfo->pair_storage [0] == ArgInIReg) {
1945 indir->inst_basereg = cfg->frame_reg;
1946 offset = ALIGN_TO (offset, sizeof (gpointer));
1947 offset += (sizeof (gpointer));
1948 indir->inst_offset = - offset;
1951 indir->inst_basereg = cfg->frame_reg;
1952 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1955 ins->opcode = OP_VTARG_ADDR;
1956 ins->inst_left = indir;
1964 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1965 ins->opcode = OP_REGOFFSET;
1966 ins->inst_basereg = cfg->frame_reg;
1967 /* These arguments are saved to the stack in the prolog */
1968 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1969 if (cfg->arch.omit_fp) {
1970 ins->inst_offset = offset;
1971 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1972 // Arguments are yet supported by the stack map creation code
1973 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1975 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1976 ins->inst_offset = - offset;
1977 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1983 cfg->stack_offset = offset;
1987 mono_arch_create_vars (MonoCompile *cfg)
1989 MonoMethodSignature *sig;
1993 sig = mono_method_signature (cfg->method);
1995 if (!cfg->arch.cinfo)
1996 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1997 cinfo = cfg->arch.cinfo;
1999 if (cinfo->ret.storage == ArgValuetypeInReg)
2000 cfg->ret_var_is_local = TRUE;
2002 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2003 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2004 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2005 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2006 printf ("vret_addr = ");
2007 mono_print_ins (cfg->vret_addr);
2011 if (cfg->gen_seq_points_debug_data) {
2014 if (cfg->compile_aot) {
2015 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2016 ins->flags |= MONO_INST_VOLATILE;
2017 cfg->arch.seq_point_info_var = ins;
2019 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2020 ins->flags |= MONO_INST_VOLATILE;
2021 cfg->arch.ss_tramp_var = ins;
2024 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2025 ins->flags |= MONO_INST_VOLATILE;
2026 cfg->arch.ss_trigger_page_var = ins;
2029 if (cfg->method->save_lmf)
2030 cfg->create_lmf_var = TRUE;
2032 if (cfg->method->save_lmf) {
2034 #if !defined(TARGET_WIN32)
2035 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2036 cfg->lmf_ir_mono_lmf = TRUE;
2042 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2048 MONO_INST_NEW (cfg, ins, OP_MOVE);
2049 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2050 ins->sreg1 = tree->dreg;
2051 MONO_ADD_INS (cfg->cbb, ins);
2052 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2054 case ArgInFloatSSEReg:
2055 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2056 ins->dreg = mono_alloc_freg (cfg);
2057 ins->sreg1 = tree->dreg;
2058 MONO_ADD_INS (cfg->cbb, ins);
2060 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062 case ArgInDoubleSSEReg:
2063 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2064 ins->dreg = mono_alloc_freg (cfg);
2065 ins->sreg1 = tree->dreg;
2066 MONO_ADD_INS (cfg->cbb, ins);
2068 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2072 g_assert_not_reached ();
2077 arg_storage_to_load_membase (ArgStorage storage)
2081 #if defined(__mono_ilp32__)
2082 return OP_LOADI8_MEMBASE;
2084 return OP_LOAD_MEMBASE;
2086 case ArgInDoubleSSEReg:
2087 return OP_LOADR8_MEMBASE;
2088 case ArgInFloatSSEReg:
2089 return OP_LOADR4_MEMBASE;
2091 g_assert_not_reached ();
2098 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2100 MonoMethodSignature *tmp_sig;
2103 if (call->tail_call)
2106 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2109 * mono_ArgIterator_Setup assumes the signature cookie is
2110 * passed first and all the arguments which were before it are
2111 * passed on the stack after the signature. So compensate by
2112 * passing a different signature.
2114 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2115 tmp_sig->param_count -= call->signature->sentinelpos;
2116 tmp_sig->sentinelpos = 0;
2117 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2119 sig_reg = mono_alloc_ireg (cfg);
2120 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2122 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2126 static inline LLVMArgStorage
2127 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2131 return LLVMArgInIReg;
2135 g_assert_not_reached ();
2141 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2147 LLVMCallInfo *linfo;
2148 MonoType *t, *sig_ret;
2150 n = sig->param_count + sig->hasthis;
2151 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2153 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2155 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2158 * LLVM always uses the native ABI while we use our own ABI, the
2159 * only difference is the handling of vtypes:
2160 * - we only pass/receive them in registers in some cases, and only
2161 * in 1 or 2 integer registers.
2163 if (cinfo->ret.storage == ArgValuetypeInReg) {
2165 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2166 cfg->disable_llvm = TRUE;
2170 linfo->ret.storage = LLVMArgVtypeInReg;
2171 for (j = 0; j < 2; ++j)
2172 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2175 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2176 /* Vtype returned using a hidden argument */
2177 linfo->ret.storage = LLVMArgVtypeRetAddr;
2178 linfo->vret_arg_index = cinfo->vret_arg_index;
2181 for (i = 0; i < n; ++i) {
2182 ainfo = cinfo->args + i;
2184 if (i >= sig->hasthis)
2185 t = sig->params [i - sig->hasthis];
2187 t = &mono_defaults.int_class->byval_arg;
2189 linfo->args [i].storage = LLVMArgNone;
2191 switch (ainfo->storage) {
2193 linfo->args [i].storage = LLVMArgInIReg;
2195 case ArgInDoubleSSEReg:
2196 case ArgInFloatSSEReg:
2197 linfo->args [i].storage = LLVMArgInFPReg;
2200 if (MONO_TYPE_ISSTRUCT (t)) {
2201 linfo->args [i].storage = LLVMArgVtypeByVal;
2203 linfo->args [i].storage = LLVMArgInIReg;
2205 if (t->type == MONO_TYPE_R4)
2206 linfo->args [i].storage = LLVMArgInFPReg;
2207 else if (t->type == MONO_TYPE_R8)
2208 linfo->args [i].storage = LLVMArgInFPReg;
2212 case ArgValuetypeInReg:
2214 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2215 cfg->disable_llvm = TRUE;
2219 linfo->args [i].storage = LLVMArgVtypeInReg;
2220 for (j = 0; j < 2; ++j)
2221 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2224 cfg->exception_message = g_strdup ("ainfo->storage");
2225 cfg->disable_llvm = TRUE;
2235 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2238 MonoMethodSignature *sig;
2244 sig = call->signature;
2245 n = sig->param_count + sig->hasthis;
2247 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2251 if (COMPILE_LLVM (cfg)) {
2252 /* We shouldn't be called in the llvm case */
2253 cfg->disable_llvm = TRUE;
2258 * Emit all arguments which are passed on the stack to prevent register
2259 * allocation problems.
2261 for (i = 0; i < n; ++i) {
2263 ainfo = cinfo->args + i;
2265 in = call->args [i];
2267 if (sig->hasthis && i == 0)
2268 t = &mono_defaults.object_class->byval_arg;
2270 t = sig->params [i - sig->hasthis];
2272 t = mini_get_underlying_type (cfg, t);
2273 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2275 if (t->type == MONO_TYPE_R4)
2276 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2277 else if (t->type == MONO_TYPE_R8)
2278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2280 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2282 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2284 if (cfg->compute_gc_maps) {
2287 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2293 * Emit all parameters passed in registers in non-reverse order for better readability
2294 * and to help the optimization in emit_prolog ().
2296 for (i = 0; i < n; ++i) {
2297 ainfo = cinfo->args + i;
2299 in = call->args [i];
2301 if (ainfo->storage == ArgInIReg)
2302 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2305 for (i = n - 1; i >= 0; --i) {
2306 ainfo = cinfo->args + i;
2308 in = call->args [i];
2310 switch (ainfo->storage) {
2314 case ArgInFloatSSEReg:
2315 case ArgInDoubleSSEReg:
2316 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2319 case ArgValuetypeInReg:
2320 case ArgValuetypeAddrInIReg:
2321 if (ainfo->storage == ArgOnStack && call->tail_call) {
2322 MonoInst *call_inst = (MonoInst*)call;
2323 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2324 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2325 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2329 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2330 size = sizeof (MonoTypedRef);
2331 align = sizeof (gpointer);
2335 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2338 * Other backends use mono_type_stack_size (), but that
2339 * aligns the size to 8, which is larger than the size of
2340 * the source, leading to reads of invalid memory if the
2341 * source is at the end of address space.
2343 size = mono_class_value_size (in->klass, &align);
2346 g_assert (in->klass);
2348 if (ainfo->storage == ArgOnStack && size >= 10000) {
2349 /* Avoid asserts in emit_memcpy () */
2350 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2351 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2352 /* Continue normally */
2356 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2357 arg->sreg1 = in->dreg;
2358 arg->klass = in->klass;
2359 arg->backend.size = size;
2360 arg->inst_p0 = call;
2361 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2362 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2364 MONO_ADD_INS (cfg->cbb, arg);
2369 g_assert_not_reached ();
2372 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2373 /* Emit the signature cookie just before the implicit arguments */
2374 emit_sig_cookie (cfg, call, cinfo);
2377 /* Handle the case where there are no implicit arguments */
2378 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2379 emit_sig_cookie (cfg, call, cinfo);
2381 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2382 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2385 if (cinfo->ret.storage == ArgValuetypeInReg) {
2386 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2388 * Tell the JIT to use a more efficient calling convention: call using
2389 * OP_CALL, compute the result location after the call, and save the
2392 call->vret_in_reg = TRUE;
2394 * Nullify the instruction computing the vret addr to enable
2395 * future optimizations.
2398 NULLIFY_INS (call->vret_var);
2400 if (call->tail_call)
2403 * The valuetype is in RAX:RDX after the call, need to be copied to
2404 * the stack. Push the address here, so the call instruction can
2407 if (!cfg->arch.vret_addr_loc) {
2408 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2409 /* Prevent it from being register allocated or optimized away */
2410 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2413 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2417 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2418 vtarg->sreg1 = call->vret_var->dreg;
2419 vtarg->dreg = mono_alloc_preg (cfg);
2420 MONO_ADD_INS (cfg->cbb, vtarg);
2422 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2426 if (cfg->method->save_lmf) {
2427 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2428 MONO_ADD_INS (cfg->cbb, arg);
2431 call->stack_usage = cinfo->stack_usage;
2435 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2438 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2439 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2440 int size = ins->backend.size;
2442 if (ainfo->storage == ArgValuetypeInReg) {
2446 for (part = 0; part < 2; ++part) {
2447 if (ainfo->pair_storage [part] == ArgNone)
2450 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2451 load->inst_basereg = src->dreg;
2452 load->inst_offset = part * sizeof(mgreg_t);
2454 switch (ainfo->pair_storage [part]) {
2456 load->dreg = mono_alloc_ireg (cfg);
2458 case ArgInDoubleSSEReg:
2459 case ArgInFloatSSEReg:
2460 load->dreg = mono_alloc_freg (cfg);
2463 g_assert_not_reached ();
2465 MONO_ADD_INS (cfg->cbb, load);
2467 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2469 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2470 MonoInst *vtaddr, *load;
2471 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2473 MONO_INST_NEW (cfg, load, OP_LDADDR);
2474 cfg->has_indirection = TRUE;
2475 load->inst_p0 = vtaddr;
2476 vtaddr->flags |= MONO_INST_INDIRECT;
2477 load->type = STACK_MP;
2478 load->klass = vtaddr->klass;
2479 load->dreg = mono_alloc_ireg (cfg);
2480 MONO_ADD_INS (cfg->cbb, load);
2481 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2483 if (ainfo->pair_storage [0] == ArgInIReg) {
2484 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2485 arg->dreg = mono_alloc_ireg (cfg);
2486 arg->sreg1 = load->dreg;
2488 MONO_ADD_INS (cfg->cbb, arg);
2489 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2491 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2495 int dreg = mono_alloc_ireg (cfg);
2497 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2498 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2499 } else if (size <= 40) {
2500 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2502 // FIXME: Code growth
2503 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2506 if (cfg->compute_gc_maps) {
2508 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2514 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2516 MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2518 if (ret->type == MONO_TYPE_R4) {
2519 if (COMPILE_LLVM (cfg))
2520 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2522 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2524 } else if (ret->type == MONO_TYPE_R8) {
2525 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2529 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2532 #endif /* DISABLE_JIT */
2534 #define EMIT_COND_BRANCH(ins,cond,sign) \
2535 if (ins->inst_true_bb->native_offset) { \
2536 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2538 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2539 if ((cfg->opt & MONO_OPT_BRANCH) && \
2540 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2541 x86_branch8 (code, cond, 0, sign); \
2543 x86_branch32 (code, cond, 0, sign); \
2547 MonoMethodSignature *sig;
2552 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2560 switch (cinfo->ret.storage) {
2564 case ArgValuetypeInReg: {
2565 ArgInfo *ainfo = &cinfo->ret;
2567 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2569 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2577 for (i = 0; i < cinfo->nargs; ++i) {
2578 ArgInfo *ainfo = &cinfo->args [i];
2579 switch (ainfo->storage) {
2582 case ArgValuetypeInReg:
2583 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2585 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2597 * mono_arch_dyn_call_prepare:
2599 * Return a pointer to an arch-specific structure which contains information
2600 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2601 * supported for SIG.
2602 * This function is equivalent to ffi_prep_cif in libffi.
2605 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2607 ArchDynCallInfo *info;
2610 cinfo = get_call_info (NULL, NULL, sig);
2612 if (!dyn_call_supported (sig, cinfo)) {
2617 info = g_new0 (ArchDynCallInfo, 1);
2618 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2620 info->cinfo = cinfo;
2622 return (MonoDynCallInfo*)info;
2626 * mono_arch_dyn_call_free:
2628 * Free a MonoDynCallInfo structure.
2631 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2633 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2635 g_free (ainfo->cinfo);
2639 #if !defined(__native_client__)
2640 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2641 #define GREG_TO_PTR(greg) (gpointer)(greg)
2643 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2644 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2645 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2649 * mono_arch_get_start_dyn_call:
2651 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2652 * store the result into BUF.
2653 * ARGS should be an array of pointers pointing to the arguments.
2654 * RET should point to a memory buffer large enought to hold the result of the
2656 * This function should be as fast as possible, any work which does not depend
2657 * on the actual values of the arguments should be done in
2658 * mono_arch_dyn_call_prepare ().
2659 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2663 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2665 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2666 DynCallArgs *p = (DynCallArgs*)buf;
2667 int arg_index, greg, i, pindex;
2668 MonoMethodSignature *sig = dinfo->sig;
2670 g_assert (buf_len >= sizeof (DynCallArgs));
2679 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2680 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2685 if (dinfo->cinfo->vtype_retaddr)
2686 p->regs [greg ++] = PTR_TO_GREG(ret);
2688 for (i = pindex; i < sig->param_count; i++) {
2689 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2690 gpointer *arg = args [arg_index ++];
2693 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2698 case MONO_TYPE_STRING:
2699 case MONO_TYPE_CLASS:
2700 case MONO_TYPE_ARRAY:
2701 case MONO_TYPE_SZARRAY:
2702 case MONO_TYPE_OBJECT:
2706 #if !defined(__mono_ilp32__)
2710 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2711 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2713 #if defined(__mono_ilp32__)
2716 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2717 p->regs [greg ++] = *(guint64*)(arg);
2721 p->regs [greg ++] = *(guint8*)(arg);
2724 p->regs [greg ++] = *(gint8*)(arg);
2727 p->regs [greg ++] = *(gint16*)(arg);
2730 p->regs [greg ++] = *(guint16*)(arg);
2733 p->regs [greg ++] = *(gint32*)(arg);
2736 p->regs [greg ++] = *(guint32*)(arg);
2738 case MONO_TYPE_GENERICINST:
2739 if (MONO_TYPE_IS_REFERENCE (t)) {
2740 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2745 case MONO_TYPE_VALUETYPE: {
2746 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2748 g_assert (ainfo->storage == ArgValuetypeInReg);
2749 if (ainfo->pair_storage [0] != ArgNone) {
2750 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2751 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2753 if (ainfo->pair_storage [1] != ArgNone) {
2754 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2755 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2760 g_assert_not_reached ();
2764 g_assert (greg <= PARAM_REGS);
2768 * mono_arch_finish_dyn_call:
2770 * Store the result of a dyn call into the return value buffer passed to
2771 * start_dyn_call ().
2772 * This function should be as fast as possible, any work which does not depend
2773 * on the actual values of the arguments should be done in
2774 * mono_arch_dyn_call_prepare ().
2777 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2779 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2780 MonoMethodSignature *sig = dinfo->sig;
2781 guint8 *ret = ((DynCallArgs*)buf)->ret;
2782 mgreg_t res = ((DynCallArgs*)buf)->res;
2783 MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2785 switch (sig_ret->type) {
2786 case MONO_TYPE_VOID:
2787 *(gpointer*)ret = NULL;
2789 case MONO_TYPE_STRING:
2790 case MONO_TYPE_CLASS:
2791 case MONO_TYPE_ARRAY:
2792 case MONO_TYPE_SZARRAY:
2793 case MONO_TYPE_OBJECT:
2797 *(gpointer*)ret = GREG_TO_PTR(res);
2803 *(guint8*)ret = res;
2806 *(gint16*)ret = res;
2809 *(guint16*)ret = res;
2812 *(gint32*)ret = res;
2815 *(guint32*)ret = res;
2818 *(gint64*)ret = res;
2821 *(guint64*)ret = res;
2823 case MONO_TYPE_GENERICINST:
2824 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2825 *(gpointer*)ret = GREG_TO_PTR(res);
2830 case MONO_TYPE_VALUETYPE:
2831 if (dinfo->cinfo->vtype_retaddr) {
2834 ArgInfo *ainfo = &dinfo->cinfo->ret;
2836 g_assert (ainfo->storage == ArgValuetypeInReg);
2838 if (ainfo->pair_storage [0] != ArgNone) {
2839 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2840 ((mgreg_t*)ret)[0] = res;
2843 g_assert (ainfo->pair_storage [1] == ArgNone);
2847 g_assert_not_reached ();
2851 /* emit an exception if condition is fail */
2852 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2854 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2855 if (tins == NULL) { \
2856 mono_add_patch_info (cfg, code - cfg->native_code, \
2857 MONO_PATCH_INFO_EXC, exc_name); \
2858 x86_branch32 (code, cond, 0, signed); \
2860 EMIT_COND_BRANCH (tins, cond, signed); \
2864 #define EMIT_FPCOMPARE(code) do { \
2865 amd64_fcompp (code); \
2866 amd64_fnstsw (code); \
2869 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2870 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2871 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2872 amd64_ ##op (code); \
2873 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2874 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2878 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2880 gboolean no_patch = FALSE;
2883 * FIXME: Add support for thunks
2886 gboolean near_call = FALSE;
2889 * Indirect calls are expensive so try to make a near call if possible.
2890 * The caller memory is allocated by the code manager so it is
2891 * guaranteed to be at a 32 bit offset.
2894 if (patch_type != MONO_PATCH_INFO_ABS) {
2895 /* The target is in memory allocated using the code manager */
2898 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2899 if (((MonoMethod*)data)->klass->image->aot_module)
2900 /* The callee might be an AOT method */
2902 if (((MonoMethod*)data)->dynamic)
2903 /* The target is in malloc-ed memory */
2907 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2909 * The call might go directly to a native function without
2912 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2914 gconstpointer target = mono_icall_get_wrapper (mi);
2915 if ((((guint64)target) >> 32) != 0)
2921 MonoJumpInfo *jinfo = NULL;
2923 if (cfg->abs_patches)
2924 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2926 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2927 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2928 if (mi && (((guint64)mi->func) >> 32) == 0)
2933 * This is not really an optimization, but required because the
2934 * generic class init trampolines use R11 to pass the vtable.
2939 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2941 if (info->func == info->wrapper) {
2943 if ((((guint64)info->func) >> 32) == 0)
2947 /* See the comment in mono_codegen () */
2948 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2952 else if ((((guint64)data) >> 32) == 0) {
2959 if (cfg->method->dynamic)
2960 /* These methods are allocated using malloc */
2963 #ifdef MONO_ARCH_NOMAP32BIT
2966 #if defined(__native_client__)
2967 /* Always use near_call == TRUE for Native Client */
2970 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2971 if (optimize_for_xen)
2974 if (cfg->compile_aot) {
2981 * Align the call displacement to an address divisible by 4 so it does
2982 * not span cache lines. This is required for code patching to work on SMP
2985 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2986 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2987 amd64_padding (code, pad_size);
2989 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2990 amd64_call_code (code, 0);
2993 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2994 amd64_set_reg_template (code, GP_SCRATCH_REG);
2995 amd64_call_reg (code, GP_SCRATCH_REG);
3002 static inline guint8*
3003 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3006 if (win64_adjust_stack)
3007 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3009 code = emit_call_body (cfg, code, patch_type, data);
3011 if (win64_adjust_stack)
3012 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3019 store_membase_imm_to_store_membase_reg (int opcode)
3022 case OP_STORE_MEMBASE_IMM:
3023 return OP_STORE_MEMBASE_REG;
3024 case OP_STOREI4_MEMBASE_IMM:
3025 return OP_STOREI4_MEMBASE_REG;
3026 case OP_STOREI8_MEMBASE_IMM:
3027 return OP_STOREI8_MEMBASE_REG;
3035 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3038 * mono_arch_peephole_pass_1:
3040 * Perform peephole opts which should/can be performed before local regalloc
3043 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3047 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3048 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3050 switch (ins->opcode) {
3054 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3056 * X86_LEA is like ADD, but doesn't have the
3057 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3058 * its operand to 64 bit.
3060 ins->opcode = OP_X86_LEA_MEMBASE;
3061 ins->inst_basereg = ins->sreg1;
3066 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3070 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3071 * the latter has length 2-3 instead of 6 (reverse constant
3072 * propagation). These instruction sequences are very common
3073 * in the initlocals bblock.
3075 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3076 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3077 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3078 ins2->sreg1 = ins->dreg;
3079 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3081 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3084 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3092 case OP_COMPARE_IMM:
3093 case OP_LCOMPARE_IMM:
3094 /* OP_COMPARE_IMM (reg, 0)
3096 * OP_AMD64_TEST_NULL (reg)
3099 ins->opcode = OP_AMD64_TEST_NULL;
3101 case OP_ICOMPARE_IMM:
3103 ins->opcode = OP_X86_TEST_NULL;
3105 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3107 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3108 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3110 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3111 * OP_COMPARE_IMM reg, imm
3113 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3115 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3116 ins->inst_basereg == last_ins->inst_destbasereg &&
3117 ins->inst_offset == last_ins->inst_offset) {
3118 ins->opcode = OP_ICOMPARE_IMM;
3119 ins->sreg1 = last_ins->sreg1;
3121 /* check if we can remove cmp reg,0 with test null */
3123 ins->opcode = OP_X86_TEST_NULL;
3129 mono_peephole_ins (bb, ins);
3134 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3138 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3139 switch (ins->opcode) {
3142 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3143 /* reg = 0 -> XOR (reg, reg) */
3144 /* XOR sets cflags on x86, so we cant do it always */
3145 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3146 ins->opcode = OP_LXOR;
3147 ins->sreg1 = ins->dreg;
3148 ins->sreg2 = ins->dreg;
3156 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3157 * 0 result into 64 bits.
3159 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3160 ins->opcode = OP_IXOR;
3164 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3168 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3169 * the latter has length 2-3 instead of 6 (reverse constant
3170 * propagation). These instruction sequences are very common
3171 * in the initlocals bblock.
3173 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3174 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3175 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3176 ins2->sreg1 = ins->dreg;
3177 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3179 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3182 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3191 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3192 ins->opcode = OP_X86_INC_REG;
3195 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3196 ins->opcode = OP_X86_DEC_REG;
3200 mono_peephole_ins (bb, ins);
3204 #define NEW_INS(cfg,ins,dest,op) do { \
3205 MONO_INST_NEW ((cfg), (dest), (op)); \
3206 (dest)->cil_code = (ins)->cil_code; \
3207 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3211 * mono_arch_lowering_pass:
3213 * Converts complex opcodes into simpler ones so that each IR instruction
3214 * corresponds to one machine instruction.
3217 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3219 MonoInst *ins, *n, *temp;
3222 * FIXME: Need to add more instructions, but the current machine
3223 * description can't model some parts of the composite instructions like
3226 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3227 switch (ins->opcode) {
3231 case OP_IDIV_UN_IMM:
3232 case OP_IREM_UN_IMM:
3235 mono_decompose_op_imm (cfg, bb, ins);
3237 case OP_COMPARE_IMM:
3238 case OP_LCOMPARE_IMM:
3239 if (!amd64_is_imm32 (ins->inst_imm)) {
3240 NEW_INS (cfg, ins, temp, OP_I8CONST);
3241 temp->inst_c0 = ins->inst_imm;
3242 temp->dreg = mono_alloc_ireg (cfg);
3243 ins->opcode = OP_COMPARE;
3244 ins->sreg2 = temp->dreg;
3247 #ifndef __mono_ilp32__
3248 case OP_LOAD_MEMBASE:
3250 case OP_LOADI8_MEMBASE:
3251 #ifndef __native_client_codegen__
3252 /* Don't generate memindex opcodes (to simplify */
3253 /* read sandboxing) */
3254 if (!amd64_is_imm32 (ins->inst_offset)) {
3255 NEW_INS (cfg, ins, temp, OP_I8CONST);
3256 temp->inst_c0 = ins->inst_offset;
3257 temp->dreg = mono_alloc_ireg (cfg);
3258 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3259 ins->inst_indexreg = temp->dreg;
3263 #ifndef __mono_ilp32__
3264 case OP_STORE_MEMBASE_IMM:
3266 case OP_STOREI8_MEMBASE_IMM:
3267 if (!amd64_is_imm32 (ins->inst_imm)) {
3268 NEW_INS (cfg, ins, temp, OP_I8CONST);
3269 temp->inst_c0 = ins->inst_imm;
3270 temp->dreg = mono_alloc_ireg (cfg);
3271 ins->opcode = OP_STOREI8_MEMBASE_REG;
3272 ins->sreg1 = temp->dreg;
3275 #ifdef MONO_ARCH_SIMD_INTRINSICS
3276 case OP_EXPAND_I1: {
3277 int temp_reg1 = mono_alloc_ireg (cfg);
3278 int temp_reg2 = mono_alloc_ireg (cfg);
3279 int original_reg = ins->sreg1;
3281 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3282 temp->sreg1 = original_reg;
3283 temp->dreg = temp_reg1;
3285 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3286 temp->sreg1 = temp_reg1;
3287 temp->dreg = temp_reg2;
3290 NEW_INS (cfg, ins, temp, OP_LOR);
3291 temp->sreg1 = temp->dreg = temp_reg2;
3292 temp->sreg2 = temp_reg1;
3294 ins->opcode = OP_EXPAND_I2;
3295 ins->sreg1 = temp_reg2;
3304 bb->max_vreg = cfg->next_vreg;
3308 branch_cc_table [] = {
3309 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3310 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3311 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3314 /* Maps CMP_... constants to X86_CC_... constants */
3317 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3318 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3322 cc_signed_table [] = {
3323 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3324 FALSE, FALSE, FALSE, FALSE
3327 /*#include "cprop.c"*/
3329 static unsigned char*
3330 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3333 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3335 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3338 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3340 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3344 static unsigned char*
3345 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3347 int sreg = tree->sreg1;
3348 int need_touch = FALSE;
3350 #if defined(TARGET_WIN32)
3352 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3353 if (!tree->flags & MONO_INST_INIT)
3362 * If requested stack size is larger than one page,
3363 * perform stack-touch operation
3366 * Generate stack probe code.
3367 * Under Windows, it is necessary to allocate one page at a time,
3368 * "touching" stack after each successful sub-allocation. This is
3369 * because of the way stack growth is implemented - there is a
3370 * guard page before the lowest stack page that is currently commited.
3371 * Stack normally grows sequentially so OS traps access to the
3372 * guard page and commits more pages when needed.
3374 amd64_test_reg_imm (code, sreg, ~0xFFF);
3375 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3377 br[2] = code; /* loop */
3378 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3379 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3380 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3381 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3382 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3383 amd64_patch (br[3], br[2]);
3384 amd64_test_reg_reg (code, sreg, sreg);
3385 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3386 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3388 br[1] = code; x86_jump8 (code, 0);
3390 amd64_patch (br[0], code);
3391 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3392 amd64_patch (br[1], code);
3393 amd64_patch (br[4], code);
3396 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3398 if (tree->flags & MONO_INST_INIT) {
3400 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3401 amd64_push_reg (code, AMD64_RAX);
3404 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3405 amd64_push_reg (code, AMD64_RCX);
3408 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3409 amd64_push_reg (code, AMD64_RDI);
3413 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3414 if (sreg != AMD64_RCX)
3415 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3416 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3418 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3419 if (cfg->param_area)
3420 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3422 #if defined(__default_codegen__)
3423 amd64_prefix (code, X86_REP_PREFIX);
3425 #elif defined(__native_client_codegen__)
3426 /* NaCl stos pseudo-instruction */
3427 amd64_codegen_pre(code);
3428 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3429 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3430 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3431 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3432 amd64_prefix (code, X86_REP_PREFIX);
3434 amd64_codegen_post(code);
3435 #endif /* __native_client_codegen__ */
3437 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3438 amd64_pop_reg (code, AMD64_RDI);
3439 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3440 amd64_pop_reg (code, AMD64_RCX);
3441 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3442 amd64_pop_reg (code, AMD64_RAX);
3448 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3453 /* Move return value to the target register */
3454 /* FIXME: do this in the local reg allocator */
3455 switch (ins->opcode) {
3458 case OP_CALL_MEMBASE:
3461 case OP_LCALL_MEMBASE:
3462 g_assert (ins->dreg == AMD64_RAX);
3466 case OP_FCALL_MEMBASE: {
3467 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3468 if (rtype->type == MONO_TYPE_R4) {
3469 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3472 if (ins->dreg != AMD64_XMM0)
3473 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3479 case OP_RCALL_MEMBASE:
3480 if (ins->dreg != AMD64_XMM0)
3481 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3485 case OP_VCALL_MEMBASE:
3488 case OP_VCALL2_MEMBASE:
3489 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3490 if (cinfo->ret.storage == ArgValuetypeInReg) {
3491 MonoInst *loc = cfg->arch.vret_addr_loc;
3493 /* Load the destination address */
3494 g_assert (loc->opcode == OP_REGOFFSET);
3495 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3497 for (quad = 0; quad < 2; quad ++) {
3498 switch (cinfo->ret.pair_storage [quad]) {
3500 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3502 case ArgInFloatSSEReg:
3503 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3505 case ArgInDoubleSSEReg:
3506 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3521 #endif /* DISABLE_JIT */
3524 static int tls_gs_offset;
3528 mono_amd64_have_tls_get (void)
3531 static gboolean have_tls_get = FALSE;
3532 static gboolean inited = FALSE;
3536 return have_tls_get;
3538 ins = (guint8*)pthread_getspecific;
3541 * We're looking for these two instructions:
3543 * mov %gs:[offset](,%rdi,8),%rax
3546 have_tls_get = ins [0] == 0x65 &&
3558 tls_gs_offset = ins[5];
3560 return have_tls_get;
3561 #elif defined(TARGET_ANDROID)
3569 mono_amd64_get_tls_gs_offset (void)
3572 return tls_gs_offset;
3574 g_assert_not_reached ();
3580 * mono_amd64_emit_tls_get:
3581 * @code: buffer to store code to
3582 * @dreg: hard register where to place the result
3583 * @tls_offset: offset info
3585 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3586 * the dreg register the item in the thread local storage identified
3589 * Returns: a pointer to the end of the stored code
3592 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3595 if (tls_offset < 64) {
3596 x86_prefix (code, X86_GS_PREFIX);
3597 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3601 g_assert (tls_offset < 0x440);
3602 /* Load TEB->TlsExpansionSlots */
3603 x86_prefix (code, X86_GS_PREFIX);
3604 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3605 amd64_test_reg_reg (code, dreg, dreg);
3607 amd64_branch (code, X86_CC_EQ, code, TRUE);
3608 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3609 amd64_patch (buf [0], code);
3611 #elif defined(__APPLE__)
3612 x86_prefix (code, X86_GS_PREFIX);
3613 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3615 if (optimize_for_xen) {
3616 x86_prefix (code, X86_FS_PREFIX);
3617 amd64_mov_reg_mem (code, dreg, 0, 8);
3618 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3620 x86_prefix (code, X86_FS_PREFIX);
3621 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3628 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3630 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3632 if (dreg != offset_reg)
3633 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3634 amd64_prefix (code, X86_GS_PREFIX);
3635 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3636 #elif defined(__linux__)
3639 if (dreg == offset_reg) {
3640 /* Use a temporary reg by saving it to the redzone */
3641 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3642 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3643 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3644 offset_reg = tmpreg;
3646 x86_prefix (code, X86_FS_PREFIX);
3647 amd64_mov_reg_mem (code, dreg, 0, 8);
3648 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3650 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3652 g_assert_not_reached ();
3658 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3661 g_assert_not_reached ();
3662 #elif defined(__APPLE__)
3663 x86_prefix (code, X86_GS_PREFIX);
3664 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3666 g_assert (!optimize_for_xen);
3667 x86_prefix (code, X86_FS_PREFIX);
3668 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3674 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3676 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3678 g_assert_not_reached ();
3679 #elif defined(__APPLE__)
3680 x86_prefix (code, X86_GS_PREFIX);
3681 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3683 x86_prefix (code, X86_FS_PREFIX);
3684 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3690 * mono_arch_translate_tls_offset:
3692 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3695 mono_arch_translate_tls_offset (int offset)
3698 return tls_gs_offset + (offset * 8);
3707 * Emit code to initialize an LMF structure at LMF_OFFSET.
3710 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3713 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3716 * sp is saved right before calls but we need to save it here too so
3717 * async stack walks would work.
3719 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3721 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3722 if (cfg->arch.omit_fp && cfa_offset != -1)
3723 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3725 /* These can't contain refs */
3726 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3727 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3728 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3729 /* These are handled automatically by the stack marking code */
3730 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3735 #define REAL_PRINT_REG(text,reg) \
3736 mono_assert (reg >= 0); \
3737 amd64_push_reg (code, AMD64_RAX); \
3738 amd64_push_reg (code, AMD64_RDX); \
3739 amd64_push_reg (code, AMD64_RCX); \
3740 amd64_push_reg (code, reg); \
3741 amd64_push_imm (code, reg); \
3742 amd64_push_imm (code, text " %d %p\n"); \
3743 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3744 amd64_call_reg (code, AMD64_RAX); \
3745 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3746 amd64_pop_reg (code, AMD64_RCX); \
3747 amd64_pop_reg (code, AMD64_RDX); \
3748 amd64_pop_reg (code, AMD64_RAX);
3750 /* benchmark and set based on cpu */
3751 #define LOOP_ALIGNMENT 8
3752 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3756 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3761 guint8 *code = cfg->native_code + cfg->code_len;
3764 /* Fix max_offset estimate for each successor bb */
3765 if (cfg->opt & MONO_OPT_BRANCH) {
3766 int current_offset = cfg->code_len;
3767 MonoBasicBlock *current_bb;
3768 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3769 current_bb->max_offset = current_offset;
3770 current_offset += current_bb->max_length;
3774 if (cfg->opt & MONO_OPT_LOOP) {
3775 int pad, align = LOOP_ALIGNMENT;
3776 /* set alignment depending on cpu */
3777 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3779 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3780 amd64_padding (code, pad);
3781 cfg->code_len += pad;
3782 bb->native_offset = cfg->code_len;
3786 #if defined(__native_client_codegen__)
3787 /* For Native Client, all indirect call/jump targets must be */
3788 /* 32-byte aligned. Exception handler blocks are jumped to */
3789 /* indirectly as well. */
3790 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3791 (bb->flags & BB_EXCEPTION_HANDLER);
3793 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3794 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3795 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3796 cfg->code_len += pad;
3797 bb->native_offset = cfg->code_len;
3799 #endif /*__native_client_codegen__*/
3801 if (cfg->verbose_level > 2)
3802 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3804 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3805 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3806 g_assert (!cfg->compile_aot);
3808 cov->data [bb->dfn].cil_code = bb->cil_code;
3809 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3810 /* this is not thread save, but good enough */
3811 amd64_inc_membase (code, AMD64_R11, 0);
3814 offset = code - cfg->native_code;
3816 mono_debug_open_block (cfg, bb, offset);
3818 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3819 x86_breakpoint (code);
3821 MONO_BB_FOR_EACH_INS (bb, ins) {
3822 offset = code - cfg->native_code;
3824 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3826 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3828 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3829 cfg->code_size *= 2;
3830 cfg->native_code = mono_realloc_native_code(cfg);
3831 code = cfg->native_code + offset;
3832 cfg->stat_code_reallocs++;
3835 if (cfg->debug_info)
3836 mono_debug_record_line_number (cfg, ins, offset);
3838 switch (ins->opcode) {
3840 amd64_mul_reg (code, ins->sreg2, TRUE);
3843 amd64_mul_reg (code, ins->sreg2, FALSE);
3845 case OP_X86_SETEQ_MEMBASE:
3846 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3848 case OP_STOREI1_MEMBASE_IMM:
3849 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3851 case OP_STOREI2_MEMBASE_IMM:
3852 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3854 case OP_STOREI4_MEMBASE_IMM:
3855 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3857 case OP_STOREI1_MEMBASE_REG:
3858 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3860 case OP_STOREI2_MEMBASE_REG:
3861 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3863 /* In AMD64 NaCl, pointers are 4 bytes, */
3864 /* so STORE_* != STOREI8_*. Likewise below. */
3865 case OP_STORE_MEMBASE_REG:
3866 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3868 case OP_STOREI8_MEMBASE_REG:
3869 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3871 case OP_STOREI4_MEMBASE_REG:
3872 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3874 case OP_STORE_MEMBASE_IMM:
3875 #ifndef __native_client_codegen__
3876 /* In NaCl, this could be a PCONST type, which could */
3877 /* mean a pointer type was copied directly into the */
3878 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3879 /* the value would be 0x00000000FFFFFFFF which is */
3880 /* not proper for an imm32 unless you cast it. */
3881 g_assert (amd64_is_imm32 (ins->inst_imm));
3883 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3885 case OP_STOREI8_MEMBASE_IMM:
3886 g_assert (amd64_is_imm32 (ins->inst_imm));
3887 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3890 #ifdef __mono_ilp32__
3891 /* In ILP32, pointers are 4 bytes, so separate these */
3892 /* cases, use literal 8 below where we really want 8 */
3893 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3894 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3898 // FIXME: Decompose this earlier
3899 if (amd64_is_imm32 (ins->inst_imm))
3900 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3902 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3903 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3907 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3908 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3911 // FIXME: Decompose this earlier
3912 if (amd64_is_imm32 (ins->inst_imm))
3913 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3915 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3916 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3920 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3921 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3924 /* For NaCl, pointers are 4 bytes, so separate these */
3925 /* cases, use literal 8 below where we really want 8 */
3926 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3927 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3929 case OP_LOAD_MEMBASE:
3930 g_assert (amd64_is_imm32 (ins->inst_offset));
3931 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3933 case OP_LOADI8_MEMBASE:
3934 /* Use literal 8 instead of sizeof pointer or */
3935 /* register, we really want 8 for this opcode */
3936 g_assert (amd64_is_imm32 (ins->inst_offset));
3937 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3939 case OP_LOADI4_MEMBASE:
3940 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3942 case OP_LOADU4_MEMBASE:
3943 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3945 case OP_LOADU1_MEMBASE:
3946 /* The cpu zero extends the result into 64 bits */
3947 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3949 case OP_LOADI1_MEMBASE:
3950 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3952 case OP_LOADU2_MEMBASE:
3953 /* The cpu zero extends the result into 64 bits */
3954 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3956 case OP_LOADI2_MEMBASE:
3957 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3959 case OP_AMD64_LOADI8_MEMINDEX:
3960 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3962 case OP_LCONV_TO_I1:
3963 case OP_ICONV_TO_I1:
3965 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3967 case OP_LCONV_TO_I2:
3968 case OP_ICONV_TO_I2:
3970 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3972 case OP_LCONV_TO_U1:
3973 case OP_ICONV_TO_U1:
3974 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3976 case OP_LCONV_TO_U2:
3977 case OP_ICONV_TO_U2:
3978 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3981 /* Clean out the upper word */
3982 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3985 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3989 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3991 case OP_COMPARE_IMM:
3992 #if defined(__mono_ilp32__)
3993 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3994 g_assert (amd64_is_imm32 (ins->inst_imm));
3995 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3998 case OP_LCOMPARE_IMM:
3999 g_assert (amd64_is_imm32 (ins->inst_imm));
4000 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4002 case OP_X86_COMPARE_REG_MEMBASE:
4003 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4005 case OP_X86_TEST_NULL:
4006 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4008 case OP_AMD64_TEST_NULL:
4009 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4012 case OP_X86_ADD_REG_MEMBASE:
4013 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4015 case OP_X86_SUB_REG_MEMBASE:
4016 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4018 case OP_X86_AND_REG_MEMBASE:
4019 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4021 case OP_X86_OR_REG_MEMBASE:
4022 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4024 case OP_X86_XOR_REG_MEMBASE:
4025 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4028 case OP_X86_ADD_MEMBASE_IMM:
4029 /* FIXME: Make a 64 version too */
4030 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4032 case OP_X86_SUB_MEMBASE_IMM:
4033 g_assert (amd64_is_imm32 (ins->inst_imm));
4034 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4036 case OP_X86_AND_MEMBASE_IMM:
4037 g_assert (amd64_is_imm32 (ins->inst_imm));
4038 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4040 case OP_X86_OR_MEMBASE_IMM:
4041 g_assert (amd64_is_imm32 (ins->inst_imm));
4042 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4044 case OP_X86_XOR_MEMBASE_IMM:
4045 g_assert (amd64_is_imm32 (ins->inst_imm));
4046 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4048 case OP_X86_ADD_MEMBASE_REG:
4049 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4051 case OP_X86_SUB_MEMBASE_REG:
4052 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4054 case OP_X86_AND_MEMBASE_REG:
4055 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4057 case OP_X86_OR_MEMBASE_REG:
4058 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4060 case OP_X86_XOR_MEMBASE_REG:
4061 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4063 case OP_X86_INC_MEMBASE:
4064 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4066 case OP_X86_INC_REG:
4067 amd64_inc_reg_size (code, ins->dreg, 4);
4069 case OP_X86_DEC_MEMBASE:
4070 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4072 case OP_X86_DEC_REG:
4073 amd64_dec_reg_size (code, ins->dreg, 4);
4075 case OP_X86_MUL_REG_MEMBASE:
4076 case OP_X86_MUL_MEMBASE_REG:
4077 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4079 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4080 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4082 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4083 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4085 case OP_AMD64_COMPARE_MEMBASE_REG:
4086 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4088 case OP_AMD64_COMPARE_MEMBASE_IMM:
4089 g_assert (amd64_is_imm32 (ins->inst_imm));
4090 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092 case OP_X86_COMPARE_MEMBASE8_IMM:
4093 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4095 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4096 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4098 case OP_AMD64_COMPARE_REG_MEMBASE:
4099 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4102 case OP_AMD64_ADD_REG_MEMBASE:
4103 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4105 case OP_AMD64_SUB_REG_MEMBASE:
4106 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4108 case OP_AMD64_AND_REG_MEMBASE:
4109 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4111 case OP_AMD64_OR_REG_MEMBASE:
4112 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4114 case OP_AMD64_XOR_REG_MEMBASE:
4115 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4118 case OP_AMD64_ADD_MEMBASE_REG:
4119 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4121 case OP_AMD64_SUB_MEMBASE_REG:
4122 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124 case OP_AMD64_AND_MEMBASE_REG:
4125 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4127 case OP_AMD64_OR_MEMBASE_REG:
4128 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4130 case OP_AMD64_XOR_MEMBASE_REG:
4131 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4134 case OP_AMD64_ADD_MEMBASE_IMM:
4135 g_assert (amd64_is_imm32 (ins->inst_imm));
4136 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4138 case OP_AMD64_SUB_MEMBASE_IMM:
4139 g_assert (amd64_is_imm32 (ins->inst_imm));
4140 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4142 case OP_AMD64_AND_MEMBASE_IMM:
4143 g_assert (amd64_is_imm32 (ins->inst_imm));
4144 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4146 case OP_AMD64_OR_MEMBASE_IMM:
4147 g_assert (amd64_is_imm32 (ins->inst_imm));
4148 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4150 case OP_AMD64_XOR_MEMBASE_IMM:
4151 g_assert (amd64_is_imm32 (ins->inst_imm));
4152 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4156 amd64_breakpoint (code);
4158 case OP_RELAXED_NOP:
4159 x86_prefix (code, X86_REP_PREFIX);
4167 case OP_DUMMY_STORE:
4168 case OP_DUMMY_ICONST:
4169 case OP_DUMMY_R8CONST:
4170 case OP_NOT_REACHED:
4173 case OP_IL_SEQ_POINT:
4174 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4176 case OP_SEQ_POINT: {
4179 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4180 if (cfg->compile_aot) {
4181 MonoInst *var = cfg->arch.ss_tramp_var;
4184 /* Load ss_tramp_var */
4185 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4186 /* Load the trampoline address */
4187 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4188 /* Call it if it is non-null */
4189 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4191 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4192 amd64_call_reg (code, AMD64_R11);
4193 amd64_patch (label, code);
4196 * Read from the single stepping trigger page. This will cause a
4197 * SIGSEGV when single stepping is enabled.
4198 * We do this _before_ the breakpoint, so single stepping after
4199 * a breakpoint is hit will step to the next IL offset.
4201 MonoInst *var = cfg->arch.ss_trigger_page_var;
4203 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4204 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4209 * This is the address which is saved in seq points,
4211 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4213 if (cfg->compile_aot) {
4214 guint32 offset = code - cfg->native_code;
4216 MonoInst *info_var = cfg->arch.seq_point_info_var;
4220 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4221 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4222 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4223 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4224 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4226 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4227 /* Call the trampoline */
4228 amd64_call_reg (code, AMD64_R11);
4229 amd64_patch (label, code);
4232 * A placeholder for a possible breakpoint inserted by
4233 * mono_arch_set_breakpoint ().
4235 for (i = 0; i < breakpoint_size; ++i)
4239 * Add an additional nop so skipping the bp doesn't cause the ip to point
4240 * to another IL offset.
4248 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4251 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4255 g_assert (amd64_is_imm32 (ins->inst_imm));
4256 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4259 g_assert (amd64_is_imm32 (ins->inst_imm));
4260 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4265 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4268 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4272 g_assert (amd64_is_imm32 (ins->inst_imm));
4273 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4276 g_assert (amd64_is_imm32 (ins->inst_imm));
4277 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4280 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4284 g_assert (amd64_is_imm32 (ins->inst_imm));
4285 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4288 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4293 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4295 switch (ins->inst_imm) {
4299 if (ins->dreg != ins->sreg1)
4300 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4301 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4304 /* LEA r1, [r2 + r2*2] */
4305 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4308 /* LEA r1, [r2 + r2*4] */
4309 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4312 /* LEA r1, [r2 + r2*2] */
4314 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4315 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4318 /* LEA r1, [r2 + r2*8] */
4319 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4322 /* LEA r1, [r2 + r2*4] */
4324 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4325 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4328 /* LEA r1, [r2 + r2*2] */
4330 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4331 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4334 /* LEA r1, [r2 + r2*4] */
4335 /* LEA r1, [r1 + r1*4] */
4336 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4337 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4340 /* LEA r1, [r2 + r2*4] */
4342 /* LEA r1, [r1 + r1*4] */
4343 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4344 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4345 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4348 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4355 #if defined( __native_client_codegen__ )
4356 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4357 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4359 /* Regalloc magic makes the div/rem cases the same */
4360 if (ins->sreg2 == AMD64_RDX) {
4361 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4363 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4366 amd64_div_reg (code, ins->sreg2, TRUE);
4371 #if defined( __native_client_codegen__ )
4372 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4373 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4375 if (ins->sreg2 == AMD64_RDX) {
4376 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4377 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4378 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4380 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4381 amd64_div_reg (code, ins->sreg2, FALSE);
4386 #if defined( __native_client_codegen__ )
4387 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4388 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4390 if (ins->sreg2 == AMD64_RDX) {
4391 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4392 amd64_cdq_size (code, 4);
4393 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4395 amd64_cdq_size (code, 4);
4396 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4401 #if defined( __native_client_codegen__ )
4402 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4403 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4405 if (ins->sreg2 == AMD64_RDX) {
4406 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4407 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4408 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4410 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4411 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4415 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4416 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4419 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4423 g_assert (amd64_is_imm32 (ins->inst_imm));
4424 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4427 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4431 g_assert (amd64_is_imm32 (ins->inst_imm));
4432 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4435 g_assert (ins->sreg2 == AMD64_RCX);
4436 amd64_shift_reg (code, X86_SHL, ins->dreg);
4439 g_assert (ins->sreg2 == AMD64_RCX);
4440 amd64_shift_reg (code, X86_SAR, ins->dreg);
4444 g_assert (amd64_is_imm32 (ins->inst_imm));
4445 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4448 g_assert (amd64_is_imm32 (ins->inst_imm));
4449 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4451 case OP_LSHR_UN_IMM:
4452 g_assert (amd64_is_imm32 (ins->inst_imm));
4453 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4456 g_assert (ins->sreg2 == AMD64_RCX);
4457 amd64_shift_reg (code, X86_SHR, ins->dreg);
4461 g_assert (amd64_is_imm32 (ins->inst_imm));
4462 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4467 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4470 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4473 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4476 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4480 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4483 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4486 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4489 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4492 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4495 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4498 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4501 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4504 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4507 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4510 amd64_neg_reg_size (code, ins->sreg1, 4);
4513 amd64_not_reg_size (code, ins->sreg1, 4);
4516 g_assert (ins->sreg2 == AMD64_RCX);
4517 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4520 g_assert (ins->sreg2 == AMD64_RCX);
4521 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4524 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4526 case OP_ISHR_UN_IMM:
4527 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4530 g_assert (ins->sreg2 == AMD64_RCX);
4531 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4534 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4537 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4540 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4541 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4543 case OP_IMUL_OVF_UN:
4544 case OP_LMUL_OVF_UN: {
4545 /* the mul operation and the exception check should most likely be split */
4546 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4547 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4548 /*g_assert (ins->sreg2 == X86_EAX);
4549 g_assert (ins->dreg == X86_EAX);*/
4550 if (ins->sreg2 == X86_EAX) {
4551 non_eax_reg = ins->sreg1;
4552 } else if (ins->sreg1 == X86_EAX) {
4553 non_eax_reg = ins->sreg2;
4555 /* no need to save since we're going to store to it anyway */
4556 if (ins->dreg != X86_EAX) {
4558 amd64_push_reg (code, X86_EAX);
4560 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4561 non_eax_reg = ins->sreg2;
4563 if (ins->dreg == X86_EDX) {
4566 amd64_push_reg (code, X86_EAX);
4570 amd64_push_reg (code, X86_EDX);
4572 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4573 /* save before the check since pop and mov don't change the flags */
4574 if (ins->dreg != X86_EAX)
4575 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4577 amd64_pop_reg (code, X86_EDX);
4579 amd64_pop_reg (code, X86_EAX);
4580 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4584 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4586 case OP_ICOMPARE_IMM:
4587 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4609 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4617 case OP_CMOV_INE_UN:
4618 case OP_CMOV_IGE_UN:
4619 case OP_CMOV_IGT_UN:
4620 case OP_CMOV_ILE_UN:
4621 case OP_CMOV_ILT_UN:
4627 case OP_CMOV_LNE_UN:
4628 case OP_CMOV_LGE_UN:
4629 case OP_CMOV_LGT_UN:
4630 case OP_CMOV_LLE_UN:
4631 case OP_CMOV_LLT_UN:
4632 g_assert (ins->dreg == ins->sreg1);
4633 /* This needs to operate on 64 bit values */
4634 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4638 amd64_not_reg (code, ins->sreg1);
4641 amd64_neg_reg (code, ins->sreg1);
4646 if ((((guint64)ins->inst_c0) >> 32) == 0)
4647 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4649 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4652 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4653 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4656 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4657 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4660 if (ins->dreg != ins->sreg1)
4661 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4663 case OP_AMD64_SET_XMMREG_R4: {
4665 if (ins->dreg != ins->sreg1)
4666 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4668 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4672 case OP_AMD64_SET_XMMREG_R8: {
4673 if (ins->dreg != ins->sreg1)
4674 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4678 MonoCallInst *call = (MonoCallInst*)ins;
4679 int i, save_area_offset;
4681 g_assert (!cfg->method->save_lmf);
4683 /* Restore callee saved registers */
4684 save_area_offset = cfg->arch.reg_save_area_offset;
4685 for (i = 0; i < AMD64_NREG; ++i)
4686 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4687 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4688 save_area_offset += 8;
4691 if (cfg->arch.omit_fp) {
4692 if (cfg->arch.stack_alloc_size)
4693 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4695 if (call->stack_usage)
4698 /* Copy arguments on the stack to our argument area */
4699 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4700 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4701 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4707 offset = code - cfg->native_code;
4708 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4709 if (cfg->compile_aot)
4710 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4712 amd64_set_reg_template (code, AMD64_R11);
4713 amd64_jump_reg (code, AMD64_R11);
4714 ins->flags |= MONO_INST_GC_CALLSITE;
4715 ins->backend.pc_offset = code - cfg->native_code;
4719 /* ensure ins->sreg1 is not NULL */
4720 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4723 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4724 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4734 call = (MonoCallInst*)ins;
4736 * The AMD64 ABI forces callers to know about varargs.
4738 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4739 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4740 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4742 * Since the unmanaged calling convention doesn't contain a
4743 * 'vararg' entry, we have to treat every pinvoke call as a
4744 * potential vararg call.
4748 for (i = 0; i < AMD64_XMM_NREG; ++i)
4749 if (call->used_fregs & (1 << i))
4752 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4754 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4757 if (ins->flags & MONO_INST_HAS_METHOD)
4758 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4760 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4761 ins->flags |= MONO_INST_GC_CALLSITE;
4762 ins->backend.pc_offset = code - cfg->native_code;
4763 code = emit_move_return_value (cfg, ins, code);
4770 case OP_VOIDCALL_REG:
4772 call = (MonoCallInst*)ins;
4774 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4775 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4776 ins->sreg1 = AMD64_R11;
4780 * The AMD64 ABI forces callers to know about varargs.
4782 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4783 if (ins->sreg1 == AMD64_RAX) {
4784 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4785 ins->sreg1 = AMD64_R11;
4787 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4788 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4790 * Since the unmanaged calling convention doesn't contain a
4791 * 'vararg' entry, we have to treat every pinvoke call as a
4792 * potential vararg call.
4796 for (i = 0; i < AMD64_XMM_NREG; ++i)
4797 if (call->used_fregs & (1 << i))
4799 if (ins->sreg1 == AMD64_RAX) {
4800 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4801 ins->sreg1 = AMD64_R11;
4804 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4806 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4809 amd64_call_reg (code, ins->sreg1);
4810 ins->flags |= MONO_INST_GC_CALLSITE;
4811 ins->backend.pc_offset = code - cfg->native_code;
4812 code = emit_move_return_value (cfg, ins, code);
4814 case OP_FCALL_MEMBASE:
4815 case OP_RCALL_MEMBASE:
4816 case OP_LCALL_MEMBASE:
4817 case OP_VCALL_MEMBASE:
4818 case OP_VCALL2_MEMBASE:
4819 case OP_VOIDCALL_MEMBASE:
4820 case OP_CALL_MEMBASE:
4821 call = (MonoCallInst*)ins;
4823 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4824 ins->flags |= MONO_INST_GC_CALLSITE;
4825 ins->backend.pc_offset = code - cfg->native_code;
4826 code = emit_move_return_value (cfg, ins, code);
4830 MonoInst *var = cfg->dyn_call_var;
4832 g_assert (var->opcode == OP_REGOFFSET);
4834 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4835 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4837 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4839 /* Save args buffer */
4840 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4842 /* Set argument registers */
4843 for (i = 0; i < PARAM_REGS; ++i)
4844 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4847 amd64_call_reg (code, AMD64_R10);
4849 ins->flags |= MONO_INST_GC_CALLSITE;
4850 ins->backend.pc_offset = code - cfg->native_code;
4853 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4854 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4857 case OP_AMD64_SAVE_SP_TO_LMF: {
4858 MonoInst *lmf_var = cfg->lmf_var;
4859 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4863 g_assert_not_reached ();
4864 amd64_push_reg (code, ins->sreg1);
4866 case OP_X86_PUSH_IMM:
4867 g_assert_not_reached ();
4868 g_assert (amd64_is_imm32 (ins->inst_imm));
4869 amd64_push_imm (code, ins->inst_imm);
4871 case OP_X86_PUSH_MEMBASE:
4872 g_assert_not_reached ();
4873 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4875 case OP_X86_PUSH_OBJ: {
4876 int size = ALIGN_TO (ins->inst_imm, 8);
4878 g_assert_not_reached ();
4880 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4881 amd64_push_reg (code, AMD64_RDI);
4882 amd64_push_reg (code, AMD64_RSI);
4883 amd64_push_reg (code, AMD64_RCX);
4884 if (ins->inst_offset)
4885 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4887 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4888 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4889 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4891 amd64_prefix (code, X86_REP_PREFIX);
4893 amd64_pop_reg (code, AMD64_RCX);
4894 amd64_pop_reg (code, AMD64_RSI);
4895 amd64_pop_reg (code, AMD64_RDI);
4899 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4901 case OP_X86_LEA_MEMBASE:
4902 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4905 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4908 /* keep alignment */
4909 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4910 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4911 code = mono_emit_stack_alloc (cfg, code, ins);
4912 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4913 if (cfg->param_area)
4914 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4916 case OP_LOCALLOC_IMM: {
4917 guint32 size = ins->inst_imm;
4918 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4920 if (ins->flags & MONO_INST_INIT) {
4924 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4925 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4927 for (i = 0; i < size; i += 8)
4928 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4929 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4931 amd64_mov_reg_imm (code, ins->dreg, size);
4932 ins->sreg1 = ins->dreg;
4934 code = mono_emit_stack_alloc (cfg, code, ins);
4935 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4938 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4939 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4941 if (cfg->param_area)
4942 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4946 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4947 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4948 (gpointer)"mono_arch_throw_exception", FALSE);
4949 ins->flags |= MONO_INST_GC_CALLSITE;
4950 ins->backend.pc_offset = code - cfg->native_code;
4954 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4955 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4956 (gpointer)"mono_arch_rethrow_exception", FALSE);
4957 ins->flags |= MONO_INST_GC_CALLSITE;
4958 ins->backend.pc_offset = code - cfg->native_code;
4961 case OP_CALL_HANDLER:
4963 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4964 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4965 amd64_call_imm (code, 0);
4966 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4967 /* Restore stack alignment */
4968 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4970 case OP_START_HANDLER: {
4971 /* Even though we're saving RSP, use sizeof */
4972 /* gpointer because spvar is of type IntPtr */
4973 /* see: mono_create_spvar_for_region */
4974 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4975 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4977 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4978 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4980 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4984 case OP_ENDFINALLY: {
4985 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4986 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4990 case OP_ENDFILTER: {
4991 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4992 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4993 /* The local allocator will put the result into RAX */
4999 ins->inst_c0 = code - cfg->native_code;
5002 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5003 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5005 if (ins->inst_target_bb->native_offset) {
5006 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5008 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5009 if ((cfg->opt & MONO_OPT_BRANCH) &&
5010 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5011 x86_jump8 (code, 0);
5013 x86_jump32 (code, 0);
5017 amd64_jump_reg (code, ins->sreg1);
5040 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5041 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5043 case OP_COND_EXC_EQ:
5044 case OP_COND_EXC_NE_UN:
5045 case OP_COND_EXC_LT:
5046 case OP_COND_EXC_LT_UN:
5047 case OP_COND_EXC_GT:
5048 case OP_COND_EXC_GT_UN:
5049 case OP_COND_EXC_GE:
5050 case OP_COND_EXC_GE_UN:
5051 case OP_COND_EXC_LE:
5052 case OP_COND_EXC_LE_UN:
5053 case OP_COND_EXC_IEQ:
5054 case OP_COND_EXC_INE_UN:
5055 case OP_COND_EXC_ILT:
5056 case OP_COND_EXC_ILT_UN:
5057 case OP_COND_EXC_IGT:
5058 case OP_COND_EXC_IGT_UN:
5059 case OP_COND_EXC_IGE:
5060 case OP_COND_EXC_IGE_UN:
5061 case OP_COND_EXC_ILE:
5062 case OP_COND_EXC_ILE_UN:
5063 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5065 case OP_COND_EXC_OV:
5066 case OP_COND_EXC_NO:
5068 case OP_COND_EXC_NC:
5069 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5070 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5072 case OP_COND_EXC_IOV:
5073 case OP_COND_EXC_INO:
5074 case OP_COND_EXC_IC:
5075 case OP_COND_EXC_INC:
5076 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5077 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5080 /* floating point opcodes */
5082 double d = *(double *)ins->inst_p0;
5084 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5085 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5088 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5089 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5094 float f = *(float *)ins->inst_p0;
5096 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5098 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5100 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5103 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5104 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5106 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5110 case OP_STORER8_MEMBASE_REG:
5111 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5113 case OP_LOADR8_MEMBASE:
5114 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5116 case OP_STORER4_MEMBASE_REG:
5118 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5120 /* This requires a double->single conversion */
5121 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5122 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5125 case OP_LOADR4_MEMBASE:
5127 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5129 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5130 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5133 case OP_ICONV_TO_R4:
5135 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5137 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5138 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5141 case OP_ICONV_TO_R8:
5142 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5144 case OP_LCONV_TO_R4:
5146 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5148 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5149 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5152 case OP_LCONV_TO_R8:
5153 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5155 case OP_FCONV_TO_R4:
5157 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5159 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5160 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5163 case OP_FCONV_TO_I1:
5164 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5166 case OP_FCONV_TO_U1:
5167 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5169 case OP_FCONV_TO_I2:
5170 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5172 case OP_FCONV_TO_U2:
5173 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5175 case OP_FCONV_TO_U4:
5176 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5178 case OP_FCONV_TO_I4:
5180 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5182 case OP_FCONV_TO_I8:
5183 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5186 case OP_RCONV_TO_I1:
5187 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5188 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5190 case OP_RCONV_TO_U1:
5191 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5192 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5194 case OP_RCONV_TO_I2:
5195 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5196 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5198 case OP_RCONV_TO_U2:
5199 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5200 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5202 case OP_RCONV_TO_I4:
5203 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5205 case OP_RCONV_TO_U4:
5206 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5208 case OP_RCONV_TO_I8:
5209 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5211 case OP_RCONV_TO_R8:
5212 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5214 case OP_RCONV_TO_R4:
5215 if (ins->dreg != ins->sreg1)
5216 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5219 case OP_LCONV_TO_R_UN: {
5222 /* Based on gcc code */
5223 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5224 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5227 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5228 br [1] = code; x86_jump8 (code, 0);
5229 amd64_patch (br [0], code);
5232 /* Save to the red zone */
5233 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5234 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5235 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5236 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5237 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5238 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5239 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5240 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5241 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5243 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5244 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5245 amd64_patch (br [1], code);
5248 case OP_LCONV_TO_OVF_U4:
5249 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5250 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5251 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5253 case OP_LCONV_TO_OVF_I4_UN:
5254 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5255 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5256 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5259 if (ins->dreg != ins->sreg1)
5260 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5263 if (ins->dreg != ins->sreg1)
5264 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5266 case OP_MOVE_F_TO_I4:
5268 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5270 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5271 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5274 case OP_MOVE_I4_TO_F:
5275 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5277 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5279 case OP_MOVE_F_TO_I8:
5280 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5282 case OP_MOVE_I8_TO_F:
5283 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5286 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5289 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5292 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5295 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5298 static double r8_0 = -0.0;
5300 g_assert (ins->sreg1 == ins->dreg);
5302 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5303 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5307 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5310 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5313 static guint64 d = 0x7fffffffffffffffUL;
5315 g_assert (ins->sreg1 == ins->dreg);
5317 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5318 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5322 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5326 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5329 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5332 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5335 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5338 static float r4_0 = -0.0;
5340 g_assert (ins->sreg1 == ins->dreg);
5342 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5343 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5344 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5349 g_assert (cfg->opt & MONO_OPT_CMOV);
5350 g_assert (ins->dreg == ins->sreg1);
5351 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5352 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5355 g_assert (cfg->opt & MONO_OPT_CMOV);
5356 g_assert (ins->dreg == ins->sreg1);
5357 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5358 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5361 g_assert (cfg->opt & MONO_OPT_CMOV);
5362 g_assert (ins->dreg == ins->sreg1);
5363 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5364 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5367 g_assert (cfg->opt & MONO_OPT_CMOV);
5368 g_assert (ins->dreg == ins->sreg1);
5369 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5370 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5373 g_assert (cfg->opt & MONO_OPT_CMOV);
5374 g_assert (ins->dreg == ins->sreg1);
5375 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5376 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5379 g_assert (cfg->opt & MONO_OPT_CMOV);
5380 g_assert (ins->dreg == ins->sreg1);
5381 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5382 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5385 g_assert (cfg->opt & MONO_OPT_CMOV);
5386 g_assert (ins->dreg == ins->sreg1);
5387 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5388 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5391 g_assert (cfg->opt & MONO_OPT_CMOV);
5392 g_assert (ins->dreg == ins->sreg1);
5393 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5394 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5400 * The two arguments are swapped because the fbranch instructions
5401 * depend on this for the non-sse case to work.
5403 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5407 * FIXME: Get rid of this.
5408 * The two arguments are swapped because the fbranch instructions
5409 * depend on this for the non-sse case to work.
5411 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5415 /* zeroing the register at the start results in
5416 * shorter and faster code (we can also remove the widening op)
5418 guchar *unordered_check;
5420 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5421 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5422 unordered_check = code;
5423 x86_branch8 (code, X86_CC_P, 0, FALSE);
5425 if (ins->opcode == OP_FCEQ) {
5426 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5427 amd64_patch (unordered_check, code);
5429 guchar *jump_to_end;
5430 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5432 x86_jump8 (code, 0);
5433 amd64_patch (unordered_check, code);
5434 amd64_inc_reg (code, ins->dreg);
5435 amd64_patch (jump_to_end, code);
5441 /* zeroing the register at the start results in
5442 * shorter and faster code (we can also remove the widening op)
5444 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5445 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5446 if (ins->opcode == OP_FCLT_UN) {
5447 guchar *unordered_check = code;
5448 guchar *jump_to_end;
5449 x86_branch8 (code, X86_CC_P, 0, FALSE);
5450 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5452 x86_jump8 (code, 0);
5453 amd64_patch (unordered_check, code);
5454 amd64_inc_reg (code, ins->dreg);
5455 amd64_patch (jump_to_end, code);
5457 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5462 guchar *unordered_check;
5463 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5464 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5465 unordered_check = code;
5466 x86_branch8 (code, X86_CC_P, 0, FALSE);
5467 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5468 amd64_patch (unordered_check, code);
5473 /* zeroing the register at the start results in
5474 * shorter and faster code (we can also remove the widening op)
5476 guchar *unordered_check;
5478 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5479 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5480 if (ins->opcode == OP_FCGT) {
5481 unordered_check = code;
5482 x86_branch8 (code, X86_CC_P, 0, FALSE);
5483 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5484 amd64_patch (unordered_check, code);
5486 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5491 guchar *unordered_check;
5492 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5493 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5494 unordered_check = code;
5495 x86_branch8 (code, X86_CC_P, 0, FALSE);
5496 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5497 amd64_patch (unordered_check, code);
5507 gboolean unordered = FALSE;
5509 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5510 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5512 switch (ins->opcode) {
5514 x86_cond = X86_CC_EQ;
5517 x86_cond = X86_CC_LT;
5520 x86_cond = X86_CC_GT;
5523 x86_cond = X86_CC_GT;
5527 x86_cond = X86_CC_LT;
5531 g_assert_not_reached ();
5536 guchar *unordered_check;
5537 guchar *jump_to_end;
5539 unordered_check = code;
5540 x86_branch8 (code, X86_CC_P, 0, FALSE);
5541 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5543 x86_jump8 (code, 0);
5544 amd64_patch (unordered_check, code);
5545 amd64_inc_reg (code, ins->dreg);
5546 amd64_patch (jump_to_end, code);
5548 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5552 case OP_FCLT_MEMBASE:
5553 case OP_FCGT_MEMBASE:
5554 case OP_FCLT_UN_MEMBASE:
5555 case OP_FCGT_UN_MEMBASE:
5556 case OP_FCEQ_MEMBASE: {
5557 guchar *unordered_check, *jump_to_end;
5560 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5561 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5563 switch (ins->opcode) {
5564 case OP_FCEQ_MEMBASE:
5565 x86_cond = X86_CC_EQ;
5567 case OP_FCLT_MEMBASE:
5568 case OP_FCLT_UN_MEMBASE:
5569 x86_cond = X86_CC_LT;
5571 case OP_FCGT_MEMBASE:
5572 case OP_FCGT_UN_MEMBASE:
5573 x86_cond = X86_CC_GT;
5576 g_assert_not_reached ();
5579 unordered_check = code;
5580 x86_branch8 (code, X86_CC_P, 0, FALSE);
5581 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5583 switch (ins->opcode) {
5584 case OP_FCEQ_MEMBASE:
5585 case OP_FCLT_MEMBASE:
5586 case OP_FCGT_MEMBASE:
5587 amd64_patch (unordered_check, code);
5589 case OP_FCLT_UN_MEMBASE:
5590 case OP_FCGT_UN_MEMBASE:
5592 x86_jump8 (code, 0);
5593 amd64_patch (unordered_check, code);
5594 amd64_inc_reg (code, ins->dreg);
5595 amd64_patch (jump_to_end, code);
5603 guchar *jump = code;
5604 x86_branch8 (code, X86_CC_P, 0, TRUE);
5605 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5606 amd64_patch (jump, code);
5610 /* Branch if C013 != 100 */
5611 /* branch if !ZF or (PF|CF) */
5612 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5613 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5614 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5617 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5620 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5621 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5625 if (ins->opcode == OP_FBGT) {
5628 /* skip branch if C1=1 */
5630 x86_branch8 (code, X86_CC_P, 0, FALSE);
5631 /* branch if (C0 | C3) = 1 */
5632 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5633 amd64_patch (br1, code);
5636 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5640 /* Branch if C013 == 100 or 001 */
5643 /* skip branch if C1=1 */
5645 x86_branch8 (code, X86_CC_P, 0, FALSE);
5646 /* branch if (C0 | C3) = 1 */
5647 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5648 amd64_patch (br1, code);
5652 /* Branch if C013 == 000 */
5653 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5656 /* Branch if C013=000 or 100 */
5659 /* skip branch if C1=1 */
5661 x86_branch8 (code, X86_CC_P, 0, FALSE);
5662 /* branch if C0=0 */
5663 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5664 amd64_patch (br1, code);
5668 /* Branch if C013 != 001 */
5669 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5670 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5673 /* Transfer value to the fp stack */
5674 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5675 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5676 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5678 amd64_push_reg (code, AMD64_RAX);
5680 amd64_fnstsw (code);
5681 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5682 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5683 amd64_pop_reg (code, AMD64_RAX);
5684 amd64_fstp (code, 0);
5685 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5686 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5689 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5692 case OP_TLS_GET_REG:
5693 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5696 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5699 case OP_TLS_SET_REG: {
5700 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5703 case OP_MEMORY_BARRIER: {
5704 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5708 case OP_ATOMIC_ADD_I4:
5709 case OP_ATOMIC_ADD_I8: {
5710 int dreg = ins->dreg;
5711 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5713 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5716 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5717 amd64_prefix (code, X86_LOCK_PREFIX);
5718 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5719 /* dreg contains the old value, add with sreg2 value */
5720 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5722 if (ins->dreg != dreg)
5723 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5727 case OP_ATOMIC_EXCHANGE_I4:
5728 case OP_ATOMIC_EXCHANGE_I8: {
5729 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5731 /* LOCK prefix is implied. */
5732 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5733 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5734 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5737 case OP_ATOMIC_CAS_I4:
5738 case OP_ATOMIC_CAS_I8: {
5741 if (ins->opcode == OP_ATOMIC_CAS_I8)
5747 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5748 * an explanation of how this works.
5750 g_assert (ins->sreg3 == AMD64_RAX);
5751 g_assert (ins->sreg1 != AMD64_RAX);
5752 g_assert (ins->sreg1 != ins->sreg2);
5754 amd64_prefix (code, X86_LOCK_PREFIX);
5755 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5757 if (ins->dreg != AMD64_RAX)
5758 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5761 case OP_ATOMIC_LOAD_I1: {
5762 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5765 case OP_ATOMIC_LOAD_U1: {
5766 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5769 case OP_ATOMIC_LOAD_I2: {
5770 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5773 case OP_ATOMIC_LOAD_U2: {
5774 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5777 case OP_ATOMIC_LOAD_I4: {
5778 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5781 case OP_ATOMIC_LOAD_U4:
5782 case OP_ATOMIC_LOAD_I8:
5783 case OP_ATOMIC_LOAD_U8: {
5784 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5787 case OP_ATOMIC_LOAD_R4: {
5788 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5789 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5792 case OP_ATOMIC_LOAD_R8: {
5793 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5796 case OP_ATOMIC_STORE_I1:
5797 case OP_ATOMIC_STORE_U1:
5798 case OP_ATOMIC_STORE_I2:
5799 case OP_ATOMIC_STORE_U2:
5800 case OP_ATOMIC_STORE_I4:
5801 case OP_ATOMIC_STORE_U4:
5802 case OP_ATOMIC_STORE_I8:
5803 case OP_ATOMIC_STORE_U8: {
5806 switch (ins->opcode) {
5807 case OP_ATOMIC_STORE_I1:
5808 case OP_ATOMIC_STORE_U1:
5811 case OP_ATOMIC_STORE_I2:
5812 case OP_ATOMIC_STORE_U2:
5815 case OP_ATOMIC_STORE_I4:
5816 case OP_ATOMIC_STORE_U4:
5819 case OP_ATOMIC_STORE_I8:
5820 case OP_ATOMIC_STORE_U8:
5825 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5827 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5831 case OP_ATOMIC_STORE_R4: {
5832 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5833 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5835 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5839 case OP_ATOMIC_STORE_R8: {
5842 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5846 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5850 case OP_CARD_TABLE_WBARRIER: {
5851 int ptr = ins->sreg1;
5852 int value = ins->sreg2;
5854 int nursery_shift, card_table_shift;
5855 gpointer card_table_mask;
5856 size_t nursery_size;
5858 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5859 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5860 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5862 /*If either point to the stack we can simply avoid the WB. This happens due to
5863 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5865 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5869 * We need one register we can clobber, we choose EDX and make sreg1
5870 * fixed EAX to work around limitations in the local register allocator.
5871 * sreg2 might get allocated to EDX, but that is not a problem since
5872 * we use it before clobbering EDX.
5874 g_assert (ins->sreg1 == AMD64_RAX);
5877 * This is the code we produce:
5880 * edx >>= nursery_shift
5881 * cmp edx, (nursery_start >> nursery_shift)
5884 * edx >>= card_table_shift
5890 if (mono_gc_card_table_nursery_check ()) {
5891 if (value != AMD64_RDX)
5892 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5893 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5894 if (shifted_nursery_start >> 31) {
5896 * The value we need to compare against is 64 bits, so we need
5897 * another spare register. We use RBX, which we save and
5900 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5901 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5902 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5903 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5905 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5907 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5909 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5910 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5911 if (card_table_mask)
5912 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5914 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5915 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5917 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5919 if (mono_gc_card_table_nursery_check ())
5920 x86_patch (br, code);
5923 #ifdef MONO_ARCH_SIMD_INTRINSICS
5924 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5926 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5929 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5932 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5935 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5938 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5941 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5944 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5945 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5948 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5951 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5954 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5963 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5966 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5969 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5972 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5978 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5981 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5984 case OP_PSHUFLEW_HIGH:
5985 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5986 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5988 case OP_PSHUFLEW_LOW:
5989 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5990 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5993 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5994 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5997 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5998 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6001 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6002 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6006 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6025 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6028 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6031 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6034 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6037 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6040 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6043 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6046 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6049 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6052 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6055 case OP_EXTRACT_MASK:
6056 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6060 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6063 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6066 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6070 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6073 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6076 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6079 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6083 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6086 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6089 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6092 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6096 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6099 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6102 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6106 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6112 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6119 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6123 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6126 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6129 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6133 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6139 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6143 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6146 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6149 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6152 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6156 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6159 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6162 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6165 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6168 case OP_PSUM_ABS_DIFF:
6169 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6172 case OP_UNPACK_LOWB:
6173 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6175 case OP_UNPACK_LOWW:
6176 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6178 case OP_UNPACK_LOWD:
6179 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6181 case OP_UNPACK_LOWQ:
6182 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6184 case OP_UNPACK_LOWPS:
6185 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6187 case OP_UNPACK_LOWPD:
6188 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6191 case OP_UNPACK_HIGHB:
6192 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6194 case OP_UNPACK_HIGHW:
6195 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6197 case OP_UNPACK_HIGHD:
6198 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6200 case OP_UNPACK_HIGHQ:
6201 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6203 case OP_UNPACK_HIGHPS:
6204 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6206 case OP_UNPACK_HIGHPD:
6207 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6211 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6214 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6217 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6220 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6223 case OP_PADDB_SAT_UN:
6224 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6226 case OP_PSUBB_SAT_UN:
6227 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6229 case OP_PADDW_SAT_UN:
6230 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6232 case OP_PSUBW_SAT_UN:
6233 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6237 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6240 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6243 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6246 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6250 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6253 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6256 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6258 case OP_PMULW_HIGH_UN:
6259 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6262 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6266 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6269 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6273 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6276 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6280 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6283 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6287 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6290 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6294 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6297 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6301 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6304 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6308 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6311 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6314 /*TODO: This is appart of the sse spec but not added
6316 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6319 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6324 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6327 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6330 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6333 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6336 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6339 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6342 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6345 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6348 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6351 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6355 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6358 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6362 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6363 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6365 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6370 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6372 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6373 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6377 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6379 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6380 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6381 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6385 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6387 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6390 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6392 case OP_EXTRACTX_U2:
6393 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6395 case OP_INSERTX_U1_SLOW:
6396 /*sreg1 is the extracted ireg (scratch)
6397 /sreg2 is the to be inserted ireg (scratch)
6398 /dreg is the xreg to receive the value*/
6400 /*clear the bits from the extracted word*/
6401 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6402 /*shift the value to insert if needed*/
6403 if (ins->inst_c0 & 1)
6404 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6405 /*join them together*/
6406 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6407 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6409 case OP_INSERTX_I4_SLOW:
6410 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6411 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6412 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6414 case OP_INSERTX_I8_SLOW:
6415 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6417 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6419 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6422 case OP_INSERTX_R4_SLOW:
6423 switch (ins->inst_c0) {
6426 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6428 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6431 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6433 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6435 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6436 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6439 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6441 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6443 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6444 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6447 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6449 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6451 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6452 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6456 case OP_INSERTX_R8_SLOW:
6458 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6460 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6462 case OP_STOREX_MEMBASE_REG:
6463 case OP_STOREX_MEMBASE:
6464 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6466 case OP_LOADX_MEMBASE:
6467 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6469 case OP_LOADX_ALIGNED_MEMBASE:
6470 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6472 case OP_STOREX_ALIGNED_MEMBASE_REG:
6473 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6475 case OP_STOREX_NTA_MEMBASE_REG:
6476 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6478 case OP_PREFETCH_MEMBASE:
6479 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6483 /*FIXME the peephole pass should have killed this*/
6484 if (ins->dreg != ins->sreg1)
6485 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6488 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6490 case OP_ICONV_TO_R4_RAW:
6491 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6494 case OP_FCONV_TO_R8_X:
6495 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6498 case OP_XCONV_R8_TO_I4:
6499 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6500 switch (ins->backend.source_opcode) {
6501 case OP_FCONV_TO_I1:
6502 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6504 case OP_FCONV_TO_U1:
6505 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6507 case OP_FCONV_TO_I2:
6508 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6510 case OP_FCONV_TO_U2:
6511 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6517 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6518 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6519 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6522 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6523 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6526 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6527 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6531 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6533 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6534 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6536 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6539 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6540 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6543 case OP_LIVERANGE_START: {
6544 if (cfg->verbose_level > 1)
6545 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6546 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6549 case OP_LIVERANGE_END: {
6550 if (cfg->verbose_level > 1)
6551 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6552 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6555 case OP_NACL_GC_SAFE_POINT: {
6556 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6557 if (cfg->compile_aot)
6558 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6562 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6563 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6564 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6565 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6566 amd64_patch (br[0], code);
6571 case OP_GC_LIVENESS_DEF:
6572 case OP_GC_LIVENESS_USE:
6573 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6574 ins->backend.pc_offset = code - cfg->native_code;
6576 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6577 ins->backend.pc_offset = code - cfg->native_code;
6578 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6581 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6582 g_assert_not_reached ();
6585 if ((code - cfg->native_code - offset) > max_len) {
6586 #if !defined(__native_client_codegen__)
6587 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6588 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6589 g_assert_not_reached ();
6594 cfg->code_len = code - cfg->native_code;
6597 #endif /* DISABLE_JIT */
6600 mono_arch_register_lowlevel_calls (void)
6602 /* The signature doesn't matter */
6603 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6607 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6609 MonoJumpInfo *patch_info;
6610 gboolean compile_aot = !run_cctors;
6612 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6613 unsigned char *ip = patch_info->ip.i + code;
6614 unsigned char *target;
6617 switch (patch_info->type) {
6618 case MONO_PATCH_INFO_BB:
6619 case MONO_PATCH_INFO_LABEL:
6622 /* No need to patch these */
6627 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6629 switch (patch_info->type) {
6630 case MONO_PATCH_INFO_NONE:
6632 case MONO_PATCH_INFO_METHOD_REL:
6633 case MONO_PATCH_INFO_R8:
6634 case MONO_PATCH_INFO_R4:
6635 g_assert_not_reached ();
6637 case MONO_PATCH_INFO_BB:
6644 * Debug code to help track down problems where the target of a near call is
6647 if (amd64_is_near_call (ip)) {
6648 gint64 disp = (guint8*)target - (guint8*)ip;
6650 if (!amd64_is_imm32 (disp)) {
6651 printf ("TYPE: %d\n", patch_info->type);
6652 switch (patch_info->type) {
6653 case MONO_PATCH_INFO_INTERNAL_METHOD:
6654 printf ("V: %s\n", patch_info->data.name);
6656 case MONO_PATCH_INFO_METHOD_JUMP:
6657 case MONO_PATCH_INFO_METHOD:
6658 printf ("V: %s\n", patch_info->data.method->name);
6666 amd64_patch (ip, (gpointer)target);
6673 get_max_epilog_size (MonoCompile *cfg)
6675 int max_epilog_size = 16;
6677 if (cfg->method->save_lmf)
6678 max_epilog_size += 256;
6680 if (mono_jit_trace_calls != NULL)
6681 max_epilog_size += 50;
6683 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6684 max_epilog_size += 50;
6686 max_epilog_size += (AMD64_NREG * 2);
6688 return max_epilog_size;
6692 * This macro is used for testing whenever the unwinder works correctly at every point
6693 * where an async exception can happen.
6695 /* This will generate a SIGSEGV at the given point in the code */
6696 #define async_exc_point(code) do { \
6697 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6698 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6699 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6700 cfg->arch.async_point_count ++; \
6705 mono_arch_emit_prolog (MonoCompile *cfg)
6707 MonoMethod *method = cfg->method;
6709 MonoMethodSignature *sig;
6711 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6714 MonoInst *lmf_var = cfg->lmf_var;
6715 gboolean args_clobbered = FALSE;
6716 gboolean trace = FALSE;
6717 #ifdef __native_client_codegen__
6718 guint alignment_check;
6721 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6723 #if defined(__default_codegen__)
6724 code = cfg->native_code = g_malloc (cfg->code_size);
6725 #elif defined(__native_client_codegen__)
6726 /* native_code_alloc is not 32-byte aligned, native_code is. */
6727 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6729 /* Align native_code to next nearest kNaclAlignment byte. */
6730 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6731 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6733 code = cfg->native_code;
6735 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6736 g_assert (alignment_check == 0);
6739 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6742 /* Amount of stack space allocated by register saving code */
6745 /* Offset between RSP and the CFA */
6749 * The prolog consists of the following parts:
6751 * - push rbp, mov rbp, rsp
6752 * - save callee saved regs using pushes
6754 * - save rgctx if needed
6755 * - save lmf if needed
6758 * - save rgctx if needed
6759 * - save lmf if needed
6760 * - save callee saved regs using moves
6765 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6766 // IP saved at CFA - 8
6767 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6768 async_exc_point (code);
6769 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6771 if (!cfg->arch.omit_fp) {
6772 amd64_push_reg (code, AMD64_RBP);
6774 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6775 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6776 async_exc_point (code);
6778 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6780 /* These are handled automatically by the stack marking code */
6781 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6783 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6784 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6785 async_exc_point (code);
6787 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6791 /* The param area is always at offset 0 from sp */
6792 /* This needs to be allocated here, since it has to come after the spill area */
6793 if (cfg->param_area) {
6794 if (cfg->arch.omit_fp)
6796 g_assert_not_reached ();
6797 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6800 if (cfg->arch.omit_fp) {
6802 * On enter, the stack is misaligned by the pushing of the return
6803 * address. It is either made aligned by the pushing of %rbp, or by
6806 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6807 if ((alloc_size % 16) == 0) {
6809 /* Mark the padding slot as NOREF */
6810 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6813 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6814 if (cfg->stack_offset != alloc_size) {
6815 /* Mark the padding slot as NOREF */
6816 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6818 cfg->arch.sp_fp_offset = alloc_size;
6822 cfg->arch.stack_alloc_size = alloc_size;
6824 /* Allocate stack frame */
6826 /* See mono_emit_stack_alloc */
6827 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6828 guint32 remaining_size = alloc_size;
6829 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6830 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6831 guint32 offset = code - cfg->native_code;
6832 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6833 while (required_code_size >= (cfg->code_size - offset))
6834 cfg->code_size *= 2;
6835 cfg->native_code = mono_realloc_native_code (cfg);
6836 code = cfg->native_code + offset;
6837 cfg->stat_code_reallocs++;
6840 while (remaining_size >= 0x1000) {
6841 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6842 if (cfg->arch.omit_fp) {
6843 cfa_offset += 0x1000;
6844 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6846 async_exc_point (code);
6848 if (cfg->arch.omit_fp)
6849 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6852 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6853 remaining_size -= 0x1000;
6855 if (remaining_size) {
6856 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6857 if (cfg->arch.omit_fp) {
6858 cfa_offset += remaining_size;
6859 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6860 async_exc_point (code);
6863 if (cfg->arch.omit_fp)
6864 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6868 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6869 if (cfg->arch.omit_fp) {
6870 cfa_offset += alloc_size;
6871 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6872 async_exc_point (code);
6877 /* Stack alignment check */
6880 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6881 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6882 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6883 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6884 amd64_breakpoint (code);
6888 if (mini_get_debug_options ()->init_stacks) {
6889 /* Fill the stack frame with a dummy value to force deterministic behavior */
6891 /* Save registers to the red zone */
6892 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6893 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6895 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6896 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6897 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6900 #if defined(__default_codegen__)
6901 amd64_prefix (code, X86_REP_PREFIX);
6903 #elif defined(__native_client_codegen__)
6904 /* NaCl stos pseudo-instruction */
6905 amd64_codegen_pre (code);
6906 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6907 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6908 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6909 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6910 amd64_prefix (code, X86_REP_PREFIX);
6912 amd64_codegen_post (code);
6913 #endif /* __native_client_codegen__ */
6915 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6916 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6920 if (method->save_lmf)
6921 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6923 /* Save callee saved registers */
6924 if (cfg->arch.omit_fp) {
6925 save_area_offset = cfg->arch.reg_save_area_offset;
6926 /* Save caller saved registers after sp is adjusted */
6927 /* The registers are saved at the bottom of the frame */
6928 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6930 /* The registers are saved just below the saved rbp */
6931 save_area_offset = cfg->arch.reg_save_area_offset;
6934 for (i = 0; i < AMD64_NREG; ++i) {
6935 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6936 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6938 if (cfg->arch.omit_fp) {
6939 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6940 /* These are handled automatically by the stack marking code */
6941 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6943 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6947 save_area_offset += 8;
6948 async_exc_point (code);
6952 /* store runtime generic context */
6953 if (cfg->rgctx_var) {
6954 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6955 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6957 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6959 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6960 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6963 /* compute max_length in order to use short forward jumps */
6964 max_epilog_size = get_max_epilog_size (cfg);
6965 if (cfg->opt & MONO_OPT_BRANCH) {
6966 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6970 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6972 /* max alignment for loops */
6973 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6974 max_length += LOOP_ALIGNMENT;
6975 #ifdef __native_client_codegen__
6976 /* max alignment for native client */
6977 max_length += kNaClAlignment;
6980 MONO_BB_FOR_EACH_INS (bb, ins) {
6981 #ifdef __native_client_codegen__
6983 int space_in_block = kNaClAlignment -
6984 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6985 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6986 if (space_in_block < max_len && max_len < kNaClAlignment) {
6987 max_length += space_in_block;
6990 #endif /*__native_client_codegen__*/
6991 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6994 /* Take prolog and epilog instrumentation into account */
6995 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6996 max_length += max_epilog_size;
6998 bb->max_length = max_length;
7002 sig = mono_method_signature (method);
7005 cinfo = cfg->arch.cinfo;
7007 if (sig->ret->type != MONO_TYPE_VOID) {
7008 /* Save volatile arguments to the stack */
7009 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7010 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7013 /* Keep this in sync with emit_load_volatile_arguments */
7014 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7015 ArgInfo *ainfo = cinfo->args + i;
7017 ins = cfg->args [i];
7019 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7020 /* Unused arguments */
7023 if (cfg->globalra) {
7024 /* All the other moves are done by the register allocator */
7025 switch (ainfo->storage) {
7026 case ArgInFloatSSEReg:
7027 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7029 case ArgValuetypeInReg:
7030 for (quad = 0; quad < 2; quad ++) {
7031 switch (ainfo->pair_storage [quad]) {
7033 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7035 case ArgInFloatSSEReg:
7036 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7038 case ArgInDoubleSSEReg:
7039 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7044 g_assert_not_reached ();
7055 /* Save volatile arguments to the stack */
7056 if (ins->opcode != OP_REGVAR) {
7057 switch (ainfo->storage) {
7063 if (stack_offset & 0x1)
7065 else if (stack_offset & 0x2)
7067 else if (stack_offset & 0x4)
7072 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7075 * Save the original location of 'this',
7076 * get_generic_info_from_stack_frame () needs this to properly look up
7077 * the argument value during the handling of async exceptions.
7079 if (ins == cfg->args [0]) {
7080 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7081 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7085 case ArgInFloatSSEReg:
7086 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7088 case ArgInDoubleSSEReg:
7089 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7091 case ArgValuetypeInReg:
7092 for (quad = 0; quad < 2; quad ++) {
7093 switch (ainfo->pair_storage [quad]) {
7095 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7097 case ArgInFloatSSEReg:
7098 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7100 case ArgInDoubleSSEReg:
7101 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7106 g_assert_not_reached ();
7110 case ArgValuetypeAddrInIReg:
7111 if (ainfo->pair_storage [0] == ArgInIReg)
7112 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7118 /* Argument allocated to (non-volatile) register */
7119 switch (ainfo->storage) {
7121 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7124 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7127 g_assert_not_reached ();
7130 if (ins == cfg->args [0]) {
7131 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7132 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7137 if (cfg->method->save_lmf)
7138 args_clobbered = TRUE;
7141 args_clobbered = TRUE;
7142 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7145 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7146 args_clobbered = TRUE;
7149 * Optimize the common case of the first bblock making a call with the same
7150 * arguments as the method. This works because the arguments are still in their
7151 * original argument registers.
7152 * FIXME: Generalize this
7154 if (!args_clobbered) {
7155 MonoBasicBlock *first_bb = cfg->bb_entry;
7157 int filter = FILTER_IL_SEQ_POINT;
7159 next = mono_bb_first_inst (first_bb, filter);
7160 if (!next && first_bb->next_bb) {
7161 first_bb = first_bb->next_bb;
7162 next = mono_bb_first_inst (first_bb, filter);
7165 if (first_bb->in_count > 1)
7168 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7169 ArgInfo *ainfo = cinfo->args + i;
7170 gboolean match = FALSE;
7172 ins = cfg->args [i];
7173 if (ins->opcode != OP_REGVAR) {
7174 switch (ainfo->storage) {
7176 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7177 if (next->dreg == ainfo->reg) {
7181 next->opcode = OP_MOVE;
7182 next->sreg1 = ainfo->reg;
7183 /* Only continue if the instruction doesn't change argument regs */
7184 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7194 /* Argument allocated to (non-volatile) register */
7195 switch (ainfo->storage) {
7197 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7208 next = mono_inst_next (next, filter);
7209 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7216 if (cfg->gen_seq_points_debug_data) {
7217 MonoInst *info_var = cfg->arch.seq_point_info_var;
7219 /* Initialize seq_point_info_var */
7220 if (cfg->compile_aot) {
7221 /* Initialize the variable from a GOT slot */
7222 /* Same as OP_AOTCONST */
7223 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7224 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7225 g_assert (info_var->opcode == OP_REGOFFSET);
7226 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7229 if (cfg->compile_aot) {
7230 /* Initialize ss_tramp_var */
7231 ins = cfg->arch.ss_tramp_var;
7232 g_assert (ins->opcode == OP_REGOFFSET);
7234 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7235 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7236 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7238 /* Initialize ss_trigger_page_var */
7239 ins = cfg->arch.ss_trigger_page_var;
7241 g_assert (ins->opcode == OP_REGOFFSET);
7243 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7244 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7248 cfg->code_len = code - cfg->native_code;
7250 g_assert (cfg->code_len < cfg->code_size);
7256 mono_arch_emit_epilog (MonoCompile *cfg)
7258 MonoMethod *method = cfg->method;
7261 int max_epilog_size;
7263 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7264 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7266 max_epilog_size = get_max_epilog_size (cfg);
7268 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7269 cfg->code_size *= 2;
7270 cfg->native_code = mono_realloc_native_code (cfg);
7271 cfg->stat_code_reallocs++;
7273 code = cfg->native_code + cfg->code_len;
7275 cfg->has_unwind_info_for_epilog = TRUE;
7277 /* Mark the start of the epilog */
7278 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7280 /* Save the uwind state which is needed by the out-of-line code */
7281 mono_emit_unwind_op_remember_state (cfg, code);
7283 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7284 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7286 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7288 if (method->save_lmf) {
7289 /* check if we need to restore protection of the stack after a stack overflow */
7290 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7292 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7293 /* we load the value in a separate instruction: this mechanism may be
7294 * used later as a safer way to do thread interruption
7296 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7297 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7299 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7300 /* note that the call trampoline will preserve eax/edx */
7301 x86_call_reg (code, X86_ECX);
7302 x86_patch (patch, code);
7304 /* FIXME: maybe save the jit tls in the prolog */
7306 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7307 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7311 /* Restore callee saved regs */
7312 for (i = 0; i < AMD64_NREG; ++i) {
7313 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7314 /* Restore only used_int_regs, not arch.saved_iregs */
7315 if (cfg->used_int_regs & (1 << i)) {
7316 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7317 mono_emit_unwind_op_same_value (cfg, code, i);
7318 async_exc_point (code);
7320 save_area_offset += 8;
7324 /* Load returned vtypes into registers if needed */
7325 cinfo = cfg->arch.cinfo;
7326 if (cinfo->ret.storage == ArgValuetypeInReg) {
7327 ArgInfo *ainfo = &cinfo->ret;
7328 MonoInst *inst = cfg->ret;
7330 for (quad = 0; quad < 2; quad ++) {
7331 switch (ainfo->pair_storage [quad]) {
7333 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7335 case ArgInFloatSSEReg:
7336 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7338 case ArgInDoubleSSEReg:
7339 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7344 g_assert_not_reached ();
7349 if (cfg->arch.omit_fp) {
7350 if (cfg->arch.stack_alloc_size) {
7351 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7355 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7357 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7358 async_exc_point (code);
7361 /* Restore the unwind state to be the same as before the epilog */
7362 mono_emit_unwind_op_restore_state (cfg, code);
7364 cfg->code_len = code - cfg->native_code;
7366 g_assert (cfg->code_len < cfg->code_size);
7370 mono_arch_emit_exceptions (MonoCompile *cfg)
7372 MonoJumpInfo *patch_info;
7375 MonoClass *exc_classes [16];
7376 guint8 *exc_throw_start [16], *exc_throw_end [16];
7377 guint32 code_size = 0;
7379 /* Compute needed space */
7380 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7381 if (patch_info->type == MONO_PATCH_INFO_EXC)
7383 if (patch_info->type == MONO_PATCH_INFO_R8)
7384 code_size += 8 + 15; /* sizeof (double) + alignment */
7385 if (patch_info->type == MONO_PATCH_INFO_R4)
7386 code_size += 4 + 15; /* sizeof (float) + alignment */
7387 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7388 code_size += 8 + 7; /*sizeof (void*) + alignment */
7391 #ifdef __native_client_codegen__
7392 /* Give us extra room on Native Client. This could be */
7393 /* more carefully calculated, but bundle alignment makes */
7394 /* it much trickier, so *2 like other places is good. */
7398 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7399 cfg->code_size *= 2;
7400 cfg->native_code = mono_realloc_native_code (cfg);
7401 cfg->stat_code_reallocs++;
7404 code = cfg->native_code + cfg->code_len;
7406 /* add code to raise exceptions */
7408 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7409 switch (patch_info->type) {
7410 case MONO_PATCH_INFO_EXC: {
7411 MonoClass *exc_class;
7415 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7417 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7418 g_assert (exc_class);
7419 throw_ip = patch_info->ip.i;
7421 //x86_breakpoint (code);
7422 /* Find a throw sequence for the same exception class */
7423 for (i = 0; i < nthrows; ++i)
7424 if (exc_classes [i] == exc_class)
7427 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7428 x86_jump_code (code, exc_throw_start [i]);
7429 patch_info->type = MONO_PATCH_INFO_NONE;
7433 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7437 exc_classes [nthrows] = exc_class;
7438 exc_throw_start [nthrows] = code;
7440 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7442 patch_info->type = MONO_PATCH_INFO_NONE;
7444 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7446 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7451 exc_throw_end [nthrows] = code;
7461 g_assert(code < cfg->native_code + cfg->code_size);
7464 /* Handle relocations with RIP relative addressing */
7465 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7466 gboolean remove = FALSE;
7467 guint8 *orig_code = code;
7469 switch (patch_info->type) {
7470 case MONO_PATCH_INFO_R8:
7471 case MONO_PATCH_INFO_R4: {
7472 guint8 *pos, *patch_pos;
7475 /* The SSE opcodes require a 16 byte alignment */
7476 #if defined(__default_codegen__)
7477 code = (guint8*)ALIGN_TO (code, 16);
7478 #elif defined(__native_client_codegen__)
7480 /* Pad this out with HLT instructions */
7481 /* or we can get garbage bytes emitted */
7482 /* which will fail validation */
7483 guint8 *aligned_code;
7484 /* extra align to make room for */
7485 /* mov/push below */
7486 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7487 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7488 /* The technique of hiding data in an */
7489 /* instruction has a problem here: we */
7490 /* need the data aligned to a 16-byte */
7491 /* boundary but the instruction cannot */
7492 /* cross the bundle boundary. so only */
7493 /* odd multiples of 16 can be used */
7494 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7497 while (code < aligned_code) {
7498 *(code++) = 0xf4; /* hlt */
7503 pos = cfg->native_code + patch_info->ip.i;
7504 if (IS_REX (pos [1])) {
7505 patch_pos = pos + 5;
7506 target_pos = code - pos - 9;
7509 patch_pos = pos + 4;
7510 target_pos = code - pos - 8;
7513 if (patch_info->type == MONO_PATCH_INFO_R8) {
7514 #ifdef __native_client_codegen__
7515 /* Hide 64-bit data in a */
7516 /* "mov imm64, r11" instruction. */
7517 /* write it before the start of */
7519 *(code-2) = 0x49; /* prefix */
7520 *(code-1) = 0xbb; /* mov X, %r11 */
7522 *(double*)code = *(double*)patch_info->data.target;
7523 code += sizeof (double);
7525 #ifdef __native_client_codegen__
7526 /* Hide 32-bit data in a */
7527 /* "push imm32" instruction. */
7528 *(code-1) = 0x68; /* push */
7530 *(float*)code = *(float*)patch_info->data.target;
7531 code += sizeof (float);
7534 *(guint32*)(patch_pos) = target_pos;
7539 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7542 if (cfg->compile_aot)
7545 /*loading is faster against aligned addresses.*/
7546 code = (guint8*)ALIGN_TO (code, 8);
7547 memset (orig_code, 0, code - orig_code);
7549 pos = cfg->native_code + patch_info->ip.i;
7551 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7552 if (IS_REX (pos [1]))
7553 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7555 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7557 *(gpointer*)code = (gpointer)patch_info->data.target;
7558 code += sizeof (gpointer);
7568 if (patch_info == cfg->patch_info)
7569 cfg->patch_info = patch_info->next;
7573 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7575 tmp->next = patch_info->next;
7578 g_assert (code < cfg->native_code + cfg->code_size);
7581 cfg->code_len = code - cfg->native_code;
7583 g_assert (cfg->code_len < cfg->code_size);
7587 #endif /* DISABLE_JIT */
7590 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7593 MonoMethodSignature *sig;
7595 int i, n, stack_area = 0;
7597 /* Keep this in sync with mono_arch_get_argument_info */
7599 if (enable_arguments) {
7600 /* Allocate a new area on the stack and save arguments there */
7601 sig = mono_method_signature (cfg->method);
7603 n = sig->param_count + sig->hasthis;
7605 stack_area = ALIGN_TO (n * 8, 16);
7607 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7609 for (i = 0; i < n; ++i) {
7610 inst = cfg->args [i];
7612 if (inst->opcode == OP_REGVAR)
7613 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7615 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7616 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7621 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7622 amd64_set_reg_template (code, AMD64_ARG_REG1);
7623 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7624 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7626 if (enable_arguments)
7627 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7641 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7644 int save_mode = SAVE_NONE;
7645 MonoMethod *method = cfg->method;
7646 MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7649 switch (ret_type->type) {
7650 case MONO_TYPE_VOID:
7651 /* special case string .ctor icall */
7652 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7653 save_mode = SAVE_EAX;
7655 save_mode = SAVE_NONE;
7659 save_mode = SAVE_EAX;
7663 save_mode = SAVE_XMM;
7665 case MONO_TYPE_GENERICINST:
7666 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7667 save_mode = SAVE_EAX;
7671 case MONO_TYPE_VALUETYPE:
7672 save_mode = SAVE_STRUCT;
7675 save_mode = SAVE_EAX;
7679 /* Save the result and copy it into the proper argument register */
7680 switch (save_mode) {
7682 amd64_push_reg (code, AMD64_RAX);
7684 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7685 if (enable_arguments)
7686 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7690 if (enable_arguments)
7691 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7694 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7695 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7697 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7699 * The result is already in the proper argument register so no copying
7706 g_assert_not_reached ();
7709 /* Set %al since this is a varargs call */
7710 if (save_mode == SAVE_XMM)
7711 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7713 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7715 if (preserve_argument_registers) {
7716 for (i = 0; i < PARAM_REGS; ++i)
7717 amd64_push_reg (code, param_regs [i]);
7720 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7721 amd64_set_reg_template (code, AMD64_ARG_REG1);
7722 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7724 if (preserve_argument_registers) {
7725 for (i = PARAM_REGS - 1; i >= 0; --i)
7726 amd64_pop_reg (code, param_regs [i]);
7729 /* Restore result */
7730 switch (save_mode) {
7732 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7733 amd64_pop_reg (code, AMD64_RAX);
7739 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7740 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7741 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7746 g_assert_not_reached ();
7753 mono_arch_flush_icache (guint8 *code, gint size)
7759 mono_arch_flush_register_windows (void)
7764 mono_arch_is_inst_imm (gint64 imm)
7766 return amd64_is_imm32 (imm);
7770 * Determine whenever the trap whose info is in SIGINFO is caused by
7774 mono_arch_is_int_overflow (void *sigctx, void *info)
7781 mono_sigctx_to_monoctx (sigctx, &ctx);
7783 rip = (guint8*)ctx.rip;
7785 if (IS_REX (rip [0])) {
7786 reg = amd64_rex_b (rip [0]);
7792 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7794 reg += x86_modrm_rm (rip [1]);
7834 g_assert_not_reached ();
7846 mono_arch_get_patch_offset (guint8 *code)
7852 * mono_breakpoint_clean_code:
7854 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7855 * breakpoints in the original code, they are removed in the copy.
7857 * Returns TRUE if no sw breakpoint was present.
7860 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7863 * If method_start is non-NULL we need to perform bound checks, since we access memory
7864 * at code - offset we could go before the start of the method and end up in a different
7865 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7868 if (!method_start || code - offset >= method_start) {
7869 memcpy (buf, code - offset, size);
7871 int diff = code - method_start;
7872 memset (buf, 0, size);
7873 memcpy (buf + offset - diff, method_start, diff + size - offset);
7878 #if defined(__native_client_codegen__)
7879 /* For membase calls, we want the base register. for Native Client, */
7880 /* all indirect calls have the following sequence with the given sizes: */
7881 /* mov %eXX,%eXX [2-3] */
7882 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7883 /* and $0xffffffffffffffe0,%r11d [4] */
7884 /* add %r15,%r11 [3] */
7885 /* callq *%r11 [3] */
7888 /* Determine if code points to a NaCl call-through-register sequence, */
7889 /* (i.e., the last 3 instructions listed above) */
7891 is_nacl_call_reg_sequence(guint8* code)
7893 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7894 "\x4d\x03\xdf" /* add */
7895 "\x41\xff\xd3"; /* call */
7896 return memcmp(code, sequence, 10) == 0;
7899 /* Determine if code points to the first opcode of the mov membase component */
7900 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7901 /* (there could be a REX prefix before the opcode but it is ignored) */
7903 is_nacl_indirect_call_membase_sequence(guint8* code)
7905 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7906 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7907 /* and that src reg = dest reg */
7908 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7909 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7911 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7912 /* and has dst of r11 and base of r15 */
7913 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7914 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7916 #endif /* __native_client_codegen__ */
7919 mono_arch_get_this_arg_reg (guint8 *code)
7921 return AMD64_ARG_REG1;
7925 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7927 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7930 #define MAX_ARCH_DELEGATE_PARAMS 10
7933 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7935 guint8 *code, *start;
7939 start = code = mono_global_codeman_reserve (64);
7941 /* Replace the this argument with the target */
7942 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7943 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7944 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7946 g_assert ((code - start) < 64);
7948 start = code = mono_global_codeman_reserve (64);
7950 if (param_count == 0) {
7951 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7953 /* We have to shift the arguments left */
7954 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7955 for (i = 0; i < param_count; ++i) {
7958 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7960 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7962 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7966 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7968 g_assert ((code - start) < 64);
7971 nacl_global_codeman_validate (&start, 64, &code);
7972 mono_arch_flush_icache (start, code - start);
7975 *code_len = code - start;
7977 if (mono_jit_map_is_enabled ()) {
7980 buff = (char*)"delegate_invoke_has_target";
7982 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7983 mono_emit_jit_tramp (start, code - start, buff);
7987 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7993 * mono_arch_get_delegate_invoke_impls:
7995 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7999 mono_arch_get_delegate_invoke_impls (void)
8007 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8008 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8010 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8011 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8012 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8013 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8014 g_free (tramp_name);
8021 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8023 guint8 *code, *start;
8026 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8029 /* FIXME: Support more cases */
8030 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8034 static guint8* cached = NULL;
8040 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8042 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8044 mono_memory_barrier ();
8048 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8049 for (i = 0; i < sig->param_count; ++i)
8050 if (!mono_is_regsize_var (sig->params [i]))
8052 if (sig->param_count > 4)
8055 code = cache [sig->param_count];
8059 if (mono_aot_only) {
8060 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8061 start = mono_aot_get_trampoline (name);
8064 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8067 mono_memory_barrier ();
8069 cache [sig->param_count] = start;
8076 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8078 guint8 *code, *start;
8081 start = code = mono_global_codeman_reserve (size);
8083 /* Replace the this argument with the target */
8084 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8085 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8088 /* Load the IMT reg */
8089 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8092 /* Load the vtable */
8093 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8094 amd64_jump_membase (code, AMD64_RAX, offset);
8095 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8101 mono_arch_finish_init (void)
8103 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8104 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8109 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8113 #if defined(__default_codegen__)
8114 #define CMP_SIZE (6 + 1)
8115 #define CMP_REG_REG_SIZE (4 + 1)
8116 #define BR_SMALL_SIZE 2
8117 #define BR_LARGE_SIZE 6
8118 #define MOV_REG_IMM_SIZE 10
8119 #define MOV_REG_IMM_32BIT_SIZE 6
8120 #define JUMP_REG_SIZE (2 + 1)
8121 #elif defined(__native_client_codegen__)
8122 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8123 #define CMP_SIZE ((6 + 1) * 2 - 1)
8124 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8125 #define BR_SMALL_SIZE (2 * 2 - 1)
8126 #define BR_LARGE_SIZE (6 * 2 - 1)
8127 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8128 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8129 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8130 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8131 /* Jump membase's size is large and unpredictable */
8132 /* in native client, just pad it out a whole bundle. */
8133 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8137 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8139 int i, distance = 0;
8140 for (i = start; i < target; ++i)
8141 distance += imt_entries [i]->chunk_size;
8146 * LOCKING: called with the domain lock held
8149 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8150 gpointer fail_tramp)
8154 guint8 *code, *start;
8155 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8157 for (i = 0; i < count; ++i) {
8158 MonoIMTCheckItem *item = imt_entries [i];
8159 if (item->is_equals) {
8160 if (item->check_target_idx) {
8161 if (!item->compare_done) {
8162 if (amd64_is_imm32 (item->key))
8163 item->chunk_size += CMP_SIZE;
8165 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8167 if (item->has_target_code) {
8168 item->chunk_size += MOV_REG_IMM_SIZE;
8170 if (vtable_is_32bit)
8171 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8173 item->chunk_size += MOV_REG_IMM_SIZE;
8174 #ifdef __native_client_codegen__
8175 item->chunk_size += JUMP_MEMBASE_SIZE;
8178 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8181 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8182 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8184 if (vtable_is_32bit)
8185 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8187 item->chunk_size += MOV_REG_IMM_SIZE;
8188 item->chunk_size += JUMP_REG_SIZE;
8189 /* with assert below:
8190 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8192 #ifdef __native_client_codegen__
8193 item->chunk_size += JUMP_MEMBASE_SIZE;
8198 if (amd64_is_imm32 (item->key))
8199 item->chunk_size += CMP_SIZE;
8201 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8202 item->chunk_size += BR_LARGE_SIZE;
8203 imt_entries [item->check_target_idx]->compare_done = TRUE;
8205 size += item->chunk_size;
8207 #if defined(__native_client__) && defined(__native_client_codegen__)
8208 /* In Native Client, we don't re-use thunks, allocate from the */
8209 /* normal code manager paths. */
8210 code = mono_domain_code_reserve (domain, size);
8213 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8215 code = mono_domain_code_reserve (domain, size);
8218 for (i = 0; i < count; ++i) {
8219 MonoIMTCheckItem *item = imt_entries [i];
8220 item->code_target = code;
8221 if (item->is_equals) {
8222 gboolean fail_case = !item->check_target_idx && fail_tramp;
8224 if (item->check_target_idx || fail_case) {
8225 if (!item->compare_done || fail_case) {
8226 if (amd64_is_imm32 (item->key))
8227 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8229 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8230 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8233 item->jmp_code = code;
8234 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8235 if (item->has_target_code) {
8236 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8237 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8239 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8240 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8244 amd64_patch (item->jmp_code, code);
8245 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8246 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8247 item->jmp_code = NULL;
8250 /* enable the commented code to assert on wrong method */
8252 if (amd64_is_imm32 (item->key))
8253 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8255 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8256 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8258 item->jmp_code = code;
8259 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8260 /* See the comment below about R10 */
8261 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8262 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8263 amd64_patch (item->jmp_code, code);
8264 amd64_breakpoint (code);
8265 item->jmp_code = NULL;
8267 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8268 needs to be preserved. R10 needs
8269 to be preserved for calls which
8270 require a runtime generic context,
8271 but interface calls don't. */
8272 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8273 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8277 if (amd64_is_imm32 (item->key))
8278 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8280 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8281 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8283 item->jmp_code = code;
8284 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8285 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8287 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8289 g_assert (code - item->code_target <= item->chunk_size);
8291 /* patch the branches to get to the target items */
8292 for (i = 0; i < count; ++i) {
8293 MonoIMTCheckItem *item = imt_entries [i];
8294 if (item->jmp_code) {
8295 if (item->check_target_idx) {
8296 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8302 mono_stats.imt_thunks_size += code - start;
8303 g_assert (code - start <= size);
8305 nacl_domain_code_validate(domain, &start, size, &code);
8306 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8312 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8314 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8318 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8320 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8324 mono_arch_get_cie_program (void)
8328 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8329 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8337 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8339 MonoInst *ins = NULL;
8342 if (cmethod->klass == mono_defaults.math_class) {
8343 if (strcmp (cmethod->name, "Sin") == 0) {
8345 } else if (strcmp (cmethod->name, "Cos") == 0) {
8347 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8349 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8353 if (opcode && fsig->param_count == 1) {
8354 MONO_INST_NEW (cfg, ins, opcode);
8355 ins->type = STACK_R8;
8356 ins->dreg = mono_alloc_freg (cfg);
8357 ins->sreg1 = args [0]->dreg;
8358 MONO_ADD_INS (cfg->cbb, ins);
8362 if (cfg->opt & MONO_OPT_CMOV) {
8363 if (strcmp (cmethod->name, "Min") == 0) {
8364 if (fsig->params [0]->type == MONO_TYPE_I4)
8366 if (fsig->params [0]->type == MONO_TYPE_U4)
8367 opcode = OP_IMIN_UN;
8368 else if (fsig->params [0]->type == MONO_TYPE_I8)
8370 else if (fsig->params [0]->type == MONO_TYPE_U8)
8371 opcode = OP_LMIN_UN;
8372 } else if (strcmp (cmethod->name, "Max") == 0) {
8373 if (fsig->params [0]->type == MONO_TYPE_I4)
8375 if (fsig->params [0]->type == MONO_TYPE_U4)
8376 opcode = OP_IMAX_UN;
8377 else if (fsig->params [0]->type == MONO_TYPE_I8)
8379 else if (fsig->params [0]->type == MONO_TYPE_U8)
8380 opcode = OP_LMAX_UN;
8384 if (opcode && fsig->param_count == 2) {
8385 MONO_INST_NEW (cfg, ins, opcode);
8386 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8387 ins->dreg = mono_alloc_ireg (cfg);
8388 ins->sreg1 = args [0]->dreg;
8389 ins->sreg2 = args [1]->dreg;
8390 MONO_ADD_INS (cfg->cbb, ins);
8394 /* OP_FREM is not IEEE compatible */
8395 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8396 MONO_INST_NEW (cfg, ins, OP_FREM);
8397 ins->inst_i0 = args [0];
8398 ins->inst_i1 = args [1];
8408 mono_arch_print_tree (MonoInst *tree, int arity)
8413 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8416 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8419 case AMD64_RCX: return ctx->rcx;
8420 case AMD64_RDX: return ctx->rdx;
8421 case AMD64_RBX: return ctx->rbx;
8422 case AMD64_RBP: return ctx->rbp;
8423 case AMD64_RSP: return ctx->rsp;
8425 return _CTX_REG (ctx, rax, reg);
8430 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8449 _CTX_REG (ctx, rax, reg) = val;
8454 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8456 gpointer *sp, old_value;
8460 bp = MONO_CONTEXT_GET_BP (ctx);
8461 sp = *(gpointer*)(bp + clause->exvar_offset);
8464 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8473 * mono_arch_emit_load_aotconst:
8475 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8476 * TARGET from the mscorlib GOT in full-aot code.
8477 * On AMD64, the result is placed into R11.
8480 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8482 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8483 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8489 * mono_arch_get_trampolines:
8491 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8495 mono_arch_get_trampolines (gboolean aot)
8497 return mono_amd64_get_exception_trampolines (aot);
8500 /* Soft Debug support */
8501 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8504 * mono_arch_set_breakpoint:
8506 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8507 * The location should contain code emitted by OP_SEQ_POINT.
8510 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8513 guint8 *orig_code = code;
8516 guint32 native_offset = ip - (guint8*)ji->code_start;
8517 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8519 g_assert (info->bp_addrs [native_offset] == 0);
8520 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8523 * In production, we will use int3 (has to fix the size in the md
8524 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8527 g_assert (code [0] == 0x90);
8528 if (breakpoint_size == 8) {
8529 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8531 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8532 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8535 g_assert (code - orig_code == breakpoint_size);
8540 * mono_arch_clear_breakpoint:
8542 * Clear the breakpoint at IP.
8545 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8551 guint32 native_offset = ip - (guint8*)ji->code_start;
8552 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8554 info->bp_addrs [native_offset] = NULL;
8556 for (i = 0; i < breakpoint_size; ++i)
8562 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8565 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8566 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8571 siginfo_t* sinfo = (siginfo_t*) info;
8572 /* Sometimes the address is off by 4 */
8573 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8581 * mono_arch_skip_breakpoint:
8583 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8584 * we resume, the instruction is not executed again.
8587 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8590 /* The breakpoint instruction is a call */
8592 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8597 * mono_arch_start_single_stepping:
8599 * Start single stepping.
8602 mono_arch_start_single_stepping (void)
8604 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8605 ss_trampoline = mini_get_single_step_trampoline ();
8609 * mono_arch_stop_single_stepping:
8611 * Stop single stepping.
8614 mono_arch_stop_single_stepping (void)
8616 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8617 ss_trampoline = NULL;
8621 * mono_arch_is_single_step_event:
8623 * Return whenever the machine state in SIGCTX corresponds to a single
8627 mono_arch_is_single_step_event (void *info, void *sigctx)
8630 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8631 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8636 siginfo_t* sinfo = (siginfo_t*) info;
8637 /* Sometimes the address is off by 4 */
8638 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8646 * mono_arch_skip_single_step:
8648 * Modify CTX so the ip is placed after the single step trigger instruction,
8649 * we resume, the instruction is not executed again.
8652 mono_arch_skip_single_step (MonoContext *ctx)
8654 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8658 * mono_arch_create_seq_point_info:
8660 * Return a pointer to a data structure which is used by the sequence
8661 * point implementation in AOTed code.
8664 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8669 // FIXME: Add a free function
8671 mono_domain_lock (domain);
8672 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8674 mono_domain_unlock (domain);
8677 ji = mono_jit_info_table_find (domain, (char*)code);
8680 // FIXME: Optimize the size
8681 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8683 info->ss_tramp_addr = &ss_trampoline;
8685 mono_domain_lock (domain);
8686 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8688 mono_domain_unlock (domain);
8695 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8697 ext->lmf.previous_lmf = prev_lmf;
8698 /* Mark that this is a MonoLMFExt */
8699 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8700 ext->lmf.rsp = (gssize)ext;
8706 mono_arch_opcode_supported (int opcode)
8709 case OP_ATOMIC_ADD_I4:
8710 case OP_ATOMIC_ADD_I8:
8711 case OP_ATOMIC_EXCHANGE_I4:
8712 case OP_ATOMIC_EXCHANGE_I8:
8713 case OP_ATOMIC_CAS_I4:
8714 case OP_ATOMIC_CAS_I8:
8715 case OP_ATOMIC_LOAD_I1:
8716 case OP_ATOMIC_LOAD_I2:
8717 case OP_ATOMIC_LOAD_I4:
8718 case OP_ATOMIC_LOAD_I8:
8719 case OP_ATOMIC_LOAD_U1:
8720 case OP_ATOMIC_LOAD_U2:
8721 case OP_ATOMIC_LOAD_U4:
8722 case OP_ATOMIC_LOAD_U8:
8723 case OP_ATOMIC_LOAD_R4:
8724 case OP_ATOMIC_LOAD_R8:
8725 case OP_ATOMIC_STORE_I1:
8726 case OP_ATOMIC_STORE_I2:
8727 case OP_ATOMIC_STORE_I4:
8728 case OP_ATOMIC_STORE_I8:
8729 case OP_ATOMIC_STORE_U1:
8730 case OP_ATOMIC_STORE_U2:
8731 case OP_ATOMIC_STORE_U4:
8732 case OP_ATOMIC_STORE_U8:
8733 case OP_ATOMIC_STORE_R4:
8734 case OP_ATOMIC_STORE_R8: