2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-mmap.h>
32 #include "mini-amd64.h"
33 #include "cpu-amd64.h"
34 #include "debugger-agent.h"
36 static gint lmf_tls_offset = -1;
37 static gint lmf_addr_tls_offset = -1;
38 static gint appdomain_tls_offset = -1;
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
53 /* Under windows, the calling convention is never stdcall */
54 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68 * The code generated for sequence points reads from this location, which is
69 * made read-only when single stepping is enabled.
71 static gpointer ss_trigger_page;
73 /* Enabled breakpoints read from this trigger page */
74 static gpointer bp_trigger_page;
76 /* The size of the breakpoint sequence */
77 static int breakpoint_size;
79 /* The size of the breakpoint instruction causing the actual fault */
80 static int breakpoint_fault_size;
82 /* The size of the single step instruction causing the actual fault */
83 static int single_step_fault_size;
86 /* On Win64 always reserve first 32 bytes for first four arguments */
87 #define ARGS_OFFSET 48
89 #define ARGS_OFFSET 16
91 #define GP_SCRATCH_REG AMD64_R11
94 * AMD64 register usage:
95 * - callee saved registers are used for global register allocation
96 * - %r11 is used for materializing 64 bit constants in opcodes
97 * - the rest is used for local allocation
101 * Floating point comparison results:
111 mono_arch_regname (int reg)
114 case AMD64_RAX: return "%rax";
115 case AMD64_RBX: return "%rbx";
116 case AMD64_RCX: return "%rcx";
117 case AMD64_RDX: return "%rdx";
118 case AMD64_RSP: return "%rsp";
119 case AMD64_RBP: return "%rbp";
120 case AMD64_RDI: return "%rdi";
121 case AMD64_RSI: return "%rsi";
122 case AMD64_R8: return "%r8";
123 case AMD64_R9: return "%r9";
124 case AMD64_R10: return "%r10";
125 case AMD64_R11: return "%r11";
126 case AMD64_R12: return "%r12";
127 case AMD64_R13: return "%r13";
128 case AMD64_R14: return "%r14";
129 case AMD64_R15: return "%r15";
134 static const char * packed_xmmregs [] = {
135 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
136 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
139 static const char * single_xmmregs [] = {
140 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
141 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
145 mono_arch_fregname (int reg)
147 if (reg < AMD64_XMM_NREG)
148 return single_xmmregs [reg];
154 mono_arch_xregname (int reg)
156 if (reg < AMD64_XMM_NREG)
157 return packed_xmmregs [reg];
162 G_GNUC_UNUSED static void
167 G_GNUC_UNUSED static gboolean
170 static int count = 0;
173 if (!getenv ("COUNT"))
176 if (count == atoi (getenv ("COUNT"))) {
180 if (count > atoi (getenv ("COUNT"))) {
191 return debug_count ();
197 static inline gboolean
198 amd64_is_near_call (guint8 *code)
201 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
204 return code [0] == 0xe8;
208 amd64_patch (unsigned char* code, gpointer target)
213 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
218 if ((code [0] & 0xf8) == 0xb8) {
219 /* amd64_set_reg_template */
220 *(guint64*)(code + 1) = (guint64)target;
222 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
223 /* mov 0(%rip), %dreg */
224 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
226 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
227 /* call *<OFFSET>(%rip) */
228 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
230 else if ((code [0] == 0xe8)) {
232 gint64 disp = (guint8*)target - (guint8*)code;
233 g_assert (amd64_is_imm32 (disp));
234 x86_patch (code, (unsigned char*)target);
237 x86_patch (code, (unsigned char*)target);
241 mono_amd64_patch (unsigned char* code, gpointer target)
243 amd64_patch (code, target);
252 ArgValuetypeAddrInIReg,
253 ArgNone /* only in pair_storage */
261 /* Only if storage == ArgValuetypeInReg */
262 ArgStorage pair_storage [2];
271 gboolean need_stack_align;
272 gboolean vtype_retaddr;
273 /* The index of the vret arg in the argument list */
280 #define DEBUG(a) if (cfg->verbose_level > 1) a
285 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
287 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
291 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
293 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
297 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
299 ainfo->offset = *stack_size;
301 if (*gr >= PARAM_REGS) {
302 ainfo->storage = ArgOnStack;
303 (*stack_size) += sizeof (gpointer);
306 ainfo->storage = ArgInIReg;
307 ainfo->reg = param_regs [*gr];
313 #define FLOAT_PARAM_REGS 4
315 #define FLOAT_PARAM_REGS 8
319 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
321 ainfo->offset = *stack_size;
323 if (*gr >= FLOAT_PARAM_REGS) {
324 ainfo->storage = ArgOnStack;
325 (*stack_size) += sizeof (gpointer);
328 /* A double register */
330 ainfo->storage = ArgInDoubleSSEReg;
332 ainfo->storage = ArgInFloatSSEReg;
338 typedef enum ArgumentClass {
346 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
348 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
351 ptype = mini_type_get_underlying_type (NULL, type);
352 switch (ptype->type) {
353 case MONO_TYPE_BOOLEAN:
363 case MONO_TYPE_STRING:
364 case MONO_TYPE_OBJECT:
365 case MONO_TYPE_CLASS:
366 case MONO_TYPE_SZARRAY:
368 case MONO_TYPE_FNPTR:
369 case MONO_TYPE_ARRAY:
372 class2 = ARG_CLASS_INTEGER;
377 class2 = ARG_CLASS_INTEGER;
379 class2 = ARG_CLASS_SSE;
383 case MONO_TYPE_TYPEDBYREF:
384 g_assert_not_reached ();
386 case MONO_TYPE_GENERICINST:
387 if (!mono_type_generic_inst_is_valuetype (ptype)) {
388 class2 = ARG_CLASS_INTEGER;
392 case MONO_TYPE_VALUETYPE: {
393 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
396 for (i = 0; i < info->num_fields; ++i) {
398 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
403 g_assert_not_reached ();
407 if (class1 == class2)
409 else if (class1 == ARG_CLASS_NO_CLASS)
411 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
412 class1 = ARG_CLASS_MEMORY;
413 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
414 class1 = ARG_CLASS_INTEGER;
416 class1 = ARG_CLASS_SSE;
422 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
424 guint32 *gr, guint32 *fr, guint32 *stack_size)
426 guint32 size, quad, nquads, i;
427 ArgumentClass args [2];
428 MonoMarshalType *info = NULL;
430 MonoGenericSharingContext tmp_gsctx;
431 gboolean pass_on_stack = FALSE;
434 * The gsctx currently contains no data, it is only used for checking whenever
435 * open types are allowed, some callers like mono_arch_get_argument_info ()
436 * don't pass it to us, so work around that.
441 klass = mono_class_from_mono_type (type);
442 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
444 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
445 /* We pass and return vtypes of size 8 in a register */
446 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
447 pass_on_stack = TRUE;
451 pass_on_stack = TRUE;
456 /* Allways pass in memory */
457 ainfo->offset = *stack_size;
458 *stack_size += ALIGN_TO (size, 8);
459 ainfo->storage = ArgOnStack;
464 /* FIXME: Handle structs smaller than 8 bytes */
465 //if ((size % 8) != 0)
474 /* Always pass in 1 or 2 integer registers */
475 args [0] = ARG_CLASS_INTEGER;
476 args [1] = ARG_CLASS_INTEGER;
477 /* Only the simplest cases are supported */
478 if (is_return && nquads != 1) {
479 args [0] = ARG_CLASS_MEMORY;
480 args [1] = ARG_CLASS_MEMORY;
484 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
485 * The X87 and SSEUP stuff is left out since there are no such types in
488 info = mono_marshal_load_type_info (klass);
492 if (info->native_size > 16) {
493 ainfo->offset = *stack_size;
494 *stack_size += ALIGN_TO (info->native_size, 8);
495 ainfo->storage = ArgOnStack;
500 switch (info->native_size) {
501 case 1: case 2: case 4: case 8:
505 ainfo->storage = ArgOnStack;
506 ainfo->offset = *stack_size;
507 *stack_size += ALIGN_TO (info->native_size, 8);
510 ainfo->storage = ArgValuetypeAddrInIReg;
512 if (*gr < PARAM_REGS) {
513 ainfo->pair_storage [0] = ArgInIReg;
514 ainfo->pair_regs [0] = param_regs [*gr];
518 ainfo->pair_storage [0] = ArgOnStack;
519 ainfo->offset = *stack_size;
528 args [0] = ARG_CLASS_NO_CLASS;
529 args [1] = ARG_CLASS_NO_CLASS;
530 for (quad = 0; quad < nquads; ++quad) {
533 ArgumentClass class1;
535 if (info->num_fields == 0)
536 class1 = ARG_CLASS_MEMORY;
538 class1 = ARG_CLASS_NO_CLASS;
539 for (i = 0; i < info->num_fields; ++i) {
540 size = mono_marshal_type_size (info->fields [i].field->type,
541 info->fields [i].mspec,
542 &align, TRUE, klass->unicode);
543 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
544 /* Unaligned field */
548 /* Skip fields in other quad */
549 if ((quad == 0) && (info->fields [i].offset >= 8))
551 if ((quad == 1) && (info->fields [i].offset < 8))
554 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
556 g_assert (class1 != ARG_CLASS_NO_CLASS);
557 args [quad] = class1;
561 /* Post merger cleanup */
562 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
563 args [0] = args [1] = ARG_CLASS_MEMORY;
565 /* Allocate registers */
570 ainfo->storage = ArgValuetypeInReg;
571 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
572 for (quad = 0; quad < nquads; ++quad) {
573 switch (args [quad]) {
574 case ARG_CLASS_INTEGER:
575 if (*gr >= PARAM_REGS)
576 args [quad] = ARG_CLASS_MEMORY;
578 ainfo->pair_storage [quad] = ArgInIReg;
580 ainfo->pair_regs [quad] = return_regs [*gr];
582 ainfo->pair_regs [quad] = param_regs [*gr];
587 if (*fr >= FLOAT_PARAM_REGS)
588 args [quad] = ARG_CLASS_MEMORY;
590 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
591 ainfo->pair_regs [quad] = *fr;
595 case ARG_CLASS_MEMORY:
598 g_assert_not_reached ();
602 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
603 /* Revert possible register assignments */
607 ainfo->offset = *stack_size;
609 *stack_size += ALIGN_TO (info->native_size, 8);
611 *stack_size += nquads * sizeof (gpointer);
612 ainfo->storage = ArgOnStack;
620 * Obtain information about a call according to the calling convention.
621 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
622 * Draft Version 0.23" document for more information.
625 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
627 guint32 i, gr, fr, pstart;
629 int n = sig->hasthis + sig->param_count;
630 guint32 stack_size = 0;
634 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
636 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
645 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
646 switch (ret_type->type) {
647 case MONO_TYPE_BOOLEAN:
658 case MONO_TYPE_FNPTR:
659 case MONO_TYPE_CLASS:
660 case MONO_TYPE_OBJECT:
661 case MONO_TYPE_SZARRAY:
662 case MONO_TYPE_ARRAY:
663 case MONO_TYPE_STRING:
664 cinfo->ret.storage = ArgInIReg;
665 cinfo->ret.reg = AMD64_RAX;
669 cinfo->ret.storage = ArgInIReg;
670 cinfo->ret.reg = AMD64_RAX;
673 cinfo->ret.storage = ArgInFloatSSEReg;
674 cinfo->ret.reg = AMD64_XMM0;
677 cinfo->ret.storage = ArgInDoubleSSEReg;
678 cinfo->ret.reg = AMD64_XMM0;
680 case MONO_TYPE_GENERICINST:
681 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
682 cinfo->ret.storage = ArgInIReg;
683 cinfo->ret.reg = AMD64_RAX;
687 case MONO_TYPE_VALUETYPE: {
688 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
690 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
691 if (cinfo->ret.storage == ArgOnStack) {
692 cinfo->vtype_retaddr = TRUE;
693 /* The caller passes the address where the value is stored */
697 case MONO_TYPE_TYPEDBYREF:
698 /* Same as a valuetype with size 24 */
699 cinfo->vtype_retaddr = TRUE;
704 g_error ("Can't handle as return value 0x%x", sig->ret->type);
710 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
711 * the first argument, allowing 'this' to be always passed in the first arg reg.
712 * Also do this if the first argument is a reference type, since virtual calls
713 * are sometimes made using calli without sig->hasthis set, like in the delegate
716 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
718 add_general (&gr, &stack_size, cinfo->args + 0);
720 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
723 add_general (&gr, &stack_size, &cinfo->ret);
724 cinfo->vret_arg_index = 1;
728 add_general (&gr, &stack_size, cinfo->args + 0);
730 if (cinfo->vtype_retaddr)
731 add_general (&gr, &stack_size, &cinfo->ret);
734 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
736 fr = FLOAT_PARAM_REGS;
738 /* Emit the signature cookie just before the implicit arguments */
739 add_general (&gr, &stack_size, &cinfo->sig_cookie);
742 for (i = pstart; i < sig->param_count; ++i) {
743 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
747 /* The float param registers and other param registers must be the same index on Windows x64.*/
754 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
755 /* We allways pass the sig cookie on the stack for simplicity */
757 * Prevent implicit arguments + the sig cookie from being passed
761 fr = FLOAT_PARAM_REGS;
763 /* Emit the signature cookie just before the implicit arguments */
764 add_general (&gr, &stack_size, &cinfo->sig_cookie);
767 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
768 switch (ptype->type) {
769 case MONO_TYPE_BOOLEAN:
772 add_general (&gr, &stack_size, ainfo);
777 add_general (&gr, &stack_size, ainfo);
781 add_general (&gr, &stack_size, ainfo);
786 case MONO_TYPE_FNPTR:
787 case MONO_TYPE_CLASS:
788 case MONO_TYPE_OBJECT:
789 case MONO_TYPE_STRING:
790 case MONO_TYPE_SZARRAY:
791 case MONO_TYPE_ARRAY:
792 add_general (&gr, &stack_size, ainfo);
794 case MONO_TYPE_GENERICINST:
795 if (!mono_type_generic_inst_is_valuetype (ptype)) {
796 add_general (&gr, &stack_size, ainfo);
800 case MONO_TYPE_VALUETYPE:
801 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
803 case MONO_TYPE_TYPEDBYREF:
805 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
807 stack_size += sizeof (MonoTypedRef);
808 ainfo->storage = ArgOnStack;
813 add_general (&gr, &stack_size, ainfo);
816 add_float (&fr, &stack_size, ainfo, FALSE);
819 add_float (&fr, &stack_size, ainfo, TRUE);
822 g_assert_not_reached ();
826 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
828 fr = FLOAT_PARAM_REGS;
830 /* Emit the signature cookie just before the implicit arguments */
831 add_general (&gr, &stack_size, &cinfo->sig_cookie);
835 // There always is 32 bytes reserved on the stack when calling on Winx64
839 if (stack_size & 0x8) {
840 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
841 cinfo->need_stack_align = TRUE;
845 cinfo->stack_usage = stack_size;
846 cinfo->reg_usage = gr;
847 cinfo->freg_usage = fr;
852 * mono_arch_get_argument_info:
853 * @csig: a method signature
854 * @param_count: the number of parameters to consider
855 * @arg_info: an array to store the result infos
857 * Gathers information on parameters such as size, alignment and
858 * padding. arg_info should be large enought to hold param_count + 1 entries.
860 * Returns the size of the argument area on the stack.
863 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
866 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
867 guint32 args_size = cinfo->stack_usage;
869 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
871 arg_info [0].offset = 0;
874 for (k = 0; k < param_count; k++) {
875 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
877 arg_info [k + 1].size = 0;
886 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
891 c1 = get_call_info (NULL, NULL, caller_sig, FALSE);
892 c2 = get_call_info (NULL, NULL, callee_sig, FALSE);
893 res = c1->stack_usage >= c2->stack_usage;
894 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
895 /* An address on the callee's stack is passed as the first argument */
905 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
908 __asm__ __volatile__ ("cpuid"
909 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
923 * Initialize the cpu to execute managed code.
926 mono_arch_cpu_init (void)
931 /* spec compliance requires running with double precision */
932 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
933 fpcw &= ~X86_FPCW_PRECC_MASK;
934 fpcw |= X86_FPCW_PREC_DOUBLE;
935 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
936 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
938 /* TODO: This is crashing on Win64 right now.
939 * _control87 (_PC_53, MCW_PC);
945 * Initialize architecture specific code.
948 mono_arch_init (void)
952 InitializeCriticalSection (&mini_arch_mutex);
954 #ifdef MONO_ARCH_NOMAP32BIT
955 flags = MONO_MMAP_READ;
956 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
957 breakpoint_size = 13;
958 breakpoint_fault_size = 3;
959 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
960 single_step_fault_size = 5;
962 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
963 /* amd64_mov_reg_mem () */
965 breakpoint_fault_size = 8;
966 single_step_fault_size = 8;
969 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
970 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
971 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
973 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
974 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
975 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
979 * Cleanup architecture specific code.
982 mono_arch_cleanup (void)
984 DeleteCriticalSection (&mini_arch_mutex);
988 * This function returns the optimizations supported on this cpu.
991 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
993 int eax, ebx, ecx, edx;
997 /* Feature Flags function, flags returned in EDX. */
998 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
999 if (edx & (1 << 15)) {
1000 opts |= MONO_OPT_CMOV;
1002 opts |= MONO_OPT_FCMOV;
1004 *exclude_mask |= MONO_OPT_FCMOV;
1006 *exclude_mask |= MONO_OPT_CMOV;
1013 * This function test for all SSE functions supported.
1015 * Returns a bitmask corresponding to all supported versions.
1019 mono_arch_cpu_enumerate_simd_versions (void)
1021 int eax, ebx, ecx, edx;
1022 guint32 sse_opts = 0;
1024 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1025 if (edx & (1 << 25))
1026 sse_opts |= SIMD_VERSION_SSE1;
1027 if (edx & (1 << 26))
1028 sse_opts |= SIMD_VERSION_SSE2;
1030 sse_opts |= SIMD_VERSION_SSE3;
1032 sse_opts |= SIMD_VERSION_SSSE3;
1033 if (ecx & (1 << 19))
1034 sse_opts |= SIMD_VERSION_SSE41;
1035 if (ecx & (1 << 20))
1036 sse_opts |= SIMD_VERSION_SSE42;
1039 /* Yes, all this needs to be done to check for sse4a.
1040 See: "Amd: CPUID Specification"
1042 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1043 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1044 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1045 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1047 sse_opts |= SIMD_VERSION_SSE4a;
1057 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1062 for (i = 0; i < cfg->num_varinfo; i++) {
1063 MonoInst *ins = cfg->varinfo [i];
1064 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1067 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1070 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1071 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1074 if (mono_is_regsize_var (ins->inst_vtype)) {
1075 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1076 g_assert (i == vmv->idx);
1077 vars = g_list_prepend (vars, vmv);
1081 vars = mono_varlist_sort (cfg, vars, 0);
1087 * mono_arch_compute_omit_fp:
1089 * Determine whenever the frame pointer can be eliminated.
1092 mono_arch_compute_omit_fp (MonoCompile *cfg)
1094 MonoMethodSignature *sig;
1095 MonoMethodHeader *header;
1099 if (cfg->arch.omit_fp_computed)
1102 header = cfg->header;
1104 sig = mono_method_signature (cfg->method);
1106 if (!cfg->arch.cinfo)
1107 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1108 cinfo = cfg->arch.cinfo;
1111 * FIXME: Remove some of the restrictions.
1113 cfg->arch.omit_fp = TRUE;
1114 cfg->arch.omit_fp_computed = TRUE;
1116 if (cfg->disable_omit_fp)
1117 cfg->arch.omit_fp = FALSE;
1119 if (!debug_omit_fp ())
1120 cfg->arch.omit_fp = FALSE;
1122 if (cfg->method->save_lmf)
1123 cfg->arch.omit_fp = FALSE;
1125 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1126 cfg->arch.omit_fp = FALSE;
1127 if (header->num_clauses)
1128 cfg->arch.omit_fp = FALSE;
1129 if (cfg->param_area)
1130 cfg->arch.omit_fp = FALSE;
1131 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1132 cfg->arch.omit_fp = FALSE;
1133 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1134 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1135 cfg->arch.omit_fp = FALSE;
1136 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1137 ArgInfo *ainfo = &cinfo->args [i];
1139 if (ainfo->storage == ArgOnStack) {
1141 * The stack offset can only be determined when the frame
1144 cfg->arch.omit_fp = FALSE;
1149 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1150 MonoInst *ins = cfg->varinfo [i];
1153 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1158 mono_arch_get_global_int_regs (MonoCompile *cfg)
1162 mono_arch_compute_omit_fp (cfg);
1164 if (cfg->globalra) {
1165 if (cfg->arch.omit_fp)
1166 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1168 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1169 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1170 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1171 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1172 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1174 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1175 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1176 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1177 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1178 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1179 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1180 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1181 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1183 if (cfg->arch.omit_fp)
1184 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1186 /* We use the callee saved registers for global allocation */
1187 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1188 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1189 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1190 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1191 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1193 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1194 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1202 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1207 /* All XMM registers */
1208 for (i = 0; i < 16; ++i)
1209 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1215 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1217 static GList *r = NULL;
1222 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1223 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1224 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1225 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1226 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1227 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1229 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1230 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1231 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1232 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1233 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1234 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1235 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1236 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1238 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1245 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1248 static GList *r = NULL;
1253 for (i = 0; i < AMD64_XMM_NREG; ++i)
1254 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1256 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1263 * mono_arch_regalloc_cost:
1265 * Return the cost, in number of memory references, of the action of
1266 * allocating the variable VMV into a register during global register
1270 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1272 MonoInst *ins = cfg->varinfo [vmv->idx];
1274 if (cfg->method->save_lmf)
1275 /* The register is already saved */
1276 /* substract 1 for the invisible store in the prolog */
1277 return (ins->opcode == OP_ARG) ? 0 : 1;
1280 return (ins->opcode == OP_ARG) ? 1 : 2;
1284 * mono_arch_fill_argument_info:
1286 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1290 mono_arch_fill_argument_info (MonoCompile *cfg)
1292 MonoMethodSignature *sig;
1293 MonoMethodHeader *header;
1298 header = cfg->header;
1300 sig = mono_method_signature (cfg->method);
1302 cinfo = cfg->arch.cinfo;
1305 * Contrary to mono_arch_allocate_vars (), the information should describe
1306 * where the arguments are at the beginning of the method, not where they can be
1307 * accessed during the execution of the method. The later makes no sense for the
1308 * global register allocator, since a variable can be in more than one location.
1310 if (sig->ret->type != MONO_TYPE_VOID) {
1311 switch (cinfo->ret.storage) {
1313 case ArgInFloatSSEReg:
1314 case ArgInDoubleSSEReg:
1315 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1316 cfg->vret_addr->opcode = OP_REGVAR;
1317 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1320 cfg->ret->opcode = OP_REGVAR;
1321 cfg->ret->inst_c0 = cinfo->ret.reg;
1324 case ArgValuetypeInReg:
1325 cfg->ret->opcode = OP_REGOFFSET;
1326 cfg->ret->inst_basereg = -1;
1327 cfg->ret->inst_offset = -1;
1330 g_assert_not_reached ();
1334 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1335 ArgInfo *ainfo = &cinfo->args [i];
1338 ins = cfg->args [i];
1340 if (sig->hasthis && (i == 0))
1341 arg_type = &mono_defaults.object_class->byval_arg;
1343 arg_type = sig->params [i - sig->hasthis];
1345 switch (ainfo->storage) {
1347 case ArgInFloatSSEReg:
1348 case ArgInDoubleSSEReg:
1349 ins->opcode = OP_REGVAR;
1350 ins->inst_c0 = ainfo->reg;
1353 ins->opcode = OP_REGOFFSET;
1354 ins->inst_basereg = -1;
1355 ins->inst_offset = -1;
1357 case ArgValuetypeInReg:
1359 ins->opcode = OP_NOP;
1362 g_assert_not_reached ();
1368 mono_arch_allocate_vars (MonoCompile *cfg)
1370 MonoMethodSignature *sig;
1371 MonoMethodHeader *header;
1374 guint32 locals_stack_size, locals_stack_align;
1378 header = cfg->header;
1380 sig = mono_method_signature (cfg->method);
1382 cinfo = cfg->arch.cinfo;
1384 mono_arch_compute_omit_fp (cfg);
1387 * We use the ABI calling conventions for managed code as well.
1388 * Exception: valuetypes are only sometimes passed or returned in registers.
1392 * The stack looks like this:
1393 * <incoming arguments passed on the stack>
1395 * <lmf/caller saved registers>
1398 * <localloc area> -> grows dynamically
1402 if (cfg->arch.omit_fp) {
1403 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1404 cfg->frame_reg = AMD64_RSP;
1407 /* Locals are allocated backwards from %fp */
1408 cfg->frame_reg = AMD64_RBP;
1412 if (cfg->method->save_lmf) {
1413 /* Reserve stack space for saving LMF */
1414 if (cfg->arch.omit_fp) {
1415 cfg->arch.lmf_offset = offset;
1416 offset += sizeof (MonoLMF);
1419 offset += sizeof (MonoLMF);
1420 cfg->arch.lmf_offset = -offset;
1423 if (cfg->arch.omit_fp)
1424 cfg->arch.reg_save_area_offset = offset;
1425 /* Reserve space for caller saved registers */
1426 for (i = 0; i < AMD64_NREG; ++i)
1427 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1428 offset += sizeof (gpointer);
1432 if (sig->ret->type != MONO_TYPE_VOID) {
1433 switch (cinfo->ret.storage) {
1435 case ArgInFloatSSEReg:
1436 case ArgInDoubleSSEReg:
1437 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1438 if (cfg->globalra) {
1439 cfg->vret_addr->opcode = OP_REGVAR;
1440 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1442 /* The register is volatile */
1443 cfg->vret_addr->opcode = OP_REGOFFSET;
1444 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1445 if (cfg->arch.omit_fp) {
1446 cfg->vret_addr->inst_offset = offset;
1450 cfg->vret_addr->inst_offset = -offset;
1452 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1453 printf ("vret_addr =");
1454 mono_print_ins (cfg->vret_addr);
1459 cfg->ret->opcode = OP_REGVAR;
1460 cfg->ret->inst_c0 = cinfo->ret.reg;
1463 case ArgValuetypeInReg:
1464 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1465 cfg->ret->opcode = OP_REGOFFSET;
1466 cfg->ret->inst_basereg = cfg->frame_reg;
1467 if (cfg->arch.omit_fp) {
1468 cfg->ret->inst_offset = offset;
1472 cfg->ret->inst_offset = - offset;
1476 g_assert_not_reached ();
1479 cfg->ret->dreg = cfg->ret->inst_c0;
1482 /* Allocate locals */
1483 if (!cfg->globalra) {
1484 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1485 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1486 char *mname = mono_method_full_name (cfg->method, TRUE);
1487 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1488 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1493 if (locals_stack_align) {
1494 offset += (locals_stack_align - 1);
1495 offset &= ~(locals_stack_align - 1);
1497 if (cfg->arch.omit_fp) {
1498 cfg->locals_min_stack_offset = offset;
1499 cfg->locals_max_stack_offset = offset + locals_stack_size;
1501 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1502 cfg->locals_max_stack_offset = - offset;
1505 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1506 if (offsets [i] != -1) {
1507 MonoInst *ins = cfg->varinfo [i];
1508 ins->opcode = OP_REGOFFSET;
1509 ins->inst_basereg = cfg->frame_reg;
1510 if (cfg->arch.omit_fp)
1511 ins->inst_offset = (offset + offsets [i]);
1513 ins->inst_offset = - (offset + offsets [i]);
1514 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1517 offset += locals_stack_size;
1520 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1521 g_assert (!cfg->arch.omit_fp);
1522 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1523 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1526 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1527 ins = cfg->args [i];
1528 if (ins->opcode != OP_REGVAR) {
1529 ArgInfo *ainfo = &cinfo->args [i];
1530 gboolean inreg = TRUE;
1533 if (sig->hasthis && (i == 0))
1534 arg_type = &mono_defaults.object_class->byval_arg;
1536 arg_type = sig->params [i - sig->hasthis];
1538 if (cfg->globalra) {
1539 /* The new allocator needs info about the original locations of the arguments */
1540 switch (ainfo->storage) {
1542 case ArgInFloatSSEReg:
1543 case ArgInDoubleSSEReg:
1544 ins->opcode = OP_REGVAR;
1545 ins->inst_c0 = ainfo->reg;
1548 g_assert (!cfg->arch.omit_fp);
1549 ins->opcode = OP_REGOFFSET;
1550 ins->inst_basereg = cfg->frame_reg;
1551 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1553 case ArgValuetypeInReg:
1554 ins->opcode = OP_REGOFFSET;
1555 ins->inst_basereg = cfg->frame_reg;
1556 /* These arguments are saved to the stack in the prolog */
1557 offset = ALIGN_TO (offset, sizeof (gpointer));
1558 if (cfg->arch.omit_fp) {
1559 ins->inst_offset = offset;
1560 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1562 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1563 ins->inst_offset = - offset;
1567 g_assert_not_reached ();
1573 /* FIXME: Allocate volatile arguments to registers */
1574 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1578 * Under AMD64, all registers used to pass arguments to functions
1579 * are volatile across calls.
1580 * FIXME: Optimize this.
1582 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1585 ins->opcode = OP_REGOFFSET;
1587 switch (ainfo->storage) {
1589 case ArgInFloatSSEReg:
1590 case ArgInDoubleSSEReg:
1592 ins->opcode = OP_REGVAR;
1593 ins->dreg = ainfo->reg;
1597 g_assert (!cfg->arch.omit_fp);
1598 ins->opcode = OP_REGOFFSET;
1599 ins->inst_basereg = cfg->frame_reg;
1600 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1602 case ArgValuetypeInReg:
1604 case ArgValuetypeAddrInIReg: {
1606 g_assert (!cfg->arch.omit_fp);
1608 MONO_INST_NEW (cfg, indir, 0);
1609 indir->opcode = OP_REGOFFSET;
1610 if (ainfo->pair_storage [0] == ArgInIReg) {
1611 indir->inst_basereg = cfg->frame_reg;
1612 offset = ALIGN_TO (offset, sizeof (gpointer));
1613 offset += (sizeof (gpointer));
1614 indir->inst_offset = - offset;
1617 indir->inst_basereg = cfg->frame_reg;
1618 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1621 ins->opcode = OP_VTARG_ADDR;
1622 ins->inst_left = indir;
1630 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1631 ins->opcode = OP_REGOFFSET;
1632 ins->inst_basereg = cfg->frame_reg;
1633 /* These arguments are saved to the stack in the prolog */
1634 offset = ALIGN_TO (offset, sizeof (gpointer));
1635 if (cfg->arch.omit_fp) {
1636 ins->inst_offset = offset;
1637 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1638 // Arguments are yet supported by the stack map creation code
1639 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1641 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1642 ins->inst_offset = - offset;
1643 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1649 cfg->stack_offset = offset;
1653 mono_arch_create_vars (MonoCompile *cfg)
1655 MonoMethodSignature *sig;
1658 sig = mono_method_signature (cfg->method);
1660 if (!cfg->arch.cinfo)
1661 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1662 cinfo = cfg->arch.cinfo;
1664 if (cinfo->ret.storage == ArgValuetypeInReg)
1665 cfg->ret_var_is_local = TRUE;
1667 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1668 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1669 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1670 printf ("vret_addr = ");
1671 mono_print_ins (cfg->vret_addr);
1675 if (cfg->gen_seq_points) {
1678 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1679 ins->flags |= MONO_INST_VOLATILE;
1680 cfg->arch.ss_trigger_page_var = ins;
1683 #ifdef MONO_AMD64_NO_PUSHES
1685 * When this is set, we pass arguments on the stack by moves, and by allocating
1686 * a bigger stack frame, instead of pushes.
1687 * Pushes complicate exception handling because the arguments on the stack have
1688 * to be popped each time a frame is unwound. They also make fp elimination
1690 * FIXME: This doesn't work inside filter/finally clauses, since those execute
1691 * on a new frame which doesn't include a param area.
1693 cfg->arch.no_pushes = TRUE;
1698 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1704 MONO_INST_NEW (cfg, ins, OP_MOVE);
1705 ins->dreg = mono_alloc_ireg (cfg);
1706 ins->sreg1 = tree->dreg;
1707 MONO_ADD_INS (cfg->cbb, ins);
1708 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1710 case ArgInFloatSSEReg:
1711 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1712 ins->dreg = mono_alloc_freg (cfg);
1713 ins->sreg1 = tree->dreg;
1714 MONO_ADD_INS (cfg->cbb, ins);
1716 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1718 case ArgInDoubleSSEReg:
1719 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1720 ins->dreg = mono_alloc_freg (cfg);
1721 ins->sreg1 = tree->dreg;
1722 MONO_ADD_INS (cfg->cbb, ins);
1724 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1728 g_assert_not_reached ();
1733 arg_storage_to_load_membase (ArgStorage storage)
1737 return OP_LOAD_MEMBASE;
1738 case ArgInDoubleSSEReg:
1739 return OP_LOADR8_MEMBASE;
1740 case ArgInFloatSSEReg:
1741 return OP_LOADR4_MEMBASE;
1743 g_assert_not_reached ();
1750 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1753 MonoMethodSignature *tmp_sig;
1756 if (call->tail_call)
1759 /* FIXME: Add support for signature tokens to AOT */
1760 cfg->disable_aot = TRUE;
1762 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1765 * mono_ArgIterator_Setup assumes the signature cookie is
1766 * passed first and all the arguments which were before it are
1767 * passed on the stack after the signature. So compensate by
1768 * passing a different signature.
1770 tmp_sig = mono_metadata_signature_dup (call->signature);
1771 tmp_sig->param_count -= call->signature->sentinelpos;
1772 tmp_sig->sentinelpos = 0;
1773 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1775 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1776 sig_arg->dreg = mono_alloc_ireg (cfg);
1777 sig_arg->inst_p0 = tmp_sig;
1778 MONO_ADD_INS (cfg->cbb, sig_arg);
1780 if (cfg->arch.no_pushes) {
1781 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1783 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1784 arg->sreg1 = sig_arg->dreg;
1785 MONO_ADD_INS (cfg->cbb, arg);
1789 static inline LLVMArgStorage
1790 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1794 return LLVMArgInIReg;
1798 g_assert_not_reached ();
1805 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1811 LLVMCallInfo *linfo;
1814 n = sig->param_count + sig->hasthis;
1816 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1818 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1821 * LLVM always uses the native ABI while we use our own ABI, the
1822 * only difference is the handling of vtypes:
1823 * - we only pass/receive them in registers in some cases, and only
1824 * in 1 or 2 integer registers.
1826 if (cinfo->ret.storage == ArgValuetypeInReg) {
1828 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1829 cfg->disable_llvm = TRUE;
1833 linfo->ret.storage = LLVMArgVtypeInReg;
1834 for (j = 0; j < 2; ++j)
1835 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1838 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1839 /* Vtype returned using a hidden argument */
1840 linfo->ret.storage = LLVMArgVtypeRetAddr;
1841 linfo->vret_arg_index = cinfo->vret_arg_index;
1844 for (i = 0; i < n; ++i) {
1845 ainfo = cinfo->args + i;
1847 if (i >= sig->hasthis)
1848 t = sig->params [i - sig->hasthis];
1850 t = &mono_defaults.int_class->byval_arg;
1852 linfo->args [i].storage = LLVMArgNone;
1854 switch (ainfo->storage) {
1856 linfo->args [i].storage = LLVMArgInIReg;
1858 case ArgInDoubleSSEReg:
1859 case ArgInFloatSSEReg:
1860 linfo->args [i].storage = LLVMArgInFPReg;
1863 if (MONO_TYPE_ISSTRUCT (t)) {
1864 linfo->args [i].storage = LLVMArgVtypeByVal;
1866 linfo->args [i].storage = LLVMArgInIReg;
1868 if (t->type == MONO_TYPE_R4)
1869 linfo->args [i].storage = LLVMArgInFPReg;
1870 else if (t->type == MONO_TYPE_R8)
1871 linfo->args [i].storage = LLVMArgInFPReg;
1875 case ArgValuetypeInReg:
1877 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1878 cfg->disable_llvm = TRUE;
1882 linfo->args [i].storage = LLVMArgVtypeInReg;
1883 for (j = 0; j < 2; ++j)
1884 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1887 cfg->exception_message = g_strdup ("ainfo->storage");
1888 cfg->disable_llvm = TRUE;
1898 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1901 MonoMethodSignature *sig;
1902 int i, n, stack_size;
1908 sig = call->signature;
1909 n = sig->param_count + sig->hasthis;
1911 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1913 if (COMPILE_LLVM (cfg)) {
1914 /* We shouldn't be called in the llvm case */
1915 cfg->disable_llvm = TRUE;
1919 if (cinfo->need_stack_align) {
1920 if (!cfg->arch.no_pushes)
1921 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1925 * Emit all arguments which are passed on the stack to prevent register
1926 * allocation problems.
1928 if (cfg->arch.no_pushes) {
1929 for (i = 0; i < n; ++i) {
1931 ainfo = cinfo->args + i;
1933 in = call->args [i];
1935 if (sig->hasthis && i == 0)
1936 t = &mono_defaults.object_class->byval_arg;
1938 t = sig->params [i - sig->hasthis];
1940 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1942 if (t->type == MONO_TYPE_R4)
1943 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1944 else if (t->type == MONO_TYPE_R8)
1945 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1947 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1949 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1956 * Emit all parameters passed in registers in non-reverse order for better readability
1957 * and to help the optimization in emit_prolog ().
1959 for (i = 0; i < n; ++i) {
1960 ainfo = cinfo->args + i;
1962 in = call->args [i];
1964 if (ainfo->storage == ArgInIReg)
1965 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1968 for (i = n - 1; i >= 0; --i) {
1969 ainfo = cinfo->args + i;
1971 in = call->args [i];
1973 switch (ainfo->storage) {
1977 case ArgInFloatSSEReg:
1978 case ArgInDoubleSSEReg:
1979 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1982 case ArgValuetypeInReg:
1983 case ArgValuetypeAddrInIReg:
1984 if (ainfo->storage == ArgOnStack && call->tail_call) {
1985 MonoInst *call_inst = (MonoInst*)call;
1986 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1987 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1988 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1992 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1993 size = sizeof (MonoTypedRef);
1994 align = sizeof (gpointer);
1998 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2001 * Other backends use mono_type_stack_size (), but that
2002 * aligns the size to 8, which is larger than the size of
2003 * the source, leading to reads of invalid memory if the
2004 * source is at the end of address space.
2006 size = mono_class_value_size (in->klass, &align);
2009 g_assert (in->klass);
2011 if (ainfo->storage == ArgOnStack && size >= 10000) {
2012 /* Avoid asserts in emit_memcpy () */
2013 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2014 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2015 /* Continue normally */
2019 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2020 arg->sreg1 = in->dreg;
2021 arg->klass = in->klass;
2022 arg->backend.size = size;
2023 arg->inst_p0 = call;
2024 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2025 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2027 MONO_ADD_INS (cfg->cbb, arg);
2030 if (cfg->arch.no_pushes) {
2033 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2034 arg->sreg1 = in->dreg;
2035 if (!sig->params [i - sig->hasthis]->byref) {
2036 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2037 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2038 arg->opcode = OP_STORER4_MEMBASE_REG;
2039 arg->inst_destbasereg = X86_ESP;
2040 arg->inst_offset = 0;
2041 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2042 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2043 arg->opcode = OP_STORER8_MEMBASE_REG;
2044 arg->inst_destbasereg = X86_ESP;
2045 arg->inst_offset = 0;
2048 MONO_ADD_INS (cfg->cbb, arg);
2053 g_assert_not_reached ();
2056 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2057 /* Emit the signature cookie just before the implicit arguments */
2058 emit_sig_cookie (cfg, call, cinfo);
2061 /* Handle the case where there are no implicit arguments */
2062 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2063 emit_sig_cookie (cfg, call, cinfo);
2065 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2068 if (cinfo->ret.storage == ArgValuetypeInReg) {
2069 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2071 * Tell the JIT to use a more efficient calling convention: call using
2072 * OP_CALL, compute the result location after the call, and save the
2075 call->vret_in_reg = TRUE;
2077 * Nullify the instruction computing the vret addr to enable
2078 * future optimizations.
2081 NULLIFY_INS (call->vret_var);
2083 if (call->tail_call)
2086 * The valuetype is in RAX:RDX after the call, need to be copied to
2087 * the stack. Push the address here, so the call instruction can
2090 if (!cfg->arch.vret_addr_loc) {
2091 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2092 /* Prevent it from being register allocated or optimized away */
2093 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2096 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2100 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2101 vtarg->sreg1 = call->vret_var->dreg;
2102 vtarg->dreg = mono_alloc_preg (cfg);
2103 MONO_ADD_INS (cfg->cbb, vtarg);
2105 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2110 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2111 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2115 if (cfg->method->save_lmf) {
2116 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2117 MONO_ADD_INS (cfg->cbb, arg);
2120 call->stack_usage = cinfo->stack_usage;
2124 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2127 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2128 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2129 int size = ins->backend.size;
2131 if (ainfo->storage == ArgValuetypeInReg) {
2135 for (part = 0; part < 2; ++part) {
2136 if (ainfo->pair_storage [part] == ArgNone)
2139 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2140 load->inst_basereg = src->dreg;
2141 load->inst_offset = part * sizeof (gpointer);
2143 switch (ainfo->pair_storage [part]) {
2145 load->dreg = mono_alloc_ireg (cfg);
2147 case ArgInDoubleSSEReg:
2148 case ArgInFloatSSEReg:
2149 load->dreg = mono_alloc_freg (cfg);
2152 g_assert_not_reached ();
2154 MONO_ADD_INS (cfg->cbb, load);
2156 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2158 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2159 MonoInst *vtaddr, *load;
2160 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2162 g_assert (!cfg->arch.no_pushes);
2164 MONO_INST_NEW (cfg, load, OP_LDADDR);
2165 load->inst_p0 = vtaddr;
2166 vtaddr->flags |= MONO_INST_INDIRECT;
2167 load->type = STACK_MP;
2168 load->klass = vtaddr->klass;
2169 load->dreg = mono_alloc_ireg (cfg);
2170 MONO_ADD_INS (cfg->cbb, load);
2171 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2173 if (ainfo->pair_storage [0] == ArgInIReg) {
2174 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2175 arg->dreg = mono_alloc_ireg (cfg);
2176 arg->sreg1 = load->dreg;
2178 MONO_ADD_INS (cfg->cbb, arg);
2179 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2181 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2182 arg->sreg1 = load->dreg;
2183 MONO_ADD_INS (cfg->cbb, arg);
2187 if (cfg->arch.no_pushes) {
2188 int dreg = mono_alloc_ireg (cfg);
2190 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2191 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2193 /* Can't use this for < 8 since it does an 8 byte memory load */
2194 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2195 arg->inst_basereg = src->dreg;
2196 arg->inst_offset = 0;
2197 MONO_ADD_INS (cfg->cbb, arg);
2199 } else if (size <= 40) {
2200 if (cfg->arch.no_pushes) {
2201 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2203 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2204 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2207 if (cfg->arch.no_pushes) {
2208 // FIXME: Code growth
2209 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2211 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2212 arg->inst_basereg = src->dreg;
2213 arg->inst_offset = 0;
2214 arg->inst_imm = size;
2215 MONO_ADD_INS (cfg->cbb, arg);
2222 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2224 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2226 if (ret->type == MONO_TYPE_R4) {
2227 if (COMPILE_LLVM (cfg))
2228 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2230 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2232 } else if (ret->type == MONO_TYPE_R8) {
2233 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2237 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2240 #endif /* DISABLE_JIT */
2242 #define EMIT_COND_BRANCH(ins,cond,sign) \
2243 if (ins->inst_true_bb->native_offset) { \
2244 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2246 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2247 if ((cfg->opt & MONO_OPT_BRANCH) && \
2248 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2249 x86_branch8 (code, cond, 0, sign); \
2251 x86_branch32 (code, cond, 0, sign); \
2255 MonoMethodSignature *sig;
2260 mgreg_t regs [PARAM_REGS];
2266 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2274 switch (cinfo->ret.storage) {
2278 case ArgValuetypeInReg: {
2279 ArgInfo *ainfo = &cinfo->ret;
2281 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2283 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2291 for (i = 0; i < cinfo->nargs; ++i) {
2292 ArgInfo *ainfo = &cinfo->args [i];
2293 switch (ainfo->storage) {
2296 case ArgValuetypeInReg:
2297 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2299 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2311 * mono_arch_dyn_call_prepare:
2313 * Return a pointer to an arch-specific structure which contains information
2314 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2315 * supported for SIG.
2316 * This function is equivalent to ffi_prep_cif in libffi.
2319 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2321 ArchDynCallInfo *info;
2324 cinfo = get_call_info (NULL, NULL, sig, FALSE);
2326 if (!dyn_call_supported (sig, cinfo)) {
2331 info = g_new0 (ArchDynCallInfo, 1);
2332 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2334 info->cinfo = cinfo;
2336 return (MonoDynCallInfo*)info;
2340 * mono_arch_dyn_call_free:
2342 * Free a MonoDynCallInfo structure.
2345 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2347 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2349 g_free (ainfo->cinfo);
2354 * mono_arch_get_start_dyn_call:
2356 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2357 * store the result into BUF.
2358 * ARGS should be an array of pointers pointing to the arguments.
2359 * RET should point to a memory buffer large enought to hold the result of the
2361 * This function should be as fast as possible, any work which does not depend
2362 * on the actual values of the arguments should be done in
2363 * mono_arch_dyn_call_prepare ().
2364 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2368 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2370 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2371 DynCallArgs *p = (DynCallArgs*)buf;
2372 int arg_index, greg, i, pindex;
2373 MonoMethodSignature *sig = dinfo->sig;
2375 g_assert (buf_len >= sizeof (DynCallArgs));
2384 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2385 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2390 if (dinfo->cinfo->vtype_retaddr)
2391 p->regs [greg ++] = (mgreg_t)ret;
2393 for (i = pindex; i < sig->param_count; i++) {
2394 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2395 gpointer *arg = args [arg_index ++];
2398 p->regs [greg ++] = (mgreg_t)*(arg);
2403 case MONO_TYPE_STRING:
2404 case MONO_TYPE_CLASS:
2405 case MONO_TYPE_ARRAY:
2406 case MONO_TYPE_SZARRAY:
2407 case MONO_TYPE_OBJECT:
2413 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2414 p->regs [greg ++] = (mgreg_t)*(arg);
2416 case MONO_TYPE_BOOLEAN:
2418 p->regs [greg ++] = *(guint8*)(arg);
2421 p->regs [greg ++] = *(gint8*)(arg);
2424 p->regs [greg ++] = *(gint16*)(arg);
2427 case MONO_TYPE_CHAR:
2428 p->regs [greg ++] = *(guint16*)(arg);
2431 p->regs [greg ++] = *(gint32*)(arg);
2434 p->regs [greg ++] = *(guint32*)(arg);
2436 case MONO_TYPE_GENERICINST:
2437 if (MONO_TYPE_IS_REFERENCE (t)) {
2438 p->regs [greg ++] = (mgreg_t)*(arg);
2443 case MONO_TYPE_VALUETYPE: {
2444 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2446 g_assert (ainfo->storage == ArgValuetypeInReg);
2447 if (ainfo->pair_storage [0] != ArgNone) {
2448 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2449 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2451 if (ainfo->pair_storage [1] != ArgNone) {
2452 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2453 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2458 g_assert_not_reached ();
2462 g_assert (greg <= PARAM_REGS);
2466 * mono_arch_finish_dyn_call:
2468 * Store the result of a dyn call into the return value buffer passed to
2469 * start_dyn_call ().
2470 * This function should be as fast as possible, any work which does not depend
2471 * on the actual values of the arguments should be done in
2472 * mono_arch_dyn_call_prepare ().
2475 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2477 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2478 MonoMethodSignature *sig = dinfo->sig;
2479 guint8 *ret = ((DynCallArgs*)buf)->ret;
2480 mgreg_t res = ((DynCallArgs*)buf)->res;
2482 switch (mono_type_get_underlying_type (sig->ret)->type) {
2483 case MONO_TYPE_VOID:
2484 *(gpointer*)ret = NULL;
2486 case MONO_TYPE_STRING:
2487 case MONO_TYPE_CLASS:
2488 case MONO_TYPE_ARRAY:
2489 case MONO_TYPE_SZARRAY:
2490 case MONO_TYPE_OBJECT:
2494 *(gpointer*)ret = (gpointer)res;
2500 case MONO_TYPE_BOOLEAN:
2501 *(guint8*)ret = res;
2504 *(gint16*)ret = res;
2507 case MONO_TYPE_CHAR:
2508 *(guint16*)ret = res;
2511 *(gint32*)ret = res;
2514 *(guint32*)ret = res;
2517 *(gint64*)ret = res;
2520 *(guint64*)ret = res;
2522 case MONO_TYPE_GENERICINST:
2523 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2524 *(gpointer*)ret = (gpointer)res;
2529 case MONO_TYPE_VALUETYPE:
2530 if (dinfo->cinfo->vtype_retaddr) {
2533 ArgInfo *ainfo = &dinfo->cinfo->ret;
2535 g_assert (ainfo->storage == ArgValuetypeInReg);
2537 if (ainfo->pair_storage [0] != ArgNone) {
2538 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2539 ((mgreg_t*)ret)[0] = res;
2542 g_assert (ainfo->pair_storage [1] == ArgNone);
2546 g_assert_not_reached ();
2550 /* emit an exception if condition is fail */
2551 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2553 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2554 if (tins == NULL) { \
2555 mono_add_patch_info (cfg, code - cfg->native_code, \
2556 MONO_PATCH_INFO_EXC, exc_name); \
2557 x86_branch32 (code, cond, 0, signed); \
2559 EMIT_COND_BRANCH (tins, cond, signed); \
2563 #define EMIT_FPCOMPARE(code) do { \
2564 amd64_fcompp (code); \
2565 amd64_fnstsw (code); \
2568 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2569 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2570 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2571 amd64_ ##op (code); \
2572 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2573 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2577 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2579 gboolean no_patch = FALSE;
2582 * FIXME: Add support for thunks
2585 gboolean near_call = FALSE;
2588 * Indirect calls are expensive so try to make a near call if possible.
2589 * The caller memory is allocated by the code manager so it is
2590 * guaranteed to be at a 32 bit offset.
2593 if (patch_type != MONO_PATCH_INFO_ABS) {
2594 /* The target is in memory allocated using the code manager */
2597 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2598 if (((MonoMethod*)data)->klass->image->aot_module)
2599 /* The callee might be an AOT method */
2601 if (((MonoMethod*)data)->dynamic)
2602 /* The target is in malloc-ed memory */
2606 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2608 * The call might go directly to a native function without
2611 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2613 gconstpointer target = mono_icall_get_wrapper (mi);
2614 if ((((guint64)target) >> 32) != 0)
2620 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2622 * This is not really an optimization, but required because the
2623 * generic class init trampolines use R11 to pass the vtable.
2627 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2629 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2630 strstr (cfg->method->name, info->name)) {
2631 /* A call to the wrapped function */
2632 if ((((guint64)data) >> 32) == 0)
2636 else if (info->func == info->wrapper) {
2638 if ((((guint64)info->func) >> 32) == 0)
2642 /* See the comment in mono_codegen () */
2643 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2647 else if ((((guint64)data) >> 32) == 0) {
2654 if (cfg->method->dynamic)
2655 /* These methods are allocated using malloc */
2658 #ifdef MONO_ARCH_NOMAP32BIT
2662 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2663 if (optimize_for_xen)
2666 if (cfg->compile_aot) {
2673 * Align the call displacement to an address divisible by 4 so it does
2674 * not span cache lines. This is required for code patching to work on SMP
2677 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2678 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2679 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2680 amd64_call_code (code, 0);
2683 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2684 amd64_set_reg_template (code, GP_SCRATCH_REG);
2685 amd64_call_reg (code, GP_SCRATCH_REG);
2692 static inline guint8*
2693 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2696 if (win64_adjust_stack)
2697 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2699 code = emit_call_body (cfg, code, patch_type, data);
2701 if (win64_adjust_stack)
2702 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2709 store_membase_imm_to_store_membase_reg (int opcode)
2712 case OP_STORE_MEMBASE_IMM:
2713 return OP_STORE_MEMBASE_REG;
2714 case OP_STOREI4_MEMBASE_IMM:
2715 return OP_STOREI4_MEMBASE_REG;
2716 case OP_STOREI8_MEMBASE_IMM:
2717 return OP_STOREI8_MEMBASE_REG;
2725 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2728 * mono_arch_peephole_pass_1:
2730 * Perform peephole opts which should/can be performed before local regalloc
2733 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2737 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2738 MonoInst *last_ins = ins->prev;
2740 switch (ins->opcode) {
2744 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2746 * X86_LEA is like ADD, but doesn't have the
2747 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2748 * its operand to 64 bit.
2750 ins->opcode = OP_X86_LEA_MEMBASE;
2751 ins->inst_basereg = ins->sreg1;
2756 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2760 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2761 * the latter has length 2-3 instead of 6 (reverse constant
2762 * propagation). These instruction sequences are very common
2763 * in the initlocals bblock.
2765 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2766 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2767 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2768 ins2->sreg1 = ins->dreg;
2769 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2771 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2780 case OP_COMPARE_IMM:
2781 case OP_LCOMPARE_IMM:
2782 /* OP_COMPARE_IMM (reg, 0)
2784 * OP_AMD64_TEST_NULL (reg)
2787 ins->opcode = OP_AMD64_TEST_NULL;
2789 case OP_ICOMPARE_IMM:
2791 ins->opcode = OP_X86_TEST_NULL;
2793 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2795 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2796 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2798 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2799 * OP_COMPARE_IMM reg, imm
2801 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2803 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2804 ins->inst_basereg == last_ins->inst_destbasereg &&
2805 ins->inst_offset == last_ins->inst_offset) {
2806 ins->opcode = OP_ICOMPARE_IMM;
2807 ins->sreg1 = last_ins->sreg1;
2809 /* check if we can remove cmp reg,0 with test null */
2811 ins->opcode = OP_X86_TEST_NULL;
2817 mono_peephole_ins (bb, ins);
2822 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2826 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2827 switch (ins->opcode) {
2830 /* reg = 0 -> XOR (reg, reg) */
2831 /* XOR sets cflags on x86, so we cant do it always */
2832 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2833 ins->opcode = OP_LXOR;
2834 ins->sreg1 = ins->dreg;
2835 ins->sreg2 = ins->dreg;
2843 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2844 * 0 result into 64 bits.
2846 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2847 ins->opcode = OP_IXOR;
2851 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2855 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2856 * the latter has length 2-3 instead of 6 (reverse constant
2857 * propagation). These instruction sequences are very common
2858 * in the initlocals bblock.
2860 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2861 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2862 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2863 ins2->sreg1 = ins->dreg;
2864 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2866 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2876 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2877 ins->opcode = OP_X86_INC_REG;
2880 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2881 ins->opcode = OP_X86_DEC_REG;
2885 mono_peephole_ins (bb, ins);
2889 #define NEW_INS(cfg,ins,dest,op) do { \
2890 MONO_INST_NEW ((cfg), (dest), (op)); \
2891 (dest)->cil_code = (ins)->cil_code; \
2892 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2896 * mono_arch_lowering_pass:
2898 * Converts complex opcodes into simpler ones so that each IR instruction
2899 * corresponds to one machine instruction.
2902 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2904 MonoInst *ins, *n, *temp;
2907 * FIXME: Need to add more instructions, but the current machine
2908 * description can't model some parts of the composite instructions like
2911 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2912 switch (ins->opcode) {
2916 case OP_IDIV_UN_IMM:
2917 case OP_IREM_UN_IMM:
2918 mono_decompose_op_imm (cfg, bb, ins);
2921 /* Keep the opcode if we can implement it efficiently */
2922 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2923 mono_decompose_op_imm (cfg, bb, ins);
2925 case OP_COMPARE_IMM:
2926 case OP_LCOMPARE_IMM:
2927 if (!amd64_is_imm32 (ins->inst_imm)) {
2928 NEW_INS (cfg, ins, temp, OP_I8CONST);
2929 temp->inst_c0 = ins->inst_imm;
2930 temp->dreg = mono_alloc_ireg (cfg);
2931 ins->opcode = OP_COMPARE;
2932 ins->sreg2 = temp->dreg;
2935 case OP_LOAD_MEMBASE:
2936 case OP_LOADI8_MEMBASE:
2937 if (!amd64_is_imm32 (ins->inst_offset)) {
2938 NEW_INS (cfg, ins, temp, OP_I8CONST);
2939 temp->inst_c0 = ins->inst_offset;
2940 temp->dreg = mono_alloc_ireg (cfg);
2941 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2942 ins->inst_indexreg = temp->dreg;
2945 case OP_STORE_MEMBASE_IMM:
2946 case OP_STOREI8_MEMBASE_IMM:
2947 if (!amd64_is_imm32 (ins->inst_imm)) {
2948 NEW_INS (cfg, ins, temp, OP_I8CONST);
2949 temp->inst_c0 = ins->inst_imm;
2950 temp->dreg = mono_alloc_ireg (cfg);
2951 ins->opcode = OP_STOREI8_MEMBASE_REG;
2952 ins->sreg1 = temp->dreg;
2955 #ifdef MONO_ARCH_SIMD_INTRINSICS
2956 case OP_EXPAND_I1: {
2957 int temp_reg1 = mono_alloc_ireg (cfg);
2958 int temp_reg2 = mono_alloc_ireg (cfg);
2959 int original_reg = ins->sreg1;
2961 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2962 temp->sreg1 = original_reg;
2963 temp->dreg = temp_reg1;
2965 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2966 temp->sreg1 = temp_reg1;
2967 temp->dreg = temp_reg2;
2970 NEW_INS (cfg, ins, temp, OP_LOR);
2971 temp->sreg1 = temp->dreg = temp_reg2;
2972 temp->sreg2 = temp_reg1;
2974 ins->opcode = OP_EXPAND_I2;
2975 ins->sreg1 = temp_reg2;
2984 bb->max_vreg = cfg->next_vreg;
2988 branch_cc_table [] = {
2989 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2990 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2991 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2994 /* Maps CMP_... constants to X86_CC_... constants */
2997 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2998 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3002 cc_signed_table [] = {
3003 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3004 FALSE, FALSE, FALSE, FALSE
3007 /*#include "cprop.c"*/
3009 static unsigned char*
3010 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3012 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3015 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3017 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3021 static unsigned char*
3022 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3024 int sreg = tree->sreg1;
3025 int need_touch = FALSE;
3027 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3028 if (!tree->flags & MONO_INST_INIT)
3037 * If requested stack size is larger than one page,
3038 * perform stack-touch operation
3041 * Generate stack probe code.
3042 * Under Windows, it is necessary to allocate one page at a time,
3043 * "touching" stack after each successful sub-allocation. This is
3044 * because of the way stack growth is implemented - there is a
3045 * guard page before the lowest stack page that is currently commited.
3046 * Stack normally grows sequentially so OS traps access to the
3047 * guard page and commits more pages when needed.
3049 amd64_test_reg_imm (code, sreg, ~0xFFF);
3050 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3052 br[2] = code; /* loop */
3053 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3054 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3055 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3056 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3057 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3058 amd64_patch (br[3], br[2]);
3059 amd64_test_reg_reg (code, sreg, sreg);
3060 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3061 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3063 br[1] = code; x86_jump8 (code, 0);
3065 amd64_patch (br[0], code);
3066 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3067 amd64_patch (br[1], code);
3068 amd64_patch (br[4], code);
3071 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3073 if (tree->flags & MONO_INST_INIT) {
3075 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3076 amd64_push_reg (code, AMD64_RAX);
3079 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3080 amd64_push_reg (code, AMD64_RCX);
3083 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3084 amd64_push_reg (code, AMD64_RDI);
3088 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3089 if (sreg != AMD64_RCX)
3090 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3091 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3093 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3094 if (cfg->param_area && cfg->arch.no_pushes)
3095 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3097 amd64_prefix (code, X86_REP_PREFIX);
3100 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3101 amd64_pop_reg (code, AMD64_RDI);
3102 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3103 amd64_pop_reg (code, AMD64_RCX);
3104 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3105 amd64_pop_reg (code, AMD64_RAX);
3111 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3116 /* Move return value to the target register */
3117 /* FIXME: do this in the local reg allocator */
3118 switch (ins->opcode) {
3121 case OP_CALL_MEMBASE:
3124 case OP_LCALL_MEMBASE:
3125 g_assert (ins->dreg == AMD64_RAX);
3129 case OP_FCALL_MEMBASE:
3130 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3131 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3134 if (ins->dreg != AMD64_XMM0)
3135 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3140 case OP_VCALL_MEMBASE:
3143 case OP_VCALL2_MEMBASE:
3144 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3145 if (cinfo->ret.storage == ArgValuetypeInReg) {
3146 MonoInst *loc = cfg->arch.vret_addr_loc;
3148 /* Load the destination address */
3149 g_assert (loc->opcode == OP_REGOFFSET);
3150 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3152 for (quad = 0; quad < 2; quad ++) {
3153 switch (cinfo->ret.pair_storage [quad]) {
3155 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3157 case ArgInFloatSSEReg:
3158 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3160 case ArgInDoubleSSEReg:
3161 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3176 #endif /* DISABLE_JIT */
3179 * mono_amd64_emit_tls_get:
3180 * @code: buffer to store code to
3181 * @dreg: hard register where to place the result
3182 * @tls_offset: offset info
3184 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3185 * the dreg register the item in the thread local storage identified
3188 * Returns: a pointer to the end of the stored code
3191 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3194 g_assert (tls_offset < 64);
3195 x86_prefix (code, X86_GS_PREFIX);
3196 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3198 if (optimize_for_xen) {
3199 x86_prefix (code, X86_FS_PREFIX);
3200 amd64_mov_reg_mem (code, dreg, 0, 8);
3201 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3203 x86_prefix (code, X86_FS_PREFIX);
3204 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3210 #define REAL_PRINT_REG(text,reg) \
3211 mono_assert (reg >= 0); \
3212 amd64_push_reg (code, AMD64_RAX); \
3213 amd64_push_reg (code, AMD64_RDX); \
3214 amd64_push_reg (code, AMD64_RCX); \
3215 amd64_push_reg (code, reg); \
3216 amd64_push_imm (code, reg); \
3217 amd64_push_imm (code, text " %d %p\n"); \
3218 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3219 amd64_call_reg (code, AMD64_RAX); \
3220 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3221 amd64_pop_reg (code, AMD64_RCX); \
3222 amd64_pop_reg (code, AMD64_RDX); \
3223 amd64_pop_reg (code, AMD64_RAX);
3225 /* benchmark and set based on cpu */
3226 #define LOOP_ALIGNMENT 8
3227 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3232 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3237 guint8 *code = cfg->native_code + cfg->code_len;
3238 MonoInst *last_ins = NULL;
3239 guint last_offset = 0;
3242 /* Fix max_offset estimate for each successor bb */
3243 if (cfg->opt & MONO_OPT_BRANCH) {
3244 int current_offset = cfg->code_len;
3245 MonoBasicBlock *current_bb;
3246 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3247 current_bb->max_offset = current_offset;
3248 current_offset += current_bb->max_length;
3252 if (cfg->opt & MONO_OPT_LOOP) {
3253 int pad, align = LOOP_ALIGNMENT;
3254 /* set alignment depending on cpu */
3255 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3257 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3258 amd64_padding (code, pad);
3259 cfg->code_len += pad;
3260 bb->native_offset = cfg->code_len;
3264 if (cfg->verbose_level > 2)
3265 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3267 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3268 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3269 g_assert (!cfg->compile_aot);
3271 cov->data [bb->dfn].cil_code = bb->cil_code;
3272 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3273 /* this is not thread save, but good enough */
3274 amd64_inc_membase (code, AMD64_R11, 0);
3277 offset = code - cfg->native_code;
3279 mono_debug_open_block (cfg, bb, offset);
3281 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3282 x86_breakpoint (code);
3284 MONO_BB_FOR_EACH_INS (bb, ins) {
3285 offset = code - cfg->native_code;
3287 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3289 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3290 cfg->code_size *= 2;
3291 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3292 code = cfg->native_code + offset;
3293 mono_jit_stats.code_reallocs++;
3296 if (cfg->debug_info)
3297 mono_debug_record_line_number (cfg, ins, offset);
3299 switch (ins->opcode) {
3301 amd64_mul_reg (code, ins->sreg2, TRUE);
3304 amd64_mul_reg (code, ins->sreg2, FALSE);
3306 case OP_X86_SETEQ_MEMBASE:
3307 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3309 case OP_STOREI1_MEMBASE_IMM:
3310 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3312 case OP_STOREI2_MEMBASE_IMM:
3313 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3315 case OP_STOREI4_MEMBASE_IMM:
3316 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3318 case OP_STOREI1_MEMBASE_REG:
3319 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3321 case OP_STOREI2_MEMBASE_REG:
3322 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3324 case OP_STORE_MEMBASE_REG:
3325 case OP_STOREI8_MEMBASE_REG:
3326 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3328 case OP_STOREI4_MEMBASE_REG:
3329 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3331 case OP_STORE_MEMBASE_IMM:
3332 case OP_STOREI8_MEMBASE_IMM:
3333 g_assert (amd64_is_imm32 (ins->inst_imm));
3334 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3338 // FIXME: Decompose this earlier
3339 if (amd64_is_imm32 (ins->inst_imm))
3340 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3342 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3343 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3347 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3348 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3351 // FIXME: Decompose this earlier
3352 if (amd64_is_imm32 (ins->inst_imm))
3353 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3355 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3356 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3360 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3361 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3364 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3365 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3367 case OP_LOAD_MEMBASE:
3368 case OP_LOADI8_MEMBASE:
3369 g_assert (amd64_is_imm32 (ins->inst_offset));
3370 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3372 case OP_LOADI4_MEMBASE:
3373 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3375 case OP_LOADU4_MEMBASE:
3376 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3378 case OP_LOADU1_MEMBASE:
3379 /* The cpu zero extends the result into 64 bits */
3380 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3382 case OP_LOADI1_MEMBASE:
3383 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3385 case OP_LOADU2_MEMBASE:
3386 /* The cpu zero extends the result into 64 bits */
3387 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3389 case OP_LOADI2_MEMBASE:
3390 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3392 case OP_AMD64_LOADI8_MEMINDEX:
3393 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3395 case OP_LCONV_TO_I1:
3396 case OP_ICONV_TO_I1:
3398 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3400 case OP_LCONV_TO_I2:
3401 case OP_ICONV_TO_I2:
3403 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3405 case OP_LCONV_TO_U1:
3406 case OP_ICONV_TO_U1:
3407 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3409 case OP_LCONV_TO_U2:
3410 case OP_ICONV_TO_U2:
3411 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3414 /* Clean out the upper word */
3415 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3418 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3422 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3424 case OP_COMPARE_IMM:
3425 case OP_LCOMPARE_IMM:
3426 g_assert (amd64_is_imm32 (ins->inst_imm));
3427 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3429 case OP_X86_COMPARE_REG_MEMBASE:
3430 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3432 case OP_X86_TEST_NULL:
3433 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3435 case OP_AMD64_TEST_NULL:
3436 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3439 case OP_X86_ADD_REG_MEMBASE:
3440 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3442 case OP_X86_SUB_REG_MEMBASE:
3443 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3445 case OP_X86_AND_REG_MEMBASE:
3446 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3448 case OP_X86_OR_REG_MEMBASE:
3449 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3451 case OP_X86_XOR_REG_MEMBASE:
3452 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3455 case OP_X86_ADD_MEMBASE_IMM:
3456 /* FIXME: Make a 64 version too */
3457 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3459 case OP_X86_SUB_MEMBASE_IMM:
3460 g_assert (amd64_is_imm32 (ins->inst_imm));
3461 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3463 case OP_X86_AND_MEMBASE_IMM:
3464 g_assert (amd64_is_imm32 (ins->inst_imm));
3465 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3467 case OP_X86_OR_MEMBASE_IMM:
3468 g_assert (amd64_is_imm32 (ins->inst_imm));
3469 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3471 case OP_X86_XOR_MEMBASE_IMM:
3472 g_assert (amd64_is_imm32 (ins->inst_imm));
3473 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3475 case OP_X86_ADD_MEMBASE_REG:
3476 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3478 case OP_X86_SUB_MEMBASE_REG:
3479 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3481 case OP_X86_AND_MEMBASE_REG:
3482 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3484 case OP_X86_OR_MEMBASE_REG:
3485 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3487 case OP_X86_XOR_MEMBASE_REG:
3488 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3490 case OP_X86_INC_MEMBASE:
3491 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3493 case OP_X86_INC_REG:
3494 amd64_inc_reg_size (code, ins->dreg, 4);
3496 case OP_X86_DEC_MEMBASE:
3497 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3499 case OP_X86_DEC_REG:
3500 amd64_dec_reg_size (code, ins->dreg, 4);
3502 case OP_X86_MUL_REG_MEMBASE:
3503 case OP_X86_MUL_MEMBASE_REG:
3504 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3506 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3507 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3509 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3510 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3512 case OP_AMD64_COMPARE_MEMBASE_REG:
3513 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3515 case OP_AMD64_COMPARE_MEMBASE_IMM:
3516 g_assert (amd64_is_imm32 (ins->inst_imm));
3517 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3519 case OP_X86_COMPARE_MEMBASE8_IMM:
3520 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3522 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3523 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3525 case OP_AMD64_COMPARE_REG_MEMBASE:
3526 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3529 case OP_AMD64_ADD_REG_MEMBASE:
3530 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3532 case OP_AMD64_SUB_REG_MEMBASE:
3533 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3535 case OP_AMD64_AND_REG_MEMBASE:
3536 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3538 case OP_AMD64_OR_REG_MEMBASE:
3539 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3541 case OP_AMD64_XOR_REG_MEMBASE:
3542 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3545 case OP_AMD64_ADD_MEMBASE_REG:
3546 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3548 case OP_AMD64_SUB_MEMBASE_REG:
3549 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3551 case OP_AMD64_AND_MEMBASE_REG:
3552 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3554 case OP_AMD64_OR_MEMBASE_REG:
3555 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3557 case OP_AMD64_XOR_MEMBASE_REG:
3558 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3561 case OP_AMD64_ADD_MEMBASE_IMM:
3562 g_assert (amd64_is_imm32 (ins->inst_imm));
3563 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3565 case OP_AMD64_SUB_MEMBASE_IMM:
3566 g_assert (amd64_is_imm32 (ins->inst_imm));
3567 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3569 case OP_AMD64_AND_MEMBASE_IMM:
3570 g_assert (amd64_is_imm32 (ins->inst_imm));
3571 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3573 case OP_AMD64_OR_MEMBASE_IMM:
3574 g_assert (amd64_is_imm32 (ins->inst_imm));
3575 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3577 case OP_AMD64_XOR_MEMBASE_IMM:
3578 g_assert (amd64_is_imm32 (ins->inst_imm));
3579 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3583 amd64_breakpoint (code);
3585 case OP_RELAXED_NOP:
3586 x86_prefix (code, X86_REP_PREFIX);
3594 case OP_DUMMY_STORE:
3595 case OP_NOT_REACHED:
3598 case OP_SEQ_POINT: {
3601 if (cfg->compile_aot)
3605 * Read from the single stepping trigger page. This will cause a
3606 * SIGSEGV when single stepping is enabled.
3607 * We do this _before_ the breakpoint, so single stepping after
3608 * a breakpoint is hit will step to the next IL offset.
3610 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3611 if (((guint64)ss_trigger_page >> 32) == 0)
3612 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3614 MonoInst *var = cfg->arch.ss_trigger_page_var;
3616 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3617 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3622 * This is the address which is saved in seq points,
3623 * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3624 * from the address of the instruction causing the fault.
3626 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3629 * A placeholder for a possible breakpoint inserted by
3630 * mono_arch_set_breakpoint ().
3632 for (i = 0; i < breakpoint_size; ++i)
3638 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3641 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3645 g_assert (amd64_is_imm32 (ins->inst_imm));
3646 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3649 g_assert (amd64_is_imm32 (ins->inst_imm));
3650 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3654 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3657 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3661 g_assert (amd64_is_imm32 (ins->inst_imm));
3662 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3665 g_assert (amd64_is_imm32 (ins->inst_imm));
3666 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3669 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3673 g_assert (amd64_is_imm32 (ins->inst_imm));
3674 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3677 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3682 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3684 switch (ins->inst_imm) {
3688 if (ins->dreg != ins->sreg1)
3689 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3690 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3693 /* LEA r1, [r2 + r2*2] */
3694 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3697 /* LEA r1, [r2 + r2*4] */
3698 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3701 /* LEA r1, [r2 + r2*2] */
3703 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3704 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3707 /* LEA r1, [r2 + r2*8] */
3708 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3711 /* LEA r1, [r2 + r2*4] */
3713 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3714 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3717 /* LEA r1, [r2 + r2*2] */
3719 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3720 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3723 /* LEA r1, [r2 + r2*4] */
3724 /* LEA r1, [r1 + r1*4] */
3725 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3726 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3729 /* LEA r1, [r2 + r2*4] */
3731 /* LEA r1, [r1 + r1*4] */
3732 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3733 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3734 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3737 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3744 /* Regalloc magic makes the div/rem cases the same */
3745 if (ins->sreg2 == AMD64_RDX) {
3746 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3748 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3751 amd64_div_reg (code, ins->sreg2, TRUE);
3756 if (ins->sreg2 == AMD64_RDX) {
3757 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3758 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3759 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3761 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3762 amd64_div_reg (code, ins->sreg2, FALSE);
3767 if (ins->sreg2 == AMD64_RDX) {
3768 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3769 amd64_cdq_size (code, 4);
3770 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3772 amd64_cdq_size (code, 4);
3773 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3778 if (ins->sreg2 == AMD64_RDX) {
3779 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3780 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3781 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3783 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3784 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3788 int power = mono_is_power_of_two (ins->inst_imm);
3790 g_assert (ins->sreg1 == X86_EAX);
3791 g_assert (ins->dreg == X86_EAX);
3792 g_assert (power >= 0);
3795 amd64_mov_reg_imm (code, ins->dreg, 0);
3799 /* Based on gcc code */
3801 /* Add compensation for negative dividents */
3802 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3804 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3805 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3806 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3807 /* Compute remainder */
3808 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3809 /* Remove compensation */
3810 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3814 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3815 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3818 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3822 g_assert (amd64_is_imm32 (ins->inst_imm));
3823 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3826 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3830 g_assert (amd64_is_imm32 (ins->inst_imm));
3831 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3834 g_assert (ins->sreg2 == AMD64_RCX);
3835 amd64_shift_reg (code, X86_SHL, ins->dreg);
3838 g_assert (ins->sreg2 == AMD64_RCX);
3839 amd64_shift_reg (code, X86_SAR, ins->dreg);
3842 g_assert (amd64_is_imm32 (ins->inst_imm));
3843 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3846 g_assert (amd64_is_imm32 (ins->inst_imm));
3847 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3850 g_assert (amd64_is_imm32 (ins->inst_imm));
3851 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3853 case OP_LSHR_UN_IMM:
3854 g_assert (amd64_is_imm32 (ins->inst_imm));
3855 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3858 g_assert (ins->sreg2 == AMD64_RCX);
3859 amd64_shift_reg (code, X86_SHR, ins->dreg);
3862 g_assert (amd64_is_imm32 (ins->inst_imm));
3863 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3866 g_assert (amd64_is_imm32 (ins->inst_imm));
3867 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3872 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3875 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3878 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3881 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3885 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3888 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3891 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3894 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3897 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3900 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3903 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3906 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3909 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3912 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3915 amd64_neg_reg_size (code, ins->sreg1, 4);
3918 amd64_not_reg_size (code, ins->sreg1, 4);
3921 g_assert (ins->sreg2 == AMD64_RCX);
3922 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3925 g_assert (ins->sreg2 == AMD64_RCX);
3926 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3929 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3931 case OP_ISHR_UN_IMM:
3932 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3935 g_assert (ins->sreg2 == AMD64_RCX);
3936 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3939 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3942 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3945 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3946 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3948 case OP_IMUL_OVF_UN:
3949 case OP_LMUL_OVF_UN: {
3950 /* the mul operation and the exception check should most likely be split */
3951 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3952 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3953 /*g_assert (ins->sreg2 == X86_EAX);
3954 g_assert (ins->dreg == X86_EAX);*/
3955 if (ins->sreg2 == X86_EAX) {
3956 non_eax_reg = ins->sreg1;
3957 } else if (ins->sreg1 == X86_EAX) {
3958 non_eax_reg = ins->sreg2;
3960 /* no need to save since we're going to store to it anyway */
3961 if (ins->dreg != X86_EAX) {
3963 amd64_push_reg (code, X86_EAX);
3965 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3966 non_eax_reg = ins->sreg2;
3968 if (ins->dreg == X86_EDX) {
3971 amd64_push_reg (code, X86_EAX);
3975 amd64_push_reg (code, X86_EDX);
3977 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3978 /* save before the check since pop and mov don't change the flags */
3979 if (ins->dreg != X86_EAX)
3980 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3982 amd64_pop_reg (code, X86_EDX);
3984 amd64_pop_reg (code, X86_EAX);
3985 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3989 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3991 case OP_ICOMPARE_IMM:
3992 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4014 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4022 case OP_CMOV_INE_UN:
4023 case OP_CMOV_IGE_UN:
4024 case OP_CMOV_IGT_UN:
4025 case OP_CMOV_ILE_UN:
4026 case OP_CMOV_ILT_UN:
4032 case OP_CMOV_LNE_UN:
4033 case OP_CMOV_LGE_UN:
4034 case OP_CMOV_LGT_UN:
4035 case OP_CMOV_LLE_UN:
4036 case OP_CMOV_LLT_UN:
4037 g_assert (ins->dreg == ins->sreg1);
4038 /* This needs to operate on 64 bit values */
4039 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4043 amd64_not_reg (code, ins->sreg1);
4046 amd64_neg_reg (code, ins->sreg1);
4051 if ((((guint64)ins->inst_c0) >> 32) == 0)
4052 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4054 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4057 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4058 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4061 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4062 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4065 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4067 case OP_AMD64_SET_XMMREG_R4: {
4068 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4071 case OP_AMD64_SET_XMMREG_R8: {
4072 if (ins->dreg != ins->sreg1)
4073 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4077 MonoCallInst *call = (MonoCallInst*)ins;
4080 /* FIXME: no tracing support... */
4081 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4082 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4084 g_assert (!cfg->method->save_lmf);
4086 if (cfg->arch.omit_fp) {
4087 guint32 save_offset = 0;
4088 /* Pop callee-saved registers */
4089 for (i = 0; i < AMD64_NREG; ++i)
4090 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4091 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4094 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4097 if (call->stack_usage)
4101 for (i = 0; i < AMD64_NREG; ++i)
4102 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4103 pos -= sizeof (gpointer);
4105 /* Restore callee-saved registers */
4106 for (i = AMD64_NREG - 1; i > 0; --i) {
4107 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4108 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4113 /* Copy arguments on the stack to our argument area */
4114 for (i = 0; i < call->stack_usage; i += 8) {
4115 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, 8);
4116 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, 8);
4120 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4125 offset = code - cfg->native_code;
4126 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4127 if (cfg->compile_aot)
4128 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4130 amd64_set_reg_template (code, AMD64_R11);
4131 amd64_jump_reg (code, AMD64_R11);
4135 /* ensure ins->sreg1 is not NULL */
4136 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4139 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4140 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4149 call = (MonoCallInst*)ins;
4151 * The AMD64 ABI forces callers to know about varargs.
4153 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4154 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4155 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4157 * Since the unmanaged calling convention doesn't contain a
4158 * 'vararg' entry, we have to treat every pinvoke call as a
4159 * potential vararg call.
4163 for (i = 0; i < AMD64_XMM_NREG; ++i)
4164 if (call->used_fregs & (1 << i))
4167 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4169 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4172 if (ins->flags & MONO_INST_HAS_METHOD)
4173 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4175 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4176 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4177 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4178 code = emit_move_return_value (cfg, ins, code);
4184 case OP_VOIDCALL_REG:
4186 call = (MonoCallInst*)ins;
4188 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4189 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4190 ins->sreg1 = AMD64_R11;
4194 * The AMD64 ABI forces callers to know about varargs.
4196 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4197 if (ins->sreg1 == AMD64_RAX) {
4198 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4199 ins->sreg1 = AMD64_R11;
4201 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4202 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4204 * Since the unmanaged calling convention doesn't contain a
4205 * 'vararg' entry, we have to treat every pinvoke call as a
4206 * potential vararg call.
4210 for (i = 0; i < AMD64_XMM_NREG; ++i)
4211 if (call->used_fregs & (1 << i))
4213 if (ins->sreg1 == AMD64_RAX) {
4214 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4215 ins->sreg1 = AMD64_R11;
4218 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4220 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4223 amd64_call_reg (code, ins->sreg1);
4224 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4225 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4226 code = emit_move_return_value (cfg, ins, code);
4228 case OP_FCALL_MEMBASE:
4229 case OP_LCALL_MEMBASE:
4230 case OP_VCALL_MEMBASE:
4231 case OP_VCALL2_MEMBASE:
4232 case OP_VOIDCALL_MEMBASE:
4233 case OP_CALL_MEMBASE:
4234 call = (MonoCallInst*)ins;
4236 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4237 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4238 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4239 code = emit_move_return_value (cfg, ins, code);
4243 MonoInst *var = cfg->dyn_call_var;
4245 g_assert (var->opcode == OP_REGOFFSET);
4247 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4248 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4250 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4252 /* Save args buffer */
4253 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4255 /* Set argument registers */
4256 for (i = 0; i < PARAM_REGS; ++i)
4257 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4260 amd64_call_reg (code, AMD64_R10);
4263 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4264 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4267 case OP_AMD64_SAVE_SP_TO_LMF:
4268 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4271 g_assert (!cfg->arch.no_pushes);
4272 amd64_push_reg (code, ins->sreg1);
4274 case OP_X86_PUSH_IMM:
4275 g_assert (!cfg->arch.no_pushes);
4276 g_assert (amd64_is_imm32 (ins->inst_imm));
4277 amd64_push_imm (code, ins->inst_imm);
4279 case OP_X86_PUSH_MEMBASE:
4280 g_assert (!cfg->arch.no_pushes);
4281 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4283 case OP_X86_PUSH_OBJ: {
4284 int size = ALIGN_TO (ins->inst_imm, 8);
4286 g_assert (!cfg->arch.no_pushes);
4288 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4289 amd64_push_reg (code, AMD64_RDI);
4290 amd64_push_reg (code, AMD64_RSI);
4291 amd64_push_reg (code, AMD64_RCX);
4292 if (ins->inst_offset)
4293 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4295 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4296 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4297 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4299 amd64_prefix (code, X86_REP_PREFIX);
4301 amd64_pop_reg (code, AMD64_RCX);
4302 amd64_pop_reg (code, AMD64_RSI);
4303 amd64_pop_reg (code, AMD64_RDI);
4307 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4309 case OP_X86_LEA_MEMBASE:
4310 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4313 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4316 /* keep alignment */
4317 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4318 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4319 code = mono_emit_stack_alloc (cfg, code, ins);
4320 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4321 if (cfg->param_area && cfg->arch.no_pushes)
4322 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4324 case OP_LOCALLOC_IMM: {
4325 guint32 size = ins->inst_imm;
4326 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4328 if (ins->flags & MONO_INST_INIT) {
4332 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4333 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4335 for (i = 0; i < size; i += 8)
4336 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4337 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4339 amd64_mov_reg_imm (code, ins->dreg, size);
4340 ins->sreg1 = ins->dreg;
4342 code = mono_emit_stack_alloc (cfg, code, ins);
4343 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4346 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4347 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4349 if (cfg->param_area && cfg->arch.no_pushes)
4350 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4354 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4355 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4356 (gpointer)"mono_arch_throw_exception", FALSE);
4360 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4361 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4362 (gpointer)"mono_arch_rethrow_exception", FALSE);
4365 case OP_CALL_HANDLER:
4367 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4368 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4369 amd64_call_imm (code, 0);
4370 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4371 /* Restore stack alignment */
4372 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4374 case OP_START_HANDLER: {
4375 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4376 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4378 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4379 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4380 cfg->param_area && cfg->arch.no_pushes) {
4381 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4385 case OP_ENDFINALLY: {
4386 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4387 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4391 case OP_ENDFILTER: {
4392 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4393 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4394 /* The local allocator will put the result into RAX */
4400 ins->inst_c0 = code - cfg->native_code;
4403 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4404 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4406 if (ins->inst_target_bb->native_offset) {
4407 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4409 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4410 if ((cfg->opt & MONO_OPT_BRANCH) &&
4411 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4412 x86_jump8 (code, 0);
4414 x86_jump32 (code, 0);
4418 amd64_jump_reg (code, ins->sreg1);
4435 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4436 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4438 case OP_COND_EXC_EQ:
4439 case OP_COND_EXC_NE_UN:
4440 case OP_COND_EXC_LT:
4441 case OP_COND_EXC_LT_UN:
4442 case OP_COND_EXC_GT:
4443 case OP_COND_EXC_GT_UN:
4444 case OP_COND_EXC_GE:
4445 case OP_COND_EXC_GE_UN:
4446 case OP_COND_EXC_LE:
4447 case OP_COND_EXC_LE_UN:
4448 case OP_COND_EXC_IEQ:
4449 case OP_COND_EXC_INE_UN:
4450 case OP_COND_EXC_ILT:
4451 case OP_COND_EXC_ILT_UN:
4452 case OP_COND_EXC_IGT:
4453 case OP_COND_EXC_IGT_UN:
4454 case OP_COND_EXC_IGE:
4455 case OP_COND_EXC_IGE_UN:
4456 case OP_COND_EXC_ILE:
4457 case OP_COND_EXC_ILE_UN:
4458 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4460 case OP_COND_EXC_OV:
4461 case OP_COND_EXC_NO:
4463 case OP_COND_EXC_NC:
4464 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4465 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4467 case OP_COND_EXC_IOV:
4468 case OP_COND_EXC_INO:
4469 case OP_COND_EXC_IC:
4470 case OP_COND_EXC_INC:
4471 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4472 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4475 /* floating point opcodes */
4477 double d = *(double *)ins->inst_p0;
4479 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4480 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4483 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4484 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4489 float f = *(float *)ins->inst_p0;
4491 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4492 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4495 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4496 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4497 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4501 case OP_STORER8_MEMBASE_REG:
4502 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4504 case OP_LOADR8_MEMBASE:
4505 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4507 case OP_STORER4_MEMBASE_REG:
4508 /* This requires a double->single conversion */
4509 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4510 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4512 case OP_LOADR4_MEMBASE:
4513 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4514 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4516 case OP_ICONV_TO_R4: /* FIXME: change precision */
4517 case OP_ICONV_TO_R8:
4518 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4520 case OP_LCONV_TO_R4: /* FIXME: change precision */
4521 case OP_LCONV_TO_R8:
4522 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4524 case OP_FCONV_TO_R4:
4525 /* FIXME: nothing to do ?? */
4527 case OP_FCONV_TO_I1:
4528 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4530 case OP_FCONV_TO_U1:
4531 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4533 case OP_FCONV_TO_I2:
4534 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4536 case OP_FCONV_TO_U2:
4537 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4539 case OP_FCONV_TO_U4:
4540 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4542 case OP_FCONV_TO_I4:
4544 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4546 case OP_FCONV_TO_I8:
4547 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4549 case OP_LCONV_TO_R_UN: {
4552 /* Based on gcc code */
4553 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4554 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4557 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4558 br [1] = code; x86_jump8 (code, 0);
4559 amd64_patch (br [0], code);
4562 /* Save to the red zone */
4563 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4564 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4565 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4566 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4567 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4568 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4569 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4570 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4571 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4573 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4574 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4575 amd64_patch (br [1], code);
4578 case OP_LCONV_TO_OVF_U4:
4579 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4580 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4581 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4583 case OP_LCONV_TO_OVF_I4_UN:
4584 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4585 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4586 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4589 if (ins->dreg != ins->sreg1)
4590 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4593 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4596 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4599 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4602 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4605 static double r8_0 = -0.0;
4607 g_assert (ins->sreg1 == ins->dreg);
4609 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4610 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4614 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4617 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4620 static guint64 d = 0x7fffffffffffffffUL;
4622 g_assert (ins->sreg1 == ins->dreg);
4624 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4625 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4629 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4632 g_assert (cfg->opt & MONO_OPT_CMOV);
4633 g_assert (ins->dreg == ins->sreg1);
4634 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4635 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4638 g_assert (cfg->opt & MONO_OPT_CMOV);
4639 g_assert (ins->dreg == ins->sreg1);
4640 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4641 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4644 g_assert (cfg->opt & MONO_OPT_CMOV);
4645 g_assert (ins->dreg == ins->sreg1);
4646 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4647 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4650 g_assert (cfg->opt & MONO_OPT_CMOV);
4651 g_assert (ins->dreg == ins->sreg1);
4652 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4653 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4656 g_assert (cfg->opt & MONO_OPT_CMOV);
4657 g_assert (ins->dreg == ins->sreg1);
4658 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4659 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4662 g_assert (cfg->opt & MONO_OPT_CMOV);
4663 g_assert (ins->dreg == ins->sreg1);
4664 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4665 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4668 g_assert (cfg->opt & MONO_OPT_CMOV);
4669 g_assert (ins->dreg == ins->sreg1);
4670 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4671 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4674 g_assert (cfg->opt & MONO_OPT_CMOV);
4675 g_assert (ins->dreg == ins->sreg1);
4676 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4677 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4683 * The two arguments are swapped because the fbranch instructions
4684 * depend on this for the non-sse case to work.
4686 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4689 /* zeroing the register at the start results in
4690 * shorter and faster code (we can also remove the widening op)
4692 guchar *unordered_check;
4693 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4694 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4695 unordered_check = code;
4696 x86_branch8 (code, X86_CC_P, 0, FALSE);
4697 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4698 amd64_patch (unordered_check, code);
4703 /* zeroing the register at the start results in
4704 * shorter and faster code (we can also remove the widening op)
4706 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4707 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4708 if (ins->opcode == OP_FCLT_UN) {
4709 guchar *unordered_check = code;
4710 guchar *jump_to_end;
4711 x86_branch8 (code, X86_CC_P, 0, FALSE);
4712 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4714 x86_jump8 (code, 0);
4715 amd64_patch (unordered_check, code);
4716 amd64_inc_reg (code, ins->dreg);
4717 amd64_patch (jump_to_end, code);
4719 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4724 /* zeroing the register at the start results in
4725 * shorter and faster code (we can also remove the widening op)
4727 guchar *unordered_check;
4728 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4729 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4730 if (ins->opcode == OP_FCGT) {
4731 unordered_check = code;
4732 x86_branch8 (code, X86_CC_P, 0, FALSE);
4733 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4734 amd64_patch (unordered_check, code);
4736 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4740 case OP_FCLT_MEMBASE:
4741 case OP_FCGT_MEMBASE:
4742 case OP_FCLT_UN_MEMBASE:
4743 case OP_FCGT_UN_MEMBASE:
4744 case OP_FCEQ_MEMBASE: {
4745 guchar *unordered_check, *jump_to_end;
4748 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4749 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4751 switch (ins->opcode) {
4752 case OP_FCEQ_MEMBASE:
4753 x86_cond = X86_CC_EQ;
4755 case OP_FCLT_MEMBASE:
4756 case OP_FCLT_UN_MEMBASE:
4757 x86_cond = X86_CC_LT;
4759 case OP_FCGT_MEMBASE:
4760 case OP_FCGT_UN_MEMBASE:
4761 x86_cond = X86_CC_GT;
4764 g_assert_not_reached ();
4767 unordered_check = code;
4768 x86_branch8 (code, X86_CC_P, 0, FALSE);
4769 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4771 switch (ins->opcode) {
4772 case OP_FCEQ_MEMBASE:
4773 case OP_FCLT_MEMBASE:
4774 case OP_FCGT_MEMBASE:
4775 amd64_patch (unordered_check, code);
4777 case OP_FCLT_UN_MEMBASE:
4778 case OP_FCGT_UN_MEMBASE:
4780 x86_jump8 (code, 0);
4781 amd64_patch (unordered_check, code);
4782 amd64_inc_reg (code, ins->dreg);
4783 amd64_patch (jump_to_end, code);
4791 guchar *jump = code;
4792 x86_branch8 (code, X86_CC_P, 0, TRUE);
4793 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4794 amd64_patch (jump, code);
4798 /* Branch if C013 != 100 */
4799 /* branch if !ZF or (PF|CF) */
4800 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4801 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4802 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4805 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4808 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4809 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4813 if (ins->opcode == OP_FBGT) {
4816 /* skip branch if C1=1 */
4818 x86_branch8 (code, X86_CC_P, 0, FALSE);
4819 /* branch if (C0 | C3) = 1 */
4820 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4821 amd64_patch (br1, code);
4824 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4828 /* Branch if C013 == 100 or 001 */
4831 /* skip branch if C1=1 */
4833 x86_branch8 (code, X86_CC_P, 0, FALSE);
4834 /* branch if (C0 | C3) = 1 */
4835 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4836 amd64_patch (br1, code);
4840 /* Branch if C013 == 000 */
4841 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4844 /* Branch if C013=000 or 100 */
4847 /* skip branch if C1=1 */
4849 x86_branch8 (code, X86_CC_P, 0, FALSE);
4850 /* branch if C0=0 */
4851 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4852 amd64_patch (br1, code);
4856 /* Branch if C013 != 001 */
4857 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4858 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4861 /* Transfer value to the fp stack */
4862 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4863 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4864 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4866 amd64_push_reg (code, AMD64_RAX);
4868 amd64_fnstsw (code);
4869 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4870 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4871 amd64_pop_reg (code, AMD64_RAX);
4872 amd64_fstp (code, 0);
4873 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4874 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4877 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4880 case OP_MEMORY_BARRIER: {
4881 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4882 x86_prefix (code, X86_LOCK_PREFIX);
4883 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
4886 case OP_ATOMIC_ADD_I4:
4887 case OP_ATOMIC_ADD_I8: {
4888 int dreg = ins->dreg;
4889 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4891 if (dreg == ins->inst_basereg)
4894 if (dreg != ins->sreg2)
4895 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4897 x86_prefix (code, X86_LOCK_PREFIX);
4898 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4900 if (dreg != ins->dreg)
4901 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4905 case OP_ATOMIC_ADD_NEW_I4:
4906 case OP_ATOMIC_ADD_NEW_I8: {
4907 int dreg = ins->dreg;
4908 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4910 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4913 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4914 amd64_prefix (code, X86_LOCK_PREFIX);
4915 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4916 /* dreg contains the old value, add with sreg2 value */
4917 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4919 if (ins->dreg != dreg)
4920 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4924 case OP_ATOMIC_EXCHANGE_I4:
4925 case OP_ATOMIC_EXCHANGE_I8: {
4927 int sreg2 = ins->sreg2;
4928 int breg = ins->inst_basereg;
4930 gboolean need_push = FALSE, rdx_pushed = FALSE;
4932 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4938 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4939 * an explanation of how this works.
4942 /* cmpxchg uses eax as comperand, need to make sure we can use it
4943 * hack to overcome limits in x86 reg allocator
4944 * (req: dreg == eax and sreg2 != eax and breg != eax)
4946 g_assert (ins->dreg == AMD64_RAX);
4948 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4949 /* Highly unlikely, but possible */
4952 /* The pushes invalidate rsp */
4953 if ((breg == AMD64_RAX) || need_push) {
4954 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4958 /* We need the EAX reg for the comparand */
4959 if (ins->sreg2 == AMD64_RAX) {
4960 if (breg != AMD64_R11) {
4961 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4964 g_assert (need_push);
4965 amd64_push_reg (code, AMD64_RDX);
4966 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4972 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4974 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4975 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4976 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4977 amd64_patch (br [1], br [0]);
4980 amd64_pop_reg (code, AMD64_RDX);
4984 case OP_ATOMIC_CAS_I4:
4985 case OP_ATOMIC_CAS_I8: {
4988 if (ins->opcode == OP_ATOMIC_CAS_I8)
4994 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4995 * an explanation of how this works.
4997 g_assert (ins->sreg3 == AMD64_RAX);
4998 g_assert (ins->sreg1 != AMD64_RAX);
4999 g_assert (ins->sreg1 != ins->sreg2);
5001 amd64_prefix (code, X86_LOCK_PREFIX);
5002 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5004 if (ins->dreg != AMD64_RAX)
5005 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5008 case OP_CARD_TABLE_WBARRIER: {
5009 int ptr = ins->sreg1;
5010 int value = ins->sreg2;
5012 int nursery_shift, card_table_shift;
5013 gpointer card_table_mask;
5014 size_t nursery_size;
5016 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5017 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5019 /*If either point to the stack we can simply avoid the WB. This happens due to
5020 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5022 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5026 * We need one register we can clobber, we choose EDX and make sreg1
5027 * fixed EAX to work around limitations in the local register allocator.
5028 * sreg2 might get allocated to EDX, but that is not a problem since
5029 * we use it before clobbering EDX.
5031 g_assert (ins->sreg1 == AMD64_RAX);
5034 * This is the code we produce:
5037 * edx >>= nursery_shift
5038 * cmp edx, (nursery_start >> nursery_shift)
5041 * edx >>= card_table_shift
5047 if (value != AMD64_RDX)
5048 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5049 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5050 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5051 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5052 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5053 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5054 if (card_table_mask)
5055 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5057 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5058 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5060 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5061 x86_patch (br, code);
5064 #ifdef MONO_ARCH_SIMD_INTRINSICS
5065 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5067 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5070 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5073 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5076 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5079 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5082 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5085 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5086 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5089 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5092 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5095 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5098 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5101 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5104 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5107 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5110 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5113 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5116 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5119 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5122 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5125 case OP_PSHUFLEW_HIGH:
5126 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5127 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5129 case OP_PSHUFLEW_LOW:
5130 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5131 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5134 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5135 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5139 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5142 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5145 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5148 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5151 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5154 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5157 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5158 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5161 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5164 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5167 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5170 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5173 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5176 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5179 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5182 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5185 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5188 case OP_EXTRACT_MASK:
5189 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5193 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5196 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5199 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5203 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5206 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5209 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5212 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5216 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5219 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5222 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5225 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5229 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5232 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5235 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5239 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5242 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5245 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5249 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5252 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5256 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5259 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5262 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5266 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5269 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5272 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5276 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5279 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5282 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5285 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5289 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5292 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5295 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5298 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5301 case OP_PSUM_ABS_DIFF:
5302 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5305 case OP_UNPACK_LOWB:
5306 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5308 case OP_UNPACK_LOWW:
5309 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5311 case OP_UNPACK_LOWD:
5312 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5314 case OP_UNPACK_LOWQ:
5315 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5317 case OP_UNPACK_LOWPS:
5318 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5320 case OP_UNPACK_LOWPD:
5321 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5324 case OP_UNPACK_HIGHB:
5325 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5327 case OP_UNPACK_HIGHW:
5328 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5330 case OP_UNPACK_HIGHD:
5331 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5333 case OP_UNPACK_HIGHQ:
5334 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5336 case OP_UNPACK_HIGHPS:
5337 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5339 case OP_UNPACK_HIGHPD:
5340 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5344 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5347 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5350 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5353 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5356 case OP_PADDB_SAT_UN:
5357 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5359 case OP_PSUBB_SAT_UN:
5360 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5362 case OP_PADDW_SAT_UN:
5363 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5365 case OP_PSUBW_SAT_UN:
5366 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5370 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5373 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5376 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5379 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5383 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5386 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5389 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5391 case OP_PMULW_HIGH_UN:
5392 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5395 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5399 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5402 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5406 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5409 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5413 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5416 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5420 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5423 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5427 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5430 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5434 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5437 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5441 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5444 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5447 /*TODO: This is appart of the sse spec but not added
5449 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5452 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5457 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5460 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5464 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5467 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5471 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5472 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5474 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5479 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5481 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5482 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5486 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5488 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5489 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5490 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5494 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5496 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5499 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5501 case OP_EXTRACTX_U2:
5502 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5504 case OP_INSERTX_U1_SLOW:
5505 /*sreg1 is the extracted ireg (scratch)
5506 /sreg2 is the to be inserted ireg (scratch)
5507 /dreg is the xreg to receive the value*/
5509 /*clear the bits from the extracted word*/
5510 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5511 /*shift the value to insert if needed*/
5512 if (ins->inst_c0 & 1)
5513 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5514 /*join them together*/
5515 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5516 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5518 case OP_INSERTX_I4_SLOW:
5519 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5520 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5521 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5523 case OP_INSERTX_I8_SLOW:
5524 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5526 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5528 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5531 case OP_INSERTX_R4_SLOW:
5532 switch (ins->inst_c0) {
5534 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5537 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5538 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5539 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5542 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5543 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5544 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5547 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5548 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5549 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5553 case OP_INSERTX_R8_SLOW:
5555 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5557 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5559 case OP_STOREX_MEMBASE_REG:
5560 case OP_STOREX_MEMBASE:
5561 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5563 case OP_LOADX_MEMBASE:
5564 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5566 case OP_LOADX_ALIGNED_MEMBASE:
5567 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5569 case OP_STOREX_ALIGNED_MEMBASE_REG:
5570 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5572 case OP_STOREX_NTA_MEMBASE_REG:
5573 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5575 case OP_PREFETCH_MEMBASE:
5576 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5580 /*FIXME the peephole pass should have killed this*/
5581 if (ins->dreg != ins->sreg1)
5582 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5585 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5587 case OP_ICONV_TO_R8_RAW:
5588 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5589 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5592 case OP_FCONV_TO_R8_X:
5593 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5596 case OP_XCONV_R8_TO_I4:
5597 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5598 switch (ins->backend.source_opcode) {
5599 case OP_FCONV_TO_I1:
5600 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5602 case OP_FCONV_TO_U1:
5603 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5605 case OP_FCONV_TO_I2:
5606 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5608 case OP_FCONV_TO_U2:
5609 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5615 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5616 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5617 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5620 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5621 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5624 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5625 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5628 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5629 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5630 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5633 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5634 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5637 case OP_LIVERANGE_START: {
5638 if (cfg->verbose_level > 1)
5639 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5640 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5643 case OP_LIVERANGE_END: {
5644 if (cfg->verbose_level > 1)
5645 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5646 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5650 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5651 g_assert_not_reached ();
5654 if ((code - cfg->native_code - offset) > max_len) {
5655 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5656 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5657 g_assert_not_reached ();
5661 last_offset = offset;
5664 cfg->code_len = code - cfg->native_code;
5667 #endif /* DISABLE_JIT */
5670 mono_arch_register_lowlevel_calls (void)
5672 /* The signature doesn't matter */
5673 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5677 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5679 MonoJumpInfo *patch_info;
5680 gboolean compile_aot = !run_cctors;
5682 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5683 unsigned char *ip = patch_info->ip.i + code;
5684 unsigned char *target;
5686 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5689 switch (patch_info->type) {
5690 case MONO_PATCH_INFO_BB:
5691 case MONO_PATCH_INFO_LABEL:
5694 /* No need to patch these */
5699 switch (patch_info->type) {
5700 case MONO_PATCH_INFO_NONE:
5702 case MONO_PATCH_INFO_METHOD_REL:
5703 case MONO_PATCH_INFO_R8:
5704 case MONO_PATCH_INFO_R4:
5705 g_assert_not_reached ();
5707 case MONO_PATCH_INFO_BB:
5714 * Debug code to help track down problems where the target of a near call is
5717 if (amd64_is_near_call (ip)) {
5718 gint64 disp = (guint8*)target - (guint8*)ip;
5720 if (!amd64_is_imm32 (disp)) {
5721 printf ("TYPE: %d\n", patch_info->type);
5722 switch (patch_info->type) {
5723 case MONO_PATCH_INFO_INTERNAL_METHOD:
5724 printf ("V: %s\n", patch_info->data.name);
5726 case MONO_PATCH_INFO_METHOD_JUMP:
5727 case MONO_PATCH_INFO_METHOD:
5728 printf ("V: %s\n", patch_info->data.method->name);
5736 amd64_patch (ip, (gpointer)target);
5743 get_max_epilog_size (MonoCompile *cfg)
5745 int max_epilog_size = 16;
5747 if (cfg->method->save_lmf)
5748 max_epilog_size += 256;
5750 if (mono_jit_trace_calls != NULL)
5751 max_epilog_size += 50;
5753 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5754 max_epilog_size += 50;
5756 max_epilog_size += (AMD64_NREG * 2);
5758 return max_epilog_size;
5762 * This macro is used for testing whenever the unwinder works correctly at every point
5763 * where an async exception can happen.
5765 /* This will generate a SIGSEGV at the given point in the code */
5766 #define async_exc_point(code) do { \
5767 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5768 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5769 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5770 cfg->arch.async_point_count ++; \
5775 mono_arch_emit_prolog (MonoCompile *cfg)
5777 MonoMethod *method = cfg->method;
5779 MonoMethodSignature *sig;
5781 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5784 gint32 lmf_offset = cfg->arch.lmf_offset;
5785 gboolean args_clobbered = FALSE;
5786 gboolean trace = FALSE;
5788 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5790 code = cfg->native_code = g_malloc (cfg->code_size);
5792 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5795 /* Amount of stack space allocated by register saving code */
5798 /* Offset between RSP and the CFA */
5802 * The prolog consists of the following parts:
5804 * - push rbp, mov rbp, rsp
5805 * - save callee saved regs using pushes
5807 * - save rgctx if needed
5808 * - save lmf if needed
5811 * - save rgctx if needed
5812 * - save lmf if needed
5813 * - save callee saved regs using moves
5818 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5819 // IP saved at CFA - 8
5820 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5821 async_exc_point (code);
5823 if (!cfg->arch.omit_fp) {
5824 amd64_push_reg (code, AMD64_RBP);
5826 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5827 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5828 async_exc_point (code);
5830 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5833 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5834 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5835 async_exc_point (code);
5837 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5841 /* Save callee saved registers */
5842 if (!cfg->arch.omit_fp && !method->save_lmf) {
5843 int offset = cfa_offset;
5845 for (i = 0; i < AMD64_NREG; ++i)
5846 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5847 amd64_push_reg (code, i);
5848 pos += sizeof (gpointer);
5850 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5851 async_exc_point (code);
5855 /* The param area is always at offset 0 from sp */
5856 /* This needs to be allocated here, since it has to come after the spill area */
5857 if (cfg->arch.no_pushes && cfg->param_area) {
5858 if (cfg->arch.omit_fp)
5860 g_assert_not_reached ();
5861 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5864 if (cfg->arch.omit_fp) {
5866 * On enter, the stack is misaligned by the the pushing of the return
5867 * address. It is either made aligned by the pushing of %rbp, or by
5870 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5871 if ((alloc_size % 16) == 0)
5874 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5879 cfg->arch.stack_alloc_size = alloc_size;
5881 /* Allocate stack frame */
5883 /* See mono_emit_stack_alloc */
5884 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5885 guint32 remaining_size = alloc_size;
5886 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5887 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5888 guint32 offset = code - cfg->native_code;
5889 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5890 while (required_code_size >= (cfg->code_size - offset))
5891 cfg->code_size *= 2;
5892 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5893 code = cfg->native_code + offset;
5894 mono_jit_stats.code_reallocs++;
5897 while (remaining_size >= 0x1000) {
5898 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5899 if (cfg->arch.omit_fp) {
5900 cfa_offset += 0x1000;
5901 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5903 async_exc_point (code);
5905 if (cfg->arch.omit_fp)
5906 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5909 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5910 remaining_size -= 0x1000;
5912 if (remaining_size) {
5913 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5914 if (cfg->arch.omit_fp) {
5915 cfa_offset += remaining_size;
5916 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5917 async_exc_point (code);
5920 if (cfg->arch.omit_fp)
5921 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5925 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5926 if (cfg->arch.omit_fp) {
5927 cfa_offset += alloc_size;
5928 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5929 async_exc_point (code);
5934 /* Stack alignment check */
5937 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5938 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5939 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5940 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5941 amd64_breakpoint (code);
5945 #ifndef TARGET_WIN32
5946 if (mini_get_debug_options ()->init_stacks) {
5947 /* Fill the stack frame with a dummy value to force deterministic behavior */
5949 /* Save registers to the red zone */
5950 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5951 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5953 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5954 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5955 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5958 amd64_prefix (code, X86_REP_PREFIX);
5961 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5962 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5967 if (method->save_lmf) {
5969 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5972 * sp is saved right before calls but we need to save it here too so
5973 * async stack walks would work.
5975 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5976 /* Skip method (only needed for trampoline LMF frames) */
5977 /* Save callee saved regs */
5978 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5982 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5983 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5984 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5985 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5986 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5987 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5989 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5990 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5998 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5999 if (cfg->arch.omit_fp || (i != AMD64_RBP))
6000 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
6005 /* Save callee saved registers */
6006 if (cfg->arch.omit_fp && !method->save_lmf) {
6007 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6009 /* Save caller saved registers after sp is adjusted */
6010 /* The registers are saved at the bottom of the frame */
6011 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6012 for (i = 0; i < AMD64_NREG; ++i)
6013 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6014 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6015 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6016 save_area_offset += 8;
6017 async_exc_point (code);
6021 /* store runtime generic context */
6022 if (cfg->rgctx_var) {
6023 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6024 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6026 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
6029 /* compute max_length in order to use short forward jumps */
6030 max_epilog_size = get_max_epilog_size (cfg);
6031 if (cfg->opt & MONO_OPT_BRANCH) {
6032 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6036 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6038 /* max alignment for loops */
6039 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6040 max_length += LOOP_ALIGNMENT;
6042 MONO_BB_FOR_EACH_INS (bb, ins) {
6043 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6046 /* Take prolog and epilog instrumentation into account */
6047 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6048 max_length += max_epilog_size;
6050 bb->max_length = max_length;
6054 sig = mono_method_signature (method);
6057 cinfo = cfg->arch.cinfo;
6059 if (sig->ret->type != MONO_TYPE_VOID) {
6060 /* Save volatile arguments to the stack */
6061 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6062 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6065 /* Keep this in sync with emit_load_volatile_arguments */
6066 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6067 ArgInfo *ainfo = cinfo->args + i;
6068 gint32 stack_offset;
6071 ins = cfg->args [i];
6073 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6074 /* Unused arguments */
6077 if (sig->hasthis && (i == 0))
6078 arg_type = &mono_defaults.object_class->byval_arg;
6080 arg_type = sig->params [i - sig->hasthis];
6082 stack_offset = ainfo->offset + ARGS_OFFSET;
6084 if (cfg->globalra) {
6085 /* All the other moves are done by the register allocator */
6086 switch (ainfo->storage) {
6087 case ArgInFloatSSEReg:
6088 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6090 case ArgValuetypeInReg:
6091 for (quad = 0; quad < 2; quad ++) {
6092 switch (ainfo->pair_storage [quad]) {
6094 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6096 case ArgInFloatSSEReg:
6097 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6099 case ArgInDoubleSSEReg:
6100 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6105 g_assert_not_reached ();
6116 /* Save volatile arguments to the stack */
6117 if (ins->opcode != OP_REGVAR) {
6118 switch (ainfo->storage) {
6124 if (stack_offset & 0x1)
6126 else if (stack_offset & 0x2)
6128 else if (stack_offset & 0x4)
6133 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6136 case ArgInFloatSSEReg:
6137 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6139 case ArgInDoubleSSEReg:
6140 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6142 case ArgValuetypeInReg:
6143 for (quad = 0; quad < 2; quad ++) {
6144 switch (ainfo->pair_storage [quad]) {
6146 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6148 case ArgInFloatSSEReg:
6149 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6151 case ArgInDoubleSSEReg:
6152 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6157 g_assert_not_reached ();
6161 case ArgValuetypeAddrInIReg:
6162 if (ainfo->pair_storage [0] == ArgInIReg)
6163 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6169 /* Argument allocated to (non-volatile) register */
6170 switch (ainfo->storage) {
6172 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6175 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6178 g_assert_not_reached ();
6183 /* Might need to attach the thread to the JIT or change the domain for the callback */
6184 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6185 guint64 domain = (guint64)cfg->domain;
6187 args_clobbered = TRUE;
6190 * The call might clobber argument registers, but they are already
6191 * saved to the stack/global regs.
6193 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6194 guint8 *buf, *no_domain_branch;
6196 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6197 if (cfg->compile_aot) {
6198 /* AOT code is only used in the root domain */
6199 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6201 if ((domain >> 32) == 0)
6202 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6204 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6206 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6207 no_domain_branch = code;
6208 x86_branch8 (code, X86_CC_NE, 0, 0);
6209 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6210 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6212 x86_branch8 (code, X86_CC_NE, 0, 0);
6213 amd64_patch (no_domain_branch, code);
6214 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6215 (gpointer)"mono_jit_thread_attach", TRUE);
6216 amd64_patch (buf, code);
6218 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6219 /* FIXME: Add a separate key for LMF to avoid this */
6220 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6223 g_assert (!cfg->compile_aot);
6224 if (cfg->compile_aot) {
6225 /* AOT code is only used in the root domain */
6226 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6228 if ((domain >> 32) == 0)
6229 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6231 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6233 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6234 (gpointer)"mono_jit_thread_attach", TRUE);
6238 if (method->save_lmf) {
6239 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6241 * Optimized version which uses the mono_lmf TLS variable instead of
6242 * indirection through the mono_lmf_addr TLS variable.
6244 /* %rax = previous_lmf */
6245 x86_prefix (code, X86_FS_PREFIX);
6246 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6248 /* Save previous_lmf */
6249 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6251 if (lmf_offset == 0) {
6252 x86_prefix (code, X86_FS_PREFIX);
6253 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6255 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6256 x86_prefix (code, X86_FS_PREFIX);
6257 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6260 if (lmf_addr_tls_offset != -1) {
6261 /* Load lmf quicky using the FS register */
6262 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6264 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6265 /* FIXME: Add a separate key for LMF to avoid this */
6266 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6271 * The call might clobber argument registers, but they are already
6272 * saved to the stack/global regs.
6274 args_clobbered = TRUE;
6275 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6276 (gpointer)"mono_get_lmf_addr", TRUE);
6280 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6281 /* Save previous_lmf */
6282 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6283 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6285 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6286 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6291 args_clobbered = TRUE;
6292 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6295 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6296 args_clobbered = TRUE;
6299 * Optimize the common case of the first bblock making a call with the same
6300 * arguments as the method. This works because the arguments are still in their
6301 * original argument registers.
6302 * FIXME: Generalize this
6304 if (!args_clobbered) {
6305 MonoBasicBlock *first_bb = cfg->bb_entry;
6308 next = mono_bb_first_ins (first_bb);
6309 if (!next && first_bb->next_bb) {
6310 first_bb = first_bb->next_bb;
6311 next = mono_bb_first_ins (first_bb);
6314 if (first_bb->in_count > 1)
6317 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6318 ArgInfo *ainfo = cinfo->args + i;
6319 gboolean match = FALSE;
6321 ins = cfg->args [i];
6322 if (ins->opcode != OP_REGVAR) {
6323 switch (ainfo->storage) {
6325 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6326 if (next->dreg == ainfo->reg) {
6330 next->opcode = OP_MOVE;
6331 next->sreg1 = ainfo->reg;
6332 /* Only continue if the instruction doesn't change argument regs */
6333 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6343 /* Argument allocated to (non-volatile) register */
6344 switch (ainfo->storage) {
6346 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6358 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6365 /* Initialize ss_trigger_page_var */
6366 if (cfg->arch.ss_trigger_page_var) {
6367 MonoInst *var = cfg->arch.ss_trigger_page_var;
6369 g_assert (!cfg->compile_aot);
6370 g_assert (var->opcode == OP_REGOFFSET);
6372 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6373 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6376 cfg->code_len = code - cfg->native_code;
6378 g_assert (cfg->code_len < cfg->code_size);
6384 mono_arch_emit_epilog (MonoCompile *cfg)
6386 MonoMethod *method = cfg->method;
6389 int max_epilog_size;
6391 gint32 lmf_offset = cfg->arch.lmf_offset;
6393 max_epilog_size = get_max_epilog_size (cfg);
6395 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6396 cfg->code_size *= 2;
6397 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6398 mono_jit_stats.code_reallocs++;
6401 code = cfg->native_code + cfg->code_len;
6403 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6404 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6406 /* the code restoring the registers must be kept in sync with OP_JMP */
6409 if (method->save_lmf) {
6410 /* check if we need to restore protection of the stack after a stack overflow */
6411 if (mono_get_jit_tls_offset () != -1) {
6413 code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6414 /* we load the value in a separate instruction: this mechanism may be
6415 * used later as a safer way to do thread interruption
6417 amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6418 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6420 x86_branch8 (code, X86_CC_Z, 0, FALSE);
6421 /* note that the call trampoline will preserve eax/edx */
6422 x86_call_reg (code, X86_ECX);
6423 x86_patch (patch, code);
6425 /* FIXME: maybe save the jit tls in the prolog */
6427 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6429 * Optimized version which uses the mono_lmf TLS variable instead of indirection
6430 * through the mono_lmf_addr TLS variable.
6432 /* reg = previous_lmf */
6433 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6434 x86_prefix (code, X86_FS_PREFIX);
6435 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6437 /* Restore previous lmf */
6438 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6439 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6440 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6443 /* Restore caller saved regs */
6444 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6445 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6447 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6448 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6450 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6451 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6453 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6454 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6456 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6457 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6459 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6460 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6463 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6464 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6466 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6467 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6472 if (cfg->arch.omit_fp) {
6473 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6475 for (i = 0; i < AMD64_NREG; ++i)
6476 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6477 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6478 save_area_offset += 8;
6482 for (i = 0; i < AMD64_NREG; ++i)
6483 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6484 pos -= sizeof (gpointer);
6487 if (pos == - sizeof (gpointer)) {
6488 /* Only one register, so avoid lea */
6489 for (i = AMD64_NREG - 1; i > 0; --i)
6490 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6491 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6495 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6497 /* Pop registers in reverse order */
6498 for (i = AMD64_NREG - 1; i > 0; --i)
6499 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6500 amd64_pop_reg (code, i);
6507 /* Load returned vtypes into registers if needed */
6508 cinfo = cfg->arch.cinfo;
6509 if (cinfo->ret.storage == ArgValuetypeInReg) {
6510 ArgInfo *ainfo = &cinfo->ret;
6511 MonoInst *inst = cfg->ret;
6513 for (quad = 0; quad < 2; quad ++) {
6514 switch (ainfo->pair_storage [quad]) {
6516 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6518 case ArgInFloatSSEReg:
6519 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6521 case ArgInDoubleSSEReg:
6522 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6527 g_assert_not_reached ();
6532 if (cfg->arch.omit_fp) {
6533 if (cfg->arch.stack_alloc_size)
6534 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6538 async_exc_point (code);
6541 cfg->code_len = code - cfg->native_code;
6543 g_assert (cfg->code_len < cfg->code_size);
6547 mono_arch_emit_exceptions (MonoCompile *cfg)
6549 MonoJumpInfo *patch_info;
6552 MonoClass *exc_classes [16];
6553 guint8 *exc_throw_start [16], *exc_throw_end [16];
6554 guint32 code_size = 0;
6556 /* Compute needed space */
6557 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6558 if (patch_info->type == MONO_PATCH_INFO_EXC)
6560 if (patch_info->type == MONO_PATCH_INFO_R8)
6561 code_size += 8 + 15; /* sizeof (double) + alignment */
6562 if (patch_info->type == MONO_PATCH_INFO_R4)
6563 code_size += 4 + 15; /* sizeof (float) + alignment */
6564 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
6565 code_size += 8 + 7; /*sizeof (void*) + alignment */
6568 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6569 cfg->code_size *= 2;
6570 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6571 mono_jit_stats.code_reallocs++;
6574 code = cfg->native_code + cfg->code_len;
6576 /* add code to raise exceptions */
6578 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6579 switch (patch_info->type) {
6580 case MONO_PATCH_INFO_EXC: {
6581 MonoClass *exc_class;
6585 amd64_patch (patch_info->ip.i + cfg->native_code, code);
6587 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6588 g_assert (exc_class);
6589 throw_ip = patch_info->ip.i;
6591 //x86_breakpoint (code);
6592 /* Find a throw sequence for the same exception class */
6593 for (i = 0; i < nthrows; ++i)
6594 if (exc_classes [i] == exc_class)
6597 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6598 x86_jump_code (code, exc_throw_start [i]);
6599 patch_info->type = MONO_PATCH_INFO_NONE;
6603 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6607 exc_classes [nthrows] = exc_class;
6608 exc_throw_start [nthrows] = code;
6610 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6612 patch_info->type = MONO_PATCH_INFO_NONE;
6614 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6616 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6621 exc_throw_end [nthrows] = code;
6633 /* Handle relocations with RIP relative addressing */
6634 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6635 gboolean remove = FALSE;
6637 switch (patch_info->type) {
6638 case MONO_PATCH_INFO_R8:
6639 case MONO_PATCH_INFO_R4: {
6642 /* The SSE opcodes require a 16 byte alignment */
6643 code = (guint8*)ALIGN_TO (code, 16);
6645 pos = cfg->native_code + patch_info->ip.i;
6647 if (IS_REX (pos [1]))
6648 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6650 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6652 if (patch_info->type == MONO_PATCH_INFO_R8) {
6653 *(double*)code = *(double*)patch_info->data.target;
6654 code += sizeof (double);
6656 *(float*)code = *(float*)patch_info->data.target;
6657 code += sizeof (float);
6663 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
6666 if (cfg->compile_aot)
6669 /*loading is faster against aligned addresses.*/
6670 code = (guint8*)ALIGN_TO (code, 8);
6672 pos = cfg->native_code + patch_info->ip.i;
6674 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
6675 if (IS_REX (pos [1]))
6676 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6678 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
6680 *(gpointer*)code = (gpointer)patch_info->data.target;
6681 code += sizeof (gpointer);
6691 if (patch_info == cfg->patch_info)
6692 cfg->patch_info = patch_info->next;
6696 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6698 tmp->next = patch_info->next;
6703 cfg->code_len = code - cfg->native_code;
6705 g_assert (cfg->code_len < cfg->code_size);
6709 #endif /* DISABLE_JIT */
6712 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6715 CallInfo *cinfo = NULL;
6716 MonoMethodSignature *sig;
6718 int i, n, stack_area = 0;
6720 /* Keep this in sync with mono_arch_get_argument_info */
6722 if (enable_arguments) {
6723 /* Allocate a new area on the stack and save arguments there */
6724 sig = mono_method_signature (cfg->method);
6726 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6728 n = sig->param_count + sig->hasthis;
6730 stack_area = ALIGN_TO (n * 8, 16);
6732 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6734 for (i = 0; i < n; ++i) {
6735 inst = cfg->args [i];
6737 if (inst->opcode == OP_REGVAR)
6738 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6740 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6741 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6746 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6747 amd64_set_reg_template (code, AMD64_ARG_REG1);
6748 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6749 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6751 if (enable_arguments)
6752 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6766 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6769 int save_mode = SAVE_NONE;
6770 MonoMethod *method = cfg->method;
6771 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6773 switch (ret_type->type) {
6774 case MONO_TYPE_VOID:
6775 /* special case string .ctor icall */
6776 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6777 save_mode = SAVE_EAX;
6779 save_mode = SAVE_NONE;
6783 save_mode = SAVE_EAX;
6787 save_mode = SAVE_XMM;
6789 case MONO_TYPE_GENERICINST:
6790 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6791 save_mode = SAVE_EAX;
6795 case MONO_TYPE_VALUETYPE:
6796 save_mode = SAVE_STRUCT;
6799 save_mode = SAVE_EAX;
6803 /* Save the result and copy it into the proper argument register */
6804 switch (save_mode) {
6806 amd64_push_reg (code, AMD64_RAX);
6808 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6809 if (enable_arguments)
6810 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6814 if (enable_arguments)
6815 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6818 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6819 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6821 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6823 * The result is already in the proper argument register so no copying
6830 g_assert_not_reached ();
6833 /* Set %al since this is a varargs call */
6834 if (save_mode == SAVE_XMM)
6835 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6837 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6839 if (preserve_argument_registers) {
6840 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6841 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6844 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6845 amd64_set_reg_template (code, AMD64_ARG_REG1);
6846 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6848 if (preserve_argument_registers) {
6849 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6850 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6853 /* Restore result */
6854 switch (save_mode) {
6856 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6857 amd64_pop_reg (code, AMD64_RAX);
6863 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6864 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6865 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6870 g_assert_not_reached ();
6877 mono_arch_flush_icache (guint8 *code, gint size)
6883 mono_arch_flush_register_windows (void)
6888 mono_arch_is_inst_imm (gint64 imm)
6890 return amd64_is_imm32 (imm);
6894 * Determine whenever the trap whose info is in SIGINFO is caused by
6898 mono_arch_is_int_overflow (void *sigctx, void *info)
6905 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6907 rip = (guint8*)ctx.rip;
6909 if (IS_REX (rip [0])) {
6910 reg = amd64_rex_b (rip [0]);
6916 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6918 reg += x86_modrm_rm (rip [1]);
6958 g_assert_not_reached ();
6970 mono_arch_get_patch_offset (guint8 *code)
6976 * mono_breakpoint_clean_code:
6978 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6979 * breakpoints in the original code, they are removed in the copy.
6981 * Returns TRUE if no sw breakpoint was present.
6984 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6987 gboolean can_write = TRUE;
6989 * If method_start is non-NULL we need to perform bound checks, since we access memory
6990 * at code - offset we could go before the start of the method and end up in a different
6991 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6994 if (!method_start || code - offset >= method_start) {
6995 memcpy (buf, code - offset, size);
6997 int diff = code - method_start;
6998 memset (buf, 0, size);
6999 memcpy (buf + offset - diff, method_start, diff + size - offset);
7002 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7003 int idx = mono_breakpoint_info_index [i];
7007 ptr = mono_breakpoint_info [idx].address;
7008 if (ptr >= code && ptr < code + size) {
7009 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7011 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7012 buf [ptr - code] = saved_byte;
7019 mono_arch_get_this_arg_reg (guint8 *code)
7021 return AMD64_ARG_REG1;
7025 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7027 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7030 #define MAX_ARCH_DELEGATE_PARAMS 10
7033 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7035 guint8 *code, *start;
7039 start = code = mono_global_codeman_reserve (64);
7041 /* Replace the this argument with the target */
7042 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7043 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7044 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7046 g_assert ((code - start) < 64);
7048 start = code = mono_global_codeman_reserve (64);
7050 if (param_count == 0) {
7051 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7053 /* We have to shift the arguments left */
7054 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7055 for (i = 0; i < param_count; ++i) {
7058 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7060 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7062 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7066 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7068 g_assert ((code - start) < 64);
7071 mono_debug_add_delegate_trampoline (start, code - start);
7074 *code_len = code - start;
7077 if (mono_jit_map_is_enabled ()) {
7080 buff = (char*)"delegate_invoke_has_target";
7082 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7083 mono_emit_jit_tramp (start, code - start, buff);
7092 * mono_arch_get_delegate_invoke_impls:
7094 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7098 mono_arch_get_delegate_invoke_impls (void)
7105 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7106 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7108 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7109 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7110 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7117 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7119 guint8 *code, *start;
7122 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7125 /* FIXME: Support more cases */
7126 if (MONO_TYPE_ISSTRUCT (sig->ret))
7130 static guint8* cached = NULL;
7136 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7138 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7140 mono_memory_barrier ();
7144 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7145 for (i = 0; i < sig->param_count; ++i)
7146 if (!mono_is_regsize_var (sig->params [i]))
7148 if (sig->param_count > 4)
7151 code = cache [sig->param_count];
7155 if (mono_aot_only) {
7156 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7157 start = mono_aot_get_trampoline (name);
7160 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7163 mono_memory_barrier ();
7165 cache [sig->param_count] = start;
7172 * Support for fast access to the thread-local lmf structure using the GS
7173 * segment register on NPTL + kernel 2.6.x.
7176 static gboolean tls_offset_inited = FALSE;
7179 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7181 if (!tls_offset_inited) {
7184 * We need to init this multiple times, since when we are first called, the key might not
7185 * be initialized yet.
7187 appdomain_tls_offset = mono_domain_get_tls_key ();
7188 lmf_tls_offset = mono_get_jit_tls_key ();
7189 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7191 /* Only 64 tls entries can be accessed using inline code */
7192 if (appdomain_tls_offset >= 64)
7193 appdomain_tls_offset = -1;
7194 if (lmf_tls_offset >= 64)
7195 lmf_tls_offset = -1;
7197 tls_offset_inited = TRUE;
7199 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7201 appdomain_tls_offset = mono_domain_get_tls_offset ();
7202 lmf_tls_offset = mono_get_lmf_tls_offset ();
7203 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7209 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7213 #ifdef MONO_ARCH_HAVE_IMT
7215 #define CMP_SIZE (6 + 1)
7216 #define CMP_REG_REG_SIZE (4 + 1)
7217 #define BR_SMALL_SIZE 2
7218 #define BR_LARGE_SIZE 6
7219 #define MOV_REG_IMM_SIZE 10
7220 #define MOV_REG_IMM_32BIT_SIZE 6
7221 #define JUMP_REG_SIZE (2 + 1)
7224 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7226 int i, distance = 0;
7227 for (i = start; i < target; ++i)
7228 distance += imt_entries [i]->chunk_size;
7233 * LOCKING: called with the domain lock held
7236 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7237 gpointer fail_tramp)
7241 guint8 *code, *start;
7242 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7244 for (i = 0; i < count; ++i) {
7245 MonoIMTCheckItem *item = imt_entries [i];
7246 if (item->is_equals) {
7247 if (item->check_target_idx) {
7248 if (!item->compare_done) {
7249 if (amd64_is_imm32 (item->key))
7250 item->chunk_size += CMP_SIZE;
7252 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7254 if (item->has_target_code) {
7255 item->chunk_size += MOV_REG_IMM_SIZE;
7257 if (vtable_is_32bit)
7258 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7260 item->chunk_size += MOV_REG_IMM_SIZE;
7262 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7265 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7266 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7268 if (vtable_is_32bit)
7269 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7271 item->chunk_size += MOV_REG_IMM_SIZE;
7272 item->chunk_size += JUMP_REG_SIZE;
7273 /* with assert below:
7274 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7279 if (amd64_is_imm32 (item->key))
7280 item->chunk_size += CMP_SIZE;
7282 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7283 item->chunk_size += BR_LARGE_SIZE;
7284 imt_entries [item->check_target_idx]->compare_done = TRUE;
7286 size += item->chunk_size;
7289 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7291 code = mono_domain_code_reserve (domain, size);
7293 for (i = 0; i < count; ++i) {
7294 MonoIMTCheckItem *item = imt_entries [i];
7295 item->code_target = code;
7296 if (item->is_equals) {
7297 gboolean fail_case = !item->check_target_idx && fail_tramp;
7299 if (item->check_target_idx || fail_case) {
7300 if (!item->compare_done || fail_case) {
7301 if (amd64_is_imm32 (item->key))
7302 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7304 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7305 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7308 item->jmp_code = code;
7309 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7310 if (item->has_target_code) {
7311 amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7312 amd64_jump_reg (code, AMD64_R11);
7314 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7315 amd64_jump_membase (code, AMD64_R11, 0);
7319 amd64_patch (item->jmp_code, code);
7320 amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7321 amd64_jump_reg (code, AMD64_R11);
7322 item->jmp_code = NULL;
7325 /* enable the commented code to assert on wrong method */
7327 if (amd64_is_imm32 (item->key))
7328 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7330 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7331 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7333 item->jmp_code = code;
7334 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7335 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7336 amd64_jump_membase (code, AMD64_R11, 0);
7337 amd64_patch (item->jmp_code, code);
7338 amd64_breakpoint (code);
7339 item->jmp_code = NULL;
7341 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7342 amd64_jump_membase (code, AMD64_R11, 0);
7346 if (amd64_is_imm32 (item->key))
7347 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7349 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7350 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7352 item->jmp_code = code;
7353 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7354 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7356 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7358 g_assert (code - item->code_target <= item->chunk_size);
7360 /* patch the branches to get to the target items */
7361 for (i = 0; i < count; ++i) {
7362 MonoIMTCheckItem *item = imt_entries [i];
7363 if (item->jmp_code) {
7364 if (item->check_target_idx) {
7365 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7371 mono_stats.imt_thunks_size += code - start;
7372 g_assert (code - start <= size);
7378 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7380 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7385 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7387 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7391 mono_arch_get_cie_program (void)
7395 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7396 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7402 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7404 MonoInst *ins = NULL;
7407 if (cmethod->klass == mono_defaults.math_class) {
7408 if (strcmp (cmethod->name, "Sin") == 0) {
7410 } else if (strcmp (cmethod->name, "Cos") == 0) {
7412 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7414 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7419 MONO_INST_NEW (cfg, ins, opcode);
7420 ins->type = STACK_R8;
7421 ins->dreg = mono_alloc_freg (cfg);
7422 ins->sreg1 = args [0]->dreg;
7423 MONO_ADD_INS (cfg->cbb, ins);
7427 if (cfg->opt & MONO_OPT_CMOV) {
7428 if (strcmp (cmethod->name, "Min") == 0) {
7429 if (fsig->params [0]->type == MONO_TYPE_I4)
7431 if (fsig->params [0]->type == MONO_TYPE_U4)
7432 opcode = OP_IMIN_UN;
7433 else if (fsig->params [0]->type == MONO_TYPE_I8)
7435 else if (fsig->params [0]->type == MONO_TYPE_U8)
7436 opcode = OP_LMIN_UN;
7437 } else if (strcmp (cmethod->name, "Max") == 0) {
7438 if (fsig->params [0]->type == MONO_TYPE_I4)
7440 if (fsig->params [0]->type == MONO_TYPE_U4)
7441 opcode = OP_IMAX_UN;
7442 else if (fsig->params [0]->type == MONO_TYPE_I8)
7444 else if (fsig->params [0]->type == MONO_TYPE_U8)
7445 opcode = OP_LMAX_UN;
7450 MONO_INST_NEW (cfg, ins, opcode);
7451 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7452 ins->dreg = mono_alloc_ireg (cfg);
7453 ins->sreg1 = args [0]->dreg;
7454 ins->sreg2 = args [1]->dreg;
7455 MONO_ADD_INS (cfg->cbb, ins);
7459 /* OP_FREM is not IEEE compatible */
7460 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7461 MONO_INST_NEW (cfg, ins, OP_FREM);
7462 ins->inst_i0 = args [0];
7463 ins->inst_i1 = args [1];
7469 * Can't implement CompareExchange methods this way since they have
7477 mono_arch_print_tree (MonoInst *tree, int arity)
7482 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7486 if (appdomain_tls_offset == -1)
7489 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7490 ins->inst_offset = appdomain_tls_offset;
7494 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7497 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7500 case AMD64_RCX: return (gpointer)ctx->rcx;
7501 case AMD64_RDX: return (gpointer)ctx->rdx;
7502 case AMD64_RBX: return (gpointer)ctx->rbx;
7503 case AMD64_RBP: return (gpointer)ctx->rbp;
7504 case AMD64_RSP: return (gpointer)ctx->rsp;
7507 return _CTX_REG (ctx, rax, reg);
7509 return _CTX_REG (ctx, r12, reg - 12);
7511 g_assert_not_reached ();
7515 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
7517 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7520 gpointer *sp, old_value;
7522 const unsigned char *handler;
7524 /*Decode the first instruction to figure out where did we store the spvar*/
7525 /*Our jit MUST generate the following:
7528 Which is encoded as: REX.W 0x89 mod_rm
7529 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
7530 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
7531 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
7533 FIXME can we generate frameless methods on this case?
7536 handler = clause->handler_start;
7539 if (*handler != 0x48)
7544 if (*handler != 0x89)
7548 if (*handler == 0x65)
7549 offset = *(signed char*)(handler + 1);
7550 else if (*handler == 0xA5)
7551 offset = *(int*)(handler + 1);
7556 bp = MONO_CONTEXT_GET_BP (ctx);
7557 sp = *(gpointer*)(bp + offset);
7560 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7569 * mono_arch_emit_load_aotconst:
7571 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7572 * TARGET from the mscorlib GOT in full-aot code.
7573 * On AMD64, the result is placed into R11.
7576 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7578 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7579 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7585 * mono_arch_get_trampolines:
7587 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7591 mono_arch_get_trampolines (gboolean aot)
7593 MonoTrampInfo *info;
7594 GSList *tramps = NULL;
7596 mono_arch_get_throw_pending_exception (&info, aot);
7598 tramps = g_slist_append (tramps, info);
7603 /* Soft Debug support */
7604 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7607 * mono_arch_set_breakpoint:
7609 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7610 * The location should contain code emitted by OP_SEQ_POINT.
7613 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7616 guint8 *orig_code = code;
7619 * In production, we will use int3 (has to fix the size in the md
7620 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7623 g_assert (code [0] == 0x90);
7624 if (breakpoint_size == 8) {
7625 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7627 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7628 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7631 g_assert (code - orig_code == breakpoint_size);
7635 * mono_arch_clear_breakpoint:
7637 * Clear the breakpoint at IP.
7640 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7645 for (i = 0; i < breakpoint_size; ++i)
7650 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7653 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7656 siginfo_t* sinfo = (siginfo_t*) info;
7657 /* Sometimes the address is off by 4 */
7658 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7666 * mono_arch_get_ip_for_breakpoint:
7668 * Convert the ip in CTX to the address where a breakpoint was placed.
7671 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7673 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7675 /* ip points to the instruction causing the fault */
7676 ip -= (breakpoint_size - breakpoint_fault_size);
7682 * mono_arch_skip_breakpoint:
7684 * Modify CTX so the ip is placed after the breakpoint instruction, so when
7685 * we resume, the instruction is not executed again.
7688 mono_arch_skip_breakpoint (MonoContext *ctx)
7690 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7694 * mono_arch_start_single_stepping:
7696 * Start single stepping.
7699 mono_arch_start_single_stepping (void)
7701 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7705 * mono_arch_stop_single_stepping:
7707 * Stop single stepping.
7710 mono_arch_stop_single_stepping (void)
7712 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7716 * mono_arch_is_single_step_event:
7718 * Return whenever the machine state in SIGCTX corresponds to a single
7722 mono_arch_is_single_step_event (void *info, void *sigctx)
7725 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7728 siginfo_t* sinfo = (siginfo_t*) info;
7729 /* Sometimes the address is off by 4 */
7730 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7738 * mono_arch_get_ip_for_single_step:
7740 * Convert the ip in CTX to the address stored in seq_points.
7743 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7745 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7747 ip += single_step_fault_size;
7753 * mono_arch_skip_single_step:
7755 * Modify CTX so the ip is placed after the single step trigger instruction,
7756 * we resume, the instruction is not executed again.
7759 mono_arch_skip_single_step (MonoContext *ctx)
7761 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7765 * mono_arch_create_seq_point_info:
7767 * Return a pointer to a data structure which is used by the sequence
7768 * point implementation in AOTed code.
7771 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)