2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
39 #include "mini-amd64.h"
40 #include "cpu-amd64.h"
41 #include "debugger-agent.h"
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
66 static mono_mutex_t mini_arch_mutex;
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 * The code generated for sequence points reads from this location, which is
73 * made read-only when single stepping is enabled.
75 static gpointer ss_trigger_page;
77 /* Enabled breakpoints read from this trigger page */
78 static gpointer bp_trigger_page;
80 /* The size of the breakpoint sequence */
81 static int breakpoint_size;
83 /* The size of the breakpoint instruction causing the actual fault */
84 static int breakpoint_fault_size;
86 /* The size of the single step instruction causing the actual fault */
87 static int single_step_fault_size;
89 /* The single step trampoline */
90 static gpointer ss_trampoline;
92 /* Offset between fp and the first argument in the callee */
93 #define ARGS_OFFSET 16
94 #define GP_SCRATCH_REG AMD64_R11
97 * AMD64 register usage:
98 * - callee saved registers are used for global register allocation
99 * - %r11 is used for materializing 64 bit constants in opcodes
100 * - the rest is used for local allocation
104 * Floating point comparison results:
114 mono_arch_regname (int reg)
117 case AMD64_RAX: return "%rax";
118 case AMD64_RBX: return "%rbx";
119 case AMD64_RCX: return "%rcx";
120 case AMD64_RDX: return "%rdx";
121 case AMD64_RSP: return "%rsp";
122 case AMD64_RBP: return "%rbp";
123 case AMD64_RDI: return "%rdi";
124 case AMD64_RSI: return "%rsi";
125 case AMD64_R8: return "%r8";
126 case AMD64_R9: return "%r9";
127 case AMD64_R10: return "%r10";
128 case AMD64_R11: return "%r11";
129 case AMD64_R12: return "%r12";
130 case AMD64_R13: return "%r13";
131 case AMD64_R14: return "%r14";
132 case AMD64_R15: return "%r15";
137 static const char * packed_xmmregs [] = {
138 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
139 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
142 static const char * single_xmmregs [] = {
143 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
144 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
148 mono_arch_fregname (int reg)
150 if (reg < AMD64_XMM_NREG)
151 return single_xmmregs [reg];
157 mono_arch_xregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return packed_xmmregs [reg];
169 return mono_debug_count ();
175 static inline gboolean
176 amd64_is_near_call (guint8 *code)
179 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
182 return code [0] == 0xe8;
185 #ifdef __native_client_codegen__
187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
188 /* for any given instruction. For instance, amd64_call_reg resolves to */
189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
190 /* We only want to force bundle alignment for the top level instruction, */
191 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
192 static MonoNativeTlsKey nacl_instruction_depth;
194 static MonoNativeTlsKey nacl_rex_tag;
195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
198 amd64_nacl_clear_legacy_prefix_tag ()
200 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
204 amd64_nacl_tag_legacy_prefix (guint8* code)
206 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
207 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
211 amd64_nacl_tag_rex (guint8* code)
213 mono_native_tls_set_value (nacl_rex_tag, code);
217 amd64_nacl_get_legacy_prefix_tag ()
219 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
223 amd64_nacl_get_rex_tag ()
225 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
228 /* Increment the instruction "depth" described above */
230 amd64_nacl_instruction_pre ()
232 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
234 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
238 /* alignment if depth == 0 (top level instruction) */
239 /* IN: start, end pointers to instruction beginning and end */
240 /* OUT: start, end pointers to beginning and end after possible alignment */
241 /* GLOBALS: nacl_instruction_depth defined above */
243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
245 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
247 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
249 g_assert ( depth >= 0 );
251 uintptr_t space_in_block;
253 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
254 /* if legacy prefix is present, and if it was emitted before */
255 /* the start of the instruction sequence, adjust the start */
256 if (prefix != NULL && prefix < *start) {
257 g_assert (*start - prefix <= 3);/* only 3 are allowed */
260 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
261 instlen = (uintptr_t)(*end - *start);
262 /* Only check for instructions which are less than */
263 /* kNaClAlignment. The only instructions that should ever */
264 /* be that long are call sequences, which are already */
265 /* padded out to align the return to the next bundle. */
266 if (instlen > space_in_block && instlen < kNaClAlignment) {
267 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
268 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
269 const size_t length = (size_t)((*end)-(*start));
270 g_assert (length < MAX_NACL_INST_LENGTH);
272 memcpy (copy_of_instruction, *start, length);
273 *start = mono_arch_nacl_pad (*start, space_in_block);
274 memcpy (*start, copy_of_instruction, length);
275 *end = *start + length;
277 amd64_nacl_clear_legacy_prefix_tag ();
278 amd64_nacl_tag_rex (NULL);
282 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
283 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
284 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
285 /* make sure the upper 32-bits are cleared, and use that register in the */
286 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
288 /* pointer to current instruction stream (in the */
289 /* middle of an instruction, after opcode is emitted) */
290 /* basereg/offset/dreg */
291 /* operands of normal membase address */
293 /* pointer to the end of the membase/memindex emit */
294 /* GLOBALS: nacl_rex_tag */
295 /* position in instruction stream that rex prefix was emitted */
296 /* nacl_legacy_prefix_tag */
297 /* (possibly NULL) position in instruction of legacy x86 prefix */
299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
301 gint8 true_basereg = basereg;
303 /* Cache these values, they might change */
304 /* as new instructions are emitted below. */
305 guint8* rex_tag = amd64_nacl_get_rex_tag ();
306 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
308 /* 'basereg' is given masked to 0x7 at this point, so check */
309 /* the rex prefix to see if this is an extended register. */
310 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
314 #define X86_LEA_OPCODE (0x8D)
316 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
317 guint8* old_instruction_start;
319 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
320 /* 32-bits of the old base register (new index register) */
322 guint8* buf_ptr = buf;
325 g_assert (rex_tag != NULL);
327 if (IS_REX(*rex_tag)) {
328 /* The old rex.B should be the new rex.X */
329 if (*rex_tag & AMD64_REX_B) {
330 *rex_tag |= AMD64_REX_X;
332 /* Since our new base is %r15 set rex.B */
333 *rex_tag |= AMD64_REX_B;
335 /* Shift the instruction by one byte */
336 /* so we can insert a rex prefix */
337 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
339 /* New rex prefix only needs rex.B for %r15 base */
340 *rex_tag = AMD64_REX(AMD64_REX_B);
343 if (legacy_prefix_tag) {
344 old_instruction_start = legacy_prefix_tag;
346 old_instruction_start = rex_tag;
349 /* Clears the upper 32-bits of the previous base register */
350 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
351 insert_len = buf_ptr - buf;
353 /* Move the old instruction forward to make */
354 /* room for 'mov' stored in 'buf_ptr' */
355 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
357 memcpy (old_instruction_start, buf, insert_len);
359 /* Sandboxed replacement for the normal membase_emit */
360 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
363 /* Normal default behavior, emit membase memory location */
364 x86_membase_emit_body (*code, dreg, basereg, offset);
369 static inline unsigned char*
370 amd64_skip_nops (unsigned char* code)
375 if ( code[0] == 0x90) {
379 if ( code[0] == 0x66 && code[1] == 0x90) {
383 if (code[0] == 0x0f && code[1] == 0x1f
384 && code[2] == 0x00) {
388 if (code[0] == 0x0f && code[1] == 0x1f
389 && code[2] == 0x40 && code[3] == 0x00) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x44 && code[3] == 0x00
395 && code[4] == 0x00) {
399 if (code[0] == 0x66 && code[1] == 0x0f
400 && code[2] == 0x1f && code[3] == 0x44
401 && code[4] == 0x00 && code[5] == 0x00) {
405 if (code[0] == 0x0f && code[1] == 0x1f
406 && code[2] == 0x80 && code[3] == 0x00
407 && code[4] == 0x00 && code[5] == 0x00
408 && code[6] == 0x00) {
412 if (code[0] == 0x0f && code[1] == 0x1f
413 && code[2] == 0x84 && code[3] == 0x00
414 && code[4] == 0x00 && code[5] == 0x00
415 && code[6] == 0x00 && code[7] == 0x00) {
424 mono_arch_nacl_skip_nops (guint8* code)
426 return amd64_skip_nops(code);
429 #endif /*__native_client_codegen__*/
432 amd64_patch (unsigned char* code, gpointer target)
436 #ifdef __native_client_codegen__
437 code = amd64_skip_nops (code);
439 #if defined(__native_client_codegen__) && defined(__native_client__)
440 if (nacl_is_code_address (code)) {
441 /* For tail calls, code is patched after being installed */
442 /* but not through the normal "patch callsite" method. */
443 unsigned char buf[kNaClAlignment];
444 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
446 memcpy (buf, aligned_code, kNaClAlignment);
447 /* Patch a temp buffer of bundle size, */
448 /* then install to actual location. */
449 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
450 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
454 target = nacl_modify_patch_target (target);
458 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
463 if ((code [0] & 0xf8) == 0xb8) {
464 /* amd64_set_reg_template */
465 *(guint64*)(code + 1) = (guint64)target;
467 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
468 /* mov 0(%rip), %dreg */
469 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
471 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
472 /* call *<OFFSET>(%rip) */
473 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
475 else if (code [0] == 0xe8) {
477 gint64 disp = (guint8*)target - (guint8*)code;
478 g_assert (amd64_is_imm32 (disp));
479 x86_patch (code, (unsigned char*)target);
482 x86_patch (code, (unsigned char*)target);
486 mono_amd64_patch (unsigned char* code, gpointer target)
488 amd64_patch (code, target);
497 ArgValuetypeAddrInIReg,
498 ArgNone /* only in pair_storage */
506 /* Only if storage == ArgValuetypeInReg */
507 ArgStorage pair_storage [2];
509 /* The size of each pair */
519 gboolean need_stack_align;
520 gboolean vtype_retaddr;
521 /* The index of the vret arg in the argument list */
528 #define DEBUG(a) if (cfg->verbose_level > 1) a
531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
537 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
543 ainfo->offset = *stack_size;
545 if (*gr >= PARAM_REGS) {
546 ainfo->storage = ArgOnStack;
547 /* Since the same stack slot size is used for all arg */
548 /* types, it needs to be big enough to hold them all */
549 (*stack_size) += sizeof(mgreg_t);
552 ainfo->storage = ArgInIReg;
553 ainfo->reg = param_regs [*gr];
559 #define FLOAT_PARAM_REGS 4
561 #define FLOAT_PARAM_REGS 8
565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
567 ainfo->offset = *stack_size;
569 if (*gr >= FLOAT_PARAM_REGS) {
570 ainfo->storage = ArgOnStack;
571 /* Since the same stack slot size is used for both float */
572 /* types, it needs to be big enough to hold them both */
573 (*stack_size) += sizeof(mgreg_t);
576 /* A double register */
578 ainfo->storage = ArgInDoubleSSEReg;
580 ainfo->storage = ArgInFloatSSEReg;
586 typedef enum ArgumentClass {
594 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
596 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
599 ptype = mini_get_underlying_type (type);
600 switch (ptype->type) {
609 case MONO_TYPE_STRING:
610 case MONO_TYPE_OBJECT:
611 case MONO_TYPE_CLASS:
612 case MONO_TYPE_SZARRAY:
614 case MONO_TYPE_FNPTR:
615 case MONO_TYPE_ARRAY:
618 class2 = ARG_CLASS_INTEGER;
623 class2 = ARG_CLASS_INTEGER;
625 class2 = ARG_CLASS_SSE;
629 case MONO_TYPE_TYPEDBYREF:
630 g_assert_not_reached ();
632 case MONO_TYPE_GENERICINST:
633 if (!mono_type_generic_inst_is_valuetype (ptype)) {
634 class2 = ARG_CLASS_INTEGER;
638 case MONO_TYPE_VALUETYPE: {
639 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
642 for (i = 0; i < info->num_fields; ++i) {
644 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
649 g_assert_not_reached ();
653 if (class1 == class2)
655 else if (class1 == ARG_CLASS_NO_CLASS)
657 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
658 class1 = ARG_CLASS_MEMORY;
659 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
660 class1 = ARG_CLASS_INTEGER;
662 class1 = ARG_CLASS_SSE;
666 #ifdef __native_client_codegen__
668 /* Default alignment for Native Client is 32-byte. */
669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
672 /* Check that alignment doesn't cross an alignment boundary. */
674 mono_arch_nacl_pad(guint8 *code, int pad)
676 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
678 if (pad == 0) return code;
679 /* assertion: alignment cannot cross a block boundary */
680 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
681 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
682 while (pad >= kMaxPadding) {
683 amd64_padding (code, kMaxPadding);
686 if (pad != 0) amd64_padding (code, pad);
692 count_fields_nested (MonoClass *klass)
694 MonoMarshalType *info;
697 info = mono_marshal_load_type_info (klass);
700 for (i = 0; i < info->num_fields; ++i) {
701 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
702 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
712 MonoMarshalType *info;
715 info = mono_marshal_load_type_info (klass);
717 for (i = 0; i < info->num_fields; ++i) {
718 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
719 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
721 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
722 fields [index].offset += offset;
730 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
732 guint32 *gr, guint32 *fr, guint32 *stack_size)
734 guint32 size, quad, nquads, i, nfields;
735 /* Keep track of the size used in each quad so we can */
736 /* use the right size when copying args/return vars. */
737 guint32 quadsize [2] = {8, 8};
738 ArgumentClass args [2];
739 MonoMarshalType *info = NULL;
740 MonoMarshalField *fields = NULL;
742 gboolean pass_on_stack = FALSE;
744 klass = mono_class_from_mono_type (type);
745 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
747 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
748 /* We pass and return vtypes of size 8 in a register */
749 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
750 pass_on_stack = TRUE;
754 pass_on_stack = TRUE;
758 /* If this struct can't be split up naturally into 8-byte */
759 /* chunks (registers), pass it on the stack. */
760 if (sig->pinvoke && !pass_on_stack) {
764 info = mono_marshal_load_type_info (klass);
768 * Collect field information recursively to be able to
769 * handle nested structures.
771 nfields = count_fields_nested (klass);
772 fields = g_new0 (MonoMarshalField, nfields);
773 collect_field_info_nested (klass, fields, 0, 0);
775 for (i = 0; i < nfields; ++i) {
776 field_size = mono_marshal_type_size (fields [i].field->type,
778 &align, TRUE, klass->unicode);
779 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
780 pass_on_stack = TRUE;
788 ainfo->storage = ArgValuetypeInReg;
789 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
795 /* Allways pass in memory */
796 ainfo->offset = *stack_size;
797 *stack_size += ALIGN_TO (size, 8);
798 ainfo->storage = ArgOnStack;
804 /* FIXME: Handle structs smaller than 8 bytes */
805 //if ((size % 8) != 0)
814 int n = mono_class_value_size (klass, NULL);
816 quadsize [0] = n >= 8 ? 8 : n;
817 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
819 /* Always pass in 1 or 2 integer registers */
820 args [0] = ARG_CLASS_INTEGER;
821 args [1] = ARG_CLASS_INTEGER;
822 /* Only the simplest cases are supported */
823 if (is_return && nquads != 1) {
824 args [0] = ARG_CLASS_MEMORY;
825 args [1] = ARG_CLASS_MEMORY;
829 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
830 * The X87 and SSEUP stuff is left out since there are no such types in
836 ainfo->storage = ArgValuetypeInReg;
837 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
842 if (info->native_size > 16) {
843 ainfo->offset = *stack_size;
844 *stack_size += ALIGN_TO (info->native_size, 8);
845 ainfo->storage = ArgOnStack;
851 switch (info->native_size) {
852 case 1: case 2: case 4: case 8:
856 ainfo->storage = ArgOnStack;
857 ainfo->offset = *stack_size;
858 *stack_size += ALIGN_TO (info->native_size, 8);
861 ainfo->storage = ArgValuetypeAddrInIReg;
863 if (*gr < PARAM_REGS) {
864 ainfo->pair_storage [0] = ArgInIReg;
865 ainfo->pair_regs [0] = param_regs [*gr];
869 ainfo->pair_storage [0] = ArgOnStack;
870 ainfo->offset = *stack_size;
880 args [0] = ARG_CLASS_NO_CLASS;
881 args [1] = ARG_CLASS_NO_CLASS;
882 for (quad = 0; quad < nquads; ++quad) {
885 ArgumentClass class1;
888 class1 = ARG_CLASS_MEMORY;
890 class1 = ARG_CLASS_NO_CLASS;
891 for (i = 0; i < nfields; ++i) {
892 size = mono_marshal_type_size (fields [i].field->type,
894 &align, TRUE, klass->unicode);
895 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
896 /* Unaligned field */
900 /* Skip fields in other quad */
901 if ((quad == 0) && (fields [i].offset >= 8))
903 if ((quad == 1) && (fields [i].offset < 8))
906 /* How far into this quad this data extends.*/
907 /* (8 is size of quad) */
908 quadsize [quad] = fields [i].offset + size - (quad * 8);
910 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
912 g_assert (class1 != ARG_CLASS_NO_CLASS);
913 args [quad] = class1;
919 /* Post merger cleanup */
920 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
921 args [0] = args [1] = ARG_CLASS_MEMORY;
923 /* Allocate registers */
928 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
930 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
933 ainfo->storage = ArgValuetypeInReg;
934 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
935 g_assert (quadsize [0] <= 8);
936 g_assert (quadsize [1] <= 8);
937 ainfo->pair_size [0] = quadsize [0];
938 ainfo->pair_size [1] = quadsize [1];
939 ainfo->nregs = nquads;
940 for (quad = 0; quad < nquads; ++quad) {
941 switch (args [quad]) {
942 case ARG_CLASS_INTEGER:
943 if (*gr >= PARAM_REGS)
944 args [quad] = ARG_CLASS_MEMORY;
946 ainfo->pair_storage [quad] = ArgInIReg;
948 ainfo->pair_regs [quad] = return_regs [*gr];
950 ainfo->pair_regs [quad] = param_regs [*gr];
955 if (*fr >= FLOAT_PARAM_REGS)
956 args [quad] = ARG_CLASS_MEMORY;
958 if (quadsize[quad] <= 4)
959 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
960 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
961 ainfo->pair_regs [quad] = *fr;
965 case ARG_CLASS_MEMORY:
968 g_assert_not_reached ();
972 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
973 /* Revert possible register assignments */
977 ainfo->offset = *stack_size;
979 *stack_size += ALIGN_TO (info->native_size, 8);
981 *stack_size += nquads * sizeof(mgreg_t);
982 ainfo->storage = ArgOnStack;
990 * Obtain information about a call according to the calling convention.
991 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
992 * Draft Version 0.23" document for more information.
995 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
997 guint32 i, gr, fr, pstart;
999 int n = sig->hasthis + sig->param_count;
1000 guint32 stack_size = 0;
1002 gboolean is_pinvoke = sig->pinvoke;
1005 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1007 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1015 /* Reserve space where the callee can save the argument registers */
1016 stack_size = 4 * sizeof (mgreg_t);
1020 ret_type = mini_get_underlying_type (sig->ret);
1021 switch (ret_type->type) {
1031 case MONO_TYPE_FNPTR:
1032 case MONO_TYPE_CLASS:
1033 case MONO_TYPE_OBJECT:
1034 case MONO_TYPE_SZARRAY:
1035 case MONO_TYPE_ARRAY:
1036 case MONO_TYPE_STRING:
1037 cinfo->ret.storage = ArgInIReg;
1038 cinfo->ret.reg = AMD64_RAX;
1042 cinfo->ret.storage = ArgInIReg;
1043 cinfo->ret.reg = AMD64_RAX;
1046 cinfo->ret.storage = ArgInFloatSSEReg;
1047 cinfo->ret.reg = AMD64_XMM0;
1050 cinfo->ret.storage = ArgInDoubleSSEReg;
1051 cinfo->ret.reg = AMD64_XMM0;
1053 case MONO_TYPE_GENERICINST:
1054 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1055 cinfo->ret.storage = ArgInIReg;
1056 cinfo->ret.reg = AMD64_RAX;
1060 #if defined( __native_client_codegen__ )
1061 case MONO_TYPE_TYPEDBYREF:
1063 case MONO_TYPE_VALUETYPE: {
1064 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1066 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1067 if (cinfo->ret.storage == ArgOnStack) {
1068 cinfo->vtype_retaddr = TRUE;
1069 /* The caller passes the address where the value is stored */
1073 #if !defined( __native_client_codegen__ )
1074 case MONO_TYPE_TYPEDBYREF:
1075 /* Same as a valuetype with size 24 */
1076 cinfo->vtype_retaddr = TRUE;
1079 case MONO_TYPE_VOID:
1082 g_error ("Can't handle as return value 0x%x", ret_type->type);
1087 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1088 * the first argument, allowing 'this' to be always passed in the first arg reg.
1089 * Also do this if the first argument is a reference type, since virtual calls
1090 * are sometimes made using calli without sig->hasthis set, like in the delegate
1093 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1095 add_general (&gr, &stack_size, cinfo->args + 0);
1097 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1100 add_general (&gr, &stack_size, &cinfo->ret);
1101 cinfo->vret_arg_index = 1;
1105 add_general (&gr, &stack_size, cinfo->args + 0);
1107 if (cinfo->vtype_retaddr)
1108 add_general (&gr, &stack_size, &cinfo->ret);
1111 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1113 fr = FLOAT_PARAM_REGS;
1115 /* Emit the signature cookie just before the implicit arguments */
1116 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1119 for (i = pstart; i < sig->param_count; ++i) {
1120 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1124 /* The float param registers and other param registers must be the same index on Windows x64.*/
1131 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1132 /* We allways pass the sig cookie on the stack for simplicity */
1134 * Prevent implicit arguments + the sig cookie from being passed
1138 fr = FLOAT_PARAM_REGS;
1140 /* Emit the signature cookie just before the implicit arguments */
1141 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1144 ptype = mini_get_underlying_type (sig->params [i]);
1145 switch (ptype->type) {
1148 add_general (&gr, &stack_size, ainfo);
1152 add_general (&gr, &stack_size, ainfo);
1156 add_general (&gr, &stack_size, ainfo);
1161 case MONO_TYPE_FNPTR:
1162 case MONO_TYPE_CLASS:
1163 case MONO_TYPE_OBJECT:
1164 case MONO_TYPE_STRING:
1165 case MONO_TYPE_SZARRAY:
1166 case MONO_TYPE_ARRAY:
1167 add_general (&gr, &stack_size, ainfo);
1169 case MONO_TYPE_GENERICINST:
1170 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171 add_general (&gr, &stack_size, ainfo);
1175 case MONO_TYPE_VALUETYPE:
1176 case MONO_TYPE_TYPEDBYREF:
1177 add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1182 add_general (&gr, &stack_size, ainfo);
1185 add_float (&fr, &stack_size, ainfo, FALSE);
1188 add_float (&fr, &stack_size, ainfo, TRUE);
1191 g_assert_not_reached ();
1195 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1197 fr = FLOAT_PARAM_REGS;
1199 /* Emit the signature cookie just before the implicit arguments */
1200 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1203 cinfo->stack_usage = stack_size;
1204 cinfo->reg_usage = gr;
1205 cinfo->freg_usage = fr;
1210 * mono_arch_get_argument_info:
1211 * @csig: a method signature
1212 * @param_count: the number of parameters to consider
1213 * @arg_info: an array to store the result infos
1215 * Gathers information on parameters such as size, alignment and
1216 * padding. arg_info should be large enought to hold param_count + 1 entries.
1218 * Returns the size of the argument area on the stack.
1221 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1224 CallInfo *cinfo = get_call_info (NULL, csig);
1225 guint32 args_size = cinfo->stack_usage;
1227 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228 if (csig->hasthis) {
1229 arg_info [0].offset = 0;
1232 for (k = 0; k < param_count; k++) {
1233 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1235 arg_info [k + 1].size = 0;
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1248 MonoType *callee_ret;
1250 c1 = get_call_info (NULL, caller_sig);
1251 c2 = get_call_info (NULL, callee_sig);
1252 res = c1->stack_usage >= c2->stack_usage;
1253 callee_ret = mini_get_underlying_type (callee_sig->ret);
1254 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255 /* An address on the callee's stack is passed as the first argument */
1265 * Initialize the cpu to execute managed code.
1268 mono_arch_cpu_init (void)
1273 /* spec compliance requires running with double precision */
1274 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 fpcw &= ~X86_FPCW_PRECC_MASK;
1276 fpcw |= X86_FPCW_PREC_DOUBLE;
1277 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1280 /* TODO: This is crashing on Win64 right now.
1281 * _control87 (_PC_53, MCW_PC);
1287 * Initialize architecture specific code.
1290 mono_arch_init (void)
1294 mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303 flags = MONO_MMAP_READ;
1304 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305 breakpoint_size = 13;
1306 breakpoint_fault_size = 3;
1308 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309 /* amd64_mov_reg_mem () */
1310 breakpoint_size = 8;
1311 breakpoint_fault_size = 8;
1314 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315 single_step_fault_size = 4;
1317 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1321 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1324 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1328 * Cleanup architecture specific code.
1331 mono_arch_cleanup (void)
1333 mono_mutex_destroy (&mini_arch_mutex);
1334 #if defined(__native_client_codegen__)
1335 mono_native_tls_free (nacl_instruction_depth);
1336 mono_native_tls_free (nacl_rex_tag);
1337 mono_native_tls_free (nacl_legacy_prefix_tag);
1342 * This function returns the optimizations supported on this cpu.
1345 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1351 if (mono_hwcap_x86_has_cmov) {
1352 opts |= MONO_OPT_CMOV;
1354 if (mono_hwcap_x86_has_fcmov)
1355 opts |= MONO_OPT_FCMOV;
1357 *exclude_mask |= MONO_OPT_FCMOV;
1359 *exclude_mask |= MONO_OPT_CMOV;
1366 * This function test for all SSE functions supported.
1368 * Returns a bitmask corresponding to all supported versions.
1372 mono_arch_cpu_enumerate_simd_versions (void)
1374 guint32 sse_opts = 0;
1376 if (mono_hwcap_x86_has_sse1)
1377 sse_opts |= SIMD_VERSION_SSE1;
1379 if (mono_hwcap_x86_has_sse2)
1380 sse_opts |= SIMD_VERSION_SSE2;
1382 if (mono_hwcap_x86_has_sse3)
1383 sse_opts |= SIMD_VERSION_SSE3;
1385 if (mono_hwcap_x86_has_ssse3)
1386 sse_opts |= SIMD_VERSION_SSSE3;
1388 if (mono_hwcap_x86_has_sse41)
1389 sse_opts |= SIMD_VERSION_SSE41;
1391 if (mono_hwcap_x86_has_sse42)
1392 sse_opts |= SIMD_VERSION_SSE42;
1394 if (mono_hwcap_x86_has_sse4a)
1395 sse_opts |= SIMD_VERSION_SSE4a;
1403 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1408 for (i = 0; i < cfg->num_varinfo; i++) {
1409 MonoInst *ins = cfg->varinfo [i];
1410 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1413 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1416 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1417 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1420 if (mono_is_regsize_var (ins->inst_vtype)) {
1421 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1422 g_assert (i == vmv->idx);
1423 vars = g_list_prepend (vars, vmv);
1427 vars = mono_varlist_sort (cfg, vars, 0);
1433 * mono_arch_compute_omit_fp:
1435 * Determine whenever the frame pointer can be eliminated.
1438 mono_arch_compute_omit_fp (MonoCompile *cfg)
1440 MonoMethodSignature *sig;
1441 MonoMethodHeader *header;
1445 if (cfg->arch.omit_fp_computed)
1448 header = cfg->header;
1450 sig = mono_method_signature (cfg->method);
1452 if (!cfg->arch.cinfo)
1453 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1454 cinfo = cfg->arch.cinfo;
1457 * FIXME: Remove some of the restrictions.
1459 cfg->arch.omit_fp = TRUE;
1460 cfg->arch.omit_fp_computed = TRUE;
1462 #ifdef __native_client_codegen__
1463 /* NaCl modules may not change the value of RBP, so it cannot be */
1464 /* used as a normal register, but it can be used as a frame pointer*/
1465 cfg->disable_omit_fp = TRUE;
1466 cfg->arch.omit_fp = FALSE;
1469 if (cfg->disable_omit_fp)
1470 cfg->arch.omit_fp = FALSE;
1472 if (!debug_omit_fp ())
1473 cfg->arch.omit_fp = FALSE;
1475 if (cfg->method->save_lmf)
1476 cfg->arch.omit_fp = FALSE;
1478 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1479 cfg->arch.omit_fp = FALSE;
1480 if (header->num_clauses)
1481 cfg->arch.omit_fp = FALSE;
1482 if (cfg->param_area)
1483 cfg->arch.omit_fp = FALSE;
1484 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1485 cfg->arch.omit_fp = FALSE;
1486 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1487 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1488 cfg->arch.omit_fp = FALSE;
1489 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1490 ArgInfo *ainfo = &cinfo->args [i];
1492 if (ainfo->storage == ArgOnStack) {
1494 * The stack offset can only be determined when the frame
1497 cfg->arch.omit_fp = FALSE;
1502 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1503 MonoInst *ins = cfg->varinfo [i];
1506 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1511 mono_arch_get_global_int_regs (MonoCompile *cfg)
1515 mono_arch_compute_omit_fp (cfg);
1517 if (cfg->arch.omit_fp)
1518 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1520 /* We use the callee saved registers for global allocation */
1521 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1522 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1523 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1524 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1525 #ifndef __native_client_codegen__
1526 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1529 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1530 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1537 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1542 /* All XMM registers */
1543 for (i = 0; i < 16; ++i)
1544 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1550 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1552 static GList *r = NULL;
1557 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1558 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1559 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1560 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1561 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1562 #ifndef __native_client_codegen__
1563 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1566 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1567 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1568 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1569 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1570 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1571 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1572 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1573 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1575 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1582 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1585 static GList *r = NULL;
1590 for (i = 0; i < AMD64_XMM_NREG; ++i)
1591 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1593 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1600 * mono_arch_regalloc_cost:
1602 * Return the cost, in number of memory references, of the action of
1603 * allocating the variable VMV into a register during global register
1607 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1609 MonoInst *ins = cfg->varinfo [vmv->idx];
1611 if (cfg->method->save_lmf)
1612 /* The register is already saved */
1613 /* substract 1 for the invisible store in the prolog */
1614 return (ins->opcode == OP_ARG) ? 0 : 1;
1617 return (ins->opcode == OP_ARG) ? 1 : 2;
1621 * mono_arch_fill_argument_info:
1623 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1627 mono_arch_fill_argument_info (MonoCompile *cfg)
1630 MonoMethodSignature *sig;
1635 sig = mono_method_signature (cfg->method);
1637 cinfo = cfg->arch.cinfo;
1638 sig_ret = mini_get_underlying_type (sig->ret);
1641 * Contrary to mono_arch_allocate_vars (), the information should describe
1642 * where the arguments are at the beginning of the method, not where they can be
1643 * accessed during the execution of the method. The later makes no sense for the
1644 * global register allocator, since a variable can be in more than one location.
1646 if (sig_ret->type != MONO_TYPE_VOID) {
1647 switch (cinfo->ret.storage) {
1649 case ArgInFloatSSEReg:
1650 case ArgInDoubleSSEReg:
1651 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1652 cfg->vret_addr->opcode = OP_REGVAR;
1653 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1656 cfg->ret->opcode = OP_REGVAR;
1657 cfg->ret->inst_c0 = cinfo->ret.reg;
1660 case ArgValuetypeInReg:
1661 cfg->ret->opcode = OP_REGOFFSET;
1662 cfg->ret->inst_basereg = -1;
1663 cfg->ret->inst_offset = -1;
1666 g_assert_not_reached ();
1670 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1671 ArgInfo *ainfo = &cinfo->args [i];
1673 ins = cfg->args [i];
1675 switch (ainfo->storage) {
1677 case ArgInFloatSSEReg:
1678 case ArgInDoubleSSEReg:
1679 ins->opcode = OP_REGVAR;
1680 ins->inst_c0 = ainfo->reg;
1683 ins->opcode = OP_REGOFFSET;
1684 ins->inst_basereg = -1;
1685 ins->inst_offset = -1;
1687 case ArgValuetypeInReg:
1689 ins->opcode = OP_NOP;
1692 g_assert_not_reached ();
1698 mono_arch_allocate_vars (MonoCompile *cfg)
1701 MonoMethodSignature *sig;
1704 guint32 locals_stack_size, locals_stack_align;
1708 sig = mono_method_signature (cfg->method);
1710 cinfo = cfg->arch.cinfo;
1711 sig_ret = mini_get_underlying_type (sig->ret);
1713 mono_arch_compute_omit_fp (cfg);
1716 * We use the ABI calling conventions for managed code as well.
1717 * Exception: valuetypes are only sometimes passed or returned in registers.
1721 * The stack looks like this:
1722 * <incoming arguments passed on the stack>
1724 * <lmf/caller saved registers>
1727 * <localloc area> -> grows dynamically
1731 if (cfg->arch.omit_fp) {
1732 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1733 cfg->frame_reg = AMD64_RSP;
1736 /* Locals are allocated backwards from %fp */
1737 cfg->frame_reg = AMD64_RBP;
1741 cfg->arch.saved_iregs = cfg->used_int_regs;
1742 if (cfg->method->save_lmf)
1743 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1744 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1746 if (cfg->arch.omit_fp)
1747 cfg->arch.reg_save_area_offset = offset;
1748 /* Reserve space for callee saved registers */
1749 for (i = 0; i < AMD64_NREG; ++i)
1750 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1751 offset += sizeof(mgreg_t);
1753 if (!cfg->arch.omit_fp)
1754 cfg->arch.reg_save_area_offset = -offset;
1756 if (sig_ret->type != MONO_TYPE_VOID) {
1757 switch (cinfo->ret.storage) {
1759 case ArgInFloatSSEReg:
1760 case ArgInDoubleSSEReg:
1761 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1762 /* The register is volatile */
1763 cfg->vret_addr->opcode = OP_REGOFFSET;
1764 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1765 if (cfg->arch.omit_fp) {
1766 cfg->vret_addr->inst_offset = offset;
1770 cfg->vret_addr->inst_offset = -offset;
1772 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1773 printf ("vret_addr =");
1774 mono_print_ins (cfg->vret_addr);
1778 cfg->ret->opcode = OP_REGVAR;
1779 cfg->ret->inst_c0 = cinfo->ret.reg;
1782 case ArgValuetypeInReg:
1783 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1784 cfg->ret->opcode = OP_REGOFFSET;
1785 cfg->ret->inst_basereg = cfg->frame_reg;
1786 if (cfg->arch.omit_fp) {
1787 cfg->ret->inst_offset = offset;
1788 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1790 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1791 cfg->ret->inst_offset = - offset;
1795 g_assert_not_reached ();
1797 cfg->ret->dreg = cfg->ret->inst_c0;
1800 /* Allocate locals */
1801 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1802 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1803 char *mname = mono_method_full_name (cfg->method, TRUE);
1804 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1805 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1810 if (locals_stack_align) {
1811 offset += (locals_stack_align - 1);
1812 offset &= ~(locals_stack_align - 1);
1814 if (cfg->arch.omit_fp) {
1815 cfg->locals_min_stack_offset = offset;
1816 cfg->locals_max_stack_offset = offset + locals_stack_size;
1818 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1819 cfg->locals_max_stack_offset = - offset;
1822 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1823 if (offsets [i] != -1) {
1824 MonoInst *ins = cfg->varinfo [i];
1825 ins->opcode = OP_REGOFFSET;
1826 ins->inst_basereg = cfg->frame_reg;
1827 if (cfg->arch.omit_fp)
1828 ins->inst_offset = (offset + offsets [i]);
1830 ins->inst_offset = - (offset + offsets [i]);
1831 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1834 offset += locals_stack_size;
1836 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1837 g_assert (!cfg->arch.omit_fp);
1838 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1839 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1842 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1843 ins = cfg->args [i];
1844 if (ins->opcode != OP_REGVAR) {
1845 ArgInfo *ainfo = &cinfo->args [i];
1846 gboolean inreg = TRUE;
1848 /* FIXME: Allocate volatile arguments to registers */
1849 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1853 * Under AMD64, all registers used to pass arguments to functions
1854 * are volatile across calls.
1855 * FIXME: Optimize this.
1857 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1860 ins->opcode = OP_REGOFFSET;
1862 switch (ainfo->storage) {
1864 case ArgInFloatSSEReg:
1865 case ArgInDoubleSSEReg:
1867 ins->opcode = OP_REGVAR;
1868 ins->dreg = ainfo->reg;
1872 g_assert (!cfg->arch.omit_fp);
1873 ins->opcode = OP_REGOFFSET;
1874 ins->inst_basereg = cfg->frame_reg;
1875 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1877 case ArgValuetypeInReg:
1879 case ArgValuetypeAddrInIReg: {
1881 g_assert (!cfg->arch.omit_fp);
1883 MONO_INST_NEW (cfg, indir, 0);
1884 indir->opcode = OP_REGOFFSET;
1885 if (ainfo->pair_storage [0] == ArgInIReg) {
1886 indir->inst_basereg = cfg->frame_reg;
1887 offset = ALIGN_TO (offset, sizeof (gpointer));
1888 offset += (sizeof (gpointer));
1889 indir->inst_offset = - offset;
1892 indir->inst_basereg = cfg->frame_reg;
1893 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1896 ins->opcode = OP_VTARG_ADDR;
1897 ins->inst_left = indir;
1905 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1906 ins->opcode = OP_REGOFFSET;
1907 ins->inst_basereg = cfg->frame_reg;
1908 /* These arguments are saved to the stack in the prolog */
1909 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1910 if (cfg->arch.omit_fp) {
1911 ins->inst_offset = offset;
1912 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1913 // Arguments are yet supported by the stack map creation code
1914 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1916 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1917 ins->inst_offset = - offset;
1918 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1924 cfg->stack_offset = offset;
1928 mono_arch_create_vars (MonoCompile *cfg)
1930 MonoMethodSignature *sig;
1934 sig = mono_method_signature (cfg->method);
1936 if (!cfg->arch.cinfo)
1937 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1938 cinfo = cfg->arch.cinfo;
1940 if (cinfo->ret.storage == ArgValuetypeInReg)
1941 cfg->ret_var_is_local = TRUE;
1943 sig_ret = mini_get_underlying_type (sig->ret);
1944 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1945 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1946 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1947 printf ("vret_addr = ");
1948 mono_print_ins (cfg->vret_addr);
1952 if (cfg->gen_sdb_seq_points) {
1955 if (cfg->compile_aot) {
1956 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1957 ins->flags |= MONO_INST_VOLATILE;
1958 cfg->arch.seq_point_info_var = ins;
1960 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1961 ins->flags |= MONO_INST_VOLATILE;
1962 cfg->arch.ss_tramp_var = ins;
1965 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1966 ins->flags |= MONO_INST_VOLATILE;
1967 cfg->arch.ss_trigger_page_var = ins;
1970 if (cfg->method->save_lmf)
1971 cfg->create_lmf_var = TRUE;
1973 if (cfg->method->save_lmf) {
1975 #if !defined(TARGET_WIN32)
1976 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1977 cfg->lmf_ir_mono_lmf = TRUE;
1983 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1989 MONO_INST_NEW (cfg, ins, OP_MOVE);
1990 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1991 ins->sreg1 = tree->dreg;
1992 MONO_ADD_INS (cfg->cbb, ins);
1993 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1995 case ArgInFloatSSEReg:
1996 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1997 ins->dreg = mono_alloc_freg (cfg);
1998 ins->sreg1 = tree->dreg;
1999 MONO_ADD_INS (cfg->cbb, ins);
2001 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2003 case ArgInDoubleSSEReg:
2004 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2005 ins->dreg = mono_alloc_freg (cfg);
2006 ins->sreg1 = tree->dreg;
2007 MONO_ADD_INS (cfg->cbb, ins);
2009 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2013 g_assert_not_reached ();
2018 arg_storage_to_load_membase (ArgStorage storage)
2022 #if defined(__mono_ilp32__)
2023 return OP_LOADI8_MEMBASE;
2025 return OP_LOAD_MEMBASE;
2027 case ArgInDoubleSSEReg:
2028 return OP_LOADR8_MEMBASE;
2029 case ArgInFloatSSEReg:
2030 return OP_LOADR4_MEMBASE;
2032 g_assert_not_reached ();
2039 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2041 MonoMethodSignature *tmp_sig;
2044 if (call->tail_call)
2047 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2050 * mono_ArgIterator_Setup assumes the signature cookie is
2051 * passed first and all the arguments which were before it are
2052 * passed on the stack after the signature. So compensate by
2053 * passing a different signature.
2055 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2056 tmp_sig->param_count -= call->signature->sentinelpos;
2057 tmp_sig->sentinelpos = 0;
2058 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2060 sig_reg = mono_alloc_ireg (cfg);
2061 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2063 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2067 static inline LLVMArgStorage
2068 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2072 return LLVMArgInIReg;
2076 g_assert_not_reached ();
2082 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2088 LLVMCallInfo *linfo;
2089 MonoType *t, *sig_ret;
2091 n = sig->param_count + sig->hasthis;
2092 sig_ret = mini_get_underlying_type (sig->ret);
2094 cinfo = get_call_info (cfg->mempool, sig);
2096 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2099 * LLVM always uses the native ABI while we use our own ABI, the
2100 * only difference is the handling of vtypes:
2101 * - we only pass/receive them in registers in some cases, and only
2102 * in 1 or 2 integer registers.
2104 if (cinfo->ret.storage == ArgValuetypeInReg) {
2106 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2107 cfg->disable_llvm = TRUE;
2111 linfo->ret.storage = LLVMArgVtypeInReg;
2112 for (j = 0; j < 2; ++j)
2113 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2116 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2117 /* Vtype returned using a hidden argument */
2118 linfo->ret.storage = LLVMArgVtypeRetAddr;
2119 linfo->vret_arg_index = cinfo->vret_arg_index;
2122 for (i = 0; i < n; ++i) {
2123 ainfo = cinfo->args + i;
2125 if (i >= sig->hasthis)
2126 t = sig->params [i - sig->hasthis];
2128 t = &mono_defaults.int_class->byval_arg;
2130 linfo->args [i].storage = LLVMArgNone;
2132 switch (ainfo->storage) {
2134 linfo->args [i].storage = LLVMArgInIReg;
2136 case ArgInDoubleSSEReg:
2137 case ArgInFloatSSEReg:
2138 linfo->args [i].storage = LLVMArgInFPReg;
2141 if (MONO_TYPE_ISSTRUCT (t)) {
2142 linfo->args [i].storage = LLVMArgVtypeByVal;
2144 linfo->args [i].storage = LLVMArgInIReg;
2146 if (t->type == MONO_TYPE_R4)
2147 linfo->args [i].storage = LLVMArgInFPReg;
2148 else if (t->type == MONO_TYPE_R8)
2149 linfo->args [i].storage = LLVMArgInFPReg;
2153 case ArgValuetypeInReg:
2155 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2156 cfg->disable_llvm = TRUE;
2160 linfo->args [i].storage = LLVMArgVtypeInReg;
2161 for (j = 0; j < 2; ++j)
2162 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2165 cfg->exception_message = g_strdup ("ainfo->storage");
2166 cfg->disable_llvm = TRUE;
2176 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2179 MonoMethodSignature *sig;
2185 sig = call->signature;
2186 n = sig->param_count + sig->hasthis;
2188 cinfo = get_call_info (cfg->mempool, sig);
2192 if (COMPILE_LLVM (cfg)) {
2193 /* We shouldn't be called in the llvm case */
2194 cfg->disable_llvm = TRUE;
2199 * Emit all arguments which are passed on the stack to prevent register
2200 * allocation problems.
2202 for (i = 0; i < n; ++i) {
2204 ainfo = cinfo->args + i;
2206 in = call->args [i];
2208 if (sig->hasthis && i == 0)
2209 t = &mono_defaults.object_class->byval_arg;
2211 t = sig->params [i - sig->hasthis];
2213 t = mini_get_underlying_type (t);
2214 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2216 if (t->type == MONO_TYPE_R4)
2217 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2218 else if (t->type == MONO_TYPE_R8)
2219 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2221 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2223 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2225 if (cfg->compute_gc_maps) {
2228 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2234 * Emit all parameters passed in registers in non-reverse order for better readability
2235 * and to help the optimization in emit_prolog ().
2237 for (i = 0; i < n; ++i) {
2238 ainfo = cinfo->args + i;
2240 in = call->args [i];
2242 if (ainfo->storage == ArgInIReg)
2243 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2246 for (i = n - 1; i >= 0; --i) {
2249 ainfo = cinfo->args + i;
2251 in = call->args [i];
2253 if (sig->hasthis && i == 0)
2254 t = &mono_defaults.object_class->byval_arg;
2256 t = sig->params [i - sig->hasthis];
2257 t = mini_get_underlying_type (t);
2259 switch (ainfo->storage) {
2263 case ArgInFloatSSEReg:
2264 case ArgInDoubleSSEReg:
2265 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2268 case ArgValuetypeInReg:
2269 case ArgValuetypeAddrInIReg:
2270 if (ainfo->storage == ArgOnStack && call->tail_call) {
2271 MonoInst *call_inst = (MonoInst*)call;
2272 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2273 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2274 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2278 if (t->type == MONO_TYPE_TYPEDBYREF) {
2279 size = sizeof (MonoTypedRef);
2280 align = sizeof (gpointer);
2284 size = mono_type_native_stack_size (t, &align);
2287 * Other backends use mono_type_stack_size (), but that
2288 * aligns the size to 8, which is larger than the size of
2289 * the source, leading to reads of invalid memory if the
2290 * source is at the end of address space.
2292 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2295 g_assert (in->klass);
2297 if (ainfo->storage == ArgOnStack && size >= 10000) {
2298 /* Avoid asserts in emit_memcpy () */
2299 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2300 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2301 /* Continue normally */
2305 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2306 arg->sreg1 = in->dreg;
2307 arg->klass = mono_class_from_mono_type (t);
2308 arg->backend.size = size;
2309 arg->inst_p0 = call;
2310 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2311 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2313 MONO_ADD_INS (cfg->cbb, arg);
2318 g_assert_not_reached ();
2321 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2322 /* Emit the signature cookie just before the implicit arguments */
2323 emit_sig_cookie (cfg, call, cinfo);
2326 /* Handle the case where there are no implicit arguments */
2327 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2328 emit_sig_cookie (cfg, call, cinfo);
2330 sig_ret = mini_get_underlying_type (sig->ret);
2331 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2334 if (cinfo->ret.storage == ArgValuetypeInReg) {
2335 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2337 * Tell the JIT to use a more efficient calling convention: call using
2338 * OP_CALL, compute the result location after the call, and save the
2341 call->vret_in_reg = TRUE;
2343 * Nullify the instruction computing the vret addr to enable
2344 * future optimizations.
2347 NULLIFY_INS (call->vret_var);
2349 if (call->tail_call)
2352 * The valuetype is in RAX:RDX after the call, need to be copied to
2353 * the stack. Push the address here, so the call instruction can
2356 if (!cfg->arch.vret_addr_loc) {
2357 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2358 /* Prevent it from being register allocated or optimized away */
2359 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2362 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2366 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2367 vtarg->sreg1 = call->vret_var->dreg;
2368 vtarg->dreg = mono_alloc_preg (cfg);
2369 MONO_ADD_INS (cfg->cbb, vtarg);
2371 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2375 if (cfg->method->save_lmf) {
2376 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2377 MONO_ADD_INS (cfg->cbb, arg);
2380 call->stack_usage = cinfo->stack_usage;
2384 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2387 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2388 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2389 int size = ins->backend.size;
2391 if (ainfo->storage == ArgValuetypeInReg) {
2395 for (part = 0; part < 2; ++part) {
2396 if (ainfo->pair_storage [part] == ArgNone)
2399 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2400 load->inst_basereg = src->dreg;
2401 load->inst_offset = part * sizeof(mgreg_t);
2403 switch (ainfo->pair_storage [part]) {
2405 load->dreg = mono_alloc_ireg (cfg);
2407 case ArgInDoubleSSEReg:
2408 case ArgInFloatSSEReg:
2409 load->dreg = mono_alloc_freg (cfg);
2412 g_assert_not_reached ();
2414 MONO_ADD_INS (cfg->cbb, load);
2416 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2418 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2419 MonoInst *vtaddr, *load;
2420 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2422 MONO_INST_NEW (cfg, load, OP_LDADDR);
2423 cfg->has_indirection = TRUE;
2424 load->inst_p0 = vtaddr;
2425 vtaddr->flags |= MONO_INST_INDIRECT;
2426 load->type = STACK_MP;
2427 load->klass = vtaddr->klass;
2428 load->dreg = mono_alloc_ireg (cfg);
2429 MONO_ADD_INS (cfg->cbb, load);
2430 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2432 if (ainfo->pair_storage [0] == ArgInIReg) {
2433 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2434 arg->dreg = mono_alloc_ireg (cfg);
2435 arg->sreg1 = load->dreg;
2437 MONO_ADD_INS (cfg->cbb, arg);
2438 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2440 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2444 int dreg = mono_alloc_ireg (cfg);
2446 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2447 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2448 } else if (size <= 40) {
2449 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2451 // FIXME: Code growth
2452 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2455 if (cfg->compute_gc_maps) {
2457 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2463 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2465 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2467 if (ret->type == MONO_TYPE_R4) {
2468 if (COMPILE_LLVM (cfg))
2469 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2471 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2473 } else if (ret->type == MONO_TYPE_R8) {
2474 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2478 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2481 #endif /* DISABLE_JIT */
2483 #define EMIT_COND_BRANCH(ins,cond,sign) \
2484 if (ins->inst_true_bb->native_offset) { \
2485 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2487 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2488 if ((cfg->opt & MONO_OPT_BRANCH) && \
2489 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2490 x86_branch8 (code, cond, 0, sign); \
2492 x86_branch32 (code, cond, 0, sign); \
2496 MonoMethodSignature *sig;
2501 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2509 switch (cinfo->ret.storage) {
2513 case ArgValuetypeInReg: {
2514 ArgInfo *ainfo = &cinfo->ret;
2516 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2518 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2526 for (i = 0; i < cinfo->nargs; ++i) {
2527 ArgInfo *ainfo = &cinfo->args [i];
2528 switch (ainfo->storage) {
2531 case ArgValuetypeInReg:
2532 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2534 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2546 * mono_arch_dyn_call_prepare:
2548 * Return a pointer to an arch-specific structure which contains information
2549 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2550 * supported for SIG.
2551 * This function is equivalent to ffi_prep_cif in libffi.
2554 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2556 ArchDynCallInfo *info;
2559 cinfo = get_call_info (NULL, sig);
2561 if (!dyn_call_supported (sig, cinfo)) {
2566 info = g_new0 (ArchDynCallInfo, 1);
2567 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2569 info->cinfo = cinfo;
2571 return (MonoDynCallInfo*)info;
2575 * mono_arch_dyn_call_free:
2577 * Free a MonoDynCallInfo structure.
2580 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2582 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2584 g_free (ainfo->cinfo);
2588 #if !defined(__native_client__)
2589 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2590 #define GREG_TO_PTR(greg) (gpointer)(greg)
2592 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2593 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2594 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2598 * mono_arch_get_start_dyn_call:
2600 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2601 * store the result into BUF.
2602 * ARGS should be an array of pointers pointing to the arguments.
2603 * RET should point to a memory buffer large enought to hold the result of the
2605 * This function should be as fast as possible, any work which does not depend
2606 * on the actual values of the arguments should be done in
2607 * mono_arch_dyn_call_prepare ().
2608 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2612 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2614 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2615 DynCallArgs *p = (DynCallArgs*)buf;
2616 int arg_index, greg, i, pindex;
2617 MonoMethodSignature *sig = dinfo->sig;
2619 g_assert (buf_len >= sizeof (DynCallArgs));
2628 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2629 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2634 if (dinfo->cinfo->vtype_retaddr)
2635 p->regs [greg ++] = PTR_TO_GREG(ret);
2637 for (i = pindex; i < sig->param_count; i++) {
2638 MonoType *t = mini_get_underlying_type (sig->params [i]);
2639 gpointer *arg = args [arg_index ++];
2642 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2647 case MONO_TYPE_STRING:
2648 case MONO_TYPE_CLASS:
2649 case MONO_TYPE_ARRAY:
2650 case MONO_TYPE_SZARRAY:
2651 case MONO_TYPE_OBJECT:
2655 #if !defined(__mono_ilp32__)
2659 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2660 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2662 #if defined(__mono_ilp32__)
2665 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2666 p->regs [greg ++] = *(guint64*)(arg);
2670 p->regs [greg ++] = *(guint8*)(arg);
2673 p->regs [greg ++] = *(gint8*)(arg);
2676 p->regs [greg ++] = *(gint16*)(arg);
2679 p->regs [greg ++] = *(guint16*)(arg);
2682 p->regs [greg ++] = *(gint32*)(arg);
2685 p->regs [greg ++] = *(guint32*)(arg);
2687 case MONO_TYPE_GENERICINST:
2688 if (MONO_TYPE_IS_REFERENCE (t)) {
2689 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2694 case MONO_TYPE_VALUETYPE: {
2695 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2697 g_assert (ainfo->storage == ArgValuetypeInReg);
2698 if (ainfo->pair_storage [0] != ArgNone) {
2699 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2700 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2702 if (ainfo->pair_storage [1] != ArgNone) {
2703 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2704 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2709 g_assert_not_reached ();
2713 g_assert (greg <= PARAM_REGS);
2717 * mono_arch_finish_dyn_call:
2719 * Store the result of a dyn call into the return value buffer passed to
2720 * start_dyn_call ().
2721 * This function should be as fast as possible, any work which does not depend
2722 * on the actual values of the arguments should be done in
2723 * mono_arch_dyn_call_prepare ().
2726 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2728 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2729 MonoMethodSignature *sig = dinfo->sig;
2730 guint8 *ret = ((DynCallArgs*)buf)->ret;
2731 mgreg_t res = ((DynCallArgs*)buf)->res;
2732 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2734 switch (sig_ret->type) {
2735 case MONO_TYPE_VOID:
2736 *(gpointer*)ret = NULL;
2738 case MONO_TYPE_STRING:
2739 case MONO_TYPE_CLASS:
2740 case MONO_TYPE_ARRAY:
2741 case MONO_TYPE_SZARRAY:
2742 case MONO_TYPE_OBJECT:
2746 *(gpointer*)ret = GREG_TO_PTR(res);
2752 *(guint8*)ret = res;
2755 *(gint16*)ret = res;
2758 *(guint16*)ret = res;
2761 *(gint32*)ret = res;
2764 *(guint32*)ret = res;
2767 *(gint64*)ret = res;
2770 *(guint64*)ret = res;
2772 case MONO_TYPE_GENERICINST:
2773 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2774 *(gpointer*)ret = GREG_TO_PTR(res);
2779 case MONO_TYPE_VALUETYPE:
2780 if (dinfo->cinfo->vtype_retaddr) {
2783 ArgInfo *ainfo = &dinfo->cinfo->ret;
2785 g_assert (ainfo->storage == ArgValuetypeInReg);
2787 if (ainfo->pair_storage [0] != ArgNone) {
2788 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2789 ((mgreg_t*)ret)[0] = res;
2792 g_assert (ainfo->pair_storage [1] == ArgNone);
2796 g_assert_not_reached ();
2800 /* emit an exception if condition is fail */
2801 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2803 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2804 if (tins == NULL) { \
2805 mono_add_patch_info (cfg, code - cfg->native_code, \
2806 MONO_PATCH_INFO_EXC, exc_name); \
2807 x86_branch32 (code, cond, 0, signed); \
2809 EMIT_COND_BRANCH (tins, cond, signed); \
2813 #define EMIT_FPCOMPARE(code) do { \
2814 amd64_fcompp (code); \
2815 amd64_fnstsw (code); \
2818 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2819 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2820 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2821 amd64_ ##op (code); \
2822 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2823 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2827 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2829 gboolean no_patch = FALSE;
2832 * FIXME: Add support for thunks
2835 gboolean near_call = FALSE;
2838 * Indirect calls are expensive so try to make a near call if possible.
2839 * The caller memory is allocated by the code manager so it is
2840 * guaranteed to be at a 32 bit offset.
2843 if (patch_type != MONO_PATCH_INFO_ABS) {
2844 /* The target is in memory allocated using the code manager */
2847 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2848 if (((MonoMethod*)data)->klass->image->aot_module)
2849 /* The callee might be an AOT method */
2851 if (((MonoMethod*)data)->dynamic)
2852 /* The target is in malloc-ed memory */
2856 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2858 * The call might go directly to a native function without
2861 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2863 gconstpointer target = mono_icall_get_wrapper (mi);
2864 if ((((guint64)target) >> 32) != 0)
2870 MonoJumpInfo *jinfo = NULL;
2872 if (cfg->abs_patches)
2873 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2875 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2876 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2877 if (mi && (((guint64)mi->func) >> 32) == 0)
2882 * This is not really an optimization, but required because the
2883 * generic class init trampolines use R11 to pass the vtable.
2888 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2890 if (info->func == info->wrapper) {
2892 if ((((guint64)info->func) >> 32) == 0)
2896 /* See the comment in mono_codegen () */
2897 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2901 else if ((((guint64)data) >> 32) == 0) {
2908 if (cfg->method->dynamic)
2909 /* These methods are allocated using malloc */
2912 #ifdef MONO_ARCH_NOMAP32BIT
2915 #if defined(__native_client__)
2916 /* Always use near_call == TRUE for Native Client */
2919 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2920 if (optimize_for_xen)
2923 if (cfg->compile_aot) {
2930 * Align the call displacement to an address divisible by 4 so it does
2931 * not span cache lines. This is required for code patching to work on SMP
2934 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2935 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2936 amd64_padding (code, pad_size);
2938 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2939 amd64_call_code (code, 0);
2942 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2943 amd64_set_reg_template (code, GP_SCRATCH_REG);
2944 amd64_call_reg (code, GP_SCRATCH_REG);
2951 static inline guint8*
2952 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2955 if (win64_adjust_stack)
2956 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2958 code = emit_call_body (cfg, code, patch_type, data);
2960 if (win64_adjust_stack)
2961 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2968 store_membase_imm_to_store_membase_reg (int opcode)
2971 case OP_STORE_MEMBASE_IMM:
2972 return OP_STORE_MEMBASE_REG;
2973 case OP_STOREI4_MEMBASE_IMM:
2974 return OP_STOREI4_MEMBASE_REG;
2975 case OP_STOREI8_MEMBASE_IMM:
2976 return OP_STOREI8_MEMBASE_REG;
2984 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2987 * mono_arch_peephole_pass_1:
2989 * Perform peephole opts which should/can be performed before local regalloc
2992 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2996 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2997 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2999 switch (ins->opcode) {
3003 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3005 * X86_LEA is like ADD, but doesn't have the
3006 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3007 * its operand to 64 bit.
3009 ins->opcode = OP_X86_LEA_MEMBASE;
3010 ins->inst_basereg = ins->sreg1;
3015 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3019 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3020 * the latter has length 2-3 instead of 6 (reverse constant
3021 * propagation). These instruction sequences are very common
3022 * in the initlocals bblock.
3024 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3025 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3026 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3027 ins2->sreg1 = ins->dreg;
3028 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3030 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3033 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3041 case OP_COMPARE_IMM:
3042 case OP_LCOMPARE_IMM:
3043 /* OP_COMPARE_IMM (reg, 0)
3045 * OP_AMD64_TEST_NULL (reg)
3048 ins->opcode = OP_AMD64_TEST_NULL;
3050 case OP_ICOMPARE_IMM:
3052 ins->opcode = OP_X86_TEST_NULL;
3054 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3056 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3057 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3059 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3060 * OP_COMPARE_IMM reg, imm
3062 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3064 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3065 ins->inst_basereg == last_ins->inst_destbasereg &&
3066 ins->inst_offset == last_ins->inst_offset) {
3067 ins->opcode = OP_ICOMPARE_IMM;
3068 ins->sreg1 = last_ins->sreg1;
3070 /* check if we can remove cmp reg,0 with test null */
3072 ins->opcode = OP_X86_TEST_NULL;
3078 mono_peephole_ins (bb, ins);
3083 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3087 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3088 switch (ins->opcode) {
3091 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3092 /* reg = 0 -> XOR (reg, reg) */
3093 /* XOR sets cflags on x86, so we cant do it always */
3094 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3095 ins->opcode = OP_LXOR;
3096 ins->sreg1 = ins->dreg;
3097 ins->sreg2 = ins->dreg;
3105 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3106 * 0 result into 64 bits.
3108 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3109 ins->opcode = OP_IXOR;
3113 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3117 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3118 * the latter has length 2-3 instead of 6 (reverse constant
3119 * propagation). These instruction sequences are very common
3120 * in the initlocals bblock.
3122 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3123 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3124 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3125 ins2->sreg1 = ins->dreg;
3126 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3128 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3131 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3140 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3141 ins->opcode = OP_X86_INC_REG;
3144 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3145 ins->opcode = OP_X86_DEC_REG;
3149 mono_peephole_ins (bb, ins);
3153 #define NEW_INS(cfg,ins,dest,op) do { \
3154 MONO_INST_NEW ((cfg), (dest), (op)); \
3155 (dest)->cil_code = (ins)->cil_code; \
3156 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3160 * mono_arch_lowering_pass:
3162 * Converts complex opcodes into simpler ones so that each IR instruction
3163 * corresponds to one machine instruction.
3166 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3168 MonoInst *ins, *n, *temp;
3171 * FIXME: Need to add more instructions, but the current machine
3172 * description can't model some parts of the composite instructions like
3175 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3176 switch (ins->opcode) {
3180 case OP_IDIV_UN_IMM:
3181 case OP_IREM_UN_IMM:
3184 mono_decompose_op_imm (cfg, bb, ins);
3186 case OP_COMPARE_IMM:
3187 case OP_LCOMPARE_IMM:
3188 if (!amd64_is_imm32 (ins->inst_imm)) {
3189 NEW_INS (cfg, ins, temp, OP_I8CONST);
3190 temp->inst_c0 = ins->inst_imm;
3191 temp->dreg = mono_alloc_ireg (cfg);
3192 ins->opcode = OP_COMPARE;
3193 ins->sreg2 = temp->dreg;
3196 #ifndef __mono_ilp32__
3197 case OP_LOAD_MEMBASE:
3199 case OP_LOADI8_MEMBASE:
3200 #ifndef __native_client_codegen__
3201 /* Don't generate memindex opcodes (to simplify */
3202 /* read sandboxing) */
3203 if (!amd64_is_imm32 (ins->inst_offset)) {
3204 NEW_INS (cfg, ins, temp, OP_I8CONST);
3205 temp->inst_c0 = ins->inst_offset;
3206 temp->dreg = mono_alloc_ireg (cfg);
3207 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3208 ins->inst_indexreg = temp->dreg;
3212 #ifndef __mono_ilp32__
3213 case OP_STORE_MEMBASE_IMM:
3215 case OP_STOREI8_MEMBASE_IMM:
3216 if (!amd64_is_imm32 (ins->inst_imm)) {
3217 NEW_INS (cfg, ins, temp, OP_I8CONST);
3218 temp->inst_c0 = ins->inst_imm;
3219 temp->dreg = mono_alloc_ireg (cfg);
3220 ins->opcode = OP_STOREI8_MEMBASE_REG;
3221 ins->sreg1 = temp->dreg;
3224 #ifdef MONO_ARCH_SIMD_INTRINSICS
3225 case OP_EXPAND_I1: {
3226 int temp_reg1 = mono_alloc_ireg (cfg);
3227 int temp_reg2 = mono_alloc_ireg (cfg);
3228 int original_reg = ins->sreg1;
3230 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3231 temp->sreg1 = original_reg;
3232 temp->dreg = temp_reg1;
3234 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3235 temp->sreg1 = temp_reg1;
3236 temp->dreg = temp_reg2;
3239 NEW_INS (cfg, ins, temp, OP_LOR);
3240 temp->sreg1 = temp->dreg = temp_reg2;
3241 temp->sreg2 = temp_reg1;
3243 ins->opcode = OP_EXPAND_I2;
3244 ins->sreg1 = temp_reg2;
3253 bb->max_vreg = cfg->next_vreg;
3257 branch_cc_table [] = {
3258 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3259 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3260 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3263 /* Maps CMP_... constants to X86_CC_... constants */
3266 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3267 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3271 cc_signed_table [] = {
3272 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3273 FALSE, FALSE, FALSE, FALSE
3276 /*#include "cprop.c"*/
3278 static unsigned char*
3279 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3282 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3284 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3287 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3289 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3293 static unsigned char*
3294 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3296 int sreg = tree->sreg1;
3297 int need_touch = FALSE;
3299 #if defined(TARGET_WIN32)
3301 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3302 if (!tree->flags & MONO_INST_INIT)
3311 * If requested stack size is larger than one page,
3312 * perform stack-touch operation
3315 * Generate stack probe code.
3316 * Under Windows, it is necessary to allocate one page at a time,
3317 * "touching" stack after each successful sub-allocation. This is
3318 * because of the way stack growth is implemented - there is a
3319 * guard page before the lowest stack page that is currently commited.
3320 * Stack normally grows sequentially so OS traps access to the
3321 * guard page and commits more pages when needed.
3323 amd64_test_reg_imm (code, sreg, ~0xFFF);
3324 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3326 br[2] = code; /* loop */
3327 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3328 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3329 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3330 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3331 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3332 amd64_patch (br[3], br[2]);
3333 amd64_test_reg_reg (code, sreg, sreg);
3334 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3335 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3337 br[1] = code; x86_jump8 (code, 0);
3339 amd64_patch (br[0], code);
3340 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3341 amd64_patch (br[1], code);
3342 amd64_patch (br[4], code);
3345 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3347 if (tree->flags & MONO_INST_INIT) {
3349 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3350 amd64_push_reg (code, AMD64_RAX);
3353 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3354 amd64_push_reg (code, AMD64_RCX);
3357 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3358 amd64_push_reg (code, AMD64_RDI);
3362 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3363 if (sreg != AMD64_RCX)
3364 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3365 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3367 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3368 if (cfg->param_area)
3369 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3371 #if defined(__default_codegen__)
3372 amd64_prefix (code, X86_REP_PREFIX);
3374 #elif defined(__native_client_codegen__)
3375 /* NaCl stos pseudo-instruction */
3376 amd64_codegen_pre(code);
3377 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3378 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3379 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3380 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3381 amd64_prefix (code, X86_REP_PREFIX);
3383 amd64_codegen_post(code);
3384 #endif /* __native_client_codegen__ */
3386 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3387 amd64_pop_reg (code, AMD64_RDI);
3388 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3389 amd64_pop_reg (code, AMD64_RCX);
3390 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3391 amd64_pop_reg (code, AMD64_RAX);
3397 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3402 /* Move return value to the target register */
3403 /* FIXME: do this in the local reg allocator */
3404 switch (ins->opcode) {
3407 case OP_CALL_MEMBASE:
3410 case OP_LCALL_MEMBASE:
3411 g_assert (ins->dreg == AMD64_RAX);
3415 case OP_FCALL_MEMBASE: {
3416 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3417 if (rtype->type == MONO_TYPE_R4) {
3418 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3421 if (ins->dreg != AMD64_XMM0)
3422 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3428 case OP_RCALL_MEMBASE:
3429 if (ins->dreg != AMD64_XMM0)
3430 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3434 case OP_VCALL_MEMBASE:
3437 case OP_VCALL2_MEMBASE:
3438 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3439 if (cinfo->ret.storage == ArgValuetypeInReg) {
3440 MonoInst *loc = cfg->arch.vret_addr_loc;
3442 /* Load the destination address */
3443 g_assert (loc->opcode == OP_REGOFFSET);
3444 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3446 for (quad = 0; quad < 2; quad ++) {
3447 switch (cinfo->ret.pair_storage [quad]) {
3449 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3451 case ArgInFloatSSEReg:
3452 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3454 case ArgInDoubleSSEReg:
3455 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3470 #endif /* DISABLE_JIT */
3473 static int tls_gs_offset;
3477 mono_amd64_have_tls_get (void)
3480 static gboolean have_tls_get = FALSE;
3481 static gboolean inited = FALSE;
3484 return have_tls_get;
3486 #if MONO_HAVE_FAST_TLS
3487 guint8 *ins = (guint8*)pthread_getspecific;
3490 * We're looking for these two instructions:
3492 * mov %gs:[offset](,%rdi,8),%rax
3495 have_tls_get = ins [0] == 0x65 &&
3505 tls_gs_offset = ins[5];
3510 return have_tls_get;
3511 #elif defined(TARGET_ANDROID)
3519 mono_amd64_get_tls_gs_offset (void)
3522 return tls_gs_offset;
3524 g_assert_not_reached ();
3530 * mono_amd64_emit_tls_get:
3531 * @code: buffer to store code to
3532 * @dreg: hard register where to place the result
3533 * @tls_offset: offset info
3535 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3536 * the dreg register the item in the thread local storage identified
3539 * Returns: a pointer to the end of the stored code
3542 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3545 if (tls_offset < 64) {
3546 x86_prefix (code, X86_GS_PREFIX);
3547 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3551 g_assert (tls_offset < 0x440);
3552 /* Load TEB->TlsExpansionSlots */
3553 x86_prefix (code, X86_GS_PREFIX);
3554 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3555 amd64_test_reg_reg (code, dreg, dreg);
3557 amd64_branch (code, X86_CC_EQ, code, TRUE);
3558 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3559 amd64_patch (buf [0], code);
3561 #elif defined(__APPLE__)
3562 x86_prefix (code, X86_GS_PREFIX);
3563 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3565 if (optimize_for_xen) {
3566 x86_prefix (code, X86_FS_PREFIX);
3567 amd64_mov_reg_mem (code, dreg, 0, 8);
3568 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3570 x86_prefix (code, X86_FS_PREFIX);
3571 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3578 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3580 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3582 if (dreg != offset_reg)
3583 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3584 amd64_prefix (code, X86_GS_PREFIX);
3585 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3586 #elif defined(__linux__)
3589 if (dreg == offset_reg) {
3590 /* Use a temporary reg by saving it to the redzone */
3591 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3592 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3593 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3594 offset_reg = tmpreg;
3596 x86_prefix (code, X86_FS_PREFIX);
3597 amd64_mov_reg_mem (code, dreg, 0, 8);
3598 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3600 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3602 g_assert_not_reached ();
3608 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3611 g_assert_not_reached ();
3612 #elif defined(__APPLE__)
3613 x86_prefix (code, X86_GS_PREFIX);
3614 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3616 g_assert (!optimize_for_xen);
3617 x86_prefix (code, X86_FS_PREFIX);
3618 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3624 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3626 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3628 g_assert_not_reached ();
3629 #elif defined(__APPLE__)
3630 x86_prefix (code, X86_GS_PREFIX);
3631 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3633 x86_prefix (code, X86_FS_PREFIX);
3634 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3640 * mono_arch_translate_tls_offset:
3642 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3645 mono_arch_translate_tls_offset (int offset)
3648 return tls_gs_offset + (offset * 8);
3657 * Emit code to initialize an LMF structure at LMF_OFFSET.
3660 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3663 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3666 * sp is saved right before calls but we need to save it here too so
3667 * async stack walks would work.
3669 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3671 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3672 if (cfg->arch.omit_fp && cfa_offset != -1)
3673 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3675 /* These can't contain refs */
3676 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3677 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3678 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3679 /* These are handled automatically by the stack marking code */
3680 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3685 #define REAL_PRINT_REG(text,reg) \
3686 mono_assert (reg >= 0); \
3687 amd64_push_reg (code, AMD64_RAX); \
3688 amd64_push_reg (code, AMD64_RDX); \
3689 amd64_push_reg (code, AMD64_RCX); \
3690 amd64_push_reg (code, reg); \
3691 amd64_push_imm (code, reg); \
3692 amd64_push_imm (code, text " %d %p\n"); \
3693 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3694 amd64_call_reg (code, AMD64_RAX); \
3695 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3696 amd64_pop_reg (code, AMD64_RCX); \
3697 amd64_pop_reg (code, AMD64_RDX); \
3698 amd64_pop_reg (code, AMD64_RAX);
3700 /* benchmark and set based on cpu */
3701 #define LOOP_ALIGNMENT 8
3702 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3706 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3711 guint8 *code = cfg->native_code + cfg->code_len;
3714 /* Fix max_offset estimate for each successor bb */
3715 if (cfg->opt & MONO_OPT_BRANCH) {
3716 int current_offset = cfg->code_len;
3717 MonoBasicBlock *current_bb;
3718 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3719 current_bb->max_offset = current_offset;
3720 current_offset += current_bb->max_length;
3724 if (cfg->opt & MONO_OPT_LOOP) {
3725 int pad, align = LOOP_ALIGNMENT;
3726 /* set alignment depending on cpu */
3727 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3729 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3730 amd64_padding (code, pad);
3731 cfg->code_len += pad;
3732 bb->native_offset = cfg->code_len;
3736 #if defined(__native_client_codegen__)
3737 /* For Native Client, all indirect call/jump targets must be */
3738 /* 32-byte aligned. Exception handler blocks are jumped to */
3739 /* indirectly as well. */
3740 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3741 (bb->flags & BB_EXCEPTION_HANDLER);
3743 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3744 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3745 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3746 cfg->code_len += pad;
3747 bb->native_offset = cfg->code_len;
3749 #endif /*__native_client_codegen__*/
3751 if (cfg->verbose_level > 2)
3752 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3754 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3755 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3756 g_assert (!cfg->compile_aot);
3758 cov->data [bb->dfn].cil_code = bb->cil_code;
3759 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3760 /* this is not thread save, but good enough */
3761 amd64_inc_membase (code, AMD64_R11, 0);
3764 offset = code - cfg->native_code;
3766 mono_debug_open_block (cfg, bb, offset);
3768 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3769 x86_breakpoint (code);
3771 MONO_BB_FOR_EACH_INS (bb, ins) {
3772 offset = code - cfg->native_code;
3774 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3776 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3778 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3779 cfg->code_size *= 2;
3780 cfg->native_code = mono_realloc_native_code(cfg);
3781 code = cfg->native_code + offset;
3782 cfg->stat_code_reallocs++;
3785 if (cfg->debug_info)
3786 mono_debug_record_line_number (cfg, ins, offset);
3788 switch (ins->opcode) {
3790 amd64_mul_reg (code, ins->sreg2, TRUE);
3793 amd64_mul_reg (code, ins->sreg2, FALSE);
3795 case OP_X86_SETEQ_MEMBASE:
3796 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3798 case OP_STOREI1_MEMBASE_IMM:
3799 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3801 case OP_STOREI2_MEMBASE_IMM:
3802 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3804 case OP_STOREI4_MEMBASE_IMM:
3805 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3807 case OP_STOREI1_MEMBASE_REG:
3808 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3810 case OP_STOREI2_MEMBASE_REG:
3811 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3813 /* In AMD64 NaCl, pointers are 4 bytes, */
3814 /* so STORE_* != STOREI8_*. Likewise below. */
3815 case OP_STORE_MEMBASE_REG:
3816 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3818 case OP_STOREI8_MEMBASE_REG:
3819 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3821 case OP_STOREI4_MEMBASE_REG:
3822 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3824 case OP_STORE_MEMBASE_IMM:
3825 #ifndef __native_client_codegen__
3826 /* In NaCl, this could be a PCONST type, which could */
3827 /* mean a pointer type was copied directly into the */
3828 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3829 /* the value would be 0x00000000FFFFFFFF which is */
3830 /* not proper for an imm32 unless you cast it. */
3831 g_assert (amd64_is_imm32 (ins->inst_imm));
3833 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3835 case OP_STOREI8_MEMBASE_IMM:
3836 g_assert (amd64_is_imm32 (ins->inst_imm));
3837 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3840 #ifdef __mono_ilp32__
3841 /* In ILP32, pointers are 4 bytes, so separate these */
3842 /* cases, use literal 8 below where we really want 8 */
3843 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3844 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3848 // FIXME: Decompose this earlier
3849 if (amd64_is_imm32 (ins->inst_imm))
3850 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3852 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3853 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3857 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3858 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3861 // FIXME: Decompose this earlier
3862 if (amd64_is_imm32 (ins->inst_imm))
3863 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3865 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3866 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3870 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3871 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3874 /* For NaCl, pointers are 4 bytes, so separate these */
3875 /* cases, use literal 8 below where we really want 8 */
3876 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3877 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3879 case OP_LOAD_MEMBASE:
3880 g_assert (amd64_is_imm32 (ins->inst_offset));
3881 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3883 case OP_LOADI8_MEMBASE:
3884 /* Use literal 8 instead of sizeof pointer or */
3885 /* register, we really want 8 for this opcode */
3886 g_assert (amd64_is_imm32 (ins->inst_offset));
3887 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3889 case OP_LOADI4_MEMBASE:
3890 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3892 case OP_LOADU4_MEMBASE:
3893 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3895 case OP_LOADU1_MEMBASE:
3896 /* The cpu zero extends the result into 64 bits */
3897 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3899 case OP_LOADI1_MEMBASE:
3900 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3902 case OP_LOADU2_MEMBASE:
3903 /* The cpu zero extends the result into 64 bits */
3904 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3906 case OP_LOADI2_MEMBASE:
3907 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3909 case OP_AMD64_LOADI8_MEMINDEX:
3910 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3912 case OP_LCONV_TO_I1:
3913 case OP_ICONV_TO_I1:
3915 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3917 case OP_LCONV_TO_I2:
3918 case OP_ICONV_TO_I2:
3920 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3922 case OP_LCONV_TO_U1:
3923 case OP_ICONV_TO_U1:
3924 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3926 case OP_LCONV_TO_U2:
3927 case OP_ICONV_TO_U2:
3928 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3931 /* Clean out the upper word */
3932 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3935 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3939 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3941 case OP_COMPARE_IMM:
3942 #if defined(__mono_ilp32__)
3943 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3944 g_assert (amd64_is_imm32 (ins->inst_imm));
3945 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3948 case OP_LCOMPARE_IMM:
3949 g_assert (amd64_is_imm32 (ins->inst_imm));
3950 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3952 case OP_X86_COMPARE_REG_MEMBASE:
3953 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3955 case OP_X86_TEST_NULL:
3956 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3958 case OP_AMD64_TEST_NULL:
3959 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3962 case OP_X86_ADD_REG_MEMBASE:
3963 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3965 case OP_X86_SUB_REG_MEMBASE:
3966 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3968 case OP_X86_AND_REG_MEMBASE:
3969 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3971 case OP_X86_OR_REG_MEMBASE:
3972 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3974 case OP_X86_XOR_REG_MEMBASE:
3975 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3978 case OP_X86_ADD_MEMBASE_IMM:
3979 /* FIXME: Make a 64 version too */
3980 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3982 case OP_X86_SUB_MEMBASE_IMM:
3983 g_assert (amd64_is_imm32 (ins->inst_imm));
3984 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3986 case OP_X86_AND_MEMBASE_IMM:
3987 g_assert (amd64_is_imm32 (ins->inst_imm));
3988 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3990 case OP_X86_OR_MEMBASE_IMM:
3991 g_assert (amd64_is_imm32 (ins->inst_imm));
3992 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3994 case OP_X86_XOR_MEMBASE_IMM:
3995 g_assert (amd64_is_imm32 (ins->inst_imm));
3996 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3998 case OP_X86_ADD_MEMBASE_REG:
3999 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4001 case OP_X86_SUB_MEMBASE_REG:
4002 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4004 case OP_X86_AND_MEMBASE_REG:
4005 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4007 case OP_X86_OR_MEMBASE_REG:
4008 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4010 case OP_X86_XOR_MEMBASE_REG:
4011 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4013 case OP_X86_INC_MEMBASE:
4014 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4016 case OP_X86_INC_REG:
4017 amd64_inc_reg_size (code, ins->dreg, 4);
4019 case OP_X86_DEC_MEMBASE:
4020 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4022 case OP_X86_DEC_REG:
4023 amd64_dec_reg_size (code, ins->dreg, 4);
4025 case OP_X86_MUL_REG_MEMBASE:
4026 case OP_X86_MUL_MEMBASE_REG:
4027 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4029 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4030 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4032 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4033 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4035 case OP_AMD64_COMPARE_MEMBASE_REG:
4036 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4038 case OP_AMD64_COMPARE_MEMBASE_IMM:
4039 g_assert (amd64_is_imm32 (ins->inst_imm));
4040 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4042 case OP_X86_COMPARE_MEMBASE8_IMM:
4043 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4045 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4046 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4048 case OP_AMD64_COMPARE_REG_MEMBASE:
4049 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052 case OP_AMD64_ADD_REG_MEMBASE:
4053 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4055 case OP_AMD64_SUB_REG_MEMBASE:
4056 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4058 case OP_AMD64_AND_REG_MEMBASE:
4059 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4061 case OP_AMD64_OR_REG_MEMBASE:
4062 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4064 case OP_AMD64_XOR_REG_MEMBASE:
4065 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4068 case OP_AMD64_ADD_MEMBASE_REG:
4069 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4071 case OP_AMD64_SUB_MEMBASE_REG:
4072 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4074 case OP_AMD64_AND_MEMBASE_REG:
4075 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4077 case OP_AMD64_OR_MEMBASE_REG:
4078 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4080 case OP_AMD64_XOR_MEMBASE_REG:
4081 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4084 case OP_AMD64_ADD_MEMBASE_IMM:
4085 g_assert (amd64_is_imm32 (ins->inst_imm));
4086 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4088 case OP_AMD64_SUB_MEMBASE_IMM:
4089 g_assert (amd64_is_imm32 (ins->inst_imm));
4090 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092 case OP_AMD64_AND_MEMBASE_IMM:
4093 g_assert (amd64_is_imm32 (ins->inst_imm));
4094 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4096 case OP_AMD64_OR_MEMBASE_IMM:
4097 g_assert (amd64_is_imm32 (ins->inst_imm));
4098 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4100 case OP_AMD64_XOR_MEMBASE_IMM:
4101 g_assert (amd64_is_imm32 (ins->inst_imm));
4102 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4106 amd64_breakpoint (code);
4108 case OP_RELAXED_NOP:
4109 x86_prefix (code, X86_REP_PREFIX);
4117 case OP_DUMMY_STORE:
4118 case OP_DUMMY_ICONST:
4119 case OP_DUMMY_R8CONST:
4120 case OP_NOT_REACHED:
4123 case OP_IL_SEQ_POINT:
4124 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4126 case OP_SEQ_POINT: {
4129 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4130 if (cfg->compile_aot) {
4131 MonoInst *var = cfg->arch.ss_tramp_var;
4134 /* Load ss_tramp_var */
4135 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4136 /* Load the trampoline address */
4137 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4138 /* Call it if it is non-null */
4139 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4141 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4142 amd64_call_reg (code, AMD64_R11);
4143 amd64_patch (label, code);
4146 * Read from the single stepping trigger page. This will cause a
4147 * SIGSEGV when single stepping is enabled.
4148 * We do this _before_ the breakpoint, so single stepping after
4149 * a breakpoint is hit will step to the next IL offset.
4151 MonoInst *var = cfg->arch.ss_trigger_page_var;
4153 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4154 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4159 * This is the address which is saved in seq points,
4161 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4163 if (cfg->compile_aot) {
4164 guint32 offset = code - cfg->native_code;
4166 MonoInst *info_var = cfg->arch.seq_point_info_var;
4170 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4171 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4172 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4173 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4174 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4176 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4177 /* Call the trampoline */
4178 amd64_call_reg (code, AMD64_R11);
4179 amd64_patch (label, code);
4182 * A placeholder for a possible breakpoint inserted by
4183 * mono_arch_set_breakpoint ().
4185 for (i = 0; i < breakpoint_size; ++i)
4189 * Add an additional nop so skipping the bp doesn't cause the ip to point
4190 * to another IL offset.
4198 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4201 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4205 g_assert (amd64_is_imm32 (ins->inst_imm));
4206 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4209 g_assert (amd64_is_imm32 (ins->inst_imm));
4210 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4215 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4218 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4222 g_assert (amd64_is_imm32 (ins->inst_imm));
4223 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4226 g_assert (amd64_is_imm32 (ins->inst_imm));
4227 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4230 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4234 g_assert (amd64_is_imm32 (ins->inst_imm));
4235 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4238 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4243 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4245 switch (ins->inst_imm) {
4249 if (ins->dreg != ins->sreg1)
4250 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4251 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4254 /* LEA r1, [r2 + r2*2] */
4255 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4258 /* LEA r1, [r2 + r2*4] */
4259 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4262 /* LEA r1, [r2 + r2*2] */
4264 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4265 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4268 /* LEA r1, [r2 + r2*8] */
4269 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4272 /* LEA r1, [r2 + r2*4] */
4274 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4275 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4278 /* LEA r1, [r2 + r2*2] */
4280 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4281 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4284 /* LEA r1, [r2 + r2*4] */
4285 /* LEA r1, [r1 + r1*4] */
4286 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4287 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4290 /* LEA r1, [r2 + r2*4] */
4292 /* LEA r1, [r1 + r1*4] */
4293 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4294 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4295 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4298 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4305 #if defined( __native_client_codegen__ )
4306 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4307 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4309 /* Regalloc magic makes the div/rem cases the same */
4310 if (ins->sreg2 == AMD64_RDX) {
4311 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4313 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4316 amd64_div_reg (code, ins->sreg2, TRUE);
4321 #if defined( __native_client_codegen__ )
4322 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4323 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4325 if (ins->sreg2 == AMD64_RDX) {
4326 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4327 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4330 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4331 amd64_div_reg (code, ins->sreg2, FALSE);
4336 #if defined( __native_client_codegen__ )
4337 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4338 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4340 if (ins->sreg2 == AMD64_RDX) {
4341 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4342 amd64_cdq_size (code, 4);
4343 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4345 amd64_cdq_size (code, 4);
4346 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4351 #if defined( __native_client_codegen__ )
4352 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4353 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4355 if (ins->sreg2 == AMD64_RDX) {
4356 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4357 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4358 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4360 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4361 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4365 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4366 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4369 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4373 g_assert (amd64_is_imm32 (ins->inst_imm));
4374 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4377 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4381 g_assert (amd64_is_imm32 (ins->inst_imm));
4382 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4385 g_assert (ins->sreg2 == AMD64_RCX);
4386 amd64_shift_reg (code, X86_SHL, ins->dreg);
4389 g_assert (ins->sreg2 == AMD64_RCX);
4390 amd64_shift_reg (code, X86_SAR, ins->dreg);
4394 g_assert (amd64_is_imm32 (ins->inst_imm));
4395 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4398 g_assert (amd64_is_imm32 (ins->inst_imm));
4399 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4401 case OP_LSHR_UN_IMM:
4402 g_assert (amd64_is_imm32 (ins->inst_imm));
4403 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4406 g_assert (ins->sreg2 == AMD64_RCX);
4407 amd64_shift_reg (code, X86_SHR, ins->dreg);
4411 g_assert (amd64_is_imm32 (ins->inst_imm));
4412 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4417 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4420 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4423 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4426 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4430 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4433 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4436 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4439 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4442 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4445 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4448 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4451 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4454 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4457 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4460 amd64_neg_reg_size (code, ins->sreg1, 4);
4463 amd64_not_reg_size (code, ins->sreg1, 4);
4466 g_assert (ins->sreg2 == AMD64_RCX);
4467 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4470 g_assert (ins->sreg2 == AMD64_RCX);
4471 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4474 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4476 case OP_ISHR_UN_IMM:
4477 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4480 g_assert (ins->sreg2 == AMD64_RCX);
4481 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4484 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4487 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4490 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4491 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4493 case OP_IMUL_OVF_UN:
4494 case OP_LMUL_OVF_UN: {
4495 /* the mul operation and the exception check should most likely be split */
4496 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4497 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4498 /*g_assert (ins->sreg2 == X86_EAX);
4499 g_assert (ins->dreg == X86_EAX);*/
4500 if (ins->sreg2 == X86_EAX) {
4501 non_eax_reg = ins->sreg1;
4502 } else if (ins->sreg1 == X86_EAX) {
4503 non_eax_reg = ins->sreg2;
4505 /* no need to save since we're going to store to it anyway */
4506 if (ins->dreg != X86_EAX) {
4508 amd64_push_reg (code, X86_EAX);
4510 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4511 non_eax_reg = ins->sreg2;
4513 if (ins->dreg == X86_EDX) {
4516 amd64_push_reg (code, X86_EAX);
4520 amd64_push_reg (code, X86_EDX);
4522 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4523 /* save before the check since pop and mov don't change the flags */
4524 if (ins->dreg != X86_EAX)
4525 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4527 amd64_pop_reg (code, X86_EDX);
4529 amd64_pop_reg (code, X86_EAX);
4530 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4534 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4536 case OP_ICOMPARE_IMM:
4537 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4559 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4567 case OP_CMOV_INE_UN:
4568 case OP_CMOV_IGE_UN:
4569 case OP_CMOV_IGT_UN:
4570 case OP_CMOV_ILE_UN:
4571 case OP_CMOV_ILT_UN:
4577 case OP_CMOV_LNE_UN:
4578 case OP_CMOV_LGE_UN:
4579 case OP_CMOV_LGT_UN:
4580 case OP_CMOV_LLE_UN:
4581 case OP_CMOV_LLT_UN:
4582 g_assert (ins->dreg == ins->sreg1);
4583 /* This needs to operate on 64 bit values */
4584 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4588 amd64_not_reg (code, ins->sreg1);
4591 amd64_neg_reg (code, ins->sreg1);
4596 if ((((guint64)ins->inst_c0) >> 32) == 0)
4597 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4599 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4602 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4603 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4606 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4607 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4610 if (ins->dreg != ins->sreg1)
4611 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4613 case OP_AMD64_SET_XMMREG_R4: {
4615 if (ins->dreg != ins->sreg1)
4616 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4618 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4622 case OP_AMD64_SET_XMMREG_R8: {
4623 if (ins->dreg != ins->sreg1)
4624 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4628 MonoCallInst *call = (MonoCallInst*)ins;
4629 int i, save_area_offset;
4631 g_assert (!cfg->method->save_lmf);
4633 /* Restore callee saved registers */
4634 save_area_offset = cfg->arch.reg_save_area_offset;
4635 for (i = 0; i < AMD64_NREG; ++i)
4636 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4637 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4638 save_area_offset += 8;
4641 if (cfg->arch.omit_fp) {
4642 if (cfg->arch.stack_alloc_size)
4643 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4645 if (call->stack_usage)
4648 /* Copy arguments on the stack to our argument area */
4649 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4650 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4651 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4657 offset = code - cfg->native_code;
4658 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4659 if (cfg->compile_aot)
4660 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4662 amd64_set_reg_template (code, AMD64_R11);
4663 amd64_jump_reg (code, AMD64_R11);
4664 ins->flags |= MONO_INST_GC_CALLSITE;
4665 ins->backend.pc_offset = code - cfg->native_code;
4669 /* ensure ins->sreg1 is not NULL */
4670 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4673 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4674 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4684 call = (MonoCallInst*)ins;
4686 * The AMD64 ABI forces callers to know about varargs.
4688 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4689 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4690 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4692 * Since the unmanaged calling convention doesn't contain a
4693 * 'vararg' entry, we have to treat every pinvoke call as a
4694 * potential vararg call.
4698 for (i = 0; i < AMD64_XMM_NREG; ++i)
4699 if (call->used_fregs & (1 << i))
4702 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4704 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4707 if (ins->flags & MONO_INST_HAS_METHOD)
4708 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4710 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4711 ins->flags |= MONO_INST_GC_CALLSITE;
4712 ins->backend.pc_offset = code - cfg->native_code;
4713 code = emit_move_return_value (cfg, ins, code);
4720 case OP_VOIDCALL_REG:
4722 call = (MonoCallInst*)ins;
4724 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4725 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4726 ins->sreg1 = AMD64_R11;
4730 * The AMD64 ABI forces callers to know about varargs.
4732 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4733 if (ins->sreg1 == AMD64_RAX) {
4734 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4735 ins->sreg1 = AMD64_R11;
4737 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4738 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4740 * Since the unmanaged calling convention doesn't contain a
4741 * 'vararg' entry, we have to treat every pinvoke call as a
4742 * potential vararg call.
4746 for (i = 0; i < AMD64_XMM_NREG; ++i)
4747 if (call->used_fregs & (1 << i))
4749 if (ins->sreg1 == AMD64_RAX) {
4750 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4751 ins->sreg1 = AMD64_R11;
4754 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4756 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4759 amd64_call_reg (code, ins->sreg1);
4760 ins->flags |= MONO_INST_GC_CALLSITE;
4761 ins->backend.pc_offset = code - cfg->native_code;
4762 code = emit_move_return_value (cfg, ins, code);
4764 case OP_FCALL_MEMBASE:
4765 case OP_RCALL_MEMBASE:
4766 case OP_LCALL_MEMBASE:
4767 case OP_VCALL_MEMBASE:
4768 case OP_VCALL2_MEMBASE:
4769 case OP_VOIDCALL_MEMBASE:
4770 case OP_CALL_MEMBASE:
4771 call = (MonoCallInst*)ins;
4773 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4774 ins->flags |= MONO_INST_GC_CALLSITE;
4775 ins->backend.pc_offset = code - cfg->native_code;
4776 code = emit_move_return_value (cfg, ins, code);
4780 MonoInst *var = cfg->dyn_call_var;
4782 g_assert (var->opcode == OP_REGOFFSET);
4784 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4785 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4787 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4789 /* Save args buffer */
4790 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4792 /* Set argument registers */
4793 for (i = 0; i < PARAM_REGS; ++i)
4794 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4797 amd64_call_reg (code, AMD64_R10);
4799 ins->flags |= MONO_INST_GC_CALLSITE;
4800 ins->backend.pc_offset = code - cfg->native_code;
4803 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4804 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4807 case OP_AMD64_SAVE_SP_TO_LMF: {
4808 MonoInst *lmf_var = cfg->lmf_var;
4809 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4813 g_assert_not_reached ();
4814 amd64_push_reg (code, ins->sreg1);
4816 case OP_X86_PUSH_IMM:
4817 g_assert_not_reached ();
4818 g_assert (amd64_is_imm32 (ins->inst_imm));
4819 amd64_push_imm (code, ins->inst_imm);
4821 case OP_X86_PUSH_MEMBASE:
4822 g_assert_not_reached ();
4823 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4825 case OP_X86_PUSH_OBJ: {
4826 int size = ALIGN_TO (ins->inst_imm, 8);
4828 g_assert_not_reached ();
4830 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4831 amd64_push_reg (code, AMD64_RDI);
4832 amd64_push_reg (code, AMD64_RSI);
4833 amd64_push_reg (code, AMD64_RCX);
4834 if (ins->inst_offset)
4835 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4837 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4838 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4839 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4841 amd64_prefix (code, X86_REP_PREFIX);
4843 amd64_pop_reg (code, AMD64_RCX);
4844 amd64_pop_reg (code, AMD64_RSI);
4845 amd64_pop_reg (code, AMD64_RDI);
4848 case OP_GENERIC_CLASS_INIT: {
4849 static int byte_offset = -1;
4850 static guint8 bitmask;
4853 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4855 if (byte_offset < 0)
4856 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4858 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4860 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4862 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4863 ins->flags |= MONO_INST_GC_CALLSITE;
4864 ins->backend.pc_offset = code - cfg->native_code;
4866 x86_patch (jump, code);
4871 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4873 case OP_X86_LEA_MEMBASE:
4874 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4877 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4880 /* keep alignment */
4881 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4882 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4883 code = mono_emit_stack_alloc (cfg, code, ins);
4884 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4885 if (cfg->param_area)
4886 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4888 case OP_LOCALLOC_IMM: {
4889 guint32 size = ins->inst_imm;
4890 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4892 if (ins->flags & MONO_INST_INIT) {
4896 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4897 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4899 for (i = 0; i < size; i += 8)
4900 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4901 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4903 amd64_mov_reg_imm (code, ins->dreg, size);
4904 ins->sreg1 = ins->dreg;
4906 code = mono_emit_stack_alloc (cfg, code, ins);
4907 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4910 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4911 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4913 if (cfg->param_area)
4914 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4918 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4919 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4920 (gpointer)"mono_arch_throw_exception", FALSE);
4921 ins->flags |= MONO_INST_GC_CALLSITE;
4922 ins->backend.pc_offset = code - cfg->native_code;
4926 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4927 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4928 (gpointer)"mono_arch_rethrow_exception", FALSE);
4929 ins->flags |= MONO_INST_GC_CALLSITE;
4930 ins->backend.pc_offset = code - cfg->native_code;
4933 case OP_CALL_HANDLER:
4935 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4936 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4937 amd64_call_imm (code, 0);
4938 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4939 /* Restore stack alignment */
4940 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4942 case OP_START_HANDLER: {
4943 /* Even though we're saving RSP, use sizeof */
4944 /* gpointer because spvar is of type IntPtr */
4945 /* see: mono_create_spvar_for_region */
4946 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4947 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4949 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4950 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4952 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4956 case OP_ENDFINALLY: {
4957 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4958 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4962 case OP_ENDFILTER: {
4963 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4964 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4965 /* The local allocator will put the result into RAX */
4970 if (ins->dreg != AMD64_RAX)
4971 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4974 ins->inst_c0 = code - cfg->native_code;
4977 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4978 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4980 if (ins->inst_target_bb->native_offset) {
4981 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4983 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4984 if ((cfg->opt & MONO_OPT_BRANCH) &&
4985 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4986 x86_jump8 (code, 0);
4988 x86_jump32 (code, 0);
4992 amd64_jump_reg (code, ins->sreg1);
5015 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5016 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5018 case OP_COND_EXC_EQ:
5019 case OP_COND_EXC_NE_UN:
5020 case OP_COND_EXC_LT:
5021 case OP_COND_EXC_LT_UN:
5022 case OP_COND_EXC_GT:
5023 case OP_COND_EXC_GT_UN:
5024 case OP_COND_EXC_GE:
5025 case OP_COND_EXC_GE_UN:
5026 case OP_COND_EXC_LE:
5027 case OP_COND_EXC_LE_UN:
5028 case OP_COND_EXC_IEQ:
5029 case OP_COND_EXC_INE_UN:
5030 case OP_COND_EXC_ILT:
5031 case OP_COND_EXC_ILT_UN:
5032 case OP_COND_EXC_IGT:
5033 case OP_COND_EXC_IGT_UN:
5034 case OP_COND_EXC_IGE:
5035 case OP_COND_EXC_IGE_UN:
5036 case OP_COND_EXC_ILE:
5037 case OP_COND_EXC_ILE_UN:
5038 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5040 case OP_COND_EXC_OV:
5041 case OP_COND_EXC_NO:
5043 case OP_COND_EXC_NC:
5044 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5045 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5047 case OP_COND_EXC_IOV:
5048 case OP_COND_EXC_INO:
5049 case OP_COND_EXC_IC:
5050 case OP_COND_EXC_INC:
5051 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5052 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5055 /* floating point opcodes */
5057 double d = *(double *)ins->inst_p0;
5059 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5060 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5063 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5064 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5069 float f = *(float *)ins->inst_p0;
5071 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5073 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5075 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5078 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5079 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5081 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5085 case OP_STORER8_MEMBASE_REG:
5086 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5088 case OP_LOADR8_MEMBASE:
5089 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5091 case OP_STORER4_MEMBASE_REG:
5093 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5095 /* This requires a double->single conversion */
5096 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5097 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5100 case OP_LOADR4_MEMBASE:
5102 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5104 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5105 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5108 case OP_ICONV_TO_R4:
5110 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5112 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5116 case OP_ICONV_TO_R8:
5117 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5119 case OP_LCONV_TO_R4:
5121 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5123 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5124 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5127 case OP_LCONV_TO_R8:
5128 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5130 case OP_FCONV_TO_R4:
5132 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5134 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5135 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5138 case OP_FCONV_TO_I1:
5139 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5141 case OP_FCONV_TO_U1:
5142 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5144 case OP_FCONV_TO_I2:
5145 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5147 case OP_FCONV_TO_U2:
5148 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5150 case OP_FCONV_TO_U4:
5151 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5153 case OP_FCONV_TO_I4:
5155 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5157 case OP_FCONV_TO_I8:
5158 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5161 case OP_RCONV_TO_I1:
5162 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5163 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5165 case OP_RCONV_TO_U1:
5166 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5167 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5169 case OP_RCONV_TO_I2:
5170 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5171 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5173 case OP_RCONV_TO_U2:
5174 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5175 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5177 case OP_RCONV_TO_I4:
5178 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5180 case OP_RCONV_TO_U4:
5181 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5183 case OP_RCONV_TO_I8:
5184 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5186 case OP_RCONV_TO_R8:
5187 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5189 case OP_RCONV_TO_R4:
5190 if (ins->dreg != ins->sreg1)
5191 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5194 case OP_LCONV_TO_R_UN: {
5197 /* Based on gcc code */
5198 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5199 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5202 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5203 br [1] = code; x86_jump8 (code, 0);
5204 amd64_patch (br [0], code);
5207 /* Save to the red zone */
5208 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5209 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5210 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5211 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5212 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5213 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5214 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5215 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5216 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5218 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5219 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5220 amd64_patch (br [1], code);
5223 case OP_LCONV_TO_OVF_U4:
5224 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5225 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5226 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5228 case OP_LCONV_TO_OVF_I4_UN:
5229 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5230 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5231 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5234 if (ins->dreg != ins->sreg1)
5235 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5238 if (ins->dreg != ins->sreg1)
5239 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5241 case OP_MOVE_F_TO_I4:
5243 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5245 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5246 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5249 case OP_MOVE_I4_TO_F:
5250 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5252 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5254 case OP_MOVE_F_TO_I8:
5255 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5257 case OP_MOVE_I8_TO_F:
5258 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5261 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5264 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5267 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5270 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5273 static double r8_0 = -0.0;
5275 g_assert (ins->sreg1 == ins->dreg);
5277 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5278 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5282 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5285 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5288 static guint64 d = 0x7fffffffffffffffUL;
5290 g_assert (ins->sreg1 == ins->dreg);
5292 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5293 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5297 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5301 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5304 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5307 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5310 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5313 static float r4_0 = -0.0;
5315 g_assert (ins->sreg1 == ins->dreg);
5317 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5318 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5319 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5324 g_assert (cfg->opt & MONO_OPT_CMOV);
5325 g_assert (ins->dreg == ins->sreg1);
5326 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5327 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5330 g_assert (cfg->opt & MONO_OPT_CMOV);
5331 g_assert (ins->dreg == ins->sreg1);
5332 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5333 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5336 g_assert (cfg->opt & MONO_OPT_CMOV);
5337 g_assert (ins->dreg == ins->sreg1);
5338 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5339 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5342 g_assert (cfg->opt & MONO_OPT_CMOV);
5343 g_assert (ins->dreg == ins->sreg1);
5344 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5345 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5348 g_assert (cfg->opt & MONO_OPT_CMOV);
5349 g_assert (ins->dreg == ins->sreg1);
5350 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5351 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5354 g_assert (cfg->opt & MONO_OPT_CMOV);
5355 g_assert (ins->dreg == ins->sreg1);
5356 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5357 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5360 g_assert (cfg->opt & MONO_OPT_CMOV);
5361 g_assert (ins->dreg == ins->sreg1);
5362 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5363 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5366 g_assert (cfg->opt & MONO_OPT_CMOV);
5367 g_assert (ins->dreg == ins->sreg1);
5368 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5369 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5375 * The two arguments are swapped because the fbranch instructions
5376 * depend on this for the non-sse case to work.
5378 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5382 * FIXME: Get rid of this.
5383 * The two arguments are swapped because the fbranch instructions
5384 * depend on this for the non-sse case to work.
5386 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5390 /* zeroing the register at the start results in
5391 * shorter and faster code (we can also remove the widening op)
5393 guchar *unordered_check;
5395 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5396 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5397 unordered_check = code;
5398 x86_branch8 (code, X86_CC_P, 0, FALSE);
5400 if (ins->opcode == OP_FCEQ) {
5401 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5402 amd64_patch (unordered_check, code);
5404 guchar *jump_to_end;
5405 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5407 x86_jump8 (code, 0);
5408 amd64_patch (unordered_check, code);
5409 amd64_inc_reg (code, ins->dreg);
5410 amd64_patch (jump_to_end, code);
5416 /* zeroing the register at the start results in
5417 * shorter and faster code (we can also remove the widening op)
5419 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5420 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5421 if (ins->opcode == OP_FCLT_UN) {
5422 guchar *unordered_check = code;
5423 guchar *jump_to_end;
5424 x86_branch8 (code, X86_CC_P, 0, FALSE);
5425 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5427 x86_jump8 (code, 0);
5428 amd64_patch (unordered_check, code);
5429 amd64_inc_reg (code, ins->dreg);
5430 amd64_patch (jump_to_end, code);
5432 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5437 guchar *unordered_check;
5438 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5439 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5440 unordered_check = code;
5441 x86_branch8 (code, X86_CC_P, 0, FALSE);
5442 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5443 amd64_patch (unordered_check, code);
5448 /* zeroing the register at the start results in
5449 * shorter and faster code (we can also remove the widening op)
5451 guchar *unordered_check;
5453 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5454 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5455 if (ins->opcode == OP_FCGT) {
5456 unordered_check = code;
5457 x86_branch8 (code, X86_CC_P, 0, FALSE);
5458 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5459 amd64_patch (unordered_check, code);
5461 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5466 guchar *unordered_check;
5467 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5468 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5469 unordered_check = code;
5470 x86_branch8 (code, X86_CC_P, 0, FALSE);
5471 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5472 amd64_patch (unordered_check, code);
5482 gboolean unordered = FALSE;
5484 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5485 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5487 switch (ins->opcode) {
5489 x86_cond = X86_CC_EQ;
5492 x86_cond = X86_CC_LT;
5495 x86_cond = X86_CC_GT;
5498 x86_cond = X86_CC_GT;
5502 x86_cond = X86_CC_LT;
5506 g_assert_not_reached ();
5511 guchar *unordered_check;
5512 guchar *jump_to_end;
5514 unordered_check = code;
5515 x86_branch8 (code, X86_CC_P, 0, FALSE);
5516 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5518 x86_jump8 (code, 0);
5519 amd64_patch (unordered_check, code);
5520 amd64_inc_reg (code, ins->dreg);
5521 amd64_patch (jump_to_end, code);
5523 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5527 case OP_FCLT_MEMBASE:
5528 case OP_FCGT_MEMBASE:
5529 case OP_FCLT_UN_MEMBASE:
5530 case OP_FCGT_UN_MEMBASE:
5531 case OP_FCEQ_MEMBASE: {
5532 guchar *unordered_check, *jump_to_end;
5535 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5536 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5538 switch (ins->opcode) {
5539 case OP_FCEQ_MEMBASE:
5540 x86_cond = X86_CC_EQ;
5542 case OP_FCLT_MEMBASE:
5543 case OP_FCLT_UN_MEMBASE:
5544 x86_cond = X86_CC_LT;
5546 case OP_FCGT_MEMBASE:
5547 case OP_FCGT_UN_MEMBASE:
5548 x86_cond = X86_CC_GT;
5551 g_assert_not_reached ();
5554 unordered_check = code;
5555 x86_branch8 (code, X86_CC_P, 0, FALSE);
5556 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5558 switch (ins->opcode) {
5559 case OP_FCEQ_MEMBASE:
5560 case OP_FCLT_MEMBASE:
5561 case OP_FCGT_MEMBASE:
5562 amd64_patch (unordered_check, code);
5564 case OP_FCLT_UN_MEMBASE:
5565 case OP_FCGT_UN_MEMBASE:
5567 x86_jump8 (code, 0);
5568 amd64_patch (unordered_check, code);
5569 amd64_inc_reg (code, ins->dreg);
5570 amd64_patch (jump_to_end, code);
5578 guchar *jump = code;
5579 x86_branch8 (code, X86_CC_P, 0, TRUE);
5580 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5581 amd64_patch (jump, code);
5585 /* Branch if C013 != 100 */
5586 /* branch if !ZF or (PF|CF) */
5587 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5588 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5589 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5592 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5595 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5596 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5600 if (ins->opcode == OP_FBGT) {
5603 /* skip branch if C1=1 */
5605 x86_branch8 (code, X86_CC_P, 0, FALSE);
5606 /* branch if (C0 | C3) = 1 */
5607 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5608 amd64_patch (br1, code);
5611 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5615 /* Branch if C013 == 100 or 001 */
5618 /* skip branch if C1=1 */
5620 x86_branch8 (code, X86_CC_P, 0, FALSE);
5621 /* branch if (C0 | C3) = 1 */
5622 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5623 amd64_patch (br1, code);
5627 /* Branch if C013 == 000 */
5628 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5631 /* Branch if C013=000 or 100 */
5634 /* skip branch if C1=1 */
5636 x86_branch8 (code, X86_CC_P, 0, FALSE);
5637 /* branch if C0=0 */
5638 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5639 amd64_patch (br1, code);
5643 /* Branch if C013 != 001 */
5644 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5645 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5648 /* Transfer value to the fp stack */
5649 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5650 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5651 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5653 amd64_push_reg (code, AMD64_RAX);
5655 amd64_fnstsw (code);
5656 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5657 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5658 amd64_pop_reg (code, AMD64_RAX);
5659 amd64_fstp (code, 0);
5660 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5661 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5664 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5667 case OP_TLS_GET_REG:
5668 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5671 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5674 case OP_TLS_SET_REG: {
5675 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5678 case OP_MEMORY_BARRIER: {
5679 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5683 case OP_ATOMIC_ADD_I4:
5684 case OP_ATOMIC_ADD_I8: {
5685 int dreg = ins->dreg;
5686 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5688 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5691 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5692 amd64_prefix (code, X86_LOCK_PREFIX);
5693 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5694 /* dreg contains the old value, add with sreg2 value */
5695 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5697 if (ins->dreg != dreg)
5698 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5702 case OP_ATOMIC_EXCHANGE_I4:
5703 case OP_ATOMIC_EXCHANGE_I8: {
5704 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5706 /* LOCK prefix is implied. */
5707 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5708 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5709 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5712 case OP_ATOMIC_CAS_I4:
5713 case OP_ATOMIC_CAS_I8: {
5716 if (ins->opcode == OP_ATOMIC_CAS_I8)
5722 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5723 * an explanation of how this works.
5725 g_assert (ins->sreg3 == AMD64_RAX);
5726 g_assert (ins->sreg1 != AMD64_RAX);
5727 g_assert (ins->sreg1 != ins->sreg2);
5729 amd64_prefix (code, X86_LOCK_PREFIX);
5730 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5732 if (ins->dreg != AMD64_RAX)
5733 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5736 case OP_ATOMIC_LOAD_I1: {
5737 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5740 case OP_ATOMIC_LOAD_U1: {
5741 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5744 case OP_ATOMIC_LOAD_I2: {
5745 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5748 case OP_ATOMIC_LOAD_U2: {
5749 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5752 case OP_ATOMIC_LOAD_I4: {
5753 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5756 case OP_ATOMIC_LOAD_U4:
5757 case OP_ATOMIC_LOAD_I8:
5758 case OP_ATOMIC_LOAD_U8: {
5759 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5762 case OP_ATOMIC_LOAD_R4: {
5763 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5764 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5767 case OP_ATOMIC_LOAD_R8: {
5768 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5771 case OP_ATOMIC_STORE_I1:
5772 case OP_ATOMIC_STORE_U1:
5773 case OP_ATOMIC_STORE_I2:
5774 case OP_ATOMIC_STORE_U2:
5775 case OP_ATOMIC_STORE_I4:
5776 case OP_ATOMIC_STORE_U4:
5777 case OP_ATOMIC_STORE_I8:
5778 case OP_ATOMIC_STORE_U8: {
5781 switch (ins->opcode) {
5782 case OP_ATOMIC_STORE_I1:
5783 case OP_ATOMIC_STORE_U1:
5786 case OP_ATOMIC_STORE_I2:
5787 case OP_ATOMIC_STORE_U2:
5790 case OP_ATOMIC_STORE_I4:
5791 case OP_ATOMIC_STORE_U4:
5794 case OP_ATOMIC_STORE_I8:
5795 case OP_ATOMIC_STORE_U8:
5800 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5802 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5806 case OP_ATOMIC_STORE_R4: {
5807 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5808 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5810 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5814 case OP_ATOMIC_STORE_R8: {
5817 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5821 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5825 case OP_CARD_TABLE_WBARRIER: {
5826 int ptr = ins->sreg1;
5827 int value = ins->sreg2;
5829 int nursery_shift, card_table_shift;
5830 gpointer card_table_mask;
5831 size_t nursery_size;
5833 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5834 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5835 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5837 /*If either point to the stack we can simply avoid the WB. This happens due to
5838 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5840 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5844 * We need one register we can clobber, we choose EDX and make sreg1
5845 * fixed EAX to work around limitations in the local register allocator.
5846 * sreg2 might get allocated to EDX, but that is not a problem since
5847 * we use it before clobbering EDX.
5849 g_assert (ins->sreg1 == AMD64_RAX);
5852 * This is the code we produce:
5855 * edx >>= nursery_shift
5856 * cmp edx, (nursery_start >> nursery_shift)
5859 * edx >>= card_table_shift
5865 if (mono_gc_card_table_nursery_check ()) {
5866 if (value != AMD64_RDX)
5867 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5868 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5869 if (shifted_nursery_start >> 31) {
5871 * The value we need to compare against is 64 bits, so we need
5872 * another spare register. We use RBX, which we save and
5875 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5876 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5877 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5878 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5880 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5882 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5884 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5885 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5886 if (card_table_mask)
5887 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5889 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5890 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5892 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5894 if (mono_gc_card_table_nursery_check ())
5895 x86_patch (br, code);
5898 #ifdef MONO_ARCH_SIMD_INTRINSICS
5899 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5901 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5904 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5907 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5910 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5913 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5916 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5919 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5920 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5923 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5929 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5932 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5935 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5938 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5941 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5944 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5947 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5956 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5959 case OP_PSHUFLEW_HIGH:
5960 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5961 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5963 case OP_PSHUFLEW_LOW:
5964 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5965 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5968 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5969 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5972 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5973 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5976 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5977 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5981 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5987 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5993 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6000 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6003 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6018 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6027 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6030 case OP_EXTRACT_MASK:
6031 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6035 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6038 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6048 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6051 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6054 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6064 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6067 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6071 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6074 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6077 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6081 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6084 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6087 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6098 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6101 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6104 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6108 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6111 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6114 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6118 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6121 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6124 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6127 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6131 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6134 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6137 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6140 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6143 case OP_PSUM_ABS_DIFF:
6144 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6147 case OP_UNPACK_LOWB:
6148 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6150 case OP_UNPACK_LOWW:
6151 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6153 case OP_UNPACK_LOWD:
6154 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6156 case OP_UNPACK_LOWQ:
6157 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6159 case OP_UNPACK_LOWPS:
6160 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6162 case OP_UNPACK_LOWPD:
6163 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6166 case OP_UNPACK_HIGHB:
6167 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6169 case OP_UNPACK_HIGHW:
6170 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6172 case OP_UNPACK_HIGHD:
6173 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6175 case OP_UNPACK_HIGHQ:
6176 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6178 case OP_UNPACK_HIGHPS:
6179 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6181 case OP_UNPACK_HIGHPD:
6182 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6192 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6195 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6198 case OP_PADDB_SAT_UN:
6199 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6201 case OP_PSUBB_SAT_UN:
6202 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6204 case OP_PADDW_SAT_UN:
6205 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6207 case OP_PSUBW_SAT_UN:
6208 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6212 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6215 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6218 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6221 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6225 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6228 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6231 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6233 case OP_PMULW_HIGH_UN:
6234 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6237 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6241 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6244 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6248 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6251 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6255 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6258 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6262 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6265 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6269 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6272 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6276 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6279 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6283 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6286 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6289 /*TODO: This is appart of the sse spec but not added
6291 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6294 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6299 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6302 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6305 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6308 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6311 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6314 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6317 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6320 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6323 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6326 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6330 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6333 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6337 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6338 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6340 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6345 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6347 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6348 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6352 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6354 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6355 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6356 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6360 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6362 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6365 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6367 case OP_EXTRACTX_U2:
6368 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6370 case OP_INSERTX_U1_SLOW:
6371 /*sreg1 is the extracted ireg (scratch)
6372 /sreg2 is the to be inserted ireg (scratch)
6373 /dreg is the xreg to receive the value*/
6375 /*clear the bits from the extracted word*/
6376 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6377 /*shift the value to insert if needed*/
6378 if (ins->inst_c0 & 1)
6379 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6380 /*join them together*/
6381 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6382 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6384 case OP_INSERTX_I4_SLOW:
6385 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6386 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6387 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6389 case OP_INSERTX_I8_SLOW:
6390 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6392 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6394 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6397 case OP_INSERTX_R4_SLOW:
6398 switch (ins->inst_c0) {
6401 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6403 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6408 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6410 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6411 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6414 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6416 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6418 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6419 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6422 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6424 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6426 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6427 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6431 case OP_INSERTX_R8_SLOW:
6433 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6435 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6437 case OP_STOREX_MEMBASE_REG:
6438 case OP_STOREX_MEMBASE:
6439 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6441 case OP_LOADX_MEMBASE:
6442 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6444 case OP_LOADX_ALIGNED_MEMBASE:
6445 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6447 case OP_STOREX_ALIGNED_MEMBASE_REG:
6448 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6450 case OP_STOREX_NTA_MEMBASE_REG:
6451 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6453 case OP_PREFETCH_MEMBASE:
6454 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6458 /*FIXME the peephole pass should have killed this*/
6459 if (ins->dreg != ins->sreg1)
6460 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6463 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6465 case OP_ICONV_TO_R4_RAW:
6466 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6469 case OP_FCONV_TO_R8_X:
6470 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6473 case OP_XCONV_R8_TO_I4:
6474 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6475 switch (ins->backend.source_opcode) {
6476 case OP_FCONV_TO_I1:
6477 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6479 case OP_FCONV_TO_U1:
6480 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6482 case OP_FCONV_TO_I2:
6483 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6485 case OP_FCONV_TO_U2:
6486 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6492 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6493 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6494 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6497 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6498 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6501 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6502 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6506 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6508 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6509 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6511 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6514 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6515 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6518 case OP_LIVERANGE_START: {
6519 if (cfg->verbose_level > 1)
6520 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6521 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6524 case OP_LIVERANGE_END: {
6525 if (cfg->verbose_level > 1)
6526 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6527 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6530 case OP_GC_SAFE_POINT: {
6531 const char *polling_func = NULL;
6532 int compare_val = 0;
6535 #if defined (USE_COOP_GC)
6536 polling_func = "mono_threads_state_poll";
6538 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6539 polling_func = "mono_nacl_gc";
6540 compare_val = 0xFFFFFFFF;
6545 amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6546 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6547 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6548 amd64_patch (br[0], code);
6552 case OP_GC_LIVENESS_DEF:
6553 case OP_GC_LIVENESS_USE:
6554 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6555 ins->backend.pc_offset = code - cfg->native_code;
6557 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6558 ins->backend.pc_offset = code - cfg->native_code;
6559 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6562 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6563 g_assert_not_reached ();
6566 if ((code - cfg->native_code - offset) > max_len) {
6567 #if !defined(__native_client_codegen__)
6568 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6569 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6570 g_assert_not_reached ();
6575 cfg->code_len = code - cfg->native_code;
6578 #endif /* DISABLE_JIT */
6581 mono_arch_register_lowlevel_calls (void)
6583 /* The signature doesn't matter */
6584 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6588 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6590 unsigned char *ip = ji->ip.i + code;
6593 * Debug code to help track down problems where the target of a near call is
6596 if (amd64_is_near_call (ip)) {
6597 gint64 disp = (guint8*)target - (guint8*)ip;
6599 if (!amd64_is_imm32 (disp)) {
6600 printf ("TYPE: %d\n", ji->type);
6602 case MONO_PATCH_INFO_INTERNAL_METHOD:
6603 printf ("V: %s\n", ji->data.name);
6605 case MONO_PATCH_INFO_METHOD_JUMP:
6606 case MONO_PATCH_INFO_METHOD:
6607 printf ("V: %s\n", ji->data.method->name);
6615 amd64_patch (ip, (gpointer)target);
6621 get_max_epilog_size (MonoCompile *cfg)
6623 int max_epilog_size = 16;
6625 if (cfg->method->save_lmf)
6626 max_epilog_size += 256;
6628 if (mono_jit_trace_calls != NULL)
6629 max_epilog_size += 50;
6631 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6632 max_epilog_size += 50;
6634 max_epilog_size += (AMD64_NREG * 2);
6636 return max_epilog_size;
6640 * This macro is used for testing whenever the unwinder works correctly at every point
6641 * where an async exception can happen.
6643 /* This will generate a SIGSEGV at the given point in the code */
6644 #define async_exc_point(code) do { \
6645 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6646 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6647 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6648 cfg->arch.async_point_count ++; \
6653 mono_arch_emit_prolog (MonoCompile *cfg)
6655 MonoMethod *method = cfg->method;
6657 MonoMethodSignature *sig;
6659 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6662 MonoInst *lmf_var = cfg->lmf_var;
6663 gboolean args_clobbered = FALSE;
6664 gboolean trace = FALSE;
6665 #ifdef __native_client_codegen__
6666 guint alignment_check;
6669 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6671 #if defined(__default_codegen__)
6672 code = cfg->native_code = g_malloc (cfg->code_size);
6673 #elif defined(__native_client_codegen__)
6674 /* native_code_alloc is not 32-byte aligned, native_code is. */
6675 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6677 /* Align native_code to next nearest kNaclAlignment byte. */
6678 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6679 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6681 code = cfg->native_code;
6683 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6684 g_assert (alignment_check == 0);
6687 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6690 /* Amount of stack space allocated by register saving code */
6693 /* Offset between RSP and the CFA */
6697 * The prolog consists of the following parts:
6699 * - push rbp, mov rbp, rsp
6700 * - save callee saved regs using pushes
6702 * - save rgctx if needed
6703 * - save lmf if needed
6706 * - save rgctx if needed
6707 * - save lmf if needed
6708 * - save callee saved regs using moves
6713 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6714 // IP saved at CFA - 8
6715 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6716 async_exc_point (code);
6717 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6719 if (!cfg->arch.omit_fp) {
6720 amd64_push_reg (code, AMD64_RBP);
6722 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6723 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6724 async_exc_point (code);
6726 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6728 /* These are handled automatically by the stack marking code */
6729 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6731 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6732 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6733 async_exc_point (code);
6735 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6739 /* The param area is always at offset 0 from sp */
6740 /* This needs to be allocated here, since it has to come after the spill area */
6741 if (cfg->param_area) {
6742 if (cfg->arch.omit_fp)
6744 g_assert_not_reached ();
6745 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6748 if (cfg->arch.omit_fp) {
6750 * On enter, the stack is misaligned by the pushing of the return
6751 * address. It is either made aligned by the pushing of %rbp, or by
6754 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6755 if ((alloc_size % 16) == 0) {
6757 /* Mark the padding slot as NOREF */
6758 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6761 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6762 if (cfg->stack_offset != alloc_size) {
6763 /* Mark the padding slot as NOREF */
6764 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6766 cfg->arch.sp_fp_offset = alloc_size;
6770 cfg->arch.stack_alloc_size = alloc_size;
6772 /* Allocate stack frame */
6774 /* See mono_emit_stack_alloc */
6775 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6776 guint32 remaining_size = alloc_size;
6777 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6778 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6779 guint32 offset = code - cfg->native_code;
6780 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6781 while (required_code_size >= (cfg->code_size - offset))
6782 cfg->code_size *= 2;
6783 cfg->native_code = mono_realloc_native_code (cfg);
6784 code = cfg->native_code + offset;
6785 cfg->stat_code_reallocs++;
6788 while (remaining_size >= 0x1000) {
6789 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6790 if (cfg->arch.omit_fp) {
6791 cfa_offset += 0x1000;
6792 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6794 async_exc_point (code);
6796 if (cfg->arch.omit_fp)
6797 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6800 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6801 remaining_size -= 0x1000;
6803 if (remaining_size) {
6804 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6805 if (cfg->arch.omit_fp) {
6806 cfa_offset += remaining_size;
6807 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6808 async_exc_point (code);
6811 if (cfg->arch.omit_fp)
6812 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6816 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6817 if (cfg->arch.omit_fp) {
6818 cfa_offset += alloc_size;
6819 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6820 async_exc_point (code);
6825 /* Stack alignment check */
6828 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6829 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6830 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6831 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6832 amd64_breakpoint (code);
6836 if (mini_get_debug_options ()->init_stacks) {
6837 /* Fill the stack frame with a dummy value to force deterministic behavior */
6839 /* Save registers to the red zone */
6840 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6841 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6843 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6844 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6845 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6848 #if defined(__default_codegen__)
6849 amd64_prefix (code, X86_REP_PREFIX);
6851 #elif defined(__native_client_codegen__)
6852 /* NaCl stos pseudo-instruction */
6853 amd64_codegen_pre (code);
6854 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6855 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6856 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6857 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6858 amd64_prefix (code, X86_REP_PREFIX);
6860 amd64_codegen_post (code);
6861 #endif /* __native_client_codegen__ */
6863 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6864 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6868 if (method->save_lmf)
6869 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6871 /* Save callee saved registers */
6872 if (cfg->arch.omit_fp) {
6873 save_area_offset = cfg->arch.reg_save_area_offset;
6874 /* Save caller saved registers after sp is adjusted */
6875 /* The registers are saved at the bottom of the frame */
6876 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6878 /* The registers are saved just below the saved rbp */
6879 save_area_offset = cfg->arch.reg_save_area_offset;
6882 for (i = 0; i < AMD64_NREG; ++i) {
6883 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6884 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6886 if (cfg->arch.omit_fp) {
6887 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6888 /* These are handled automatically by the stack marking code */
6889 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6891 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6895 save_area_offset += 8;
6896 async_exc_point (code);
6900 /* store runtime generic context */
6901 if (cfg->rgctx_var) {
6902 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6903 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6905 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6907 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6908 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6911 /* compute max_length in order to use short forward jumps */
6912 max_epilog_size = get_max_epilog_size (cfg);
6913 if (cfg->opt & MONO_OPT_BRANCH) {
6914 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6918 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6920 /* max alignment for loops */
6921 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6922 max_length += LOOP_ALIGNMENT;
6923 #ifdef __native_client_codegen__
6924 /* max alignment for native client */
6925 max_length += kNaClAlignment;
6928 MONO_BB_FOR_EACH_INS (bb, ins) {
6929 #ifdef __native_client_codegen__
6931 int space_in_block = kNaClAlignment -
6932 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6933 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6934 if (space_in_block < max_len && max_len < kNaClAlignment) {
6935 max_length += space_in_block;
6938 #endif /*__native_client_codegen__*/
6939 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6942 /* Take prolog and epilog instrumentation into account */
6943 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6944 max_length += max_epilog_size;
6946 bb->max_length = max_length;
6950 sig = mono_method_signature (method);
6953 cinfo = cfg->arch.cinfo;
6955 if (sig->ret->type != MONO_TYPE_VOID) {
6956 /* Save volatile arguments to the stack */
6957 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6958 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6961 /* Keep this in sync with emit_load_volatile_arguments */
6962 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6963 ArgInfo *ainfo = cinfo->args + i;
6965 ins = cfg->args [i];
6967 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6968 /* Unused arguments */
6971 /* Save volatile arguments to the stack */
6972 if (ins->opcode != OP_REGVAR) {
6973 switch (ainfo->storage) {
6979 if (stack_offset & 0x1)
6981 else if (stack_offset & 0x2)
6983 else if (stack_offset & 0x4)
6988 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6991 * Save the original location of 'this',
6992 * get_generic_info_from_stack_frame () needs this to properly look up
6993 * the argument value during the handling of async exceptions.
6995 if (ins == cfg->args [0]) {
6996 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6997 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7001 case ArgInFloatSSEReg:
7002 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7004 case ArgInDoubleSSEReg:
7005 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7007 case ArgValuetypeInReg:
7008 for (quad = 0; quad < 2; quad ++) {
7009 switch (ainfo->pair_storage [quad]) {
7011 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7013 case ArgInFloatSSEReg:
7014 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7016 case ArgInDoubleSSEReg:
7017 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7022 g_assert_not_reached ();
7026 case ArgValuetypeAddrInIReg:
7027 if (ainfo->pair_storage [0] == ArgInIReg)
7028 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7034 /* Argument allocated to (non-volatile) register */
7035 switch (ainfo->storage) {
7037 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7040 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7043 g_assert_not_reached ();
7046 if (ins == cfg->args [0]) {
7047 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7048 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7053 if (cfg->method->save_lmf)
7054 args_clobbered = TRUE;
7057 args_clobbered = TRUE;
7058 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7061 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7062 args_clobbered = TRUE;
7065 * Optimize the common case of the first bblock making a call with the same
7066 * arguments as the method. This works because the arguments are still in their
7067 * original argument registers.
7068 * FIXME: Generalize this
7070 if (!args_clobbered) {
7071 MonoBasicBlock *first_bb = cfg->bb_entry;
7073 int filter = FILTER_IL_SEQ_POINT;
7075 next = mono_bb_first_inst (first_bb, filter);
7076 if (!next && first_bb->next_bb) {
7077 first_bb = first_bb->next_bb;
7078 next = mono_bb_first_inst (first_bb, filter);
7081 if (first_bb->in_count > 1)
7084 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7085 ArgInfo *ainfo = cinfo->args + i;
7086 gboolean match = FALSE;
7088 ins = cfg->args [i];
7089 if (ins->opcode != OP_REGVAR) {
7090 switch (ainfo->storage) {
7092 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7093 if (next->dreg == ainfo->reg) {
7097 next->opcode = OP_MOVE;
7098 next->sreg1 = ainfo->reg;
7099 /* Only continue if the instruction doesn't change argument regs */
7100 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7110 /* Argument allocated to (non-volatile) register */
7111 switch (ainfo->storage) {
7113 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7124 next = mono_inst_next (next, filter);
7125 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7132 if (cfg->gen_sdb_seq_points) {
7133 MonoInst *info_var = cfg->arch.seq_point_info_var;
7135 /* Initialize seq_point_info_var */
7136 if (cfg->compile_aot) {
7137 /* Initialize the variable from a GOT slot */
7138 /* Same as OP_AOTCONST */
7139 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7140 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7141 g_assert (info_var->opcode == OP_REGOFFSET);
7142 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7145 if (cfg->compile_aot) {
7146 /* Initialize ss_tramp_var */
7147 ins = cfg->arch.ss_tramp_var;
7148 g_assert (ins->opcode == OP_REGOFFSET);
7150 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7151 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7152 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7154 /* Initialize ss_trigger_page_var */
7155 ins = cfg->arch.ss_trigger_page_var;
7157 g_assert (ins->opcode == OP_REGOFFSET);
7159 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7160 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7164 cfg->code_len = code - cfg->native_code;
7166 g_assert (cfg->code_len < cfg->code_size);
7172 mono_arch_emit_epilog (MonoCompile *cfg)
7174 MonoMethod *method = cfg->method;
7177 int max_epilog_size;
7179 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7180 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7182 max_epilog_size = get_max_epilog_size (cfg);
7184 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7185 cfg->code_size *= 2;
7186 cfg->native_code = mono_realloc_native_code (cfg);
7187 cfg->stat_code_reallocs++;
7189 code = cfg->native_code + cfg->code_len;
7191 cfg->has_unwind_info_for_epilog = TRUE;
7193 /* Mark the start of the epilog */
7194 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7196 /* Save the uwind state which is needed by the out-of-line code */
7197 mono_emit_unwind_op_remember_state (cfg, code);
7199 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7200 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7202 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7204 if (method->save_lmf) {
7205 /* check if we need to restore protection of the stack after a stack overflow */
7206 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7208 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7209 /* we load the value in a separate instruction: this mechanism may be
7210 * used later as a safer way to do thread interruption
7212 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7213 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7215 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7216 /* note that the call trampoline will preserve eax/edx */
7217 x86_call_reg (code, X86_ECX);
7218 x86_patch (patch, code);
7220 /* FIXME: maybe save the jit tls in the prolog */
7222 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7223 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7227 /* Restore callee saved regs */
7228 for (i = 0; i < AMD64_NREG; ++i) {
7229 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7230 /* Restore only used_int_regs, not arch.saved_iregs */
7231 if (cfg->used_int_regs & (1 << i)) {
7232 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7233 mono_emit_unwind_op_same_value (cfg, code, i);
7234 async_exc_point (code);
7236 save_area_offset += 8;
7240 /* Load returned vtypes into registers if needed */
7241 cinfo = cfg->arch.cinfo;
7242 if (cinfo->ret.storage == ArgValuetypeInReg) {
7243 ArgInfo *ainfo = &cinfo->ret;
7244 MonoInst *inst = cfg->ret;
7246 for (quad = 0; quad < 2; quad ++) {
7247 switch (ainfo->pair_storage [quad]) {
7249 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7251 case ArgInFloatSSEReg:
7252 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7254 case ArgInDoubleSSEReg:
7255 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7260 g_assert_not_reached ();
7265 if (cfg->arch.omit_fp) {
7266 if (cfg->arch.stack_alloc_size) {
7267 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7271 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7273 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7274 async_exc_point (code);
7277 /* Restore the unwind state to be the same as before the epilog */
7278 mono_emit_unwind_op_restore_state (cfg, code);
7280 cfg->code_len = code - cfg->native_code;
7282 g_assert (cfg->code_len < cfg->code_size);
7286 mono_arch_emit_exceptions (MonoCompile *cfg)
7288 MonoJumpInfo *patch_info;
7291 MonoClass *exc_classes [16];
7292 guint8 *exc_throw_start [16], *exc_throw_end [16];
7293 guint32 code_size = 0;
7295 /* Compute needed space */
7296 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7297 if (patch_info->type == MONO_PATCH_INFO_EXC)
7299 if (patch_info->type == MONO_PATCH_INFO_R8)
7300 code_size += 8 + 15; /* sizeof (double) + alignment */
7301 if (patch_info->type == MONO_PATCH_INFO_R4)
7302 code_size += 4 + 15; /* sizeof (float) + alignment */
7303 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7304 code_size += 8 + 7; /*sizeof (void*) + alignment */
7307 #ifdef __native_client_codegen__
7308 /* Give us extra room on Native Client. This could be */
7309 /* more carefully calculated, but bundle alignment makes */
7310 /* it much trickier, so *2 like other places is good. */
7314 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7315 cfg->code_size *= 2;
7316 cfg->native_code = mono_realloc_native_code (cfg);
7317 cfg->stat_code_reallocs++;
7320 code = cfg->native_code + cfg->code_len;
7322 /* add code to raise exceptions */
7324 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7325 switch (patch_info->type) {
7326 case MONO_PATCH_INFO_EXC: {
7327 MonoClass *exc_class;
7331 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7333 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7334 g_assert (exc_class);
7335 throw_ip = patch_info->ip.i;
7337 //x86_breakpoint (code);
7338 /* Find a throw sequence for the same exception class */
7339 for (i = 0; i < nthrows; ++i)
7340 if (exc_classes [i] == exc_class)
7343 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7344 x86_jump_code (code, exc_throw_start [i]);
7345 patch_info->type = MONO_PATCH_INFO_NONE;
7349 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7353 exc_classes [nthrows] = exc_class;
7354 exc_throw_start [nthrows] = code;
7356 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7358 patch_info->type = MONO_PATCH_INFO_NONE;
7360 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7362 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7367 exc_throw_end [nthrows] = code;
7377 g_assert(code < cfg->native_code + cfg->code_size);
7380 /* Handle relocations with RIP relative addressing */
7381 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7382 gboolean remove = FALSE;
7383 guint8 *orig_code = code;
7385 switch (patch_info->type) {
7386 case MONO_PATCH_INFO_R8:
7387 case MONO_PATCH_INFO_R4: {
7388 guint8 *pos, *patch_pos;
7391 /* The SSE opcodes require a 16 byte alignment */
7392 #if defined(__default_codegen__)
7393 code = (guint8*)ALIGN_TO (code, 16);
7394 #elif defined(__native_client_codegen__)
7396 /* Pad this out with HLT instructions */
7397 /* or we can get garbage bytes emitted */
7398 /* which will fail validation */
7399 guint8 *aligned_code;
7400 /* extra align to make room for */
7401 /* mov/push below */
7402 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7403 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7404 /* The technique of hiding data in an */
7405 /* instruction has a problem here: we */
7406 /* need the data aligned to a 16-byte */
7407 /* boundary but the instruction cannot */
7408 /* cross the bundle boundary. so only */
7409 /* odd multiples of 16 can be used */
7410 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7413 while (code < aligned_code) {
7414 *(code++) = 0xf4; /* hlt */
7419 pos = cfg->native_code + patch_info->ip.i;
7420 if (IS_REX (pos [1])) {
7421 patch_pos = pos + 5;
7422 target_pos = code - pos - 9;
7425 patch_pos = pos + 4;
7426 target_pos = code - pos - 8;
7429 if (patch_info->type == MONO_PATCH_INFO_R8) {
7430 #ifdef __native_client_codegen__
7431 /* Hide 64-bit data in a */
7432 /* "mov imm64, r11" instruction. */
7433 /* write it before the start of */
7435 *(code-2) = 0x49; /* prefix */
7436 *(code-1) = 0xbb; /* mov X, %r11 */
7438 *(double*)code = *(double*)patch_info->data.target;
7439 code += sizeof (double);
7441 #ifdef __native_client_codegen__
7442 /* Hide 32-bit data in a */
7443 /* "push imm32" instruction. */
7444 *(code-1) = 0x68; /* push */
7446 *(float*)code = *(float*)patch_info->data.target;
7447 code += sizeof (float);
7450 *(guint32*)(patch_pos) = target_pos;
7455 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7458 if (cfg->compile_aot)
7461 /*loading is faster against aligned addresses.*/
7462 code = (guint8*)ALIGN_TO (code, 8);
7463 memset (orig_code, 0, code - orig_code);
7465 pos = cfg->native_code + patch_info->ip.i;
7467 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7468 if (IS_REX (pos [1]))
7469 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7471 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7473 *(gpointer*)code = (gpointer)patch_info->data.target;
7474 code += sizeof (gpointer);
7484 if (patch_info == cfg->patch_info)
7485 cfg->patch_info = patch_info->next;
7489 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7491 tmp->next = patch_info->next;
7494 g_assert (code < cfg->native_code + cfg->code_size);
7497 cfg->code_len = code - cfg->native_code;
7499 g_assert (cfg->code_len < cfg->code_size);
7503 #endif /* DISABLE_JIT */
7506 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7509 MonoMethodSignature *sig;
7511 int i, n, stack_area = 0;
7513 /* Keep this in sync with mono_arch_get_argument_info */
7515 if (enable_arguments) {
7516 /* Allocate a new area on the stack and save arguments there */
7517 sig = mono_method_signature (cfg->method);
7519 n = sig->param_count + sig->hasthis;
7521 stack_area = ALIGN_TO (n * 8, 16);
7523 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7525 for (i = 0; i < n; ++i) {
7526 inst = cfg->args [i];
7528 if (inst->opcode == OP_REGVAR)
7529 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7531 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7532 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7537 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7538 amd64_set_reg_template (code, AMD64_ARG_REG1);
7539 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7540 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7542 if (enable_arguments)
7543 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7557 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7560 int save_mode = SAVE_NONE;
7561 MonoMethod *method = cfg->method;
7562 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7565 switch (ret_type->type) {
7566 case MONO_TYPE_VOID:
7567 /* special case string .ctor icall */
7568 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7569 save_mode = SAVE_EAX;
7571 save_mode = SAVE_NONE;
7575 save_mode = SAVE_EAX;
7579 save_mode = SAVE_XMM;
7581 case MONO_TYPE_GENERICINST:
7582 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7583 save_mode = SAVE_EAX;
7587 case MONO_TYPE_VALUETYPE:
7588 save_mode = SAVE_STRUCT;
7591 save_mode = SAVE_EAX;
7595 /* Save the result and copy it into the proper argument register */
7596 switch (save_mode) {
7598 amd64_push_reg (code, AMD64_RAX);
7600 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7601 if (enable_arguments)
7602 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7606 if (enable_arguments)
7607 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7610 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7611 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7613 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7615 * The result is already in the proper argument register so no copying
7622 g_assert_not_reached ();
7625 /* Set %al since this is a varargs call */
7626 if (save_mode == SAVE_XMM)
7627 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7629 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7631 if (preserve_argument_registers) {
7632 for (i = 0; i < PARAM_REGS; ++i)
7633 amd64_push_reg (code, param_regs [i]);
7636 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7637 amd64_set_reg_template (code, AMD64_ARG_REG1);
7638 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7640 if (preserve_argument_registers) {
7641 for (i = PARAM_REGS - 1; i >= 0; --i)
7642 amd64_pop_reg (code, param_regs [i]);
7645 /* Restore result */
7646 switch (save_mode) {
7648 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7649 amd64_pop_reg (code, AMD64_RAX);
7655 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7656 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7657 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7662 g_assert_not_reached ();
7669 mono_arch_flush_icache (guint8 *code, gint size)
7675 mono_arch_flush_register_windows (void)
7680 mono_arch_is_inst_imm (gint64 imm)
7682 return amd64_is_imm32 (imm);
7686 * Determine whenever the trap whose info is in SIGINFO is caused by
7690 mono_arch_is_int_overflow (void *sigctx, void *info)
7697 mono_sigctx_to_monoctx (sigctx, &ctx);
7699 rip = (guint8*)ctx.gregs [AMD64_RIP];
7701 if (IS_REX (rip [0])) {
7702 reg = amd64_rex_b (rip [0]);
7708 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7710 reg += x86_modrm_rm (rip [1]);
7712 value = ctx.gregs [reg];
7722 mono_arch_get_patch_offset (guint8 *code)
7728 * mono_breakpoint_clean_code:
7730 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7731 * breakpoints in the original code, they are removed in the copy.
7733 * Returns TRUE if no sw breakpoint was present.
7736 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7739 * If method_start is non-NULL we need to perform bound checks, since we access memory
7740 * at code - offset we could go before the start of the method and end up in a different
7741 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7744 if (!method_start || code - offset >= method_start) {
7745 memcpy (buf, code - offset, size);
7747 int diff = code - method_start;
7748 memset (buf, 0, size);
7749 memcpy (buf + offset - diff, method_start, diff + size - offset);
7754 #if defined(__native_client_codegen__)
7755 /* For membase calls, we want the base register. for Native Client, */
7756 /* all indirect calls have the following sequence with the given sizes: */
7757 /* mov %eXX,%eXX [2-3] */
7758 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7759 /* and $0xffffffffffffffe0,%r11d [4] */
7760 /* add %r15,%r11 [3] */
7761 /* callq *%r11 [3] */
7764 /* Determine if code points to a NaCl call-through-register sequence, */
7765 /* (i.e., the last 3 instructions listed above) */
7767 is_nacl_call_reg_sequence(guint8* code)
7769 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7770 "\x4d\x03\xdf" /* add */
7771 "\x41\xff\xd3"; /* call */
7772 return memcmp(code, sequence, 10) == 0;
7775 /* Determine if code points to the first opcode of the mov membase component */
7776 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7777 /* (there could be a REX prefix before the opcode but it is ignored) */
7779 is_nacl_indirect_call_membase_sequence(guint8* code)
7781 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7782 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7783 /* and that src reg = dest reg */
7784 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7785 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7787 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7788 /* and has dst of r11 and base of r15 */
7789 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7790 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7792 #endif /* __native_client_codegen__ */
7795 mono_arch_get_this_arg_reg (guint8 *code)
7797 return AMD64_ARG_REG1;
7801 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7803 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7806 #define MAX_ARCH_DELEGATE_PARAMS 10
7809 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7811 guint8 *code, *start;
7815 start = code = mono_global_codeman_reserve (64);
7817 /* Replace the this argument with the target */
7818 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7819 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7820 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7822 g_assert ((code - start) < 64);
7824 start = code = mono_global_codeman_reserve (64);
7826 if (param_count == 0) {
7827 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7829 /* We have to shift the arguments left */
7830 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7831 for (i = 0; i < param_count; ++i) {
7834 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7836 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7838 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7842 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7844 g_assert ((code - start) < 64);
7847 nacl_global_codeman_validate (&start, 64, &code);
7848 mono_arch_flush_icache (start, code - start);
7851 *code_len = code - start;
7853 if (mono_jit_map_is_enabled ()) {
7856 buff = (char*)"delegate_invoke_has_target";
7858 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7859 mono_emit_jit_tramp (start, code - start, buff);
7863 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7868 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7871 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_len)
7873 guint8 *code, *start;
7876 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7879 start = code = mono_global_codeman_reserve (size);
7881 /* Replace the this argument with the target */
7882 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7883 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7886 /* Load the IMT reg */
7887 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7890 /* Load the vtable */
7891 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7892 amd64_jump_membase (code, AMD64_RAX, offset);
7893 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7896 *code_len = code - start;
7902 * mono_arch_get_delegate_invoke_impls:
7904 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7908 mono_arch_get_delegate_invoke_impls (void)
7916 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7917 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7919 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7920 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7921 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7922 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7923 g_free (tramp_name);
7926 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7927 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
7928 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
7929 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7930 g_free (tramp_name);
7932 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
7933 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
7934 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7935 g_free (tramp_name);
7942 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7944 guint8 *code, *start;
7947 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7950 /* FIXME: Support more cases */
7951 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7955 static guint8* cached = NULL;
7961 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7963 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7965 mono_memory_barrier ();
7969 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7970 for (i = 0; i < sig->param_count; ++i)
7971 if (!mono_is_regsize_var (sig->params [i]))
7973 if (sig->param_count > 4)
7976 code = cache [sig->param_count];
7980 if (mono_aot_only) {
7981 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7982 start = mono_aot_get_trampoline (name);
7985 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7988 mono_memory_barrier ();
7990 cache [sig->param_count] = start;
7997 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7999 return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
8003 mono_arch_finish_init (void)
8005 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8006 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8011 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8015 #if defined(__default_codegen__)
8016 #define CMP_SIZE (6 + 1)
8017 #define CMP_REG_REG_SIZE (4 + 1)
8018 #define BR_SMALL_SIZE 2
8019 #define BR_LARGE_SIZE 6
8020 #define MOV_REG_IMM_SIZE 10
8021 #define MOV_REG_IMM_32BIT_SIZE 6
8022 #define JUMP_REG_SIZE (2 + 1)
8023 #elif defined(__native_client_codegen__)
8024 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8025 #define CMP_SIZE ((6 + 1) * 2 - 1)
8026 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8027 #define BR_SMALL_SIZE (2 * 2 - 1)
8028 #define BR_LARGE_SIZE (6 * 2 - 1)
8029 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8030 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8031 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8032 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8033 /* Jump membase's size is large and unpredictable */
8034 /* in native client, just pad it out a whole bundle. */
8035 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8039 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8041 int i, distance = 0;
8042 for (i = start; i < target; ++i)
8043 distance += imt_entries [i]->chunk_size;
8048 * LOCKING: called with the domain lock held
8051 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8052 gpointer fail_tramp)
8056 guint8 *code, *start;
8057 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8059 for (i = 0; i < count; ++i) {
8060 MonoIMTCheckItem *item = imt_entries [i];
8061 if (item->is_equals) {
8062 if (item->check_target_idx) {
8063 if (!item->compare_done) {
8064 if (amd64_is_imm32 (item->key))
8065 item->chunk_size += CMP_SIZE;
8067 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8069 if (item->has_target_code) {
8070 item->chunk_size += MOV_REG_IMM_SIZE;
8072 if (vtable_is_32bit)
8073 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8075 item->chunk_size += MOV_REG_IMM_SIZE;
8076 #ifdef __native_client_codegen__
8077 item->chunk_size += JUMP_MEMBASE_SIZE;
8080 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8083 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8084 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8086 if (vtable_is_32bit)
8087 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8089 item->chunk_size += MOV_REG_IMM_SIZE;
8090 item->chunk_size += JUMP_REG_SIZE;
8091 /* with assert below:
8092 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8094 #ifdef __native_client_codegen__
8095 item->chunk_size += JUMP_MEMBASE_SIZE;
8100 if (amd64_is_imm32 (item->key))
8101 item->chunk_size += CMP_SIZE;
8103 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8104 item->chunk_size += BR_LARGE_SIZE;
8105 imt_entries [item->check_target_idx]->compare_done = TRUE;
8107 size += item->chunk_size;
8109 #if defined(__native_client__) && defined(__native_client_codegen__)
8110 /* In Native Client, we don't re-use thunks, allocate from the */
8111 /* normal code manager paths. */
8112 code = mono_domain_code_reserve (domain, size);
8115 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8117 code = mono_domain_code_reserve (domain, size);
8120 for (i = 0; i < count; ++i) {
8121 MonoIMTCheckItem *item = imt_entries [i];
8122 item->code_target = code;
8123 if (item->is_equals) {
8124 gboolean fail_case = !item->check_target_idx && fail_tramp;
8126 if (item->check_target_idx || fail_case) {
8127 if (!item->compare_done || fail_case) {
8128 if (amd64_is_imm32 (item->key))
8129 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8131 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8132 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8135 item->jmp_code = code;
8136 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8137 if (item->has_target_code) {
8138 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8139 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8141 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8142 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8146 amd64_patch (item->jmp_code, code);
8147 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8148 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8149 item->jmp_code = NULL;
8152 /* enable the commented code to assert on wrong method */
8154 if (amd64_is_imm32 (item->key))
8155 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8157 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8158 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8160 item->jmp_code = code;
8161 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8162 /* See the comment below about R10 */
8163 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8164 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8165 amd64_patch (item->jmp_code, code);
8166 amd64_breakpoint (code);
8167 item->jmp_code = NULL;
8169 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8170 needs to be preserved. R10 needs
8171 to be preserved for calls which
8172 require a runtime generic context,
8173 but interface calls don't. */
8174 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8175 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8179 if (amd64_is_imm32 (item->key))
8180 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8182 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8183 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8185 item->jmp_code = code;
8186 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8187 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8189 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8191 g_assert (code - item->code_target <= item->chunk_size);
8193 /* patch the branches to get to the target items */
8194 for (i = 0; i < count; ++i) {
8195 MonoIMTCheckItem *item = imt_entries [i];
8196 if (item->jmp_code) {
8197 if (item->check_target_idx) {
8198 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8204 mono_stats.imt_thunks_size += code - start;
8205 g_assert (code - start <= size);
8207 nacl_domain_code_validate(domain, &start, size, &code);
8208 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8214 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8216 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8220 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8222 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8226 mono_arch_get_cie_program (void)
8230 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8231 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8239 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8241 MonoInst *ins = NULL;
8244 if (cmethod->klass == mono_defaults.math_class) {
8245 if (strcmp (cmethod->name, "Sin") == 0) {
8247 } else if (strcmp (cmethod->name, "Cos") == 0) {
8249 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8251 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8255 if (opcode && fsig->param_count == 1) {
8256 MONO_INST_NEW (cfg, ins, opcode);
8257 ins->type = STACK_R8;
8258 ins->dreg = mono_alloc_freg (cfg);
8259 ins->sreg1 = args [0]->dreg;
8260 MONO_ADD_INS (cfg->cbb, ins);
8264 if (cfg->opt & MONO_OPT_CMOV) {
8265 if (strcmp (cmethod->name, "Min") == 0) {
8266 if (fsig->params [0]->type == MONO_TYPE_I4)
8268 if (fsig->params [0]->type == MONO_TYPE_U4)
8269 opcode = OP_IMIN_UN;
8270 else if (fsig->params [0]->type == MONO_TYPE_I8)
8272 else if (fsig->params [0]->type == MONO_TYPE_U8)
8273 opcode = OP_LMIN_UN;
8274 } else if (strcmp (cmethod->name, "Max") == 0) {
8275 if (fsig->params [0]->type == MONO_TYPE_I4)
8277 if (fsig->params [0]->type == MONO_TYPE_U4)
8278 opcode = OP_IMAX_UN;
8279 else if (fsig->params [0]->type == MONO_TYPE_I8)
8281 else if (fsig->params [0]->type == MONO_TYPE_U8)
8282 opcode = OP_LMAX_UN;
8286 if (opcode && fsig->param_count == 2) {
8287 MONO_INST_NEW (cfg, ins, opcode);
8288 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8289 ins->dreg = mono_alloc_ireg (cfg);
8290 ins->sreg1 = args [0]->dreg;
8291 ins->sreg2 = args [1]->dreg;
8292 MONO_ADD_INS (cfg->cbb, ins);
8296 /* OP_FREM is not IEEE compatible */
8297 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8298 MONO_INST_NEW (cfg, ins, OP_FREM);
8299 ins->inst_i0 = args [0];
8300 ins->inst_i1 = args [1];
8310 mono_arch_print_tree (MonoInst *tree, int arity)
8316 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8318 return ctx->gregs [reg];
8322 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8324 ctx->gregs [reg] = val;
8328 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8330 gpointer *sp, old_value;
8334 bp = MONO_CONTEXT_GET_BP (ctx);
8335 sp = *(gpointer*)(bp + clause->exvar_offset);
8338 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8347 * mono_arch_emit_load_aotconst:
8349 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8350 * TARGET from the mscorlib GOT in full-aot code.
8351 * On AMD64, the result is placed into R11.
8354 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8356 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8357 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8363 * mono_arch_get_trampolines:
8365 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8369 mono_arch_get_trampolines (gboolean aot)
8371 return mono_amd64_get_exception_trampolines (aot);
8374 /* Soft Debug support */
8375 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8378 * mono_arch_set_breakpoint:
8380 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8381 * The location should contain code emitted by OP_SEQ_POINT.
8384 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8387 guint8 *orig_code = code;
8390 guint32 native_offset = ip - (guint8*)ji->code_start;
8391 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8393 g_assert (info->bp_addrs [native_offset] == 0);
8394 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8397 * In production, we will use int3 (has to fix the size in the md
8398 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8401 g_assert (code [0] == 0x90);
8402 if (breakpoint_size == 8) {
8403 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8405 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8406 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8409 g_assert (code - orig_code == breakpoint_size);
8414 * mono_arch_clear_breakpoint:
8416 * Clear the breakpoint at IP.
8419 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8425 guint32 native_offset = ip - (guint8*)ji->code_start;
8426 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8428 info->bp_addrs [native_offset] = NULL;
8430 for (i = 0; i < breakpoint_size; ++i)
8436 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8439 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8440 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8445 siginfo_t* sinfo = (siginfo_t*) info;
8446 /* Sometimes the address is off by 4 */
8447 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8455 * mono_arch_skip_breakpoint:
8457 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8458 * we resume, the instruction is not executed again.
8461 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8464 /* The breakpoint instruction is a call */
8466 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8471 * mono_arch_start_single_stepping:
8473 * Start single stepping.
8476 mono_arch_start_single_stepping (void)
8478 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8479 ss_trampoline = mini_get_single_step_trampoline ();
8483 * mono_arch_stop_single_stepping:
8485 * Stop single stepping.
8488 mono_arch_stop_single_stepping (void)
8490 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8491 ss_trampoline = NULL;
8495 * mono_arch_is_single_step_event:
8497 * Return whenever the machine state in SIGCTX corresponds to a single
8501 mono_arch_is_single_step_event (void *info, void *sigctx)
8504 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8505 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8510 siginfo_t* sinfo = (siginfo_t*) info;
8511 /* Sometimes the address is off by 4 */
8512 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8520 * mono_arch_skip_single_step:
8522 * Modify CTX so the ip is placed after the single step trigger instruction,
8523 * we resume, the instruction is not executed again.
8526 mono_arch_skip_single_step (MonoContext *ctx)
8528 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8532 * mono_arch_create_seq_point_info:
8534 * Return a pointer to a data structure which is used by the sequence
8535 * point implementation in AOTed code.
8538 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8543 // FIXME: Add a free function
8545 mono_domain_lock (domain);
8546 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8548 mono_domain_unlock (domain);
8551 ji = mono_jit_info_table_find (domain, (char*)code);
8554 // FIXME: Optimize the size
8555 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8557 info->ss_tramp_addr = &ss_trampoline;
8559 mono_domain_lock (domain);
8560 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8562 mono_domain_unlock (domain);
8569 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8571 ext->lmf.previous_lmf = prev_lmf;
8572 /* Mark that this is a MonoLMFExt */
8573 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8574 ext->lmf.rsp = (gssize)ext;
8580 mono_arch_opcode_supported (int opcode)
8583 case OP_ATOMIC_ADD_I4:
8584 case OP_ATOMIC_ADD_I8:
8585 case OP_ATOMIC_EXCHANGE_I4:
8586 case OP_ATOMIC_EXCHANGE_I8:
8587 case OP_ATOMIC_CAS_I4:
8588 case OP_ATOMIC_CAS_I8:
8589 case OP_ATOMIC_LOAD_I1:
8590 case OP_ATOMIC_LOAD_I2:
8591 case OP_ATOMIC_LOAD_I4:
8592 case OP_ATOMIC_LOAD_I8:
8593 case OP_ATOMIC_LOAD_U1:
8594 case OP_ATOMIC_LOAD_U2:
8595 case OP_ATOMIC_LOAD_U4:
8596 case OP_ATOMIC_LOAD_U8:
8597 case OP_ATOMIC_LOAD_R4:
8598 case OP_ATOMIC_LOAD_R8:
8599 case OP_ATOMIC_STORE_I1:
8600 case OP_ATOMIC_STORE_I2:
8601 case OP_ATOMIC_STORE_I4:
8602 case OP_ATOMIC_STORE_I8:
8603 case OP_ATOMIC_STORE_U1:
8604 case OP_ATOMIC_STORE_U2:
8605 case OP_ATOMIC_STORE_U4:
8606 case OP_ATOMIC_STORE_U8:
8607 case OP_ATOMIC_STORE_R4:
8608 case OP_ATOMIC_STORE_R8: