mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 static void
 178 amd64_patch (unsigned char* code, gpointer target)
 179 {
 180         guint8 rex = 0;
 181
 182         /* Skip REX */
 183         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 184                 rex = code [0];
 185                 code += 1;
 186         }
 187
 188         if ((code [0] & 0xf8) == 0xb8) {
 189                 /* amd64_set_reg_template */
 190                 *(guint64*)(code + 1) = (guint64)target;
 191         }
 192         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 193                 /* mov 0(%rip), %dreg */
 194                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 195         }
 196         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 197                 /* call *<OFFSET>(%rip) */
 198                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 199         }
 200         else if (code [0] == 0xe8) {
 201                 /* call <DISP> */
 202                 gint64 disp = (guint8*)target - (guint8*)code;
 203                 g_assert (amd64_is_imm32 (disp));
 204                 x86_patch (code, (unsigned char*)target);
 205         }
 206         else
 207                 x86_patch (code, (unsigned char*)target);
 208 }
 209
 210 void
 211 mono_amd64_patch (unsigned char* code, gpointer target)
 212 {
 213         amd64_patch (code, target);
 214 }
 215
 216 #define DEBUG(a) if (cfg->verbose_level > 1) a
 217
 218 static void inline
 219 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 ainfo->arg_size = sizeof (mgreg_t);
 226                 /* Since the same stack slot size is used for all arg */
 227                 /*  types, it needs to be big enough to hold them all */
 228                 (*stack_size) += sizeof(mgreg_t);
 229     }
 230     else {
 231                 ainfo->storage = ArgInIReg;
 232                 ainfo->reg = param_regs [*gr];
 233                 (*gr) ++;
 234     }
 235 }
 236
 237 static void inline
 238 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 239 {
 240     ainfo->offset = *stack_size;
 241
 242     if (*gr >= FLOAT_PARAM_REGS) {
 243                 ainfo->storage = ArgOnStack;
 244                 ainfo->arg_size = sizeof (mgreg_t);
 245                 /* Since the same stack slot size is used for both float */
 246                 /*  types, it needs to be big enough to hold them both */
 247                 (*stack_size) += sizeof(mgreg_t);
 248     }
 249     else {
 250                 /* A double register */
 251                 if (is_double)
 252                         ainfo->storage = ArgInDoubleSSEReg;
 253                 else
 254                         ainfo->storage = ArgInFloatSSEReg;
 255                 ainfo->reg = *gr;
 256                 (*gr) += 1;
 257     }
 258 }
 259
 260 typedef enum ArgumentClass {
 261         ARG_CLASS_NO_CLASS,
 262         ARG_CLASS_MEMORY,
 263         ARG_CLASS_INTEGER,
 264         ARG_CLASS_SSE
 265 } ArgumentClass;
 266
 267 static ArgumentClass
 268 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 269 {
 270         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 271         MonoType *ptype;
 272
 273         ptype = mini_get_underlying_type (type);
 274         switch (ptype->type) {
 275         case MONO_TYPE_I1:
 276         case MONO_TYPE_U1:
 277         case MONO_TYPE_I2:
 278         case MONO_TYPE_U2:
 279         case MONO_TYPE_I4:
 280         case MONO_TYPE_U4:
 281         case MONO_TYPE_I:
 282         case MONO_TYPE_U:
 283         case MONO_TYPE_STRING:
 284         case MONO_TYPE_OBJECT:
 285         case MONO_TYPE_CLASS:
 286         case MONO_TYPE_SZARRAY:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_ARRAY:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 static int
 342 count_fields_nested (MonoClass *klass)
 343 {
 344         MonoMarshalType *info;
 345         int i, count;
 346
 347         info = mono_marshal_load_type_info (klass);
 348         g_assert(info);
 349         count = 0;
 350         for (i = 0; i < info->num_fields; ++i) {
 351                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 352                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 353                 else
 354                         count ++;
 355         }
 356         return count;
 357 }
 358
 359 static int
 360 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 361 {
 362         MonoMarshalType *info;
 363         int i;
 364
 365         info = mono_marshal_load_type_info (klass);
 366         g_assert(info);
 367         for (i = 0; i < info->num_fields; ++i) {
 368                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 369                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 370                 } else {
 371                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 372                         fields [index].offset += offset;
 373                         index ++;
 374                 }
 375         }
 376         return index;
 377 }
 378
 379 #ifdef TARGET_WIN32
 380 static void
 381 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 382                                          gboolean is_return,
 383                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 384 {
 385         guint32 size, i, nfields;
 386         guint32 argsize = 8;
 387         ArgumentClass arg_class;
 388         MonoMarshalType *info = NULL;
 389         MonoMarshalField *fields = NULL;
 390         MonoClass *klass;
 391         gboolean pass_on_stack = FALSE;
 392
 393         klass = mono_class_from_mono_type (type);
 394         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 395         if (!sig->pinvoke)
 396                 pass_on_stack = TRUE;
 397
 398         /* If this struct can't be split up naturally into 8-byte */
 399         /* chunks (registers), pass it on the stack.              */
 400         if (sig->pinvoke && !pass_on_stack) {
 401                 guint32 align;
 402                 guint32 field_size;
 403
 404                 info = mono_marshal_load_type_info (klass);
 405                 g_assert (info);
 406
 407                 /*
 408                  * Collect field information recursively to be able to
 409                  * handle nested structures.
 410                  */
 411                 nfields = count_fields_nested (klass);
 412                 fields = g_new0 (MonoMarshalField, nfields);
 413                 collect_field_info_nested (klass, fields, 0, 0);
 414
 415                 for (i = 0; i < nfields; ++i) {
 416                         field_size = mono_marshal_type_size (fields [i].field->type,
 417                                                            fields [i].mspec,
 418                                                            &align, TRUE, klass->unicode);
 419                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 420                                 pass_on_stack = TRUE;
 421                                 break;
 422                         }
 423                 }
 424         }
 425
 426         if (pass_on_stack) {
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 431                 if (!is_return)
 432                         ainfo->arg_size = ALIGN_TO (size, 8);
 433
 434                 g_free (fields);
 435                 return;
 436         }
 437
 438         if (!sig->pinvoke) {
 439                 int n = mono_class_value_size (klass, NULL);
 440
 441                 argsize = n;
 442
 443                 if (n > 8)
 444                         arg_class = ARG_CLASS_MEMORY;
 445                 else
 446                         /* Always pass in 1 integer register */
 447                         arg_class = ARG_CLASS_INTEGER;
 448         } else {
 449                 g_assert (info);
 450
 451                 if (!fields) {
 452                         ainfo->storage = ArgValuetypeInReg;
 453                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 454                         return;
 455                 }
 456
 457                 switch (info->native_size) {
 458                 case 1: case 2: case 4: case 8:
 459                         break;
 460                 default:
 461                         if (is_return) {
 462                                 ainfo->storage = ArgValuetypeAddrInIReg;
 463                                 ainfo->offset = *stack_size;
 464                                 *stack_size += ALIGN_TO (info->native_size, 8);
 465                         }
 466                         else {
 467                                 ainfo->storage = ArgValuetypeAddrInIReg;
 468
 469                                 if (*gr < PARAM_REGS) {
 470                                         ainfo->pair_storage [0] = ArgInIReg;
 471                                         ainfo->pair_regs [0] = param_regs [*gr];
 472                                         (*gr) ++;
 473                                 }
 474                                 else {
 475                                         ainfo->pair_storage [0] = ArgOnStack;
 476                                         ainfo->offset = *stack_size;
 477                                         ainfo->arg_size = sizeof (mgreg_t);
 478                                         *stack_size += 8;
 479                                 }
 480                         }
 481
 482                         g_free (fields);
 483                         return;
 484                 }
 485
 486                 int size;
 487                 guint32 align;
 488                 ArgumentClass class1;
 489
 490                 if (nfields == 0)
 491                         class1 = ARG_CLASS_MEMORY;
 492                 else
 493                         class1 = ARG_CLASS_NO_CLASS;
 494                 for (i = 0; i < nfields; ++i) {
 495                         size = mono_marshal_type_size (fields [i].field->type,
 496                                                                                    fields [i].mspec,
 497                                                                                    &align, TRUE, klass->unicode);
 498                         /* How far into this quad this data extends.*/
 499                         /* (8 is size of quad) */
 500                         argsize = fields [i].offset + size;
 501
 502                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 503                 }
 504                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 505                 arg_class = class1;
 506         }
 507
 508         g_free (fields);
 509
 510         /* Allocate registers */
 511         {
 512                 int orig_gr = *gr;
 513                 int orig_fr = *fr;
 514
 515                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 516                         argsize ++;
 517
 518                 ainfo->storage = ArgValuetypeInReg;
 519                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 520                 ainfo->pair_size [0] = argsize;
 521                 ainfo->pair_size [1] = 0;
 522                 ainfo->nregs = 1;
 523                 switch (arg_class) {
 524                 case ARG_CLASS_INTEGER:
 525                         if (*gr >= PARAM_REGS)
 526                                 arg_class = ARG_CLASS_MEMORY;
 527                         else {
 528                                 ainfo->pair_storage [0] = ArgInIReg;
 529                                 if (is_return)
 530                                         ainfo->pair_regs [0] = return_regs [*gr];
 531                                 else
 532                                         ainfo->pair_regs [0] = param_regs [*gr];
 533                                 (*gr) ++;
 534                         }
 535                         break;
 536                 case ARG_CLASS_SSE:
 537                         if (*fr >= FLOAT_PARAM_REGS)
 538                                 arg_class = ARG_CLASS_MEMORY;
 539                         else {
 540                                 if (argsize <= 4)
 541                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 542                                 else
 543                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 544                                 ainfo->pair_regs [0] = *fr;
 545                                 (*fr) ++;
 546                         }
 547                         break;
 548                 case ARG_CLASS_MEMORY:
 549                         break;
 550                 default:
 551                         g_assert_not_reached ();
 552                 }
 553
 554                 if (arg_class == ARG_CLASS_MEMORY) {
 555                         /* Revert possible register assignments */
 556                         *gr = orig_gr;
 557                         *fr = orig_fr;
 558
 559                         ainfo->offset = *stack_size;
 560                         *stack_size += sizeof (mgreg_t);
 561                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 562                         if (!is_return)
 563                                 ainfo->arg_size = sizeof (mgreg_t);
 564                 }
 565         }
 566 }
 567 #endif /* TARGET_WIN32 */
 568
 569 static void
 570 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 571                            gboolean is_return,
 572                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 573 {
 574 #ifdef TARGET_WIN32
 575         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 576 #else
 577         guint32 size, quad, nquads, i, nfields;
 578         /* Keep track of the size used in each quad so we can */
 579         /* use the right size when copying args/return vars.  */
 580         guint32 quadsize [2] = {8, 8};
 581         ArgumentClass args [2];
 582         MonoMarshalType *info = NULL;
 583         MonoMarshalField *fields = NULL;
 584         MonoClass *klass;
 585         gboolean pass_on_stack = FALSE;
 586
 587         klass = mono_class_from_mono_type (type);
 588         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 589         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 590                 /* We pass and return vtypes of size 8 in a register */
 591         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 592                 pass_on_stack = TRUE;
 593         }
 594
 595         /* If this struct can't be split up naturally into 8-byte */
 596         /* chunks (registers), pass it on the stack.              */
 597         if (sig->pinvoke && !pass_on_stack) {
 598                 guint32 align;
 599                 guint32 field_size;
 600
 601                 info = mono_marshal_load_type_info (klass);
 602                 g_assert (info);
 603
 604                 /*
 605                  * Collect field information recursively to be able to
 606                  * handle nested structures.
 607                  */
 608                 nfields = count_fields_nested (klass);
 609                 fields = g_new0 (MonoMarshalField, nfields);
 610                 collect_field_info_nested (klass, fields, 0, 0);
 611
 612                 for (i = 0; i < nfields; ++i) {
 613                         field_size = mono_marshal_type_size (fields [i].field->type,
 614                                                            fields [i].mspec,
 615                                                            &align, TRUE, klass->unicode);
 616                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 617                                 pass_on_stack = TRUE;
 618                                 break;
 619                         }
 620                 }
 621         }
 622
 623         if (size == 0) {
 624                 ainfo->storage = ArgValuetypeInReg;
 625                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 626                 return;
 627         }
 628
 629         if (pass_on_stack) {
 630                 /* Allways pass in memory */
 631                 ainfo->offset = *stack_size;
 632                 *stack_size += ALIGN_TO (size, 8);
 633                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 634                 if (!is_return)
 635                         ainfo->arg_size = ALIGN_TO (size, 8);
 636
 637                 g_free (fields);
 638                 return;
 639         }
 640
 641         if (size > 8)
 642                 nquads = 2;
 643         else
 644                 nquads = 1;
 645
 646         if (!sig->pinvoke) {
 647                 int n = mono_class_value_size (klass, NULL);
 648
 649                 quadsize [0] = n >= 8 ? 8 : n;
 650                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 651
 652                 /* Always pass in 1 or 2 integer registers */
 653                 args [0] = ARG_CLASS_INTEGER;
 654                 args [1] = ARG_CLASS_INTEGER;
 655                 /* Only the simplest cases are supported */
 656                 if (is_return && nquads != 1) {
 657                         args [0] = ARG_CLASS_MEMORY;
 658                         args [1] = ARG_CLASS_MEMORY;
 659                 }
 660         } else {
 661                 /*
 662                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 663                  * The X87 and SSEUP stuff is left out since there are no such types in
 664                  * the CLR.
 665                  */
 666                 g_assert (info);
 667
 668                 if (!fields) {
 669                         ainfo->storage = ArgValuetypeInReg;
 670                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 671                         return;
 672                 }
 673
 674                 if (info->native_size > 16) {
 675                         ainfo->offset = *stack_size;
 676                         *stack_size += ALIGN_TO (info->native_size, 8);
 677                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 678                         if (!is_return)
 679                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 680
 681                         g_free (fields);
 682                         return;
 683                 }
 684
 685                 args [0] = ARG_CLASS_NO_CLASS;
 686                 args [1] = ARG_CLASS_NO_CLASS;
 687                 for (quad = 0; quad < nquads; ++quad) {
 688                         int size;
 689                         guint32 align;
 690                         ArgumentClass class1;
 691
 692                         if (nfields == 0)
 693                                 class1 = ARG_CLASS_MEMORY;
 694                         else
 695                                 class1 = ARG_CLASS_NO_CLASS;
 696                         for (i = 0; i < nfields; ++i) {
 697                                 size = mono_marshal_type_size (fields [i].field->type,
 698                                                                                            fields [i].mspec,
 699                                                                                            &align, TRUE, klass->unicode);
 700                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 701                                         /* Unaligned field */
 702                                         NOT_IMPLEMENTED;
 703                                 }
 704
 705                                 /* Skip fields in other quad */
 706                                 if ((quad == 0) && (fields [i].offset >= 8))
 707                                         continue;
 708                                 if ((quad == 1) && (fields [i].offset < 8))
 709                                         continue;
 710
 711                                 /* How far into this quad this data extends.*/
 712                                 /* (8 is size of quad) */
 713                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 714
 715                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 716                         }
 717                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 718                         args [quad] = class1;
 719                 }
 720         }
 721
 722         g_free (fields);
 723
 724         /* Post merger cleanup */
 725         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 726                 args [0] = args [1] = ARG_CLASS_MEMORY;
 727
 728         /* Allocate registers */
 729         {
 730                 int orig_gr = *gr;
 731                 int orig_fr = *fr;
 732
 733                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 734                         quadsize [0] ++;
 735                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 736                         quadsize [1] ++;
 737
 738                 ainfo->storage = ArgValuetypeInReg;
 739                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 740                 g_assert (quadsize [0] <= 8);
 741                 g_assert (quadsize [1] <= 8);
 742                 ainfo->pair_size [0] = quadsize [0];
 743                 ainfo->pair_size [1] = quadsize [1];
 744                 ainfo->nregs = nquads;
 745                 for (quad = 0; quad < nquads; ++quad) {
 746                         switch (args [quad]) {
 747                         case ARG_CLASS_INTEGER:
 748                                 if (*gr >= PARAM_REGS)
 749                                         args [quad] = ARG_CLASS_MEMORY;
 750                                 else {
 751                                         ainfo->pair_storage [quad] = ArgInIReg;
 752                                         if (is_return)
 753                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 754                                         else
 755                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 756                                         (*gr) ++;
 757                                 }
 758                                 break;
 759                         case ARG_CLASS_SSE:
 760                                 if (*fr >= FLOAT_PARAM_REGS)
 761                                         args [quad] = ARG_CLASS_MEMORY;
 762                                 else {
 763                                         if (quadsize[quad] <= 4)
 764                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 765                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 766                                         ainfo->pair_regs [quad] = *fr;
 767                                         (*fr) ++;
 768                                 }
 769                                 break;
 770                         case ARG_CLASS_MEMORY:
 771                                 break;
 772                         default:
 773                                 g_assert_not_reached ();
 774                         }
 775                 }
 776
 777                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 778                         int arg_size;
 779                         /* Revert possible register assignments */
 780                         *gr = orig_gr;
 781                         *fr = orig_fr;
 782
 783                         ainfo->offset = *stack_size;
 784                         if (sig->pinvoke)
 785                                 arg_size = ALIGN_TO (info->native_size, 8);
 786                         else
 787                                 arg_size = nquads * sizeof(mgreg_t);
 788                         *stack_size += arg_size;
 789                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 790                         if (!is_return)
 791                                 ainfo->arg_size = arg_size;
 792                 }
 793         }
 794 #endif /* !TARGET_WIN32 */
 795 }
 796
 797 /*
 798  * get_call_info:
 799  *
 800  * Obtain information about a call according to the calling convention.
 801  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 802  * Draft Version 0.23" document for more information.
 803  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 804  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 805  */
 806 static CallInfo*
 807 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 808 {
 809         guint32 i, gr, fr, pstart;
 810         MonoType *ret_type;
 811         int n = sig->hasthis + sig->param_count;
 812         guint32 stack_size = 0;
 813         CallInfo *cinfo;
 814         gboolean is_pinvoke = sig->pinvoke;
 815
 816         if (mp)
 817                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 818         else
 819                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 820
 821         cinfo->nargs = n;
 822         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 823
 824         gr = 0;
 825         fr = 0;
 826
 827 #ifdef TARGET_WIN32
 828         /* Reserve space where the callee can save the argument registers */
 829         stack_size = 4 * sizeof (mgreg_t);
 830 #endif
 831
 832         /* return value */
 833         ret_type = mini_get_underlying_type (sig->ret);
 834         switch (ret_type->type) {
 835         case MONO_TYPE_I1:
 836         case MONO_TYPE_U1:
 837         case MONO_TYPE_I2:
 838         case MONO_TYPE_U2:
 839         case MONO_TYPE_I4:
 840         case MONO_TYPE_U4:
 841         case MONO_TYPE_I:
 842         case MONO_TYPE_U:
 843         case MONO_TYPE_PTR:
 844         case MONO_TYPE_FNPTR:
 845         case MONO_TYPE_CLASS:
 846         case MONO_TYPE_OBJECT:
 847         case MONO_TYPE_SZARRAY:
 848         case MONO_TYPE_ARRAY:
 849         case MONO_TYPE_STRING:
 850                 cinfo->ret.storage = ArgInIReg;
 851                 cinfo->ret.reg = AMD64_RAX;
 852                 break;
 853         case MONO_TYPE_U8:
 854         case MONO_TYPE_I8:
 855                 cinfo->ret.storage = ArgInIReg;
 856                 cinfo->ret.reg = AMD64_RAX;
 857                 break;
 858         case MONO_TYPE_R4:
 859                 cinfo->ret.storage = ArgInFloatSSEReg;
 860                 cinfo->ret.reg = AMD64_XMM0;
 861                 break;
 862         case MONO_TYPE_R8:
 863                 cinfo->ret.storage = ArgInDoubleSSEReg;
 864                 cinfo->ret.reg = AMD64_XMM0;
 865                 break;
 866         case MONO_TYPE_GENERICINST:
 867                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 868                         cinfo->ret.storage = ArgInIReg;
 869                         cinfo->ret.reg = AMD64_RAX;
 870                         break;
 871                 }
 872                 if (mini_is_gsharedvt_type (ret_type)) {
 873                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 874                         break;
 875                 }
 876                 /* fall through */
 877         case MONO_TYPE_VALUETYPE:
 878         case MONO_TYPE_TYPEDBYREF: {
 879                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 880
 881                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 882                 g_assert (cinfo->ret.storage != ArgInIReg);
 883                 break;
 884         }
 885         case MONO_TYPE_VAR:
 886         case MONO_TYPE_MVAR:
 887                 g_assert (mini_is_gsharedvt_type (ret_type));
 888                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 889                 break;
 890         case MONO_TYPE_VOID:
 891                 break;
 892         default:
 893                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 894         }
 895
 896         pstart = 0;
 897         /*
 898          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 899          * the first argument, allowing 'this' to be always passed in the first arg reg.
 900          * Also do this if the first argument is a reference type, since virtual calls
 901          * are sometimes made using calli without sig->hasthis set, like in the delegate
 902          * invoke wrappers.
 903          */
 904         ArgStorage ret_storage = cinfo->ret.storage;
 905         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 906                 if (sig->hasthis) {
 907                         add_general (&gr, &stack_size, cinfo->args + 0);
 908                 } else {
 909                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 910                         pstart = 1;
 911                 }
 912                 add_general (&gr, &stack_size, &cinfo->ret);
 913                 cinfo->ret.storage = ret_storage;
 914                 cinfo->vret_arg_index = 1;
 915         } else {
 916                 /* this */
 917                 if (sig->hasthis)
 918                         add_general (&gr, &stack_size, cinfo->args + 0);
 919
 920                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 921                         add_general (&gr, &stack_size, &cinfo->ret);
 922                         cinfo->ret.storage = ret_storage;
 923                 }
 924         }
 925
 926         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 927                 gr = PARAM_REGS;
 928                 fr = FLOAT_PARAM_REGS;
 929
 930                 /* Emit the signature cookie just before the implicit arguments */
 931                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 932         }
 933
 934         for (i = pstart; i < sig->param_count; ++i) {
 935                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 936                 MonoType *ptype;
 937
 938 #ifdef TARGET_WIN32
 939                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 940                 if (gr > fr)
 941                         fr = gr;
 942                 else if (fr > gr)
 943                         gr = fr;
 944 #endif
 945
 946                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 947                         /* We allways pass the sig cookie on the stack for simplicity */
 948                         /*
 949                          * Prevent implicit arguments + the sig cookie from being passed
 950                          * in registers.
 951                          */
 952                         gr = PARAM_REGS;
 953                         fr = FLOAT_PARAM_REGS;
 954
 955                         /* Emit the signature cookie just before the implicit arguments */
 956                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 957                 }
 958
 959                 ptype = mini_get_underlying_type (sig->params [i]);
 960                 switch (ptype->type) {
 961                 case MONO_TYPE_I1:
 962                 case MONO_TYPE_U1:
 963                         add_general (&gr, &stack_size, ainfo);
 964                         break;
 965                 case MONO_TYPE_I2:
 966                 case MONO_TYPE_U2:
 967                         add_general (&gr, &stack_size, ainfo);
 968                         break;
 969                 case MONO_TYPE_I4:
 970                 case MONO_TYPE_U4:
 971                         add_general (&gr, &stack_size, ainfo);
 972                         break;
 973                 case MONO_TYPE_I:
 974                 case MONO_TYPE_U:
 975                 case MONO_TYPE_PTR:
 976                 case MONO_TYPE_FNPTR:
 977                 case MONO_TYPE_CLASS:
 978                 case MONO_TYPE_OBJECT:
 979                 case MONO_TYPE_STRING:
 980                 case MONO_TYPE_SZARRAY:
 981                 case MONO_TYPE_ARRAY:
 982                         add_general (&gr, &stack_size, ainfo);
 983                         break;
 984                 case MONO_TYPE_GENERICINST:
 985                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 986                                 add_general (&gr, &stack_size, ainfo);
 987                                 break;
 988                         }
 989                         if (mini_is_gsharedvt_variable_type (ptype)) {
 990                                 /* gsharedvt arguments are passed by ref */
 991                                 add_general (&gr, &stack_size, ainfo);
 992                                 if (ainfo->storage == ArgInIReg)
 993                                         ainfo->storage = ArgGSharedVtInReg;
 994                                 else
 995                                         ainfo->storage = ArgGSharedVtOnStack;
 996                                 break;
 997                         }
 998                         /* fall through */
 999                 case MONO_TYPE_VALUETYPE:
1000                 case MONO_TYPE_TYPEDBYREF:
1001                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1002                         break;
1003                 case MONO_TYPE_U8:
1004
1005                 case MONO_TYPE_I8:
1006                         add_general (&gr, &stack_size, ainfo);
1007                         break;
1008                 case MONO_TYPE_R4:
1009                         add_float (&fr, &stack_size, ainfo, FALSE);
1010                         break;
1011                 case MONO_TYPE_R8:
1012                         add_float (&fr, &stack_size, ainfo, TRUE);
1013                         break;
1014                 case MONO_TYPE_VAR:
1015                 case MONO_TYPE_MVAR:
1016                         /* gsharedvt arguments are passed by ref */
1017                         g_assert (mini_is_gsharedvt_type (ptype));
1018                         add_general (&gr, &stack_size, ainfo);
1019                         if (ainfo->storage == ArgInIReg)
1020                                 ainfo->storage = ArgGSharedVtInReg;
1021                         else
1022                                 ainfo->storage = ArgGSharedVtOnStack;
1023                         break;
1024                 default:
1025                         g_assert_not_reached ();
1026                 }
1027         }
1028
1029         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1030                 gr = PARAM_REGS;
1031                 fr = FLOAT_PARAM_REGS;
1032
1033                 /* Emit the signature cookie just before the implicit arguments */
1034                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1035         }
1036
1037         cinfo->stack_usage = stack_size;
1038         cinfo->reg_usage = gr;
1039         cinfo->freg_usage = fr;
1040         return cinfo;
1041 }
1042
1043 /*
1044  * mono_arch_get_argument_info:
1045  * @csig:  a method signature
1046  * @param_count: the number of parameters to consider
1047  * @arg_info: an array to store the result infos
1048  *
1049  * Gathers information on parameters such as size, alignment and
1050  * padding. arg_info should be large enought to hold param_count + 1 entries.
1051  *
1052  * Returns the size of the argument area on the stack.
1053  */
1054 int
1055 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1056 {
1057         int k;
1058         CallInfo *cinfo = get_call_info (NULL, csig);
1059         guint32 args_size = cinfo->stack_usage;
1060
1061         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1062         if (csig->hasthis) {
1063                 arg_info [0].offset = 0;
1064         }
1065
1066         for (k = 0; k < param_count; k++) {
1067                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1068                 /* FIXME: */
1069                 arg_info [k + 1].size = 0;
1070         }
1071
1072         g_free (cinfo);
1073
1074         return args_size;
1075 }
1076
1077 gboolean
1078 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1079 {
1080         CallInfo *c1, *c2;
1081         gboolean res;
1082         MonoType *callee_ret;
1083
1084         c1 = get_call_info (NULL, caller_sig);
1085         c2 = get_call_info (NULL, callee_sig);
1086         res = c1->stack_usage >= c2->stack_usage;
1087         callee_ret = mini_get_underlying_type (callee_sig->ret);
1088         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1089                 /* An address on the callee's stack is passed as the first argument */
1090                 res = FALSE;
1091
1092         g_free (c1);
1093         g_free (c2);
1094
1095         return res;
1096 }
1097
1098 /*
1099  * Initialize the cpu to execute managed code.
1100  */
1101 void
1102 mono_arch_cpu_init (void)
1103 {
1104 #ifndef _MSC_VER
1105         guint16 fpcw;
1106
1107         /* spec compliance requires running with double precision */
1108         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1109         fpcw &= ~X86_FPCW_PRECC_MASK;
1110         fpcw |= X86_FPCW_PREC_DOUBLE;
1111         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1112         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1113 #else
1114         /* TODO: This is crashing on Win64 right now.
1115         * _control87 (_PC_53, MCW_PC);
1116         */
1117 #endif
1118 }
1119
1120 /*
1121  * Initialize architecture specific code.
1122  */
1123 void
1124 mono_arch_init (void)
1125 {
1126         mono_os_mutex_init_recursive (&mini_arch_mutex);
1127
1128         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1129         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1130         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1131         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1132 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1133         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1134 #endif
1135
1136         if (!mono_aot_only)
1137                 bp_trampoline = mini_get_breakpoint_trampoline ();
1138 }
1139
1140 /*
1141  * Cleanup architecture specific code.
1142  */
1143 void
1144 mono_arch_cleanup (void)
1145 {
1146         mono_os_mutex_destroy (&mini_arch_mutex);
1147 }
1148
1149 /*
1150  * This function returns the optimizations supported on this cpu.
1151  */
1152 guint32
1153 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1154 {
1155         guint32 opts = 0;
1156
1157         *exclude_mask = 0;
1158
1159         if (mono_hwcap_x86_has_cmov) {
1160                 opts |= MONO_OPT_CMOV;
1161
1162                 if (mono_hwcap_x86_has_fcmov)
1163                         opts |= MONO_OPT_FCMOV;
1164                 else
1165                         *exclude_mask |= MONO_OPT_FCMOV;
1166         } else {
1167                 *exclude_mask |= MONO_OPT_CMOV;
1168         }
1169
1170         return opts;
1171 }
1172
1173 /*
1174  * This function test for all SSE functions supported.
1175  *
1176  * Returns a bitmask corresponding to all supported versions.
1177  *
1178  */
1179 guint32
1180 mono_arch_cpu_enumerate_simd_versions (void)
1181 {
1182         guint32 sse_opts = 0;
1183
1184         if (mono_hwcap_x86_has_sse1)
1185                 sse_opts |= SIMD_VERSION_SSE1;
1186
1187         if (mono_hwcap_x86_has_sse2)
1188                 sse_opts |= SIMD_VERSION_SSE2;
1189
1190         if (mono_hwcap_x86_has_sse3)
1191                 sse_opts |= SIMD_VERSION_SSE3;
1192
1193         if (mono_hwcap_x86_has_ssse3)
1194                 sse_opts |= SIMD_VERSION_SSSE3;
1195
1196         if (mono_hwcap_x86_has_sse41)
1197                 sse_opts |= SIMD_VERSION_SSE41;
1198
1199         if (mono_hwcap_x86_has_sse42)
1200                 sse_opts |= SIMD_VERSION_SSE42;
1201
1202         if (mono_hwcap_x86_has_sse4a)
1203                 sse_opts |= SIMD_VERSION_SSE4a;
1204
1205         return sse_opts;
1206 }
1207
1208 #ifndef DISABLE_JIT
1209
1210 GList *
1211 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1212 {
1213         GList *vars = NULL;
1214         int i;
1215
1216         for (i = 0; i < cfg->num_varinfo; i++) {
1217                 MonoInst *ins = cfg->varinfo [i];
1218                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1219
1220                 /* unused vars */
1221                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1222                         continue;
1223
1224                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1225                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1226                         continue;
1227
1228                 if (mono_is_regsize_var (ins->inst_vtype)) {
1229                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1230                         g_assert (i == vmv->idx);
1231                         vars = g_list_prepend (vars, vmv);
1232                 }
1233         }
1234
1235         vars = mono_varlist_sort (cfg, vars, 0);
1236
1237         return vars;
1238 }
1239
1240 /**
1241  * mono_arch_compute_omit_fp:
1242  *
1243  *   Determine whenever the frame pointer can be eliminated.
1244  */
1245 static void
1246 mono_arch_compute_omit_fp (MonoCompile *cfg)
1247 {
1248         MonoMethodSignature *sig;
1249         MonoMethodHeader *header;
1250         int i, locals_size;
1251         CallInfo *cinfo;
1252
1253         if (cfg->arch.omit_fp_computed)
1254                 return;
1255
1256         header = cfg->header;
1257
1258         sig = mono_method_signature (cfg->method);
1259
1260         if (!cfg->arch.cinfo)
1261                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1262         cinfo = (CallInfo *)cfg->arch.cinfo;
1263
1264         /*
1265          * FIXME: Remove some of the restrictions.
1266          */
1267         cfg->arch.omit_fp = TRUE;
1268         cfg->arch.omit_fp_computed = TRUE;
1269
1270         if (cfg->disable_omit_fp)
1271                 cfg->arch.omit_fp = FALSE;
1272
1273         if (!debug_omit_fp ())
1274                 cfg->arch.omit_fp = FALSE;
1275         /*
1276         if (cfg->method->save_lmf)
1277                 cfg->arch.omit_fp = FALSE;
1278         */
1279         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1280                 cfg->arch.omit_fp = FALSE;
1281         if (header->num_clauses)
1282                 cfg->arch.omit_fp = FALSE;
1283         if (cfg->param_area)
1284                 cfg->arch.omit_fp = FALSE;
1285         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1286                 cfg->arch.omit_fp = FALSE;
1287         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1288                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1289                 cfg->arch.omit_fp = FALSE;
1290         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1291                 ArgInfo *ainfo = &cinfo->args [i];
1292
1293                 if (ainfo->storage == ArgOnStack) {
1294                         /*
1295                          * The stack offset can only be determined when the frame
1296                          * size is known.
1297                          */
1298                         cfg->arch.omit_fp = FALSE;
1299                 }
1300         }
1301
1302         locals_size = 0;
1303         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1304                 MonoInst *ins = cfg->varinfo [i];
1305                 int ialign;
1306
1307                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1308         }
1309 }
1310
1311 GList *
1312 mono_arch_get_global_int_regs (MonoCompile *cfg)
1313 {
1314         GList *regs = NULL;
1315
1316         mono_arch_compute_omit_fp (cfg);
1317
1318         if (cfg->arch.omit_fp)
1319                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1320
1321         /* We use the callee saved registers for global allocation */
1322         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1323         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1324         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1325         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1326         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1327 #ifdef TARGET_WIN32
1328         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1329         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1330 #endif
1331
1332         return regs;
1333 }
1334
1335 GList*
1336 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1337 {
1338         GList *regs = NULL;
1339         int i;
1340
1341         /* All XMM registers */
1342         for (i = 0; i < 16; ++i)
1343                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1344
1345         return regs;
1346 }
1347
1348 GList*
1349 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1350 {
1351         static GList *r = NULL;
1352
1353         if (r == NULL) {
1354                 GList *regs = NULL;
1355
1356                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1357                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1358                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1359                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1360                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1361                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1362
1363                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1364                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1365                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1366                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1367                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1368                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1369                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1370                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1371
1372                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1373         }
1374
1375         return r;
1376 }
1377
1378 GList*
1379 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1380 {
1381         int i;
1382         static GList *r = NULL;
1383
1384         if (r == NULL) {
1385                 GList *regs = NULL;
1386
1387                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1388                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1389
1390                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1391         }
1392
1393         return r;
1394 }
1395
1396 /*
1397  * mono_arch_regalloc_cost:
1398  *
1399  *  Return the cost, in number of memory references, of the action of
1400  * allocating the variable VMV into a register during global register
1401  * allocation.
1402  */
1403 guint32
1404 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1405 {
1406         MonoInst *ins = cfg->varinfo [vmv->idx];
1407
1408         if (cfg->method->save_lmf)
1409                 /* The register is already saved */
1410                 /* substract 1 for the invisible store in the prolog */
1411                 return (ins->opcode == OP_ARG) ? 0 : 1;
1412         else
1413                 /* push+pop */
1414                 return (ins->opcode == OP_ARG) ? 1 : 2;
1415 }
1416
1417 /*
1418  * mono_arch_fill_argument_info:
1419  *
1420  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1421  * of the method.
1422  */
1423 void
1424 mono_arch_fill_argument_info (MonoCompile *cfg)
1425 {
1426         MonoType *sig_ret;
1427         MonoMethodSignature *sig;
1428         MonoInst *ins;
1429         int i;
1430         CallInfo *cinfo;
1431
1432         sig = mono_method_signature (cfg->method);
1433
1434         cinfo = (CallInfo *)cfg->arch.cinfo;
1435         sig_ret = mini_get_underlying_type (sig->ret);
1436
1437         /*
1438          * Contrary to mono_arch_allocate_vars (), the information should describe
1439          * where the arguments are at the beginning of the method, not where they can be
1440          * accessed during the execution of the method. The later makes no sense for the
1441          * global register allocator, since a variable can be in more than one location.
1442          */
1443         switch (cinfo->ret.storage) {
1444         case ArgInIReg:
1445         case ArgInFloatSSEReg:
1446         case ArgInDoubleSSEReg:
1447                 cfg->ret->opcode = OP_REGVAR;
1448                 cfg->ret->inst_c0 = cinfo->ret.reg;
1449                 break;
1450         case ArgValuetypeInReg:
1451                 cfg->ret->opcode = OP_REGOFFSET;
1452                 cfg->ret->inst_basereg = -1;
1453                 cfg->ret->inst_offset = -1;
1454                 break;
1455         case ArgNone:
1456                 break;
1457         default:
1458                 g_assert_not_reached ();
1459         }
1460
1461         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1462                 ArgInfo *ainfo = &cinfo->args [i];
1463
1464                 ins = cfg->args [i];
1465
1466                 switch (ainfo->storage) {
1467                 case ArgInIReg:
1468                 case ArgInFloatSSEReg:
1469                 case ArgInDoubleSSEReg:
1470                         ins->opcode = OP_REGVAR;
1471                         ins->inst_c0 = ainfo->reg;
1472                         break;
1473                 case ArgOnStack:
1474                         ins->opcode = OP_REGOFFSET;
1475                         ins->inst_basereg = -1;
1476                         ins->inst_offset = -1;
1477                         break;
1478                 case ArgValuetypeInReg:
1479                         /* Dummy */
1480                         ins->opcode = OP_NOP;
1481                         break;
1482                 default:
1483                         g_assert_not_reached ();
1484                 }
1485         }
1486 }
1487
1488 void
1489 mono_arch_allocate_vars (MonoCompile *cfg)
1490 {
1491         MonoType *sig_ret;
1492         MonoMethodSignature *sig;
1493         MonoInst *ins;
1494         int i, offset;
1495         guint32 locals_stack_size, locals_stack_align;
1496         gint32 *offsets;
1497         CallInfo *cinfo;
1498
1499         sig = mono_method_signature (cfg->method);
1500
1501         cinfo = (CallInfo *)cfg->arch.cinfo;
1502         sig_ret = mini_get_underlying_type (sig->ret);
1503
1504         mono_arch_compute_omit_fp (cfg);
1505
1506         /*
1507          * We use the ABI calling conventions for managed code as well.
1508          * Exception: valuetypes are only sometimes passed or returned in registers.
1509          */
1510
1511         /*
1512          * The stack looks like this:
1513          * <incoming arguments passed on the stack>
1514          * <return value>
1515          * <lmf/caller saved registers>
1516          * <locals>
1517          * <spill area>
1518          * <localloc area>  -> grows dynamically
1519          * <params area>
1520          */
1521
1522         if (cfg->arch.omit_fp) {
1523                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1524                 cfg->frame_reg = AMD64_RSP;
1525                 offset = 0;
1526         } else {
1527                 /* Locals are allocated backwards from %fp */
1528                 cfg->frame_reg = AMD64_RBP;
1529                 offset = 0;
1530         }
1531
1532         cfg->arch.saved_iregs = cfg->used_int_regs;
1533         if (cfg->method->save_lmf)
1534                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1535                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1536
1537         if (cfg->arch.omit_fp)
1538                 cfg->arch.reg_save_area_offset = offset;
1539         /* Reserve space for callee saved registers */
1540         for (i = 0; i < AMD64_NREG; ++i)
1541                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1542                         offset += sizeof(mgreg_t);
1543                 }
1544         if (!cfg->arch.omit_fp)
1545                 cfg->arch.reg_save_area_offset = -offset;
1546
1547         if (sig_ret->type != MONO_TYPE_VOID) {
1548                 switch (cinfo->ret.storage) {
1549                 case ArgInIReg:
1550                 case ArgInFloatSSEReg:
1551                 case ArgInDoubleSSEReg:
1552                         cfg->ret->opcode = OP_REGVAR;
1553                         cfg->ret->inst_c0 = cinfo->ret.reg;
1554                         cfg->ret->dreg = cinfo->ret.reg;
1555                         break;
1556                 case ArgValuetypeAddrInIReg:
1557                 case ArgGsharedvtVariableInReg:
1558                         /* The register is volatile */
1559                         cfg->vret_addr->opcode = OP_REGOFFSET;
1560                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1561                         if (cfg->arch.omit_fp) {
1562                                 cfg->vret_addr->inst_offset = offset;
1563                                 offset += 8;
1564                         } else {
1565                                 offset += 8;
1566                                 cfg->vret_addr->inst_offset = -offset;
1567                         }
1568                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1569                                 printf ("vret_addr =");
1570                                 mono_print_ins (cfg->vret_addr);
1571                         }
1572                         break;
1573                 case ArgValuetypeInReg:
1574                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1575                         cfg->ret->opcode = OP_REGOFFSET;
1576                         cfg->ret->inst_basereg = cfg->frame_reg;
1577                         if (cfg->arch.omit_fp) {
1578                                 cfg->ret->inst_offset = offset;
1579                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1580                         } else {
1581                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1582                                 cfg->ret->inst_offset = - offset;
1583                         }
1584                         break;
1585                 default:
1586                         g_assert_not_reached ();
1587                 }
1588         }
1589
1590         /* Allocate locals */
1591         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1592         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1593                 char *mname = mono_method_full_name (cfg->method, TRUE);
1594                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1595                 g_free (mname);
1596                 return;
1597         }
1598
1599         if (locals_stack_align) {
1600                 offset += (locals_stack_align - 1);
1601                 offset &= ~(locals_stack_align - 1);
1602         }
1603         if (cfg->arch.omit_fp) {
1604                 cfg->locals_min_stack_offset = offset;
1605                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1606         } else {
1607                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1608                 cfg->locals_max_stack_offset = - offset;
1609         }
1610
1611         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1612                 if (offsets [i] != -1) {
1613                         MonoInst *ins = cfg->varinfo [i];
1614                         ins->opcode = OP_REGOFFSET;
1615                         ins->inst_basereg = cfg->frame_reg;
1616                         if (cfg->arch.omit_fp)
1617                                 ins->inst_offset = (offset + offsets [i]);
1618                         else
1619                                 ins->inst_offset = - (offset + offsets [i]);
1620                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1621                 }
1622         }
1623         offset += locals_stack_size;
1624
1625         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1626                 g_assert (!cfg->arch.omit_fp);
1627                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1628                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1629         }
1630
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ins = cfg->args [i];
1633                 if (ins->opcode != OP_REGVAR) {
1634                         ArgInfo *ainfo = &cinfo->args [i];
1635                         gboolean inreg = TRUE;
1636
1637                         /* FIXME: Allocate volatile arguments to registers */
1638                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1639                                 inreg = FALSE;
1640
1641                         /*
1642                          * Under AMD64, all registers used to pass arguments to functions
1643                          * are volatile across calls.
1644                          * FIXME: Optimize this.
1645                          */
1646                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1647                                 inreg = FALSE;
1648
1649                         ins->opcode = OP_REGOFFSET;
1650
1651                         switch (ainfo->storage) {
1652                         case ArgInIReg:
1653                         case ArgInFloatSSEReg:
1654                         case ArgInDoubleSSEReg:
1655                         case ArgGSharedVtInReg:
1656                                 if (inreg) {
1657                                         ins->opcode = OP_REGVAR;
1658                                         ins->dreg = ainfo->reg;
1659                                 }
1660                                 break;
1661                         case ArgOnStack:
1662                         case ArgGSharedVtOnStack:
1663                                 g_assert (!cfg->arch.omit_fp);
1664                                 ins->opcode = OP_REGOFFSET;
1665                                 ins->inst_basereg = cfg->frame_reg;
1666                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1667                                 break;
1668                         case ArgValuetypeInReg:
1669                                 break;
1670                         case ArgValuetypeAddrInIReg: {
1671                                 MonoInst *indir;
1672                                 g_assert (!cfg->arch.omit_fp);
1673
1674                                 MONO_INST_NEW (cfg, indir, 0);
1675                                 indir->opcode = OP_REGOFFSET;
1676                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1677                                         indir->inst_basereg = cfg->frame_reg;
1678                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1679                                         offset += (sizeof (gpointer));
1680                                         indir->inst_offset = - offset;
1681                                 }
1682                                 else {
1683                                         indir->inst_basereg = cfg->frame_reg;
1684                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1685                                 }
1686
1687                                 ins->opcode = OP_VTARG_ADDR;
1688                                 ins->inst_left = indir;
1689
1690                                 break;
1691                         }
1692                         default:
1693                                 NOT_IMPLEMENTED;
1694                         }
1695
1696                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
1697                                 ins->opcode = OP_REGOFFSET;
1698                                 ins->inst_basereg = cfg->frame_reg;
1699                                 /* These arguments are saved to the stack in the prolog */
1700                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1701                                 if (cfg->arch.omit_fp) {
1702                                         ins->inst_offset = offset;
1703                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1704                                         // Arguments are yet supported by the stack map creation code
1705                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1706                                 } else {
1707                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1708                                         ins->inst_offset = - offset;
1709                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1710                                 }
1711                         }
1712                 }
1713         }
1714
1715         cfg->stack_offset = offset;
1716 }
1717
1718 void
1719 mono_arch_create_vars (MonoCompile *cfg)
1720 {
1721         MonoMethodSignature *sig;
1722         CallInfo *cinfo;
1723         MonoType *sig_ret;
1724
1725         sig = mono_method_signature (cfg->method);
1726
1727         if (!cfg->arch.cinfo)
1728                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1729         cinfo = (CallInfo *)cfg->arch.cinfo;
1730
1731         if (cinfo->ret.storage == ArgValuetypeInReg)
1732                 cfg->ret_var_is_local = TRUE;
1733
1734         sig_ret = mini_get_underlying_type (sig->ret);
1735         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1736                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1737                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1738                         printf ("vret_addr = ");
1739                         mono_print_ins (cfg->vret_addr);
1740                 }
1741         }
1742
1743         if (cfg->gen_sdb_seq_points) {
1744                 MonoInst *ins;
1745
1746                 if (cfg->compile_aot) {
1747                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1748                         ins->flags |= MONO_INST_VOLATILE;
1749                         cfg->arch.seq_point_info_var = ins;
1750                 }
1751                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1752                 ins->flags |= MONO_INST_VOLATILE;
1753                 cfg->arch.ss_tramp_var = ins;
1754
1755                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1756                 ins->flags |= MONO_INST_VOLATILE;
1757                 cfg->arch.bp_tramp_var = ins;
1758         }
1759
1760         if (cfg->method->save_lmf)
1761                 cfg->create_lmf_var = TRUE;
1762
1763         if (cfg->method->save_lmf) {
1764                 cfg->lmf_ir = TRUE;
1765 #if !defined(TARGET_WIN32)
1766                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1767                         cfg->lmf_ir_mono_lmf = TRUE;
1768 #endif
1769         }
1770 }
1771
1772 static void
1773 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1774 {
1775         MonoInst *ins;
1776
1777         switch (storage) {
1778         case ArgInIReg:
1779                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1780                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1781                 ins->sreg1 = tree->dreg;
1782                 MONO_ADD_INS (cfg->cbb, ins);
1783                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1784                 break;
1785         case ArgInFloatSSEReg:
1786                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1787                 ins->dreg = mono_alloc_freg (cfg);
1788                 ins->sreg1 = tree->dreg;
1789                 MONO_ADD_INS (cfg->cbb, ins);
1790
1791                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1792                 break;
1793         case ArgInDoubleSSEReg:
1794                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1795                 ins->dreg = mono_alloc_freg (cfg);
1796                 ins->sreg1 = tree->dreg;
1797                 MONO_ADD_INS (cfg->cbb, ins);
1798
1799                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1800
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805 }
1806
1807 static int
1808 arg_storage_to_load_membase (ArgStorage storage)
1809 {
1810         switch (storage) {
1811         case ArgInIReg:
1812 #if defined(__mono_ilp32__)
1813                 return OP_LOADI8_MEMBASE;
1814 #else
1815                 return OP_LOAD_MEMBASE;
1816 #endif
1817         case ArgInDoubleSSEReg:
1818                 return OP_LOADR8_MEMBASE;
1819         case ArgInFloatSSEReg:
1820                 return OP_LOADR4_MEMBASE;
1821         default:
1822                 g_assert_not_reached ();
1823         }
1824
1825         return -1;
1826 }
1827
1828 static void
1829 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1830 {
1831         MonoMethodSignature *tmp_sig;
1832         int sig_reg;
1833
1834         if (call->tail_call)
1835                 NOT_IMPLEMENTED;
1836
1837         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1838
1839         /*
1840          * mono_ArgIterator_Setup assumes the signature cookie is
1841          * passed first and all the arguments which were before it are
1842          * passed on the stack after the signature. So compensate by
1843          * passing a different signature.
1844          */
1845         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1846         tmp_sig->param_count -= call->signature->sentinelpos;
1847         tmp_sig->sentinelpos = 0;
1848         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1849
1850         sig_reg = mono_alloc_ireg (cfg);
1851         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1852
1853         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1854 }
1855
1856 #ifdef ENABLE_LLVM
1857 static inline LLVMArgStorage
1858 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1859 {
1860         switch (storage) {
1861         case ArgInIReg:
1862                 return LLVMArgInIReg;
1863         case ArgNone:
1864                 return LLVMArgNone;
1865         case ArgGSharedVtInReg:
1866         case ArgGSharedVtOnStack:
1867                 return LLVMArgGSharedVt;
1868         default:
1869                 g_assert_not_reached ();
1870                 return LLVMArgNone;
1871         }
1872 }
1873
1874 LLVMCallInfo*
1875 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1876 {
1877         int i, n;
1878         CallInfo *cinfo;
1879         ArgInfo *ainfo;
1880         int j;
1881         LLVMCallInfo *linfo;
1882         MonoType *t, *sig_ret;
1883
1884         n = sig->param_count + sig->hasthis;
1885         sig_ret = mini_get_underlying_type (sig->ret);
1886
1887         cinfo = get_call_info (cfg->mempool, sig);
1888
1889         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1890
1891         /*
1892          * LLVM always uses the native ABI while we use our own ABI, the
1893          * only difference is the handling of vtypes:
1894          * - we only pass/receive them in registers in some cases, and only
1895          *   in 1 or 2 integer registers.
1896          */
1897         switch (cinfo->ret.storage) {
1898         case ArgNone:
1899                 linfo->ret.storage = LLVMArgNone;
1900                 break;
1901         case ArgInIReg:
1902         case ArgInFloatSSEReg:
1903         case ArgInDoubleSSEReg:
1904                 linfo->ret.storage = LLVMArgNormal;
1905                 break;
1906         case ArgValuetypeInReg: {
1907                 ainfo = &cinfo->ret;
1908
1909                 if (sig->pinvoke &&
1910                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1911                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1912                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1913                         cfg->disable_llvm = TRUE;
1914                         return linfo;
1915                 }
1916
1917                 linfo->ret.storage = LLVMArgVtypeInReg;
1918                 for (j = 0; j < 2; ++j)
1919                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1920                 break;
1921         }
1922         case ArgValuetypeAddrInIReg:
1923         case ArgGsharedvtVariableInReg:
1924                 /* Vtype returned using a hidden argument */
1925                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1926                 linfo->vret_arg_index = cinfo->vret_arg_index;
1927                 break;
1928         default:
1929                 g_assert_not_reached ();
1930                 break;
1931         }
1932
1933         for (i = 0; i < n; ++i) {
1934                 ainfo = cinfo->args + i;
1935
1936                 if (i >= sig->hasthis)
1937                         t = sig->params [i - sig->hasthis];
1938                 else
1939                         t = &mono_defaults.int_class->byval_arg;
1940
1941                 linfo->args [i].storage = LLVMArgNone;
1942
1943                 switch (ainfo->storage) {
1944                 case ArgInIReg:
1945                         linfo->args [i].storage = LLVMArgNormal;
1946                         break;
1947                 case ArgInDoubleSSEReg:
1948                 case ArgInFloatSSEReg:
1949                         linfo->args [i].storage = LLVMArgNormal;
1950                         break;
1951                 case ArgOnStack:
1952                         if (MONO_TYPE_ISSTRUCT (t))
1953                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1954                         else
1955                                 linfo->args [i].storage = LLVMArgNormal;
1956                         break;
1957                 case ArgValuetypeInReg:
1958                         if (sig->pinvoke &&
1959                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1960                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1961                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1962                                 cfg->disable_llvm = TRUE;
1963                                 return linfo;
1964                         }
1965
1966                         linfo->args [i].storage = LLVMArgVtypeInReg;
1967                         for (j = 0; j < 2; ++j)
1968                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1969                         break;
1970                 case ArgGSharedVtInReg:
1971                 case ArgGSharedVtOnStack:
1972                         linfo->args [i].storage = LLVMArgGSharedVt;
1973                         break;
1974                 default:
1975                         cfg->exception_message = g_strdup ("ainfo->storage");
1976                         cfg->disable_llvm = TRUE;
1977                         break;
1978                 }
1979         }
1980
1981         return linfo;
1982 }
1983 #endif
1984
1985 void
1986 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1987 {
1988         MonoInst *arg, *in;
1989         MonoMethodSignature *sig;
1990         MonoType *sig_ret;
1991         int i, n;
1992         CallInfo *cinfo;
1993         ArgInfo *ainfo;
1994
1995         sig = call->signature;
1996         n = sig->param_count + sig->hasthis;
1997
1998         cinfo = get_call_info (cfg->mempool, sig);
1999
2000         sig_ret = sig->ret;
2001
2002         if (COMPILE_LLVM (cfg)) {
2003                 /* We shouldn't be called in the llvm case */
2004                 cfg->disable_llvm = TRUE;
2005                 return;
2006         }
2007
2008         /*
2009          * Emit all arguments which are passed on the stack to prevent register
2010          * allocation problems.
2011          */
2012         for (i = 0; i < n; ++i) {
2013                 MonoType *t;
2014                 ainfo = cinfo->args + i;
2015
2016                 in = call->args [i];
2017
2018                 if (sig->hasthis && i == 0)
2019                         t = &mono_defaults.object_class->byval_arg;
2020                 else
2021                         t = sig->params [i - sig->hasthis];
2022
2023                 t = mini_get_underlying_type (t);
2024                 //XXX what about ArgGSharedVtOnStack here?
2025                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2026                         if (!t->byref) {
2027                                 if (t->type == MONO_TYPE_R4)
2028                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2029                                 else if (t->type == MONO_TYPE_R8)
2030                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2031                                 else
2032                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2033                         } else {
2034                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2035                         }
2036                         if (cfg->compute_gc_maps) {
2037                                 MonoInst *def;
2038
2039                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2040                         }
2041                 }
2042         }
2043
2044         /*
2045          * Emit all parameters passed in registers in non-reverse order for better readability
2046          * and to help the optimization in emit_prolog ().
2047          */
2048         for (i = 0; i < n; ++i) {
2049                 ainfo = cinfo->args + i;
2050
2051                 in = call->args [i];
2052
2053                 if (ainfo->storage == ArgInIReg)
2054                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2055         }
2056
2057         for (i = n - 1; i >= 0; --i) {
2058                 MonoType *t;
2059
2060                 ainfo = cinfo->args + i;
2061
2062                 in = call->args [i];
2063
2064                 if (sig->hasthis && i == 0)
2065                         t = &mono_defaults.object_class->byval_arg;
2066                 else
2067                         t = sig->params [i - sig->hasthis];
2068                 t = mini_get_underlying_type (t);
2069
2070                 switch (ainfo->storage) {
2071                 case ArgInIReg:
2072                         /* Already done */
2073                         break;
2074                 case ArgInFloatSSEReg:
2075                 case ArgInDoubleSSEReg:
2076                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2077                         break;
2078                 case ArgOnStack:
2079                 case ArgValuetypeInReg:
2080                 case ArgValuetypeAddrInIReg:
2081                 case ArgGSharedVtInReg:
2082                 case ArgGSharedVtOnStack: {
2083                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2084                                 /* Already emitted above */
2085                                 break;
2086                         //FIXME what about ArgGSharedVtOnStack ?
2087                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2088                                 MonoInst *call_inst = (MonoInst*)call;
2089                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2090                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2091                                 break;
2092                         }
2093
2094                         guint32 align;
2095                         guint32 size;
2096
2097                         if (sig->pinvoke)
2098                                 size = mono_type_native_stack_size (t, &align);
2099                         else {
2100                                 /*
2101                                  * Other backends use mono_type_stack_size (), but that
2102                                  * aligns the size to 8, which is larger than the size of
2103                                  * the source, leading to reads of invalid memory if the
2104                                  * source is at the end of address space.
2105                                  */
2106                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2107                         }
2108
2109                         if (size >= 10000) {
2110                                 /* Avoid asserts in emit_memcpy () */
2111                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2112                                 /* Continue normally */
2113                         }
2114
2115                         if (size > 0) {
2116                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2117                                 arg->sreg1 = in->dreg;
2118                                 arg->klass = mono_class_from_mono_type (t);
2119                                 arg->backend.size = size;
2120                                 arg->inst_p0 = call;
2121                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2122                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2123
2124                                 MONO_ADD_INS (cfg->cbb, arg);
2125                         }
2126                         break;
2127                 }
2128                 default:
2129                         g_assert_not_reached ();
2130                 }
2131
2132                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2133                         /* Emit the signature cookie just before the implicit arguments */
2134                         emit_sig_cookie (cfg, call, cinfo);
2135         }
2136
2137         /* Handle the case where there are no implicit arguments */
2138         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2139                 emit_sig_cookie (cfg, call, cinfo);
2140
2141         switch (cinfo->ret.storage) {
2142         case ArgValuetypeInReg:
2143                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2144                         /*
2145                          * Tell the JIT to use a more efficient calling convention: call using
2146                          * OP_CALL, compute the result location after the call, and save the
2147                          * result there.
2148                          */
2149                         call->vret_in_reg = TRUE;
2150                         /*
2151                          * Nullify the instruction computing the vret addr to enable
2152                          * future optimizations.
2153                          */
2154                         if (call->vret_var)
2155                                 NULLIFY_INS (call->vret_var);
2156                 } else {
2157                         if (call->tail_call)
2158                                 NOT_IMPLEMENTED;
2159                         /*
2160                          * The valuetype is in RAX:RDX after the call, need to be copied to
2161                          * the stack. Push the address here, so the call instruction can
2162                          * access it.
2163                          */
2164                         if (!cfg->arch.vret_addr_loc) {
2165                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2166                                 /* Prevent it from being register allocated or optimized away */
2167                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2168                         }
2169
2170                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2171                 }
2172                 break;
2173         case ArgValuetypeAddrInIReg:
2174         case ArgGsharedvtVariableInReg: {
2175                 MonoInst *vtarg;
2176                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2177                 vtarg->sreg1 = call->vret_var->dreg;
2178                 vtarg->dreg = mono_alloc_preg (cfg);
2179                 MONO_ADD_INS (cfg->cbb, vtarg);
2180
2181                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2182                 break;
2183         }
2184         default:
2185                 break;
2186         }
2187
2188         if (cfg->method->save_lmf) {
2189                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2190                 MONO_ADD_INS (cfg->cbb, arg);
2191         }
2192
2193         call->stack_usage = cinfo->stack_usage;
2194 }
2195
2196 void
2197 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2198 {
2199         MonoInst *arg;
2200         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2201         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2202         int size = ins->backend.size;
2203
2204         switch (ainfo->storage) {
2205         case ArgValuetypeInReg: {
2206                 MonoInst *load;
2207                 int part;
2208
2209                 for (part = 0; part < 2; ++part) {
2210                         if (ainfo->pair_storage [part] == ArgNone)
2211                                 continue;
2212
2213                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2214                         load->inst_basereg = src->dreg;
2215                         load->inst_offset = part * sizeof(mgreg_t);
2216
2217                         switch (ainfo->pair_storage [part]) {
2218                         case ArgInIReg:
2219                                 load->dreg = mono_alloc_ireg (cfg);
2220                                 break;
2221                         case ArgInDoubleSSEReg:
2222                         case ArgInFloatSSEReg:
2223                                 load->dreg = mono_alloc_freg (cfg);
2224                                 break;
2225                         default:
2226                                 g_assert_not_reached ();
2227                         }
2228                         MONO_ADD_INS (cfg->cbb, load);
2229
2230                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2231                 }
2232                 break;
2233         }
2234         case ArgValuetypeAddrInIReg: {
2235                 MonoInst *vtaddr, *load;
2236                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2237
2238                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2239                 cfg->has_indirection = TRUE;
2240                 load->inst_p0 = vtaddr;
2241                 vtaddr->flags |= MONO_INST_INDIRECT;
2242                 load->type = STACK_MP;
2243                 load->klass = vtaddr->klass;
2244                 load->dreg = mono_alloc_ireg (cfg);
2245                 MONO_ADD_INS (cfg->cbb, load);
2246                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2247
2248                 if (ainfo->pair_storage [0] == ArgInIReg) {
2249                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2250                         arg->dreg = mono_alloc_ireg (cfg);
2251                         arg->sreg1 = load->dreg;
2252                         arg->inst_imm = 0;
2253                         MONO_ADD_INS (cfg->cbb, arg);
2254                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2255                 } else {
2256                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2257                 }
2258                 break;
2259         }
2260         case ArgGSharedVtInReg:
2261                 /* Pass by addr */
2262                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2263                 break;
2264         case ArgGSharedVtOnStack:
2265                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2266                 break;
2267         default:
2268                 if (size == 8) {
2269                         int dreg = mono_alloc_ireg (cfg);
2270
2271                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2272                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2273                 } else if (size <= 40) {
2274                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2275                 } else {
2276                         // FIXME: Code growth
2277                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2278                 }
2279
2280                 if (cfg->compute_gc_maps) {
2281                         MonoInst *def;
2282                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2283                 }
2284         }
2285 }
2286
2287 void
2288 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2289 {
2290         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2291
2292         if (ret->type == MONO_TYPE_R4) {
2293                 if (COMPILE_LLVM (cfg))
2294                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2295                 else
2296                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2297                 return;
2298         } else if (ret->type == MONO_TYPE_R8) {
2299                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2300                 return;
2301         }
2302
2303         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2304 }
2305
2306 #endif /* DISABLE_JIT */
2307
2308 #define EMIT_COND_BRANCH(ins,cond,sign) \
2309         if (ins->inst_true_bb->native_offset) { \
2310                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2311         } else { \
2312                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2313                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2314             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2315                         x86_branch8 (code, cond, 0, sign); \
2316                 else \
2317                         x86_branch32 (code, cond, 0, sign); \
2318 }
2319
2320 typedef struct {
2321         MonoMethodSignature *sig;
2322         CallInfo *cinfo;
2323 } ArchDynCallInfo;
2324
2325 static gboolean
2326 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2327 {
2328         int i;
2329
2330         switch (cinfo->ret.storage) {
2331         case ArgNone:
2332         case ArgInIReg:
2333         case ArgInFloatSSEReg:
2334         case ArgInDoubleSSEReg:
2335                 break;
2336         case ArgValuetypeInReg: {
2337                 ArgInfo *ainfo = &cinfo->ret;
2338
2339                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2340                         return FALSE;
2341                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2342                         return FALSE;
2343                 break;
2344         }
2345         default:
2346                 return FALSE;
2347         }
2348
2349         for (i = 0; i < cinfo->nargs; ++i) {
2350                 ArgInfo *ainfo = &cinfo->args [i];
2351                 switch (ainfo->storage) {
2352                 case ArgInIReg:
2353                 case ArgInFloatSSEReg:
2354                 case ArgInDoubleSSEReg:
2355                         break;
2356                 case ArgValuetypeInReg:
2357                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2358                                 return FALSE;
2359                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2360                                 return FALSE;
2361                         break;
2362                 default:
2363                         return FALSE;
2364                 }
2365         }
2366
2367         return TRUE;
2368 }
2369
2370 /*
2371  * mono_arch_dyn_call_prepare:
2372  *
2373  *   Return a pointer to an arch-specific structure which contains information
2374  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2375  * supported for SIG.
2376  * This function is equivalent to ffi_prep_cif in libffi.
2377  */
2378 MonoDynCallInfo*
2379 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2380 {
2381         ArchDynCallInfo *info;
2382         CallInfo *cinfo;
2383
2384         cinfo = get_call_info (NULL, sig);
2385
2386         if (!dyn_call_supported (sig, cinfo)) {
2387                 g_free (cinfo);
2388                 return NULL;
2389         }
2390
2391         info = g_new0 (ArchDynCallInfo, 1);
2392         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2393         info->sig = sig;
2394         info->cinfo = cinfo;
2395
2396         return (MonoDynCallInfo*)info;
2397 }
2398
2399 /*
2400  * mono_arch_dyn_call_free:
2401  *
2402  *   Free a MonoDynCallInfo structure.
2403  */
2404 void
2405 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2406 {
2407         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2408
2409         g_free (ainfo->cinfo);
2410         g_free (ainfo);
2411 }
2412
2413 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2414 #define GREG_TO_PTR(greg) (gpointer)(greg)
2415
2416 /*
2417  * mono_arch_get_start_dyn_call:
2418  *
2419  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2420  * store the result into BUF.
2421  * ARGS should be an array of pointers pointing to the arguments.
2422  * RET should point to a memory buffer large enought to hold the result of the
2423  * call.
2424  * This function should be as fast as possible, any work which does not depend
2425  * on the actual values of the arguments should be done in
2426  * mono_arch_dyn_call_prepare ().
2427  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2428  * libffi.
2429  */
2430 void
2431 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2432 {
2433         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2434         DynCallArgs *p = (DynCallArgs*)buf;
2435         int arg_index, greg, freg, i, pindex;
2436         MonoMethodSignature *sig = dinfo->sig;
2437         int buffer_offset = 0;
2438
2439         g_assert (buf_len >= sizeof (DynCallArgs));
2440
2441         p->res = 0;
2442         p->ret = ret;
2443
2444         arg_index = 0;
2445         greg = 0;
2446         freg = 0;
2447         pindex = 0;
2448
2449         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2450                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2451                 if (!sig->hasthis)
2452                         pindex = 1;
2453         }
2454
2455         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2456                 p->regs [greg ++] = PTR_TO_GREG(ret);
2457
2458         for (i = pindex; i < sig->param_count; i++) {
2459                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2460                 gpointer *arg = args [arg_index ++];
2461
2462                 if (t->byref) {
2463                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2464                         continue;
2465                 }
2466
2467                 switch (t->type) {
2468                 case MONO_TYPE_STRING:
2469                 case MONO_TYPE_CLASS:
2470                 case MONO_TYPE_ARRAY:
2471                 case MONO_TYPE_SZARRAY:
2472                 case MONO_TYPE_OBJECT:
2473                 case MONO_TYPE_PTR:
2474                 case MONO_TYPE_I:
2475                 case MONO_TYPE_U:
2476 #if !defined(__mono_ilp32__)
2477                 case MONO_TYPE_I8:
2478                 case MONO_TYPE_U8:
2479 #endif
2480                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2481                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2482                         break;
2483 #if defined(__mono_ilp32__)
2484                 case MONO_TYPE_I8:
2485                 case MONO_TYPE_U8:
2486                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2487                         p->regs [greg ++] = *(guint64*)(arg);
2488                         break;
2489 #endif
2490                 case MONO_TYPE_U1:
2491                         p->regs [greg ++] = *(guint8*)(arg);
2492                         break;
2493                 case MONO_TYPE_I1:
2494                         p->regs [greg ++] = *(gint8*)(arg);
2495                         break;
2496                 case MONO_TYPE_I2:
2497                         p->regs [greg ++] = *(gint16*)(arg);
2498                         break;
2499                 case MONO_TYPE_U2:
2500                         p->regs [greg ++] = *(guint16*)(arg);
2501                         break;
2502                 case MONO_TYPE_I4:
2503                         p->regs [greg ++] = *(gint32*)(arg);
2504                         break;
2505                 case MONO_TYPE_U4:
2506                         p->regs [greg ++] = *(guint32*)(arg);
2507                         break;
2508                 case MONO_TYPE_R4: {
2509                         double d;
2510
2511                         *(float*)&d = *(float*)(arg);
2512                         p->has_fp = 1;
2513                         p->fregs [freg ++] = d;
2514                         break;
2515                 }
2516                 case MONO_TYPE_R8:
2517                         p->has_fp = 1;
2518                         p->fregs [freg ++] = *(double*)(arg);
2519                         break;
2520                 case MONO_TYPE_GENERICINST:
2521                     if (MONO_TYPE_IS_REFERENCE (t)) {
2522                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2523                                 break;
2524                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2525                                         MonoClass *klass = mono_class_from_mono_type (t);
2526                                         guint8 *nullable_buf;
2527                                         int size;
2528
2529                                         size = mono_class_value_size (klass, NULL);
2530                                         nullable_buf = p->buffer + buffer_offset;
2531                                         buffer_offset += size;
2532                                         g_assert (buffer_offset <= 256);
2533
2534                                         /* The argument pointed to by arg is either a boxed vtype or null */
2535                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2536
2537                                         arg = (gpointer*)nullable_buf;
2538                                         /* Fall though */
2539
2540                         } else {
2541                                 /* Fall through */
2542                         }
2543                 case MONO_TYPE_VALUETYPE: {
2544                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2545
2546                         g_assert (ainfo->storage == ArgValuetypeInReg);
2547                         if (ainfo->pair_storage [0] != ArgNone) {
2548                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2549                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2550                         }
2551                         if (ainfo->pair_storage [1] != ArgNone) {
2552                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2553                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2554                         }
2555                         break;
2556                 }
2557                 default:
2558                         g_assert_not_reached ();
2559                 }
2560         }
2561
2562         g_assert (greg <= PARAM_REGS);
2563 }
2564
2565 /*
2566  * mono_arch_finish_dyn_call:
2567  *
2568  *   Store the result of a dyn call into the return value buffer passed to
2569  * start_dyn_call ().
2570  * This function should be as fast as possible, any work which does not depend
2571  * on the actual values of the arguments should be done in
2572  * mono_arch_dyn_call_prepare ().
2573  */
2574 void
2575 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2576 {
2577         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2578         MonoMethodSignature *sig = dinfo->sig;
2579         DynCallArgs *dargs = (DynCallArgs*)buf;
2580         guint8 *ret = dargs->ret;
2581         mgreg_t res = dargs->res;
2582         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2583
2584         switch (sig_ret->type) {
2585         case MONO_TYPE_VOID:
2586                 *(gpointer*)ret = NULL;
2587                 break;
2588         case MONO_TYPE_STRING:
2589         case MONO_TYPE_CLASS:
2590         case MONO_TYPE_ARRAY:
2591         case MONO_TYPE_SZARRAY:
2592         case MONO_TYPE_OBJECT:
2593         case MONO_TYPE_I:
2594         case MONO_TYPE_U:
2595         case MONO_TYPE_PTR:
2596                 *(gpointer*)ret = GREG_TO_PTR(res);
2597                 break;
2598         case MONO_TYPE_I1:
2599                 *(gint8*)ret = res;
2600                 break;
2601         case MONO_TYPE_U1:
2602                 *(guint8*)ret = res;
2603                 break;
2604         case MONO_TYPE_I2:
2605                 *(gint16*)ret = res;
2606                 break;
2607         case MONO_TYPE_U2:
2608                 *(guint16*)ret = res;
2609                 break;
2610         case MONO_TYPE_I4:
2611                 *(gint32*)ret = res;
2612                 break;
2613         case MONO_TYPE_U4:
2614                 *(guint32*)ret = res;
2615                 break;
2616         case MONO_TYPE_I8:
2617                 *(gint64*)ret = res;
2618                 break;
2619         case MONO_TYPE_U8:
2620                 *(guint64*)ret = res;
2621                 break;
2622         case MONO_TYPE_R4:
2623                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2624                 break;
2625         case MONO_TYPE_R8:
2626                 *(double*)ret = dargs->fregs [0];
2627                 break;
2628         case MONO_TYPE_GENERICINST:
2629                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2630                         *(gpointer*)ret = GREG_TO_PTR(res);
2631                         break;
2632                 } else {
2633                         /* Fall through */
2634                 }
2635         case MONO_TYPE_VALUETYPE:
2636                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2637                         /* Nothing to do */
2638                 } else {
2639                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2640
2641                         g_assert (ainfo->storage == ArgValuetypeInReg);
2642
2643                         if (ainfo->pair_storage [0] != ArgNone) {
2644                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2645                                 ((mgreg_t*)ret)[0] = res;
2646                         }
2647
2648                         g_assert (ainfo->pair_storage [1] == ArgNone);
2649                 }
2650                 break;
2651         default:
2652                 g_assert_not_reached ();
2653         }
2654 }
2655
2656 /* emit an exception if condition is fail */
2657 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2658         do {                                                        \
2659                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2660                 if (tins == NULL) {                                                                             \
2661                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2662                                         MONO_PATCH_INFO_EXC, exc_name);  \
2663                         x86_branch32 (code, cond, 0, signed);               \
2664                 } else {        \
2665                         EMIT_COND_BRANCH (tins, cond, signed);  \
2666                 }                       \
2667         } while (0);
2668
2669 #define EMIT_FPCOMPARE(code) do { \
2670         amd64_fcompp (code); \
2671         amd64_fnstsw (code); \
2672 } while (0);
2673
2674 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2675     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2676         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2677         amd64_ ##op (code); \
2678         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2679         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2680 } while (0);
2681
2682 static guint8*
2683 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2684 {
2685         gboolean no_patch = FALSE;
2686
2687         /*
2688          * FIXME: Add support for thunks
2689          */
2690         {
2691                 gboolean near_call = FALSE;
2692
2693                 /*
2694                  * Indirect calls are expensive so try to make a near call if possible.
2695                  * The caller memory is allocated by the code manager so it is
2696                  * guaranteed to be at a 32 bit offset.
2697                  */
2698
2699                 if (patch_type != MONO_PATCH_INFO_ABS) {
2700                         /* The target is in memory allocated using the code manager */
2701                         near_call = TRUE;
2702
2703                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2704                                 if (((MonoMethod*)data)->klass->image->aot_module)
2705                                         /* The callee might be an AOT method */
2706                                         near_call = FALSE;
2707                                 if (((MonoMethod*)data)->dynamic)
2708                                         /* The target is in malloc-ed memory */
2709                                         near_call = FALSE;
2710                         }
2711
2712                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2713                                 /*
2714                                  * The call might go directly to a native function without
2715                                  * the wrapper.
2716                                  */
2717                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2718                                 if (mi) {
2719                                         gconstpointer target = mono_icall_get_wrapper (mi);
2720                                         if ((((guint64)target) >> 32) != 0)
2721                                                 near_call = FALSE;
2722                                 }
2723                         }
2724                 }
2725                 else {
2726                         MonoJumpInfo *jinfo = NULL;
2727
2728                         if (cfg->abs_patches)
2729                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2730                         if (jinfo) {
2731                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2732                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2733                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2734                                                 near_call = TRUE;
2735                                         no_patch = TRUE;
2736                                 } else {
2737                                         /*
2738                                          * This is not really an optimization, but required because the
2739                                          * generic class init trampolines use R11 to pass the vtable.
2740                                          */
2741                                         near_call = TRUE;
2742                                 }
2743                         } else {
2744                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2745                                 if (info) {
2746                                         if (info->func == info->wrapper) {
2747                                                 /* No wrapper */
2748                                                 if ((((guint64)info->func) >> 32) == 0)
2749                                                         near_call = TRUE;
2750                                         }
2751                                         else {
2752                                                 /* See the comment in mono_codegen () */
2753                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2754                                                         near_call = TRUE;
2755                                         }
2756                                 }
2757                                 else if ((((guint64)data) >> 32) == 0) {
2758                                         near_call = TRUE;
2759                                         no_patch = TRUE;
2760                                 }
2761                         }
2762                 }
2763
2764                 if (cfg->method->dynamic)
2765                         /* These methods are allocated using malloc */
2766                         near_call = FALSE;
2767
2768 #ifdef MONO_ARCH_NOMAP32BIT
2769                 near_call = FALSE;
2770 #endif
2771                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2772                 if (optimize_for_xen)
2773                         near_call = FALSE;
2774
2775                 if (cfg->compile_aot) {
2776                         near_call = TRUE;
2777                         no_patch = TRUE;
2778                 }
2779
2780                 if (near_call) {
2781                         /*
2782                          * Align the call displacement to an address divisible by 4 so it does
2783                          * not span cache lines. This is required for code patching to work on SMP
2784                          * systems.
2785                          */
2786                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2787                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2788                                 amd64_padding (code, pad_size);
2789                         }
2790                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2791                         amd64_call_code (code, 0);
2792                 }
2793                 else {
2794                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2795                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2796                         amd64_call_reg (code, GP_SCRATCH_REG);
2797                 }
2798         }
2799
2800         return code;
2801 }
2802
2803 static inline guint8*
2804 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2805 {
2806 #ifdef TARGET_WIN32
2807         if (win64_adjust_stack)
2808                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2809 #endif
2810         code = emit_call_body (cfg, code, patch_type, data);
2811 #ifdef TARGET_WIN32
2812         if (win64_adjust_stack)
2813                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2814 #endif
2815
2816         return code;
2817 }
2818
2819 static inline int
2820 store_membase_imm_to_store_membase_reg (int opcode)
2821 {
2822         switch (opcode) {
2823         case OP_STORE_MEMBASE_IMM:
2824                 return OP_STORE_MEMBASE_REG;
2825         case OP_STOREI4_MEMBASE_IMM:
2826                 return OP_STOREI4_MEMBASE_REG;
2827         case OP_STOREI8_MEMBASE_IMM:
2828                 return OP_STOREI8_MEMBASE_REG;
2829         }
2830
2831         return -1;
2832 }
2833
2834 #ifndef DISABLE_JIT
2835
2836 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2837
2838 /*
2839  * mono_arch_peephole_pass_1:
2840  *
2841  *   Perform peephole opts which should/can be performed before local regalloc
2842  */
2843 void
2844 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2845 {
2846         MonoInst *ins, *n;
2847
2848         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2849                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2850
2851                 switch (ins->opcode) {
2852                 case OP_ADD_IMM:
2853                 case OP_IADD_IMM:
2854                 case OP_LADD_IMM:
2855                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2856                                 /*
2857                                  * X86_LEA is like ADD, but doesn't have the
2858                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2859                                  * its operand to 64 bit.
2860                                  */
2861                                 ins->opcode = OP_X86_LEA_MEMBASE;
2862                                 ins->inst_basereg = ins->sreg1;
2863                         }
2864                         break;
2865                 case OP_LXOR:
2866                 case OP_IXOR:
2867                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2868                                 MonoInst *ins2;
2869
2870                                 /*
2871                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2872                                  * the latter has length 2-3 instead of 6 (reverse constant
2873                                  * propagation). These instruction sequences are very common
2874                                  * in the initlocals bblock.
2875                                  */
2876                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2877                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2878                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2879                                                 ins2->sreg1 = ins->dreg;
2880                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2881                                                 /* Continue */
2882                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2883                                                 NULLIFY_INS (ins2);
2884                                                 /* Continue */
2885                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2886                                                 /* Continue */
2887                                         } else {
2888                                                 break;
2889                                         }
2890                                 }
2891                         }
2892                         break;
2893                 case OP_COMPARE_IMM:
2894                 case OP_LCOMPARE_IMM:
2895                         /* OP_COMPARE_IMM (reg, 0)
2896                          * -->
2897                          * OP_AMD64_TEST_NULL (reg)
2898                          */
2899                         if (!ins->inst_imm)
2900                                 ins->opcode = OP_AMD64_TEST_NULL;
2901                         break;
2902                 case OP_ICOMPARE_IMM:
2903                         if (!ins->inst_imm)
2904                                 ins->opcode = OP_X86_TEST_NULL;
2905                         break;
2906                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2907                         /*
2908                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2909                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2910                          * -->
2911                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2912                          * OP_COMPARE_IMM reg, imm
2913                          *
2914                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2915                          */
2916                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2917                             ins->inst_basereg == last_ins->inst_destbasereg &&
2918                             ins->inst_offset == last_ins->inst_offset) {
2919                                         ins->opcode = OP_ICOMPARE_IMM;
2920                                         ins->sreg1 = last_ins->sreg1;
2921
2922                                         /* check if we can remove cmp reg,0 with test null */
2923                                         if (!ins->inst_imm)
2924                                                 ins->opcode = OP_X86_TEST_NULL;
2925                                 }
2926
2927                         break;
2928                 }
2929
2930                 mono_peephole_ins (bb, ins);
2931         }
2932 }
2933
2934 void
2935 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2936 {
2937         MonoInst *ins, *n;
2938
2939         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2940                 switch (ins->opcode) {
2941                 case OP_ICONST:
2942                 case OP_I8CONST: {
2943                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
2944                         /* reg = 0 -> XOR (reg, reg) */
2945                         /* XOR sets cflags on x86, so we cant do it always */
2946                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
2947                                 ins->opcode = OP_LXOR;
2948                                 ins->sreg1 = ins->dreg;
2949                                 ins->sreg2 = ins->dreg;
2950                                 /* Fall through */
2951                         } else {
2952                                 break;
2953                         }
2954                 }
2955                 case OP_LXOR:
2956                         /*
2957                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2958                          * 0 result into 64 bits.
2959                          */
2960                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2961                                 ins->opcode = OP_IXOR;
2962                         }
2963                         /* Fall through */
2964                 case OP_IXOR:
2965                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2966                                 MonoInst *ins2;
2967
2968                                 /*
2969                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2970                                  * the latter has length 2-3 instead of 6 (reverse constant
2971                                  * propagation). These instruction sequences are very common
2972                                  * in the initlocals bblock.
2973                                  */
2974                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2975                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2976                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2977                                                 ins2->sreg1 = ins->dreg;
2978                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
2979                                                 /* Continue */
2980                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2981                                                 NULLIFY_INS (ins2);
2982                                                 /* Continue */
2983                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2984                                                 /* Continue */
2985                                         } else {
2986                                                 break;
2987                                         }
2988                                 }
2989                         }
2990                         break;
2991                 case OP_IADD_IMM:
2992                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2993                                 ins->opcode = OP_X86_INC_REG;
2994                         break;
2995                 case OP_ISUB_IMM:
2996                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2997                                 ins->opcode = OP_X86_DEC_REG;
2998                         break;
2999                 }
3000
3001                 mono_peephole_ins (bb, ins);
3002         }
3003 }
3004
3005 #define NEW_INS(cfg,ins,dest,op) do {   \
3006                 MONO_INST_NEW ((cfg), (dest), (op)); \
3007         (dest)->cil_code = (ins)->cil_code; \
3008         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3009         } while (0)
3010
3011 /*
3012  * mono_arch_lowering_pass:
3013  *
3014  *  Converts complex opcodes into simpler ones so that each IR instruction
3015  * corresponds to one machine instruction.
3016  */
3017 void
3018 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3019 {
3020         MonoInst *ins, *n, *temp;
3021
3022         /*
3023          * FIXME: Need to add more instructions, but the current machine
3024          * description can't model some parts of the composite instructions like
3025          * cdq.
3026          */
3027         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3028                 switch (ins->opcode) {
3029                 case OP_DIV_IMM:
3030                 case OP_REM_IMM:
3031                 case OP_IDIV_IMM:
3032                 case OP_IDIV_UN_IMM:
3033                 case OP_IREM_UN_IMM:
3034                 case OP_LREM_IMM:
3035                 case OP_IREM_IMM:
3036                         mono_decompose_op_imm (cfg, bb, ins);
3037                         break;
3038                 case OP_COMPARE_IMM:
3039                 case OP_LCOMPARE_IMM:
3040                         if (!amd64_use_imm32 (ins->inst_imm)) {
3041                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3042                                 temp->inst_c0 = ins->inst_imm;
3043                                 temp->dreg = mono_alloc_ireg (cfg);
3044                                 ins->opcode = OP_COMPARE;
3045                                 ins->sreg2 = temp->dreg;
3046                         }
3047                         break;
3048 #ifndef __mono_ilp32__
3049                 case OP_LOAD_MEMBASE:
3050 #endif
3051                 case OP_LOADI8_MEMBASE:
3052                 /*  Don't generate memindex opcodes (to simplify */
3053                 /*  read sandboxing) */
3054                         if (!amd64_use_imm32 (ins->inst_offset)) {
3055                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3056                                 temp->inst_c0 = ins->inst_offset;
3057                                 temp->dreg = mono_alloc_ireg (cfg);
3058                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3059                                 ins->inst_indexreg = temp->dreg;
3060                         }
3061                         break;
3062 #ifndef __mono_ilp32__
3063                 case OP_STORE_MEMBASE_IMM:
3064 #endif
3065                 case OP_STOREI8_MEMBASE_IMM:
3066                         if (!amd64_use_imm32 (ins->inst_imm)) {
3067                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3068                                 temp->inst_c0 = ins->inst_imm;
3069                                 temp->dreg = mono_alloc_ireg (cfg);
3070                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3071                                 ins->sreg1 = temp->dreg;
3072                         }
3073                         break;
3074 #ifdef MONO_ARCH_SIMD_INTRINSICS
3075                 case OP_EXPAND_I1: {
3076                                 int temp_reg1 = mono_alloc_ireg (cfg);
3077                                 int temp_reg2 = mono_alloc_ireg (cfg);
3078                                 int original_reg = ins->sreg1;
3079
3080                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3081                                 temp->sreg1 = original_reg;
3082                                 temp->dreg = temp_reg1;
3083
3084                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3085                                 temp->sreg1 = temp_reg1;
3086                                 temp->dreg = temp_reg2;
3087                                 temp->inst_imm = 8;
3088
3089                                 NEW_INS (cfg, ins, temp, OP_LOR);
3090                                 temp->sreg1 = temp->dreg = temp_reg2;
3091                                 temp->sreg2 = temp_reg1;
3092
3093                                 ins->opcode = OP_EXPAND_I2;
3094                                 ins->sreg1 = temp_reg2;
3095                         }
3096                         break;
3097 #endif
3098                 default:
3099                         break;
3100                 }
3101         }
3102
3103         bb->max_vreg = cfg->next_vreg;
3104 }
3105
3106 static const int
3107 branch_cc_table [] = {
3108         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3109         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3110         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3111 };
3112
3113 /* Maps CMP_... constants to X86_CC_... constants */
3114 static const int
3115 cc_table [] = {
3116         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3117         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3118 };
3119
3120 static const int
3121 cc_signed_table [] = {
3122         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3123         FALSE, FALSE, FALSE, FALSE
3124 };
3125
3126 /*#include "cprop.c"*/
3127
3128 static unsigned char*
3129 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3130 {
3131         if (size == 8)
3132                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3133         else
3134                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3135
3136         if (size == 1)
3137                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3138         else if (size == 2)
3139                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3140         return code;
3141 }
3142
3143 static unsigned char*
3144 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3145 {
3146         int sreg = tree->sreg1;
3147         int need_touch = FALSE;
3148
3149 #if defined(TARGET_WIN32)
3150         need_touch = TRUE;
3151 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3152         if (!tree->flags & MONO_INST_INIT)
3153                 need_touch = TRUE;
3154 #endif
3155
3156         if (need_touch) {
3157                 guint8* br[5];
3158
3159                 /*
3160                  * Under Windows:
3161                  * If requested stack size is larger than one page,
3162                  * perform stack-touch operation
3163                  */
3164                 /*
3165                  * Generate stack probe code.
3166                  * Under Windows, it is necessary to allocate one page at a time,
3167                  * "touching" stack after each successful sub-allocation. This is
3168                  * because of the way stack growth is implemented - there is a
3169                  * guard page before the lowest stack page that is currently commited.
3170                  * Stack normally grows sequentially so OS traps access to the
3171                  * guard page and commits more pages when needed.
3172                  */
3173                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3174                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3175
3176                 br[2] = code; /* loop */
3177                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3178                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3179                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3180                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3181                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3182                 amd64_patch (br[3], br[2]);
3183                 amd64_test_reg_reg (code, sreg, sreg);
3184                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3185                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3186
3187                 br[1] = code; x86_jump8 (code, 0);
3188
3189                 amd64_patch (br[0], code);
3190                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3191                 amd64_patch (br[1], code);
3192                 amd64_patch (br[4], code);
3193         }
3194         else
3195                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3196
3197         if (tree->flags & MONO_INST_INIT) {
3198                 int offset = 0;
3199                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3200                         amd64_push_reg (code, AMD64_RAX);
3201                         offset += 8;
3202                 }
3203                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3204                         amd64_push_reg (code, AMD64_RCX);
3205                         offset += 8;
3206                 }
3207                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3208                         amd64_push_reg (code, AMD64_RDI);
3209                         offset += 8;
3210                 }
3211
3212                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3213                 if (sreg != AMD64_RCX)
3214                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3215                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3216
3217                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3218                 if (cfg->param_area)
3219                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3220                 amd64_cld (code);
3221                 amd64_prefix (code, X86_REP_PREFIX);
3222                 amd64_stosl (code);
3223
3224                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3225                         amd64_pop_reg (code, AMD64_RDI);
3226                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3227                         amd64_pop_reg (code, AMD64_RCX);
3228                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3229                         amd64_pop_reg (code, AMD64_RAX);
3230         }
3231         return code;
3232 }
3233
3234 static guint8*
3235 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3236 {
3237         CallInfo *cinfo;
3238         guint32 quad;
3239
3240         /* Move return value to the target register */
3241         /* FIXME: do this in the local reg allocator */
3242         switch (ins->opcode) {
3243         case OP_CALL:
3244         case OP_CALL_REG:
3245         case OP_CALL_MEMBASE:
3246         case OP_LCALL:
3247         case OP_LCALL_REG:
3248         case OP_LCALL_MEMBASE:
3249                 g_assert (ins->dreg == AMD64_RAX);
3250                 break;
3251         case OP_FCALL:
3252         case OP_FCALL_REG:
3253         case OP_FCALL_MEMBASE: {
3254                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3255                 if (rtype->type == MONO_TYPE_R4) {
3256                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3257                 }
3258                 else {
3259                         if (ins->dreg != AMD64_XMM0)
3260                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3261                 }
3262                 break;
3263         }
3264         case OP_RCALL:
3265         case OP_RCALL_REG:
3266         case OP_RCALL_MEMBASE:
3267                 if (ins->dreg != AMD64_XMM0)
3268                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3269                 break;
3270         case OP_VCALL:
3271         case OP_VCALL_REG:
3272         case OP_VCALL_MEMBASE:
3273         case OP_VCALL2:
3274         case OP_VCALL2_REG:
3275         case OP_VCALL2_MEMBASE:
3276                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3277                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3278                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3279
3280                         /* Load the destination address */
3281                         g_assert (loc->opcode == OP_REGOFFSET);
3282                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3283
3284                         for (quad = 0; quad < 2; quad ++) {
3285                                 switch (cinfo->ret.pair_storage [quad]) {
3286                                 case ArgInIReg:
3287                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3288                                         break;
3289                                 case ArgInFloatSSEReg:
3290                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3291                                         break;
3292                                 case ArgInDoubleSSEReg:
3293                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3294                                         break;
3295                                 case ArgNone:
3296                                         break;
3297                                 default:
3298                                         NOT_IMPLEMENTED;
3299                                 }
3300                         }
3301                 }
3302                 break;
3303         }
3304
3305         return code;
3306 }
3307
3308 #endif /* DISABLE_JIT */
3309
3310 #ifdef __APPLE__
3311 static int tls_gs_offset;
3312 #endif
3313
3314 gboolean
3315 mono_amd64_have_tls_get (void)
3316 {
3317 #ifdef TARGET_MACH
3318         static gboolean have_tls_get = FALSE;
3319         static gboolean inited = FALSE;
3320
3321         if (inited)
3322                 return have_tls_get;
3323
3324 #if MONO_HAVE_FAST_TLS
3325         guint8 *ins = (guint8*)pthread_getspecific;
3326
3327         /*
3328          * We're looking for these two instructions:
3329          *
3330          * mov    %gs:[offset](,%rdi,8),%rax
3331          * retq
3332          */
3333         have_tls_get = ins [0] == 0x65 &&
3334                        ins [1] == 0x48 &&
3335                        ins [2] == 0x8b &&
3336                        ins [3] == 0x04 &&
3337                        ins [4] == 0xfd &&
3338                        ins [6] == 0x00 &&
3339                        ins [7] == 0x00 &&
3340                        ins [8] == 0x00 &&
3341                        ins [9] == 0xc3;
3342
3343         tls_gs_offset = ins[5];
3344
3345         /*
3346          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3347          * For that version we're looking for these instructions:
3348          *
3349          * pushq  %rbp
3350          * movq   %rsp, %rbp
3351          * mov    %gs:[offset](,%rdi,8),%rax
3352          * popq   %rbp
3353          * retq
3354          */
3355         if (!have_tls_get) {
3356                 have_tls_get = ins [0] == 0x55 &&
3357                                ins [1] == 0x48 &&
3358                                ins [2] == 0x89 &&
3359                                ins [3] == 0xe5 &&
3360                                ins [4] == 0x65 &&
3361                                ins [5] == 0x48 &&
3362                                ins [6] == 0x8b &&
3363                                ins [7] == 0x04 &&
3364                                ins [8] == 0xfd &&
3365                                ins [10] == 0x00 &&
3366                                ins [11] == 0x00 &&
3367                                ins [12] == 0x00 &&
3368                                ins [13] == 0x5d &&
3369                                ins [14] == 0xc3;
3370
3371                 tls_gs_offset = ins[9];
3372         }
3373 #endif
3374
3375         inited = TRUE;
3376
3377         return have_tls_get;
3378 #elif defined(TARGET_ANDROID)
3379         return FALSE;
3380 #else
3381         return TRUE;
3382 #endif
3383 }
3384
3385 int
3386 mono_amd64_get_tls_gs_offset (void)
3387 {
3388 #ifdef TARGET_OSX
3389         return tls_gs_offset;
3390 #else
3391         g_assert_not_reached ();
3392         return -1;
3393 #endif
3394 }
3395
3396 /*
3397  * mono_amd64_emit_tls_get:
3398  * @code: buffer to store code to
3399  * @dreg: hard register where to place the result
3400  * @tls_offset: offset info
3401  *
3402  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3403  * the dreg register the item in the thread local storage identified
3404  * by tls_offset.
3405  *
3406  * Returns: a pointer to the end of the stored code
3407  */
3408 guint8*
3409 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3410 {
3411 #ifdef TARGET_WIN32
3412         if (tls_offset < 64) {
3413                 x86_prefix (code, X86_GS_PREFIX);
3414                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3415         } else {
3416                 guint8 *buf [16];
3417
3418                 g_assert (tls_offset < 0x440);
3419                 /* Load TEB->TlsExpansionSlots */
3420                 x86_prefix (code, X86_GS_PREFIX);
3421                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3422                 amd64_test_reg_reg (code, dreg, dreg);
3423                 buf [0] = code;
3424                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3425                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3426                 amd64_patch (buf [0], code);
3427         }
3428 #elif defined(__APPLE__)
3429         x86_prefix (code, X86_GS_PREFIX);
3430         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3431 #else
3432         if (optimize_for_xen) {
3433                 x86_prefix (code, X86_FS_PREFIX);
3434                 amd64_mov_reg_mem (code, dreg, 0, 8);
3435                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3436         } else {
3437                 x86_prefix (code, X86_FS_PREFIX);
3438                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3439         }
3440 #endif
3441         return code;
3442 }
3443
3444 #ifdef TARGET_WIN32
3445
3446 #define MAX_TEB_TLS_SLOTS 64
3447 #define TEB_TLS_SLOTS_OFFSET 0x1480
3448 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3449
3450 static guint8*
3451 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3452 {
3453         int tmp_reg = -1;
3454         guint8 * more_than_64_slots = NULL;
3455         guint8 * empty_slot = NULL;
3456         guint8 * tls_get_reg_done = NULL;
3457
3458         //Use temporary register for offset calculation?
3459         if (dreg == offset_reg) {
3460                 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3461                 amd64_push_reg (code, tmp_reg);
3462                 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3463                 offset_reg = tmp_reg;
3464         }
3465
3466         //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3467         amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3468         more_than_64_slots = code;
3469         amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3470
3471         //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3472         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3473         amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3474
3475         //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3476         x86_prefix (code, X86_GS_PREFIX);
3477         amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3478
3479         tls_get_reg_done = code;
3480         amd64_jump8 (code, 0);
3481
3482         amd64_patch (more_than_64_slots, code);
3483
3484         //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3485         x86_prefix (code, X86_GS_PREFIX);
3486         amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3487
3488         //Check for NULL in _TEB.TlsExpansionSlots.
3489         amd64_test_reg_reg (code, dreg, dreg);
3490         empty_slot = code;
3491         amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3492
3493         //TLS expansion slots are at index offset into the expansion array.
3494         //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3495         amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3496         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3497
3498         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3499
3500         amd64_patch (empty_slot, code);
3501         amd64_patch (tls_get_reg_done, code);
3502
3503         if (tmp_reg != -1)
3504                 amd64_pop_reg (code, tmp_reg);
3505
3506         return code;
3507 }
3508
3509 #endif
3510
3511 static guint8*
3512 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3513 {
3514         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3515 #ifdef TARGET_OSX
3516         if (dreg != offset_reg)
3517                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3518         amd64_prefix (code, X86_GS_PREFIX);
3519         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3520 #elif defined(__linux__)
3521         int tmpreg = -1;
3522
3523         if (dreg == offset_reg) {
3524                 /* Use a temporary reg by saving it to the redzone */
3525                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3526                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3527                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3528                 offset_reg = tmpreg;
3529         }
3530         x86_prefix (code, X86_FS_PREFIX);
3531         amd64_mov_reg_mem (code, dreg, 0, 8);
3532         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3533         if (tmpreg != -1)
3534                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3535 #elif defined(TARGET_WIN32)
3536         code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3537 #else
3538         g_assert_not_reached ();
3539 #endif
3540         return code;
3541 }
3542
3543 static guint8*
3544 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3545 {
3546 #ifdef TARGET_WIN32
3547         g_assert_not_reached ();
3548 #elif defined(__APPLE__)
3549         x86_prefix (code, X86_GS_PREFIX);
3550         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3551 #else
3552         g_assert (!optimize_for_xen);
3553         x86_prefix (code, X86_FS_PREFIX);
3554         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3555 #endif
3556         return code;
3557 }
3558
3559 static guint8*
3560 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3561 {
3562         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3563 #ifdef TARGET_WIN32
3564         g_assert_not_reached ();
3565 #elif defined(__APPLE__)
3566         x86_prefix (code, X86_GS_PREFIX);
3567         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3568 #else
3569         x86_prefix (code, X86_FS_PREFIX);
3570         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3571 #endif
3572         return code;
3573 }
3574
3575  /*
3576  * mono_arch_translate_tls_offset:
3577  *
3578  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3579  */
3580 int
3581 mono_arch_translate_tls_offset (int offset)
3582 {
3583 #ifdef __APPLE__
3584         return tls_gs_offset + (offset * 8);
3585 #else
3586         return offset;
3587 #endif
3588 }
3589
3590 /*
3591  * emit_setup_lmf:
3592  *
3593  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3594  */
3595 static guint8*
3596 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3597 {
3598         /*
3599          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3600          */
3601         /*
3602          * sp is saved right before calls but we need to save it here too so
3603          * async stack walks would work.
3604          */
3605         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3606         /* Save rbp */
3607         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3608         if (cfg->arch.omit_fp && cfa_offset != -1)
3609                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3610
3611         /* These can't contain refs */
3612         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3613         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3614         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3615         /* These are handled automatically by the stack marking code */
3616         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3617
3618         return code;
3619 }
3620
3621 /* benchmark and set based on cpu */
3622 #define LOOP_ALIGNMENT 8
3623 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3624
3625 #ifndef DISABLE_JIT
3626 void
3627 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3628 {
3629         MonoInst *ins;
3630         MonoCallInst *call;
3631         guint offset;
3632         guint8 *code = cfg->native_code + cfg->code_len;
3633         int max_len;
3634
3635         /* Fix max_offset estimate for each successor bb */
3636         if (cfg->opt & MONO_OPT_BRANCH) {
3637                 int current_offset = cfg->code_len;
3638                 MonoBasicBlock *current_bb;
3639                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3640                         current_bb->max_offset = current_offset;
3641                         current_offset += current_bb->max_length;
3642                 }
3643         }
3644
3645         if (cfg->opt & MONO_OPT_LOOP) {
3646                 int pad, align = LOOP_ALIGNMENT;
3647                 /* set alignment depending on cpu */
3648                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3649                         pad = align - pad;
3650                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3651                         amd64_padding (code, pad);
3652                         cfg->code_len += pad;
3653                         bb->native_offset = cfg->code_len;
3654                 }
3655         }
3656
3657         if (cfg->verbose_level > 2)
3658                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3659
3660         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3661                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3662                 g_assert (!cfg->compile_aot);
3663
3664                 cov->data [bb->dfn].cil_code = bb->cil_code;
3665                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3666                 /* this is not thread save, but good enough */
3667                 amd64_inc_membase (code, AMD64_R11, 0);
3668         }
3669
3670         offset = code - cfg->native_code;
3671
3672         mono_debug_open_block (cfg, bb, offset);
3673
3674     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3675                 x86_breakpoint (code);
3676
3677         MONO_BB_FOR_EACH_INS (bb, ins) {
3678                 offset = code - cfg->native_code;
3679
3680                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3681
3682 #define EXTRA_CODE_SPACE (16)
3683
3684                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3685                         cfg->code_size *= 2;
3686                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3687                         code = cfg->native_code + offset;
3688                         cfg->stat_code_reallocs++;
3689                 }
3690
3691                 if (cfg->debug_info)
3692                         mono_debug_record_line_number (cfg, ins, offset);
3693
3694                 switch (ins->opcode) {
3695                 case OP_BIGMUL:
3696                         amd64_mul_reg (code, ins->sreg2, TRUE);
3697                         break;
3698                 case OP_BIGMUL_UN:
3699                         amd64_mul_reg (code, ins->sreg2, FALSE);
3700                         break;
3701                 case OP_X86_SETEQ_MEMBASE:
3702                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3703                         break;
3704                 case OP_STOREI1_MEMBASE_IMM:
3705                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3706                         break;
3707                 case OP_STOREI2_MEMBASE_IMM:
3708                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3709                         break;
3710                 case OP_STOREI4_MEMBASE_IMM:
3711                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3712                         break;
3713                 case OP_STOREI1_MEMBASE_REG:
3714                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3715                         break;
3716                 case OP_STOREI2_MEMBASE_REG:
3717                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3718                         break;
3719                 /* In AMD64 NaCl, pointers are 4 bytes, */
3720                 /*  so STORE_* != STOREI8_*. Likewise below. */
3721                 case OP_STORE_MEMBASE_REG:
3722                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3723                         break;
3724                 case OP_STOREI8_MEMBASE_REG:
3725                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3726                         break;
3727                 case OP_STOREI4_MEMBASE_REG:
3728                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3729                         break;
3730                 case OP_STORE_MEMBASE_IMM:
3731                         /* In NaCl, this could be a PCONST type, which could */
3732                         /* mean a pointer type was copied directly into the  */
3733                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3734                         /* the value would be 0x00000000FFFFFFFF which is    */
3735                         /* not proper for an imm32 unless you cast it.       */
3736                         g_assert (amd64_is_imm32 (ins->inst_imm));
3737                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3738                         break;
3739                 case OP_STOREI8_MEMBASE_IMM:
3740                         g_assert (amd64_is_imm32 (ins->inst_imm));
3741                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3742                         break;
3743                 case OP_LOAD_MEM:
3744 #ifdef __mono_ilp32__
3745                         /* In ILP32, pointers are 4 bytes, so separate these */
3746                         /* cases, use literal 8 below where we really want 8 */
3747                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3748                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3749                         break;
3750 #endif
3751                 case OP_LOADI8_MEM:
3752                         // FIXME: Decompose this earlier
3753                         if (amd64_use_imm32 (ins->inst_imm))
3754                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3755                         else {
3756                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3757                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3758                         }
3759                         break;
3760                 case OP_LOADI4_MEM:
3761                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3762                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3763                         break;
3764                 case OP_LOADU4_MEM:
3765                         // FIXME: Decompose this earlier
3766                         if (amd64_use_imm32 (ins->inst_imm))
3767                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3768                         else {
3769                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3770                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3771                         }
3772                         break;
3773                 case OP_LOADU1_MEM:
3774                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3775                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3776                         break;
3777                 case OP_LOADU2_MEM:
3778                         /* For NaCl, pointers are 4 bytes, so separate these */
3779                         /* cases, use literal 8 below where we really want 8 */
3780                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3781                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3782                         break;
3783                 case OP_LOAD_MEMBASE:
3784                         g_assert (amd64_is_imm32 (ins->inst_offset));
3785                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3786                         break;
3787                 case OP_LOADI8_MEMBASE:
3788                         /* Use literal 8 instead of sizeof pointer or */
3789                         /* register, we really want 8 for this opcode */
3790                         g_assert (amd64_is_imm32 (ins->inst_offset));
3791                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3792                         break;
3793                 case OP_LOADI4_MEMBASE:
3794                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3795                         break;
3796                 case OP_LOADU4_MEMBASE:
3797                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3798                         break;
3799                 case OP_LOADU1_MEMBASE:
3800                         /* The cpu zero extends the result into 64 bits */
3801                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3802                         break;
3803                 case OP_LOADI1_MEMBASE:
3804                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3805                         break;
3806                 case OP_LOADU2_MEMBASE:
3807                         /* The cpu zero extends the result into 64 bits */
3808                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3809                         break;
3810                 case OP_LOADI2_MEMBASE:
3811                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3812                         break;
3813                 case OP_AMD64_LOADI8_MEMINDEX:
3814                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3815                         break;
3816                 case OP_LCONV_TO_I1:
3817                 case OP_ICONV_TO_I1:
3818                 case OP_SEXT_I1:
3819                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3820                         break;
3821                 case OP_LCONV_TO_I2:
3822                 case OP_ICONV_TO_I2:
3823                 case OP_SEXT_I2:
3824                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3825                         break;
3826                 case OP_LCONV_TO_U1:
3827                 case OP_ICONV_TO_U1:
3828                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3829                         break;
3830                 case OP_LCONV_TO_U2:
3831                 case OP_ICONV_TO_U2:
3832                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3833                         break;
3834                 case OP_ZEXT_I4:
3835                         /* Clean out the upper word */
3836                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3837                         break;
3838                 case OP_SEXT_I4:
3839                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3840                         break;
3841                 case OP_COMPARE:
3842                 case OP_LCOMPARE:
3843                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3844                         break;
3845                 case OP_COMPARE_IMM:
3846 #if defined(__mono_ilp32__)
3847                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3848                         g_assert (amd64_is_imm32 (ins->inst_imm));
3849                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3850                         break;
3851 #endif
3852                 case OP_LCOMPARE_IMM:
3853                         g_assert (amd64_is_imm32 (ins->inst_imm));
3854                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3855                         break;
3856                 case OP_X86_COMPARE_REG_MEMBASE:
3857                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3858                         break;
3859                 case OP_X86_TEST_NULL:
3860                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3861                         break;
3862                 case OP_AMD64_TEST_NULL:
3863                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3864                         break;
3865
3866                 case OP_X86_ADD_REG_MEMBASE:
3867                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3868                         break;
3869                 case OP_X86_SUB_REG_MEMBASE:
3870                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3871                         break;
3872                 case OP_X86_AND_REG_MEMBASE:
3873                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3874                         break;
3875                 case OP_X86_OR_REG_MEMBASE:
3876                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3877                         break;
3878                 case OP_X86_XOR_REG_MEMBASE:
3879                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3880                         break;
3881
3882                 case OP_X86_ADD_MEMBASE_IMM:
3883                         /* FIXME: Make a 64 version too */
3884                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3885                         break;
3886                 case OP_X86_SUB_MEMBASE_IMM:
3887                         g_assert (amd64_is_imm32 (ins->inst_imm));
3888                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3889                         break;
3890                 case OP_X86_AND_MEMBASE_IMM:
3891                         g_assert (amd64_is_imm32 (ins->inst_imm));
3892                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3893                         break;
3894                 case OP_X86_OR_MEMBASE_IMM:
3895                         g_assert (amd64_is_imm32 (ins->inst_imm));
3896                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3897                         break;
3898                 case OP_X86_XOR_MEMBASE_IMM:
3899                         g_assert (amd64_is_imm32 (ins->inst_imm));
3900                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3901                         break;
3902                 case OP_X86_ADD_MEMBASE_REG:
3903                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3904                         break;
3905                 case OP_X86_SUB_MEMBASE_REG:
3906                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3907                         break;
3908                 case OP_X86_AND_MEMBASE_REG:
3909                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3910                         break;
3911                 case OP_X86_OR_MEMBASE_REG:
3912                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3913                         break;
3914                 case OP_X86_XOR_MEMBASE_REG:
3915                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3916                         break;
3917                 case OP_X86_INC_MEMBASE:
3918                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3919                         break;
3920                 case OP_X86_INC_REG:
3921                         amd64_inc_reg_size (code, ins->dreg, 4);
3922                         break;
3923                 case OP_X86_DEC_MEMBASE:
3924                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3925                         break;
3926                 case OP_X86_DEC_REG:
3927                         amd64_dec_reg_size (code, ins->dreg, 4);
3928                         break;
3929                 case OP_X86_MUL_REG_MEMBASE:
3930                 case OP_X86_MUL_MEMBASE_REG:
3931                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3932                         break;
3933                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3934                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3935                         break;
3936                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3937                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3938                         break;
3939                 case OP_AMD64_COMPARE_MEMBASE_REG:
3940                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3941                         break;
3942                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3943                         g_assert (amd64_is_imm32 (ins->inst_imm));
3944                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3945                         break;
3946                 case OP_X86_COMPARE_MEMBASE8_IMM:
3947                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3948                         break;
3949                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3950                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3951                         break;
3952                 case OP_AMD64_COMPARE_REG_MEMBASE:
3953                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3954                         break;
3955
3956                 case OP_AMD64_ADD_REG_MEMBASE:
3957                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3958                         break;
3959                 case OP_AMD64_SUB_REG_MEMBASE:
3960                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3961                         break;
3962                 case OP_AMD64_AND_REG_MEMBASE:
3963                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3964                         break;
3965                 case OP_AMD64_OR_REG_MEMBASE:
3966                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3967                         break;
3968                 case OP_AMD64_XOR_REG_MEMBASE:
3969                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3970                         break;
3971
3972                 case OP_AMD64_ADD_MEMBASE_REG:
3973                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3974                         break;
3975                 case OP_AMD64_SUB_MEMBASE_REG:
3976                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3977                         break;
3978                 case OP_AMD64_AND_MEMBASE_REG:
3979                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3980                         break;
3981                 case OP_AMD64_OR_MEMBASE_REG:
3982                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3983                         break;
3984                 case OP_AMD64_XOR_MEMBASE_REG:
3985                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3986                         break;
3987
3988                 case OP_AMD64_ADD_MEMBASE_IMM:
3989                         g_assert (amd64_is_imm32 (ins->inst_imm));
3990                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3991                         break;
3992                 case OP_AMD64_SUB_MEMBASE_IMM:
3993                         g_assert (amd64_is_imm32 (ins->inst_imm));
3994                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3995                         break;
3996                 case OP_AMD64_AND_MEMBASE_IMM:
3997                         g_assert (amd64_is_imm32 (ins->inst_imm));
3998                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3999                         break;
4000                 case OP_AMD64_OR_MEMBASE_IMM:
4001                         g_assert (amd64_is_imm32 (ins->inst_imm));
4002                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4003                         break;
4004                 case OP_AMD64_XOR_MEMBASE_IMM:
4005                         g_assert (amd64_is_imm32 (ins->inst_imm));
4006                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4007                         break;
4008
4009                 case OP_BREAK:
4010                         amd64_breakpoint (code);
4011                         break;
4012                 case OP_RELAXED_NOP:
4013                         x86_prefix (code, X86_REP_PREFIX);
4014                         x86_nop (code);
4015                         break;
4016                 case OP_HARD_NOP:
4017                         x86_nop (code);
4018                         break;
4019                 case OP_NOP:
4020                 case OP_DUMMY_USE:
4021                 case OP_DUMMY_STORE:
4022                 case OP_DUMMY_ICONST:
4023                 case OP_DUMMY_R8CONST:
4024                 case OP_NOT_REACHED:
4025                 case OP_NOT_NULL:
4026                         break;
4027                 case OP_IL_SEQ_POINT:
4028                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4029                         break;
4030                 case OP_SEQ_POINT: {
4031                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4032                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4033                                 guint8 *label;
4034
4035                                 /* Load ss_tramp_var */
4036                                 /* This is equal to &ss_trampoline */
4037                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4038                                 /* Load the trampoline address */
4039                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4040                                 /* Call it if it is non-null */
4041                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4042                                 label = code;
4043                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4044                                 amd64_call_reg (code, AMD64_R11);
4045                                 amd64_patch (label, code);
4046                         }
4047
4048                         /*
4049                          * This is the address which is saved in seq points,
4050                          */
4051                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4052
4053                         if (cfg->compile_aot) {
4054                                 guint32 offset = code - cfg->native_code;
4055                                 guint32 val;
4056                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4057                                 guint8 *label;
4058
4059                                 /* Load info var */
4060                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4061                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4062                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4063                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4064                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4065                                 label = code;
4066                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4067                                 /* Call the trampoline */
4068                                 amd64_call_reg (code, AMD64_R11);
4069                                 amd64_patch (label, code);
4070                         } else {
4071                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4072                                 guint8 *label;
4073
4074                                 /*
4075                                  * Emit a test+branch against a constant, the constant will be overwritten
4076                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4077                                  */
4078                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4079                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4080                                 label = code;
4081                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4082
4083                                 g_assert (var);
4084                                 g_assert (var->opcode == OP_REGOFFSET);
4085                                 /* Load bp_tramp_var */
4086                                 /* This is equal to &bp_trampoline */
4087                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4088                                 /* Call the trampoline */
4089                                 amd64_call_membase (code, AMD64_R11, 0);
4090                                 amd64_patch (label, code);
4091                         }
4092                         /*
4093                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4094                          * to another IL offset.
4095                          */
4096                         x86_nop (code);
4097                         break;
4098                 }
4099                 case OP_ADDCC:
4100                 case OP_LADDCC:
4101                 case OP_LADD:
4102                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4103                         break;
4104                 case OP_ADC:
4105                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4106                         break;
4107                 case OP_ADD_IMM:
4108                 case OP_LADD_IMM:
4109                         g_assert (amd64_is_imm32 (ins->inst_imm));
4110                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4111                         break;
4112                 case OP_ADC_IMM:
4113                         g_assert (amd64_is_imm32 (ins->inst_imm));
4114                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4115                         break;
4116                 case OP_SUBCC:
4117                 case OP_LSUBCC:
4118                 case OP_LSUB:
4119                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4120                         break;
4121                 case OP_SBB:
4122                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4123                         break;
4124                 case OP_SUB_IMM:
4125                 case OP_LSUB_IMM:
4126                         g_assert (amd64_is_imm32 (ins->inst_imm));
4127                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4128                         break;
4129                 case OP_SBB_IMM:
4130                         g_assert (amd64_is_imm32 (ins->inst_imm));
4131                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4132                         break;
4133                 case OP_LAND:
4134                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4135                         break;
4136                 case OP_AND_IMM:
4137                 case OP_LAND_IMM:
4138                         g_assert (amd64_is_imm32 (ins->inst_imm));
4139                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4140                         break;
4141                 case OP_LMUL:
4142                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4143                         break;
4144                 case OP_MUL_IMM:
4145                 case OP_LMUL_IMM:
4146                 case OP_IMUL_IMM: {
4147                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4148
4149                         switch (ins->inst_imm) {
4150                         case 2:
4151                                 /* MOV r1, r2 */
4152                                 /* ADD r1, r1 */
4153                                 if (ins->dreg != ins->sreg1)
4154                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4155                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4156                                 break;
4157                         case 3:
4158                                 /* LEA r1, [r2 + r2*2] */
4159                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4160                                 break;
4161                         case 5:
4162                                 /* LEA r1, [r2 + r2*4] */
4163                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4164                                 break;
4165                         case 6:
4166                                 /* LEA r1, [r2 + r2*2] */
4167                                 /* ADD r1, r1          */
4168                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4169                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4170                                 break;
4171                         case 9:
4172                                 /* LEA r1, [r2 + r2*8] */
4173                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4174                                 break;
4175                         case 10:
4176                                 /* LEA r1, [r2 + r2*4] */
4177                                 /* ADD r1, r1          */
4178                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4179                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4180                                 break;
4181                         case 12:
4182                                 /* LEA r1, [r2 + r2*2] */
4183                                 /* SHL r1, 2           */
4184                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4185                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4186                                 break;
4187                         case 25:
4188                                 /* LEA r1, [r2 + r2*4] */
4189                                 /* LEA r1, [r1 + r1*4] */
4190                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4191                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4192                                 break;
4193                         case 100:
4194                                 /* LEA r1, [r2 + r2*4] */
4195                                 /* SHL r1, 2           */
4196                                 /* LEA r1, [r1 + r1*4] */
4197                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4198                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4199                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4200                                 break;
4201                         default:
4202                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4203                                 break;
4204                         }
4205                         break;
4206                 }
4207                 case OP_LDIV:
4208                 case OP_LREM:
4209                         /* Regalloc magic makes the div/rem cases the same */
4210                         if (ins->sreg2 == AMD64_RDX) {
4211                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4212                                 amd64_cdq (code);
4213                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4214                         } else {
4215                                 amd64_cdq (code);
4216                                 amd64_div_reg (code, ins->sreg2, TRUE);
4217                         }
4218                         break;
4219                 case OP_LDIV_UN:
4220                 case OP_LREM_UN:
4221                         if (ins->sreg2 == AMD64_RDX) {
4222                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4223                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4224                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4225                         } else {
4226                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4227                                 amd64_div_reg (code, ins->sreg2, FALSE);
4228                         }
4229                         break;
4230                 case OP_IDIV:
4231                 case OP_IREM:
4232                         if (ins->sreg2 == AMD64_RDX) {
4233                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4234                                 amd64_cdq_size (code, 4);
4235                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4236                         } else {
4237                                 amd64_cdq_size (code, 4);
4238                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4239                         }
4240                         break;
4241                 case OP_IDIV_UN:
4242                 case OP_IREM_UN:
4243                         if (ins->sreg2 == AMD64_RDX) {
4244                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4245                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4246                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4247                         } else {
4248                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4249                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4250                         }
4251                         break;
4252                 case OP_LMUL_OVF:
4253                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4254                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4255                         break;
4256                 case OP_LOR:
4257                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4258                         break;
4259                 case OP_OR_IMM:
4260                 case OP_LOR_IMM:
4261                         g_assert (amd64_is_imm32 (ins->inst_imm));
4262                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4263                         break;
4264                 case OP_LXOR:
4265                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4266                         break;
4267                 case OP_XOR_IMM:
4268                 case OP_LXOR_IMM:
4269                         g_assert (amd64_is_imm32 (ins->inst_imm));
4270                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4271                         break;
4272                 case OP_LSHL:
4273                         g_assert (ins->sreg2 == AMD64_RCX);
4274                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4275                         break;
4276                 case OP_LSHR:
4277                         g_assert (ins->sreg2 == AMD64_RCX);
4278                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4279                         break;
4280                 case OP_SHR_IMM:
4281                 case OP_LSHR_IMM:
4282                         g_assert (amd64_is_imm32 (ins->inst_imm));
4283                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4284                         break;
4285                 case OP_SHR_UN_IMM:
4286                         g_assert (amd64_is_imm32 (ins->inst_imm));
4287                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4288                         break;
4289                 case OP_LSHR_UN_IMM:
4290                         g_assert (amd64_is_imm32 (ins->inst_imm));
4291                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4292                         break;
4293                 case OP_LSHR_UN:
4294                         g_assert (ins->sreg2 == AMD64_RCX);
4295                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4296                         break;
4297                 case OP_SHL_IMM:
4298                 case OP_LSHL_IMM:
4299                         g_assert (amd64_is_imm32 (ins->inst_imm));
4300                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4301                         break;
4302
4303                 case OP_IADDCC:
4304                 case OP_IADD:
4305                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4306                         break;
4307                 case OP_IADC:
4308                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4309                         break;
4310                 case OP_IADD_IMM:
4311                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4312                         break;
4313                 case OP_IADC_IMM:
4314                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4315                         break;
4316                 case OP_ISUBCC:
4317                 case OP_ISUB:
4318                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4319                         break;
4320                 case OP_ISBB:
4321                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4322                         break;
4323                 case OP_ISUB_IMM:
4324                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4325                         break;
4326                 case OP_ISBB_IMM:
4327                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4328                         break;
4329                 case OP_IAND:
4330                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4331                         break;
4332                 case OP_IAND_IMM:
4333                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4334                         break;
4335                 case OP_IOR:
4336                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4337                         break;
4338                 case OP_IOR_IMM:
4339                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4340                         break;
4341                 case OP_IXOR:
4342                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4343                         break;
4344                 case OP_IXOR_IMM:
4345                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4346                         break;
4347                 case OP_INEG:
4348                         amd64_neg_reg_size (code, ins->sreg1, 4);
4349                         break;
4350                 case OP_INOT:
4351                         amd64_not_reg_size (code, ins->sreg1, 4);
4352                         break;
4353                 case OP_ISHL:
4354                         g_assert (ins->sreg2 == AMD64_RCX);
4355                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4356                         break;
4357                 case OP_ISHR:
4358                         g_assert (ins->sreg2 == AMD64_RCX);
4359                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4360                         break;
4361                 case OP_ISHR_IMM:
4362                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4363                         break;
4364                 case OP_ISHR_UN_IMM:
4365                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4366                         break;
4367                 case OP_ISHR_UN:
4368                         g_assert (ins->sreg2 == AMD64_RCX);
4369                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4370                         break;
4371                 case OP_ISHL_IMM:
4372                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4373                         break;
4374                 case OP_IMUL:
4375                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4376                         break;
4377                 case OP_IMUL_OVF:
4378                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4379                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4380                         break;
4381                 case OP_IMUL_OVF_UN:
4382                 case OP_LMUL_OVF_UN: {
4383                         /* the mul operation and the exception check should most likely be split */
4384                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4385                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4386                         /*g_assert (ins->sreg2 == X86_EAX);
4387                         g_assert (ins->dreg == X86_EAX);*/
4388                         if (ins->sreg2 == X86_EAX) {
4389                                 non_eax_reg = ins->sreg1;
4390                         } else if (ins->sreg1 == X86_EAX) {
4391                                 non_eax_reg = ins->sreg2;
4392                         } else {
4393                                 /* no need to save since we're going to store to it anyway */
4394                                 if (ins->dreg != X86_EAX) {
4395                                         saved_eax = TRUE;
4396                                         amd64_push_reg (code, X86_EAX);
4397                                 }
4398                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4399                                 non_eax_reg = ins->sreg2;
4400                         }
4401                         if (ins->dreg == X86_EDX) {
4402                                 if (!saved_eax) {
4403                                         saved_eax = TRUE;
4404                                         amd64_push_reg (code, X86_EAX);
4405                                 }
4406                         } else {
4407                                 saved_edx = TRUE;
4408                                 amd64_push_reg (code, X86_EDX);
4409                         }
4410                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4411                         /* save before the check since pop and mov don't change the flags */
4412                         if (ins->dreg != X86_EAX)
4413                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4414                         if (saved_edx)
4415                                 amd64_pop_reg (code, X86_EDX);
4416                         if (saved_eax)
4417                                 amd64_pop_reg (code, X86_EAX);
4418                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4419                         break;
4420                 }
4421                 case OP_ICOMPARE:
4422                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4423                         break;
4424                 case OP_ICOMPARE_IMM:
4425                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4426                         break;
4427                 case OP_IBEQ:
4428                 case OP_IBLT:
4429                 case OP_IBGT:
4430                 case OP_IBGE:
4431                 case OP_IBLE:
4432                 case OP_LBEQ:
4433                 case OP_LBLT:
4434                 case OP_LBGT:
4435                 case OP_LBGE:
4436                 case OP_LBLE:
4437                 case OP_IBNE_UN:
4438                 case OP_IBLT_UN:
4439                 case OP_IBGT_UN:
4440                 case OP_IBGE_UN:
4441                 case OP_IBLE_UN:
4442                 case OP_LBNE_UN:
4443                 case OP_LBLT_UN:
4444                 case OP_LBGT_UN:
4445                 case OP_LBGE_UN:
4446                 case OP_LBLE_UN:
4447                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4448                         break;
4449
4450                 case OP_CMOV_IEQ:
4451                 case OP_CMOV_IGE:
4452                 case OP_CMOV_IGT:
4453                 case OP_CMOV_ILE:
4454                 case OP_CMOV_ILT:
4455                 case OP_CMOV_INE_UN:
4456                 case OP_CMOV_IGE_UN:
4457                 case OP_CMOV_IGT_UN:
4458                 case OP_CMOV_ILE_UN:
4459                 case OP_CMOV_ILT_UN:
4460                 case OP_CMOV_LEQ:
4461                 case OP_CMOV_LGE:
4462                 case OP_CMOV_LGT:
4463                 case OP_CMOV_LLE:
4464                 case OP_CMOV_LLT:
4465                 case OP_CMOV_LNE_UN:
4466                 case OP_CMOV_LGE_UN:
4467                 case OP_CMOV_LGT_UN:
4468                 case OP_CMOV_LLE_UN:
4469                 case OP_CMOV_LLT_UN:
4470                         g_assert (ins->dreg == ins->sreg1);
4471                         /* This needs to operate on 64 bit values */
4472                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4473                         break;
4474
4475                 case OP_LNOT:
4476                         amd64_not_reg (code, ins->sreg1);
4477                         break;
4478                 case OP_LNEG:
4479                         amd64_neg_reg (code, ins->sreg1);
4480                         break;
4481
4482                 case OP_ICONST:
4483                 case OP_I8CONST:
4484                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4485                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4486                         else
4487                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4488                         break;
4489                 case OP_AOTCONST:
4490                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4491                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4492                         break;
4493                 case OP_JUMP_TABLE:
4494                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4495                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4496                         break;
4497                 case OP_MOVE:
4498                         if (ins->dreg != ins->sreg1)
4499                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4500                         break;
4501                 case OP_AMD64_SET_XMMREG_R4: {
4502                         if (cfg->r4fp) {
4503                                 if (ins->dreg != ins->sreg1)
4504                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4505                         } else {
4506                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4507                         }
4508                         break;
4509                 }
4510                 case OP_AMD64_SET_XMMREG_R8: {
4511                         if (ins->dreg != ins->sreg1)
4512                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4513                         break;
4514                 }
4515                 case OP_TAILCALL: {
4516                         MonoCallInst *call = (MonoCallInst*)ins;
4517                         int i, save_area_offset;
4518
4519                         g_assert (!cfg->method->save_lmf);
4520
4521                         /* Restore callee saved registers */
4522                         save_area_offset = cfg->arch.reg_save_area_offset;
4523                         for (i = 0; i < AMD64_NREG; ++i)
4524                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4525                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4526                                         save_area_offset += 8;
4527                                 }
4528
4529                         if (cfg->arch.omit_fp) {
4530                                 if (cfg->arch.stack_alloc_size)
4531                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4532                                 // FIXME:
4533                                 if (call->stack_usage)
4534                                         NOT_IMPLEMENTED;
4535                         } else {
4536                                 /* Copy arguments on the stack to our argument area */
4537                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4538                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4539                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4540                                 }
4541
4542                                 amd64_leave (code);
4543                         }
4544
4545                         offset = code - cfg->native_code;
4546                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4547                         if (cfg->compile_aot)
4548                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4549                         else
4550                                 amd64_set_reg_template (code, AMD64_R11);
4551                         amd64_jump_reg (code, AMD64_R11);
4552                         ins->flags |= MONO_INST_GC_CALLSITE;
4553                         ins->backend.pc_offset = code - cfg->native_code;
4554                         break;
4555                 }
4556                 case OP_CHECK_THIS:
4557                         /* ensure ins->sreg1 is not NULL */
4558                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4559                         break;
4560                 case OP_ARGLIST: {
4561                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4562                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4563                         break;
4564                 }
4565                 case OP_CALL:
4566                 case OP_FCALL:
4567                 case OP_RCALL:
4568                 case OP_LCALL:
4569                 case OP_VCALL:
4570                 case OP_VCALL2:
4571                 case OP_VOIDCALL:
4572                         call = (MonoCallInst*)ins;
4573                         /*
4574                          * The AMD64 ABI forces callers to know about varargs.
4575                          */
4576                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4577                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4578                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4579                                 /*
4580                                  * Since the unmanaged calling convention doesn't contain a
4581                                  * 'vararg' entry, we have to treat every pinvoke call as a
4582                                  * potential vararg call.
4583                                  */
4584                                 guint32 nregs, i;
4585                                 nregs = 0;
4586                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4587                                         if (call->used_fregs & (1 << i))
4588                                                 nregs ++;
4589                                 if (!nregs)
4590                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4591                                 else
4592                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4593                         }
4594
4595                         if (ins->flags & MONO_INST_HAS_METHOD)
4596                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4597                         else
4598                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4599                         ins->flags |= MONO_INST_GC_CALLSITE;
4600                         ins->backend.pc_offset = code - cfg->native_code;
4601                         code = emit_move_return_value (cfg, ins, code);
4602                         break;
4603                 case OP_FCALL_REG:
4604                 case OP_RCALL_REG:
4605                 case OP_LCALL_REG:
4606                 case OP_VCALL_REG:
4607                 case OP_VCALL2_REG:
4608                 case OP_VOIDCALL_REG:
4609                 case OP_CALL_REG:
4610                         call = (MonoCallInst*)ins;
4611
4612                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4613                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4614                                 ins->sreg1 = AMD64_R11;
4615                         }
4616
4617                         /*
4618                          * The AMD64 ABI forces callers to know about varargs.
4619                          */
4620                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4621                                 if (ins->sreg1 == AMD64_RAX) {
4622                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4623                                         ins->sreg1 = AMD64_R11;
4624                                 }
4625                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4626                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4627                                 /*
4628                                  * Since the unmanaged calling convention doesn't contain a
4629                                  * 'vararg' entry, we have to treat every pinvoke call as a
4630                                  * potential vararg call.
4631                                  */
4632                                 guint32 nregs, i;
4633                                 nregs = 0;
4634                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4635                                         if (call->used_fregs & (1 << i))
4636                                                 nregs ++;
4637                                 if (ins->sreg1 == AMD64_RAX) {
4638                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4639                                         ins->sreg1 = AMD64_R11;
4640                                 }
4641                                 if (!nregs)
4642                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4643                                 else
4644                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4645                         }
4646
4647                         amd64_call_reg (code, ins->sreg1);
4648                         ins->flags |= MONO_INST_GC_CALLSITE;
4649                         ins->backend.pc_offset = code - cfg->native_code;
4650                         code = emit_move_return_value (cfg, ins, code);
4651                         break;
4652                 case OP_FCALL_MEMBASE:
4653                 case OP_RCALL_MEMBASE:
4654                 case OP_LCALL_MEMBASE:
4655                 case OP_VCALL_MEMBASE:
4656                 case OP_VCALL2_MEMBASE:
4657                 case OP_VOIDCALL_MEMBASE:
4658                 case OP_CALL_MEMBASE:
4659                         call = (MonoCallInst*)ins;
4660
4661                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4662                         ins->flags |= MONO_INST_GC_CALLSITE;
4663                         ins->backend.pc_offset = code - cfg->native_code;
4664                         code = emit_move_return_value (cfg, ins, code);
4665                         break;
4666                 case OP_DYN_CALL: {
4667                         int i;
4668                         MonoInst *var = cfg->dyn_call_var;
4669                         guint8 *label;
4670
4671                         g_assert (var->opcode == OP_REGOFFSET);
4672
4673                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4674                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4675                         /* r10 = ftn */
4676                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4677
4678                         /* Save args buffer */
4679                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4680
4681                         /* Set fp arg regs */
4682                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4683                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4684                         label = code;
4685                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4686                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4687                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4688                         amd64_patch (label, code);
4689
4690                         /* Set argument registers */
4691                         for (i = 0; i < PARAM_REGS; ++i)
4692                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4693
4694                         /* Make the call */
4695                         amd64_call_reg (code, AMD64_R10);
4696
4697                         ins->flags |= MONO_INST_GC_CALLSITE;
4698                         ins->backend.pc_offset = code - cfg->native_code;
4699
4700                         /* Save result */
4701                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4702                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4703                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4704                         break;
4705                 }
4706                 case OP_AMD64_SAVE_SP_TO_LMF: {
4707                         MonoInst *lmf_var = cfg->lmf_var;
4708                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4709                         break;
4710                 }
4711                 case OP_X86_PUSH:
4712                         g_assert_not_reached ();
4713                         amd64_push_reg (code, ins->sreg1);
4714                         break;
4715                 case OP_X86_PUSH_IMM:
4716                         g_assert_not_reached ();
4717                         g_assert (amd64_is_imm32 (ins->inst_imm));
4718                         amd64_push_imm (code, ins->inst_imm);
4719                         break;
4720                 case OP_X86_PUSH_MEMBASE:
4721                         g_assert_not_reached ();
4722                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4723                         break;
4724                 case OP_X86_PUSH_OBJ: {
4725                         int size = ALIGN_TO (ins->inst_imm, 8);
4726
4727                         g_assert_not_reached ();
4728
4729                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4730                         amd64_push_reg (code, AMD64_RDI);
4731                         amd64_push_reg (code, AMD64_RSI);
4732                         amd64_push_reg (code, AMD64_RCX);
4733                         if (ins->inst_offset)
4734                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4735                         else
4736                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4737                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4738                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4739                         amd64_cld (code);
4740                         amd64_prefix (code, X86_REP_PREFIX);
4741                         amd64_movsd (code);
4742                         amd64_pop_reg (code, AMD64_RCX);
4743                         amd64_pop_reg (code, AMD64_RSI);
4744                         amd64_pop_reg (code, AMD64_RDI);
4745                         break;
4746                 }
4747                 case OP_GENERIC_CLASS_INIT: {
4748                         static int byte_offset = -1;
4749                         static guint8 bitmask;
4750                         guint8 *jump;
4751
4752                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4753
4754                         if (byte_offset < 0)
4755                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4756
4757                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4758                         jump = code;
4759                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4760
4761                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4762                         ins->flags |= MONO_INST_GC_CALLSITE;
4763                         ins->backend.pc_offset = code - cfg->native_code;
4764
4765                         x86_patch (jump, code);
4766                         break;
4767                 }
4768
4769                 case OP_X86_LEA:
4770                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4771                         break;
4772                 case OP_X86_LEA_MEMBASE:
4773                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4774                         break;
4775                 case OP_X86_XCHG:
4776                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4777                         break;
4778                 case OP_LOCALLOC:
4779                         /* keep alignment */
4780                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4781                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4782                         code = mono_emit_stack_alloc (cfg, code, ins);
4783                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4784                         if (cfg->param_area)
4785                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4786                         break;
4787                 case OP_LOCALLOC_IMM: {
4788                         guint32 size = ins->inst_imm;
4789                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4790
4791                         if (ins->flags & MONO_INST_INIT) {
4792                                 if (size < 64) {
4793                                         int i;
4794
4795                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4796                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4797
4798                                         for (i = 0; i < size; i += 8)
4799                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4800                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4801                                 } else {
4802                                         amd64_mov_reg_imm (code, ins->dreg, size);
4803                                         ins->sreg1 = ins->dreg;
4804
4805                                         code = mono_emit_stack_alloc (cfg, code, ins);
4806                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4807                                 }
4808                         } else {
4809                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4810                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4811                         }
4812                         if (cfg->param_area)
4813                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4814                         break;
4815                 }
4816                 case OP_THROW: {
4817                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4818                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4819                                              (gpointer)"mono_arch_throw_exception", FALSE);
4820                         ins->flags |= MONO_INST_GC_CALLSITE;
4821                         ins->backend.pc_offset = code - cfg->native_code;
4822                         break;
4823                 }
4824                 case OP_RETHROW: {
4825                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4826                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4827                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4828                         ins->flags |= MONO_INST_GC_CALLSITE;
4829                         ins->backend.pc_offset = code - cfg->native_code;
4830                         break;
4831                 }
4832                 case OP_CALL_HANDLER:
4833                         /* Align stack */
4834                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4835                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4836                         amd64_call_imm (code, 0);
4837                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4838                         /* Restore stack alignment */
4839                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4840                         break;
4841                 case OP_START_HANDLER: {
4842                         /* Even though we're saving RSP, use sizeof */
4843                         /* gpointer because spvar is of type IntPtr */
4844                         /* see: mono_create_spvar_for_region */
4845                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4846                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4847
4848                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4849                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4850                                 cfg->param_area) {
4851                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4852                         }
4853                         break;
4854                 }
4855                 case OP_ENDFINALLY: {
4856                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4857                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4858                         amd64_ret (code);
4859                         break;
4860                 }
4861                 case OP_ENDFILTER: {
4862                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4863                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4864                         /* The local allocator will put the result into RAX */
4865                         amd64_ret (code);
4866                         break;
4867                 }
4868                 case OP_GET_EX_OBJ:
4869                         if (ins->dreg != AMD64_RAX)
4870                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4871                         break;
4872                 case OP_LABEL:
4873                         ins->inst_c0 = code - cfg->native_code;
4874                         break;
4875                 case OP_BR:
4876                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4877                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4878                         //break;
4879                                 if (ins->inst_target_bb->native_offset) {
4880                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4881                                 } else {
4882                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4883                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4884                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4885                                                 x86_jump8 (code, 0);
4886                                         else
4887                                                 x86_jump32 (code, 0);
4888                         }
4889                         break;
4890                 case OP_BR_REG:
4891                         amd64_jump_reg (code, ins->sreg1);
4892                         break;
4893                 case OP_ICNEQ:
4894                 case OP_ICGE:
4895                 case OP_ICLE:
4896                 case OP_ICGE_UN:
4897                 case OP_ICLE_UN:
4898
4899                 case OP_CEQ:
4900                 case OP_LCEQ:
4901                 case OP_ICEQ:
4902                 case OP_CLT:
4903                 case OP_LCLT:
4904                 case OP_ICLT:
4905                 case OP_CGT:
4906                 case OP_ICGT:
4907                 case OP_LCGT:
4908                 case OP_CLT_UN:
4909                 case OP_LCLT_UN:
4910                 case OP_ICLT_UN:
4911                 case OP_CGT_UN:
4912                 case OP_LCGT_UN:
4913                 case OP_ICGT_UN:
4914                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4915                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4916                         break;
4917                 case OP_COND_EXC_EQ:
4918                 case OP_COND_EXC_NE_UN:
4919                 case OP_COND_EXC_LT:
4920                 case OP_COND_EXC_LT_UN:
4921                 case OP_COND_EXC_GT:
4922                 case OP_COND_EXC_GT_UN:
4923                 case OP_COND_EXC_GE:
4924                 case OP_COND_EXC_GE_UN:
4925                 case OP_COND_EXC_LE:
4926                 case OP_COND_EXC_LE_UN:
4927                 case OP_COND_EXC_IEQ:
4928                 case OP_COND_EXC_INE_UN:
4929                 case OP_COND_EXC_ILT:
4930                 case OP_COND_EXC_ILT_UN:
4931                 case OP_COND_EXC_IGT:
4932                 case OP_COND_EXC_IGT_UN:
4933                 case OP_COND_EXC_IGE:
4934                 case OP_COND_EXC_IGE_UN:
4935                 case OP_COND_EXC_ILE:
4936                 case OP_COND_EXC_ILE_UN:
4937                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4938                         break;
4939                 case OP_COND_EXC_OV:
4940                 case OP_COND_EXC_NO:
4941                 case OP_COND_EXC_C:
4942                 case OP_COND_EXC_NC:
4943                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4944                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4945                         break;
4946                 case OP_COND_EXC_IOV:
4947                 case OP_COND_EXC_INO:
4948                 case OP_COND_EXC_IC:
4949                 case OP_COND_EXC_INC:
4950                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4951                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4952                         break;
4953
4954                 /* floating point opcodes */
4955                 case OP_R8CONST: {
4956                         double d = *(double *)ins->inst_p0;
4957
4958                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4959                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4960                         }
4961                         else {
4962                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4963                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4964                         }
4965                         break;
4966                 }
4967                 case OP_R4CONST: {
4968                         float f = *(float *)ins->inst_p0;
4969
4970                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4971                                 if (cfg->r4fp)
4972                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4973                                 else
4974                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4975                         }
4976                         else {
4977                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4978                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4979                                 if (!cfg->r4fp)
4980                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4981                         }
4982                         break;
4983                 }
4984                 case OP_STORER8_MEMBASE_REG:
4985                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4986                         break;
4987                 case OP_LOADR8_MEMBASE:
4988                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4989                         break;
4990                 case OP_STORER4_MEMBASE_REG:
4991                         if (cfg->r4fp) {
4992                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4993                         } else {
4994                                 /* This requires a double->single conversion */
4995                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4996                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4997                         }
4998                         break;
4999                 case OP_LOADR4_MEMBASE:
5000                         if (cfg->r4fp) {
5001                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5002                         } else {
5003                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5004                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5005                         }
5006                         break;
5007                 case OP_ICONV_TO_R4:
5008                         if (cfg->r4fp) {
5009                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5010                         } else {
5011                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5012                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5013                         }
5014                         break;
5015                 case OP_ICONV_TO_R8:
5016                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5017                         break;
5018                 case OP_LCONV_TO_R4:
5019                         if (cfg->r4fp) {
5020                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5021                         } else {
5022                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5023                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5024                         }
5025                         break;
5026                 case OP_LCONV_TO_R8:
5027                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5028                         break;
5029                 case OP_FCONV_TO_R4:
5030                         if (cfg->r4fp) {
5031                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5032                         } else {
5033                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5034                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5035                         }
5036                         break;
5037                 case OP_FCONV_TO_I1:
5038                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5039                         break;
5040                 case OP_FCONV_TO_U1:
5041                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5042                         break;
5043                 case OP_FCONV_TO_I2:
5044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5045                         break;
5046                 case OP_FCONV_TO_U2:
5047                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5048                         break;
5049                 case OP_FCONV_TO_U4:
5050                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5051                         break;
5052                 case OP_FCONV_TO_I4:
5053                 case OP_FCONV_TO_I:
5054                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5055                         break;
5056                 case OP_FCONV_TO_I8:
5057                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5058                         break;
5059
5060                 case OP_RCONV_TO_I1:
5061                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5062                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5063                         break;
5064                 case OP_RCONV_TO_U1:
5065                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5066                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5067                         break;
5068                 case OP_RCONV_TO_I2:
5069                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5070                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5071                         break;
5072                 case OP_RCONV_TO_U2:
5073                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5074                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5075                         break;
5076                 case OP_RCONV_TO_I4:
5077                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5078                         break;
5079                 case OP_RCONV_TO_U4:
5080                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5081                         break;
5082                 case OP_RCONV_TO_I8:
5083                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5084                         break;
5085                 case OP_RCONV_TO_R8:
5086                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5087                         break;
5088                 case OP_RCONV_TO_R4:
5089                         if (ins->dreg != ins->sreg1)
5090                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5091                         break;
5092
5093                 case OP_LCONV_TO_R_UN: {
5094                         guint8 *br [2];
5095
5096                         /* Based on gcc code */
5097                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5098                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5099
5100                         /* Positive case */
5101                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5102                         br [1] = code; x86_jump8 (code, 0);
5103                         amd64_patch (br [0], code);
5104
5105                         /* Negative case */
5106                         /* Save to the red zone */
5107                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5108                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5109                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5110                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5111                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5112                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5113                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5114                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5115                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5116                         /* Restore */
5117                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5118                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5119                         amd64_patch (br [1], code);
5120                         break;
5121                 }
5122                 case OP_LCONV_TO_OVF_U4:
5123                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5124                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5125                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5126                         break;
5127                 case OP_LCONV_TO_OVF_I4_UN:
5128                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5129                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5130                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5131                         break;
5132                 case OP_FMOVE:
5133                         if (ins->dreg != ins->sreg1)
5134                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5135                         break;
5136                 case OP_RMOVE:
5137                         if (ins->dreg != ins->sreg1)
5138                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5139                         break;
5140                 case OP_MOVE_F_TO_I4:
5141                         if (cfg->r4fp) {
5142                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5143                         } else {
5144                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5145                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5146                         }
5147                         break;
5148                 case OP_MOVE_I4_TO_F:
5149                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5150                         if (!cfg->r4fp)
5151                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5152                         break;
5153                 case OP_MOVE_F_TO_I8:
5154                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5155                         break;
5156                 case OP_MOVE_I8_TO_F:
5157                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5158                         break;
5159                 case OP_FADD:
5160                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5161                         break;
5162                 case OP_FSUB:
5163                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5164                         break;
5165                 case OP_FMUL:
5166                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5167                         break;
5168                 case OP_FDIV:
5169                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5170                         break;
5171                 case OP_FNEG: {
5172                         static double r8_0 = -0.0;
5173
5174                         g_assert (ins->sreg1 == ins->dreg);
5175
5176                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5177                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5178                         break;
5179                 }
5180                 case OP_SIN:
5181                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5182                         break;
5183                 case OP_COS:
5184                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5185                         break;
5186                 case OP_ABS: {
5187                         static guint64 d = 0x7fffffffffffffffUL;
5188
5189                         g_assert (ins->sreg1 == ins->dreg);
5190
5191                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5192                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5193                         break;
5194                 }
5195                 case OP_SQRT:
5196                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5197                         break;
5198
5199                 case OP_RADD:
5200                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5201                         break;
5202                 case OP_RSUB:
5203                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5204                         break;
5205                 case OP_RMUL:
5206                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5207                         break;
5208                 case OP_RDIV:
5209                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5210                         break;
5211                 case OP_RNEG: {
5212                         static float r4_0 = -0.0;
5213
5214                         g_assert (ins->sreg1 == ins->dreg);
5215
5216                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5217                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5218                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5219                         break;
5220                 }
5221
5222                 case OP_IMIN:
5223                         g_assert (cfg->opt & MONO_OPT_CMOV);
5224                         g_assert (ins->dreg == ins->sreg1);
5225                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5226                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5227                         break;
5228                 case OP_IMIN_UN:
5229                         g_assert (cfg->opt & MONO_OPT_CMOV);
5230                         g_assert (ins->dreg == ins->sreg1);
5231                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5232                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5233                         break;
5234                 case OP_IMAX:
5235                         g_assert (cfg->opt & MONO_OPT_CMOV);
5236                         g_assert (ins->dreg == ins->sreg1);
5237                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5238                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5239                         break;
5240                 case OP_IMAX_UN:
5241                         g_assert (cfg->opt & MONO_OPT_CMOV);
5242                         g_assert (ins->dreg == ins->sreg1);
5243                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5244                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5245                         break;
5246                 case OP_LMIN:
5247                         g_assert (cfg->opt & MONO_OPT_CMOV);
5248                         g_assert (ins->dreg == ins->sreg1);
5249                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5250                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5251                         break;
5252                 case OP_LMIN_UN:
5253                         g_assert (cfg->opt & MONO_OPT_CMOV);
5254                         g_assert (ins->dreg == ins->sreg1);
5255                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5256                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5257                         break;
5258                 case OP_LMAX:
5259                         g_assert (cfg->opt & MONO_OPT_CMOV);
5260                         g_assert (ins->dreg == ins->sreg1);
5261                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5262                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5263                         break;
5264                 case OP_LMAX_UN:
5265                         g_assert (cfg->opt & MONO_OPT_CMOV);
5266                         g_assert (ins->dreg == ins->sreg1);
5267                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5268                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5269                         break;
5270                 case OP_X86_FPOP:
5271                         break;
5272                 case OP_FCOMPARE:
5273                         /*
5274                          * The two arguments are swapped because the fbranch instructions
5275                          * depend on this for the non-sse case to work.
5276                          */
5277                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5278                         break;
5279                 case OP_RCOMPARE:
5280                         /*
5281                          * FIXME: Get rid of this.
5282                          * The two arguments are swapped because the fbranch instructions
5283                          * depend on this for the non-sse case to work.
5284                          */
5285                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5286                         break;
5287                 case OP_FCNEQ:
5288                 case OP_FCEQ: {
5289                         /* zeroing the register at the start results in
5290                          * shorter and faster code (we can also remove the widening op)
5291                          */
5292                         guchar *unordered_check;
5293
5294                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5295                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         unordered_check = code;
5297                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5298
5299                         if (ins->opcode == OP_FCEQ) {
5300                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5301                                 amd64_patch (unordered_check, code);
5302                         } else {
5303                                 guchar *jump_to_end;
5304                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5305                                 jump_to_end = code;
5306                                 x86_jump8 (code, 0);
5307                                 amd64_patch (unordered_check, code);
5308                                 amd64_inc_reg (code, ins->dreg);
5309                                 amd64_patch (jump_to_end, code);
5310                         }
5311                         break;
5312                 }
5313                 case OP_FCLT:
5314                 case OP_FCLT_UN: {
5315                         /* zeroing the register at the start results in
5316                          * shorter and faster code (we can also remove the widening op)
5317                          */
5318                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5319                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5320                         if (ins->opcode == OP_FCLT_UN) {
5321                                 guchar *unordered_check = code;
5322                                 guchar *jump_to_end;
5323                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5324                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5325                                 jump_to_end = code;
5326                                 x86_jump8 (code, 0);
5327                                 amd64_patch (unordered_check, code);
5328                                 amd64_inc_reg (code, ins->dreg);
5329                                 amd64_patch (jump_to_end, code);
5330                         } else {
5331                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5332                         }
5333                         break;
5334                 }
5335                 case OP_FCLE: {
5336                         guchar *unordered_check;
5337                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5338                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5339                         unordered_check = code;
5340                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5341                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5342                         amd64_patch (unordered_check, code);
5343                         break;
5344                 }
5345                 case OP_FCGT:
5346                 case OP_FCGT_UN: {
5347                         /* zeroing the register at the start results in
5348                          * shorter and faster code (we can also remove the widening op)
5349                          */
5350                         guchar *unordered_check;
5351
5352                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5353                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5354                         if (ins->opcode == OP_FCGT) {
5355                                 unordered_check = code;
5356                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5357                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5358                                 amd64_patch (unordered_check, code);
5359                         } else {
5360                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5361                         }
5362                         break;
5363                 }
5364                 case OP_FCGE: {
5365                         guchar *unordered_check;
5366                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5367                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5368                         unordered_check = code;
5369                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5370                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5371                         amd64_patch (unordered_check, code);
5372                         break;
5373                 }
5374
5375                 case OP_RCEQ:
5376                 case OP_RCGT:
5377                 case OP_RCLT:
5378                 case OP_RCLT_UN:
5379                 case OP_RCGT_UN: {
5380                         int x86_cond;
5381                         gboolean unordered = FALSE;
5382
5383                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5384                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5385
5386                         switch (ins->opcode) {
5387                         case OP_RCEQ:
5388                                 x86_cond = X86_CC_EQ;
5389                                 break;
5390                         case OP_RCGT:
5391                                 x86_cond = X86_CC_LT;
5392                                 break;
5393                         case OP_RCLT:
5394                                 x86_cond = X86_CC_GT;
5395                                 break;
5396                         case OP_RCLT_UN:
5397                                 x86_cond = X86_CC_GT;
5398                                 unordered = TRUE;
5399                                 break;
5400                         case OP_RCGT_UN:
5401                                 x86_cond = X86_CC_LT;
5402                                 unordered = TRUE;
5403                                 break;
5404                         default:
5405                                 g_assert_not_reached ();
5406                                 break;
5407                         }
5408
5409                         if (unordered) {
5410                                 guchar *unordered_check;
5411                                 guchar *jump_to_end;
5412
5413                                 unordered_check = code;
5414                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5415                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5416                                 jump_to_end = code;
5417                                 x86_jump8 (code, 0);
5418                                 amd64_patch (unordered_check, code);
5419                                 amd64_inc_reg (code, ins->dreg);
5420                                 amd64_patch (jump_to_end, code);
5421                         } else {
5422                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5423                         }
5424                         break;
5425                 }
5426                 case OP_FCLT_MEMBASE:
5427                 case OP_FCGT_MEMBASE:
5428                 case OP_FCLT_UN_MEMBASE:
5429                 case OP_FCGT_UN_MEMBASE:
5430                 case OP_FCEQ_MEMBASE: {
5431                         guchar *unordered_check, *jump_to_end;
5432                         int x86_cond;
5433
5434                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5435                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5436
5437                         switch (ins->opcode) {
5438                         case OP_FCEQ_MEMBASE:
5439                                 x86_cond = X86_CC_EQ;
5440                                 break;
5441                         case OP_FCLT_MEMBASE:
5442                         case OP_FCLT_UN_MEMBASE:
5443                                 x86_cond = X86_CC_LT;
5444                                 break;
5445                         case OP_FCGT_MEMBASE:
5446                         case OP_FCGT_UN_MEMBASE:
5447                                 x86_cond = X86_CC_GT;
5448                                 break;
5449                         default:
5450                                 g_assert_not_reached ();
5451                         }
5452
5453                         unordered_check = code;
5454                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5455                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5456
5457                         switch (ins->opcode) {
5458                         case OP_FCEQ_MEMBASE:
5459                         case OP_FCLT_MEMBASE:
5460                         case OP_FCGT_MEMBASE:
5461                                 amd64_patch (unordered_check, code);
5462                                 break;
5463                         case OP_FCLT_UN_MEMBASE:
5464                         case OP_FCGT_UN_MEMBASE:
5465                                 jump_to_end = code;
5466                                 x86_jump8 (code, 0);
5467                                 amd64_patch (unordered_check, code);
5468                                 amd64_inc_reg (code, ins->dreg);
5469                                 amd64_patch (jump_to_end, code);
5470                                 break;
5471                         default:
5472                                 break;
5473                         }
5474                         break;
5475                 }
5476                 case OP_FBEQ: {
5477                         guchar *jump = code;
5478                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5479                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5480                         amd64_patch (jump, code);
5481                         break;
5482                 }
5483                 case OP_FBNE_UN:
5484                         /* Branch if C013 != 100 */
5485                         /* branch if !ZF or (PF|CF) */
5486                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5487                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5488                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5489                         break;
5490                 case OP_FBLT:
5491                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5492                         break;
5493                 case OP_FBLT_UN:
5494                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5495                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5496                         break;
5497                 case OP_FBGT:
5498                 case OP_FBGT_UN:
5499                         if (ins->opcode == OP_FBGT) {
5500                                 guchar *br1;
5501
5502                                 /* skip branch if C1=1 */
5503                                 br1 = code;
5504                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5505                                 /* branch if (C0 | C3) = 1 */
5506                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5507                                 amd64_patch (br1, code);
5508                                 break;
5509                         } else {
5510                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5511                         }
5512                         break;
5513                 case OP_FBGE: {
5514                         /* Branch if C013 == 100 or 001 */
5515                         guchar *br1;
5516
5517                         /* skip branch if C1=1 */
5518                         br1 = code;
5519                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5520                         /* branch if (C0 | C3) = 1 */
5521                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5522                         amd64_patch (br1, code);
5523                         break;
5524                 }
5525                 case OP_FBGE_UN:
5526                         /* Branch if C013 == 000 */
5527                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5528                         break;
5529                 case OP_FBLE: {
5530                         /* Branch if C013=000 or 100 */
5531                         guchar *br1;
5532
5533                         /* skip branch if C1=1 */
5534                         br1 = code;
5535                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5536                         /* branch if C0=0 */
5537                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5538                         amd64_patch (br1, code);
5539                         break;
5540                 }
5541                 case OP_FBLE_UN:
5542                         /* Branch if C013 != 001 */
5543                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5544                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5545                         break;
5546                 case OP_CKFINITE:
5547                         /* Transfer value to the fp stack */
5548                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5549                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5550                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5551
5552                         amd64_push_reg (code, AMD64_RAX);
5553                         amd64_fxam (code);
5554                         amd64_fnstsw (code);
5555                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5556                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5557                         amd64_pop_reg (code, AMD64_RAX);
5558                         amd64_fstp (code, 0);
5559                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5560                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5561                         break;
5562                 case OP_TLS_GET: {
5563                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5564                         break;
5565                 }
5566                 case OP_TLS_GET_REG:
5567                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5568                         break;
5569                 case OP_TLS_SET: {
5570                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5571                         break;
5572                 }
5573                 case OP_TLS_SET_REG: {
5574                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5575                         break;
5576                 }
5577                 case OP_MEMORY_BARRIER: {
5578                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5579                                 x86_mfence (code);
5580                         break;
5581                 }
5582                 case OP_ATOMIC_ADD_I4:
5583                 case OP_ATOMIC_ADD_I8: {
5584                         int dreg = ins->dreg;
5585                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5586
5587                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5588                                 dreg = AMD64_R11;
5589
5590                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5591                         amd64_prefix (code, X86_LOCK_PREFIX);
5592                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5593                         /* dreg contains the old value, add with sreg2 value */
5594                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5595
5596                         if (ins->dreg != dreg)
5597                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5598
5599                         break;
5600                 }
5601                 case OP_ATOMIC_EXCHANGE_I4:
5602                 case OP_ATOMIC_EXCHANGE_I8: {
5603                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5604
5605                         /* LOCK prefix is implied. */
5606                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5607                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5608                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5609                         break;
5610                 }
5611                 case OP_ATOMIC_CAS_I4:
5612                 case OP_ATOMIC_CAS_I8: {
5613                         guint32 size;
5614
5615                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5616                                 size = 8;
5617                         else
5618                                 size = 4;
5619
5620                         /*
5621                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5622                          * an explanation of how this works.
5623                          */
5624                         g_assert (ins->sreg3 == AMD64_RAX);
5625                         g_assert (ins->sreg1 != AMD64_RAX);
5626                         g_assert (ins->sreg1 != ins->sreg2);
5627
5628                         amd64_prefix (code, X86_LOCK_PREFIX);
5629                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5630
5631                         if (ins->dreg != AMD64_RAX)
5632                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5633                         break;
5634                 }
5635                 case OP_ATOMIC_LOAD_I1: {
5636                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5637                         break;
5638                 }
5639                 case OP_ATOMIC_LOAD_U1: {
5640                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5641                         break;
5642                 }
5643                 case OP_ATOMIC_LOAD_I2: {
5644                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5645                         break;
5646                 }
5647                 case OP_ATOMIC_LOAD_U2: {
5648                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5649                         break;
5650                 }
5651                 case OP_ATOMIC_LOAD_I4: {
5652                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5653                         break;
5654                 }
5655                 case OP_ATOMIC_LOAD_U4:
5656                 case OP_ATOMIC_LOAD_I8:
5657                 case OP_ATOMIC_LOAD_U8: {
5658                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5659                         break;
5660                 }
5661                 case OP_ATOMIC_LOAD_R4: {
5662                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5663                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5664                         break;
5665                 }
5666                 case OP_ATOMIC_LOAD_R8: {
5667                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5668                         break;
5669                 }
5670                 case OP_ATOMIC_STORE_I1:
5671                 case OP_ATOMIC_STORE_U1:
5672                 case OP_ATOMIC_STORE_I2:
5673                 case OP_ATOMIC_STORE_U2:
5674                 case OP_ATOMIC_STORE_I4:
5675                 case OP_ATOMIC_STORE_U4:
5676                 case OP_ATOMIC_STORE_I8:
5677                 case OP_ATOMIC_STORE_U8: {
5678                         int size;
5679
5680                         switch (ins->opcode) {
5681                         case OP_ATOMIC_STORE_I1:
5682                         case OP_ATOMIC_STORE_U1:
5683                                 size = 1;
5684                                 break;
5685                         case OP_ATOMIC_STORE_I2:
5686                         case OP_ATOMIC_STORE_U2:
5687                                 size = 2;
5688                                 break;
5689                         case OP_ATOMIC_STORE_I4:
5690                         case OP_ATOMIC_STORE_U4:
5691                                 size = 4;
5692                                 break;
5693                         case OP_ATOMIC_STORE_I8:
5694                         case OP_ATOMIC_STORE_U8:
5695                                 size = 8;
5696                                 break;
5697                         }
5698
5699                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5700
5701                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5702                                 x86_mfence (code);
5703                         break;
5704                 }
5705                 case OP_ATOMIC_STORE_R4: {
5706                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5707                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5708
5709                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5710                                 x86_mfence (code);
5711                         break;
5712                 }
5713                 case OP_ATOMIC_STORE_R8: {
5714                         x86_nop (code);
5715                         x86_nop (code);
5716                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5717                         x86_nop (code);
5718                         x86_nop (code);
5719
5720                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5721                                 x86_mfence (code);
5722                         break;
5723                 }
5724                 case OP_CARD_TABLE_WBARRIER: {
5725                         int ptr = ins->sreg1;
5726                         int value = ins->sreg2;
5727                         guchar *br = 0;
5728                         int nursery_shift, card_table_shift;
5729                         gpointer card_table_mask;
5730                         size_t nursery_size;
5731
5732                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5733                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5734                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5735
5736                         /*If either point to the stack we can simply avoid the WB. This happens due to
5737                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5738                          */
5739                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5740                                 continue;
5741
5742                         /*
5743                          * We need one register we can clobber, we choose EDX and make sreg1
5744                          * fixed EAX to work around limitations in the local register allocator.
5745                          * sreg2 might get allocated to EDX, but that is not a problem since
5746                          * we use it before clobbering EDX.
5747                          */
5748                         g_assert (ins->sreg1 == AMD64_RAX);
5749
5750                         /*
5751                          * This is the code we produce:
5752                          *
5753                          *   edx = value
5754                          *   edx >>= nursery_shift
5755                          *   cmp edx, (nursery_start >> nursery_shift)
5756                          *   jne done
5757                          *   edx = ptr
5758                          *   edx >>= card_table_shift
5759                          *   edx += cardtable
5760                          *   [edx] = 1
5761                          * done:
5762                          */
5763
5764                         if (mono_gc_card_table_nursery_check ()) {
5765                                 if (value != AMD64_RDX)
5766                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5767                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5768                                 if (shifted_nursery_start >> 31) {
5769                                         /*
5770                                          * The value we need to compare against is 64 bits, so we need
5771                                          * another spare register.  We use RBX, which we save and
5772                                          * restore.
5773                                          */
5774                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5775                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5776                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5777                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5778                                 } else {
5779                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5780                                 }
5781                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5782                         }
5783                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5784                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5785                         if (card_table_mask)
5786                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5787
5788                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5789                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5790
5791                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5792
5793                         if (mono_gc_card_table_nursery_check ())
5794                                 x86_patch (br, code);
5795                         break;
5796                 }
5797 #ifdef MONO_ARCH_SIMD_INTRINSICS
5798                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5799                 case OP_ADDPS:
5800                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_DIVPS:
5803                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_MULPS:
5806                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_SUBPS:
5809                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5810                         break;
5811                 case OP_MAXPS:
5812                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5813                         break;
5814                 case OP_MINPS:
5815                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5816                         break;
5817                 case OP_COMPPS:
5818                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5819                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5820                         break;
5821                 case OP_ANDPS:
5822                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_ANDNPS:
5825                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_ORPS:
5828                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5829                         break;
5830                 case OP_XORPS:
5831                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5832                         break;
5833                 case OP_SQRTPS:
5834                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5835                         break;
5836                 case OP_RSQRTPS:
5837                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5838                         break;
5839                 case OP_RCPPS:
5840                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5841                         break;
5842                 case OP_ADDSUBPS:
5843                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845                 case OP_HADDPS:
5846                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_HSUBPS:
5849                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851                 case OP_DUPPS_HIGH:
5852                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5853                         break;
5854                 case OP_DUPPS_LOW:
5855                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5856                         break;
5857
5858                 case OP_PSHUFLEW_HIGH:
5859                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5860                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5861                         break;
5862                 case OP_PSHUFLEW_LOW:
5863                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5864                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5865                         break;
5866                 case OP_PSHUFLED:
5867                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5868                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5869                         break;
5870                 case OP_SHUFPS:
5871                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5872                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5873                         break;
5874                 case OP_SHUFPD:
5875                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5876                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5877                         break;
5878
5879                 case OP_ADDPD:
5880                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_DIVPD:
5883                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_MULPD:
5886                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887                         break;
5888                 case OP_SUBPD:
5889                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5890                         break;
5891                 case OP_MAXPD:
5892                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_MINPD:
5895                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_COMPPD:
5898                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5899                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5900                         break;
5901                 case OP_ANDPD:
5902                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_ANDNPD:
5905                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_ORPD:
5908                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_XORPD:
5911                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_SQRTPD:
5914                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5915                         break;
5916                 case OP_ADDSUBPD:
5917                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_HADDPD:
5920                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_HSUBPD:
5923                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_DUPPD:
5926                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5927                         break;
5928
5929                 case OP_EXTRACT_MASK:
5930                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5931                         break;
5932
5933                 case OP_PAND:
5934                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_POR:
5937                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PXOR:
5940                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942
5943                 case OP_PADDB:
5944                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PADDW:
5947                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_PADDD:
5950                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PADDQ:
5953                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955
5956                 case OP_PSUBB:
5957                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_PSUBW:
5960                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PSUBD:
5963                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PSUBQ:
5966                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PMAXB_UN:
5970                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PMAXW_UN:
5973                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMAXD_UN:
5976                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_PMAXB:
5980                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PMAXW:
5983                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PMAXD:
5986                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988
5989                 case OP_PAVGB_UN:
5990                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_PAVGW_UN:
5993                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995
5996                 case OP_PMINB_UN:
5997                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_PMINW_UN:
6000                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PMIND_UN:
6003                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005
6006                 case OP_PMINB:
6007                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_PMINW:
6010                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PMIND:
6013                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015
6016                 case OP_PCMPEQB:
6017                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_PCMPEQW:
6020                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_PCMPEQD:
6023                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_PCMPEQQ:
6026                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028
6029                 case OP_PCMPGTB:
6030                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_PCMPGTW:
6033                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PCMPGTD:
6036                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_PCMPGTQ:
6039                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041
6042                 case OP_PSUM_ABS_DIFF:
6043                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045
6046                 case OP_UNPACK_LOWB:
6047                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_UNPACK_LOWW:
6050                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_UNPACK_LOWD:
6053                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_UNPACK_LOWQ:
6056                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058                 case OP_UNPACK_LOWPS:
6059                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_UNPACK_LOWPD:
6062                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064
6065                 case OP_UNPACK_HIGHB:
6066                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_UNPACK_HIGHW:
6069                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_UNPACK_HIGHD:
6072                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_UNPACK_HIGHQ:
6075                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_UNPACK_HIGHPS:
6078                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_UNPACK_HIGHPD:
6081                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083
6084                 case OP_PACKW:
6085                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PACKD:
6088                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PACKW_UN:
6091                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PACKD_UN:
6094                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096
6097                 case OP_PADDB_SAT_UN:
6098                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PSUBB_SAT_UN:
6101                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_PADDW_SAT_UN:
6104                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PSUBW_SAT_UN:
6107                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109
6110                 case OP_PADDB_SAT:
6111                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113                 case OP_PSUBB_SAT:
6114                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_PADDW_SAT:
6117                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PSUBW_SAT:
6120                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122
6123                 case OP_PMULW:
6124                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PMULD:
6127                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PMULQ:
6130                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PMULW_HIGH_UN:
6133                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_PMULW_HIGH:
6136                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138
6139                 case OP_PSHRW:
6140                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6141                         break;
6142                 case OP_PSHRW_REG:
6143                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6144                         break;
6145
6146                 case OP_PSARW:
6147                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6148                         break;
6149                 case OP_PSARW_REG:
6150                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6151                         break;
6152
6153                 case OP_PSHLW:
6154                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6155                         break;
6156                 case OP_PSHLW_REG:
6157                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6158                         break;
6159
6160                 case OP_PSHRD:
6161                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6162                         break;
6163                 case OP_PSHRD_REG:
6164                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6165                         break;
6166
6167                 case OP_PSARD:
6168                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6169                         break;
6170                 case OP_PSARD_REG:
6171                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6172                         break;
6173
6174                 case OP_PSHLD:
6175                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6176                         break;
6177                 case OP_PSHLD_REG:
6178                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6179                         break;
6180
6181                 case OP_PSHRQ:
6182                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6183                         break;
6184                 case OP_PSHRQ_REG:
6185                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6186                         break;
6187
6188                 /*TODO: This is appart of the sse spec but not added
6189                 case OP_PSARQ:
6190                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6191                         break;
6192                 case OP_PSARQ_REG:
6193                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6194                         break;
6195                 */
6196
6197                 case OP_PSHLQ:
6198                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6199                         break;
6200                 case OP_PSHLQ_REG:
6201                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6202                         break;
6203                 case OP_CVTDQ2PD:
6204                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206                 case OP_CVTDQ2PS:
6207                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6208                         break;
6209                 case OP_CVTPD2DQ:
6210                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6211                         break;
6212                 case OP_CVTPD2PS:
6213                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6214                         break;
6215                 case OP_CVTPS2DQ:
6216                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6217                         break;
6218                 case OP_CVTPS2PD:
6219                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6220                         break;
6221                 case OP_CVTTPD2DQ:
6222                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6223                         break;
6224                 case OP_CVTTPS2DQ:
6225                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6226                         break;
6227
6228                 case OP_ICONV_TO_X:
6229                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6230                         break;
6231                 case OP_EXTRACT_I4:
6232                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6233                         break;
6234                 case OP_EXTRACT_I8:
6235                         if (ins->inst_c0) {
6236                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6237                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6238                         } else {
6239                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6240                         }
6241                         break;
6242                 case OP_EXTRACT_I1:
6243                 case OP_EXTRACT_U1:
6244                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6245                         if (ins->inst_c0)
6246                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6247                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6248                         break;
6249                 case OP_EXTRACT_I2:
6250                 case OP_EXTRACT_U2:
6251                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6252                         if (ins->inst_c0)
6253                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6254                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6255                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6256                         break;
6257                 case OP_EXTRACT_R8:
6258                         if (ins->inst_c0)
6259                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6260                         else
6261                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6262                         break;
6263                 case OP_INSERT_I2:
6264                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6265                         break;
6266                 case OP_EXTRACTX_U2:
6267                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6268                         break;
6269                 case OP_INSERTX_U1_SLOW:
6270                         /*sreg1 is the extracted ireg (scratch)
6271                         /sreg2 is the to be inserted ireg (scratch)
6272                         /dreg is the xreg to receive the value*/
6273
6274                         /*clear the bits from the extracted word*/
6275                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6276                         /*shift the value to insert if needed*/
6277                         if (ins->inst_c0 & 1)
6278                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6279                         /*join them together*/
6280                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6281                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6282                         break;
6283                 case OP_INSERTX_I4_SLOW:
6284                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6285                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6286                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6287                         break;
6288                 case OP_INSERTX_I8_SLOW:
6289                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6290                         if (ins->inst_c0)
6291                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6292                         else
6293                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6294                         break;
6295
6296                 case OP_INSERTX_R4_SLOW:
6297                         switch (ins->inst_c0) {
6298                         case 0:
6299                                 if (cfg->r4fp)
6300                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6301                                 else
6302                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6303                                 break;
6304                         case 1:
6305                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6306                                 if (cfg->r4fp)
6307                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6308                                 else
6309                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6310                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6311                                 break;
6312                         case 2:
6313                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6314                                 if (cfg->r4fp)
6315                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6316                                 else
6317                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6318                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6319                                 break;
6320                         case 3:
6321                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6322                                 if (cfg->r4fp)
6323                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6324                                 else
6325                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6326                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6327                                 break;
6328                         }
6329                         break;
6330                 case OP_INSERTX_R8_SLOW:
6331                         if (ins->inst_c0)
6332                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6333                         else
6334                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6335                         break;
6336                 case OP_STOREX_MEMBASE_REG:
6337                 case OP_STOREX_MEMBASE:
6338                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6339                         break;
6340                 case OP_LOADX_MEMBASE:
6341                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6342                         break;
6343                 case OP_LOADX_ALIGNED_MEMBASE:
6344                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6345                         break;
6346                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6347                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6348                         break;
6349                 case OP_STOREX_NTA_MEMBASE_REG:
6350                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6351                         break;
6352                 case OP_PREFETCH_MEMBASE:
6353                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6354                         break;
6355
6356                 case OP_XMOVE:
6357                         /*FIXME the peephole pass should have killed this*/
6358                         if (ins->dreg != ins->sreg1)
6359                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6360                         break;
6361                 case OP_XZERO:
6362                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6363                         break;
6364                 case OP_ICONV_TO_R4_RAW:
6365                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6366                         break;
6367
6368                 case OP_FCONV_TO_R8_X:
6369                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6370                         break;
6371
6372                 case OP_XCONV_R8_TO_I4:
6373                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6374                         switch (ins->backend.source_opcode) {
6375                         case OP_FCONV_TO_I1:
6376                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6377                                 break;
6378                         case OP_FCONV_TO_U1:
6379                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6380                                 break;
6381                         case OP_FCONV_TO_I2:
6382                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6383                                 break;
6384                         case OP_FCONV_TO_U2:
6385                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6386                                 break;
6387                         }
6388                         break;
6389
6390                 case OP_EXPAND_I2:
6391                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6392                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6393                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6394                         break;
6395                 case OP_EXPAND_I4:
6396                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6397                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6398                         break;
6399                 case OP_EXPAND_I8:
6400                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6401                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6402                         break;
6403                 case OP_EXPAND_R4:
6404                         if (cfg->r4fp) {
6405                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6406                         } else {
6407                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6408                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6409                         }
6410                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6411                         break;
6412                 case OP_EXPAND_R8:
6413                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6414                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6415                         break;
6416 #endif
6417                 case OP_LIVERANGE_START: {
6418                         if (cfg->verbose_level > 1)
6419                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6420                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6421                         break;
6422                 }
6423                 case OP_LIVERANGE_END: {
6424                         if (cfg->verbose_level > 1)
6425                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6426                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6427                         break;
6428                 }
6429                 case OP_GC_SAFE_POINT: {
6430                         guint8 *br [1];
6431
6432                         g_assert (mono_threads_is_coop_enabled ());
6433
6434                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6435                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6436                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6437                         amd64_patch (br[0], code);
6438                         break;
6439                 }
6440
6441                 case OP_GC_LIVENESS_DEF:
6442                 case OP_GC_LIVENESS_USE:
6443                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6444                         ins->backend.pc_offset = code - cfg->native_code;
6445                         break;
6446                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6447                         ins->backend.pc_offset = code - cfg->native_code;
6448                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6449                         break;
6450                 default:
6451                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6452                         g_assert_not_reached ();
6453                 }
6454
6455                 if ((code - cfg->native_code - offset) > max_len) {
6456                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6457                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6458                         g_assert_not_reached ();
6459                 }
6460         }
6461
6462         cfg->code_len = code - cfg->native_code;
6463 }
6464
6465 #endif /* DISABLE_JIT */
6466
6467 void
6468 mono_arch_register_lowlevel_calls (void)
6469 {
6470         /* The signature doesn't matter */
6471         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6472 }
6473
6474 void
6475 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6476 {
6477         unsigned char *ip = ji->ip.i + code;
6478
6479         /*
6480          * Debug code to help track down problems where the target of a near call is
6481          * is not valid.
6482          */
6483         if (amd64_is_near_call (ip)) {
6484                 gint64 disp = (guint8*)target - (guint8*)ip;
6485
6486                 if (!amd64_is_imm32 (disp)) {
6487                         printf ("TYPE: %d\n", ji->type);
6488                         switch (ji->type) {
6489                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6490                                 printf ("V: %s\n", ji->data.name);
6491                                 break;
6492                         case MONO_PATCH_INFO_METHOD_JUMP:
6493                         case MONO_PATCH_INFO_METHOD:
6494                                 printf ("V: %s\n", ji->data.method->name);
6495                                 break;
6496                         default:
6497                                 break;
6498                         }
6499                 }
6500         }
6501
6502         amd64_patch (ip, (gpointer)target);
6503 }
6504
6505 #ifndef DISABLE_JIT
6506
6507 static int
6508 get_max_epilog_size (MonoCompile *cfg)
6509 {
6510         int max_epilog_size = 16;
6511
6512         if (cfg->method->save_lmf)
6513                 max_epilog_size += 256;
6514
6515         if (mono_jit_trace_calls != NULL)
6516                 max_epilog_size += 50;
6517
6518         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6519                 max_epilog_size += 50;
6520
6521         max_epilog_size += (AMD64_NREG * 2);
6522
6523         return max_epilog_size;
6524 }
6525
6526 /*
6527  * This macro is used for testing whenever the unwinder works correctly at every point
6528  * where an async exception can happen.
6529  */
6530 /* This will generate a SIGSEGV at the given point in the code */
6531 #define async_exc_point(code) do { \
6532     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6533          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6534              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6535          cfg->arch.async_point_count ++; \
6536     } \
6537 } while (0)
6538
6539 guint8 *
6540 mono_arch_emit_prolog (MonoCompile *cfg)
6541 {
6542         MonoMethod *method = cfg->method;
6543         MonoBasicBlock *bb;
6544         MonoMethodSignature *sig;
6545         MonoInst *ins;
6546         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6547         guint8 *code;
6548         CallInfo *cinfo;
6549         MonoInst *lmf_var = cfg->lmf_var;
6550         gboolean args_clobbered = FALSE;
6551         gboolean trace = FALSE;
6552
6553         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6554
6555         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6556
6557         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6558                 trace = TRUE;
6559
6560         /* Amount of stack space allocated by register saving code */
6561         pos = 0;
6562
6563         /* Offset between RSP and the CFA */
6564         cfa_offset = 0;
6565
6566         /*
6567          * The prolog consists of the following parts:
6568          * FP present:
6569          * - push rbp, mov rbp, rsp
6570          * - save callee saved regs using pushes
6571          * - allocate frame
6572          * - save rgctx if needed
6573          * - save lmf if needed
6574          * FP not present:
6575          * - allocate frame
6576          * - save rgctx if needed
6577          * - save lmf if needed
6578          * - save callee saved regs using moves
6579          */
6580
6581         // CFA = sp + 8
6582         cfa_offset = 8;
6583         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6584         // IP saved at CFA - 8
6585         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6586         async_exc_point (code);
6587         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6588
6589         if (!cfg->arch.omit_fp) {
6590                 amd64_push_reg (code, AMD64_RBP);
6591                 cfa_offset += 8;
6592                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6593                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6594                 async_exc_point (code);
6595 #ifdef TARGET_WIN32
6596                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6597 #endif
6598                 /* These are handled automatically by the stack marking code */
6599                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6600
6601                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6602                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6603                 async_exc_point (code);
6604 #ifdef TARGET_WIN32
6605                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6606 #endif
6607         }
6608
6609         /* The param area is always at offset 0 from sp */
6610         /* This needs to be allocated here, since it has to come after the spill area */
6611         if (cfg->param_area) {
6612                 if (cfg->arch.omit_fp)
6613                         // FIXME:
6614                         g_assert_not_reached ();
6615                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6616         }
6617
6618         if (cfg->arch.omit_fp) {
6619                 /*
6620                  * On enter, the stack is misaligned by the pushing of the return
6621                  * address. It is either made aligned by the pushing of %rbp, or by
6622                  * this.
6623                  */
6624                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6625                 if ((alloc_size % 16) == 0) {
6626                         alloc_size += 8;
6627                         /* Mark the padding slot as NOREF */
6628                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6629                 }
6630         } else {
6631                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6632                 if (cfg->stack_offset != alloc_size) {
6633                         /* Mark the padding slot as NOREF */
6634                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6635                 }
6636                 cfg->arch.sp_fp_offset = alloc_size;
6637                 alloc_size -= pos;
6638         }
6639
6640         cfg->arch.stack_alloc_size = alloc_size;
6641
6642         /* Allocate stack frame */
6643         if (alloc_size) {
6644                 /* See mono_emit_stack_alloc */
6645 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6646                 guint32 remaining_size = alloc_size;
6647                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6648                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6649                 guint32 offset = code - cfg->native_code;
6650                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6651                         while (required_code_size >= (cfg->code_size - offset))
6652                                 cfg->code_size *= 2;
6653                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6654                         code = cfg->native_code + offset;
6655                         cfg->stat_code_reallocs++;
6656                 }
6657
6658                 while (remaining_size >= 0x1000) {
6659                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6660                         if (cfg->arch.omit_fp) {
6661                                 cfa_offset += 0x1000;
6662                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6663                         }
6664                         async_exc_point (code);
6665 #ifdef TARGET_WIN32
6666                         if (cfg->arch.omit_fp)
6667                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6668 #endif
6669
6670                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6671                         remaining_size -= 0x1000;
6672                 }
6673                 if (remaining_size) {
6674                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6675                         if (cfg->arch.omit_fp) {
6676                                 cfa_offset += remaining_size;
6677                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6678                                 async_exc_point (code);
6679                         }
6680 #ifdef TARGET_WIN32
6681                         if (cfg->arch.omit_fp)
6682                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6683 #endif
6684                 }
6685 #else
6686                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6687                 if (cfg->arch.omit_fp) {
6688                         cfa_offset += alloc_size;
6689                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6690                         async_exc_point (code);
6691                 }
6692 #endif
6693         }
6694
6695         /* Stack alignment check */
6696 #if 0
6697         {
6698                 guint8 *buf;
6699
6700                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6701                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6702                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6703                 buf = code;
6704                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6705                 amd64_breakpoint (code);
6706                 amd64_patch (buf, code);
6707         }
6708 #endif
6709
6710         if (mini_get_debug_options ()->init_stacks) {
6711                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6712
6713                 /* Save registers to the red zone */
6714                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6715                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6716
6717                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6718                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6719                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6720
6721                 amd64_cld (code);
6722                 amd64_prefix (code, X86_REP_PREFIX);
6723                 amd64_stosl (code);
6724
6725                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6726                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6727         }
6728
6729         /* Save LMF */
6730         if (method->save_lmf)
6731                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6732
6733         /* Save callee saved registers */
6734         if (cfg->arch.omit_fp) {
6735                 save_area_offset = cfg->arch.reg_save_area_offset;
6736                 /* Save caller saved registers after sp is adjusted */
6737                 /* The registers are saved at the bottom of the frame */
6738                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6739         } else {
6740                 /* The registers are saved just below the saved rbp */
6741                 save_area_offset = cfg->arch.reg_save_area_offset;
6742         }
6743
6744         for (i = 0; i < AMD64_NREG; ++i) {
6745                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6746                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6747
6748                         if (cfg->arch.omit_fp) {
6749                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6750                                 /* These are handled automatically by the stack marking code */
6751                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6752                         } else {
6753                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6754                                 // FIXME: GC
6755                         }
6756
6757                         save_area_offset += 8;
6758                         async_exc_point (code);
6759                 }
6760         }
6761
6762         /* store runtime generic context */
6763         if (cfg->rgctx_var) {
6764                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6765                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6766
6767                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6768
6769                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6770                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6771         }
6772
6773         /* compute max_length in order to use short forward jumps */
6774         max_epilog_size = get_max_epilog_size (cfg);
6775         if (cfg->opt & MONO_OPT_BRANCH) {
6776                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6777                         MonoInst *ins;
6778                         int max_length = 0;
6779
6780                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6781                                 max_length += 6;
6782                         /* max alignment for loops */
6783                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6784                                 max_length += LOOP_ALIGNMENT;
6785
6786                         MONO_BB_FOR_EACH_INS (bb, ins) {
6787                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6788                         }
6789
6790                         /* Take prolog and epilog instrumentation into account */
6791                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6792                                 max_length += max_epilog_size;
6793
6794                         bb->max_length = max_length;
6795                 }
6796         }
6797
6798         sig = mono_method_signature (method);
6799         pos = 0;
6800
6801         cinfo = (CallInfo *)cfg->arch.cinfo;
6802
6803         if (sig->ret->type != MONO_TYPE_VOID) {
6804                 /* Save volatile arguments to the stack */
6805                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6806                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6807         }
6808
6809         /* Keep this in sync with emit_load_volatile_arguments */
6810         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6811                 ArgInfo *ainfo = cinfo->args + i;
6812
6813                 ins = cfg->args [i];
6814
6815                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6816                         /* Unused arguments */
6817                         continue;
6818
6819                 /* Save volatile arguments to the stack */
6820                 if (ins->opcode != OP_REGVAR) {
6821                         switch (ainfo->storage) {
6822                         case ArgInIReg: {
6823                                 guint32 size = 8;
6824
6825                                 /* FIXME: I1 etc */
6826                                 /*
6827                                 if (stack_offset & 0x1)
6828                                         size = 1;
6829                                 else if (stack_offset & 0x2)
6830                                         size = 2;
6831                                 else if (stack_offset & 0x4)
6832                                         size = 4;
6833                                 else
6834                                         size = 8;
6835                                 */
6836                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6837
6838                                 /*
6839                                  * Save the original location of 'this',
6840                                  * get_generic_info_from_stack_frame () needs this to properly look up
6841                                  * the argument value during the handling of async exceptions.
6842                                  */
6843                                 if (ins == cfg->args [0]) {
6844                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6845                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6846                                 }
6847                                 break;
6848                         }
6849                         case ArgInFloatSSEReg:
6850                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6851                                 break;
6852                         case ArgInDoubleSSEReg:
6853                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6854                                 break;
6855                         case ArgValuetypeInReg:
6856                                 for (quad = 0; quad < 2; quad ++) {
6857                                         switch (ainfo->pair_storage [quad]) {
6858                                         case ArgInIReg:
6859                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6860                                                 break;
6861                                         case ArgInFloatSSEReg:
6862                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6863                                                 break;
6864                                         case ArgInDoubleSSEReg:
6865                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6866                                                 break;
6867                                         case ArgNone:
6868                                                 break;
6869                                         default:
6870                                                 g_assert_not_reached ();
6871                                         }
6872                                 }
6873                                 break;
6874                         case ArgValuetypeAddrInIReg:
6875                                 if (ainfo->pair_storage [0] == ArgInIReg)
6876                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6877                                 break;
6878                         case ArgGSharedVtInReg:
6879                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6880                                 break;
6881                         default:
6882                                 break;
6883                         }
6884                 } else {
6885                         /* Argument allocated to (non-volatile) register */
6886                         switch (ainfo->storage) {
6887                         case ArgInIReg:
6888                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6889                                 break;
6890                         case ArgOnStack:
6891                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6892                                 break;
6893                         default:
6894                                 g_assert_not_reached ();
6895                         }
6896
6897                         if (ins == cfg->args [0]) {
6898                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6899                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6900                         }
6901                 }
6902         }
6903
6904         if (cfg->method->save_lmf)
6905                 args_clobbered = TRUE;
6906
6907         if (trace) {
6908                 args_clobbered = TRUE;
6909                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6910         }
6911
6912         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6913                 args_clobbered = TRUE;
6914
6915         /*
6916          * Optimize the common case of the first bblock making a call with the same
6917          * arguments as the method. This works because the arguments are still in their
6918          * original argument registers.
6919          * FIXME: Generalize this
6920          */
6921         if (!args_clobbered) {
6922                 MonoBasicBlock *first_bb = cfg->bb_entry;
6923                 MonoInst *next;
6924                 int filter = FILTER_IL_SEQ_POINT;
6925
6926                 next = mono_bb_first_inst (first_bb, filter);
6927                 if (!next && first_bb->next_bb) {
6928                         first_bb = first_bb->next_bb;
6929                         next = mono_bb_first_inst (first_bb, filter);
6930                 }
6931
6932                 if (first_bb->in_count > 1)
6933                         next = NULL;
6934
6935                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6936                         ArgInfo *ainfo = cinfo->args + i;
6937                         gboolean match = FALSE;
6938
6939                         ins = cfg->args [i];
6940                         if (ins->opcode != OP_REGVAR) {
6941                                 switch (ainfo->storage) {
6942                                 case ArgInIReg: {
6943                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6944                                                 if (next->dreg == ainfo->reg) {
6945                                                         NULLIFY_INS (next);
6946                                                         match = TRUE;
6947                                                 } else {
6948                                                         next->opcode = OP_MOVE;
6949                                                         next->sreg1 = ainfo->reg;
6950                                                         /* Only continue if the instruction doesn't change argument regs */
6951                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6952                                                                 match = TRUE;
6953                                                 }
6954                                         }
6955                                         break;
6956                                 }
6957                                 default:
6958                                         break;
6959                                 }
6960                         } else {
6961                                 /* Argument allocated to (non-volatile) register */
6962                                 switch (ainfo->storage) {
6963                                 case ArgInIReg:
6964                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6965                                                 NULLIFY_INS (next);
6966                                                 match = TRUE;
6967                                         }
6968                                         break;
6969                                 default:
6970                                         break;
6971                                 }
6972                         }
6973
6974                         if (match) {
6975                                 next = mono_inst_next (next, filter);
6976                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6977                                 if (!next)
6978                                         break;
6979                         }
6980                 }
6981         }
6982
6983         if (cfg->gen_sdb_seq_points) {
6984                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
6985
6986                 /* Initialize seq_point_info_var */
6987                 if (cfg->compile_aot) {
6988                         /* Initialize the variable from a GOT slot */
6989                         /* Same as OP_AOTCONST */
6990                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6991                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6992                         g_assert (info_var->opcode == OP_REGOFFSET);
6993                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6994                 }
6995
6996                 if (cfg->compile_aot) {
6997                         /* Initialize ss_tramp_var */
6998                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
6999                         g_assert (ins->opcode == OP_REGOFFSET);
7000
7001                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7002                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7003                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7004                 } else {
7005                         /* Initialize ss_tramp_var */
7006                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7007                         g_assert (ins->opcode == OP_REGOFFSET);
7008
7009                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7010                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7011
7012                         /* Initialize bp_tramp_var */
7013                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7014                         g_assert (ins->opcode == OP_REGOFFSET);
7015
7016                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7017                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7018                 }
7019         }
7020
7021         cfg->code_len = code - cfg->native_code;
7022
7023         g_assert (cfg->code_len < cfg->code_size);
7024
7025         return code;
7026 }
7027
7028 void
7029 mono_arch_emit_epilog (MonoCompile *cfg)
7030 {
7031         MonoMethod *method = cfg->method;
7032         int quad, i;
7033         guint8 *code;
7034         int max_epilog_size;
7035         CallInfo *cinfo;
7036         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7037         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7038
7039         max_epilog_size = get_max_epilog_size (cfg);
7040
7041         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7042                 cfg->code_size *= 2;
7043                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7044                 cfg->stat_code_reallocs++;
7045         }
7046         code = cfg->native_code + cfg->code_len;
7047
7048         cfg->has_unwind_info_for_epilog = TRUE;
7049
7050         /* Mark the start of the epilog */
7051         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7052
7053         /* Save the uwind state which is needed by the out-of-line code */
7054         mono_emit_unwind_op_remember_state (cfg, code);
7055
7056         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7057                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7058
7059         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7060
7061         if (method->save_lmf) {
7062                 /* check if we need to restore protection of the stack after a stack overflow */
7063                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7064                         guint8 *patch;
7065                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7066                         /* we load the value in a separate instruction: this mechanism may be
7067                          * used later as a safer way to do thread interruption
7068                          */
7069                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7070                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7071                         patch = code;
7072                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7073                         /* note that the call trampoline will preserve eax/edx */
7074                         x86_call_reg (code, X86_ECX);
7075                         x86_patch (patch, code);
7076                 } else {
7077                         /* FIXME: maybe save the jit tls in the prolog */
7078                 }
7079                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7080                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7081                 }
7082         }
7083
7084         /* Restore callee saved regs */
7085         for (i = 0; i < AMD64_NREG; ++i) {
7086                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7087                         /* Restore only used_int_regs, not arch.saved_iregs */
7088                         if (cfg->used_int_regs & (1 << i)) {
7089                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7090                                 mono_emit_unwind_op_same_value (cfg, code, i);
7091                                 async_exc_point (code);
7092                         }
7093                         save_area_offset += 8;
7094                 }
7095         }
7096
7097         /* Load returned vtypes into registers if needed */
7098         cinfo = (CallInfo *)cfg->arch.cinfo;
7099         if (cinfo->ret.storage == ArgValuetypeInReg) {
7100                 ArgInfo *ainfo = &cinfo->ret;
7101                 MonoInst *inst = cfg->ret;
7102
7103                 for (quad = 0; quad < 2; quad ++) {
7104                         switch (ainfo->pair_storage [quad]) {
7105                         case ArgInIReg:
7106                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7107                                 break;
7108                         case ArgInFloatSSEReg:
7109                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7110                                 break;
7111                         case ArgInDoubleSSEReg:
7112                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7113                                 break;
7114                         case ArgNone:
7115                                 break;
7116                         default:
7117                                 g_assert_not_reached ();
7118                         }
7119                 }
7120         }
7121
7122         if (cfg->arch.omit_fp) {
7123                 if (cfg->arch.stack_alloc_size) {
7124                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7125                 }
7126         } else {
7127                 amd64_leave (code);
7128                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7129         }
7130         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7131         async_exc_point (code);
7132         amd64_ret (code);
7133
7134         /* Restore the unwind state to be the same as before the epilog */
7135         mono_emit_unwind_op_restore_state (cfg, code);
7136
7137         cfg->code_len = code - cfg->native_code;
7138
7139         g_assert (cfg->code_len < cfg->code_size);
7140 }
7141
7142 void
7143 mono_arch_emit_exceptions (MonoCompile *cfg)
7144 {
7145         MonoJumpInfo *patch_info;
7146         int nthrows, i;
7147         guint8 *code;
7148         MonoClass *exc_classes [16];
7149         guint8 *exc_throw_start [16], *exc_throw_end [16];
7150         guint32 code_size = 0;
7151
7152         /* Compute needed space */
7153         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7154                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7155                         code_size += 40;
7156                 if (patch_info->type == MONO_PATCH_INFO_R8)
7157                         code_size += 8 + 15; /* sizeof (double) + alignment */
7158                 if (patch_info->type == MONO_PATCH_INFO_R4)
7159                         code_size += 4 + 15; /* sizeof (float) + alignment */
7160                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7161                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7162         }
7163
7164         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7165                 cfg->code_size *= 2;
7166                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7167                 cfg->stat_code_reallocs++;
7168         }
7169
7170         code = cfg->native_code + cfg->code_len;
7171
7172         /* add code to raise exceptions */
7173         nthrows = 0;
7174         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7175                 switch (patch_info->type) {
7176                 case MONO_PATCH_INFO_EXC: {
7177                         MonoClass *exc_class;
7178                         guint8 *buf, *buf2;
7179                         guint32 throw_ip;
7180
7181                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7182
7183                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7184                         throw_ip = patch_info->ip.i;
7185
7186                         //x86_breakpoint (code);
7187                         /* Find a throw sequence for the same exception class */
7188                         for (i = 0; i < nthrows; ++i)
7189                                 if (exc_classes [i] == exc_class)
7190                                         break;
7191                         if (i < nthrows) {
7192                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7193                                 x86_jump_code (code, exc_throw_start [i]);
7194                                 patch_info->type = MONO_PATCH_INFO_NONE;
7195                         }
7196                         else {
7197                                 buf = code;
7198                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7199                                 buf2 = code;
7200
7201                                 if (nthrows < 16) {
7202                                         exc_classes [nthrows] = exc_class;
7203                                         exc_throw_start [nthrows] = code;
7204                                 }
7205                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7206
7207                                 patch_info->type = MONO_PATCH_INFO_NONE;
7208
7209                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7210
7211                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7212                                 while (buf < buf2)
7213                                         x86_nop (buf);
7214
7215                                 if (nthrows < 16) {
7216                                         exc_throw_end [nthrows] = code;
7217                                         nthrows ++;
7218                                 }
7219                         }
7220                         break;
7221                 }
7222                 default:
7223                         /* do nothing */
7224                         break;
7225                 }
7226                 g_assert(code < cfg->native_code + cfg->code_size);
7227         }
7228
7229         /* Handle relocations with RIP relative addressing */
7230         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7231                 gboolean remove = FALSE;
7232                 guint8 *orig_code = code;
7233
7234                 switch (patch_info->type) {
7235                 case MONO_PATCH_INFO_R8:
7236                 case MONO_PATCH_INFO_R4: {
7237                         guint8 *pos, *patch_pos;
7238                         guint32 target_pos;
7239
7240                         /* The SSE opcodes require a 16 byte alignment */
7241                         code = (guint8*)ALIGN_TO (code, 16);
7242
7243                         pos = cfg->native_code + patch_info->ip.i;
7244                         if (IS_REX (pos [1])) {
7245                                 patch_pos = pos + 5;
7246                                 target_pos = code - pos - 9;
7247                         }
7248                         else {
7249                                 patch_pos = pos + 4;
7250                                 target_pos = code - pos - 8;
7251                         }
7252
7253                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7254                                 *(double*)code = *(double*)patch_info->data.target;
7255                                 code += sizeof (double);
7256                         } else {
7257                                 *(float*)code = *(float*)patch_info->data.target;
7258                                 code += sizeof (float);
7259                         }
7260
7261                         *(guint32*)(patch_pos) = target_pos;
7262
7263                         remove = TRUE;
7264                         break;
7265                 }
7266                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7267                         guint8 *pos;
7268
7269                         if (cfg->compile_aot)
7270                                 continue;
7271
7272                         /*loading is faster against aligned addresses.*/
7273                         code = (guint8*)ALIGN_TO (code, 8);
7274                         memset (orig_code, 0, code - orig_code);
7275
7276                         pos = cfg->native_code + patch_info->ip.i;
7277
7278                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7279                         if (IS_REX (pos [1]))
7280                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7281                         else
7282                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7283
7284                         *(gpointer*)code = (gpointer)patch_info->data.target;
7285                         code += sizeof (gpointer);
7286
7287                         remove = TRUE;
7288                         break;
7289                 }
7290                 default:
7291                         break;
7292                 }
7293
7294                 if (remove) {
7295                         if (patch_info == cfg->patch_info)
7296                                 cfg->patch_info = patch_info->next;
7297                         else {
7298                                 MonoJumpInfo *tmp;
7299
7300                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7301                                         ;
7302                                 tmp->next = patch_info->next;
7303                         }
7304                 }
7305                 g_assert (code < cfg->native_code + cfg->code_size);
7306         }
7307
7308         cfg->code_len = code - cfg->native_code;
7309
7310         g_assert (cfg->code_len < cfg->code_size);
7311
7312 }
7313
7314 #endif /* DISABLE_JIT */
7315
7316 void*
7317 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7318 {
7319         guchar *code = (guchar *)p;
7320         MonoMethodSignature *sig;
7321         MonoInst *inst;
7322         int i, n, stack_area = 0;
7323
7324         /* Keep this in sync with mono_arch_get_argument_info */
7325
7326         if (enable_arguments) {
7327                 /* Allocate a new area on the stack and save arguments there */
7328                 sig = mono_method_signature (cfg->method);
7329
7330                 n = sig->param_count + sig->hasthis;
7331
7332                 stack_area = ALIGN_TO (n * 8, 16);
7333
7334                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7335
7336                 for (i = 0; i < n; ++i) {
7337                         inst = cfg->args [i];
7338
7339                         if (inst->opcode == OP_REGVAR)
7340                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7341                         else {
7342                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7343                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7344                         }
7345                 }
7346         }
7347
7348         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7349         amd64_set_reg_template (code, AMD64_ARG_REG1);
7350         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7351         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7352
7353         if (enable_arguments)
7354                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7355
7356         return code;
7357 }
7358
7359 enum {
7360         SAVE_NONE,
7361         SAVE_STRUCT,
7362         SAVE_EAX,
7363         SAVE_EAX_EDX,
7364         SAVE_XMM
7365 };
7366
7367 void*
7368 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7369 {
7370         guchar *code = (guchar *)p;
7371         int save_mode = SAVE_NONE;
7372         MonoMethod *method = cfg->method;
7373         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7374         int i;
7375
7376         switch (ret_type->type) {
7377         case MONO_TYPE_VOID:
7378                 /* special case string .ctor icall */
7379                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7380                         save_mode = SAVE_EAX;
7381                 else
7382                         save_mode = SAVE_NONE;
7383                 break;
7384         case MONO_TYPE_I8:
7385         case MONO_TYPE_U8:
7386                 save_mode = SAVE_EAX;
7387                 break;
7388         case MONO_TYPE_R4:
7389         case MONO_TYPE_R8:
7390                 save_mode = SAVE_XMM;
7391                 break;
7392         case MONO_TYPE_GENERICINST:
7393                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7394                         save_mode = SAVE_EAX;
7395                         break;
7396                 }
7397                 /* Fall through */
7398         case MONO_TYPE_VALUETYPE:
7399                 save_mode = SAVE_STRUCT;
7400                 break;
7401         default:
7402                 save_mode = SAVE_EAX;
7403                 break;
7404         }
7405
7406         /* Save the result and copy it into the proper argument register */
7407         switch (save_mode) {
7408         case SAVE_EAX:
7409                 amd64_push_reg (code, AMD64_RAX);
7410                 /* Align stack */
7411                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7412                 if (enable_arguments)
7413                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7414                 break;
7415         case SAVE_STRUCT:
7416                 /* FIXME: */
7417                 if (enable_arguments)
7418                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7419                 break;
7420         case SAVE_XMM:
7421                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7422                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7423                 /* Align stack */
7424                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7425                 /*
7426                  * The result is already in the proper argument register so no copying
7427                  * needed.
7428                  */
7429                 break;
7430         case SAVE_NONE:
7431                 break;
7432         default:
7433                 g_assert_not_reached ();
7434         }
7435
7436         /* Set %al since this is a varargs call */
7437         if (save_mode == SAVE_XMM)
7438                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7439         else
7440                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7441
7442         if (preserve_argument_registers) {
7443                 for (i = 0; i < PARAM_REGS; ++i)
7444                         amd64_push_reg (code, param_regs [i]);
7445         }
7446
7447         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7448         amd64_set_reg_template (code, AMD64_ARG_REG1);
7449         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7450
7451         if (preserve_argument_registers) {
7452                 for (i = PARAM_REGS - 1; i >= 0; --i)
7453                         amd64_pop_reg (code, param_regs [i]);
7454         }
7455
7456         /* Restore result */
7457         switch (save_mode) {
7458         case SAVE_EAX:
7459                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7460                 amd64_pop_reg (code, AMD64_RAX);
7461                 break;
7462         case SAVE_STRUCT:
7463                 /* FIXME: */
7464                 break;
7465         case SAVE_XMM:
7466                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7467                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7468                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7469                 break;
7470         case SAVE_NONE:
7471                 break;
7472         default:
7473                 g_assert_not_reached ();
7474         }
7475
7476         return code;
7477 }
7478
7479 void
7480 mono_arch_flush_icache (guint8 *code, gint size)
7481 {
7482         /* Not needed */
7483 }
7484
7485 void
7486 mono_arch_flush_register_windows (void)
7487 {
7488 }
7489
7490 gboolean
7491 mono_arch_is_inst_imm (gint64 imm)
7492 {
7493         return amd64_use_imm32 (imm);
7494 }
7495
7496 /*
7497  * Determine whenever the trap whose info is in SIGINFO is caused by
7498  * integer overflow.
7499  */
7500 gboolean
7501 mono_arch_is_int_overflow (void *sigctx, void *info)
7502 {
7503         MonoContext ctx;
7504         guint8* rip;
7505         int reg;
7506         gint64 value;
7507
7508         mono_sigctx_to_monoctx (sigctx, &ctx);
7509
7510         rip = (guint8*)ctx.gregs [AMD64_RIP];
7511
7512         if (IS_REX (rip [0])) {
7513                 reg = amd64_rex_b (rip [0]);
7514                 rip ++;
7515         }
7516         else
7517                 reg = 0;
7518
7519         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7520                 /* idiv REG */
7521                 reg += x86_modrm_rm (rip [1]);
7522
7523                 value = ctx.gregs [reg];
7524
7525                 if (value == -1)
7526                         return TRUE;
7527         }
7528
7529         return FALSE;
7530 }
7531
7532 guint32
7533 mono_arch_get_patch_offset (guint8 *code)
7534 {
7535         return 3;
7536 }
7537
7538 /**
7539  * mono_breakpoint_clean_code:
7540  *
7541  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7542  * breakpoints in the original code, they are removed in the copy.
7543  *
7544  * Returns TRUE if no sw breakpoint was present.
7545  */
7546 gboolean
7547 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7548 {
7549         /*
7550          * If method_start is non-NULL we need to perform bound checks, since we access memory
7551          * at code - offset we could go before the start of the method and end up in a different
7552          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7553          * instead.
7554          */
7555         if (!method_start || code - offset >= method_start) {
7556                 memcpy (buf, code - offset, size);
7557         } else {
7558                 int diff = code - method_start;
7559                 memset (buf, 0, size);
7560                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7561         }
7562         return TRUE;
7563 }
7564
7565 int
7566 mono_arch_get_this_arg_reg (guint8 *code)
7567 {
7568         return AMD64_ARG_REG1;
7569 }
7570
7571 gpointer
7572 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7573 {
7574         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7575 }
7576
7577 #define MAX_ARCH_DELEGATE_PARAMS 10
7578
7579 static gpointer
7580 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7581 {
7582         guint8 *code, *start;
7583         GSList *unwind_ops = NULL;
7584         int i;
7585
7586         unwind_ops = mono_arch_get_cie_program ();
7587
7588         if (has_target) {
7589                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7590
7591                 /* Replace the this argument with the target */
7592                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7593                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7594                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7595
7596                 g_assert ((code - start) < 64);
7597         } else {
7598                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7599
7600                 if (param_count == 0) {
7601                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7602                 } else {
7603                         /* We have to shift the arguments left */
7604                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7605                         for (i = 0; i < param_count; ++i) {
7606 #ifdef TARGET_WIN32
7607                                 if (i < 3)
7608                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7609                                 else
7610                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7611 #else
7612                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7613 #endif
7614                         }
7615
7616                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7617                 }
7618                 g_assert ((code - start) < 64);
7619         }
7620
7621         mono_arch_flush_icache (start, code - start);
7622
7623         if (has_target) {
7624                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7625         } else {
7626                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7627                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7628                 g_free (name);
7629         }
7630
7631         if (mono_jit_map_is_enabled ()) {
7632                 char *buff;
7633                 if (has_target)
7634                         buff = (char*)"delegate_invoke_has_target";
7635                 else
7636                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7637                 mono_emit_jit_tramp (start, code - start, buff);
7638                 if (!has_target)
7639                         g_free (buff);
7640         }
7641         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7642
7643         return start;
7644 }
7645
7646 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7647
7648 static gpointer
7649 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7650 {
7651         guint8 *code, *start;
7652         int size = 20;
7653         char *tramp_name;
7654         GSList *unwind_ops;
7655
7656         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7657                 return NULL;
7658
7659         start = code = (guint8 *)mono_global_codeman_reserve (size);
7660
7661         unwind_ops = mono_arch_get_cie_program ();
7662
7663         /* Replace the this argument with the target */
7664         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7665         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7666
7667         if (load_imt_reg) {
7668                 /* Load the IMT reg */
7669                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7670         }
7671
7672         /* Load the vtable */
7673         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7674         amd64_jump_membase (code, AMD64_RAX, offset);
7675         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7676
7677         if (load_imt_reg)
7678                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7679         else
7680                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7681         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7682         g_free (tramp_name);
7683
7684         return start;
7685 }
7686
7687 /*
7688  * mono_arch_get_delegate_invoke_impls:
7689  *
7690  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7691  * trampolines.
7692  */
7693 GSList*
7694 mono_arch_get_delegate_invoke_impls (void)
7695 {
7696         GSList *res = NULL;
7697         MonoTrampInfo *info;
7698         int i;
7699
7700         get_delegate_invoke_impl (&info, TRUE, 0);
7701         res = g_slist_prepend (res, info);
7702
7703         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7704                 get_delegate_invoke_impl (&info, FALSE, i);
7705                 res = g_slist_prepend (res, info);
7706         }
7707
7708         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7709                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7710                 res = g_slist_prepend (res, info);
7711
7712                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7713                 res = g_slist_prepend (res, info);
7714         }
7715
7716         return res;
7717 }
7718
7719 gpointer
7720 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7721 {
7722         guint8 *code, *start;
7723         int i;
7724
7725         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7726                 return NULL;
7727
7728         /* FIXME: Support more cases */
7729         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7730                 return NULL;
7731
7732         if (has_target) {
7733                 static guint8* cached = NULL;
7734
7735                 if (cached)
7736                         return cached;
7737
7738                 if (mono_aot_only) {
7739                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7740                 } else {
7741                         MonoTrampInfo *info;
7742                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7743                         mono_tramp_info_register (info, NULL);
7744                 }
7745
7746                 mono_memory_barrier ();
7747
7748                 cached = start;
7749         } else {
7750                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7751                 for (i = 0; i < sig->param_count; ++i)
7752                         if (!mono_is_regsize_var (sig->params [i]))
7753                                 return NULL;
7754                 if (sig->param_count > 4)
7755                         return NULL;
7756
7757                 code = cache [sig->param_count];
7758                 if (code)
7759                         return code;
7760
7761                 if (mono_aot_only) {
7762                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7763                         start = (guint8 *)mono_aot_get_trampoline (name);
7764                         g_free (name);
7765                 } else {
7766                         MonoTrampInfo *info;
7767                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7768                         mono_tramp_info_register (info, NULL);
7769                 }
7770
7771                 mono_memory_barrier ();
7772
7773                 cache [sig->param_count] = start;
7774         }
7775
7776         return start;
7777 }
7778
7779 gpointer
7780 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7781 {
7782         MonoTrampInfo *info;
7783         gpointer code;
7784
7785         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7786         if (code)
7787                 mono_tramp_info_register (info, NULL);
7788         return code;
7789 }
7790
7791 void
7792 mono_arch_finish_init (void)
7793 {
7794 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7795         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7796 #endif
7797 }
7798
7799 void
7800 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7801 {
7802 }
7803
7804 #define CMP_SIZE (6 + 1)
7805 #define CMP_REG_REG_SIZE (4 + 1)
7806 #define BR_SMALL_SIZE 2
7807 #define BR_LARGE_SIZE 6
7808 #define MOV_REG_IMM_SIZE 10
7809 #define MOV_REG_IMM_32BIT_SIZE 6
7810 #define JUMP_REG_SIZE (2 + 1)
7811
7812 static int
7813 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7814 {
7815         int i, distance = 0;
7816         for (i = start; i < target; ++i)
7817                 distance += imt_entries [i]->chunk_size;
7818         return distance;
7819 }
7820
7821 /*
7822  * LOCKING: called with the domain lock held
7823  */
7824 gpointer
7825 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7826         gpointer fail_tramp)
7827 {
7828         int i;
7829         int size = 0;
7830         guint8 *code, *start;
7831         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7832         GSList *unwind_ops;
7833
7834         for (i = 0; i < count; ++i) {
7835                 MonoIMTCheckItem *item = imt_entries [i];
7836                 if (item->is_equals) {
7837                         if (item->check_target_idx) {
7838                                 if (!item->compare_done) {
7839                                         if (amd64_use_imm32 ((gint64)item->key))
7840                                                 item->chunk_size += CMP_SIZE;
7841                                         else
7842                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7843                                 }
7844                                 if (item->has_target_code) {
7845                                         item->chunk_size += MOV_REG_IMM_SIZE;
7846                                 } else {
7847                                         if (vtable_is_32bit)
7848                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7849                                         else
7850                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7851                                 }
7852                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7853                         } else {
7854                                 if (fail_tramp) {
7855                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7856                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7857                                 } else {
7858                                         if (vtable_is_32bit)
7859                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7860                                         else
7861                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7862                                         item->chunk_size += JUMP_REG_SIZE;
7863                                         /* with assert below:
7864                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7865                                          */
7866                                 }
7867                         }
7868                 } else {
7869                         if (amd64_use_imm32 ((gint64)item->key))
7870                                 item->chunk_size += CMP_SIZE;
7871                         else
7872                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7873                         item->chunk_size += BR_LARGE_SIZE;
7874                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7875                 }
7876                 size += item->chunk_size;
7877         }
7878         if (fail_tramp)
7879                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
7880         else
7881                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7882         start = code;
7883
7884         unwind_ops = mono_arch_get_cie_program ();
7885
7886         for (i = 0; i < count; ++i) {
7887                 MonoIMTCheckItem *item = imt_entries [i];
7888                 item->code_target = code;
7889                 if (item->is_equals) {
7890                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7891
7892                         if (item->check_target_idx || fail_case) {
7893                                 if (!item->compare_done || fail_case) {
7894                                         if (amd64_use_imm32 ((gint64)item->key))
7895                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7896                                         else {
7897                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7898                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7899                                         }
7900                                 }
7901                                 item->jmp_code = code;
7902                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7903                                 if (item->has_target_code) {
7904                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7905                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7906                                 } else {
7907                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7908                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7909                                 }
7910
7911                                 if (fail_case) {
7912                                         amd64_patch (item->jmp_code, code);
7913                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7914                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7915                                         item->jmp_code = NULL;
7916                                 }
7917                         } else {
7918                                 /* enable the commented code to assert on wrong method */
7919 #if 0
7920                                 if (amd64_is_imm32 (item->key))
7921                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7922                                 else {
7923                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7924                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7925                                 }
7926                                 item->jmp_code = code;
7927                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7928                                 /* See the comment below about R10 */
7929                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7930                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7931                                 amd64_patch (item->jmp_code, code);
7932                                 amd64_breakpoint (code);
7933                                 item->jmp_code = NULL;
7934 #else
7935                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7936                                    needs to be preserved.  R10 needs
7937                                    to be preserved for calls which
7938                                    require a runtime generic context,
7939                                    but interface calls don't. */
7940                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7941                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7942 #endif
7943                         }
7944                 } else {
7945                         if (amd64_use_imm32 ((gint64)item->key))
7946                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7947                         else {
7948                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7949                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7950                         }
7951                         item->jmp_code = code;
7952                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7953                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7954                         else
7955                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7956                 }
7957                 g_assert (code - item->code_target <= item->chunk_size);
7958         }
7959         /* patch the branches to get to the target items */
7960         for (i = 0; i < count; ++i) {
7961                 MonoIMTCheckItem *item = imt_entries [i];
7962                 if (item->jmp_code) {
7963                         if (item->check_target_idx) {
7964                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7965                         }
7966                 }
7967         }
7968
7969         if (!fail_tramp)
7970                 mono_stats.imt_thunks_size += code - start;
7971         g_assert (code - start <= size);
7972
7973         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7974
7975         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
7976
7977         return start;
7978 }
7979
7980 MonoMethod*
7981 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7982 {
7983         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7984 }
7985
7986 MonoVTable*
7987 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7988 {
7989         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7990 }
7991
7992 GSList*
7993 mono_arch_get_cie_program (void)
7994 {
7995         GSList *l = NULL;
7996
7997         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7998         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7999
8000         return l;
8001 }
8002
8003 #ifndef DISABLE_JIT
8004
8005 MonoInst*
8006 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8007 {
8008         MonoInst *ins = NULL;
8009         int opcode = 0;
8010
8011         if (cmethod->klass == mono_defaults.math_class) {
8012                 if (strcmp (cmethod->name, "Sin") == 0) {
8013                         opcode = OP_SIN;
8014                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8015                         opcode = OP_COS;
8016                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8017                         opcode = OP_SQRT;
8018                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8019                         opcode = OP_ABS;
8020                 }
8021
8022                 if (opcode && fsig->param_count == 1) {
8023                         MONO_INST_NEW (cfg, ins, opcode);
8024                         ins->type = STACK_R8;
8025                         ins->dreg = mono_alloc_freg (cfg);
8026                         ins->sreg1 = args [0]->dreg;
8027                         MONO_ADD_INS (cfg->cbb, ins);
8028                 }
8029
8030                 opcode = 0;
8031                 if (cfg->opt & MONO_OPT_CMOV) {
8032                         if (strcmp (cmethod->name, "Min") == 0) {
8033                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8034                                         opcode = OP_IMIN;
8035                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8036                                         opcode = OP_IMIN_UN;
8037                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8038                                         opcode = OP_LMIN;
8039                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8040                                         opcode = OP_LMIN_UN;
8041                         } else if (strcmp (cmethod->name, "Max") == 0) {
8042                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8043                                         opcode = OP_IMAX;
8044                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8045                                         opcode = OP_IMAX_UN;
8046                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8047                                         opcode = OP_LMAX;
8048                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8049                                         opcode = OP_LMAX_UN;
8050                         }
8051                 }
8052
8053                 if (opcode && fsig->param_count == 2) {
8054                         MONO_INST_NEW (cfg, ins, opcode);
8055                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8056                         ins->dreg = mono_alloc_ireg (cfg);
8057                         ins->sreg1 = args [0]->dreg;
8058                         ins->sreg2 = args [1]->dreg;
8059                         MONO_ADD_INS (cfg->cbb, ins);
8060                 }
8061
8062 #if 0
8063                 /* OP_FREM is not IEEE compatible */
8064                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8065                         MONO_INST_NEW (cfg, ins, OP_FREM);
8066                         ins->inst_i0 = args [0];
8067                         ins->inst_i1 = args [1];
8068                 }
8069 #endif
8070         }
8071
8072         return ins;
8073 }
8074 #endif
8075
8076 gboolean
8077 mono_arch_print_tree (MonoInst *tree, int arity)
8078 {
8079         return 0;
8080 }
8081
8082 mgreg_t
8083 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8084 {
8085         return ctx->gregs [reg];
8086 }
8087
8088 void
8089 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8090 {
8091         ctx->gregs [reg] = val;
8092 }
8093
8094 gpointer
8095 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8096 {
8097         gpointer *sp, old_value;
8098         char *bp;
8099
8100         /*Load the spvar*/
8101         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8102         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8103
8104         old_value = *sp;
8105         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8106                 return old_value;
8107
8108         *sp = new_value;
8109
8110         return old_value;
8111 }
8112
8113 /*
8114  * mono_arch_emit_load_aotconst:
8115  *
8116  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8117  * TARGET from the mscorlib GOT in full-aot code.
8118  * On AMD64, the result is placed into R11.
8119  */
8120 guint8*
8121 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8122 {
8123         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8124         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8125
8126         return code;
8127 }
8128
8129 /*
8130  * mono_arch_get_trampolines:
8131  *
8132  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8133  * for AOT.
8134  */
8135 GSList *
8136 mono_arch_get_trampolines (gboolean aot)
8137 {
8138         return mono_amd64_get_exception_trampolines (aot);
8139 }
8140
8141 /* Soft Debug support */
8142 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8143
8144 /*
8145  * mono_arch_set_breakpoint:
8146  *
8147  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8148  * The location should contain code emitted by OP_SEQ_POINT.
8149  */
8150 void
8151 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8152 {
8153         guint8 *code = ip;
8154
8155         if (ji->from_aot) {
8156                 guint32 native_offset = ip - (guint8*)ji->code_start;
8157                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8158
8159                 g_assert (info->bp_addrs [native_offset] == 0);
8160                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8161         } else {
8162                 /* ip points to a mov r11, 0 */
8163                 g_assert (code [0] == 0x41);
8164                 g_assert (code [1] == 0xbb);
8165                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8166         }
8167 }
8168
8169 /*
8170  * mono_arch_clear_breakpoint:
8171  *
8172  *   Clear the breakpoint at IP.
8173  */
8174 void
8175 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8176 {
8177         guint8 *code = ip;
8178
8179         if (ji->from_aot) {
8180                 guint32 native_offset = ip - (guint8*)ji->code_start;
8181                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8182
8183                 info->bp_addrs [native_offset] = NULL;
8184         } else {
8185                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8186         }
8187 }
8188
8189 gboolean
8190 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8191 {
8192         /* We use soft breakpoints on amd64 */
8193         return FALSE;
8194 }
8195
8196 /*
8197  * mono_arch_skip_breakpoint:
8198  *
8199  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8200  * we resume, the instruction is not executed again.
8201  */
8202 void
8203 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8204 {
8205         g_assert_not_reached ();
8206 }
8207
8208 /*
8209  * mono_arch_start_single_stepping:
8210  *
8211  *   Start single stepping.
8212  */
8213 void
8214 mono_arch_start_single_stepping (void)
8215 {
8216         ss_trampoline = mini_get_single_step_trampoline ();
8217 }
8218
8219 /*
8220  * mono_arch_stop_single_stepping:
8221  *
8222  *   Stop single stepping.
8223  */
8224 void
8225 mono_arch_stop_single_stepping (void)
8226 {
8227         ss_trampoline = NULL;
8228 }
8229
8230 /*
8231  * mono_arch_is_single_step_event:
8232  *
8233  *   Return whenever the machine state in SIGCTX corresponds to a single
8234  * step event.
8235  */
8236 gboolean
8237 mono_arch_is_single_step_event (void *info, void *sigctx)
8238 {
8239         /* We use soft breakpoints on amd64 */
8240         return FALSE;
8241 }
8242
8243 /*
8244  * mono_arch_skip_single_step:
8245  *
8246  *   Modify CTX so the ip is placed after the single step trigger instruction,
8247  * we resume, the instruction is not executed again.
8248  */
8249 void
8250 mono_arch_skip_single_step (MonoContext *ctx)
8251 {
8252         g_assert_not_reached ();
8253 }
8254
8255 /*
8256  * mono_arch_create_seq_point_info:
8257  *
8258  *   Return a pointer to a data structure which is used by the sequence
8259  * point implementation in AOTed code.
8260  */
8261 gpointer
8262 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8263 {
8264         SeqPointInfo *info;
8265         MonoJitInfo *ji;
8266
8267         // FIXME: Add a free function
8268
8269         mono_domain_lock (domain);
8270         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8271                                                                 code);
8272         mono_domain_unlock (domain);
8273
8274         if (!info) {
8275                 ji = mono_jit_info_table_find (domain, (char*)code);
8276                 g_assert (ji);
8277
8278                 // FIXME: Optimize the size
8279                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8280
8281                 info->ss_tramp_addr = &ss_trampoline;
8282
8283                 mono_domain_lock (domain);
8284                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8285                                                          code, info);
8286                 mono_domain_unlock (domain);
8287         }
8288
8289         return info;
8290 }
8291
8292 void
8293 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8294 {
8295         ext->lmf.previous_lmf = prev_lmf;
8296         /* Mark that this is a MonoLMFExt */
8297         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8298         ext->lmf.rsp = (gssize)ext;
8299 }
8300
8301 #endif
8302
8303 gboolean
8304 mono_arch_opcode_supported (int opcode)
8305 {
8306         switch (opcode) {
8307         case OP_ATOMIC_ADD_I4:
8308         case OP_ATOMIC_ADD_I8:
8309         case OP_ATOMIC_EXCHANGE_I4:
8310         case OP_ATOMIC_EXCHANGE_I8:
8311         case OP_ATOMIC_CAS_I4:
8312         case OP_ATOMIC_CAS_I8:
8313         case OP_ATOMIC_LOAD_I1:
8314         case OP_ATOMIC_LOAD_I2:
8315         case OP_ATOMIC_LOAD_I4:
8316         case OP_ATOMIC_LOAD_I8:
8317         case OP_ATOMIC_LOAD_U1:
8318         case OP_ATOMIC_LOAD_U2:
8319         case OP_ATOMIC_LOAD_U4:
8320         case OP_ATOMIC_LOAD_U8:
8321         case OP_ATOMIC_LOAD_R4:
8322         case OP_ATOMIC_LOAD_R8:
8323         case OP_ATOMIC_STORE_I1:
8324         case OP_ATOMIC_STORE_I2:
8325         case OP_ATOMIC_STORE_I4:
8326         case OP_ATOMIC_STORE_I8:
8327         case OP_ATOMIC_STORE_U1:
8328         case OP_ATOMIC_STORE_U2:
8329         case OP_ATOMIC_STORE_U4:
8330         case OP_ATOMIC_STORE_U8:
8331         case OP_ATOMIC_STORE_R4:
8332         case OP_ATOMIC_STORE_R8:
8333                 return TRUE;
8334         default:
8335                 return FALSE;
8336         }
8337 }
8338
8339 CallInfo*
8340 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8341 {
8342         return get_call_info (mp, sig);
8343 }