mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                            gboolean is_return,
 393                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400         gboolean pass_on_stack = FALSE;
 401
 402         /*
 403          * The gsctx currently contains no data, it is only used for checking whenever
 404          * open types are allowed, some callers like mono_arch_get_argument_info ()
 405          * don't pass it to us, so work around that.
 406          */
 407         if (!gsctx)
 408                 gsctx = &tmp_gsctx;
 409
 410         klass = mono_class_from_mono_type (type);
 411         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 412 #ifndef PLATFORM_WIN32
 413         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 414                 /* We pass and return vtypes of size 8 in a register */
 415         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 416                 pass_on_stack = TRUE;
 417         }
 418 #else
 419         if (!sig->pinvoke) {
 420                 pass_on_stack = TRUE;
 421         }
 422 #endif
 423
 424         if (pass_on_stack) {
 425                 /* Allways pass in memory */
 426                 ainfo->offset = *stack_size;
 427                 *stack_size += ALIGN_TO (size, 8);
 428                 ainfo->storage = ArgOnStack;
 429
 430                 return;
 431         }
 432
 433         /* FIXME: Handle structs smaller than 8 bytes */
 434         //if ((size % 8) != 0)
 435         //      NOT_IMPLEMENTED;
 436
 437         if (size > 8)
 438                 nquads = 2;
 439         else
 440                 nquads = 1;
 441
 442         if (!sig->pinvoke) {
 443                 /* Always pass in 1 or 2 integer registers */
 444                 args [0] = ARG_CLASS_INTEGER;
 445                 args [1] = ARG_CLASS_INTEGER;
 446                 /* Only the simplest cases are supported */
 447                 if (is_return && nquads != 1) {
 448                         args [0] = ARG_CLASS_MEMORY;
 449                         args [1] = ARG_CLASS_MEMORY;
 450                 }
 451         } else {
 452                 /*
 453                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 454                  * The X87 and SSEUP stuff is left out since there are no such types in
 455                  * the CLR.
 456                  */
 457                 info = mono_marshal_load_type_info (klass);
 458                 g_assert (info);
 459
 460 #ifndef PLATFORM_WIN32
 461                 if (info->native_size > 16) {
 462                         ainfo->offset = *stack_size;
 463                         *stack_size += ALIGN_TO (info->native_size, 8);
 464                         ainfo->storage = ArgOnStack;
 465
 466                         return;
 467                 }
 468 #else
 469                 switch (info->native_size) {
 470                 case 1: case 2: case 4: case 8:
 471                         break;
 472                 default:
 473                         if (is_return) {
 474                                 ainfo->storage = ArgOnStack;
 475                                 ainfo->offset = *stack_size;
 476                                 *stack_size += ALIGN_TO (info->native_size, 8);
 477                         }
 478                         else {
 479                                 ainfo->storage = ArgValuetypeAddrInIReg;
 480
 481                                 if (*gr < PARAM_REGS) {
 482                                         ainfo->pair_storage [0] = ArgInIReg;
 483                                         ainfo->pair_regs [0] = param_regs [*gr];
 484                                         (*gr) ++;
 485                                 }
 486                                 else {
 487                                         ainfo->pair_storage [0] = ArgOnStack;
 488                                         ainfo->offset = *stack_size;
 489                                         *stack_size += 8;
 490                                 }
 491                         }
 492
 493                         return;
 494                 }
 495 #endif
 496
 497                 args [0] = ARG_CLASS_NO_CLASS;
 498                 args [1] = ARG_CLASS_NO_CLASS;
 499                 for (quad = 0; quad < nquads; ++quad) {
 500                         int size;
 501                         guint32 align;
 502                         ArgumentClass class1;
 503
 504                         if (info->num_fields == 0)
 505                                 class1 = ARG_CLASS_MEMORY;
 506                         else
 507                                 class1 = ARG_CLASS_NO_CLASS;
 508                         for (i = 0; i < info->num_fields; ++i) {
 509                                 size = mono_marshal_type_size (info->fields [i].field->type,
 510                                                                                            info->fields [i].mspec,
 511                                                                                            &align, TRUE, klass->unicode);
 512                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 513                                         /* Unaligned field */
 514                                         NOT_IMPLEMENTED;
 515                                 }
 516
 517                                 /* Skip fields in other quad */
 518                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 519                                         continue;
 520                                 if ((quad == 1) && (info->fields [i].offset < 8))
 521                                         continue;
 522
 523                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 524                         }
 525                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 526                         args [quad] = class1;
 527                 }
 528         }
 529
 530         /* Post merger cleanup */
 531         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 532                 args [0] = args [1] = ARG_CLASS_MEMORY;
 533
 534         /* Allocate registers */
 535         {
 536                 int orig_gr = *gr;
 537                 int orig_fr = *fr;
 538
 539                 ainfo->storage = ArgValuetypeInReg;
 540                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 541                 for (quad = 0; quad < nquads; ++quad) {
 542                         switch (args [quad]) {
 543                         case ARG_CLASS_INTEGER:
 544                                 if (*gr >= PARAM_REGS)
 545                                         args [quad] = ARG_CLASS_MEMORY;
 546                                 else {
 547                                         ainfo->pair_storage [quad] = ArgInIReg;
 548                                         if (is_return)
 549                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 550                                         else
 551                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 552                                         (*gr) ++;
 553                                 }
 554                                 break;
 555                         case ARG_CLASS_SSE:
 556                                 if (*fr >= FLOAT_PARAM_REGS)
 557                                         args [quad] = ARG_CLASS_MEMORY;
 558                                 else {
 559                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 560                                         ainfo->pair_regs [quad] = *fr;
 561                                         (*fr) ++;
 562                                 }
 563                                 break;
 564                         case ARG_CLASS_MEMORY:
 565                                 break;
 566                         default:
 567                                 g_assert_not_reached ();
 568                         }
 569                 }
 570
 571                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 572                         /* Revert possible register assignments */
 573                         *gr = orig_gr;
 574                         *fr = orig_fr;
 575
 576                         ainfo->offset = *stack_size;
 577                         if (sig->pinvoke)
 578                                 *stack_size += ALIGN_TO (info->native_size, 8);
 579                         else
 580                                 *stack_size += nquads * sizeof (gpointer);
 581                         ainfo->storage = ArgOnStack;
 582                 }
 583         }
 584 }
 585
 586 /*
 587  * get_call_info:
 588  *
 589  *  Obtain information about a call according to the calling convention.
 590  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 591  * Draft Version 0.23" document for more information.
 592  */
 593 static CallInfo*
 594 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 595 {
 596         guint32 i, gr, fr;
 597         MonoType *ret_type;
 598         int n = sig->hasthis + sig->param_count;
 599         guint32 stack_size = 0;
 600         CallInfo *cinfo;
 601
 602         if (mp)
 603                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 604         else
 605                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606
 607         gr = 0;
 608         fr = 0;
 609
 610         /* return value */
 611         {
 612                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 613                 switch (ret_type->type) {
 614                 case MONO_TYPE_BOOLEAN:
 615                 case MONO_TYPE_I1:
 616                 case MONO_TYPE_U1:
 617                 case MONO_TYPE_I2:
 618                 case MONO_TYPE_U2:
 619                 case MONO_TYPE_CHAR:
 620                 case MONO_TYPE_I4:
 621                 case MONO_TYPE_U4:
 622                 case MONO_TYPE_I:
 623                 case MONO_TYPE_U:
 624                 case MONO_TYPE_PTR:
 625                 case MONO_TYPE_FNPTR:
 626                 case MONO_TYPE_CLASS:
 627                 case MONO_TYPE_OBJECT:
 628                 case MONO_TYPE_SZARRAY:
 629                 case MONO_TYPE_ARRAY:
 630                 case MONO_TYPE_STRING:
 631                         cinfo->ret.storage = ArgInIReg;
 632                         cinfo->ret.reg = AMD64_RAX;
 633                         break;
 634                 case MONO_TYPE_U8:
 635                 case MONO_TYPE_I8:
 636                         cinfo->ret.storage = ArgInIReg;
 637                         cinfo->ret.reg = AMD64_RAX;
 638                         break;
 639                 case MONO_TYPE_R4:
 640                         cinfo->ret.storage = ArgInFloatSSEReg;
 641                         cinfo->ret.reg = AMD64_XMM0;
 642                         break;
 643                 case MONO_TYPE_R8:
 644                         cinfo->ret.storage = ArgInDoubleSSEReg;
 645                         cinfo->ret.reg = AMD64_XMM0;
 646                         break;
 647                 case MONO_TYPE_GENERICINST:
 648                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 649                                 cinfo->ret.storage = ArgInIReg;
 650                                 cinfo->ret.reg = AMD64_RAX;
 651                                 break;
 652                         }
 653                         /* fall through */
 654                 case MONO_TYPE_VALUETYPE: {
 655                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 656
 657                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 658                         if (cinfo->ret.storage == ArgOnStack)
 659                                 /* The caller passes the address where the value is stored */
 660                                 add_general (&gr, &stack_size, &cinfo->ret);
 661                         break;
 662                 }
 663                 case MONO_TYPE_TYPEDBYREF:
 664                         /* Same as a valuetype with size 24 */
 665                         add_general (&gr, &stack_size, &cinfo->ret);
 666                         ;
 667                         break;
 668                 case MONO_TYPE_VOID:
 669                         break;
 670                 default:
 671                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 672                 }
 673         }
 674
 675         /* this */
 676         if (sig->hasthis)
 677                 add_general (&gr, &stack_size, cinfo->args + 0);
 678
 679         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 680                 gr = PARAM_REGS;
 681                 fr = FLOAT_PARAM_REGS;
 682
 683                 /* Emit the signature cookie just before the implicit arguments */
 684                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 685         }
 686
 687         for (i = 0; i < sig->param_count; ++i) {
 688                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 689                 MonoType *ptype;
 690
 691 #ifdef PLATFORM_WIN32
 692                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 693                 if (gr > fr)
 694                         fr = gr;
 695                 else if (fr > gr)
 696                         gr = fr;
 697 #endif
 698
 699                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 700                         /* We allways pass the sig cookie on the stack for simplicity */
 701                         /*
 702                          * Prevent implicit arguments + the sig cookie from being passed
 703                          * in registers.
 704                          */
 705                         gr = PARAM_REGS;
 706                         fr = FLOAT_PARAM_REGS;
 707
 708                         /* Emit the signature cookie just before the implicit arguments */
 709                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 710                 }
 711
 712                 if (sig->params [i]->byref) {
 713                         add_general (&gr, &stack_size, ainfo);
 714                         continue;
 715                 }
 716                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 717                 switch (ptype->type) {
 718                 case MONO_TYPE_BOOLEAN:
 719                 case MONO_TYPE_I1:
 720                 case MONO_TYPE_U1:
 721                         add_general (&gr, &stack_size, ainfo);
 722                         break;
 723                 case MONO_TYPE_I2:
 724                 case MONO_TYPE_U2:
 725                 case MONO_TYPE_CHAR:
 726                         add_general (&gr, &stack_size, ainfo);
 727                         break;
 728                 case MONO_TYPE_I4:
 729                 case MONO_TYPE_U4:
 730                         add_general (&gr, &stack_size, ainfo);
 731                         break;
 732                 case MONO_TYPE_I:
 733                 case MONO_TYPE_U:
 734                 case MONO_TYPE_PTR:
 735                 case MONO_TYPE_FNPTR:
 736                 case MONO_TYPE_CLASS:
 737                 case MONO_TYPE_OBJECT:
 738                 case MONO_TYPE_STRING:
 739                 case MONO_TYPE_SZARRAY:
 740                 case MONO_TYPE_ARRAY:
 741                         add_general (&gr, &stack_size, ainfo);
 742                         break;
 743                 case MONO_TYPE_GENERICINST:
 744                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 745                                 add_general (&gr, &stack_size, ainfo);
 746                                 break;
 747                         }
 748                         /* fall through */
 749                 case MONO_TYPE_VALUETYPE:
 750                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 751                         break;
 752                 case MONO_TYPE_TYPEDBYREF:
 753 #ifdef PLATFORM_WIN32
 754                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 755 #else
 756                         stack_size += sizeof (MonoTypedRef);
 757                         ainfo->storage = ArgOnStack;
 758 #endif
 759                         break;
 760                 case MONO_TYPE_U8:
 761                 case MONO_TYPE_I8:
 762                         add_general (&gr, &stack_size, ainfo);
 763                         break;
 764                 case MONO_TYPE_R4:
 765                         add_float (&fr, &stack_size, ainfo, FALSE);
 766                         break;
 767                 case MONO_TYPE_R8:
 768                         add_float (&fr, &stack_size, ainfo, TRUE);
 769                         break;
 770                 default:
 771                         g_assert_not_reached ();
 772                 }
 773         }
 774
 775         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 776                 gr = PARAM_REGS;
 777                 fr = FLOAT_PARAM_REGS;
 778
 779                 /* Emit the signature cookie just before the implicit arguments */
 780                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 781         }
 782
 783 #ifdef PLATFORM_WIN32
 784         // There always is 32 bytes reserved on the stack when calling on Winx64
 785         stack_size += 0x20;
 786 #endif
 787
 788         if (stack_size & 0x8) {
 789                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 790                 cinfo->need_stack_align = TRUE;
 791                 stack_size += 8;
 792         }
 793
 794         cinfo->stack_usage = stack_size;
 795         cinfo->reg_usage = gr;
 796         cinfo->freg_usage = fr;
 797         return cinfo;
 798 }
 799
 800 /*
 801  * mono_arch_get_argument_info:
 802  * @csig:  a method signature
 803  * @param_count: the number of parameters to consider
 804  * @arg_info: an array to store the result infos
 805  *
 806  * Gathers information on parameters such as size, alignment and
 807  * padding. arg_info should be large enought to hold param_count + 1 entries.
 808  *
 809  * Returns the size of the argument area on the stack.
 810  */
 811 int
 812 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 813 {
 814         int k;
 815         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 816         guint32 args_size = cinfo->stack_usage;
 817
 818         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 819         if (csig->hasthis) {
 820                 arg_info [0].offset = 0;
 821         }
 822
 823         for (k = 0; k < param_count; k++) {
 824                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 825                 /* FIXME: */
 826                 arg_info [k + 1].size = 0;
 827         }
 828
 829         g_free (cinfo);
 830
 831         return args_size;
 832 }
 833
 834 static int
 835 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 836 {
 837 #ifndef _MSC_VER
 838         __asm__ __volatile__ ("cpuid"
 839                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 840                 : "a" (id));
 841 #else
 842         int info[4];
 843         __cpuid(info, id);
 844         *p_eax = info[0];
 845         *p_ebx = info[1];
 846         *p_ecx = info[2];
 847         *p_edx = info[3];
 848 #endif
 849         return 1;
 850 }
 851
 852 /*
 853  * Initialize the cpu to execute managed code.
 854  */
 855 void
 856 mono_arch_cpu_init (void)
 857 {
 858 #ifndef _MSC_VER
 859         guint16 fpcw;
 860
 861         /* spec compliance requires running with double precision */
 862         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 863         fpcw &= ~X86_FPCW_PRECC_MASK;
 864         fpcw |= X86_FPCW_PREC_DOUBLE;
 865         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 866         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 867 #else
 868         /* TODO: This is crashing on Win64 right now.
 869         * _control87 (_PC_53, MCW_PC);
 870         */
 871 #endif
 872 }
 873
 874 /*
 875  * Initialize architecture specific code.
 876  */
 877 void
 878 mono_arch_init (void)
 879 {
 880         InitializeCriticalSection (&mini_arch_mutex);
 881 }
 882
 883 /*
 884  * Cleanup architecture specific code.
 885  */
 886 void
 887 mono_arch_cleanup (void)
 888 {
 889         DeleteCriticalSection (&mini_arch_mutex);
 890 }
 891
 892 /*
 893  * This function returns the optimizations supported on this cpu.
 894  */
 895 guint32
 896 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 897 {
 898         int eax, ebx, ecx, edx;
 899         guint32 opts = 0;
 900
 901         /* FIXME: AMD64 */
 902
 903         *exclude_mask = 0;
 904         /* Feature Flags function, flags returned in EDX. */
 905         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 906                 if (edx & (1 << 15)) {
 907                         opts |= MONO_OPT_CMOV;
 908                         if (edx & 1)
 909                                 opts |= MONO_OPT_FCMOV;
 910                         else
 911                                 *exclude_mask |= MONO_OPT_FCMOV;
 912                 } else
 913                         *exclude_mask |= MONO_OPT_CMOV;
 914         }
 915
 916         return opts;
 917 }
 918
 919 /*
 920  * This function test for all SSE functions supported.
 921  *
 922  * Returns a bitmask corresponding to all supported versions.
 923  *
 924  * TODO detect other versions like SSE4a.
 925  */
 926 guint32
 927 mono_arch_cpu_enumerate_simd_versions (void)
 928 {
 929         int eax, ebx, ecx, edx;
 930         guint32 sse_opts = 0;
 931
 932         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 933                 if (edx & (1 << 25))
 934                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 935                 if (edx & (1 << 26))
 936                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 937                 if (ecx & (1 << 0))
 938                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 939                 if (ecx & (1 << 9))
 940                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 941                 if (ecx & (1 << 19))
 942                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 943                 if (ecx & (1 << 20))
 944                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 945         }
 946         return sse_opts;
 947 }
 948
 949 GList *
 950 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 951 {
 952         GList *vars = NULL;
 953         int i;
 954
 955         for (i = 0; i < cfg->num_varinfo; i++) {
 956                 MonoInst *ins = cfg->varinfo [i];
 957                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 958
 959                 /* unused vars */
 960                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 961                         continue;
 962
 963                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 964                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 965                         continue;
 966
 967                 if (mono_is_regsize_var (ins->inst_vtype)) {
 968                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 969                         g_assert (i == vmv->idx);
 970                         vars = g_list_prepend (vars, vmv);
 971                 }
 972         }
 973
 974         vars = mono_varlist_sort (cfg, vars, 0);
 975
 976         return vars;
 977 }
 978
 979 /**
 980  * mono_arch_compute_omit_fp:
 981  *
 982  *   Determine whenever the frame pointer can be eliminated.
 983  */
 984 static void
 985 mono_arch_compute_omit_fp (MonoCompile *cfg)
 986 {
 987         MonoMethodSignature *sig;
 988         MonoMethodHeader *header;
 989         int i, locals_size;
 990         CallInfo *cinfo;
 991
 992         if (cfg->arch.omit_fp_computed)
 993                 return;
 994
 995         header = mono_method_get_header (cfg->method);
 996
 997         sig = mono_method_signature (cfg->method);
 998
 999         if (!cfg->arch.cinfo)
1000                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1001         cinfo = cfg->arch.cinfo;
1002
1003         /*
1004          * FIXME: Remove some of the restrictions.
1005          */
1006         cfg->arch.omit_fp = TRUE;
1007         cfg->arch.omit_fp_computed = TRUE;
1008
1009         if (cfg->disable_omit_fp)
1010                 cfg->arch.omit_fp = FALSE;
1011
1012         if (!debug_omit_fp ())
1013                 cfg->arch.omit_fp = FALSE;
1014         /*
1015         if (cfg->method->save_lmf)
1016                 cfg->arch.omit_fp = FALSE;
1017         */
1018         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1019                 cfg->arch.omit_fp = FALSE;
1020         if (header->num_clauses)
1021                 cfg->arch.omit_fp = FALSE;
1022         if (cfg->param_area)
1023                 cfg->arch.omit_fp = FALSE;
1024         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1025                 cfg->arch.omit_fp = FALSE;
1026         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1027                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1028                 cfg->arch.omit_fp = FALSE;
1029         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1030                 ArgInfo *ainfo = &cinfo->args [i];
1031
1032                 if (ainfo->storage == ArgOnStack) {
1033                         /*
1034                          * The stack offset can only be determined when the frame
1035                          * size is known.
1036                          */
1037                         cfg->arch.omit_fp = FALSE;
1038                 }
1039         }
1040
1041         locals_size = 0;
1042         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1043                 MonoInst *ins = cfg->varinfo [i];
1044                 int ialign;
1045
1046                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1047         }
1048 }
1049
1050 GList *
1051 mono_arch_get_global_int_regs (MonoCompile *cfg)
1052 {
1053         GList *regs = NULL;
1054
1055         mono_arch_compute_omit_fp (cfg);
1056
1057         if (cfg->globalra) {
1058                 if (cfg->arch.omit_fp)
1059                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1060
1061                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1062                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1063                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1064                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1065                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1066
1067                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1068                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1069                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1070                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1071                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1072                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1073                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1074                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1075         } else {
1076                 if (cfg->arch.omit_fp)
1077                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1078
1079                 /* We use the callee saved registers for global allocation */
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1085 #ifdef PLATFORM_WIN32
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1088 #endif
1089         }
1090
1091         return regs;
1092 }
1093
1094 GList*
1095 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1096 {
1097         GList *regs = NULL;
1098         int i;
1099
1100         /* All XMM registers */
1101         for (i = 0; i < 16; ++i)
1102                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1103
1104         return regs;
1105 }
1106
1107 GList*
1108 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1109 {
1110         static GList *r = NULL;
1111
1112         if (r == NULL) {
1113                 GList *regs = NULL;
1114
1115                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1116                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1117                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1118                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1119                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1120                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1121
1122                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1123                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1124                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1125                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1126                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1127                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1128                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1129                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1130
1131                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1132         }
1133
1134         return r;
1135 }
1136
1137 GList*
1138 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1139 {
1140         int i;
1141         static GList *r = NULL;
1142
1143         if (r == NULL) {
1144                 GList *regs = NULL;
1145
1146                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1147                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1148
1149                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1150         }
1151
1152         return r;
1153 }
1154
1155 /*
1156  * mono_arch_regalloc_cost:
1157  *
1158  *  Return the cost, in number of memory references, of the action of
1159  * allocating the variable VMV into a register during global register
1160  * allocation.
1161  */
1162 guint32
1163 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1164 {
1165         MonoInst *ins = cfg->varinfo [vmv->idx];
1166
1167         if (cfg->method->save_lmf)
1168                 /* The register is already saved */
1169                 /* substract 1 for the invisible store in the prolog */
1170                 return (ins->opcode == OP_ARG) ? 0 : 1;
1171         else
1172                 /* push+pop */
1173                 return (ins->opcode == OP_ARG) ? 1 : 2;
1174 }
1175
1176 /*
1177  * mono_arch_fill_argument_info:
1178  *
1179  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1180  * of the method.
1181  */
1182 void
1183 mono_arch_fill_argument_info (MonoCompile *cfg)
1184 {
1185         MonoMethodSignature *sig;
1186         MonoMethodHeader *header;
1187         MonoInst *ins;
1188         int i;
1189         CallInfo *cinfo;
1190
1191         header = mono_method_get_header (cfg->method);
1192
1193         sig = mono_method_signature (cfg->method);
1194
1195         cinfo = cfg->arch.cinfo;
1196
1197         /*
1198          * Contrary to mono_arch_allocate_vars (), the information should describe
1199          * where the arguments are at the beginning of the method, not where they can be
1200          * accessed during the execution of the method. The later makes no sense for the
1201          * global register allocator, since a variable can be in more than one location.
1202          */
1203         if (sig->ret->type != MONO_TYPE_VOID) {
1204                 switch (cinfo->ret.storage) {
1205                 case ArgInIReg:
1206                 case ArgInFloatSSEReg:
1207                 case ArgInDoubleSSEReg:
1208                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1209                                 cfg->vret_addr->opcode = OP_REGVAR;
1210                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1211                         }
1212                         else {
1213                                 cfg->ret->opcode = OP_REGVAR;
1214                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1215                         }
1216                         break;
1217                 case ArgValuetypeInReg:
1218                         cfg->ret->opcode = OP_REGOFFSET;
1219                         cfg->ret->inst_basereg = -1;
1220                         cfg->ret->inst_offset = -1;
1221                         break;
1222                 default:
1223                         g_assert_not_reached ();
1224                 }
1225         }
1226
1227         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1228                 ArgInfo *ainfo = &cinfo->args [i];
1229                 MonoType *arg_type;
1230
1231                 ins = cfg->args [i];
1232
1233                 if (sig->hasthis && (i == 0))
1234                         arg_type = &mono_defaults.object_class->byval_arg;
1235                 else
1236                         arg_type = sig->params [i - sig->hasthis];
1237
1238                 switch (ainfo->storage) {
1239                 case ArgInIReg:
1240                 case ArgInFloatSSEReg:
1241                 case ArgInDoubleSSEReg:
1242                         ins->opcode = OP_REGVAR;
1243                         ins->inst_c0 = ainfo->reg;
1244                         break;
1245                 case ArgOnStack:
1246                         ins->opcode = OP_REGOFFSET;
1247                         ins->inst_basereg = -1;
1248                         ins->inst_offset = -1;
1249                         break;
1250                 case ArgValuetypeInReg:
1251                         /* Dummy */
1252                         ins->opcode = OP_NOP;
1253                         break;
1254                 default:
1255                         g_assert_not_reached ();
1256                 }
1257         }
1258 }
1259
1260 void
1261 mono_arch_allocate_vars (MonoCompile *cfg)
1262 {
1263         MonoMethodSignature *sig;
1264         MonoMethodHeader *header;
1265         MonoInst *ins;
1266         int i, offset;
1267         guint32 locals_stack_size, locals_stack_align;
1268         gint32 *offsets;
1269         CallInfo *cinfo;
1270
1271         header = mono_method_get_header (cfg->method);
1272
1273         sig = mono_method_signature (cfg->method);
1274
1275         cinfo = cfg->arch.cinfo;
1276
1277         mono_arch_compute_omit_fp (cfg);
1278
1279         /*
1280          * We use the ABI calling conventions for managed code as well.
1281          * Exception: valuetypes are only sometimes passed or returned in registers.
1282          */
1283
1284         /*
1285          * The stack looks like this:
1286          * <incoming arguments passed on the stack>
1287          * <return value>
1288          * <lmf/caller saved registers>
1289          * <locals>
1290          * <spill area>
1291          * <localloc area>  -> grows dynamically
1292          * <params area>
1293          */
1294
1295         if (cfg->arch.omit_fp) {
1296                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1297                 cfg->frame_reg = AMD64_RSP;
1298                 offset = 0;
1299         } else {
1300                 /* Locals are allocated backwards from %fp */
1301                 cfg->frame_reg = AMD64_RBP;
1302                 offset = 0;
1303         }
1304
1305         if (cfg->method->save_lmf) {
1306                 /* Reserve stack space for saving LMF */
1307                 if (cfg->arch.omit_fp) {
1308                         cfg->arch.lmf_offset = offset;
1309                         offset += sizeof (MonoLMF);
1310                 }
1311                 else {
1312                         offset += sizeof (MonoLMF);
1313                         cfg->arch.lmf_offset = -offset;
1314                 }
1315         } else {
1316                 if (cfg->arch.omit_fp)
1317                         cfg->arch.reg_save_area_offset = offset;
1318                 /* Reserve space for caller saved registers */
1319                 for (i = 0; i < AMD64_NREG; ++i)
1320                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1321                                 offset += sizeof (gpointer);
1322                         }
1323         }
1324
1325         if (sig->ret->type != MONO_TYPE_VOID) {
1326                 switch (cinfo->ret.storage) {
1327                 case ArgInIReg:
1328                 case ArgInFloatSSEReg:
1329                 case ArgInDoubleSSEReg:
1330                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1331                                 if (cfg->globalra) {
1332                                         cfg->vret_addr->opcode = OP_REGVAR;
1333                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1334                                 } else {
1335                                         /* The register is volatile */
1336                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1337                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1338                                         if (cfg->arch.omit_fp) {
1339                                                 cfg->vret_addr->inst_offset = offset;
1340                                                 offset += 8;
1341                                         } else {
1342                                                 offset += 8;
1343                                                 cfg->vret_addr->inst_offset = -offset;
1344                                         }
1345                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1346                                                 printf ("vret_addr =");
1347                                                 mono_print_ins (cfg->vret_addr);
1348                                         }
1349                                 }
1350                         }
1351                         else {
1352                                 cfg->ret->opcode = OP_REGVAR;
1353                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1354                         }
1355                         break;
1356                 case ArgValuetypeInReg:
1357                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1358                         cfg->ret->opcode = OP_REGOFFSET;
1359                         cfg->ret->inst_basereg = cfg->frame_reg;
1360                         if (cfg->arch.omit_fp) {
1361                                 cfg->ret->inst_offset = offset;
1362                                 offset += 16;
1363                         } else {
1364                                 offset += 16;
1365                                 cfg->ret->inst_offset = - offset;
1366                         }
1367                         break;
1368                 default:
1369                         g_assert_not_reached ();
1370                 }
1371                 if (!cfg->globalra)
1372                         cfg->ret->dreg = cfg->ret->inst_c0;
1373         }
1374
1375         /* Allocate locals */
1376         if (!cfg->globalra) {
1377                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1378                 if (locals_stack_align) {
1379                         offset += (locals_stack_align - 1);
1380                         offset &= ~(locals_stack_align - 1);
1381                 }
1382                 if (cfg->arch.omit_fp) {
1383                         cfg->locals_min_stack_offset = offset;
1384                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1385                 } else {
1386                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1387                         cfg->locals_max_stack_offset = - offset;
1388                 }
1389
1390                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1391                         if (offsets [i] != -1) {
1392                                 MonoInst *ins = cfg->varinfo [i];
1393                                 ins->opcode = OP_REGOFFSET;
1394                                 ins->inst_basereg = cfg->frame_reg;
1395                                 if (cfg->arch.omit_fp)
1396                                         ins->inst_offset = (offset + offsets [i]);
1397                                 else
1398                                         ins->inst_offset = - (offset + offsets [i]);
1399                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1400                         }
1401                 }
1402                 offset += locals_stack_size;
1403         }
1404
1405         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1406                 g_assert (!cfg->arch.omit_fp);
1407                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1408                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1409         }
1410
1411         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1412                 ins = cfg->args [i];
1413                 if (ins->opcode != OP_REGVAR) {
1414                         ArgInfo *ainfo = &cinfo->args [i];
1415                         gboolean inreg = TRUE;
1416                         MonoType *arg_type;
1417
1418                         if (sig->hasthis && (i == 0))
1419                                 arg_type = &mono_defaults.object_class->byval_arg;
1420                         else
1421                                 arg_type = sig->params [i - sig->hasthis];
1422
1423                         if (cfg->globalra) {
1424                                 /* The new allocator needs info about the original locations of the arguments */
1425                                 switch (ainfo->storage) {
1426                                 case ArgInIReg:
1427                                 case ArgInFloatSSEReg:
1428                                 case ArgInDoubleSSEReg:
1429                                         ins->opcode = OP_REGVAR;
1430                                         ins->inst_c0 = ainfo->reg;
1431                                         break;
1432                                 case ArgOnStack:
1433                                         g_assert (!cfg->arch.omit_fp);
1434                                         ins->opcode = OP_REGOFFSET;
1435                                         ins->inst_basereg = cfg->frame_reg;
1436                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1437                                         break;
1438                                 case ArgValuetypeInReg:
1439                                         ins->opcode = OP_REGOFFSET;
1440                                         ins->inst_basereg = cfg->frame_reg;
1441                                         /* These arguments are saved to the stack in the prolog */
1442                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1443                                         if (cfg->arch.omit_fp) {
1444                                                 ins->inst_offset = offset;
1445                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1446                                         } else {
1447                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1448                                                 ins->inst_offset = - offset;
1449                                         }
1450                                         break;
1451                                 default:
1452                                         g_assert_not_reached ();
1453                                 }
1454
1455                                 continue;
1456                         }
1457
1458                         /* FIXME: Allocate volatile arguments to registers */
1459                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1460                                 inreg = FALSE;
1461
1462                         /*
1463                          * Under AMD64, all registers used to pass arguments to functions
1464                          * are volatile across calls.
1465                          * FIXME: Optimize this.
1466                          */
1467                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1468                                 inreg = FALSE;
1469
1470                         ins->opcode = OP_REGOFFSET;
1471
1472                         switch (ainfo->storage) {
1473                         case ArgInIReg:
1474                         case ArgInFloatSSEReg:
1475                         case ArgInDoubleSSEReg:
1476                                 if (inreg) {
1477                                         ins->opcode = OP_REGVAR;
1478                                         ins->dreg = ainfo->reg;
1479                                 }
1480                                 break;
1481                         case ArgOnStack:
1482                                 g_assert (!cfg->arch.omit_fp);
1483                                 ins->opcode = OP_REGOFFSET;
1484                                 ins->inst_basereg = cfg->frame_reg;
1485                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1486                                 break;
1487                         case ArgValuetypeInReg:
1488                                 break;
1489                         case ArgValuetypeAddrInIReg: {
1490                                 MonoInst *indir;
1491                                 g_assert (!cfg->arch.omit_fp);
1492
1493                                 MONO_INST_NEW (cfg, indir, 0);
1494                                 indir->opcode = OP_REGOFFSET;
1495                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1496                                         indir->inst_basereg = cfg->frame_reg;
1497                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1498                                         offset += (sizeof (gpointer));
1499                                         indir->inst_offset = - offset;
1500                                 }
1501                                 else {
1502                                         indir->inst_basereg = cfg->frame_reg;
1503                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1504                                 }
1505
1506                                 ins->opcode = OP_VTARG_ADDR;
1507                                 ins->inst_left = indir;
1508
1509                                 break;
1510                         }
1511                         default:
1512                                 NOT_IMPLEMENTED;
1513                         }
1514
1515                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1516                                 ins->opcode = OP_REGOFFSET;
1517                                 ins->inst_basereg = cfg->frame_reg;
1518                                 /* These arguments are saved to the stack in the prolog */
1519                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1520                                 if (cfg->arch.omit_fp) {
1521                                         ins->inst_offset = offset;
1522                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1523                                 } else {
1524                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1525                                         ins->inst_offset = - offset;
1526                                 }
1527                         }
1528                 }
1529         }
1530
1531         cfg->stack_offset = offset;
1532 }
1533
1534 void
1535 mono_arch_create_vars (MonoCompile *cfg)
1536 {
1537         MonoMethodSignature *sig;
1538         CallInfo *cinfo;
1539
1540         sig = mono_method_signature (cfg->method);
1541
1542         if (!cfg->arch.cinfo)
1543                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1544         cinfo = cfg->arch.cinfo;
1545
1546         if (cinfo->ret.storage == ArgValuetypeInReg)
1547                 cfg->ret_var_is_local = TRUE;
1548
1549         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1550                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1551                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1552                         printf ("vret_addr = ");
1553                         mono_print_ins (cfg->vret_addr);
1554                 }
1555         }
1556
1557 #ifdef MONO_AMD64_NO_PUSHES
1558         /*
1559          * When this is set, we pass arguments on the stack by moves, and by allocating
1560          * a bigger stack frame, instead of pushes.
1561          * Pushes complicate exception handling because the arguments on the stack have
1562          * to be popped each time a frame is unwound. They also make fp elimination
1563          * impossible.
1564          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1565          * on a new frame which doesn't include a param area.
1566          */
1567         cfg->arch.no_pushes = TRUE;
1568 #endif
1569 }
1570
1571 static void
1572 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1573 {
1574         MonoInst *ins;
1575
1576         switch (storage) {
1577         case ArgInIReg:
1578                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1579                 ins->dreg = mono_alloc_ireg (cfg);
1580                 ins->sreg1 = tree->dreg;
1581                 MONO_ADD_INS (cfg->cbb, ins);
1582                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1583                 break;
1584         case ArgInFloatSSEReg:
1585                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1586                 ins->dreg = mono_alloc_freg (cfg);
1587                 ins->sreg1 = tree->dreg;
1588                 MONO_ADD_INS (cfg->cbb, ins);
1589
1590                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1591                 break;
1592         case ArgInDoubleSSEReg:
1593                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1594                 ins->dreg = mono_alloc_freg (cfg);
1595                 ins->sreg1 = tree->dreg;
1596                 MONO_ADD_INS (cfg->cbb, ins);
1597
1598                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1599
1600                 break;
1601         default:
1602                 g_assert_not_reached ();
1603         }
1604 }
1605
1606 static int
1607 arg_storage_to_load_membase (ArgStorage storage)
1608 {
1609         switch (storage) {
1610         case ArgInIReg:
1611                 return OP_LOAD_MEMBASE;
1612         case ArgInDoubleSSEReg:
1613                 return OP_LOADR8_MEMBASE;
1614         case ArgInFloatSSEReg:
1615                 return OP_LOADR4_MEMBASE;
1616         default:
1617                 g_assert_not_reached ();
1618         }
1619
1620         return -1;
1621 }
1622
1623 static void
1624 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1625 {
1626         MonoInst *arg;
1627         MonoMethodSignature *tmp_sig;
1628         MonoInst *sig_arg;
1629
1630         if (call->tail_call)
1631                 NOT_IMPLEMENTED;
1632
1633         /* FIXME: Add support for signature tokens to AOT */
1634         cfg->disable_aot = TRUE;
1635
1636         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1637
1638         /*
1639          * mono_ArgIterator_Setup assumes the signature cookie is
1640          * passed first and all the arguments which were before it are
1641          * passed on the stack after the signature. So compensate by
1642          * passing a different signature.
1643          */
1644         tmp_sig = mono_metadata_signature_dup (call->signature);
1645         tmp_sig->param_count -= call->signature->sentinelpos;
1646         tmp_sig->sentinelpos = 0;
1647         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1648
1649         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1650         sig_arg->dreg = mono_alloc_ireg (cfg);
1651         sig_arg->inst_p0 = tmp_sig;
1652         MONO_ADD_INS (cfg->cbb, sig_arg);
1653
1654         if (cfg->arch.no_pushes) {
1655                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1656         } else {
1657                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1658                 arg->sreg1 = sig_arg->dreg;
1659                 MONO_ADD_INS (cfg->cbb, arg);
1660         }
1661 }
1662
1663 static inline LLVMArgStorage
1664 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1665 {
1666         switch (storage) {
1667         case ArgInIReg:
1668                 return LLVMArgInIReg;
1669         case ArgNone:
1670                 return LLVMArgNone;
1671         default:
1672                 g_assert_not_reached ();
1673                 return LLVMArgNone;
1674         }
1675 }
1676
1677 #ifdef ENABLE_LLVM
1678 LLVMCallInfo*
1679 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1680 {
1681         int i, n;
1682         CallInfo *cinfo;
1683         ArgInfo *ainfo;
1684         int j;
1685         LLVMCallInfo *linfo;
1686
1687         n = sig->param_count + sig->hasthis;
1688
1689         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1690
1691         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1692
1693         /*
1694          * LLVM always uses the native ABI while we use our own ABI, the
1695          * only difference is the handling of vtypes:
1696          * - we only pass/receive them in registers in some cases, and only
1697          *   in 1 or 2 integer registers.
1698          */
1699         if (cinfo->ret.storage == ArgValuetypeInReg) {
1700                 if (sig->pinvoke) {
1701                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1702                         cfg->disable_llvm = TRUE;
1703                         return linfo;
1704                 }
1705
1706                 linfo->ret.storage = LLVMArgVtypeInReg;
1707                 for (j = 0; j < 2; ++j)
1708                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1709         }
1710
1711         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1712                 /* Vtype returned using a hidden argument */
1713                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1714         }
1715
1716         for (i = 0; i < n; ++i) {
1717                 ainfo = cinfo->args + i;
1718
1719                 linfo->args [i].storage = LLVMArgNone;
1720
1721                 switch (ainfo->storage) {
1722                 case ArgInIReg:
1723                         linfo->args [i].storage = LLVMArgInIReg;
1724                         break;
1725                 case ArgInDoubleSSEReg:
1726                 case ArgInFloatSSEReg:
1727                         linfo->args [i].storage = LLVMArgInFPReg;
1728                         break;
1729                 case ArgOnStack:
1730                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1731                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1732                         } else {
1733                                 linfo->args [i].storage = LLVMArgInIReg;
1734                                 if (!sig->params [i - sig->hasthis]->byref) {
1735                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1736                                                 linfo->args [i].storage = LLVMArgInFPReg;
1737                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1738                                                 linfo->args [i].storage = LLVMArgInFPReg;
1739                                         }
1740                                 }
1741                         }
1742                         break;
1743                 case ArgValuetypeInReg:
1744                         if (sig->pinvoke) {
1745                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1746                                 cfg->disable_llvm = TRUE;
1747                                 return linfo;
1748                         }
1749
1750                         linfo->args [i].storage = LLVMArgVtypeInReg;
1751                         for (j = 0; j < 2; ++j)
1752                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1753                         break;
1754                 default:
1755                         cfg->exception_message = g_strdup ("ainfo->storage");
1756                         cfg->disable_llvm = TRUE;
1757                         break;
1758                 }
1759         }
1760
1761         return linfo;
1762 }
1763 #endif
1764
1765 void
1766 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1767 {
1768         MonoInst *arg, *in;
1769         MonoMethodSignature *sig;
1770         int i, n, stack_size;
1771         CallInfo *cinfo;
1772         ArgInfo *ainfo;
1773
1774         stack_size = 0;
1775
1776         sig = call->signature;
1777         n = sig->param_count + sig->hasthis;
1778
1779         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1780
1781         if (COMPILE_LLVM (cfg)) {
1782                 /* We shouldn't be called in the llvm case */
1783                 cfg->disable_llvm = TRUE;
1784                 return;
1785         }
1786
1787         if (cinfo->need_stack_align) {
1788                 if (!cfg->arch.no_pushes)
1789                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1790         }
1791
1792         /*
1793          * Emit all arguments which are passed on the stack to prevent register
1794          * allocation problems.
1795          */
1796         if (cfg->arch.no_pushes) {
1797                 for (i = 0; i < n; ++i) {
1798                         MonoType *t;
1799                         ainfo = cinfo->args + i;
1800
1801                         in = call->args [i];
1802
1803                         if (sig->hasthis && i == 0)
1804                                 t = &mono_defaults.object_class->byval_arg;
1805                         else
1806                                 t = sig->params [i - sig->hasthis];
1807
1808                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1809                                 if (!t->byref) {
1810                                         if (t->type == MONO_TYPE_R4)
1811                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1812                                         else if (t->type == MONO_TYPE_R8)
1813                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1814                                         else
1815                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1816                                 } else {
1817                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1818                                 }
1819                         }
1820                 }
1821         }
1822
1823         /*
1824          * Emit all parameters passed in registers in non-reverse order for better readability
1825          * and to help the optimization in emit_prolog ().
1826          */
1827         for (i = 0; i < n; ++i) {
1828                 ainfo = cinfo->args + i;
1829
1830                 in = call->args [i];
1831
1832                 if (ainfo->storage == ArgInIReg)
1833                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1834         }
1835
1836         for (i = n - 1; i >= 0; --i) {
1837                 ainfo = cinfo->args + i;
1838
1839                 in = call->args [i];
1840
1841                 switch (ainfo->storage) {
1842                 case ArgInIReg:
1843                         /* Already done */
1844                         break;
1845                 case ArgInFloatSSEReg:
1846                 case ArgInDoubleSSEReg:
1847                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1848                         break;
1849                 case ArgOnStack:
1850                 case ArgValuetypeInReg:
1851                 case ArgValuetypeAddrInIReg:
1852                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1853                                 MonoInst *call_inst = (MonoInst*)call;
1854                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1855                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1856                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1857                                 guint32 align;
1858                                 guint32 size;
1859
1860                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1861                                         size = sizeof (MonoTypedRef);
1862                                         align = sizeof (gpointer);
1863                                 }
1864                                 else {
1865                                         if (sig->pinvoke)
1866                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1867                                         else {
1868                                                 /*
1869                                                  * Other backends use mono_type_stack_size (), but that
1870                                                  * aligns the size to 8, which is larger than the size of
1871                                                  * the source, leading to reads of invalid memory if the
1872                                                  * source is at the end of address space.
1873                                                  */
1874                                                 size = mono_class_value_size (in->klass, &align);
1875                                         }
1876                                 }
1877                                 g_assert (in->klass);
1878
1879                                 if (size > 0) {
1880                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1881                                         arg->sreg1 = in->dreg;
1882                                         arg->klass = in->klass;
1883                                         arg->backend.size = size;
1884                                         arg->inst_p0 = call;
1885                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1886                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1887
1888                                         MONO_ADD_INS (cfg->cbb, arg);
1889                                 }
1890                         } else {
1891                                 if (cfg->arch.no_pushes) {
1892                                         /* Already done */
1893                                 } else {
1894                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1895                                         arg->sreg1 = in->dreg;
1896                                         if (!sig->params [i - sig->hasthis]->byref) {
1897                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1898                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1899                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1900                                                         arg->inst_destbasereg = X86_ESP;
1901                                                         arg->inst_offset = 0;
1902                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1903                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1904                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1905                                                         arg->inst_destbasereg = X86_ESP;
1906                                                         arg->inst_offset = 0;
1907                                                 }
1908                                         }
1909                                         MONO_ADD_INS (cfg->cbb, arg);
1910                                 }
1911                         }
1912                         break;
1913                 default:
1914                         g_assert_not_reached ();
1915                 }
1916
1917                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1918                         /* Emit the signature cookie just before the implicit arguments */
1919                         emit_sig_cookie (cfg, call, cinfo);
1920         }
1921
1922         /* Handle the case where there are no implicit arguments */
1923         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1924                 emit_sig_cookie (cfg, call, cinfo);
1925
1926         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1927                 MonoInst *vtarg;
1928
1929                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1930                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1931                                 /*
1932                                  * Tell the JIT to use a more efficient calling convention: call using
1933                                  * OP_CALL, compute the result location after the call, and save the
1934                                  * result there.
1935                                  */
1936                                 call->vret_in_reg = TRUE;
1937                                 /*
1938                                  * Nullify the instruction computing the vret addr to enable
1939                                  * future optimizations.
1940                                  */
1941                                 if (call->vret_var)
1942                                         NULLIFY_INS (call->vret_var);
1943                         } else {
1944                                 if (call->tail_call)
1945                                         NOT_IMPLEMENTED;
1946                                 /*
1947                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1948                                  * the stack. Push the address here, so the call instruction can
1949                                  * access it.
1950                                  */
1951                                 if (!cfg->arch.vret_addr_loc) {
1952                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1953                                         /* Prevent it from being register allocated or optimized away */
1954                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1955                                 }
1956
1957                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1958                         }
1959                 }
1960                 else {
1961                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1962                         vtarg->sreg1 = call->vret_var->dreg;
1963                         vtarg->dreg = mono_alloc_preg (cfg);
1964                         MONO_ADD_INS (cfg->cbb, vtarg);
1965
1966                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1967                 }
1968         }
1969
1970 #ifdef PLATFORM_WIN32
1971         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1972                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1973         }
1974 #endif
1975
1976         if (cfg->method->save_lmf) {
1977                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1978                 MONO_ADD_INS (cfg->cbb, arg);
1979         }
1980
1981         call->stack_usage = cinfo->stack_usage;
1982 }
1983
1984 void
1985 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1986 {
1987         MonoInst *arg;
1988         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1989         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1990         int size = ins->backend.size;
1991
1992         if (ainfo->storage == ArgValuetypeInReg) {
1993                 MonoInst *load;
1994                 int part;
1995
1996                 for (part = 0; part < 2; ++part) {
1997                         if (ainfo->pair_storage [part] == ArgNone)
1998                                 continue;
1999
2000                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2001                         load->inst_basereg = src->dreg;
2002                         load->inst_offset = part * sizeof (gpointer);
2003
2004                         switch (ainfo->pair_storage [part]) {
2005                         case ArgInIReg:
2006                                 load->dreg = mono_alloc_ireg (cfg);
2007                                 break;
2008                         case ArgInDoubleSSEReg:
2009                         case ArgInFloatSSEReg:
2010                                 load->dreg = mono_alloc_freg (cfg);
2011                                 break;
2012                         default:
2013                                 g_assert_not_reached ();
2014                         }
2015                         MONO_ADD_INS (cfg->cbb, load);
2016
2017                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2018                 }
2019         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2020                 MonoInst *vtaddr, *load;
2021                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2022
2023                 g_assert (!cfg->arch.no_pushes);
2024
2025                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2026                 load->inst_p0 = vtaddr;
2027                 vtaddr->flags |= MONO_INST_INDIRECT;
2028                 load->type = STACK_MP;
2029                 load->klass = vtaddr->klass;
2030                 load->dreg = mono_alloc_ireg (cfg);
2031                 MONO_ADD_INS (cfg->cbb, load);
2032                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2033
2034                 if (ainfo->pair_storage [0] == ArgInIReg) {
2035                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2036                         arg->dreg = mono_alloc_ireg (cfg);
2037                         arg->sreg1 = load->dreg;
2038                         arg->inst_imm = 0;
2039                         MONO_ADD_INS (cfg->cbb, arg);
2040                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2041                 } else {
2042                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2043                         arg->sreg1 = load->dreg;
2044                         MONO_ADD_INS (cfg->cbb, arg);
2045                 }
2046         } else {
2047                 if (size == 8) {
2048                         if (cfg->arch.no_pushes) {
2049                                 int dreg = mono_alloc_ireg (cfg);
2050
2051                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2052                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2053                         } else {
2054                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2055                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2056                                 arg->inst_basereg = src->dreg;
2057                                 arg->inst_offset = 0;
2058                                 MONO_ADD_INS (cfg->cbb, arg);
2059                         }
2060                 } else if (size <= 40) {
2061                         if (cfg->arch.no_pushes) {
2062                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2063                         } else {
2064                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2065                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2066                         }
2067                 } else {
2068                         if (cfg->arch.no_pushes) {
2069                                 // FIXME: Code growth
2070                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2071                         } else {
2072                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2073                                 arg->inst_basereg = src->dreg;
2074                                 arg->inst_offset = 0;
2075                                 arg->inst_imm = size;
2076                                 MONO_ADD_INS (cfg->cbb, arg);
2077                         }
2078                 }
2079         }
2080 }
2081
2082 void
2083 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2084 {
2085         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2086
2087         if (!ret->byref) {
2088                 if (ret->type == MONO_TYPE_R4) {
2089                         if (COMPILE_LLVM (cfg))
2090                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2091                         else
2092                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2093                         return;
2094                 } else if (ret->type == MONO_TYPE_R8) {
2095                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2096                         return;
2097                 }
2098         }
2099
2100         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2101 }
2102
2103 #define EMIT_COND_BRANCH(ins,cond,sign) \
2104         if (ins->inst_true_bb->native_offset) { \
2105                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2106         } else { \
2107                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2108                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2109             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2110                         x86_branch8 (code, cond, 0, sign); \
2111                 else \
2112                         x86_branch32 (code, cond, 0, sign); \
2113 }
2114
2115 /* emit an exception if condition is fail */
2116 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2117         do {                                                        \
2118                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2119                 if (tins == NULL) {                                                                             \
2120                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2121                                         MONO_PATCH_INFO_EXC, exc_name);  \
2122                         x86_branch32 (code, cond, 0, signed);               \
2123                 } else {        \
2124                         EMIT_COND_BRANCH (tins, cond, signed);  \
2125                 }                       \
2126         } while (0);
2127
2128 #define EMIT_FPCOMPARE(code) do { \
2129         amd64_fcompp (code); \
2130         amd64_fnstsw (code); \
2131 } while (0);
2132
2133 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2134     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2135         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2136         amd64_ ##op (code); \
2137         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2138         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2139 } while (0);
2140
2141 static guint8*
2142 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2143 {
2144         gboolean no_patch = FALSE;
2145
2146         /*
2147          * FIXME: Add support for thunks
2148          */
2149         {
2150                 gboolean near_call = FALSE;
2151
2152                 /*
2153                  * Indirect calls are expensive so try to make a near call if possible.
2154                  * The caller memory is allocated by the code manager so it is
2155                  * guaranteed to be at a 32 bit offset.
2156                  */
2157
2158                 if (patch_type != MONO_PATCH_INFO_ABS) {
2159                         /* The target is in memory allocated using the code manager */
2160                         near_call = TRUE;
2161
2162                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2163                                 if (((MonoMethod*)data)->klass->image->aot_module)
2164                                         /* The callee might be an AOT method */
2165                                         near_call = FALSE;
2166                                 if (((MonoMethod*)data)->dynamic)
2167                                         /* The target is in malloc-ed memory */
2168                                         near_call = FALSE;
2169                         }
2170
2171                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2172                                 /*
2173                                  * The call might go directly to a native function without
2174                                  * the wrapper.
2175                                  */
2176                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2177                                 if (mi) {
2178                                         gconstpointer target = mono_icall_get_wrapper (mi);
2179                                         if ((((guint64)target) >> 32) != 0)
2180                                                 near_call = FALSE;
2181                                 }
2182                         }
2183                 }
2184                 else {
2185                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2186                                 /*
2187                                  * This is not really an optimization, but required because the
2188                                  * generic class init trampolines use R11 to pass the vtable.
2189                                  */
2190                                 near_call = TRUE;
2191                         } else {
2192                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2193                                 if (info) {
2194                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2195                                                 strstr (cfg->method->name, info->name)) {
2196                                                 /* A call to the wrapped function */
2197                                                 if ((((guint64)data) >> 32) == 0)
2198                                                         near_call = TRUE;
2199                                                 no_patch = TRUE;
2200                                         }
2201                                         else if (info->func == info->wrapper) {
2202                                                 /* No wrapper */
2203                                                 if ((((guint64)info->func) >> 32) == 0)
2204                                                         near_call = TRUE;
2205                                         }
2206                                         else {
2207                                                 /* See the comment in mono_codegen () */
2208                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2209                                                         near_call = TRUE;
2210                                         }
2211                                 }
2212                                 else if ((((guint64)data) >> 32) == 0) {
2213                                         near_call = TRUE;
2214                                         no_patch = TRUE;
2215                                 }
2216                         }
2217                 }
2218
2219                 if (cfg->method->dynamic)
2220                         /* These methods are allocated using malloc */
2221                         near_call = FALSE;
2222
2223                 if (cfg->compile_aot) {
2224                         near_call = TRUE;
2225                         no_patch = TRUE;
2226                 }
2227
2228 #ifdef MONO_ARCH_NOMAP32BIT
2229                 near_call = FALSE;
2230 #endif
2231
2232                 if (near_call) {
2233                         /*
2234                          * Align the call displacement to an address divisible by 4 so it does
2235                          * not span cache lines. This is required for code patching to work on SMP
2236                          * systems.
2237                          */
2238                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2239                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2240                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2241                         amd64_call_code (code, 0);
2242                 }
2243                 else {
2244                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2245                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2246                         amd64_call_reg (code, GP_SCRATCH_REG);
2247                 }
2248         }
2249
2250         return code;
2251 }
2252
2253 static inline guint8*
2254 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2255 {
2256 #ifdef PLATFORM_WIN32
2257         if (win64_adjust_stack)
2258                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2259 #endif
2260         code = emit_call_body (cfg, code, patch_type, data);
2261 #ifdef PLATFORM_WIN32
2262         if (win64_adjust_stack)
2263                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2264 #endif
2265
2266         return code;
2267 }
2268
2269 static inline int
2270 store_membase_imm_to_store_membase_reg (int opcode)
2271 {
2272         switch (opcode) {
2273         case OP_STORE_MEMBASE_IMM:
2274                 return OP_STORE_MEMBASE_REG;
2275         case OP_STOREI4_MEMBASE_IMM:
2276                 return OP_STOREI4_MEMBASE_REG;
2277         case OP_STOREI8_MEMBASE_IMM:
2278                 return OP_STOREI8_MEMBASE_REG;
2279         }
2280
2281         return -1;
2282 }
2283
2284 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2285
2286 /*
2287  * mono_arch_peephole_pass_1:
2288  *
2289  *   Perform peephole opts which should/can be performed before local regalloc
2290  */
2291 void
2292 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2293 {
2294         MonoInst *ins, *n;
2295
2296         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2297                 MonoInst *last_ins = ins->prev;
2298
2299                 switch (ins->opcode) {
2300                 case OP_ADD_IMM:
2301                 case OP_IADD_IMM:
2302                 case OP_LADD_IMM:
2303                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2304                                 /*
2305                                  * X86_LEA is like ADD, but doesn't have the
2306                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2307                                  * its operand to 64 bit.
2308                                  */
2309                                 ins->opcode = OP_X86_LEA_MEMBASE;
2310                                 ins->inst_basereg = ins->sreg1;
2311                         }
2312                         break;
2313                 case OP_LXOR:
2314                 case OP_IXOR:
2315                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2316                                 MonoInst *ins2;
2317
2318                                 /*
2319                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2320                                  * the latter has length 2-3 instead of 6 (reverse constant
2321                                  * propagation). These instruction sequences are very common
2322                                  * in the initlocals bblock.
2323                                  */
2324                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2325                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2326                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2327                                                 ins2->sreg1 = ins->dreg;
2328                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2329                                                 /* Continue */
2330                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2331                                                 NULLIFY_INS (ins2);
2332                                                 /* Continue */
2333                                         } else {
2334                                                 break;
2335                                         }
2336                                 }
2337                         }
2338                         break;
2339                 case OP_COMPARE_IMM:
2340                 case OP_LCOMPARE_IMM:
2341                         /* OP_COMPARE_IMM (reg, 0)
2342                          * -->
2343                          * OP_AMD64_TEST_NULL (reg)
2344                          */
2345                         if (!ins->inst_imm)
2346                                 ins->opcode = OP_AMD64_TEST_NULL;
2347                         break;
2348                 case OP_ICOMPARE_IMM:
2349                         if (!ins->inst_imm)
2350                                 ins->opcode = OP_X86_TEST_NULL;
2351                         break;
2352                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2353                         /*
2354                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2355                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2356                          * -->
2357                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2358                          * OP_COMPARE_IMM reg, imm
2359                          *
2360                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2361                          */
2362                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2363                             ins->inst_basereg == last_ins->inst_destbasereg &&
2364                             ins->inst_offset == last_ins->inst_offset) {
2365                                         ins->opcode = OP_ICOMPARE_IMM;
2366                                         ins->sreg1 = last_ins->sreg1;
2367
2368                                         /* check if we can remove cmp reg,0 with test null */
2369                                         if (!ins->inst_imm)
2370                                                 ins->opcode = OP_X86_TEST_NULL;
2371                                 }
2372
2373                         break;
2374                 }
2375
2376                 mono_peephole_ins (bb, ins);
2377         }
2378 }
2379
2380 void
2381 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2382 {
2383         MonoInst *ins, *n;
2384
2385         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2386                 switch (ins->opcode) {
2387                 case OP_ICONST:
2388                 case OP_I8CONST: {
2389                         /* reg = 0 -> XOR (reg, reg) */
2390                         /* XOR sets cflags on x86, so we cant do it always */
2391                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2392                                 ins->opcode = OP_LXOR;
2393                                 ins->sreg1 = ins->dreg;
2394                                 ins->sreg2 = ins->dreg;
2395                                 /* Fall through */
2396                         } else {
2397                                 break;
2398                         }
2399                 }
2400                 case OP_LXOR:
2401                         /*
2402                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2403                          * 0 result into 64 bits.
2404                          */
2405                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2406                                 ins->opcode = OP_IXOR;
2407                         }
2408                         /* Fall through */
2409                 case OP_IXOR:
2410                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2411                                 MonoInst *ins2;
2412
2413                                 /*
2414                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2415                                  * the latter has length 2-3 instead of 6 (reverse constant
2416                                  * propagation). These instruction sequences are very common
2417                                  * in the initlocals bblock.
2418                                  */
2419                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2420                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2421                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2422                                                 ins2->sreg1 = ins->dreg;
2423                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2424                                                 /* Continue */
2425                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2426                                                 NULLIFY_INS (ins2);
2427                                                 /* Continue */
2428                                         } else {
2429                                                 break;
2430                                         }
2431                                 }
2432                         }
2433                         break;
2434                 case OP_IADD_IMM:
2435                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2436                                 ins->opcode = OP_X86_INC_REG;
2437                         break;
2438                 case OP_ISUB_IMM:
2439                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2440                                 ins->opcode = OP_X86_DEC_REG;
2441                         break;
2442                 }
2443
2444                 mono_peephole_ins (bb, ins);
2445         }
2446 }
2447
2448 #define NEW_INS(cfg,ins,dest,op) do {   \
2449                 MONO_INST_NEW ((cfg), (dest), (op)); \
2450         (dest)->cil_code = (ins)->cil_code; \
2451         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2452         } while (0)
2453
2454 /*
2455  * mono_arch_lowering_pass:
2456  *
2457  *  Converts complex opcodes into simpler ones so that each IR instruction
2458  * corresponds to one machine instruction.
2459  */
2460 void
2461 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2462 {
2463         MonoInst *ins, *n, *temp;
2464
2465         /*
2466          * FIXME: Need to add more instructions, but the current machine
2467          * description can't model some parts of the composite instructions like
2468          * cdq.
2469          */
2470         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2471                 switch (ins->opcode) {
2472                 case OP_DIV_IMM:
2473                 case OP_REM_IMM:
2474                 case OP_IDIV_IMM:
2475                 case OP_IDIV_UN_IMM:
2476                 case OP_IREM_UN_IMM:
2477                         mono_decompose_op_imm (cfg, bb, ins);
2478                         break;
2479                 case OP_IREM_IMM:
2480                         /* Keep the opcode if we can implement it efficiently */
2481                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2482                                 mono_decompose_op_imm (cfg, bb, ins);
2483                         break;
2484                 case OP_COMPARE_IMM:
2485                 case OP_LCOMPARE_IMM:
2486                         if (!amd64_is_imm32 (ins->inst_imm)) {
2487                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2488                                 temp->inst_c0 = ins->inst_imm;
2489                                 temp->dreg = mono_alloc_ireg (cfg);
2490                                 ins->opcode = OP_COMPARE;
2491                                 ins->sreg2 = temp->dreg;
2492                         }
2493                         break;
2494                 case OP_LOAD_MEMBASE:
2495                 case OP_LOADI8_MEMBASE:
2496                         if (!amd64_is_imm32 (ins->inst_offset)) {
2497                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2498                                 temp->inst_c0 = ins->inst_offset;
2499                                 temp->dreg = mono_alloc_ireg (cfg);
2500                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2501                                 ins->inst_indexreg = temp->dreg;
2502                         }
2503                         break;
2504                 case OP_STORE_MEMBASE_IMM:
2505                 case OP_STOREI8_MEMBASE_IMM:
2506                         if (!amd64_is_imm32 (ins->inst_imm)) {
2507                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2508                                 temp->inst_c0 = ins->inst_imm;
2509                                 temp->dreg = mono_alloc_ireg (cfg);
2510                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2511                                 ins->sreg1 = temp->dreg;
2512                         }
2513                         break;
2514                 default:
2515                         break;
2516                 }
2517         }
2518
2519         bb->max_vreg = cfg->next_vreg;
2520 }
2521
2522 static const int
2523 branch_cc_table [] = {
2524         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2525         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2526         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2527 };
2528
2529 /* Maps CMP_... constants to X86_CC_... constants */
2530 static const int
2531 cc_table [] = {
2532         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2533         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2534 };
2535
2536 static const int
2537 cc_signed_table [] = {
2538         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2539         FALSE, FALSE, FALSE, FALSE
2540 };
2541
2542 /*#include "cprop.c"*/
2543
2544 static unsigned char*
2545 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2546 {
2547         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2548
2549         if (size == 1)
2550                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2551         else if (size == 2)
2552                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2553         return code;
2554 }
2555
2556 static unsigned char*
2557 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2558 {
2559         int sreg = tree->sreg1;
2560         int need_touch = FALSE;
2561
2562 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2563         if (!tree->flags & MONO_INST_INIT)
2564                 need_touch = TRUE;
2565 #endif
2566
2567         if (need_touch) {
2568                 guint8* br[5];
2569
2570                 /*
2571                  * Under Windows:
2572                  * If requested stack size is larger than one page,
2573                  * perform stack-touch operation
2574                  */
2575                 /*
2576                  * Generate stack probe code.
2577                  * Under Windows, it is necessary to allocate one page at a time,
2578                  * "touching" stack after each successful sub-allocation. This is
2579                  * because of the way stack growth is implemented - there is a
2580                  * guard page before the lowest stack page that is currently commited.
2581                  * Stack normally grows sequentially so OS traps access to the
2582                  * guard page and commits more pages when needed.
2583                  */
2584                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2585                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2586
2587                 br[2] = code; /* loop */
2588                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2589                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2590                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2591                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2592                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2593                 amd64_patch (br[3], br[2]);
2594                 amd64_test_reg_reg (code, sreg, sreg);
2595                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2596                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2597
2598                 br[1] = code; x86_jump8 (code, 0);
2599
2600                 amd64_patch (br[0], code);
2601                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2602                 amd64_patch (br[1], code);
2603                 amd64_patch (br[4], code);
2604         }
2605         else
2606                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2607
2608         if (tree->flags & MONO_INST_INIT) {
2609                 int offset = 0;
2610                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2611                         amd64_push_reg (code, AMD64_RAX);
2612                         offset += 8;
2613                 }
2614                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2615                         amd64_push_reg (code, AMD64_RCX);
2616                         offset += 8;
2617                 }
2618                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2619                         amd64_push_reg (code, AMD64_RDI);
2620                         offset += 8;
2621                 }
2622
2623                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2624                 if (sreg != AMD64_RCX)
2625                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2626                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2627
2628                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2629                 if (cfg->param_area && cfg->arch.no_pushes)
2630                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
2631                 amd64_cld (code);
2632                 amd64_prefix (code, X86_REP_PREFIX);
2633                 amd64_stosl (code);
2634
2635                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2636                         amd64_pop_reg (code, AMD64_RDI);
2637                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2638                         amd64_pop_reg (code, AMD64_RCX);
2639                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2640                         amd64_pop_reg (code, AMD64_RAX);
2641         }
2642         return code;
2643 }
2644
2645 static guint8*
2646 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2647 {
2648         CallInfo *cinfo;
2649         guint32 quad;
2650
2651         /* Move return value to the target register */
2652         /* FIXME: do this in the local reg allocator */
2653         switch (ins->opcode) {
2654         case OP_CALL:
2655         case OP_CALL_REG:
2656         case OP_CALL_MEMBASE:
2657         case OP_LCALL:
2658         case OP_LCALL_REG:
2659         case OP_LCALL_MEMBASE:
2660                 g_assert (ins->dreg == AMD64_RAX);
2661                 break;
2662         case OP_FCALL:
2663         case OP_FCALL_REG:
2664         case OP_FCALL_MEMBASE:
2665                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2666                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2667                 }
2668                 else {
2669                         if (ins->dreg != AMD64_XMM0)
2670                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2671                 }
2672                 break;
2673         case OP_VCALL:
2674         case OP_VCALL_REG:
2675         case OP_VCALL_MEMBASE:
2676         case OP_VCALL2:
2677         case OP_VCALL2_REG:
2678         case OP_VCALL2_MEMBASE:
2679                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2680                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2681                         MonoInst *loc = cfg->arch.vret_addr_loc;
2682
2683                         /* Load the destination address */
2684                         g_assert (loc->opcode == OP_REGOFFSET);
2685                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2686
2687                         for (quad = 0; quad < 2; quad ++) {
2688                                 switch (cinfo->ret.pair_storage [quad]) {
2689                                 case ArgInIReg:
2690                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2691                                         break;
2692                                 case ArgInFloatSSEReg:
2693                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2694                                         break;
2695                                 case ArgInDoubleSSEReg:
2696                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2697                                         break;
2698                                 case ArgNone:
2699                                         break;
2700                                 default:
2701                                         NOT_IMPLEMENTED;
2702                                 }
2703                         }
2704                 }
2705                 break;
2706         }
2707
2708         return code;
2709 }
2710
2711 /*
2712  * mono_amd64_emit_tls_get:
2713  * @code: buffer to store code to
2714  * @dreg: hard register where to place the result
2715  * @tls_offset: offset info
2716  *
2717  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2718  * the dreg register the item in the thread local storage identified
2719  * by tls_offset.
2720  *
2721  * Returns: a pointer to the end of the stored code
2722  */
2723 guint8*
2724 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2725 {
2726 #ifdef PLATFORM_WIN32
2727         g_assert (tls_offset < 64);
2728         x86_prefix (code, X86_GS_PREFIX);
2729         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2730 #else
2731         if (optimize_for_xen) {
2732                 x86_prefix (code, X86_FS_PREFIX);
2733                 amd64_mov_reg_mem (code, dreg, 0, 8);
2734                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2735         } else {
2736                 x86_prefix (code, X86_FS_PREFIX);
2737                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2738         }
2739 #endif
2740         return code;
2741 }
2742
2743 #define REAL_PRINT_REG(text,reg) \
2744 mono_assert (reg >= 0); \
2745 amd64_push_reg (code, AMD64_RAX); \
2746 amd64_push_reg (code, AMD64_RDX); \
2747 amd64_push_reg (code, AMD64_RCX); \
2748 amd64_push_reg (code, reg); \
2749 amd64_push_imm (code, reg); \
2750 amd64_push_imm (code, text " %d %p\n"); \
2751 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2752 amd64_call_reg (code, AMD64_RAX); \
2753 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2754 amd64_pop_reg (code, AMD64_RCX); \
2755 amd64_pop_reg (code, AMD64_RDX); \
2756 amd64_pop_reg (code, AMD64_RAX);
2757
2758 /* benchmark and set based on cpu */
2759 #define LOOP_ALIGNMENT 8
2760 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2761
2762 #ifndef DISABLE_JIT
2763
2764 void
2765 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2766 {
2767         MonoInst *ins;
2768         MonoCallInst *call;
2769         guint offset;
2770         guint8 *code = cfg->native_code + cfg->code_len;
2771         MonoInst *last_ins = NULL;
2772         guint last_offset = 0;
2773         int max_len;
2774
2775         /* Fix max_offset estimate for each successor bb */
2776         if (cfg->opt & MONO_OPT_BRANCH) {
2777                 int current_offset = cfg->code_len;
2778                 MonoBasicBlock *current_bb;
2779                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
2780                         current_bb->max_offset = current_offset;
2781                         current_offset += current_bb->max_length;
2782                 }
2783         }
2784
2785         if (cfg->opt & MONO_OPT_LOOP) {
2786                 int pad, align = LOOP_ALIGNMENT;
2787                 /* set alignment depending on cpu */
2788                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2789                         pad = align - pad;
2790                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2791                         amd64_padding (code, pad);
2792                         cfg->code_len += pad;
2793                         bb->native_offset = cfg->code_len;
2794                 }
2795         }
2796
2797         if (cfg->verbose_level > 2)
2798                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2799
2800         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2801                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2802                 g_assert (!cfg->compile_aot);
2803
2804                 cov->data [bb->dfn].cil_code = bb->cil_code;
2805                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2806                 /* this is not thread save, but good enough */
2807                 amd64_inc_membase (code, AMD64_R11, 0);
2808         }
2809
2810         offset = code - cfg->native_code;
2811
2812         mono_debug_open_block (cfg, bb, offset);
2813
2814     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2815                 x86_breakpoint (code);
2816
2817         MONO_BB_FOR_EACH_INS (bb, ins) {
2818                 offset = code - cfg->native_code;
2819
2820                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2821
2822                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2823                         cfg->code_size *= 2;
2824                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2825                         code = cfg->native_code + offset;
2826                         mono_jit_stats.code_reallocs++;
2827                 }
2828
2829                 if (cfg->debug_info)
2830                         mono_debug_record_line_number (cfg, ins, offset);
2831
2832                 switch (ins->opcode) {
2833                 case OP_BIGMUL:
2834                         amd64_mul_reg (code, ins->sreg2, TRUE);
2835                         break;
2836                 case OP_BIGMUL_UN:
2837                         amd64_mul_reg (code, ins->sreg2, FALSE);
2838                         break;
2839                 case OP_X86_SETEQ_MEMBASE:
2840                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2841                         break;
2842                 case OP_STOREI1_MEMBASE_IMM:
2843                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2844                         break;
2845                 case OP_STOREI2_MEMBASE_IMM:
2846                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2847                         break;
2848                 case OP_STOREI4_MEMBASE_IMM:
2849                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2850                         break;
2851                 case OP_STOREI1_MEMBASE_REG:
2852                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2853                         break;
2854                 case OP_STOREI2_MEMBASE_REG:
2855                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2856                         break;
2857                 case OP_STORE_MEMBASE_REG:
2858                 case OP_STOREI8_MEMBASE_REG:
2859                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2860                         break;
2861                 case OP_STOREI4_MEMBASE_REG:
2862                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2863                         break;
2864                 case OP_STORE_MEMBASE_IMM:
2865                 case OP_STOREI8_MEMBASE_IMM:
2866                         g_assert (amd64_is_imm32 (ins->inst_imm));
2867                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2868                         break;
2869                 case OP_LOAD_MEM:
2870                 case OP_LOADI8_MEM:
2871                         // FIXME: Decompose this earlier
2872                         if (amd64_is_imm32 (ins->inst_imm))
2873                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2874                         else {
2875                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2876                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2877                         }
2878                         break;
2879                 case OP_LOADI4_MEM:
2880                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2881                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2882                         break;
2883                 case OP_LOADU4_MEM:
2884                         // FIXME: Decompose this earlier
2885                         if (amd64_is_imm32 (ins->inst_imm))
2886                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2887                         else {
2888                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2889                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2890                         }
2891                         break;
2892                 case OP_LOADU1_MEM:
2893                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2894                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2895                         break;
2896                 case OP_LOADU2_MEM:
2897                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2898                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2899                         break;
2900                 case OP_LOAD_MEMBASE:
2901                 case OP_LOADI8_MEMBASE:
2902                         g_assert (amd64_is_imm32 (ins->inst_offset));
2903                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2904                         break;
2905                 case OP_LOADI4_MEMBASE:
2906                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2907                         break;
2908                 case OP_LOADU4_MEMBASE:
2909                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2910                         break;
2911                 case OP_LOADU1_MEMBASE:
2912                         /* The cpu zero extends the result into 64 bits */
2913                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2914                         break;
2915                 case OP_LOADI1_MEMBASE:
2916                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2917                         break;
2918                 case OP_LOADU2_MEMBASE:
2919                         /* The cpu zero extends the result into 64 bits */
2920                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2921                         break;
2922                 case OP_LOADI2_MEMBASE:
2923                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2924                         break;
2925                 case OP_AMD64_LOADI8_MEMINDEX:
2926                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2927                         break;
2928                 case OP_LCONV_TO_I1:
2929                 case OP_ICONV_TO_I1:
2930                 case OP_SEXT_I1:
2931                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2932                         break;
2933                 case OP_LCONV_TO_I2:
2934                 case OP_ICONV_TO_I2:
2935                 case OP_SEXT_I2:
2936                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2937                         break;
2938                 case OP_LCONV_TO_U1:
2939                 case OP_ICONV_TO_U1:
2940                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2941                         break;
2942                 case OP_LCONV_TO_U2:
2943                 case OP_ICONV_TO_U2:
2944                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2945                         break;
2946                 case OP_ZEXT_I4:
2947                         /* Clean out the upper word */
2948                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2949                         break;
2950                 case OP_SEXT_I4:
2951                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2952                         break;
2953                 case OP_COMPARE:
2954                 case OP_LCOMPARE:
2955                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2956                         break;
2957                 case OP_COMPARE_IMM:
2958                 case OP_LCOMPARE_IMM:
2959                         g_assert (amd64_is_imm32 (ins->inst_imm));
2960                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2961                         break;
2962                 case OP_X86_COMPARE_REG_MEMBASE:
2963                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2964                         break;
2965                 case OP_X86_TEST_NULL:
2966                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2967                         break;
2968                 case OP_AMD64_TEST_NULL:
2969                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2970                         break;
2971
2972                 case OP_X86_ADD_REG_MEMBASE:
2973                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2974                         break;
2975                 case OP_X86_SUB_REG_MEMBASE:
2976                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2977                         break;
2978                 case OP_X86_AND_REG_MEMBASE:
2979                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2980                         break;
2981                 case OP_X86_OR_REG_MEMBASE:
2982                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2983                         break;
2984                 case OP_X86_XOR_REG_MEMBASE:
2985                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2986                         break;
2987
2988                 case OP_X86_ADD_MEMBASE_IMM:
2989                         /* FIXME: Make a 64 version too */
2990                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2991                         break;
2992                 case OP_X86_SUB_MEMBASE_IMM:
2993                         g_assert (amd64_is_imm32 (ins->inst_imm));
2994                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2995                         break;
2996                 case OP_X86_AND_MEMBASE_IMM:
2997                         g_assert (amd64_is_imm32 (ins->inst_imm));
2998                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2999                         break;
3000                 case OP_X86_OR_MEMBASE_IMM:
3001                         g_assert (amd64_is_imm32 (ins->inst_imm));
3002                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3003                         break;
3004                 case OP_X86_XOR_MEMBASE_IMM:
3005                         g_assert (amd64_is_imm32 (ins->inst_imm));
3006                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3007                         break;
3008                 case OP_X86_ADD_MEMBASE_REG:
3009                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3010                         break;
3011                 case OP_X86_SUB_MEMBASE_REG:
3012                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3013                         break;
3014                 case OP_X86_AND_MEMBASE_REG:
3015                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3016                         break;
3017                 case OP_X86_OR_MEMBASE_REG:
3018                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3019                         break;
3020                 case OP_X86_XOR_MEMBASE_REG:
3021                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3022                         break;
3023                 case OP_X86_INC_MEMBASE:
3024                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3025                         break;
3026                 case OP_X86_INC_REG:
3027                         amd64_inc_reg_size (code, ins->dreg, 4);
3028                         break;
3029                 case OP_X86_DEC_MEMBASE:
3030                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3031                         break;
3032                 case OP_X86_DEC_REG:
3033                         amd64_dec_reg_size (code, ins->dreg, 4);
3034                         break;
3035                 case OP_X86_MUL_REG_MEMBASE:
3036                 case OP_X86_MUL_MEMBASE_REG:
3037                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3038                         break;
3039                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3040                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3041                         break;
3042                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3043                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3044                         break;
3045                 case OP_AMD64_COMPARE_MEMBASE_REG:
3046                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3047                         break;
3048                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3049                         g_assert (amd64_is_imm32 (ins->inst_imm));
3050                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3051                         break;
3052                 case OP_X86_COMPARE_MEMBASE8_IMM:
3053                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3054                         break;
3055                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3056                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3057                         break;
3058                 case OP_AMD64_COMPARE_REG_MEMBASE:
3059                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3060                         break;
3061
3062                 case OP_AMD64_ADD_REG_MEMBASE:
3063                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3064                         break;
3065                 case OP_AMD64_SUB_REG_MEMBASE:
3066                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3067                         break;
3068                 case OP_AMD64_AND_REG_MEMBASE:
3069                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3070                         break;
3071                 case OP_AMD64_OR_REG_MEMBASE:
3072                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3073                         break;
3074                 case OP_AMD64_XOR_REG_MEMBASE:
3075                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3076                         break;
3077
3078                 case OP_AMD64_ADD_MEMBASE_REG:
3079                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3080                         break;
3081                 case OP_AMD64_SUB_MEMBASE_REG:
3082                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3083                         break;
3084                 case OP_AMD64_AND_MEMBASE_REG:
3085                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3086                         break;
3087                 case OP_AMD64_OR_MEMBASE_REG:
3088                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3089                         break;
3090                 case OP_AMD64_XOR_MEMBASE_REG:
3091                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3092                         break;
3093
3094                 case OP_AMD64_ADD_MEMBASE_IMM:
3095                         g_assert (amd64_is_imm32 (ins->inst_imm));
3096                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3097                         break;
3098                 case OP_AMD64_SUB_MEMBASE_IMM:
3099                         g_assert (amd64_is_imm32 (ins->inst_imm));
3100                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3101                         break;
3102                 case OP_AMD64_AND_MEMBASE_IMM:
3103                         g_assert (amd64_is_imm32 (ins->inst_imm));
3104                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3105                         break;
3106                 case OP_AMD64_OR_MEMBASE_IMM:
3107                         g_assert (amd64_is_imm32 (ins->inst_imm));
3108                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3109                         break;
3110                 case OP_AMD64_XOR_MEMBASE_IMM:
3111                         g_assert (amd64_is_imm32 (ins->inst_imm));
3112                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3113                         break;
3114
3115                 case OP_BREAK:
3116                         amd64_breakpoint (code);
3117                         break;
3118                 case OP_RELAXED_NOP:
3119                         x86_prefix (code, X86_REP_PREFIX);
3120                         x86_nop (code);
3121                         break;
3122                 case OP_HARD_NOP:
3123                         x86_nop (code);
3124                         break;
3125                 case OP_NOP:
3126                 case OP_DUMMY_USE:
3127                 case OP_DUMMY_STORE:
3128                 case OP_NOT_REACHED:
3129                 case OP_NOT_NULL:
3130                         break;
3131                 case OP_ADDCC:
3132                 case OP_LADD:
3133                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3134                         break;
3135                 case OP_ADC:
3136                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3137                         break;
3138                 case OP_ADD_IMM:
3139                 case OP_LADD_IMM:
3140                         g_assert (amd64_is_imm32 (ins->inst_imm));
3141                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3142                         break;
3143                 case OP_ADC_IMM:
3144                         g_assert (amd64_is_imm32 (ins->inst_imm));
3145                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3146                         break;
3147                 case OP_SUBCC:
3148                 case OP_LSUB:
3149                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3150                         break;
3151                 case OP_SBB:
3152                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3153                         break;
3154                 case OP_SUB_IMM:
3155                 case OP_LSUB_IMM:
3156                         g_assert (amd64_is_imm32 (ins->inst_imm));
3157                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3158                         break;
3159                 case OP_SBB_IMM:
3160                         g_assert (amd64_is_imm32 (ins->inst_imm));
3161                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3162                         break;
3163                 case OP_LAND:
3164                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3165                         break;
3166                 case OP_AND_IMM:
3167                 case OP_LAND_IMM:
3168                         g_assert (amd64_is_imm32 (ins->inst_imm));
3169                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3170                         break;
3171                 case OP_LMUL:
3172                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3173                         break;
3174                 case OP_MUL_IMM:
3175                 case OP_LMUL_IMM:
3176                 case OP_IMUL_IMM: {
3177                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3178
3179                         switch (ins->inst_imm) {
3180                         case 2:
3181                                 /* MOV r1, r2 */
3182                                 /* ADD r1, r1 */
3183                                 if (ins->dreg != ins->sreg1)
3184                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3185                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3186                                 break;
3187                         case 3:
3188                                 /* LEA r1, [r2 + r2*2] */
3189                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3190                                 break;
3191                         case 5:
3192                                 /* LEA r1, [r2 + r2*4] */
3193                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3194                                 break;
3195                         case 6:
3196                                 /* LEA r1, [r2 + r2*2] */
3197                                 /* ADD r1, r1          */
3198                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3199                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3200                                 break;
3201                         case 9:
3202                                 /* LEA r1, [r2 + r2*8] */
3203                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3204                                 break;
3205                         case 10:
3206                                 /* LEA r1, [r2 + r2*4] */
3207                                 /* ADD r1, r1          */
3208                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3209                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3210                                 break;
3211                         case 12:
3212                                 /* LEA r1, [r2 + r2*2] */
3213                                 /* SHL r1, 2           */
3214                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3215                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3216                                 break;
3217                         case 25:
3218                                 /* LEA r1, [r2 + r2*4] */
3219                                 /* LEA r1, [r1 + r1*4] */
3220                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3221                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3222                                 break;
3223                         case 100:
3224                                 /* LEA r1, [r2 + r2*4] */
3225                                 /* SHL r1, 2           */
3226                                 /* LEA r1, [r1 + r1*4] */
3227                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3228                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3229                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3230                                 break;
3231                         default:
3232                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3233                                 break;
3234                         }
3235                         break;
3236                 }
3237                 case OP_LDIV:
3238                 case OP_LREM:
3239                         /* Regalloc magic makes the div/rem cases the same */
3240                         if (ins->sreg2 == AMD64_RDX) {
3241                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3242                                 amd64_cdq (code);
3243                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3244                         } else {
3245                                 amd64_cdq (code);
3246                                 amd64_div_reg (code, ins->sreg2, TRUE);
3247                         }
3248                         break;
3249                 case OP_LDIV_UN:
3250                 case OP_LREM_UN:
3251                         if (ins->sreg2 == AMD64_RDX) {
3252                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3253                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3254                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3255                         } else {
3256                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3257                                 amd64_div_reg (code, ins->sreg2, FALSE);
3258                         }
3259                         break;
3260                 case OP_IDIV:
3261                 case OP_IREM:
3262                         if (ins->sreg2 == AMD64_RDX) {
3263                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3264                                 amd64_cdq_size (code, 4);
3265                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3266                         } else {
3267                                 amd64_cdq_size (code, 4);
3268                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3269                         }
3270                         break;
3271                 case OP_IDIV_UN:
3272                 case OP_IREM_UN:
3273                         if (ins->sreg2 == AMD64_RDX) {
3274                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3275                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3276                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3277                         } else {
3278                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3279                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3280                         }
3281                         break;
3282                 case OP_IREM_IMM: {
3283                         int power = mono_is_power_of_two (ins->inst_imm);
3284
3285                         g_assert (ins->sreg1 == X86_EAX);
3286                         g_assert (ins->dreg == X86_EAX);
3287                         g_assert (power >= 0);
3288
3289                         if (power == 0) {
3290                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3291                                 break;
3292                         }
3293
3294                         /* Based on gcc code */
3295
3296                         /* Add compensation for negative dividents */
3297                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3298                         if (power > 1)
3299                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3300                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3301                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3302                         /* Compute remainder */
3303                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3304                         /* Remove compensation */
3305                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3306                         break;
3307                 }
3308                 case OP_LMUL_OVF:
3309                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3310                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3311                         break;
3312                 case OP_LOR:
3313                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3314                         break;
3315                 case OP_OR_IMM:
3316                 case OP_LOR_IMM:
3317                         g_assert (amd64_is_imm32 (ins->inst_imm));
3318                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3319                         break;
3320                 case OP_LXOR:
3321                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3322                         break;
3323                 case OP_XOR_IMM:
3324                 case OP_LXOR_IMM:
3325                         g_assert (amd64_is_imm32 (ins->inst_imm));
3326                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3327                         break;
3328                 case OP_LSHL:
3329                         g_assert (ins->sreg2 == AMD64_RCX);
3330                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3331                         break;
3332                 case OP_LSHR:
3333                         g_assert (ins->sreg2 == AMD64_RCX);
3334                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3335                         break;
3336                 case OP_SHR_IMM:
3337                         g_assert (amd64_is_imm32 (ins->inst_imm));
3338                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3339                         break;
3340                 case OP_LSHR_IMM:
3341                         g_assert (amd64_is_imm32 (ins->inst_imm));
3342                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3343                         break;
3344                 case OP_SHR_UN_IMM:
3345                         g_assert (amd64_is_imm32 (ins->inst_imm));
3346                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3347                         break;
3348                 case OP_LSHR_UN_IMM:
3349                         g_assert (amd64_is_imm32 (ins->inst_imm));
3350                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3351                         break;
3352                 case OP_LSHR_UN:
3353                         g_assert (ins->sreg2 == AMD64_RCX);
3354                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3355                         break;
3356                 case OP_SHL_IMM:
3357                         g_assert (amd64_is_imm32 (ins->inst_imm));
3358                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3359                         break;
3360                 case OP_LSHL_IMM:
3361                         g_assert (amd64_is_imm32 (ins->inst_imm));
3362                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3363                         break;
3364
3365                 case OP_IADDCC:
3366                 case OP_IADD:
3367                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3368                         break;
3369                 case OP_IADC:
3370                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3371                         break;
3372                 case OP_IADD_IMM:
3373                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3374                         break;
3375                 case OP_IADC_IMM:
3376                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3377                         break;
3378                 case OP_ISUBCC:
3379                 case OP_ISUB:
3380                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3381                         break;
3382                 case OP_ISBB:
3383                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3384                         break;
3385                 case OP_ISUB_IMM:
3386                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3387                         break;
3388                 case OP_ISBB_IMM:
3389                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3390                         break;
3391                 case OP_IAND:
3392                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3393                         break;
3394                 case OP_IAND_IMM:
3395                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3396                         break;
3397                 case OP_IOR:
3398                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3399                         break;
3400                 case OP_IOR_IMM:
3401                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3402                         break;
3403                 case OP_IXOR:
3404                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3405                         break;
3406                 case OP_IXOR_IMM:
3407                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3408                         break;
3409                 case OP_INEG:
3410                         amd64_neg_reg_size (code, ins->sreg1, 4);
3411                         break;
3412                 case OP_INOT:
3413                         amd64_not_reg_size (code, ins->sreg1, 4);
3414                         break;
3415                 case OP_ISHL:
3416                         g_assert (ins->sreg2 == AMD64_RCX);
3417                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3418                         break;
3419                 case OP_ISHR:
3420                         g_assert (ins->sreg2 == AMD64_RCX);
3421                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3422                         break;
3423                 case OP_ISHR_IMM:
3424                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3425                         break;
3426                 case OP_ISHR_UN_IMM:
3427                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3428                         break;
3429                 case OP_ISHR_UN:
3430                         g_assert (ins->sreg2 == AMD64_RCX);
3431                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3432                         break;
3433                 case OP_ISHL_IMM:
3434                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3435                         break;
3436                 case OP_IMUL:
3437                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3438                         break;
3439                 case OP_IMUL_OVF:
3440                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3441                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3442                         break;
3443                 case OP_IMUL_OVF_UN:
3444                 case OP_LMUL_OVF_UN: {
3445                         /* the mul operation and the exception check should most likely be split */
3446                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3447                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3448                         /*g_assert (ins->sreg2 == X86_EAX);
3449                         g_assert (ins->dreg == X86_EAX);*/
3450                         if (ins->sreg2 == X86_EAX) {
3451                                 non_eax_reg = ins->sreg1;
3452                         } else if (ins->sreg1 == X86_EAX) {
3453                                 non_eax_reg = ins->sreg2;
3454                         } else {
3455                                 /* no need to save since we're going to store to it anyway */
3456                                 if (ins->dreg != X86_EAX) {
3457                                         saved_eax = TRUE;
3458                                         amd64_push_reg (code, X86_EAX);
3459                                 }
3460                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3461                                 non_eax_reg = ins->sreg2;
3462                         }
3463                         if (ins->dreg == X86_EDX) {
3464                                 if (!saved_eax) {
3465                                         saved_eax = TRUE;
3466                                         amd64_push_reg (code, X86_EAX);
3467                                 }
3468                         } else {
3469                                 saved_edx = TRUE;
3470                                 amd64_push_reg (code, X86_EDX);
3471                         }
3472                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3473                         /* save before the check since pop and mov don't change the flags */
3474                         if (ins->dreg != X86_EAX)
3475                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3476                         if (saved_edx)
3477                                 amd64_pop_reg (code, X86_EDX);
3478                         if (saved_eax)
3479                                 amd64_pop_reg (code, X86_EAX);
3480                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3481                         break;
3482                 }
3483                 case OP_ICOMPARE:
3484                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3485                         break;
3486                 case OP_ICOMPARE_IMM:
3487                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3488                         break;
3489                 case OP_IBEQ:
3490                 case OP_IBLT:
3491                 case OP_IBGT:
3492                 case OP_IBGE:
3493                 case OP_IBLE:
3494                 case OP_LBEQ:
3495                 case OP_LBLT:
3496                 case OP_LBGT:
3497                 case OP_LBGE:
3498                 case OP_LBLE:
3499                 case OP_IBNE_UN:
3500                 case OP_IBLT_UN:
3501                 case OP_IBGT_UN:
3502                 case OP_IBGE_UN:
3503                 case OP_IBLE_UN:
3504                 case OP_LBNE_UN:
3505                 case OP_LBLT_UN:
3506                 case OP_LBGT_UN:
3507                 case OP_LBGE_UN:
3508                 case OP_LBLE_UN:
3509                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3510                         break;
3511
3512                 case OP_CMOV_IEQ:
3513                 case OP_CMOV_IGE:
3514                 case OP_CMOV_IGT:
3515                 case OP_CMOV_ILE:
3516                 case OP_CMOV_ILT:
3517                 case OP_CMOV_INE_UN:
3518                 case OP_CMOV_IGE_UN:
3519                 case OP_CMOV_IGT_UN:
3520                 case OP_CMOV_ILE_UN:
3521                 case OP_CMOV_ILT_UN:
3522                 case OP_CMOV_LEQ:
3523                 case OP_CMOV_LGE:
3524                 case OP_CMOV_LGT:
3525                 case OP_CMOV_LLE:
3526                 case OP_CMOV_LLT:
3527                 case OP_CMOV_LNE_UN:
3528                 case OP_CMOV_LGE_UN:
3529                 case OP_CMOV_LGT_UN:
3530                 case OP_CMOV_LLE_UN:
3531                 case OP_CMOV_LLT_UN:
3532                         g_assert (ins->dreg == ins->sreg1);
3533                         /* This needs to operate on 64 bit values */
3534                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3535                         break;
3536
3537                 case OP_LNOT:
3538                         amd64_not_reg (code, ins->sreg1);
3539                         break;
3540                 case OP_LNEG:
3541                         amd64_neg_reg (code, ins->sreg1);
3542                         break;
3543
3544                 case OP_ICONST:
3545                 case OP_I8CONST:
3546                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3547                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3548                         else
3549                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3550                         break;
3551                 case OP_AOTCONST:
3552                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3553                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3554                         break;
3555                 case OP_JUMP_TABLE:
3556                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3557                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3558                         break;
3559                 case OP_MOVE:
3560                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3561                         break;
3562                 case OP_AMD64_SET_XMMREG_R4: {
3563                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3564                         break;
3565                 }
3566                 case OP_AMD64_SET_XMMREG_R8: {
3567                         if (ins->dreg != ins->sreg1)
3568                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3569                         break;
3570                 }
3571                 case OP_TAILCALL: {
3572                         /*
3573                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3574                          * Keep in sync with the code in emit_epilog.
3575                          */
3576                         int pos = 0, i;
3577
3578                         /* FIXME: no tracing support... */
3579                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3580                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3581
3582                         g_assert (!cfg->method->save_lmf);
3583
3584                         if (cfg->arch.omit_fp) {
3585                                 guint32 save_offset = 0;
3586                                 /* Pop callee-saved registers */
3587                                 for (i = 0; i < AMD64_NREG; ++i)
3588                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3589                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3590                                                 save_offset += 8;
3591                                         }
3592                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3593                         }
3594                         else {
3595                                 for (i = 0; i < AMD64_NREG; ++i)
3596                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3597                                                 pos -= sizeof (gpointer);
3598
3599                                 if (pos)
3600                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3601
3602                                 /* Pop registers in reverse order */
3603                                 for (i = AMD64_NREG - 1; i > 0; --i)
3604                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3605                                                 amd64_pop_reg (code, i);
3606                                         }
3607
3608                                 amd64_leave (code);
3609                         }
3610
3611                         offset = code - cfg->native_code;
3612                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3613                         if (cfg->compile_aot)
3614                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3615                         else
3616                                 amd64_set_reg_template (code, AMD64_R11);
3617                         amd64_jump_reg (code, AMD64_R11);
3618                         break;
3619                 }
3620                 case OP_CHECK_THIS:
3621                         /* ensure ins->sreg1 is not NULL */
3622                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3623                         break;
3624                 case OP_ARGLIST: {
3625                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3626                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3627                         break;
3628                 }
3629                 case OP_CALL:
3630                 case OP_FCALL:
3631                 case OP_LCALL:
3632                 case OP_VCALL:
3633                 case OP_VCALL2:
3634                 case OP_VOIDCALL:
3635                         call = (MonoCallInst*)ins;
3636                         /*
3637                          * The AMD64 ABI forces callers to know about varargs.
3638                          */
3639                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3640                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3641                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3642                                 /*
3643                                  * Since the unmanaged calling convention doesn't contain a
3644                                  * 'vararg' entry, we have to treat every pinvoke call as a
3645                                  * potential vararg call.
3646                                  */
3647                                 guint32 nregs, i;
3648                                 nregs = 0;
3649                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3650                                         if (call->used_fregs & (1 << i))
3651                                                 nregs ++;
3652                                 if (!nregs)
3653                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3654                                 else
3655                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3656                         }
3657
3658                         if (ins->flags & MONO_INST_HAS_METHOD)
3659                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3660                         else
3661                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3662                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3663                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3664                         code = emit_move_return_value (cfg, ins, code);
3665                         break;
3666                 case OP_FCALL_REG:
3667                 case OP_LCALL_REG:
3668                 case OP_VCALL_REG:
3669                 case OP_VCALL2_REG:
3670                 case OP_VOIDCALL_REG:
3671                 case OP_CALL_REG:
3672                         call = (MonoCallInst*)ins;
3673
3674                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3675                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3676                                 ins->sreg1 = AMD64_R11;
3677                         }
3678
3679                         /*
3680                          * The AMD64 ABI forces callers to know about varargs.
3681                          */
3682                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3683                                 if (ins->sreg1 == AMD64_RAX) {
3684                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3685                                         ins->sreg1 = AMD64_R11;
3686                                 }
3687                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3688                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3689                                 /*
3690                                  * Since the unmanaged calling convention doesn't contain a
3691                                  * 'vararg' entry, we have to treat every pinvoke call as a
3692                                  * potential vararg call.
3693                                  */
3694                                 guint32 nregs, i;
3695                                 nregs = 0;
3696                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3697                                         if (call->used_fregs & (1 << i))
3698                                                 nregs ++;
3699                                 if (ins->sreg1 == AMD64_RAX) {
3700                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3701                                         ins->sreg1 = AMD64_R11;
3702                                 }
3703                                 if (!nregs)
3704                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3705                                 else
3706                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3707                         }
3708
3709                         amd64_call_reg (code, ins->sreg1);
3710                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3711                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3712                         code = emit_move_return_value (cfg, ins, code);
3713                         break;
3714                 case OP_FCALL_MEMBASE:
3715                 case OP_LCALL_MEMBASE:
3716                 case OP_VCALL_MEMBASE:
3717                 case OP_VCALL2_MEMBASE:
3718                 case OP_VOIDCALL_MEMBASE:
3719                 case OP_CALL_MEMBASE:
3720                         call = (MonoCallInst*)ins;
3721
3722                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3723                                 /*
3724                                  * Can't use R11 because it is clobbered by the trampoline
3725                                  * code, and the reg value is needed by get_vcall_slot_addr.
3726                                  */
3727                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3728                                 ins->sreg1 = AMD64_RAX;
3729                         }
3730
3731                         /*
3732                          * Emit a few nops to simplify get_vcall_slot ().
3733                          */
3734                         amd64_nop (code);
3735                         amd64_nop (code);
3736                         amd64_nop (code);
3737
3738                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3739                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3740                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3741                         code = emit_move_return_value (cfg, ins, code);
3742                         break;
3743                 case OP_AMD64_SAVE_SP_TO_LMF:
3744                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3745                         break;
3746                 case OP_X86_PUSH:
3747                         g_assert (!cfg->arch.no_pushes);
3748                         amd64_push_reg (code, ins->sreg1);
3749                         break;
3750                 case OP_X86_PUSH_IMM:
3751                         g_assert (!cfg->arch.no_pushes);
3752                         g_assert (amd64_is_imm32 (ins->inst_imm));
3753                         amd64_push_imm (code, ins->inst_imm);
3754                         break;
3755                 case OP_X86_PUSH_MEMBASE:
3756                         g_assert (!cfg->arch.no_pushes);
3757                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3758                         break;
3759                 case OP_X86_PUSH_OBJ: {
3760                         int size = ALIGN_TO (ins->inst_imm, 8);
3761
3762                         g_assert (!cfg->arch.no_pushes);
3763
3764                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3765                         amd64_push_reg (code, AMD64_RDI);
3766                         amd64_push_reg (code, AMD64_RSI);
3767                         amd64_push_reg (code, AMD64_RCX);
3768                         if (ins->inst_offset)
3769                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3770                         else
3771                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3772                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3773                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3774                         amd64_cld (code);
3775                         amd64_prefix (code, X86_REP_PREFIX);
3776                         amd64_movsd (code);
3777                         amd64_pop_reg (code, AMD64_RCX);
3778                         amd64_pop_reg (code, AMD64_RSI);
3779                         amd64_pop_reg (code, AMD64_RDI);
3780                         break;
3781                 }
3782                 case OP_X86_LEA:
3783                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3784                         break;
3785                 case OP_X86_LEA_MEMBASE:
3786                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3787                         break;
3788                 case OP_X86_XCHG:
3789                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3790                         break;
3791                 case OP_LOCALLOC:
3792                         /* keep alignment */
3793                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3794                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3795                         code = mono_emit_stack_alloc (cfg, code, ins);
3796                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3797                         if (cfg->param_area && cfg->arch.no_pushes)
3798                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3799                         break;
3800                 case OP_LOCALLOC_IMM: {
3801                         guint32 size = ins->inst_imm;
3802                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3803
3804                         if (ins->flags & MONO_INST_INIT) {
3805                                 if (size < 64) {
3806                                         int i;
3807
3808                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3809                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3810
3811                                         for (i = 0; i < size; i += 8)
3812                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3813                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3814                                 } else {
3815                                         amd64_mov_reg_imm (code, ins->dreg, size);
3816                                         ins->sreg1 = ins->dreg;
3817
3818                                         code = mono_emit_stack_alloc (cfg, code, ins);
3819                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3820                                 }
3821                         } else {
3822                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3823                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3824                         }
3825                         if (cfg->param_area && cfg->arch.no_pushes)
3826                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3827                         break;
3828                 }
3829                 case OP_THROW: {
3830                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3831                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3832                                              (gpointer)"mono_arch_throw_exception", FALSE);
3833                         break;
3834                 }
3835                 case OP_RETHROW: {
3836                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3837                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3838                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3839                         break;
3840                 }
3841                 case OP_CALL_HANDLER:
3842                         /* Align stack */
3843                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3844                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3845                         amd64_call_imm (code, 0);
3846                         /* Restore stack alignment */
3847                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3848                         break;
3849                 case OP_START_HANDLER: {
3850                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3851                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3852
3853                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
3854                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
3855                                 cfg->param_area && cfg->arch.no_pushes) {
3856                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3857                         }
3858                         break;
3859                 }
3860                 case OP_ENDFINALLY: {
3861                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3862                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3863                         amd64_ret (code);
3864                         break;
3865                 }
3866                 case OP_ENDFILTER: {
3867                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3868                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3869                         /* The local allocator will put the result into RAX */
3870                         amd64_ret (code);
3871                         break;
3872                 }
3873
3874                 case OP_LABEL:
3875                         ins->inst_c0 = code - cfg->native_code;
3876                         break;
3877                 case OP_BR:
3878                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3879                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3880                         //break;
3881                                 if (ins->inst_target_bb->native_offset) {
3882                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3883                                 } else {
3884                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3885                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3886                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
3887                                                 x86_jump8 (code, 0);
3888                                         else
3889                                                 x86_jump32 (code, 0);
3890                         }
3891                         break;
3892                 case OP_BR_REG:
3893                         amd64_jump_reg (code, ins->sreg1);
3894                         break;
3895                 case OP_CEQ:
3896                 case OP_LCEQ:
3897                 case OP_ICEQ:
3898                 case OP_CLT:
3899                 case OP_LCLT:
3900                 case OP_ICLT:
3901                 case OP_CGT:
3902                 case OP_ICGT:
3903                 case OP_LCGT:
3904                 case OP_CLT_UN:
3905                 case OP_LCLT_UN:
3906                 case OP_ICLT_UN:
3907                 case OP_CGT_UN:
3908                 case OP_LCGT_UN:
3909                 case OP_ICGT_UN:
3910                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3911                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3912                         break;
3913                 case OP_COND_EXC_EQ:
3914                 case OP_COND_EXC_NE_UN:
3915                 case OP_COND_EXC_LT:
3916                 case OP_COND_EXC_LT_UN:
3917                 case OP_COND_EXC_GT:
3918                 case OP_COND_EXC_GT_UN:
3919                 case OP_COND_EXC_GE:
3920                 case OP_COND_EXC_GE_UN:
3921                 case OP_COND_EXC_LE:
3922                 case OP_COND_EXC_LE_UN:
3923                 case OP_COND_EXC_IEQ:
3924                 case OP_COND_EXC_INE_UN:
3925                 case OP_COND_EXC_ILT:
3926                 case OP_COND_EXC_ILT_UN:
3927                 case OP_COND_EXC_IGT:
3928                 case OP_COND_EXC_IGT_UN:
3929                 case OP_COND_EXC_IGE:
3930                 case OP_COND_EXC_IGE_UN:
3931                 case OP_COND_EXC_ILE:
3932                 case OP_COND_EXC_ILE_UN:
3933                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3934                         break;
3935                 case OP_COND_EXC_OV:
3936                 case OP_COND_EXC_NO:
3937                 case OP_COND_EXC_C:
3938                 case OP_COND_EXC_NC:
3939                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3940                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3941                         break;
3942                 case OP_COND_EXC_IOV:
3943                 case OP_COND_EXC_INO:
3944                 case OP_COND_EXC_IC:
3945                 case OP_COND_EXC_INC:
3946                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3947                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3948                         break;
3949
3950                 /* floating point opcodes */
3951                 case OP_R8CONST: {
3952                         double d = *(double *)ins->inst_p0;
3953
3954                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3955                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3956                         }
3957                         else {
3958                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3959                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3960                         }
3961                         break;
3962                 }
3963                 case OP_R4CONST: {
3964                         float f = *(float *)ins->inst_p0;
3965
3966                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3967                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3968                         }
3969                         else {
3970                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3971                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3972                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3973                         }
3974                         break;
3975                 }
3976                 case OP_STORER8_MEMBASE_REG:
3977                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3978                         break;
3979                 case OP_LOADR8_SPILL_MEMBASE:
3980                         g_assert_not_reached ();
3981                         break;
3982                 case OP_LOADR8_MEMBASE:
3983                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3984                         break;
3985                 case OP_STORER4_MEMBASE_REG:
3986                         /* This requires a double->single conversion */
3987                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3988                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3989                         break;
3990                 case OP_LOADR4_MEMBASE:
3991                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3992                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3993                         break;
3994                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3995                 case OP_ICONV_TO_R8:
3996                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3997                         break;
3998                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3999                 case OP_LCONV_TO_R8:
4000                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4001                         break;
4002                 case OP_FCONV_TO_R4:
4003                         /* FIXME: nothing to do ?? */
4004                         break;
4005                 case OP_FCONV_TO_I1:
4006                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4007                         break;
4008                 case OP_FCONV_TO_U1:
4009                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4010                         break;
4011                 case OP_FCONV_TO_I2:
4012                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4013                         break;
4014                 case OP_FCONV_TO_U2:
4015                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4016                         break;
4017                 case OP_FCONV_TO_U4:
4018                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4019                         break;
4020                 case OP_FCONV_TO_I4:
4021                 case OP_FCONV_TO_I:
4022                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4023                         break;
4024                 case OP_FCONV_TO_I8:
4025                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4026                         break;
4027                 case OP_LCONV_TO_R_UN: {
4028                         guint8 *br [2];
4029
4030                         /* Based on gcc code */
4031                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4032                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4033
4034                         /* Positive case */
4035                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4036                         br [1] = code; x86_jump8 (code, 0);
4037                         amd64_patch (br [0], code);
4038
4039                         /* Negative case */
4040                         /* Save to the red zone */
4041                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4042                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4043                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4044                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4045                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4046                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4047                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4048                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4049                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4050                         /* Restore */
4051                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4052                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4053                         amd64_patch (br [1], code);
4054                         break;
4055                 }
4056                 case OP_LCONV_TO_OVF_U4:
4057                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4058                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4059                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4060                         break;
4061                 case OP_LCONV_TO_OVF_I4_UN:
4062                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4063                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4064                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4065                         break;
4066                 case OP_FMOVE:
4067                         if (ins->dreg != ins->sreg1)
4068                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4069                         break;
4070                 case OP_FADD:
4071                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4072                         break;
4073                 case OP_FSUB:
4074                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4075                         break;
4076                 case OP_FMUL:
4077                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4078                         break;
4079                 case OP_FDIV:
4080                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4081                         break;
4082                 case OP_FNEG: {
4083                         static double r8_0 = -0.0;
4084
4085                         g_assert (ins->sreg1 == ins->dreg);
4086
4087                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4088                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4089                         break;
4090                 }
4091                 case OP_SIN:
4092                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4093                         break;
4094                 case OP_COS:
4095                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4096                         break;
4097                 case OP_ABS: {
4098                         static guint64 d = 0x7fffffffffffffffUL;
4099
4100                         g_assert (ins->sreg1 == ins->dreg);
4101
4102                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4103                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4104                         break;
4105                 }
4106                 case OP_SQRT:
4107                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4108                         break;
4109                 case OP_IMIN:
4110                         g_assert (cfg->opt & MONO_OPT_CMOV);
4111                         g_assert (ins->dreg == ins->sreg1);
4112                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4113                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4114                         break;
4115                 case OP_IMIN_UN:
4116                         g_assert (cfg->opt & MONO_OPT_CMOV);
4117                         g_assert (ins->dreg == ins->sreg1);
4118                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4119                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4120                         break;
4121                 case OP_IMAX:
4122                         g_assert (cfg->opt & MONO_OPT_CMOV);
4123                         g_assert (ins->dreg == ins->sreg1);
4124                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4125                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4126                         break;
4127                 case OP_IMAX_UN:
4128                         g_assert (cfg->opt & MONO_OPT_CMOV);
4129                         g_assert (ins->dreg == ins->sreg1);
4130                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4131                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4132                         break;
4133                 case OP_LMIN:
4134                         g_assert (cfg->opt & MONO_OPT_CMOV);
4135                         g_assert (ins->dreg == ins->sreg1);
4136                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4137                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4138                         break;
4139                 case OP_LMIN_UN:
4140                         g_assert (cfg->opt & MONO_OPT_CMOV);
4141                         g_assert (ins->dreg == ins->sreg1);
4142                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4143                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4144                         break;
4145                 case OP_LMAX:
4146                         g_assert (cfg->opt & MONO_OPT_CMOV);
4147                         g_assert (ins->dreg == ins->sreg1);
4148                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4149                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4150                         break;
4151                 case OP_LMAX_UN:
4152                         g_assert (cfg->opt & MONO_OPT_CMOV);
4153                         g_assert (ins->dreg == ins->sreg1);
4154                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4155                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4156                         break;
4157                 case OP_X86_FPOP:
4158                         break;
4159                 case OP_FCOMPARE:
4160                         /*
4161                          * The two arguments are swapped because the fbranch instructions
4162                          * depend on this for the non-sse case to work.
4163                          */
4164                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4165                         break;
4166                 case OP_FCEQ: {
4167                         /* zeroing the register at the start results in
4168                          * shorter and faster code (we can also remove the widening op)
4169                          */
4170                         guchar *unordered_check;
4171                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4172                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4173                         unordered_check = code;
4174                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4175                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4176                         amd64_patch (unordered_check, code);
4177                         break;
4178                 }
4179                 case OP_FCLT:
4180                 case OP_FCLT_UN:
4181                         /* zeroing the register at the start results in
4182                          * shorter and faster code (we can also remove the widening op)
4183                          */
4184                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4185                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4186                         if (ins->opcode == OP_FCLT_UN) {
4187                                 guchar *unordered_check = code;
4188                                 guchar *jump_to_end;
4189                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4190                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4191                                 jump_to_end = code;
4192                                 x86_jump8 (code, 0);
4193                                 amd64_patch (unordered_check, code);
4194                                 amd64_inc_reg (code, ins->dreg);
4195                                 amd64_patch (jump_to_end, code);
4196                         } else {
4197                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4198                         }
4199                         break;
4200                 case OP_FCGT:
4201                 case OP_FCGT_UN: {
4202                         /* zeroing the register at the start results in
4203                          * shorter and faster code (we can also remove the widening op)
4204                          */
4205                         guchar *unordered_check;
4206                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4207                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4208                         if (ins->opcode == OP_FCGT) {
4209                                 unordered_check = code;
4210                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4211                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4212                                 amd64_patch (unordered_check, code);
4213                         } else {
4214                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4215                         }
4216                         break;
4217                 }
4218                 case OP_FCLT_MEMBASE:
4219                 case OP_FCGT_MEMBASE:
4220                 case OP_FCLT_UN_MEMBASE:
4221                 case OP_FCGT_UN_MEMBASE:
4222                 case OP_FCEQ_MEMBASE: {
4223                         guchar *unordered_check, *jump_to_end;
4224                         int x86_cond;
4225
4226                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4227                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4228
4229                         switch (ins->opcode) {
4230                         case OP_FCEQ_MEMBASE:
4231                                 x86_cond = X86_CC_EQ;
4232                                 break;
4233                         case OP_FCLT_MEMBASE:
4234                         case OP_FCLT_UN_MEMBASE:
4235                                 x86_cond = X86_CC_LT;
4236                                 break;
4237                         case OP_FCGT_MEMBASE:
4238                         case OP_FCGT_UN_MEMBASE:
4239                                 x86_cond = X86_CC_GT;
4240                                 break;
4241                         default:
4242                                 g_assert_not_reached ();
4243                         }
4244
4245                         unordered_check = code;
4246                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4247                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4248
4249                         switch (ins->opcode) {
4250                         case OP_FCEQ_MEMBASE:
4251                         case OP_FCLT_MEMBASE:
4252                         case OP_FCGT_MEMBASE:
4253                                 amd64_patch (unordered_check, code);
4254                                 break;
4255                         case OP_FCLT_UN_MEMBASE:
4256                         case OP_FCGT_UN_MEMBASE:
4257                                 jump_to_end = code;
4258                                 x86_jump8 (code, 0);
4259                                 amd64_patch (unordered_check, code);
4260                                 amd64_inc_reg (code, ins->dreg);
4261                                 amd64_patch (jump_to_end, code);
4262                                 break;
4263                         default:
4264                                 break;
4265                         }
4266                         break;
4267                 }
4268                 case OP_FBEQ: {
4269                         guchar *jump = code;
4270                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4271                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4272                         amd64_patch (jump, code);
4273                         break;
4274                 }
4275                 case OP_FBNE_UN:
4276                         /* Branch if C013 != 100 */
4277                         /* branch if !ZF or (PF|CF) */
4278                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4279                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4280                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4281                         break;
4282                 case OP_FBLT:
4283                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4284                         break;
4285                 case OP_FBLT_UN:
4286                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4287                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4288                         break;
4289                 case OP_FBGT:
4290                 case OP_FBGT_UN:
4291                         if (ins->opcode == OP_FBGT) {
4292                                 guchar *br1;
4293
4294                                 /* skip branch if C1=1 */
4295                                 br1 = code;
4296                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4297                                 /* branch if (C0 | C3) = 1 */
4298                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4299                                 amd64_patch (br1, code);
4300                                 break;
4301                         } else {
4302                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4303                         }
4304                         break;
4305                 case OP_FBGE: {
4306                         /* Branch if C013 == 100 or 001 */
4307                         guchar *br1;
4308
4309                         /* skip branch if C1=1 */
4310                         br1 = code;
4311                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4312                         /* branch if (C0 | C3) = 1 */
4313                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4314                         amd64_patch (br1, code);
4315                         break;
4316                 }
4317                 case OP_FBGE_UN:
4318                         /* Branch if C013 == 000 */
4319                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4320                         break;
4321                 case OP_FBLE: {
4322                         /* Branch if C013=000 or 100 */
4323                         guchar *br1;
4324
4325                         /* skip branch if C1=1 */
4326                         br1 = code;
4327                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4328                         /* branch if C0=0 */
4329                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4330                         amd64_patch (br1, code);
4331                         break;
4332                 }
4333                 case OP_FBLE_UN:
4334                         /* Branch if C013 != 001 */
4335                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4336                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4337                         break;
4338                 case OP_CKFINITE:
4339                         /* Transfer value to the fp stack */
4340                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4341                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4342                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4343
4344                         amd64_push_reg (code, AMD64_RAX);
4345                         amd64_fxam (code);
4346                         amd64_fnstsw (code);
4347                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4348                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4349                         amd64_pop_reg (code, AMD64_RAX);
4350                         amd64_fstp (code, 0);
4351                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4352                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4353                         break;
4354                 case OP_TLS_GET: {
4355                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4356                         break;
4357                 }
4358                 case OP_MEMORY_BARRIER: {
4359                         /* Not needed on amd64 */
4360                         break;
4361                 }
4362                 case OP_ATOMIC_ADD_I4:
4363                 case OP_ATOMIC_ADD_I8: {
4364                         int dreg = ins->dreg;
4365                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4366
4367                         if (dreg == ins->inst_basereg)
4368                                 dreg = AMD64_R11;
4369
4370                         if (dreg != ins->sreg2)
4371                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4372
4373                         x86_prefix (code, X86_LOCK_PREFIX);
4374                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4375
4376                         if (dreg != ins->dreg)
4377                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4378
4379                         break;
4380                 }
4381                 case OP_ATOMIC_ADD_NEW_I4:
4382                 case OP_ATOMIC_ADD_NEW_I8: {
4383                         int dreg = ins->dreg;
4384                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4385
4386                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4387                                 dreg = AMD64_R11;
4388
4389                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4390                         amd64_prefix (code, X86_LOCK_PREFIX);
4391                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4392                         /* dreg contains the old value, add with sreg2 value */
4393                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4394
4395                         if (ins->dreg != dreg)
4396                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4397
4398                         break;
4399                 }
4400                 case OP_ATOMIC_EXCHANGE_I4:
4401                 case OP_ATOMIC_EXCHANGE_I8: {
4402                         guchar *br[2];
4403                         int sreg2 = ins->sreg2;
4404                         int breg = ins->inst_basereg;
4405                         guint32 size;
4406                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4407
4408                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4409                                 size = 8;
4410                         else
4411                                 size = 4;
4412
4413                         /*
4414                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4415                          * an explanation of how this works.
4416                          */
4417
4418                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4419                          * hack to overcome limits in x86 reg allocator
4420                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4421                          */
4422                         g_assert (ins->dreg == AMD64_RAX);
4423
4424                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4425                                 /* Highly unlikely, but possible */
4426                                 need_push = TRUE;
4427
4428                         /* The pushes invalidate rsp */
4429                         if ((breg == AMD64_RAX) || need_push) {
4430                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4431                                 breg = AMD64_R11;
4432                         }
4433
4434                         /* We need the EAX reg for the comparand */
4435                         if (ins->sreg2 == AMD64_RAX) {
4436                                 if (breg != AMD64_R11) {
4437                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4438                                         sreg2 = AMD64_R11;
4439                                 } else {
4440                                         g_assert (need_push);
4441                                         amd64_push_reg (code, AMD64_RDX);
4442                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4443                                         sreg2 = AMD64_RDX;
4444                                         rdx_pushed = TRUE;
4445                                 }
4446                         }
4447
4448                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4449
4450                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4451                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4452                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4453                         amd64_patch (br [1], br [0]);
4454
4455                         if (rdx_pushed)
4456                                 amd64_pop_reg (code, AMD64_RDX);
4457
4458                         break;
4459                 }
4460                 case OP_ATOMIC_CAS_I4:
4461                 case OP_ATOMIC_CAS_I8: {
4462                         guint32 size;
4463
4464                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4465                                 size = 8;
4466                         else
4467                                 size = 4;
4468
4469                         /*
4470                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4471                          * an explanation of how this works.
4472                          */
4473                         g_assert (ins->sreg3 == AMD64_RAX);
4474                         g_assert (ins->sreg1 != AMD64_RAX);
4475                         g_assert (ins->sreg1 != ins->sreg2);
4476
4477                         amd64_prefix (code, X86_LOCK_PREFIX);
4478                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4479
4480                         if (ins->dreg != AMD64_RAX)
4481                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4482                         break;
4483                 }
4484 #ifdef MONO_ARCH_SIMD_INTRINSICS
4485                 case OP_ADDPS:
4486                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4487                         break;
4488                 case OP_DIVPS:
4489                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4490                         break;
4491                 case OP_MULPS:
4492                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4493                         break;
4494                 case OP_SUBPS:
4495                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4496                         break;
4497                 case OP_MAXPS:
4498                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4499                         break;
4500                 case OP_MINPS:
4501                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4502                         break;
4503                 case OP_COMPPS:
4504                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4505                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4506                         break;
4507                 case OP_ANDPS:
4508                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4509                         break;
4510                 case OP_ANDNPS:
4511                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4512                         break;
4513                 case OP_ORPS:
4514                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4515                         break;
4516                 case OP_XORPS:
4517                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4518                         break;
4519                 case OP_SQRTPS:
4520                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4521                         break;
4522                 case OP_RSQRTPS:
4523                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4524                         break;
4525                 case OP_RCPPS:
4526                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4527                         break;
4528                 case OP_ADDSUBPS:
4529                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4530                         break;
4531                 case OP_HADDPS:
4532                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4533                         break;
4534                 case OP_HSUBPS:
4535                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4536                         break;
4537                 case OP_DUPPS_HIGH:
4538                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4539                         break;
4540                 case OP_DUPPS_LOW:
4541                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4542                         break;
4543
4544                 case OP_PSHUFLEW_HIGH:
4545                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4546                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4547                         break;
4548                 case OP_PSHUFLEW_LOW:
4549                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4550                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4551                         break;
4552                 case OP_PSHUFLED:
4553                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4554                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4555                         break;
4556
4557                 case OP_ADDPD:
4558                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4559                         break;
4560                 case OP_DIVPD:
4561                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4562                         break;
4563                 case OP_MULPD:
4564                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
4565                         break;
4566                 case OP_SUBPD:
4567                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
4568                         break;
4569                 case OP_MAXPD:
4570                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
4571                         break;
4572                 case OP_MINPD:
4573                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
4574                         break;
4575                 case OP_COMPPD:
4576                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4577                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4578                         break;
4579                 case OP_ANDPD:
4580                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
4581                         break;
4582                 case OP_ANDNPD:
4583                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
4584                         break;
4585                 case OP_ORPD:
4586                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
4587                         break;
4588                 case OP_XORPD:
4589                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
4590                         break;
4591                 /* TODO: This op is in the AMD64 manual but has not been implemented.
4592                 case OP_SQRTPD:
4593                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
4594                         break;
4595                 */
4596                 case OP_ADDSUBPD:
4597                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4598                         break;
4599                 case OP_HADDPD:
4600                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
4601                         break;
4602                 case OP_HSUBPD:
4603                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4604                         break;
4605                 case OP_DUPPD:
4606                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
4607                         break;
4608
4609                 case OP_EXTRACT_MASK:
4610                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
4611                         break;
4612
4613                 case OP_PAND:
4614                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
4615                         break;
4616                 case OP_POR:
4617                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
4618                         break;
4619                 case OP_PXOR:
4620                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
4621                         break;
4622
4623                 case OP_PADDB:
4624                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
4625                         break;
4626                 case OP_PADDW:
4627                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
4628                         break;
4629                 case OP_PADDD:
4630                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
4631                         break;
4632                 case OP_PADDQ:
4633                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
4634                         break;
4635 #endif
4636                 case OP_LIVERANGE_START: {
4637                         if (cfg->verbose_level > 1)
4638                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4639                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4640                         break;
4641                 }
4642                 case OP_LIVERANGE_END: {
4643                         if (cfg->verbose_level > 1)
4644                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4645                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4646                         break;
4647                 }
4648                 default:
4649                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4650                         g_assert_not_reached ();
4651                 }
4652
4653                 if ((code - cfg->native_code - offset) > max_len) {
4654                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4655                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4656                         g_assert_not_reached ();
4657                 }
4658
4659                 last_ins = ins;
4660                 last_offset = offset;
4661         }
4662
4663         cfg->code_len = code - cfg->native_code;
4664 }
4665
4666 #endif /* DISABLE_JIT */
4667
4668 void
4669 mono_arch_register_lowlevel_calls (void)
4670 {
4671         /* The signature doesn't matter */
4672         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4673 }
4674
4675 void
4676 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4677 {
4678         MonoJumpInfo *patch_info;
4679         gboolean compile_aot = !run_cctors;
4680
4681         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4682                 unsigned char *ip = patch_info->ip.i + code;
4683                 unsigned char *target;
4684
4685                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4686
4687                 if (compile_aot) {
4688                         switch (patch_info->type) {
4689                         case MONO_PATCH_INFO_BB:
4690                         case MONO_PATCH_INFO_LABEL:
4691                                 break;
4692                         default:
4693                                 /* No need to patch these */
4694                                 continue;
4695                         }
4696                 }
4697
4698                 switch (patch_info->type) {
4699                 case MONO_PATCH_INFO_NONE:
4700                         continue;
4701                 case MONO_PATCH_INFO_METHOD_REL:
4702                 case MONO_PATCH_INFO_R8:
4703                 case MONO_PATCH_INFO_R4:
4704                         g_assert_not_reached ();
4705                         continue;
4706                 case MONO_PATCH_INFO_BB:
4707                         break;
4708                 default:
4709                         break;
4710                 }
4711
4712                 /*
4713                  * Debug code to help track down problems where the target of a near call is
4714                  * is not valid.
4715                  */
4716                 if (amd64_is_near_call (ip)) {
4717                         gint64 disp = (guint8*)target - (guint8*)ip;
4718
4719                         if (!amd64_is_imm32 (disp)) {
4720                                 printf ("TYPE: %d\n", patch_info->type);
4721                                 switch (patch_info->type) {
4722                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4723                                         printf ("V: %s\n", patch_info->data.name);
4724                                         break;
4725                                 case MONO_PATCH_INFO_METHOD_JUMP:
4726                                 case MONO_PATCH_INFO_METHOD:
4727                                         printf ("V: %s\n", patch_info->data.method->name);
4728                                         break;
4729                                 default:
4730                                         break;
4731                                 }
4732                         }
4733                 }
4734
4735                 amd64_patch (ip, (gpointer)target);
4736         }
4737 }
4738
4739 static int
4740 get_max_epilog_size (MonoCompile *cfg)
4741 {
4742         int max_epilog_size = 16;
4743
4744         if (cfg->method->save_lmf)
4745                 max_epilog_size += 256;
4746
4747         if (mono_jit_trace_calls != NULL)
4748                 max_epilog_size += 50;
4749
4750         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4751                 max_epilog_size += 50;
4752
4753         max_epilog_size += (AMD64_NREG * 2);
4754
4755         return max_epilog_size;
4756 }
4757
4758 /*
4759  * This macro is used for testing whenever the unwinder works correctly at every point
4760  * where an async exception can happen.
4761  */
4762 /* This will generate a SIGSEGV at the given point in the code */
4763 #define async_exc_point(code) do { \
4764     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4765          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4766              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4767          cfg->arch.async_point_count ++; \
4768     } \
4769 } while (0)
4770
4771 guint8 *
4772 mono_arch_emit_prolog (MonoCompile *cfg)
4773 {
4774         MonoMethod *method = cfg->method;
4775         MonoBasicBlock *bb;
4776         MonoMethodSignature *sig;
4777         MonoInst *ins;
4778         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
4779         guint8 *code;
4780         CallInfo *cinfo;
4781         gint32 lmf_offset = cfg->arch.lmf_offset;
4782         gboolean args_clobbered = FALSE;
4783         gboolean trace = FALSE;
4784
4785         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4786
4787         code = cfg->native_code = g_malloc (cfg->code_size);
4788
4789         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4790                 trace = TRUE;
4791
4792         /* Amount of stack space allocated by register saving code */
4793         pos = 0;
4794
4795         /* Offset between RSP and the CFA */
4796         cfa_offset = 0;
4797
4798         /*
4799          * The prolog consists of the following parts:
4800          * FP present:
4801          * - push rbp, mov rbp, rsp
4802          * - save callee saved regs using pushes
4803          * - allocate frame
4804          * - save rgctx if needed
4805          * - save lmf if needed
4806          * FP not present:
4807          * - allocate frame
4808          * - save rgctx if needed
4809          * - save lmf if needed
4810          * - save callee saved regs using moves
4811          */
4812
4813         // CFA = sp + 8
4814         cfa_offset = 8;
4815         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4816         // IP saved at CFA - 8
4817         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4818         async_exc_point (code);
4819
4820         if (!cfg->arch.omit_fp) {
4821                 amd64_push_reg (code, AMD64_RBP);
4822                 cfa_offset += 8;
4823                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4824                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4825                 async_exc_point (code);
4826 #ifdef PLATFORM_WIN32
4827                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4828 #endif
4829
4830                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4831                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4832                 async_exc_point (code);
4833 #ifdef PLATFORM_WIN32
4834                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4835 #endif
4836         }
4837
4838         /* Save callee saved registers */
4839         if (!cfg->arch.omit_fp && !method->save_lmf) {
4840                 int offset = cfa_offset;
4841
4842                 for (i = 0; i < AMD64_NREG; ++i)
4843                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4844                                 amd64_push_reg (code, i);
4845                                 pos += sizeof (gpointer);
4846                                 offset += 8;
4847                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4848                                 async_exc_point (code);
4849                         }
4850         }
4851
4852         /* The param area is always at offset 0 from sp */
4853         /* This needs to be allocated here, since it has to come after the spill area */
4854         if (cfg->arch.no_pushes && cfg->param_area) {
4855                 if (cfg->arch.omit_fp)
4856                         // FIXME:
4857                         g_assert_not_reached ();
4858                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
4859         }
4860
4861         if (cfg->arch.omit_fp) {
4862                 /*
4863                  * On enter, the stack is misaligned by the the pushing of the return
4864                  * address. It is either made aligned by the pushing of %rbp, or by
4865                  * this.
4866                  */
4867                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4868                 if ((alloc_size % 16) == 0)
4869                         alloc_size += 8;
4870         } else {
4871                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4872
4873                 alloc_size -= pos;
4874         }
4875
4876         cfg->arch.stack_alloc_size = alloc_size;
4877
4878         /* Allocate stack frame */
4879         if (alloc_size) {
4880                 /* See mono_emit_stack_alloc */
4881 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4882                 guint32 remaining_size = alloc_size;
4883                 while (remaining_size >= 0x1000) {
4884                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4885                         if (cfg->arch.omit_fp) {
4886                                 cfa_offset += 0x1000;
4887                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4888                         }
4889                         async_exc_point (code);
4890 #ifdef PLATFORM_WIN32
4891                         if (cfg->arch.omit_fp)
4892                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4893 #endif
4894
4895                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4896                         remaining_size -= 0x1000;
4897                 }
4898                 if (remaining_size) {
4899                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4900                         if (cfg->arch.omit_fp) {
4901                                 cfa_offset += remaining_size;
4902                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4903                                 async_exc_point (code);
4904                         }
4905 #ifdef PLATFORM_WIN32
4906                         if (cfg->arch.omit_fp)
4907                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4908 #endif
4909                 }
4910 #else
4911                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4912                 if (cfg->arch.omit_fp) {
4913                         cfa_offset += alloc_size;
4914                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4915                         async_exc_point (code);
4916                 }
4917 #endif
4918         }
4919
4920         /* Stack alignment check */
4921 #if 0
4922         {
4923                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4924                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4925                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4926                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4927                 amd64_breakpoint (code);
4928         }
4929 #endif
4930
4931         /* Save LMF */
4932         if (method->save_lmf) {
4933                 /*
4934                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4935                  */
4936                 /* sp is saved right before calls */
4937                 /* Skip method (only needed for trampoline LMF frames) */
4938                 /* Save callee saved regs */
4939                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4940                         int offset;
4941
4942                         switch (i) {
4943                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4944                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4945                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4946                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4947                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4948                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4949 #ifdef PLATFORM_WIN32
4950                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4951                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4952 #endif
4953                         default:
4954                                 offset = -1;
4955                                 break;
4956                         }
4957
4958                         if (offset != -1) {
4959                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4960                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4961                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4962                         }
4963                 }
4964         }
4965
4966         /* Save callee saved registers */
4967         if (cfg->arch.omit_fp && !method->save_lmf) {
4968                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4969
4970                 /* Save caller saved registers after sp is adjusted */
4971                 /* The registers are saved at the bottom of the frame */
4972                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4973                 for (i = 0; i < AMD64_NREG; ++i)
4974                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4975                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4976                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4977                                 save_area_offset += 8;
4978                                 async_exc_point (code);
4979                         }
4980         }
4981
4982         /* store runtime generic context */
4983         if (cfg->rgctx_var) {
4984                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4985                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4986
4987                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4988         }
4989
4990         /* compute max_length in order to use short forward jumps */
4991         max_epilog_size = get_max_epilog_size (cfg);
4992         if (cfg->opt & MONO_OPT_BRANCH) {
4993                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4994                         MonoInst *ins;
4995                         int max_length = 0;
4996
4997                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4998                                 max_length += 6;
4999                         /* max alignment for loops */
5000                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5001                                 max_length += LOOP_ALIGNMENT;
5002
5003                         MONO_BB_FOR_EACH_INS (bb, ins) {
5004                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5005                         }
5006
5007                         /* Take prolog and epilog instrumentation into account */
5008                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5009                                 max_length += max_epilog_size;
5010
5011                         bb->max_length = max_length;
5012                 }
5013         }
5014
5015         sig = mono_method_signature (method);
5016         pos = 0;
5017
5018         cinfo = cfg->arch.cinfo;
5019
5020         if (sig->ret->type != MONO_TYPE_VOID) {
5021                 /* Save volatile arguments to the stack */
5022                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5023                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5024         }
5025
5026         /* Keep this in sync with emit_load_volatile_arguments */
5027         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5028                 ArgInfo *ainfo = cinfo->args + i;
5029                 gint32 stack_offset;
5030                 MonoType *arg_type;
5031
5032                 ins = cfg->args [i];
5033
5034                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5035                         /* Unused arguments */
5036                         continue;
5037
5038                 if (sig->hasthis && (i == 0))
5039                         arg_type = &mono_defaults.object_class->byval_arg;
5040                 else
5041                         arg_type = sig->params [i - sig->hasthis];
5042
5043                 stack_offset = ainfo->offset + ARGS_OFFSET;
5044
5045                 if (cfg->globalra) {
5046                         /* All the other moves are done by the register allocator */
5047                         switch (ainfo->storage) {
5048                         case ArgInFloatSSEReg:
5049                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5050                                 break;
5051                         case ArgValuetypeInReg:
5052                                 for (quad = 0; quad < 2; quad ++) {
5053                                         switch (ainfo->pair_storage [quad]) {
5054                                         case ArgInIReg:
5055                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5056                                                 break;
5057                                         case ArgInFloatSSEReg:
5058                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5059                                                 break;
5060                                         case ArgInDoubleSSEReg:
5061                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5062                                                 break;
5063                                         case ArgNone:
5064                                                 break;
5065                                         default:
5066                                                 g_assert_not_reached ();
5067                                         }
5068                                 }
5069                                 break;
5070                         default:
5071                                 break;
5072                         }
5073
5074                         continue;
5075                 }
5076
5077                 /* Save volatile arguments to the stack */
5078                 if (ins->opcode != OP_REGVAR) {
5079                         switch (ainfo->storage) {
5080                         case ArgInIReg: {
5081                                 guint32 size = 8;
5082
5083                                 /* FIXME: I1 etc */
5084                                 /*
5085                                 if (stack_offset & 0x1)
5086                                         size = 1;
5087                                 else if (stack_offset & 0x2)
5088                                         size = 2;
5089                                 else if (stack_offset & 0x4)
5090                                         size = 4;
5091                                 else
5092                                         size = 8;
5093                                 */
5094                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5095                                 break;
5096                         }
5097                         case ArgInFloatSSEReg:
5098                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5099                                 break;
5100                         case ArgInDoubleSSEReg:
5101                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5102                                 break;
5103                         case ArgValuetypeInReg:
5104                                 for (quad = 0; quad < 2; quad ++) {
5105                                         switch (ainfo->pair_storage [quad]) {
5106                                         case ArgInIReg:
5107                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5108                                                 break;
5109                                         case ArgInFloatSSEReg:
5110                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5111                                                 break;
5112                                         case ArgInDoubleSSEReg:
5113                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5114                                                 break;
5115                                         case ArgNone:
5116                                                 break;
5117                                         default:
5118                                                 g_assert_not_reached ();
5119                                         }
5120                                 }
5121                                 break;
5122                         case ArgValuetypeAddrInIReg:
5123                                 if (ainfo->pair_storage [0] == ArgInIReg)
5124                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5125                                 break;
5126                         default:
5127                                 break;
5128                         }
5129                 } else {
5130                         /* Argument allocated to (non-volatile) register */
5131                         switch (ainfo->storage) {
5132                         case ArgInIReg:
5133                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5134                                 break;
5135                         case ArgOnStack:
5136                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5137                                 break;
5138                         default:
5139                                 g_assert_not_reached ();
5140                         }
5141                 }
5142         }
5143
5144         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5145         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5146                 guint64 domain = (guint64)cfg->domain;
5147
5148                 args_clobbered = TRUE;
5149
5150                 /*
5151                  * The call might clobber argument registers, but they are already
5152                  * saved to the stack/global regs.
5153                  */
5154                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5155                         guint8 *buf, *no_domain_branch;
5156
5157                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5158                         if (cfg->compile_aot) {
5159                                 /* AOT code is only used in the root domain */
5160                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5161                         } else {
5162                                 if ((domain >> 32) == 0)
5163                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5164                                 else
5165                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5166                         }
5167                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5168                         no_domain_branch = code;
5169                         x86_branch8 (code, X86_CC_NE, 0, 0);
5170                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5171                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5172                         buf = code;
5173                         x86_branch8 (code, X86_CC_NE, 0, 0);
5174                         amd64_patch (no_domain_branch, code);
5175                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5176                                           (gpointer)"mono_jit_thread_attach", TRUE);
5177                         amd64_patch (buf, code);
5178 #ifdef PLATFORM_WIN32
5179                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5180                         /* FIXME: Add a separate key for LMF to avoid this */
5181                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5182 #endif
5183                 } else {
5184                         g_assert (!cfg->compile_aot);
5185                         if (cfg->compile_aot) {
5186                                 /* AOT code is only used in the root domain */
5187                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5188                         } else {
5189                                 if ((domain >> 32) == 0)
5190                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5191                                 else
5192                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5193                         }
5194                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5195                                           (gpointer)"mono_jit_thread_attach", TRUE);
5196                 }
5197         }
5198
5199         if (method->save_lmf) {
5200                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5201                         /*
5202                          * Optimized version which uses the mono_lmf TLS variable instead of
5203                          * indirection through the mono_lmf_addr TLS variable.
5204                          */
5205                         /* %rax = previous_lmf */
5206                         x86_prefix (code, X86_FS_PREFIX);
5207                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5208
5209                         /* Save previous_lmf */
5210                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5211                         /* Set new lmf */
5212                         if (lmf_offset == 0) {
5213                                 x86_prefix (code, X86_FS_PREFIX);
5214                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5215                         } else {
5216                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5217                                 x86_prefix (code, X86_FS_PREFIX);
5218                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5219                         }
5220                 } else {
5221                         if (lmf_addr_tls_offset != -1) {
5222                                 /* Load lmf quicky using the FS register */
5223                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5224 #ifdef PLATFORM_WIN32
5225                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5226                                 /* FIXME: Add a separate key for LMF to avoid this */
5227                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5228 #endif
5229                         }
5230                         else {
5231                                 /*
5232                                  * The call might clobber argument registers, but they are already
5233                                  * saved to the stack/global regs.
5234                                  */
5235                                 args_clobbered = TRUE;
5236                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5237                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5238                         }
5239
5240                         /* Save lmf_addr */
5241                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5242                         /* Save previous_lmf */
5243                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5244                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5245                         /* Set new lmf */
5246                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5247                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5248                 }
5249         }
5250
5251         if (trace) {
5252                 args_clobbered = TRUE;
5253                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5254         }
5255
5256         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5257                 args_clobbered = TRUE;
5258
5259         /*
5260          * Optimize the common case of the first bblock making a call with the same
5261          * arguments as the method. This works because the arguments are still in their
5262          * original argument registers.
5263          * FIXME: Generalize this
5264          */
5265         if (!args_clobbered) {
5266                 MonoBasicBlock *first_bb = cfg->bb_entry;
5267                 MonoInst *next;
5268
5269                 next = mono_bb_first_ins (first_bb);
5270                 if (!next && first_bb->next_bb) {
5271                         first_bb = first_bb->next_bb;
5272                         next = mono_bb_first_ins (first_bb);
5273                 }
5274
5275                 if (first_bb->in_count > 1)
5276                         next = NULL;
5277
5278                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5279                         ArgInfo *ainfo = cinfo->args + i;
5280                         gboolean match = FALSE;
5281
5282                         ins = cfg->args [i];
5283                         if (ins->opcode != OP_REGVAR) {
5284                                 switch (ainfo->storage) {
5285                                 case ArgInIReg: {
5286                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5287                                                 if (next->dreg == ainfo->reg) {
5288                                                         NULLIFY_INS (next);
5289                                                         match = TRUE;
5290                                                 } else {
5291                                                         next->opcode = OP_MOVE;
5292                                                         next->sreg1 = ainfo->reg;
5293                                                         /* Only continue if the instruction doesn't change argument regs */
5294                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5295                                                                 match = TRUE;
5296                                                 }
5297                                         }
5298                                         break;
5299                                 }
5300                                 default:
5301                                         break;
5302                                 }
5303                         } else {
5304                                 /* Argument allocated to (non-volatile) register */
5305                                 switch (ainfo->storage) {
5306                                 case ArgInIReg:
5307                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5308                                                 NULLIFY_INS (next);
5309                                                 match = TRUE;
5310                                         }
5311                                         break;
5312                                 default:
5313                                         break;
5314                                 }
5315                         }
5316
5317                         if (match) {
5318                                 next = next->next;
5319                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5320                                 if (!next)
5321                                         break;
5322                         }
5323                 }
5324         }
5325
5326         cfg->code_len = code - cfg->native_code;
5327
5328         g_assert (cfg->code_len < cfg->code_size);
5329
5330         return code;
5331 }
5332
5333 void
5334 mono_arch_emit_epilog (MonoCompile *cfg)
5335 {
5336         MonoMethod *method = cfg->method;
5337         int quad, pos, i;
5338         guint8 *code;
5339         int max_epilog_size;
5340         CallInfo *cinfo;
5341         gint32 lmf_offset = cfg->arch.lmf_offset;
5342
5343         max_epilog_size = get_max_epilog_size (cfg);
5344
5345         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5346                 cfg->code_size *= 2;
5347                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5348                 mono_jit_stats.code_reallocs++;
5349         }
5350
5351         code = cfg->native_code + cfg->code_len;
5352
5353         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5354                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5355
5356         /* the code restoring the registers must be kept in sync with OP_JMP */
5357         pos = 0;
5358
5359         if (method->save_lmf) {
5360                 /* check if we need to restore protection of the stack after a stack overflow */
5361                 if (mono_get_jit_tls_offset () != -1) {
5362                         guint8 *patch;
5363                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5364                         /* we load the value in a separate instruction: this mechanism may be
5365                          * used later as a safer way to do thread interruption
5366                          */
5367                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5368                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5369                         patch = code;
5370                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5371                         /* note that the call trampoline will preserve eax/edx */
5372                         x86_call_reg (code, X86_ECX);
5373                         x86_patch (patch, code);
5374                 } else {
5375                         /* FIXME: maybe save the jit tls in the prolog */
5376                 }
5377                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5378                         /*
5379                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5380                          * through the mono_lmf_addr TLS variable.
5381                          */
5382                         /* reg = previous_lmf */
5383                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5384                         x86_prefix (code, X86_FS_PREFIX);
5385                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5386                 } else {
5387                         /* Restore previous lmf */
5388                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5389                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5390                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5391                 }
5392
5393                 /* Restore caller saved regs */
5394                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5395                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5396                 }
5397                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5398                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5399                 }
5400                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5401                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5402                 }
5403                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5404                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5405                 }
5406                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5407                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5408                 }
5409                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5410                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5411                 }
5412 #ifdef PLATFORM_WIN32
5413                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5414                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5415                 }
5416                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5417                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5418                 }
5419 #endif
5420         } else {
5421
5422                 if (cfg->arch.omit_fp) {
5423                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5424
5425                         for (i = 0; i < AMD64_NREG; ++i)
5426                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5427                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5428                                         save_area_offset += 8;
5429                                 }
5430                 }
5431                 else {
5432                         for (i = 0; i < AMD64_NREG; ++i)
5433                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5434                                         pos -= sizeof (gpointer);
5435
5436                         if (pos) {
5437                                 if (pos == - sizeof (gpointer)) {
5438                                         /* Only one register, so avoid lea */
5439                                         for (i = AMD64_NREG - 1; i > 0; --i)
5440                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5441                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5442                                                 }
5443                                 }
5444                                 else {
5445                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5446
5447                                         /* Pop registers in reverse order */
5448                                         for (i = AMD64_NREG - 1; i > 0; --i)
5449                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5450                                                         amd64_pop_reg (code, i);
5451                                                 }
5452                                 }
5453                         }
5454                 }
5455         }
5456
5457         /* Load returned vtypes into registers if needed */
5458         cinfo = cfg->arch.cinfo;
5459         if (cinfo->ret.storage == ArgValuetypeInReg) {
5460                 ArgInfo *ainfo = &cinfo->ret;
5461                 MonoInst *inst = cfg->ret;
5462
5463                 for (quad = 0; quad < 2; quad ++) {
5464                         switch (ainfo->pair_storage [quad]) {
5465                         case ArgInIReg:
5466                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5467                                 break;
5468                         case ArgInFloatSSEReg:
5469                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5470                                 break;
5471                         case ArgInDoubleSSEReg:
5472                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5473                                 break;
5474                         case ArgNone:
5475                                 break;
5476                         default:
5477                                 g_assert_not_reached ();
5478                         }
5479                 }
5480         }
5481
5482         if (cfg->arch.omit_fp) {
5483                 if (cfg->arch.stack_alloc_size)
5484                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5485         } else {
5486                 amd64_leave (code);
5487         }
5488         async_exc_point (code);
5489         amd64_ret (code);
5490
5491         cfg->code_len = code - cfg->native_code;
5492
5493         g_assert (cfg->code_len < cfg->code_size);
5494 }
5495
5496 void
5497 mono_arch_emit_exceptions (MonoCompile *cfg)
5498 {
5499         MonoJumpInfo *patch_info;
5500         int nthrows, i;
5501         guint8 *code;
5502         MonoClass *exc_classes [16];
5503         guint8 *exc_throw_start [16], *exc_throw_end [16];
5504         guint32 code_size = 0;
5505
5506         /* Compute needed space */
5507         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5508                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5509                         code_size += 40;
5510                 if (patch_info->type == MONO_PATCH_INFO_R8)
5511                         code_size += 8 + 15; /* sizeof (double) + alignment */
5512                 if (patch_info->type == MONO_PATCH_INFO_R4)
5513                         code_size += 4 + 15; /* sizeof (float) + alignment */
5514         }
5515
5516         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5517                 cfg->code_size *= 2;
5518                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5519                 mono_jit_stats.code_reallocs++;
5520         }
5521
5522         code = cfg->native_code + cfg->code_len;
5523
5524         /* add code to raise exceptions */
5525         nthrows = 0;
5526         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5527                 switch (patch_info->type) {
5528                 case MONO_PATCH_INFO_EXC: {
5529                         MonoClass *exc_class;
5530                         guint8 *buf, *buf2;
5531                         guint32 throw_ip;
5532
5533                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5534
5535                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5536                         g_assert (exc_class);
5537                         throw_ip = patch_info->ip.i;
5538
5539                         //x86_breakpoint (code);
5540                         /* Find a throw sequence for the same exception class */
5541                         for (i = 0; i < nthrows; ++i)
5542                                 if (exc_classes [i] == exc_class)
5543                                         break;
5544                         if (i < nthrows) {
5545                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5546                                 x86_jump_code (code, exc_throw_start [i]);
5547                                 patch_info->type = MONO_PATCH_INFO_NONE;
5548                         }
5549                         else {
5550                                 buf = code;
5551                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5552                                 buf2 = code;
5553
5554                                 if (nthrows < 16) {
5555                                         exc_classes [nthrows] = exc_class;
5556                                         exc_throw_start [nthrows] = code;
5557                                 }
5558                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5559
5560                                 patch_info->type = MONO_PATCH_INFO_NONE;
5561
5562                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5563
5564                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5565                                 while (buf < buf2)
5566                                         x86_nop (buf);
5567
5568                                 if (nthrows < 16) {
5569                                         exc_throw_end [nthrows] = code;
5570                                         nthrows ++;
5571                                 }
5572                         }
5573                         break;
5574                 }
5575                 default:
5576                         /* do nothing */
5577                         break;
5578                 }
5579         }
5580
5581         /* Handle relocations with RIP relative addressing */
5582         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5583                 gboolean remove = FALSE;
5584
5585                 switch (patch_info->type) {
5586                 case MONO_PATCH_INFO_R8:
5587                 case MONO_PATCH_INFO_R4: {
5588                         guint8 *pos;
5589
5590                         /* The SSE opcodes require a 16 byte alignment */
5591                         code = (guint8*)ALIGN_TO (code, 16);
5592
5593                         pos = cfg->native_code + patch_info->ip.i;
5594
5595                         if (IS_REX (pos [1]))
5596                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5597                         else
5598                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5599
5600                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5601                                 *(double*)code = *(double*)patch_info->data.target;
5602                                 code += sizeof (double);
5603                         } else {
5604                                 *(float*)code = *(float*)patch_info->data.target;
5605                                 code += sizeof (float);
5606                         }
5607
5608                         remove = TRUE;
5609                         break;
5610                 }
5611                 default:
5612                         break;
5613                 }
5614
5615                 if (remove) {
5616                         if (patch_info == cfg->patch_info)
5617                                 cfg->patch_info = patch_info->next;
5618                         else {
5619                                 MonoJumpInfo *tmp;
5620
5621                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5622                                         ;
5623                                 tmp->next = patch_info->next;
5624                         }
5625                 }
5626         }
5627
5628         cfg->code_len = code - cfg->native_code;
5629
5630         g_assert (cfg->code_len < cfg->code_size);
5631
5632 }
5633
5634 void*
5635 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5636 {
5637         guchar *code = p;
5638         CallInfo *cinfo = NULL;
5639         MonoMethodSignature *sig;
5640         MonoInst *inst;
5641         int i, n, stack_area = 0;
5642
5643         /* Keep this in sync with mono_arch_get_argument_info */
5644
5645         if (enable_arguments) {
5646                 /* Allocate a new area on the stack and save arguments there */
5647                 sig = mono_method_signature (cfg->method);
5648
5649                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5650
5651                 n = sig->param_count + sig->hasthis;
5652
5653                 stack_area = ALIGN_TO (n * 8, 16);
5654
5655                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5656
5657                 for (i = 0; i < n; ++i) {
5658                         inst = cfg->args [i];
5659
5660                         if (inst->opcode == OP_REGVAR)
5661                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5662                         else {
5663                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5664                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5665                         }
5666                 }
5667         }
5668
5669         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5670         amd64_set_reg_template (code, AMD64_ARG_REG1);
5671         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5672         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5673
5674         if (enable_arguments)
5675                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5676
5677         return code;
5678 }
5679
5680 enum {
5681         SAVE_NONE,
5682         SAVE_STRUCT,
5683         SAVE_EAX,
5684         SAVE_EAX_EDX,
5685         SAVE_XMM
5686 };
5687
5688 void*
5689 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
5690 {
5691         guchar *code = p;
5692         int save_mode = SAVE_NONE;
5693         MonoMethod *method = cfg->method;
5694         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5695
5696         switch (rtype) {
5697         case MONO_TYPE_VOID:
5698                 /* special case string .ctor icall */
5699                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5700                         save_mode = SAVE_EAX;
5701                 else
5702                         save_mode = SAVE_NONE;
5703                 break;
5704         case MONO_TYPE_I8:
5705         case MONO_TYPE_U8:
5706                 save_mode = SAVE_EAX;
5707                 break;
5708         case MONO_TYPE_R4:
5709         case MONO_TYPE_R8:
5710                 save_mode = SAVE_XMM;
5711                 break;
5712         case MONO_TYPE_GENERICINST:
5713                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5714                         save_mode = SAVE_EAX;
5715                         break;
5716                 }
5717                 /* Fall through */
5718         case MONO_TYPE_VALUETYPE:
5719                 save_mode = SAVE_STRUCT;
5720                 break;
5721         default:
5722                 save_mode = SAVE_EAX;
5723                 break;
5724         }
5725
5726         /* Save the result and copy it into the proper argument register */
5727         switch (save_mode) {
5728         case SAVE_EAX:
5729                 amd64_push_reg (code, AMD64_RAX);
5730                 /* Align stack */
5731                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5732                 if (enable_arguments)
5733                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5734                 break;
5735         case SAVE_STRUCT:
5736                 /* FIXME: */
5737                 if (enable_arguments)
5738                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5739                 break;
5740         case SAVE_XMM:
5741                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5742                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5743                 /* Align stack */
5744                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5745                 /*
5746                  * The result is already in the proper argument register so no copying
5747                  * needed.
5748                  */
5749                 break;
5750         case SAVE_NONE:
5751                 break;
5752         default:
5753                 g_assert_not_reached ();
5754         }
5755
5756         /* Set %al since this is a varargs call */
5757         if (save_mode == SAVE_XMM)
5758                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5759         else
5760                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5761
5762         if (preserve_argument_registers) {
5763                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
5764                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
5765         }
5766
5767         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5768         amd64_set_reg_template (code, AMD64_ARG_REG1);
5769         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5770
5771         if (preserve_argument_registers) {
5772                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
5773                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
5774         }
5775
5776         /* Restore result */
5777         switch (save_mode) {
5778         case SAVE_EAX:
5779                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5780                 amd64_pop_reg (code, AMD64_RAX);
5781                 break;
5782         case SAVE_STRUCT:
5783                 /* FIXME: */
5784                 break;
5785         case SAVE_XMM:
5786                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5787                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5788                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5789                 break;
5790         case SAVE_NONE:
5791                 break;
5792         default:
5793                 g_assert_not_reached ();
5794         }
5795
5796         return code;
5797 }
5798
5799 void
5800 mono_arch_flush_icache (guint8 *code, gint size)
5801 {
5802         /* Not needed */
5803 }
5804
5805 void
5806 mono_arch_flush_register_windows (void)
5807 {
5808 }
5809
5810 gboolean
5811 mono_arch_is_inst_imm (gint64 imm)
5812 {
5813         return amd64_is_imm32 (imm);
5814 }
5815
5816 /*
5817  * Determine whenever the trap whose info is in SIGINFO is caused by
5818  * integer overflow.
5819  */
5820 gboolean
5821 mono_arch_is_int_overflow (void *sigctx, void *info)
5822 {
5823         MonoContext ctx;
5824         guint8* rip;
5825         int reg;
5826         gint64 value;
5827
5828         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5829
5830         rip = (guint8*)ctx.rip;
5831
5832         if (IS_REX (rip [0])) {
5833                 reg = amd64_rex_b (rip [0]);
5834                 rip ++;
5835         }
5836         else
5837                 reg = 0;
5838
5839         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5840                 /* idiv REG */
5841                 reg += x86_modrm_rm (rip [1]);
5842
5843                 switch (reg) {
5844                 case AMD64_RAX:
5845                         value = ctx.rax;
5846                         break;
5847                 case AMD64_RBX:
5848                         value = ctx.rbx;
5849                         break;
5850                 case AMD64_RCX:
5851                         value = ctx.rcx;
5852                         break;
5853                 case AMD64_RDX:
5854                         value = ctx.rdx;
5855                         break;
5856                 case AMD64_RBP:
5857                         value = ctx.rbp;
5858                         break;
5859                 case AMD64_RSP:
5860                         value = ctx.rsp;
5861                         break;
5862                 case AMD64_RSI:
5863                         value = ctx.rsi;
5864                         break;
5865                 case AMD64_RDI:
5866                         value = ctx.rdi;
5867                         break;
5868                 case AMD64_R12:
5869                         value = ctx.r12;
5870                         break;
5871                 case AMD64_R13:
5872                         value = ctx.r13;
5873                         break;
5874                 case AMD64_R14:
5875                         value = ctx.r14;
5876                         break;
5877                 case AMD64_R15:
5878                         value = ctx.r15;
5879                         break;
5880                 default:
5881                         g_assert_not_reached ();
5882                         reg = -1;
5883                 }
5884
5885                 if (value == -1)
5886                         return TRUE;
5887         }
5888
5889         return FALSE;
5890 }
5891
5892 guint32
5893 mono_arch_get_patch_offset (guint8 *code)
5894 {
5895         return 3;
5896 }
5897
5898 /**
5899  * mono_breakpoint_clean_code:
5900  *
5901  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5902  * breakpoints in the original code, they are removed in the copy.
5903  *
5904  * Returns TRUE if no sw breakpoint was present.
5905  */
5906 gboolean
5907 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5908 {
5909         int i;
5910         gboolean can_write = TRUE;
5911         /*
5912          * If method_start is non-NULL we need to perform bound checks, since we access memory
5913          * at code - offset we could go before the start of the method and end up in a different
5914          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5915          * instead.
5916          */
5917         if (!method_start || code - offset >= method_start) {
5918                 memcpy (buf, code - offset, size);
5919         } else {
5920                 int diff = code - method_start;
5921                 memset (buf, 0, size);
5922                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5923         }
5924         code -= offset;
5925         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5926                 int idx = mono_breakpoint_info_index [i];
5927                 guint8 *ptr;
5928                 if (idx < 1)
5929                         continue;
5930                 ptr = mono_breakpoint_info [idx].address;
5931                 if (ptr >= code && ptr < code + size) {
5932                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5933                         can_write = FALSE;
5934                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5935                         buf [ptr - code] = saved_byte;
5936                 }
5937         }
5938         return can_write;
5939 }
5940
5941 gpointer
5942 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5943 {
5944         guint8 buf [10];
5945         guint32 reg;
5946         gint32 disp;
5947         guint8 rex = 0;
5948
5949         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5950         code = buf + 9;
5951
5952         *displacement = 0;
5953
5954         code -= 7;
5955
5956         /*
5957          * A given byte sequence can match more than case here, so we have to be
5958          * really careful about the ordering of the cases. Longer sequences
5959          * come first.
5960          * There are two types of calls:
5961          * - direct calls: 0xff address_byte 8/32 bits displacement
5962          * - indirect calls: nop nop nop <call>
5963          * The nops make sure we don't confuse the instruction preceeding an indirect
5964          * call with a direct call.
5965          */
5966         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5967                 /* call OFFSET(%rip) */
5968                 disp = *(guint32*)(code + 3);
5969                 return (gpointer*)(code + disp + 7);
5970         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
5971                 /* call *[reg+disp32] using indexed addressing */
5972                 /* The LLVM JIT emits this, and we emit it too for %r12 */
5973                 if (IS_REX (code [-1])) {
5974                         rex = code [-1];
5975                         g_assert (amd64_rex_x (rex) == 0);
5976                 }
5977                 reg = amd64_sib_base (code [2]);
5978                 disp = *(gint32*)(code + 3);
5979         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5980                 /* call *[reg+disp32] */
5981                 if (IS_REX (code [0]))
5982                         rex = code [0];
5983                 reg = amd64_modrm_rm (code [2]);
5984                 disp = *(gint32*)(code + 3);
5985                 /* R10 is clobbered by the IMT thunk code */
5986                 g_assert (reg != AMD64_R10);
5987         } else if (code [2] == 0xe8) {
5988                 /* call <ADDR> */
5989                 return NULL;
5990         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
5991                 /* call *[r12+disp8] using indexed addressing */
5992                 if (IS_REX (code [2]))
5993                         rex = code [2];
5994                 reg = amd64_sib_base (code [5]);
5995                 disp = *(gint8*)(code + 6);
5996         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5997                 /* call *%reg */
5998                 return NULL;
5999         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6000                 /* call *[reg+disp8] */
6001                 if (IS_REX (code [3]))
6002                         rex = code [3];
6003                 reg = amd64_modrm_rm (code [5]);
6004                 disp = *(gint8*)(code + 6);
6005                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6006         }
6007         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6008                 /* call *%reg */
6009                 if (IS_REX (code [4]))
6010                         rex = code [4];
6011                 reg = amd64_modrm_rm (code [6]);
6012                 disp = 0;
6013         }
6014         else
6015                 g_assert_not_reached ();
6016
6017         reg += amd64_rex_b (rex);
6018
6019         /* R11 is clobbered by the trampoline code */
6020         g_assert (reg != AMD64_R11);
6021
6022         *displacement = disp;
6023         return (gpointer)regs [reg];
6024 }
6025
6026 int
6027 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6028 {
6029         int this_reg = AMD64_ARG_REG1;
6030
6031         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6032                 CallInfo *cinfo;
6033
6034                 if (!gsctx && code)
6035                         gsctx = mono_get_generic_context_from_code (code);
6036
6037                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6038
6039                 if (cinfo->ret.storage != ArgValuetypeInReg)
6040                         this_reg = AMD64_ARG_REG2;
6041                 g_free (cinfo);
6042         }
6043
6044         return this_reg;
6045 }
6046
6047 gpointer
6048 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6049 {
6050         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6051 }
6052
6053 #define MAX_ARCH_DELEGATE_PARAMS 10
6054
6055 static gpointer
6056 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6057 {
6058         guint8 *code, *start;
6059         int i;
6060
6061         if (has_target) {
6062                 start = code = mono_global_codeman_reserve (64);
6063
6064                 /* Replace the this argument with the target */
6065                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6066                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6067                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6068
6069                 g_assert ((code - start) < 64);
6070         } else {
6071                 start = code = mono_global_codeman_reserve (64);
6072
6073                 if (param_count == 0) {
6074                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6075                 } else {
6076                         /* We have to shift the arguments left */
6077                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6078                         for (i = 0; i < param_count; ++i) {
6079 #ifdef PLATFORM_WIN32
6080                                 if (i < 3)
6081                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6082                                 else
6083                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6084 #else
6085                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6086 #endif
6087                         }
6088
6089                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6090                 }
6091                 g_assert ((code - start) < 64);
6092         }
6093
6094         mono_debug_add_delegate_trampoline (start, code - start);
6095
6096         if (code_len)
6097                 *code_len = code - start;
6098
6099         return start;
6100 }
6101
6102 /*
6103  * mono_arch_get_delegate_invoke_impls:
6104  *
6105  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6106  * trampolines.
6107  */
6108 GSList*
6109 mono_arch_get_delegate_invoke_impls (void)
6110 {
6111         GSList *res = NULL;
6112         guint8 *code;
6113         guint32 code_len;
6114         int i;
6115
6116         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6117         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6118
6119         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6120                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6121                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6122         }
6123
6124         return res;
6125 }
6126
6127 gpointer
6128 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6129 {
6130         guint8 *code, *start;
6131         int i;
6132
6133         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6134                 return NULL;
6135
6136         /* FIXME: Support more cases */
6137         if (MONO_TYPE_ISSTRUCT (sig->ret))
6138                 return NULL;
6139
6140         if (has_target) {
6141                 static guint8* cached = NULL;
6142
6143                 if (cached)
6144                         return cached;
6145
6146                 if (mono_aot_only)
6147                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
6148                 else
6149                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
6150
6151                 mono_memory_barrier ();
6152
6153                 cached = start;
6154         } else {
6155                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6156                 for (i = 0; i < sig->param_count; ++i)
6157                         if (!mono_is_regsize_var (sig->params [i]))
6158                                 return NULL;
6159                 if (sig->param_count > 4)
6160                         return NULL;
6161
6162                 code = cache [sig->param_count];
6163                 if (code)
6164                         return code;
6165
6166                 if (mono_aot_only) {
6167                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6168                         start = mono_aot_get_named_code (name);
6169                         g_free (name);
6170                 } else {
6171                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6172                 }
6173
6174                 mono_memory_barrier ();
6175
6176                 cache [sig->param_count] = start;
6177         }
6178
6179         return start;
6180 }
6181
6182 /*
6183  * Support for fast access to the thread-local lmf structure using the GS
6184  * segment register on NPTL + kernel 2.6.x.
6185  */
6186
6187 static gboolean tls_offset_inited = FALSE;
6188
6189 void
6190 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6191 {
6192         if (!tls_offset_inited) {
6193 #ifdef PLATFORM_WIN32
6194                 /*
6195                  * We need to init this multiple times, since when we are first called, the key might not
6196                  * be initialized yet.
6197                  */
6198                 appdomain_tls_offset = mono_domain_get_tls_key ();
6199                 lmf_tls_offset = mono_get_jit_tls_key ();
6200                 thread_tls_offset = mono_thread_get_tls_key ();
6201                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6202
6203                 /* Only 64 tls entries can be accessed using inline code */
6204                 if (appdomain_tls_offset >= 64)
6205                         appdomain_tls_offset = -1;
6206                 if (lmf_tls_offset >= 64)
6207                         lmf_tls_offset = -1;
6208                 if (thread_tls_offset >= 64)
6209                         thread_tls_offset = -1;
6210 #else
6211                 tls_offset_inited = TRUE;
6212 #ifdef MONO_XEN_OPT
6213                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6214 #endif
6215                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6216                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6217                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6218                 thread_tls_offset = mono_thread_get_tls_offset ();
6219 #endif
6220         }
6221 }
6222
6223 void
6224 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6225 {
6226 }
6227
6228 #ifdef MONO_ARCH_HAVE_IMT
6229
6230 #define CMP_SIZE (6 + 1)
6231 #define CMP_REG_REG_SIZE (4 + 1)
6232 #define BR_SMALL_SIZE 2
6233 #define BR_LARGE_SIZE 6
6234 #define MOV_REG_IMM_SIZE 10
6235 #define MOV_REG_IMM_32BIT_SIZE 6
6236 #define JUMP_REG_SIZE (2 + 1)
6237
6238 static int
6239 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6240 {
6241         int i, distance = 0;
6242         for (i = start; i < target; ++i)
6243                 distance += imt_entries [i]->chunk_size;
6244         return distance;
6245 }
6246
6247 /*
6248  * LOCKING: called with the domain lock held
6249  */
6250 gpointer
6251 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6252         gpointer fail_tramp)
6253 {
6254         int i;
6255         int size = 0;
6256         guint8 *code, *start;
6257         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6258
6259         for (i = 0; i < count; ++i) {
6260                 MonoIMTCheckItem *item = imt_entries [i];
6261                 if (item->is_equals) {
6262                         if (item->check_target_idx) {
6263                                 if (!item->compare_done) {
6264                                         if (amd64_is_imm32 (item->key))
6265                                                 item->chunk_size += CMP_SIZE;
6266                                         else
6267                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6268                                 }
6269                                 if (item->has_target_code) {
6270                                         item->chunk_size += MOV_REG_IMM_SIZE;
6271                                 } else {
6272                                         if (vtable_is_32bit)
6273                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6274                                         else
6275                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6276                                 }
6277                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6278                         } else {
6279                                 if (fail_tramp) {
6280                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
6281                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
6282                                 } else {
6283                                         if (vtable_is_32bit)
6284                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6285                                         else
6286                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6287                                         item->chunk_size += JUMP_REG_SIZE;
6288                                         /* with assert below:
6289                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6290                                          */
6291                                 }
6292                         }
6293                 } else {
6294                         if (amd64_is_imm32 (item->key))
6295                                 item->chunk_size += CMP_SIZE;
6296                         else
6297                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6298                         item->chunk_size += BR_LARGE_SIZE;
6299                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6300                 }
6301                 size += item->chunk_size;
6302         }
6303         if (fail_tramp)
6304                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6305         else
6306                 code = mono_domain_code_reserve (domain, size);
6307         start = code;
6308         for (i = 0; i < count; ++i) {
6309                 MonoIMTCheckItem *item = imt_entries [i];
6310                 item->code_target = code;
6311                 if (item->is_equals) {
6312                         gboolean fail_case = !item->check_target_idx && fail_tramp;
6313
6314                         if (item->check_target_idx || fail_case) {
6315                                 if (!item->compare_done || fail_case) {
6316                                         if (amd64_is_imm32 (item->key))
6317                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6318                                         else {
6319                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6320                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6321                                         }
6322                                 }
6323                                 item->jmp_code = code;
6324                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6325                                 /* See the comment below about R10 */
6326                                 if (item->has_target_code) {
6327                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6328                                         amd64_jump_reg (code, AMD64_R10);
6329                                 } else {
6330                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6331                                         amd64_jump_membase (code, AMD64_R10, 0);
6332                                 }
6333
6334                                 if (fail_case) {
6335                                         amd64_patch (item->jmp_code, code);
6336                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
6337                                         amd64_jump_reg (code, AMD64_R10);
6338                                         item->jmp_code = NULL;
6339                                 }
6340                         } else {
6341                                 /* enable the commented code to assert on wrong method */
6342 #if 0
6343                                 if (amd64_is_imm32 (item->key))
6344                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6345                                 else {
6346                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
6347                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6348                                 }
6349                                 item->jmp_code = code;
6350                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6351                                 /* See the comment below about R10 */
6352                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6353                                 amd64_jump_membase (code, AMD64_R10, 0);
6354                                 amd64_patch (item->jmp_code, code);
6355                                 amd64_breakpoint (code);
6356                                 item->jmp_code = NULL;
6357 #else
6358                                 /* We're using R10 here because R11
6359                                    needs to be preserved.  R10 needs
6360                                    to be preserved for calls which
6361                                    require a runtime generic context,
6362                                    but interface calls don't. */
6363                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6364                                 amd64_jump_membase (code, AMD64_R10, 0);
6365 #endif
6366                         }
6367                 } else {
6368                         if (amd64_is_imm32 (item->key))
6369                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6370                         else {
6371                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6372                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6373                         }
6374                         item->jmp_code = code;
6375                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6376                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6377                         else
6378                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6379                 }
6380                 g_assert (code - item->code_target <= item->chunk_size);
6381         }
6382         /* patch the branches to get to the target items */
6383         for (i = 0; i < count; ++i) {
6384                 MonoIMTCheckItem *item = imt_entries [i];
6385                 if (item->jmp_code) {
6386                         if (item->check_target_idx) {
6387                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6388                         }
6389                 }
6390         }
6391
6392         if (!fail_tramp)
6393                 mono_stats.imt_thunks_size += code - start;
6394         g_assert (code - start <= size);
6395
6396         return start;
6397 }
6398
6399 MonoMethod*
6400 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6401 {
6402         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6403 }
6404
6405 MonoObject*
6406 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6407 {
6408         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
6409 }
6410 #endif
6411
6412 MonoVTable*
6413 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6414 {
6415         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6416 }
6417
6418 MonoInst*
6419 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6420 {
6421         MonoInst *ins = NULL;
6422         int opcode = 0;
6423
6424         if (cmethod->klass == mono_defaults.math_class) {
6425                 if (strcmp (cmethod->name, "Sin") == 0) {
6426                         opcode = OP_SIN;
6427                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6428                         opcode = OP_COS;
6429                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6430                         opcode = OP_SQRT;
6431                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6432                         opcode = OP_ABS;
6433                 }
6434
6435                 if (opcode) {
6436                         MONO_INST_NEW (cfg, ins, opcode);
6437                         ins->type = STACK_R8;
6438                         ins->dreg = mono_alloc_freg (cfg);
6439                         ins->sreg1 = args [0]->dreg;
6440                         MONO_ADD_INS (cfg->cbb, ins);
6441                 }
6442
6443                 opcode = 0;
6444                 if (cfg->opt & MONO_OPT_CMOV) {
6445                         if (strcmp (cmethod->name, "Min") == 0) {
6446                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6447                                         opcode = OP_IMIN;
6448                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6449                                         opcode = OP_IMIN_UN;
6450                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6451                                         opcode = OP_LMIN;
6452                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6453                                         opcode = OP_LMIN_UN;
6454                         } else if (strcmp (cmethod->name, "Max") == 0) {
6455                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6456                                         opcode = OP_IMAX;
6457                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6458                                         opcode = OP_IMAX_UN;
6459                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6460                                         opcode = OP_LMAX;
6461                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6462                                         opcode = OP_LMAX_UN;
6463                         }
6464                 }
6465
6466                 if (opcode) {
6467                         MONO_INST_NEW (cfg, ins, opcode);
6468                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6469                         ins->dreg = mono_alloc_ireg (cfg);
6470                         ins->sreg1 = args [0]->dreg;
6471                         ins->sreg2 = args [1]->dreg;
6472                         MONO_ADD_INS (cfg->cbb, ins);
6473                 }
6474
6475 #if 0
6476                 /* OP_FREM is not IEEE compatible */
6477                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6478                         MONO_INST_NEW (cfg, ins, OP_FREM);
6479                         ins->inst_i0 = args [0];
6480                         ins->inst_i1 = args [1];
6481                 }
6482 #endif
6483         }
6484
6485         /*
6486          * Can't implement CompareExchange methods this way since they have
6487          * three arguments.
6488          */
6489
6490         return ins;
6491 }
6492
6493 gboolean
6494 mono_arch_print_tree (MonoInst *tree, int arity)
6495 {
6496         return 0;
6497 }
6498
6499 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6500 {
6501         MonoInst* ins;
6502
6503         if (appdomain_tls_offset == -1)
6504                 return NULL;
6505
6506         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6507         ins->inst_offset = appdomain_tls_offset;
6508         return ins;
6509 }
6510
6511 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6512 {
6513         MonoInst* ins;
6514
6515         if (thread_tls_offset == -1)
6516                 return NULL;
6517
6518         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6519         ins->inst_offset = thread_tls_offset;
6520         return ins;
6521 }
6522
6523 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6524
6525 gpointer
6526 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6527 {
6528         switch (reg) {
6529         case AMD64_RCX: return (gpointer)ctx->rcx;
6530         case AMD64_RDX: return (gpointer)ctx->rdx;
6531         case AMD64_RBX: return (gpointer)ctx->rbx;
6532         case AMD64_RBP: return (gpointer)ctx->rbp;
6533         case AMD64_RSP: return (gpointer)ctx->rsp;
6534         default:
6535                 if (reg < 8)
6536                         return _CTX_REG (ctx, rax, reg);
6537                 else if (reg >= 12)
6538                         return _CTX_REG (ctx, r12, reg - 12);
6539                 else
6540                         g_assert_not_reached ();
6541         }
6542 }