mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_replace_type (callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoMethodHeader *header;
1653         MonoInst *ins;
1654         int i;
1655         CallInfo *cinfo;
1656
1657         header = cfg->header;
1658
1659         sig = mono_method_signature (cfg->method);
1660
1661         cinfo = cfg->arch.cinfo;
1662         sig_ret = mini_replace_type (sig->ret);
1663
1664         /*
1665          * Contrary to mono_arch_allocate_vars (), the information should describe
1666          * where the arguments are at the beginning of the method, not where they can be
1667          * accessed during the execution of the method. The later makes no sense for the
1668          * global register allocator, since a variable can be in more than one location.
1669          */
1670         if (sig_ret->type != MONO_TYPE_VOID) {
1671                 switch (cinfo->ret.storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1676                                 cfg->vret_addr->opcode = OP_REGVAR;
1677                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1678                         }
1679                         else {
1680                                 cfg->ret->opcode = OP_REGVAR;
1681                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1682                         }
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         cfg->ret->opcode = OP_REGOFFSET;
1686                         cfg->ret->inst_basereg = -1;
1687                         cfg->ret->inst_offset = -1;
1688                         break;
1689                 default:
1690                         g_assert_not_reached ();
1691                 }
1692         }
1693
1694         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1695                 ArgInfo *ainfo = &cinfo->args [i];
1696                 MonoType *arg_type;
1697
1698                 ins = cfg->args [i];
1699
1700                 if (sig->hasthis && (i == 0))
1701                         arg_type = &mono_defaults.object_class->byval_arg;
1702                 else
1703                         arg_type = sig->params [i - sig->hasthis];
1704
1705                 switch (ainfo->storage) {
1706                 case ArgInIReg:
1707                 case ArgInFloatSSEReg:
1708                 case ArgInDoubleSSEReg:
1709                         ins->opcode = OP_REGVAR;
1710                         ins->inst_c0 = ainfo->reg;
1711                         break;
1712                 case ArgOnStack:
1713                         ins->opcode = OP_REGOFFSET;
1714                         ins->inst_basereg = -1;
1715                         ins->inst_offset = -1;
1716                         break;
1717                 case ArgValuetypeInReg:
1718                         /* Dummy */
1719                         ins->opcode = OP_NOP;
1720                         break;
1721                 default:
1722                         g_assert_not_reached ();
1723                 }
1724         }
1725 }
1726
1727 void
1728 mono_arch_allocate_vars (MonoCompile *cfg)
1729 {
1730         MonoType *sig_ret;
1731         MonoMethodSignature *sig;
1732         MonoMethodHeader *header;
1733         MonoInst *ins;
1734         int i, offset;
1735         guint32 locals_stack_size, locals_stack_align;
1736         gint32 *offsets;
1737         CallInfo *cinfo;
1738
1739         header = cfg->header;
1740
1741         sig = mono_method_signature (cfg->method);
1742
1743         cinfo = cfg->arch.cinfo;
1744         sig_ret = mini_replace_type (sig->ret);
1745
1746         mono_arch_compute_omit_fp (cfg);
1747
1748         /*
1749          * We use the ABI calling conventions for managed code as well.
1750          * Exception: valuetypes are only sometimes passed or returned in registers.
1751          */
1752
1753         /*
1754          * The stack looks like this:
1755          * <incoming arguments passed on the stack>
1756          * <return value>
1757          * <lmf/caller saved registers>
1758          * <locals>
1759          * <spill area>
1760          * <localloc area>  -> grows dynamically
1761          * <params area>
1762          */
1763
1764         if (cfg->arch.omit_fp) {
1765                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1766                 cfg->frame_reg = AMD64_RSP;
1767                 offset = 0;
1768         } else {
1769                 /* Locals are allocated backwards from %fp */
1770                 cfg->frame_reg = AMD64_RBP;
1771                 offset = 0;
1772         }
1773
1774         cfg->arch.saved_iregs = cfg->used_int_regs;
1775         if (cfg->method->save_lmf)
1776                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1777                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1778
1779         if (cfg->arch.omit_fp)
1780                 cfg->arch.reg_save_area_offset = offset;
1781         /* Reserve space for callee saved registers */
1782         for (i = 0; i < AMD64_NREG; ++i)
1783                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1784                         offset += sizeof(mgreg_t);
1785                 }
1786         if (!cfg->arch.omit_fp)
1787                 cfg->arch.reg_save_area_offset = -offset;
1788
1789         if (sig_ret->type != MONO_TYPE_VOID) {
1790                 switch (cinfo->ret.storage) {
1791                 case ArgInIReg:
1792                 case ArgInFloatSSEReg:
1793                 case ArgInDoubleSSEReg:
1794                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1795                                 if (cfg->globalra) {
1796                                         cfg->vret_addr->opcode = OP_REGVAR;
1797                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1798                                 } else {
1799                                         /* The register is volatile */
1800                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1801                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1802                                         if (cfg->arch.omit_fp) {
1803                                                 cfg->vret_addr->inst_offset = offset;
1804                                                 offset += 8;
1805                                         } else {
1806                                                 offset += 8;
1807                                                 cfg->vret_addr->inst_offset = -offset;
1808                                         }
1809                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1810                                                 printf ("vret_addr =");
1811                                                 mono_print_ins (cfg->vret_addr);
1812                                         }
1813                                 }
1814                         }
1815                         else {
1816                                 cfg->ret->opcode = OP_REGVAR;
1817                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1818                         }
1819                         break;
1820                 case ArgValuetypeInReg:
1821                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1822                         cfg->ret->opcode = OP_REGOFFSET;
1823                         cfg->ret->inst_basereg = cfg->frame_reg;
1824                         if (cfg->arch.omit_fp) {
1825                                 cfg->ret->inst_offset = offset;
1826                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1827                         } else {
1828                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1829                                 cfg->ret->inst_offset = - offset;
1830                         }
1831                         break;
1832                 default:
1833                         g_assert_not_reached ();
1834                 }
1835                 if (!cfg->globalra)
1836                         cfg->ret->dreg = cfg->ret->inst_c0;
1837         }
1838
1839         /* Allocate locals */
1840         if (!cfg->globalra) {
1841                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1842                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1843                         char *mname = mono_method_full_name (cfg->method, TRUE);
1844                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1845                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1846                         g_free (mname);
1847                         return;
1848                 }
1849
1850                 if (locals_stack_align) {
1851                         offset += (locals_stack_align - 1);
1852                         offset &= ~(locals_stack_align - 1);
1853                 }
1854                 if (cfg->arch.omit_fp) {
1855                         cfg->locals_min_stack_offset = offset;
1856                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1857                 } else {
1858                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1859                         cfg->locals_max_stack_offset = - offset;
1860                 }
1861
1862                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1863                         if (offsets [i] != -1) {
1864                                 MonoInst *ins = cfg->varinfo [i];
1865                                 ins->opcode = OP_REGOFFSET;
1866                                 ins->inst_basereg = cfg->frame_reg;
1867                                 if (cfg->arch.omit_fp)
1868                                         ins->inst_offset = (offset + offsets [i]);
1869                                 else
1870                                         ins->inst_offset = - (offset + offsets [i]);
1871                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1872                         }
1873                 }
1874                 offset += locals_stack_size;
1875         }
1876
1877         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1878                 g_assert (!cfg->arch.omit_fp);
1879                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1881         }
1882
1883         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1884                 ins = cfg->args [i];
1885                 if (ins->opcode != OP_REGVAR) {
1886                         ArgInfo *ainfo = &cinfo->args [i];
1887                         gboolean inreg = TRUE;
1888                         MonoType *arg_type;
1889
1890                         if (sig->hasthis && (i == 0))
1891                                 arg_type = &mono_defaults.object_class->byval_arg;
1892                         else
1893                                 arg_type = sig->params [i - sig->hasthis];
1894
1895                         if (cfg->globalra) {
1896                                 /* The new allocator needs info about the original locations of the arguments */
1897                                 switch (ainfo->storage) {
1898                                 case ArgInIReg:
1899                                 case ArgInFloatSSEReg:
1900                                 case ArgInDoubleSSEReg:
1901                                         ins->opcode = OP_REGVAR;
1902                                         ins->inst_c0 = ainfo->reg;
1903                                         break;
1904                                 case ArgOnStack:
1905                                         g_assert (!cfg->arch.omit_fp);
1906                                         ins->opcode = OP_REGOFFSET;
1907                                         ins->inst_basereg = cfg->frame_reg;
1908                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1909                                         break;
1910                                 case ArgValuetypeInReg:
1911                                         ins->opcode = OP_REGOFFSET;
1912                                         ins->inst_basereg = cfg->frame_reg;
1913                                         /* These arguments are saved to the stack in the prolog */
1914                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1915                                         if (cfg->arch.omit_fp) {
1916                                                 ins->inst_offset = offset;
1917                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1918                                         } else {
1919                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1920                                                 ins->inst_offset = - offset;
1921                                         }
1922                                         break;
1923                                 default:
1924                                         g_assert_not_reached ();
1925                                 }
1926
1927                                 continue;
1928                         }
1929
1930                         /* FIXME: Allocate volatile arguments to registers */
1931                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1932                                 inreg = FALSE;
1933
1934                         /*
1935                          * Under AMD64, all registers used to pass arguments to functions
1936                          * are volatile across calls.
1937                          * FIXME: Optimize this.
1938                          */
1939                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1940                                 inreg = FALSE;
1941
1942                         ins->opcode = OP_REGOFFSET;
1943
1944                         switch (ainfo->storage) {
1945                         case ArgInIReg:
1946                         case ArgInFloatSSEReg:
1947                         case ArgInDoubleSSEReg:
1948                                 if (inreg) {
1949                                         ins->opcode = OP_REGVAR;
1950                                         ins->dreg = ainfo->reg;
1951                                 }
1952                                 break;
1953                         case ArgOnStack:
1954                                 g_assert (!cfg->arch.omit_fp);
1955                                 ins->opcode = OP_REGOFFSET;
1956                                 ins->inst_basereg = cfg->frame_reg;
1957                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 break;
1959                         case ArgValuetypeInReg:
1960                                 break;
1961                         case ArgValuetypeAddrInIReg: {
1962                                 MonoInst *indir;
1963                                 g_assert (!cfg->arch.omit_fp);
1964
1965                                 MONO_INST_NEW (cfg, indir, 0);
1966                                 indir->opcode = OP_REGOFFSET;
1967                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1968                                         indir->inst_basereg = cfg->frame_reg;
1969                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1970                                         offset += (sizeof (gpointer));
1971                                         indir->inst_offset = - offset;
1972                                 }
1973                                 else {
1974                                         indir->inst_basereg = cfg->frame_reg;
1975                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1976                                 }
1977
1978                                 ins->opcode = OP_VTARG_ADDR;
1979                                 ins->inst_left = indir;
1980
1981                                 break;
1982                         }
1983                         default:
1984                                 NOT_IMPLEMENTED;
1985                         }
1986
1987                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1988                                 ins->opcode = OP_REGOFFSET;
1989                                 ins->inst_basereg = cfg->frame_reg;
1990                                 /* These arguments are saved to the stack in the prolog */
1991                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1992                                 if (cfg->arch.omit_fp) {
1993                                         ins->inst_offset = offset;
1994                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1995                                         // Arguments are yet supported by the stack map creation code
1996                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1997                                 } else {
1998                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1999                                         ins->inst_offset = - offset;
2000                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2001                                 }
2002                         }
2003                 }
2004         }
2005
2006         cfg->stack_offset = offset;
2007 }
2008
2009 void
2010 mono_arch_create_vars (MonoCompile *cfg)
2011 {
2012         MonoMethodSignature *sig;
2013         CallInfo *cinfo;
2014         MonoType *sig_ret;
2015
2016         sig = mono_method_signature (cfg->method);
2017
2018         if (!cfg->arch.cinfo)
2019                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2020         cinfo = cfg->arch.cinfo;
2021
2022         if (cinfo->ret.storage == ArgValuetypeInReg)
2023                 cfg->ret_var_is_local = TRUE;
2024
2025         sig_ret = mini_replace_type (sig->ret);
2026         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2027                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2028                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2029                         printf ("vret_addr = ");
2030                         mono_print_ins (cfg->vret_addr);
2031                 }
2032         }
2033
2034         if (cfg->gen_seq_points_debug_data) {
2035                 MonoInst *ins;
2036
2037                 if (cfg->compile_aot) {
2038                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2039                         ins->flags |= MONO_INST_VOLATILE;
2040                         cfg->arch.seq_point_info_var = ins;
2041                 }
2042
2043             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2044                 ins->flags |= MONO_INST_VOLATILE;
2045                 cfg->arch.ss_trigger_page_var = ins;
2046         }
2047
2048         if (cfg->method->save_lmf)
2049                 cfg->create_lmf_var = TRUE;
2050
2051         if (cfg->method->save_lmf) {
2052                 cfg->lmf_ir = TRUE;
2053 #if !defined(HOST_WIN32)
2054                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2055                         cfg->lmf_ir_mono_lmf = TRUE;
2056 #endif
2057         }
2058 }
2059
2060 static void
2061 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2062 {
2063         MonoInst *ins;
2064
2065         switch (storage) {
2066         case ArgInIReg:
2067                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2068                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2069                 ins->sreg1 = tree->dreg;
2070                 MONO_ADD_INS (cfg->cbb, ins);
2071                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2072                 break;
2073         case ArgInFloatSSEReg:
2074                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2075                 ins->dreg = mono_alloc_freg (cfg);
2076                 ins->sreg1 = tree->dreg;
2077                 MONO_ADD_INS (cfg->cbb, ins);
2078
2079                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2080                 break;
2081         case ArgInDoubleSSEReg:
2082                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2083                 ins->dreg = mono_alloc_freg (cfg);
2084                 ins->sreg1 = tree->dreg;
2085                 MONO_ADD_INS (cfg->cbb, ins);
2086
2087                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2088
2089                 break;
2090         default:
2091                 g_assert_not_reached ();
2092         }
2093 }
2094
2095 static int
2096 arg_storage_to_load_membase (ArgStorage storage)
2097 {
2098         switch (storage) {
2099         case ArgInIReg:
2100 #if defined(__mono_ilp32__)
2101                 return OP_LOADI8_MEMBASE;
2102 #else
2103                 return OP_LOAD_MEMBASE;
2104 #endif
2105         case ArgInDoubleSSEReg:
2106                 return OP_LOADR8_MEMBASE;
2107         case ArgInFloatSSEReg:
2108                 return OP_LOADR4_MEMBASE;
2109         default:
2110                 g_assert_not_reached ();
2111         }
2112
2113         return -1;
2114 }
2115
2116 static void
2117 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2118 {
2119         MonoMethodSignature *tmp_sig;
2120         int sig_reg;
2121
2122         if (call->tail_call)
2123                 NOT_IMPLEMENTED;
2124
2125         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2126
2127         /*
2128          * mono_ArgIterator_Setup assumes the signature cookie is
2129          * passed first and all the arguments which were before it are
2130          * passed on the stack after the signature. So compensate by
2131          * passing a different signature.
2132          */
2133         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2134         tmp_sig->param_count -= call->signature->sentinelpos;
2135         tmp_sig->sentinelpos = 0;
2136         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2137
2138         sig_reg = mono_alloc_ireg (cfg);
2139         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2140
2141         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2142 }
2143
2144 static inline LLVMArgStorage
2145 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2146 {
2147         switch (storage) {
2148         case ArgInIReg:
2149                 return LLVMArgInIReg;
2150         case ArgNone:
2151                 return LLVMArgNone;
2152         default:
2153                 g_assert_not_reached ();
2154                 return LLVMArgNone;
2155         }
2156 }
2157
2158 #ifdef ENABLE_LLVM
2159 LLVMCallInfo*
2160 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2161 {
2162         int i, n;
2163         CallInfo *cinfo;
2164         ArgInfo *ainfo;
2165         int j;
2166         LLVMCallInfo *linfo;
2167         MonoType *t, *sig_ret;
2168
2169         n = sig->param_count + sig->hasthis;
2170         sig_ret = mini_replace_type (sig->ret);
2171
2172         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2173
2174         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2175
2176         /*
2177          * LLVM always uses the native ABI while we use our own ABI, the
2178          * only difference is the handling of vtypes:
2179          * - we only pass/receive them in registers in some cases, and only
2180          *   in 1 or 2 integer registers.
2181          */
2182         if (cinfo->ret.storage == ArgValuetypeInReg) {
2183                 if (sig->pinvoke) {
2184                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2185                         cfg->disable_llvm = TRUE;
2186                         return linfo;
2187                 }
2188
2189                 linfo->ret.storage = LLVMArgVtypeInReg;
2190                 for (j = 0; j < 2; ++j)
2191                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2192         }
2193
2194         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2195                 /* Vtype returned using a hidden argument */
2196                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2197                 linfo->vret_arg_index = cinfo->vret_arg_index;
2198         }
2199
2200         for (i = 0; i < n; ++i) {
2201                 ainfo = cinfo->args + i;
2202
2203                 if (i >= sig->hasthis)
2204                         t = sig->params [i - sig->hasthis];
2205                 else
2206                         t = &mono_defaults.int_class->byval_arg;
2207
2208                 linfo->args [i].storage = LLVMArgNone;
2209
2210                 switch (ainfo->storage) {
2211                 case ArgInIReg:
2212                         linfo->args [i].storage = LLVMArgInIReg;
2213                         break;
2214                 case ArgInDoubleSSEReg:
2215                 case ArgInFloatSSEReg:
2216                         linfo->args [i].storage = LLVMArgInFPReg;
2217                         break;
2218                 case ArgOnStack:
2219                         if (MONO_TYPE_ISSTRUCT (t)) {
2220                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2221                         } else {
2222                                 linfo->args [i].storage = LLVMArgInIReg;
2223                                 if (!t->byref) {
2224                                         if (t->type == MONO_TYPE_R4)
2225                                                 linfo->args [i].storage = LLVMArgInFPReg;
2226                                         else if (t->type == MONO_TYPE_R8)
2227                                                 linfo->args [i].storage = LLVMArgInFPReg;
2228                                 }
2229                         }
2230                         break;
2231                 case ArgValuetypeInReg:
2232                         if (sig->pinvoke) {
2233                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2234                                 cfg->disable_llvm = TRUE;
2235                                 return linfo;
2236                         }
2237
2238                         linfo->args [i].storage = LLVMArgVtypeInReg;
2239                         for (j = 0; j < 2; ++j)
2240                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2241                         break;
2242                 default:
2243                         cfg->exception_message = g_strdup ("ainfo->storage");
2244                         cfg->disable_llvm = TRUE;
2245                         break;
2246                 }
2247         }
2248
2249         return linfo;
2250 }
2251 #endif
2252
2253 void
2254 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2255 {
2256         MonoInst *arg, *in;
2257         MonoMethodSignature *sig;
2258         MonoType *sig_ret;
2259         int i, n, stack_size;
2260         CallInfo *cinfo;
2261         ArgInfo *ainfo;
2262
2263         stack_size = 0;
2264
2265         sig = call->signature;
2266         n = sig->param_count + sig->hasthis;
2267
2268         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2269
2270         sig_ret = sig->ret;
2271
2272         if (COMPILE_LLVM (cfg)) {
2273                 /* We shouldn't be called in the llvm case */
2274                 cfg->disable_llvm = TRUE;
2275                 return;
2276         }
2277
2278         /*
2279          * Emit all arguments which are passed on the stack to prevent register
2280          * allocation problems.
2281          */
2282         for (i = 0; i < n; ++i) {
2283                 MonoType *t;
2284                 ainfo = cinfo->args + i;
2285
2286                 in = call->args [i];
2287
2288                 if (sig->hasthis && i == 0)
2289                         t = &mono_defaults.object_class->byval_arg;
2290                 else
2291                         t = sig->params [i - sig->hasthis];
2292
2293                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2294                         if (!t->byref) {
2295                                 if (t->type == MONO_TYPE_R4)
2296                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                 else if (t->type == MONO_TYPE_R8)
2298                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 else
2300                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                         } else {
2302                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                         }
2304                         if (cfg->compute_gc_maps) {
2305                                 MonoInst *def;
2306
2307                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2308                         }
2309                 }
2310         }
2311
2312         /*
2313          * Emit all parameters passed in registers in non-reverse order for better readability
2314          * and to help the optimization in emit_prolog ().
2315          */
2316         for (i = 0; i < n; ++i) {
2317                 ainfo = cinfo->args + i;
2318
2319                 in = call->args [i];
2320
2321                 if (ainfo->storage == ArgInIReg)
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323         }
2324
2325         for (i = n - 1; i >= 0; --i) {
2326                 ainfo = cinfo->args + i;
2327
2328                 in = call->args [i];
2329
2330                 switch (ainfo->storage) {
2331                 case ArgInIReg:
2332                         /* Already done */
2333                         break;
2334                 case ArgInFloatSSEReg:
2335                 case ArgInDoubleSSEReg:
2336                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2337                         break;
2338                 case ArgOnStack:
2339                 case ArgValuetypeInReg:
2340                 case ArgValuetypeAddrInIReg:
2341                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2342                                 MonoInst *call_inst = (MonoInst*)call;
2343                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2344                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2345                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2346                                 guint32 align;
2347                                 guint32 size;
2348
2349                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2350                                         size = sizeof (MonoTypedRef);
2351                                         align = sizeof (gpointer);
2352                                 }
2353                                 else {
2354                                         if (sig->pinvoke)
2355                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2356                                         else {
2357                                                 /*
2358                                                  * Other backends use mono_type_stack_size (), but that
2359                                                  * aligns the size to 8, which is larger than the size of
2360                                                  * the source, leading to reads of invalid memory if the
2361                                                  * source is at the end of address space.
2362                                                  */
2363                                                 size = mono_class_value_size (in->klass, &align);
2364                                         }
2365                                 }
2366                                 g_assert (in->klass);
2367
2368                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2369                                         /* Avoid asserts in emit_memcpy () */
2370                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2371                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2372                                         /* Continue normally */
2373                                 }
2374
2375                                 if (size > 0) {
2376                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2377                                         arg->sreg1 = in->dreg;
2378                                         arg->klass = in->klass;
2379                                         arg->backend.size = size;
2380                                         arg->inst_p0 = call;
2381                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2383
2384                                         MONO_ADD_INS (cfg->cbb, arg);
2385                                 }
2386                         }
2387                         break;
2388                 default:
2389                         g_assert_not_reached ();
2390                 }
2391
2392                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2393                         /* Emit the signature cookie just before the implicit arguments */
2394                         emit_sig_cookie (cfg, call, cinfo);
2395         }
2396
2397         /* Handle the case where there are no implicit arguments */
2398         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2399                 emit_sig_cookie (cfg, call, cinfo);
2400
2401         sig_ret = mini_replace_type (sig->ret);
2402         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2403                 MonoInst *vtarg;
2404
2405                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2406                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2407                                 /*
2408                                  * Tell the JIT to use a more efficient calling convention: call using
2409                                  * OP_CALL, compute the result location after the call, and save the
2410                                  * result there.
2411                                  */
2412                                 call->vret_in_reg = TRUE;
2413                                 /*
2414                                  * Nullify the instruction computing the vret addr to enable
2415                                  * future optimizations.
2416                                  */
2417                                 if (call->vret_var)
2418                                         NULLIFY_INS (call->vret_var);
2419                         } else {
2420                                 if (call->tail_call)
2421                                         NOT_IMPLEMENTED;
2422                                 /*
2423                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2424                                  * the stack. Push the address here, so the call instruction can
2425                                  * access it.
2426                                  */
2427                                 if (!cfg->arch.vret_addr_loc) {
2428                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2429                                         /* Prevent it from being register allocated or optimized away */
2430                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2431                                 }
2432
2433                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2434                         }
2435                 }
2436                 else {
2437                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2438                         vtarg->sreg1 = call->vret_var->dreg;
2439                         vtarg->dreg = mono_alloc_preg (cfg);
2440                         MONO_ADD_INS (cfg->cbb, vtarg);
2441
2442                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2443                 }
2444         }
2445
2446         if (cfg->method->save_lmf) {
2447                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2448                 MONO_ADD_INS (cfg->cbb, arg);
2449         }
2450
2451         call->stack_usage = cinfo->stack_usage;
2452 }
2453
2454 void
2455 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2456 {
2457         MonoInst *arg;
2458         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2460         int size = ins->backend.size;
2461
2462         if (ainfo->storage == ArgValuetypeInReg) {
2463                 MonoInst *load;
2464                 int part;
2465
2466                 for (part = 0; part < 2; ++part) {
2467                         if (ainfo->pair_storage [part] == ArgNone)
2468                                 continue;
2469
2470                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2471                         load->inst_basereg = src->dreg;
2472                         load->inst_offset = part * sizeof(mgreg_t);
2473
2474                         switch (ainfo->pair_storage [part]) {
2475                         case ArgInIReg:
2476                                 load->dreg = mono_alloc_ireg (cfg);
2477                                 break;
2478                         case ArgInDoubleSSEReg:
2479                         case ArgInFloatSSEReg:
2480                                 load->dreg = mono_alloc_freg (cfg);
2481                                 break;
2482                         default:
2483                                 g_assert_not_reached ();
2484                         }
2485                         MONO_ADD_INS (cfg->cbb, load);
2486
2487                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2488                 }
2489         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2490                 MonoInst *vtaddr, *load;
2491                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2492
2493                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2494                 cfg->has_indirection = TRUE;
2495                 load->inst_p0 = vtaddr;
2496                 vtaddr->flags |= MONO_INST_INDIRECT;
2497                 load->type = STACK_MP;
2498                 load->klass = vtaddr->klass;
2499                 load->dreg = mono_alloc_ireg (cfg);
2500                 MONO_ADD_INS (cfg->cbb, load);
2501                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2502
2503                 if (ainfo->pair_storage [0] == ArgInIReg) {
2504                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2505                         arg->dreg = mono_alloc_ireg (cfg);
2506                         arg->sreg1 = load->dreg;
2507                         arg->inst_imm = 0;
2508                         MONO_ADD_INS (cfg->cbb, arg);
2509                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2510                 } else {
2511                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2512                 }
2513         } else {
2514                 if (size == 8) {
2515                         int dreg = mono_alloc_ireg (cfg);
2516
2517                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2518                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2519                 } else if (size <= 40) {
2520                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2521                 } else {
2522                         // FIXME: Code growth
2523                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2524                 }
2525
2526                 if (cfg->compute_gc_maps) {
2527                         MonoInst *def;
2528                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2529                 }
2530         }
2531 }
2532
2533 void
2534 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2535 {
2536         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2537
2538         if (ret->type == MONO_TYPE_R4) {
2539                 if (COMPILE_LLVM (cfg))
2540                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2541                 else
2542                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2543                 return;
2544         } else if (ret->type == MONO_TYPE_R8) {
2545                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2546                 return;
2547         }
2548
2549         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2550 }
2551
2552 #endif /* DISABLE_JIT */
2553
2554 #define EMIT_COND_BRANCH(ins,cond,sign) \
2555         if (ins->inst_true_bb->native_offset) { \
2556                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2557         } else { \
2558                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2559                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2560             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2561                         x86_branch8 (code, cond, 0, sign); \
2562                 else \
2563                         x86_branch32 (code, cond, 0, sign); \
2564 }
2565
2566 typedef struct {
2567         MonoMethodSignature *sig;
2568         CallInfo *cinfo;
2569 } ArchDynCallInfo;
2570
2571 static gboolean
2572 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2573 {
2574         int i;
2575
2576 #ifdef HOST_WIN32
2577         return FALSE;
2578 #endif
2579
2580         switch (cinfo->ret.storage) {
2581         case ArgNone:
2582         case ArgInIReg:
2583                 break;
2584         case ArgValuetypeInReg: {
2585                 ArgInfo *ainfo = &cinfo->ret;
2586
2587                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2588                         return FALSE;
2589                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2590                         return FALSE;
2591                 break;
2592         }
2593         default:
2594                 return FALSE;
2595         }
2596
2597         for (i = 0; i < cinfo->nargs; ++i) {
2598                 ArgInfo *ainfo = &cinfo->args [i];
2599                 switch (ainfo->storage) {
2600                 case ArgInIReg:
2601                         break;
2602                 case ArgValuetypeInReg:
2603                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2604                                 return FALSE;
2605                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2606                                 return FALSE;
2607                         break;
2608                 default:
2609                         return FALSE;
2610                 }
2611         }
2612
2613         return TRUE;
2614 }
2615
2616 /*
2617  * mono_arch_dyn_call_prepare:
2618  *
2619  *   Return a pointer to an arch-specific structure which contains information
2620  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2621  * supported for SIG.
2622  * This function is equivalent to ffi_prep_cif in libffi.
2623  */
2624 MonoDynCallInfo*
2625 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2626 {
2627         ArchDynCallInfo *info;
2628         CallInfo *cinfo;
2629
2630         cinfo = get_call_info (NULL, NULL, sig);
2631
2632         if (!dyn_call_supported (sig, cinfo)) {
2633                 g_free (cinfo);
2634                 return NULL;
2635         }
2636
2637         info = g_new0 (ArchDynCallInfo, 1);
2638         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2639         info->sig = sig;
2640         info->cinfo = cinfo;
2641
2642         return (MonoDynCallInfo*)info;
2643 }
2644
2645 /*
2646  * mono_arch_dyn_call_free:
2647  *
2648  *   Free a MonoDynCallInfo structure.
2649  */
2650 void
2651 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2652 {
2653         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2654
2655         g_free (ainfo->cinfo);
2656         g_free (ainfo);
2657 }
2658
2659 #if !defined(__native_client__)
2660 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2661 #define GREG_TO_PTR(greg) (gpointer)(greg)
2662 #else
2663 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2664 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2665 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2666 #endif
2667
2668 /*
2669  * mono_arch_get_start_dyn_call:
2670  *
2671  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2672  * store the result into BUF.
2673  * ARGS should be an array of pointers pointing to the arguments.
2674  * RET should point to a memory buffer large enought to hold the result of the
2675  * call.
2676  * This function should be as fast as possible, any work which does not depend
2677  * on the actual values of the arguments should be done in
2678  * mono_arch_dyn_call_prepare ().
2679  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2680  * libffi.
2681  */
2682 void
2683 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2684 {
2685         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2686         DynCallArgs *p = (DynCallArgs*)buf;
2687         int arg_index, greg, i, pindex;
2688         MonoMethodSignature *sig = dinfo->sig;
2689
2690         g_assert (buf_len >= sizeof (DynCallArgs));
2691
2692         p->res = 0;
2693         p->ret = ret;
2694
2695         arg_index = 0;
2696         greg = 0;
2697         pindex = 0;
2698
2699         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2700                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2701                 if (!sig->hasthis)
2702                         pindex = 1;
2703         }
2704
2705         if (dinfo->cinfo->vtype_retaddr)
2706                 p->regs [greg ++] = PTR_TO_GREG(ret);
2707
2708         for (i = pindex; i < sig->param_count; i++) {
2709                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2710                 gpointer *arg = args [arg_index ++];
2711
2712                 if (t->byref) {
2713                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2714                         continue;
2715                 }
2716
2717                 switch (t->type) {
2718                 case MONO_TYPE_STRING:
2719                 case MONO_TYPE_CLASS:
2720                 case MONO_TYPE_ARRAY:
2721                 case MONO_TYPE_SZARRAY:
2722                 case MONO_TYPE_OBJECT:
2723                 case MONO_TYPE_PTR:
2724                 case MONO_TYPE_I:
2725                 case MONO_TYPE_U:
2726 #if !defined(__mono_ilp32__)
2727                 case MONO_TYPE_I8:
2728                 case MONO_TYPE_U8:
2729 #endif
2730                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2731                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2732                         break;
2733 #if defined(__mono_ilp32__)
2734                 case MONO_TYPE_I8:
2735                 case MONO_TYPE_U8:
2736                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2737                         p->regs [greg ++] = *(guint64*)(arg);
2738                         break;
2739 #endif
2740                 case MONO_TYPE_BOOLEAN:
2741                 case MONO_TYPE_U1:
2742                         p->regs [greg ++] = *(guint8*)(arg);
2743                         break;
2744                 case MONO_TYPE_I1:
2745                         p->regs [greg ++] = *(gint8*)(arg);
2746                         break;
2747                 case MONO_TYPE_I2:
2748                         p->regs [greg ++] = *(gint16*)(arg);
2749                         break;
2750                 case MONO_TYPE_U2:
2751                 case MONO_TYPE_CHAR:
2752                         p->regs [greg ++] = *(guint16*)(arg);
2753                         break;
2754                 case MONO_TYPE_I4:
2755                         p->regs [greg ++] = *(gint32*)(arg);
2756                         break;
2757                 case MONO_TYPE_U4:
2758                         p->regs [greg ++] = *(guint32*)(arg);
2759                         break;
2760                 case MONO_TYPE_GENERICINST:
2761                     if (MONO_TYPE_IS_REFERENCE (t)) {
2762                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2763                                 break;
2764                         } else {
2765                                 /* Fall through */
2766                         }
2767                 case MONO_TYPE_VALUETYPE: {
2768                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2769
2770                         g_assert (ainfo->storage == ArgValuetypeInReg);
2771                         if (ainfo->pair_storage [0] != ArgNone) {
2772                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2773                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2774                         }
2775                         if (ainfo->pair_storage [1] != ArgNone) {
2776                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2777                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2778                         }
2779                         break;
2780                 }
2781                 default:
2782                         g_assert_not_reached ();
2783                 }
2784         }
2785
2786         g_assert (greg <= PARAM_REGS);
2787 }
2788
2789 /*
2790  * mono_arch_finish_dyn_call:
2791  *
2792  *   Store the result of a dyn call into the return value buffer passed to
2793  * start_dyn_call ().
2794  * This function should be as fast as possible, any work which does not depend
2795  * on the actual values of the arguments should be done in
2796  * mono_arch_dyn_call_prepare ().
2797  */
2798 void
2799 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2800 {
2801         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2802         MonoMethodSignature *sig = dinfo->sig;
2803         guint8 *ret = ((DynCallArgs*)buf)->ret;
2804         mgreg_t res = ((DynCallArgs*)buf)->res;
2805         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2806
2807         switch (sig_ret->type) {
2808         case MONO_TYPE_VOID:
2809                 *(gpointer*)ret = NULL;
2810                 break;
2811         case MONO_TYPE_STRING:
2812         case MONO_TYPE_CLASS:
2813         case MONO_TYPE_ARRAY:
2814         case MONO_TYPE_SZARRAY:
2815         case MONO_TYPE_OBJECT:
2816         case MONO_TYPE_I:
2817         case MONO_TYPE_U:
2818         case MONO_TYPE_PTR:
2819                 *(gpointer*)ret = GREG_TO_PTR(res);
2820                 break;
2821         case MONO_TYPE_I1:
2822                 *(gint8*)ret = res;
2823                 break;
2824         case MONO_TYPE_U1:
2825         case MONO_TYPE_BOOLEAN:
2826                 *(guint8*)ret = res;
2827                 break;
2828         case MONO_TYPE_I2:
2829                 *(gint16*)ret = res;
2830                 break;
2831         case MONO_TYPE_U2:
2832         case MONO_TYPE_CHAR:
2833                 *(guint16*)ret = res;
2834                 break;
2835         case MONO_TYPE_I4:
2836                 *(gint32*)ret = res;
2837                 break;
2838         case MONO_TYPE_U4:
2839                 *(guint32*)ret = res;
2840                 break;
2841         case MONO_TYPE_I8:
2842                 *(gint64*)ret = res;
2843                 break;
2844         case MONO_TYPE_U8:
2845                 *(guint64*)ret = res;
2846                 break;
2847         case MONO_TYPE_GENERICINST:
2848                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2849                         *(gpointer*)ret = GREG_TO_PTR(res);
2850                         break;
2851                 } else {
2852                         /* Fall through */
2853                 }
2854         case MONO_TYPE_VALUETYPE:
2855                 if (dinfo->cinfo->vtype_retaddr) {
2856                         /* Nothing to do */
2857                 } else {
2858                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2859
2860                         g_assert (ainfo->storage == ArgValuetypeInReg);
2861
2862                         if (ainfo->pair_storage [0] != ArgNone) {
2863                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2864                                 ((mgreg_t*)ret)[0] = res;
2865                         }
2866
2867                         g_assert (ainfo->pair_storage [1] == ArgNone);
2868                 }
2869                 break;
2870         default:
2871                 g_assert_not_reached ();
2872         }
2873 }
2874
2875 /* emit an exception if condition is fail */
2876 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2877         do {                                                        \
2878                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2879                 if (tins == NULL) {                                                                             \
2880                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2881                                         MONO_PATCH_INFO_EXC, exc_name);  \
2882                         x86_branch32 (code, cond, 0, signed);               \
2883                 } else {        \
2884                         EMIT_COND_BRANCH (tins, cond, signed);  \
2885                 }                       \
2886         } while (0);
2887
2888 #define EMIT_FPCOMPARE(code) do { \
2889         amd64_fcompp (code); \
2890         amd64_fnstsw (code); \
2891 } while (0);
2892
2893 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2894     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2895         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2896         amd64_ ##op (code); \
2897         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2898         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2899 } while (0);
2900
2901 static guint8*
2902 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2903 {
2904         gboolean no_patch = FALSE;
2905
2906         /*
2907          * FIXME: Add support for thunks
2908          */
2909         {
2910                 gboolean near_call = FALSE;
2911
2912                 /*
2913                  * Indirect calls are expensive so try to make a near call if possible.
2914                  * The caller memory is allocated by the code manager so it is
2915                  * guaranteed to be at a 32 bit offset.
2916                  */
2917
2918                 if (patch_type != MONO_PATCH_INFO_ABS) {
2919                         /* The target is in memory allocated using the code manager */
2920                         near_call = TRUE;
2921
2922                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2923                                 if (((MonoMethod*)data)->klass->image->aot_module)
2924                                         /* The callee might be an AOT method */
2925                                         near_call = FALSE;
2926                                 if (((MonoMethod*)data)->dynamic)
2927                                         /* The target is in malloc-ed memory */
2928                                         near_call = FALSE;
2929                         }
2930
2931                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2932                                 /*
2933                                  * The call might go directly to a native function without
2934                                  * the wrapper.
2935                                  */
2936                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2937                                 if (mi) {
2938                                         gconstpointer target = mono_icall_get_wrapper (mi);
2939                                         if ((((guint64)target) >> 32) != 0)
2940                                                 near_call = FALSE;
2941                                 }
2942                         }
2943                 }
2944                 else {
2945                         MonoJumpInfo *jinfo = NULL;
2946
2947                         if (cfg->abs_patches)
2948                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2949                         if (jinfo) {
2950                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2951                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2952                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2953                                                 near_call = TRUE;
2954                                         no_patch = TRUE;
2955                                 } else {
2956                                         /*
2957                                          * This is not really an optimization, but required because the
2958                                          * generic class init trampolines use R11 to pass the vtable.
2959                                          */
2960                                         near_call = TRUE;
2961                                 }
2962                         } else {
2963                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2964                                 if (info) {
2965                                         if (info->func == info->wrapper) {
2966                                                 /* No wrapper */
2967                                                 if ((((guint64)info->func) >> 32) == 0)
2968                                                         near_call = TRUE;
2969                                         }
2970                                         else {
2971                                                 /* See the comment in mono_codegen () */
2972                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2973                                                         near_call = TRUE;
2974                                         }
2975                                 }
2976                                 else if ((((guint64)data) >> 32) == 0) {
2977                                         near_call = TRUE;
2978                                         no_patch = TRUE;
2979                                 }
2980                         }
2981                 }
2982
2983                 if (cfg->method->dynamic)
2984                         /* These methods are allocated using malloc */
2985                         near_call = FALSE;
2986
2987 #ifdef MONO_ARCH_NOMAP32BIT
2988                 near_call = FALSE;
2989 #endif
2990 #if defined(__native_client__)
2991                 /* Always use near_call == TRUE for Native Client */
2992                 near_call = TRUE;
2993 #endif
2994                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2995                 if (optimize_for_xen)
2996                         near_call = FALSE;
2997
2998                 if (cfg->compile_aot) {
2999                         near_call = TRUE;
3000                         no_patch = TRUE;
3001                 }
3002
3003                 if (near_call) {
3004                         /*
3005                          * Align the call displacement to an address divisible by 4 so it does
3006                          * not span cache lines. This is required for code patching to work on SMP
3007                          * systems.
3008                          */
3009                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3010                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3011                                 amd64_padding (code, pad_size);
3012                         }
3013                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3014                         amd64_call_code (code, 0);
3015                 }
3016                 else {
3017                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3018                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3019                         amd64_call_reg (code, GP_SCRATCH_REG);
3020                 }
3021         }
3022
3023         return code;
3024 }
3025
3026 static inline guint8*
3027 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3028 {
3029 #ifdef HOST_WIN32
3030         if (win64_adjust_stack)
3031                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3032 #endif
3033         code = emit_call_body (cfg, code, patch_type, data);
3034 #ifdef HOST_WIN32
3035         if (win64_adjust_stack)
3036                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3037 #endif
3038
3039         return code;
3040 }
3041
3042 static inline int
3043 store_membase_imm_to_store_membase_reg (int opcode)
3044 {
3045         switch (opcode) {
3046         case OP_STORE_MEMBASE_IMM:
3047                 return OP_STORE_MEMBASE_REG;
3048         case OP_STOREI4_MEMBASE_IMM:
3049                 return OP_STOREI4_MEMBASE_REG;
3050         case OP_STOREI8_MEMBASE_IMM:
3051                 return OP_STOREI8_MEMBASE_REG;
3052         }
3053
3054         return -1;
3055 }
3056
3057 #ifndef DISABLE_JIT
3058
3059 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3060
3061 /*
3062  * mono_arch_peephole_pass_1:
3063  *
3064  *   Perform peephole opts which should/can be performed before local regalloc
3065  */
3066 void
3067 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3068 {
3069         MonoInst *ins, *n;
3070
3071         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3072                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3073
3074                 switch (ins->opcode) {
3075                 case OP_ADD_IMM:
3076                 case OP_IADD_IMM:
3077                 case OP_LADD_IMM:
3078                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3079                                 /*
3080                                  * X86_LEA is like ADD, but doesn't have the
3081                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3082                                  * its operand to 64 bit.
3083                                  */
3084                                 ins->opcode = OP_X86_LEA_MEMBASE;
3085                                 ins->inst_basereg = ins->sreg1;
3086                         }
3087                         break;
3088                 case OP_LXOR:
3089                 case OP_IXOR:
3090                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3091                                 MonoInst *ins2;
3092
3093                                 /*
3094                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3095                                  * the latter has length 2-3 instead of 6 (reverse constant
3096                                  * propagation). These instruction sequences are very common
3097                                  * in the initlocals bblock.
3098                                  */
3099                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3100                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3101                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3102                                                 ins2->sreg1 = ins->dreg;
3103                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3104                                                 /* Continue */
3105                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3106                                                 NULLIFY_INS (ins2);
3107                                                 /* Continue */
3108                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3109                                                 /* Continue */
3110                                         } else {
3111                                                 break;
3112                                         }
3113                                 }
3114                         }
3115                         break;
3116                 case OP_COMPARE_IMM:
3117                 case OP_LCOMPARE_IMM:
3118                         /* OP_COMPARE_IMM (reg, 0)
3119                          * -->
3120                          * OP_AMD64_TEST_NULL (reg)
3121                          */
3122                         if (!ins->inst_imm)
3123                                 ins->opcode = OP_AMD64_TEST_NULL;
3124                         break;
3125                 case OP_ICOMPARE_IMM:
3126                         if (!ins->inst_imm)
3127                                 ins->opcode = OP_X86_TEST_NULL;
3128                         break;
3129                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3130                         /*
3131                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3132                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3133                          * -->
3134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3135                          * OP_COMPARE_IMM reg, imm
3136                          *
3137                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3138                          */
3139                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3140                             ins->inst_basereg == last_ins->inst_destbasereg &&
3141                             ins->inst_offset == last_ins->inst_offset) {
3142                                         ins->opcode = OP_ICOMPARE_IMM;
3143                                         ins->sreg1 = last_ins->sreg1;
3144
3145                                         /* check if we can remove cmp reg,0 with test null */
3146                                         if (!ins->inst_imm)
3147                                                 ins->opcode = OP_X86_TEST_NULL;
3148                                 }
3149
3150                         break;
3151                 }
3152
3153                 mono_peephole_ins (bb, ins);
3154         }
3155 }
3156
3157 void
3158 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3159 {
3160         MonoInst *ins, *n;
3161
3162         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163                 switch (ins->opcode) {
3164                 case OP_ICONST:
3165                 case OP_I8CONST: {
3166                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3167                         /* reg = 0 -> XOR (reg, reg) */
3168                         /* XOR sets cflags on x86, so we cant do it always */
3169                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3170                                 ins->opcode = OP_LXOR;
3171                                 ins->sreg1 = ins->dreg;
3172                                 ins->sreg2 = ins->dreg;
3173                                 /* Fall through */
3174                         } else {
3175                                 break;
3176                         }
3177                 }
3178                 case OP_LXOR:
3179                         /*
3180                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3181                          * 0 result into 64 bits.
3182                          */
3183                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3184                                 ins->opcode = OP_IXOR;
3185                         }
3186                         /* Fall through */
3187                 case OP_IXOR:
3188                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3189                                 MonoInst *ins2;
3190
3191                                 /*
3192                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3193                                  * the latter has length 2-3 instead of 6 (reverse constant
3194                                  * propagation). These instruction sequences are very common
3195                                  * in the initlocals bblock.
3196                                  */
3197                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3198                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3199                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3200                                                 ins2->sreg1 = ins->dreg;
3201                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3202                                                 /* Continue */
3203                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3204                                                 NULLIFY_INS (ins2);
3205                                                 /* Continue */
3206                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3207                                                 /* Continue */
3208                                         } else {
3209                                                 break;
3210                                         }
3211                                 }
3212                         }
3213                         break;
3214                 case OP_IADD_IMM:
3215                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3216                                 ins->opcode = OP_X86_INC_REG;
3217                         break;
3218                 case OP_ISUB_IMM:
3219                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3220                                 ins->opcode = OP_X86_DEC_REG;
3221                         break;
3222                 }
3223
3224                 mono_peephole_ins (bb, ins);
3225         }
3226 }
3227
3228 #define NEW_INS(cfg,ins,dest,op) do {   \
3229                 MONO_INST_NEW ((cfg), (dest), (op)); \
3230         (dest)->cil_code = (ins)->cil_code; \
3231         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3232         } while (0)
3233
3234 /*
3235  * mono_arch_lowering_pass:
3236  *
3237  *  Converts complex opcodes into simpler ones so that each IR instruction
3238  * corresponds to one machine instruction.
3239  */
3240 void
3241 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3242 {
3243         MonoInst *ins, *n, *temp;
3244
3245         /*
3246          * FIXME: Need to add more instructions, but the current machine
3247          * description can't model some parts of the composite instructions like
3248          * cdq.
3249          */
3250         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3251                 switch (ins->opcode) {
3252                 case OP_DIV_IMM:
3253                 case OP_REM_IMM:
3254                 case OP_IDIV_IMM:
3255                 case OP_IDIV_UN_IMM:
3256                 case OP_IREM_UN_IMM:
3257                 case OP_LREM_IMM:
3258                 case OP_IREM_IMM:
3259                         mono_decompose_op_imm (cfg, bb, ins);
3260                         break;
3261                 case OP_COMPARE_IMM:
3262                 case OP_LCOMPARE_IMM:
3263                         if (!amd64_is_imm32 (ins->inst_imm)) {
3264                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3265                                 temp->inst_c0 = ins->inst_imm;
3266                                 temp->dreg = mono_alloc_ireg (cfg);
3267                                 ins->opcode = OP_COMPARE;
3268                                 ins->sreg2 = temp->dreg;
3269                         }
3270                         break;
3271 #ifndef __mono_ilp32__
3272                 case OP_LOAD_MEMBASE:
3273 #endif
3274                 case OP_LOADI8_MEMBASE:
3275 #ifndef __native_client_codegen__
3276                 /*  Don't generate memindex opcodes (to simplify */
3277                 /*  read sandboxing) */
3278                         if (!amd64_is_imm32 (ins->inst_offset)) {
3279                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3280                                 temp->inst_c0 = ins->inst_offset;
3281                                 temp->dreg = mono_alloc_ireg (cfg);
3282                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3283                                 ins->inst_indexreg = temp->dreg;
3284                         }
3285 #endif
3286                         break;
3287 #ifndef __mono_ilp32__
3288                 case OP_STORE_MEMBASE_IMM:
3289 #endif
3290                 case OP_STOREI8_MEMBASE_IMM:
3291                         if (!amd64_is_imm32 (ins->inst_imm)) {
3292                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3293                                 temp->inst_c0 = ins->inst_imm;
3294                                 temp->dreg = mono_alloc_ireg (cfg);
3295                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3296                                 ins->sreg1 = temp->dreg;
3297                         }
3298                         break;
3299 #ifdef MONO_ARCH_SIMD_INTRINSICS
3300                 case OP_EXPAND_I1: {
3301                                 int temp_reg1 = mono_alloc_ireg (cfg);
3302                                 int temp_reg2 = mono_alloc_ireg (cfg);
3303                                 int original_reg = ins->sreg1;
3304
3305                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3306                                 temp->sreg1 = original_reg;
3307                                 temp->dreg = temp_reg1;
3308
3309                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3310                                 temp->sreg1 = temp_reg1;
3311                                 temp->dreg = temp_reg2;
3312                                 temp->inst_imm = 8;
3313
3314                                 NEW_INS (cfg, ins, temp, OP_LOR);
3315                                 temp->sreg1 = temp->dreg = temp_reg2;
3316                                 temp->sreg2 = temp_reg1;
3317
3318                                 ins->opcode = OP_EXPAND_I2;
3319                                 ins->sreg1 = temp_reg2;
3320                         }
3321                         break;
3322 #endif
3323                 default:
3324                         break;
3325                 }
3326         }
3327
3328         bb->max_vreg = cfg->next_vreg;
3329 }
3330
3331 static const int
3332 branch_cc_table [] = {
3333         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3334         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3335         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3336 };
3337
3338 /* Maps CMP_... constants to X86_CC_... constants */
3339 static const int
3340 cc_table [] = {
3341         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3342         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3343 };
3344
3345 static const int
3346 cc_signed_table [] = {
3347         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3348         FALSE, FALSE, FALSE, FALSE
3349 };
3350
3351 /*#include "cprop.c"*/
3352
3353 static unsigned char*
3354 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3355 {
3356         if (size == 8)
3357                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3358         else
3359                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3360
3361         if (size == 1)
3362                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3363         else if (size == 2)
3364                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3365         return code;
3366 }
3367
3368 static unsigned char*
3369 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3370 {
3371         int sreg = tree->sreg1;
3372         int need_touch = FALSE;
3373
3374 #if defined(HOST_WIN32)
3375         need_touch = TRUE;
3376 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3377         if (!tree->flags & MONO_INST_INIT)
3378                 need_touch = TRUE;
3379 #endif
3380
3381         if (need_touch) {
3382                 guint8* br[5];
3383
3384                 /*
3385                  * Under Windows:
3386                  * If requested stack size is larger than one page,
3387                  * perform stack-touch operation
3388                  */
3389                 /*
3390                  * Generate stack probe code.
3391                  * Under Windows, it is necessary to allocate one page at a time,
3392                  * "touching" stack after each successful sub-allocation. This is
3393                  * because of the way stack growth is implemented - there is a
3394                  * guard page before the lowest stack page that is currently commited.
3395                  * Stack normally grows sequentially so OS traps access to the
3396                  * guard page and commits more pages when needed.
3397                  */
3398                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3399                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3400
3401                 br[2] = code; /* loop */
3402                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3403                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3404                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3405                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3406                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3407                 amd64_patch (br[3], br[2]);
3408                 amd64_test_reg_reg (code, sreg, sreg);
3409                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3410                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3411
3412                 br[1] = code; x86_jump8 (code, 0);
3413
3414                 amd64_patch (br[0], code);
3415                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3416                 amd64_patch (br[1], code);
3417                 amd64_patch (br[4], code);
3418         }
3419         else
3420                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3421
3422         if (tree->flags & MONO_INST_INIT) {
3423                 int offset = 0;
3424                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3425                         amd64_push_reg (code, AMD64_RAX);
3426                         offset += 8;
3427                 }
3428                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3429                         amd64_push_reg (code, AMD64_RCX);
3430                         offset += 8;
3431                 }
3432                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3433                         amd64_push_reg (code, AMD64_RDI);
3434                         offset += 8;
3435                 }
3436
3437                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3438                 if (sreg != AMD64_RCX)
3439                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3440                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3441
3442                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3443                 if (cfg->param_area)
3444                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3445                 amd64_cld (code);
3446 #if defined(__default_codegen__)
3447                 amd64_prefix (code, X86_REP_PREFIX);
3448                 amd64_stosl (code);
3449 #elif defined(__native_client_codegen__)
3450                 /* NaCl stos pseudo-instruction */
3451                 amd64_codegen_pre(code);
3452                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3453                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3454                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3455                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3456                 amd64_prefix (code, X86_REP_PREFIX);
3457                 amd64_stosl (code);
3458                 amd64_codegen_post(code);
3459 #endif /* __native_client_codegen__ */
3460
3461                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3462                         amd64_pop_reg (code, AMD64_RDI);
3463                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3464                         amd64_pop_reg (code, AMD64_RCX);
3465                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3466                         amd64_pop_reg (code, AMD64_RAX);
3467         }
3468         return code;
3469 }
3470
3471 static guint8*
3472 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3473 {
3474         CallInfo *cinfo;
3475         guint32 quad;
3476
3477         /* Move return value to the target register */
3478         /* FIXME: do this in the local reg allocator */
3479         switch (ins->opcode) {
3480         case OP_CALL:
3481         case OP_CALL_REG:
3482         case OP_CALL_MEMBASE:
3483         case OP_LCALL:
3484         case OP_LCALL_REG:
3485         case OP_LCALL_MEMBASE:
3486                 g_assert (ins->dreg == AMD64_RAX);
3487                 break;
3488         case OP_FCALL:
3489         case OP_FCALL_REG:
3490         case OP_FCALL_MEMBASE:
3491                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3492                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3493                 }
3494                 else {
3495                         if (ins->dreg != AMD64_XMM0)
3496                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3497                 }
3498                 break;
3499         case OP_VCALL:
3500         case OP_VCALL_REG:
3501         case OP_VCALL_MEMBASE:
3502         case OP_VCALL2:
3503         case OP_VCALL2_REG:
3504         case OP_VCALL2_MEMBASE:
3505                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3506                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3507                         MonoInst *loc = cfg->arch.vret_addr_loc;
3508
3509                         /* Load the destination address */
3510                         g_assert (loc->opcode == OP_REGOFFSET);
3511                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3512
3513                         for (quad = 0; quad < 2; quad ++) {
3514                                 switch (cinfo->ret.pair_storage [quad]) {
3515                                 case ArgInIReg:
3516                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3517                                         break;
3518                                 case ArgInFloatSSEReg:
3519                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3520                                         break;
3521                                 case ArgInDoubleSSEReg:
3522                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3523                                         break;
3524                                 case ArgNone:
3525                                         break;
3526                                 default:
3527                                         NOT_IMPLEMENTED;
3528                                 }
3529                         }
3530                 }
3531                 break;
3532         }
3533
3534         return code;
3535 }
3536
3537 #endif /* DISABLE_JIT */
3538
3539 #ifdef __APPLE__
3540 static int tls_gs_offset;
3541 #endif
3542
3543 gboolean
3544 mono_amd64_have_tls_get (void)
3545 {
3546 #ifdef __APPLE__
3547         static gboolean have_tls_get = FALSE;
3548         static gboolean inited = FALSE;
3549         guint8 *ins;
3550
3551         if (inited)
3552                 return have_tls_get;
3553
3554         ins = (guint8*)pthread_getspecific;
3555
3556         /*
3557          * We're looking for these two instructions:
3558          *
3559          * mov    %gs:[offset](,%rdi,8),%rax
3560          * retq
3561          */
3562         have_tls_get = ins [0] == 0x65 &&
3563                        ins [1] == 0x48 &&
3564                        ins [2] == 0x8b &&
3565                        ins [3] == 0x04 &&
3566                        ins [4] == 0xfd &&
3567                        ins [6] == 0x00 &&
3568                        ins [7] == 0x00 &&
3569                        ins [8] == 0x00 &&
3570                        ins [9] == 0xc3;
3571
3572         inited = TRUE;
3573
3574         tls_gs_offset = ins[5];
3575
3576         return have_tls_get;
3577 #elif defined(PLATFORM_ANDROID)
3578         return FALSE;
3579 #else
3580         return TRUE;
3581 #endif
3582 }
3583
3584 int
3585 mono_amd64_get_tls_gs_offset (void)
3586 {
3587 #ifdef TARGET_OSX
3588         return tls_gs_offset;
3589 #else
3590         g_assert_not_reached ();
3591         return -1;
3592 #endif
3593 }
3594
3595 /*
3596  * mono_amd64_emit_tls_get:
3597  * @code: buffer to store code to
3598  * @dreg: hard register where to place the result
3599  * @tls_offset: offset info
3600  *
3601  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3602  * the dreg register the item in the thread local storage identified
3603  * by tls_offset.
3604  *
3605  * Returns: a pointer to the end of the stored code
3606  */
3607 guint8*
3608 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3609 {
3610 #ifdef HOST_WIN32
3611         if (tls_offset < 64) {
3612                 x86_prefix (code, X86_GS_PREFIX);
3613                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3614         } else {
3615                 guint8 *buf [16];
3616
3617                 g_assert (tls_offset < 0x440);
3618                 /* Load TEB->TlsExpansionSlots */
3619                 x86_prefix (code, X86_GS_PREFIX);
3620                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3621                 amd64_test_reg_reg (code, dreg, dreg);
3622                 buf [0] = code;
3623                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3624                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3625                 amd64_patch (buf [0], code);
3626         }
3627 #elif defined(__APPLE__)
3628         x86_prefix (code, X86_GS_PREFIX);
3629         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3630 #else
3631         if (optimize_for_xen) {
3632                 x86_prefix (code, X86_FS_PREFIX);
3633                 amd64_mov_reg_mem (code, dreg, 0, 8);
3634                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3635         } else {
3636                 x86_prefix (code, X86_FS_PREFIX);
3637                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3638         }
3639 #endif
3640         return code;
3641 }
3642
3643 static guint8*
3644 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3645 {
3646         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3647 #ifdef TARGET_OSX
3648         if (dreg != offset_reg)
3649                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3650         amd64_prefix (code, X86_GS_PREFIX);
3651         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3652 #elif defined(__linux__)
3653         int tmpreg = -1;
3654
3655         if (dreg == offset_reg) {
3656                 /* Use a temporary reg by saving it to the redzone */
3657                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3658                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3659                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3660                 offset_reg = tmpreg;
3661         }
3662         x86_prefix (code, X86_FS_PREFIX);
3663         amd64_mov_reg_mem (code, dreg, 0, 8);
3664         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3665         if (tmpreg != -1)
3666                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3667 #else
3668         g_assert_not_reached ();
3669 #endif
3670         return code;
3671 }
3672
3673 static guint8*
3674 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3675 {
3676 #ifdef HOST_WIN32
3677         g_assert_not_reached ();
3678 #elif defined(__APPLE__)
3679         x86_prefix (code, X86_GS_PREFIX);
3680         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3681 #else
3682         g_assert (!optimize_for_xen);
3683         x86_prefix (code, X86_FS_PREFIX);
3684         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3685 #endif
3686         return code;
3687 }
3688
3689 static guint8*
3690 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3691 {
3692         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3693 #ifdef HOST_WIN32
3694         g_assert_not_reached ();
3695 #elif defined(__APPLE__)
3696         x86_prefix (code, X86_GS_PREFIX);
3697         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3698 #else
3699         x86_prefix (code, X86_FS_PREFIX);
3700         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3701 #endif
3702         return code;
3703 }
3704
3705  /*
3706  * mono_arch_translate_tls_offset:
3707  *
3708  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3709  */
3710 int
3711 mono_arch_translate_tls_offset (int offset)
3712 {
3713 #ifdef __APPLE__
3714         return tls_gs_offset + (offset * 8);
3715 #else
3716         return offset;
3717 #endif
3718 }
3719
3720 /*
3721  * emit_setup_lmf:
3722  *
3723  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3724  */
3725 static guint8*
3726 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3727 {
3728         /*
3729          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3730          */
3731         /*
3732          * sp is saved right before calls but we need to save it here too so
3733          * async stack walks would work.
3734          */
3735         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3736         /* Save rbp */
3737         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3738         if (cfg->arch.omit_fp && cfa_offset != -1)
3739                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3740
3741         /* These can't contain refs */
3742         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3743         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3744         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3745         /* These are handled automatically by the stack marking code */
3746         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3747
3748         return code;
3749 }
3750
3751 #define REAL_PRINT_REG(text,reg) \
3752 mono_assert (reg >= 0); \
3753 amd64_push_reg (code, AMD64_RAX); \
3754 amd64_push_reg (code, AMD64_RDX); \
3755 amd64_push_reg (code, AMD64_RCX); \
3756 amd64_push_reg (code, reg); \
3757 amd64_push_imm (code, reg); \
3758 amd64_push_imm (code, text " %d %p\n"); \
3759 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3760 amd64_call_reg (code, AMD64_RAX); \
3761 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3762 amd64_pop_reg (code, AMD64_RCX); \
3763 amd64_pop_reg (code, AMD64_RDX); \
3764 amd64_pop_reg (code, AMD64_RAX);
3765
3766 /* benchmark and set based on cpu */
3767 #define LOOP_ALIGNMENT 8
3768 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3769
3770 #ifndef DISABLE_JIT
3771 void
3772 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3773 {
3774         MonoInst *ins;
3775         MonoCallInst *call;
3776         guint offset;
3777         guint8 *code = cfg->native_code + cfg->code_len;
3778         MonoInst *last_ins = NULL;
3779         guint last_offset = 0;
3780         int max_len;
3781
3782         /* Fix max_offset estimate for each successor bb */
3783         if (cfg->opt & MONO_OPT_BRANCH) {
3784                 int current_offset = cfg->code_len;
3785                 MonoBasicBlock *current_bb;
3786                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3787                         current_bb->max_offset = current_offset;
3788                         current_offset += current_bb->max_length;
3789                 }
3790         }
3791
3792         if (cfg->opt & MONO_OPT_LOOP) {
3793                 int pad, align = LOOP_ALIGNMENT;
3794                 /* set alignment depending on cpu */
3795                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3796                         pad = align - pad;
3797                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3798                         amd64_padding (code, pad);
3799                         cfg->code_len += pad;
3800                         bb->native_offset = cfg->code_len;
3801                 }
3802         }
3803
3804 #if defined(__native_client_codegen__)
3805         /* For Native Client, all indirect call/jump targets must be */
3806         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3807         /* indirectly as well.                                       */
3808         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3809                                       (bb->flags & BB_EXCEPTION_HANDLER);
3810
3811         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3812                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3813                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3814                 cfg->code_len += pad;
3815                 bb->native_offset = cfg->code_len;
3816         }
3817 #endif  /*__native_client_codegen__*/
3818
3819         if (cfg->verbose_level > 2)
3820                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3821
3822         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3823                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3824                 g_assert (!cfg->compile_aot);
3825
3826                 cov->data [bb->dfn].cil_code = bb->cil_code;
3827                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3828                 /* this is not thread save, but good enough */
3829                 amd64_inc_membase (code, AMD64_R11, 0);
3830         }
3831
3832         offset = code - cfg->native_code;
3833
3834         mono_debug_open_block (cfg, bb, offset);
3835
3836     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3837                 x86_breakpoint (code);
3838
3839         MONO_BB_FOR_EACH_INS (bb, ins) {
3840                 offset = code - cfg->native_code;
3841
3842                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3843
3844 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3845
3846                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3847                         cfg->code_size *= 2;
3848                         cfg->native_code = mono_realloc_native_code(cfg);
3849                         code = cfg->native_code + offset;
3850                         cfg->stat_code_reallocs++;
3851                 }
3852
3853                 if (cfg->debug_info)
3854                         mono_debug_record_line_number (cfg, ins, offset);
3855
3856                 switch (ins->opcode) {
3857                 case OP_BIGMUL:
3858                         amd64_mul_reg (code, ins->sreg2, TRUE);
3859                         break;
3860                 case OP_BIGMUL_UN:
3861                         amd64_mul_reg (code, ins->sreg2, FALSE);
3862                         break;
3863                 case OP_X86_SETEQ_MEMBASE:
3864                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3865                         break;
3866                 case OP_STOREI1_MEMBASE_IMM:
3867                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3868                         break;
3869                 case OP_STOREI2_MEMBASE_IMM:
3870                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3871                         break;
3872                 case OP_STOREI4_MEMBASE_IMM:
3873                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3874                         break;
3875                 case OP_STOREI1_MEMBASE_REG:
3876                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3877                         break;
3878                 case OP_STOREI2_MEMBASE_REG:
3879                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3880                         break;
3881                 /* In AMD64 NaCl, pointers are 4 bytes, */
3882                 /*  so STORE_* != STOREI8_*. Likewise below. */
3883                 case OP_STORE_MEMBASE_REG:
3884                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3885                         break;
3886                 case OP_STOREI8_MEMBASE_REG:
3887                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3888                         break;
3889                 case OP_STOREI4_MEMBASE_REG:
3890                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3891                         break;
3892                 case OP_STORE_MEMBASE_IMM:
3893 #ifndef __native_client_codegen__
3894                         /* In NaCl, this could be a PCONST type, which could */
3895                         /* mean a pointer type was copied directly into the  */
3896                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3897                         /* the value would be 0x00000000FFFFFFFF which is    */
3898                         /* not proper for an imm32 unless you cast it.       */
3899                         g_assert (amd64_is_imm32 (ins->inst_imm));
3900 #endif
3901                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3902                         break;
3903                 case OP_STOREI8_MEMBASE_IMM:
3904                         g_assert (amd64_is_imm32 (ins->inst_imm));
3905                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3906                         break;
3907                 case OP_LOAD_MEM:
3908 #ifdef __mono_ilp32__
3909                         /* In ILP32, pointers are 4 bytes, so separate these */
3910                         /* cases, use literal 8 below where we really want 8 */
3911                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3912                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3913                         break;
3914 #endif
3915                 case OP_LOADI8_MEM:
3916                         // FIXME: Decompose this earlier
3917                         if (amd64_is_imm32 (ins->inst_imm))
3918                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3919                         else {
3920                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3921                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3922                         }
3923                         break;
3924                 case OP_LOADI4_MEM:
3925                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3926                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3927                         break;
3928                 case OP_LOADU4_MEM:
3929                         // FIXME: Decompose this earlier
3930                         if (amd64_is_imm32 (ins->inst_imm))
3931                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3932                         else {
3933                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3934                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3935                         }
3936                         break;
3937                 case OP_LOADU1_MEM:
3938                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3939                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3940                         break;
3941                 case OP_LOADU2_MEM:
3942                         /* For NaCl, pointers are 4 bytes, so separate these */
3943                         /* cases, use literal 8 below where we really want 8 */
3944                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3945                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3946                         break;
3947                 case OP_LOAD_MEMBASE:
3948                         g_assert (amd64_is_imm32 (ins->inst_offset));
3949                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3950                         break;
3951                 case OP_LOADI8_MEMBASE:
3952                         /* Use literal 8 instead of sizeof pointer or */
3953                         /* register, we really want 8 for this opcode */
3954                         g_assert (amd64_is_imm32 (ins->inst_offset));
3955                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3956                         break;
3957                 case OP_LOADI4_MEMBASE:
3958                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3959                         break;
3960                 case OP_LOADU4_MEMBASE:
3961                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3962                         break;
3963                 case OP_LOADU1_MEMBASE:
3964                         /* The cpu zero extends the result into 64 bits */
3965                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3966                         break;
3967                 case OP_LOADI1_MEMBASE:
3968                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3969                         break;
3970                 case OP_LOADU2_MEMBASE:
3971                         /* The cpu zero extends the result into 64 bits */
3972                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3973                         break;
3974                 case OP_LOADI2_MEMBASE:
3975                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3976                         break;
3977                 case OP_AMD64_LOADI8_MEMINDEX:
3978                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3979                         break;
3980                 case OP_LCONV_TO_I1:
3981                 case OP_ICONV_TO_I1:
3982                 case OP_SEXT_I1:
3983                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3984                         break;
3985                 case OP_LCONV_TO_I2:
3986                 case OP_ICONV_TO_I2:
3987                 case OP_SEXT_I2:
3988                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3989                         break;
3990                 case OP_LCONV_TO_U1:
3991                 case OP_ICONV_TO_U1:
3992                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3993                         break;
3994                 case OP_LCONV_TO_U2:
3995                 case OP_ICONV_TO_U2:
3996                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3997                         break;
3998                 case OP_ZEXT_I4:
3999                         /* Clean out the upper word */
4000                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4001                         break;
4002                 case OP_SEXT_I4:
4003                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4004                         break;
4005                 case OP_COMPARE:
4006                 case OP_LCOMPARE:
4007                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4008                         break;
4009                 case OP_COMPARE_IMM:
4010 #if defined(__mono_ilp32__)
4011                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4012                         g_assert (amd64_is_imm32 (ins->inst_imm));
4013                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4014                         break;
4015 #endif
4016                 case OP_LCOMPARE_IMM:
4017                         g_assert (amd64_is_imm32 (ins->inst_imm));
4018                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4019                         break;
4020                 case OP_X86_COMPARE_REG_MEMBASE:
4021                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4022                         break;
4023                 case OP_X86_TEST_NULL:
4024                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4025                         break;
4026                 case OP_AMD64_TEST_NULL:
4027                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4028                         break;
4029
4030                 case OP_X86_ADD_REG_MEMBASE:
4031                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4032                         break;
4033                 case OP_X86_SUB_REG_MEMBASE:
4034                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4035                         break;
4036                 case OP_X86_AND_REG_MEMBASE:
4037                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4038                         break;
4039                 case OP_X86_OR_REG_MEMBASE:
4040                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4041                         break;
4042                 case OP_X86_XOR_REG_MEMBASE:
4043                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4044                         break;
4045
4046                 case OP_X86_ADD_MEMBASE_IMM:
4047                         /* FIXME: Make a 64 version too */
4048                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4049                         break;
4050                 case OP_X86_SUB_MEMBASE_IMM:
4051                         g_assert (amd64_is_imm32 (ins->inst_imm));
4052                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4053                         break;
4054                 case OP_X86_AND_MEMBASE_IMM:
4055                         g_assert (amd64_is_imm32 (ins->inst_imm));
4056                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4057                         break;
4058                 case OP_X86_OR_MEMBASE_IMM:
4059                         g_assert (amd64_is_imm32 (ins->inst_imm));
4060                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4061                         break;
4062                 case OP_X86_XOR_MEMBASE_IMM:
4063                         g_assert (amd64_is_imm32 (ins->inst_imm));
4064                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4065                         break;
4066                 case OP_X86_ADD_MEMBASE_REG:
4067                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4068                         break;
4069                 case OP_X86_SUB_MEMBASE_REG:
4070                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4071                         break;
4072                 case OP_X86_AND_MEMBASE_REG:
4073                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4074                         break;
4075                 case OP_X86_OR_MEMBASE_REG:
4076                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4077                         break;
4078                 case OP_X86_XOR_MEMBASE_REG:
4079                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4080                         break;
4081                 case OP_X86_INC_MEMBASE:
4082                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4083                         break;
4084                 case OP_X86_INC_REG:
4085                         amd64_inc_reg_size (code, ins->dreg, 4);
4086                         break;
4087                 case OP_X86_DEC_MEMBASE:
4088                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4089                         break;
4090                 case OP_X86_DEC_REG:
4091                         amd64_dec_reg_size (code, ins->dreg, 4);
4092                         break;
4093                 case OP_X86_MUL_REG_MEMBASE:
4094                 case OP_X86_MUL_MEMBASE_REG:
4095                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4096                         break;
4097                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4098                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4099                         break;
4100                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4101                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4102                         break;
4103                 case OP_AMD64_COMPARE_MEMBASE_REG:
4104                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4105                         break;
4106                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4107                         g_assert (amd64_is_imm32 (ins->inst_imm));
4108                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4109                         break;
4110                 case OP_X86_COMPARE_MEMBASE8_IMM:
4111                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4112                         break;
4113                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4114                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4115                         break;
4116                 case OP_AMD64_COMPARE_REG_MEMBASE:
4117                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4118                         break;
4119
4120                 case OP_AMD64_ADD_REG_MEMBASE:
4121                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4122                         break;
4123                 case OP_AMD64_SUB_REG_MEMBASE:
4124                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4125                         break;
4126                 case OP_AMD64_AND_REG_MEMBASE:
4127                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4128                         break;
4129                 case OP_AMD64_OR_REG_MEMBASE:
4130                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4131                         break;
4132                 case OP_AMD64_XOR_REG_MEMBASE:
4133                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4134                         break;
4135
4136                 case OP_AMD64_ADD_MEMBASE_REG:
4137                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4138                         break;
4139                 case OP_AMD64_SUB_MEMBASE_REG:
4140                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4141                         break;
4142                 case OP_AMD64_AND_MEMBASE_REG:
4143                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4144                         break;
4145                 case OP_AMD64_OR_MEMBASE_REG:
4146                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4147                         break;
4148                 case OP_AMD64_XOR_MEMBASE_REG:
4149                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4150                         break;
4151
4152                 case OP_AMD64_ADD_MEMBASE_IMM:
4153                         g_assert (amd64_is_imm32 (ins->inst_imm));
4154                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4155                         break;
4156                 case OP_AMD64_SUB_MEMBASE_IMM:
4157                         g_assert (amd64_is_imm32 (ins->inst_imm));
4158                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4159                         break;
4160                 case OP_AMD64_AND_MEMBASE_IMM:
4161                         g_assert (amd64_is_imm32 (ins->inst_imm));
4162                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4163                         break;
4164                 case OP_AMD64_OR_MEMBASE_IMM:
4165                         g_assert (amd64_is_imm32 (ins->inst_imm));
4166                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4167                         break;
4168                 case OP_AMD64_XOR_MEMBASE_IMM:
4169                         g_assert (amd64_is_imm32 (ins->inst_imm));
4170                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4171                         break;
4172
4173                 case OP_BREAK:
4174                         amd64_breakpoint (code);
4175                         break;
4176                 case OP_RELAXED_NOP:
4177                         x86_prefix (code, X86_REP_PREFIX);
4178                         x86_nop (code);
4179                         break;
4180                 case OP_HARD_NOP:
4181                         x86_nop (code);
4182                         break;
4183                 case OP_NOP:
4184                 case OP_DUMMY_USE:
4185                 case OP_DUMMY_STORE:
4186                 case OP_DUMMY_ICONST:
4187                 case OP_DUMMY_R8CONST:
4188                 case OP_NOT_REACHED:
4189                 case OP_NOT_NULL:
4190                         break;
4191                 case OP_IL_SEQ_POINT:
4192                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4193                         break;
4194                 case OP_SEQ_POINT: {
4195                         int i;
4196
4197                         /*
4198                          * Read from the single stepping trigger page. This will cause a
4199                          * SIGSEGV when single stepping is enabled.
4200                          * We do this _before_ the breakpoint, so single stepping after
4201                          * a breakpoint is hit will step to the next IL offset.
4202                          */
4203                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4204                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4205
4206                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4207                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4208                         }
4209
4210                         /*
4211                          * This is the address which is saved in seq points,
4212                          */
4213                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4214
4215                         if (cfg->compile_aot) {
4216                                 guint32 offset = code - cfg->native_code;
4217                                 guint32 val;
4218                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4219
4220                                 /* Load info var */
4221                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4222                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4223                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4224                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4225                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4226                         } else {
4227                                 /*
4228                                  * A placeholder for a possible breakpoint inserted by
4229                                  * mono_arch_set_breakpoint ().
4230                                  */
4231                                 for (i = 0; i < breakpoint_size; ++i)
4232                                         x86_nop (code);
4233                         }
4234                         /*
4235                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4236                          * to another IL offset.
4237                          */
4238                         x86_nop (code);
4239                         break;
4240                 }
4241                 case OP_ADDCC:
4242                 case OP_LADDCC:
4243                 case OP_LADD:
4244                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4245                         break;
4246                 case OP_ADC:
4247                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4248                         break;
4249                 case OP_ADD_IMM:
4250                 case OP_LADD_IMM:
4251                         g_assert (amd64_is_imm32 (ins->inst_imm));
4252                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4253                         break;
4254                 case OP_ADC_IMM:
4255                         g_assert (amd64_is_imm32 (ins->inst_imm));
4256                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4257                         break;
4258                 case OP_SUBCC:
4259                 case OP_LSUBCC:
4260                 case OP_LSUB:
4261                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4262                         break;
4263                 case OP_SBB:
4264                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4265                         break;
4266                 case OP_SUB_IMM:
4267                 case OP_LSUB_IMM:
4268                         g_assert (amd64_is_imm32 (ins->inst_imm));
4269                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4270                         break;
4271                 case OP_SBB_IMM:
4272                         g_assert (amd64_is_imm32 (ins->inst_imm));
4273                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4274                         break;
4275                 case OP_LAND:
4276                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4277                         break;
4278                 case OP_AND_IMM:
4279                 case OP_LAND_IMM:
4280                         g_assert (amd64_is_imm32 (ins->inst_imm));
4281                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4282                         break;
4283                 case OP_LMUL:
4284                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4285                         break;
4286                 case OP_MUL_IMM:
4287                 case OP_LMUL_IMM:
4288                 case OP_IMUL_IMM: {
4289                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4290
4291                         switch (ins->inst_imm) {
4292                         case 2:
4293                                 /* MOV r1, r2 */
4294                                 /* ADD r1, r1 */
4295                                 if (ins->dreg != ins->sreg1)
4296                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4297                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4298                                 break;
4299                         case 3:
4300                                 /* LEA r1, [r2 + r2*2] */
4301                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4302                                 break;
4303                         case 5:
4304                                 /* LEA r1, [r2 + r2*4] */
4305                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4306                                 break;
4307                         case 6:
4308                                 /* LEA r1, [r2 + r2*2] */
4309                                 /* ADD r1, r1          */
4310                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4311                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4312                                 break;
4313                         case 9:
4314                                 /* LEA r1, [r2 + r2*8] */
4315                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4316                                 break;
4317                         case 10:
4318                                 /* LEA r1, [r2 + r2*4] */
4319                                 /* ADD r1, r1          */
4320                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4321                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4322                                 break;
4323                         case 12:
4324                                 /* LEA r1, [r2 + r2*2] */
4325                                 /* SHL r1, 2           */
4326                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4327                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4328                                 break;
4329                         case 25:
4330                                 /* LEA r1, [r2 + r2*4] */
4331                                 /* LEA r1, [r1 + r1*4] */
4332                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4333                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4334                                 break;
4335                         case 100:
4336                                 /* LEA r1, [r2 + r2*4] */
4337                                 /* SHL r1, 2           */
4338                                 /* LEA r1, [r1 + r1*4] */
4339                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4340                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4341                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4342                                 break;
4343                         default:
4344                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4345                                 break;
4346                         }
4347                         break;
4348                 }
4349                 case OP_LDIV:
4350                 case OP_LREM:
4351 #if defined( __native_client_codegen__ )
4352                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4353                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4354 #endif
4355                         /* Regalloc magic makes the div/rem cases the same */
4356                         if (ins->sreg2 == AMD64_RDX) {
4357                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4358                                 amd64_cdq (code);
4359                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4360                         } else {
4361                                 amd64_cdq (code);
4362                                 amd64_div_reg (code, ins->sreg2, TRUE);
4363                         }
4364                         break;
4365                 case OP_LDIV_UN:
4366                 case OP_LREM_UN:
4367 #if defined( __native_client_codegen__ )
4368                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4369                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4370 #endif
4371                         if (ins->sreg2 == AMD64_RDX) {
4372                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4373                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4374                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4375                         } else {
4376                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4377                                 amd64_div_reg (code, ins->sreg2, FALSE);
4378                         }
4379                         break;
4380                 case OP_IDIV:
4381                 case OP_IREM:
4382 #if defined( __native_client_codegen__ )
4383                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4384                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4385 #endif
4386                         if (ins->sreg2 == AMD64_RDX) {
4387                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4388                                 amd64_cdq_size (code, 4);
4389                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4390                         } else {
4391                                 amd64_cdq_size (code, 4);
4392                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4393                         }
4394                         break;
4395                 case OP_IDIV_UN:
4396                 case OP_IREM_UN:
4397 #if defined( __native_client_codegen__ )
4398                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4399                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4400 #endif
4401                         if (ins->sreg2 == AMD64_RDX) {
4402                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4403                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4404                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4405                         } else {
4406                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4407                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4408                         }
4409                         break;
4410                 case OP_LMUL_OVF:
4411                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4412                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4413                         break;
4414                 case OP_LOR:
4415                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4416                         break;
4417                 case OP_OR_IMM:
4418                 case OP_LOR_IMM:
4419                         g_assert (amd64_is_imm32 (ins->inst_imm));
4420                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4421                         break;
4422                 case OP_LXOR:
4423                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4424                         break;
4425                 case OP_XOR_IMM:
4426                 case OP_LXOR_IMM:
4427                         g_assert (amd64_is_imm32 (ins->inst_imm));
4428                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4429                         break;
4430                 case OP_LSHL:
4431                         g_assert (ins->sreg2 == AMD64_RCX);
4432                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4433                         break;
4434                 case OP_LSHR:
4435                         g_assert (ins->sreg2 == AMD64_RCX);
4436                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4437                         break;
4438                 case OP_SHR_IMM:
4439                         g_assert (amd64_is_imm32 (ins->inst_imm));
4440                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4441                         break;
4442                 case OP_LSHR_IMM:
4443                         g_assert (amd64_is_imm32 (ins->inst_imm));
4444                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4445                         break;
4446                 case OP_SHR_UN_IMM:
4447                         g_assert (amd64_is_imm32 (ins->inst_imm));
4448                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4449                         break;
4450                 case OP_LSHR_UN_IMM:
4451                         g_assert (amd64_is_imm32 (ins->inst_imm));
4452                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4453                         break;
4454                 case OP_LSHR_UN:
4455                         g_assert (ins->sreg2 == AMD64_RCX);
4456                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4457                         break;
4458                 case OP_SHL_IMM:
4459                         g_assert (amd64_is_imm32 (ins->inst_imm));
4460                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4461                         break;
4462                 case OP_LSHL_IMM:
4463                         g_assert (amd64_is_imm32 (ins->inst_imm));
4464                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4465                         break;
4466
4467                 case OP_IADDCC:
4468                 case OP_IADD:
4469                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4470                         break;
4471                 case OP_IADC:
4472                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4473                         break;
4474                 case OP_IADD_IMM:
4475                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4476                         break;
4477                 case OP_IADC_IMM:
4478                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4479                         break;
4480                 case OP_ISUBCC:
4481                 case OP_ISUB:
4482                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4483                         break;
4484                 case OP_ISBB:
4485                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4486                         break;
4487                 case OP_ISUB_IMM:
4488                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4489                         break;
4490                 case OP_ISBB_IMM:
4491                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4492                         break;
4493                 case OP_IAND:
4494                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4495                         break;
4496                 case OP_IAND_IMM:
4497                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4498                         break;
4499                 case OP_IOR:
4500                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4501                         break;
4502                 case OP_IOR_IMM:
4503                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4504                         break;
4505                 case OP_IXOR:
4506                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4507                         break;
4508                 case OP_IXOR_IMM:
4509                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4510                         break;
4511                 case OP_INEG:
4512                         amd64_neg_reg_size (code, ins->sreg1, 4);
4513                         break;
4514                 case OP_INOT:
4515                         amd64_not_reg_size (code, ins->sreg1, 4);
4516                         break;
4517                 case OP_ISHL:
4518                         g_assert (ins->sreg2 == AMD64_RCX);
4519                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4520                         break;
4521                 case OP_ISHR:
4522                         g_assert (ins->sreg2 == AMD64_RCX);
4523                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4524                         break;
4525                 case OP_ISHR_IMM:
4526                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4527                         break;
4528                 case OP_ISHR_UN_IMM:
4529                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4530                         break;
4531                 case OP_ISHR_UN:
4532                         g_assert (ins->sreg2 == AMD64_RCX);
4533                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4534                         break;
4535                 case OP_ISHL_IMM:
4536                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4537                         break;
4538                 case OP_IMUL:
4539                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4540                         break;
4541                 case OP_IMUL_OVF:
4542                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4543                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4544                         break;
4545                 case OP_IMUL_OVF_UN:
4546                 case OP_LMUL_OVF_UN: {
4547                         /* the mul operation and the exception check should most likely be split */
4548                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4549                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4550                         /*g_assert (ins->sreg2 == X86_EAX);
4551                         g_assert (ins->dreg == X86_EAX);*/
4552                         if (ins->sreg2 == X86_EAX) {
4553                                 non_eax_reg = ins->sreg1;
4554                         } else if (ins->sreg1 == X86_EAX) {
4555                                 non_eax_reg = ins->sreg2;
4556                         } else {
4557                                 /* no need to save since we're going to store to it anyway */
4558                                 if (ins->dreg != X86_EAX) {
4559                                         saved_eax = TRUE;
4560                                         amd64_push_reg (code, X86_EAX);
4561                                 }
4562                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4563                                 non_eax_reg = ins->sreg2;
4564                         }
4565                         if (ins->dreg == X86_EDX) {
4566                                 if (!saved_eax) {
4567                                         saved_eax = TRUE;
4568                                         amd64_push_reg (code, X86_EAX);
4569                                 }
4570                         } else {
4571                                 saved_edx = TRUE;
4572                                 amd64_push_reg (code, X86_EDX);
4573                         }
4574                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4575                         /* save before the check since pop and mov don't change the flags */
4576                         if (ins->dreg != X86_EAX)
4577                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4578                         if (saved_edx)
4579                                 amd64_pop_reg (code, X86_EDX);
4580                         if (saved_eax)
4581                                 amd64_pop_reg (code, X86_EAX);
4582                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4583                         break;
4584                 }
4585                 case OP_ICOMPARE:
4586                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4587                         break;
4588                 case OP_ICOMPARE_IMM:
4589                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4590                         break;
4591                 case OP_IBEQ:
4592                 case OP_IBLT:
4593                 case OP_IBGT:
4594                 case OP_IBGE:
4595                 case OP_IBLE:
4596                 case OP_LBEQ:
4597                 case OP_LBLT:
4598                 case OP_LBGT:
4599                 case OP_LBGE:
4600                 case OP_LBLE:
4601                 case OP_IBNE_UN:
4602                 case OP_IBLT_UN:
4603                 case OP_IBGT_UN:
4604                 case OP_IBGE_UN:
4605                 case OP_IBLE_UN:
4606                 case OP_LBNE_UN:
4607                 case OP_LBLT_UN:
4608                 case OP_LBGT_UN:
4609                 case OP_LBGE_UN:
4610                 case OP_LBLE_UN:
4611                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4612                         break;
4613
4614                 case OP_CMOV_IEQ:
4615                 case OP_CMOV_IGE:
4616                 case OP_CMOV_IGT:
4617                 case OP_CMOV_ILE:
4618                 case OP_CMOV_ILT:
4619                 case OP_CMOV_INE_UN:
4620                 case OP_CMOV_IGE_UN:
4621                 case OP_CMOV_IGT_UN:
4622                 case OP_CMOV_ILE_UN:
4623                 case OP_CMOV_ILT_UN:
4624                 case OP_CMOV_LEQ:
4625                 case OP_CMOV_LGE:
4626                 case OP_CMOV_LGT:
4627                 case OP_CMOV_LLE:
4628                 case OP_CMOV_LLT:
4629                 case OP_CMOV_LNE_UN:
4630                 case OP_CMOV_LGE_UN:
4631                 case OP_CMOV_LGT_UN:
4632                 case OP_CMOV_LLE_UN:
4633                 case OP_CMOV_LLT_UN:
4634                         g_assert (ins->dreg == ins->sreg1);
4635                         /* This needs to operate on 64 bit values */
4636                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4637                         break;
4638
4639                 case OP_LNOT:
4640                         amd64_not_reg (code, ins->sreg1);
4641                         break;
4642                 case OP_LNEG:
4643                         amd64_neg_reg (code, ins->sreg1);
4644                         break;
4645
4646                 case OP_ICONST:
4647                 case OP_I8CONST:
4648                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4649                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4650                         else
4651                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4652                         break;
4653                 case OP_AOTCONST:
4654                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4655                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4656                         break;
4657                 case OP_JUMP_TABLE:
4658                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4659                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4660                         break;
4661                 case OP_MOVE:
4662                         if (ins->dreg != ins->sreg1)
4663                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4664                         break;
4665                 case OP_AMD64_SET_XMMREG_R4: {
4666                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4667                         break;
4668                 }
4669                 case OP_AMD64_SET_XMMREG_R8: {
4670                         if (ins->dreg != ins->sreg1)
4671                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4672                         break;
4673                 }
4674                 case OP_TAILCALL: {
4675                         MonoCallInst *call = (MonoCallInst*)ins;
4676                         int i, save_area_offset;
4677
4678                         g_assert (!cfg->method->save_lmf);
4679
4680                         /* Restore callee saved registers */
4681                         save_area_offset = cfg->arch.reg_save_area_offset;
4682                         for (i = 0; i < AMD64_NREG; ++i)
4683                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4684                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4685                                         save_area_offset += 8;
4686                                 }
4687
4688                         if (cfg->arch.omit_fp) {
4689                                 if (cfg->arch.stack_alloc_size)
4690                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4691                                 // FIXME:
4692                                 if (call->stack_usage)
4693                                         NOT_IMPLEMENTED;
4694                         } else {
4695                                 /* Copy arguments on the stack to our argument area */
4696                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4697                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4698                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4699                                 }
4700
4701                                 amd64_leave (code);
4702                         }
4703
4704                         offset = code - cfg->native_code;
4705                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4706                         if (cfg->compile_aot)
4707                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4708                         else
4709                                 amd64_set_reg_template (code, AMD64_R11);
4710                         amd64_jump_reg (code, AMD64_R11);
4711                         ins->flags |= MONO_INST_GC_CALLSITE;
4712                         ins->backend.pc_offset = code - cfg->native_code;
4713                         break;
4714                 }
4715                 case OP_CHECK_THIS:
4716                         /* ensure ins->sreg1 is not NULL */
4717                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4718                         break;
4719                 case OP_ARGLIST: {
4720                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4721                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4722                         break;
4723                 }
4724                 case OP_CALL:
4725                 case OP_FCALL:
4726                 case OP_LCALL:
4727                 case OP_VCALL:
4728                 case OP_VCALL2:
4729                 case OP_VOIDCALL:
4730                         call = (MonoCallInst*)ins;
4731                         /*
4732                          * The AMD64 ABI forces callers to know about varargs.
4733                          */
4734                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4735                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4736                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4737                                 /*
4738                                  * Since the unmanaged calling convention doesn't contain a
4739                                  * 'vararg' entry, we have to treat every pinvoke call as a
4740                                  * potential vararg call.
4741                                  */
4742                                 guint32 nregs, i;
4743                                 nregs = 0;
4744                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4745                                         if (call->used_fregs & (1 << i))
4746                                                 nregs ++;
4747                                 if (!nregs)
4748                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4749                                 else
4750                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4751                         }
4752
4753                         if (ins->flags & MONO_INST_HAS_METHOD)
4754                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4755                         else
4756                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4757                         ins->flags |= MONO_INST_GC_CALLSITE;
4758                         ins->backend.pc_offset = code - cfg->native_code;
4759                         code = emit_move_return_value (cfg, ins, code);
4760                         break;
4761                 case OP_FCALL_REG:
4762                 case OP_LCALL_REG:
4763                 case OP_VCALL_REG:
4764                 case OP_VCALL2_REG:
4765                 case OP_VOIDCALL_REG:
4766                 case OP_CALL_REG:
4767                         call = (MonoCallInst*)ins;
4768
4769                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4770                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4771                                 ins->sreg1 = AMD64_R11;
4772                         }
4773
4774                         /*
4775                          * The AMD64 ABI forces callers to know about varargs.
4776                          */
4777                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4778                                 if (ins->sreg1 == AMD64_RAX) {
4779                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4780                                         ins->sreg1 = AMD64_R11;
4781                                 }
4782                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4783                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4784                                 /*
4785                                  * Since the unmanaged calling convention doesn't contain a
4786                                  * 'vararg' entry, we have to treat every pinvoke call as a
4787                                  * potential vararg call.
4788                                  */
4789                                 guint32 nregs, i;
4790                                 nregs = 0;
4791                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4792                                         if (call->used_fregs & (1 << i))
4793                                                 nregs ++;
4794                                 if (ins->sreg1 == AMD64_RAX) {
4795                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4796                                         ins->sreg1 = AMD64_R11;
4797                                 }
4798                                 if (!nregs)
4799                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4800                                 else
4801                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4802                         }
4803
4804                         amd64_call_reg (code, ins->sreg1);
4805                         ins->flags |= MONO_INST_GC_CALLSITE;
4806                         ins->backend.pc_offset = code - cfg->native_code;
4807                         code = emit_move_return_value (cfg, ins, code);
4808                         break;
4809                 case OP_FCALL_MEMBASE:
4810                 case OP_LCALL_MEMBASE:
4811                 case OP_VCALL_MEMBASE:
4812                 case OP_VCALL2_MEMBASE:
4813                 case OP_VOIDCALL_MEMBASE:
4814                 case OP_CALL_MEMBASE:
4815                         call = (MonoCallInst*)ins;
4816
4817                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4818                         ins->flags |= MONO_INST_GC_CALLSITE;
4819                         ins->backend.pc_offset = code - cfg->native_code;
4820                         code = emit_move_return_value (cfg, ins, code);
4821                         break;
4822                 case OP_DYN_CALL: {
4823                         int i;
4824                         MonoInst *var = cfg->dyn_call_var;
4825
4826                         g_assert (var->opcode == OP_REGOFFSET);
4827
4828                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4829                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4830                         /* r10 = ftn */
4831                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4832
4833                         /* Save args buffer */
4834                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4835
4836                         /* Set argument registers */
4837                         for (i = 0; i < PARAM_REGS; ++i)
4838                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4839
4840                         /* Make the call */
4841                         amd64_call_reg (code, AMD64_R10);
4842
4843                         ins->flags |= MONO_INST_GC_CALLSITE;
4844                         ins->backend.pc_offset = code - cfg->native_code;
4845
4846                         /* Save result */
4847                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4848                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4849                         break;
4850                 }
4851                 case OP_AMD64_SAVE_SP_TO_LMF: {
4852                         MonoInst *lmf_var = cfg->lmf_var;
4853                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4854                         break;
4855                 }
4856                 case OP_X86_PUSH:
4857                         g_assert_not_reached ();
4858                         amd64_push_reg (code, ins->sreg1);
4859                         break;
4860                 case OP_X86_PUSH_IMM:
4861                         g_assert_not_reached ();
4862                         g_assert (amd64_is_imm32 (ins->inst_imm));
4863                         amd64_push_imm (code, ins->inst_imm);
4864                         break;
4865                 case OP_X86_PUSH_MEMBASE:
4866                         g_assert_not_reached ();
4867                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4868                         break;
4869                 case OP_X86_PUSH_OBJ: {
4870                         int size = ALIGN_TO (ins->inst_imm, 8);
4871
4872                         g_assert_not_reached ();
4873
4874                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4875                         amd64_push_reg (code, AMD64_RDI);
4876                         amd64_push_reg (code, AMD64_RSI);
4877                         amd64_push_reg (code, AMD64_RCX);
4878                         if (ins->inst_offset)
4879                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4880                         else
4881                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4882                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4883                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4884                         amd64_cld (code);
4885                         amd64_prefix (code, X86_REP_PREFIX);
4886                         amd64_movsd (code);
4887                         amd64_pop_reg (code, AMD64_RCX);
4888                         amd64_pop_reg (code, AMD64_RSI);
4889                         amd64_pop_reg (code, AMD64_RDI);
4890                         break;
4891                 }
4892                 case OP_X86_LEA:
4893                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4894                         break;
4895                 case OP_X86_LEA_MEMBASE:
4896                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4897                         break;
4898                 case OP_X86_XCHG:
4899                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4900                         break;
4901                 case OP_LOCALLOC:
4902                         /* keep alignment */
4903                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4904                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4905                         code = mono_emit_stack_alloc (cfg, code, ins);
4906                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4907                         if (cfg->param_area)
4908                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4909                         break;
4910                 case OP_LOCALLOC_IMM: {
4911                         guint32 size = ins->inst_imm;
4912                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4913
4914                         if (ins->flags & MONO_INST_INIT) {
4915                                 if (size < 64) {
4916                                         int i;
4917
4918                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4919                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4920
4921                                         for (i = 0; i < size; i += 8)
4922                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4923                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4924                                 } else {
4925                                         amd64_mov_reg_imm (code, ins->dreg, size);
4926                                         ins->sreg1 = ins->dreg;
4927
4928                                         code = mono_emit_stack_alloc (cfg, code, ins);
4929                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4930                                 }
4931                         } else {
4932                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4933                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4934                         }
4935                         if (cfg->param_area)
4936                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4937                         break;
4938                 }
4939                 case OP_THROW: {
4940                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4941                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4942                                              (gpointer)"mono_arch_throw_exception", FALSE);
4943                         ins->flags |= MONO_INST_GC_CALLSITE;
4944                         ins->backend.pc_offset = code - cfg->native_code;
4945                         break;
4946                 }
4947                 case OP_RETHROW: {
4948                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4949                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4950                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4951                         ins->flags |= MONO_INST_GC_CALLSITE;
4952                         ins->backend.pc_offset = code - cfg->native_code;
4953                         break;
4954                 }
4955                 case OP_CALL_HANDLER:
4956                         /* Align stack */
4957                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4958                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4959                         amd64_call_imm (code, 0);
4960                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4961                         /* Restore stack alignment */
4962                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4963                         break;
4964                 case OP_START_HANDLER: {
4965                         /* Even though we're saving RSP, use sizeof */
4966                         /* gpointer because spvar is of type IntPtr */
4967                         /* see: mono_create_spvar_for_region */
4968                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4969                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4970
4971                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4972                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4973                                 cfg->param_area) {
4974                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4975                         }
4976                         break;
4977                 }
4978                 case OP_ENDFINALLY: {
4979                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4980                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4981                         amd64_ret (code);
4982                         break;
4983                 }
4984                 case OP_ENDFILTER: {
4985                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4986                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4987                         /* The local allocator will put the result into RAX */
4988                         amd64_ret (code);
4989                         break;
4990                 }
4991
4992                 case OP_LABEL:
4993                         ins->inst_c0 = code - cfg->native_code;
4994                         break;
4995                 case OP_BR:
4996                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4997                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4998                         //break;
4999                                 if (ins->inst_target_bb->native_offset) {
5000                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5001                                 } else {
5002                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5003                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5004                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5005                                                 x86_jump8 (code, 0);
5006                                         else
5007                                                 x86_jump32 (code, 0);
5008                         }
5009                         break;
5010                 case OP_BR_REG:
5011                         amd64_jump_reg (code, ins->sreg1);
5012                         break;
5013                 case OP_ICNEQ:
5014                 case OP_ICGE:
5015                 case OP_ICLE:
5016                 case OP_ICGE_UN:
5017                 case OP_ICLE_UN:
5018
5019                 case OP_CEQ:
5020                 case OP_LCEQ:
5021                 case OP_ICEQ:
5022                 case OP_CLT:
5023                 case OP_LCLT:
5024                 case OP_ICLT:
5025                 case OP_CGT:
5026                 case OP_ICGT:
5027                 case OP_LCGT:
5028                 case OP_CLT_UN:
5029                 case OP_LCLT_UN:
5030                 case OP_ICLT_UN:
5031                 case OP_CGT_UN:
5032                 case OP_LCGT_UN:
5033                 case OP_ICGT_UN:
5034                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5035                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5036                         break;
5037                 case OP_COND_EXC_EQ:
5038                 case OP_COND_EXC_NE_UN:
5039                 case OP_COND_EXC_LT:
5040                 case OP_COND_EXC_LT_UN:
5041                 case OP_COND_EXC_GT:
5042                 case OP_COND_EXC_GT_UN:
5043                 case OP_COND_EXC_GE:
5044                 case OP_COND_EXC_GE_UN:
5045                 case OP_COND_EXC_LE:
5046                 case OP_COND_EXC_LE_UN:
5047                 case OP_COND_EXC_IEQ:
5048                 case OP_COND_EXC_INE_UN:
5049                 case OP_COND_EXC_ILT:
5050                 case OP_COND_EXC_ILT_UN:
5051                 case OP_COND_EXC_IGT:
5052                 case OP_COND_EXC_IGT_UN:
5053                 case OP_COND_EXC_IGE:
5054                 case OP_COND_EXC_IGE_UN:
5055                 case OP_COND_EXC_ILE:
5056                 case OP_COND_EXC_ILE_UN:
5057                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5058                         break;
5059                 case OP_COND_EXC_OV:
5060                 case OP_COND_EXC_NO:
5061                 case OP_COND_EXC_C:
5062                 case OP_COND_EXC_NC:
5063                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5064                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5065                         break;
5066                 case OP_COND_EXC_IOV:
5067                 case OP_COND_EXC_INO:
5068                 case OP_COND_EXC_IC:
5069                 case OP_COND_EXC_INC:
5070                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5071                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5072                         break;
5073
5074                 /* floating point opcodes */
5075                 case OP_R8CONST: {
5076                         double d = *(double *)ins->inst_p0;
5077
5078                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5079                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5080                         }
5081                         else {
5082                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5083                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5084                         }
5085                         break;
5086                 }
5087                 case OP_R4CONST: {
5088                         float f = *(float *)ins->inst_p0;
5089
5090                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5091                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5092                         }
5093                         else {
5094                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5095                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5096                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5097                         }
5098                         break;
5099                 }
5100                 case OP_STORER8_MEMBASE_REG:
5101                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5102                         break;
5103                 case OP_LOADR8_MEMBASE:
5104                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5105                         break;
5106                 case OP_STORER4_MEMBASE_REG:
5107                         /* This requires a double->single conversion */
5108                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5109                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5110                         break;
5111                 case OP_LOADR4_MEMBASE:
5112                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5113                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5114                         break;
5115                 case OP_ICONV_TO_R4:
5116                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5117                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5118                         break;
5119                 case OP_ICONV_TO_R8:
5120                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5121                         break;
5122                 case OP_LCONV_TO_R4:
5123                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5124                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5125                         break;
5126                 case OP_LCONV_TO_R8:
5127                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5128                         break;
5129                 case OP_FCONV_TO_R4:
5130                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5131                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5132                         break;
5133                 case OP_FCONV_TO_I1:
5134                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5135                         break;
5136                 case OP_FCONV_TO_U1:
5137                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5138                         break;
5139                 case OP_FCONV_TO_I2:
5140                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5141                         break;
5142                 case OP_FCONV_TO_U2:
5143                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5144                         break;
5145                 case OP_FCONV_TO_U4:
5146                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5147                         break;
5148                 case OP_FCONV_TO_I4:
5149                 case OP_FCONV_TO_I:
5150                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5151                         break;
5152                 case OP_FCONV_TO_I8:
5153                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5154                         break;
5155                 case OP_LCONV_TO_R_UN: {
5156                         guint8 *br [2];
5157
5158                         /* Based on gcc code */
5159                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5160                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5161
5162                         /* Positive case */
5163                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5164                         br [1] = code; x86_jump8 (code, 0);
5165                         amd64_patch (br [0], code);
5166
5167                         /* Negative case */
5168                         /* Save to the red zone */
5169                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5170                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5171                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5172                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5173                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5174                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5175                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5176                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5177                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5178                         /* Restore */
5179                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5180                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5181                         amd64_patch (br [1], code);
5182                         break;
5183                 }
5184                 case OP_LCONV_TO_OVF_U4:
5185                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5186                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5187                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5188                         break;
5189                 case OP_LCONV_TO_OVF_I4_UN:
5190                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5191                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5192                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5193                         break;
5194                 case OP_FMOVE:
5195                         if (ins->dreg != ins->sreg1)
5196                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5197                         break;
5198                 case OP_MOVE_F_TO_I4:
5199                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5200                         amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5201                         break;
5202                 case OP_MOVE_I4_TO_F:
5203                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5204                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5205                         break;
5206                 case OP_MOVE_F_TO_I8:
5207                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5208                         break;
5209                 case OP_MOVE_I8_TO_F:
5210                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5211                         break;
5212                 case OP_FADD:
5213                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5214                         break;
5215                 case OP_FSUB:
5216                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5217                         break;
5218                 case OP_FMUL:
5219                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5220                         break;
5221                 case OP_FDIV:
5222                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5223                         break;
5224                 case OP_FNEG: {
5225                         static double r8_0 = -0.0;
5226
5227                         g_assert (ins->sreg1 == ins->dreg);
5228
5229                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5230                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5231                         break;
5232                 }
5233                 case OP_SIN:
5234                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5235                         break;
5236                 case OP_COS:
5237                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5238                         break;
5239                 case OP_ABS: {
5240                         static guint64 d = 0x7fffffffffffffffUL;
5241
5242                         g_assert (ins->sreg1 == ins->dreg);
5243
5244                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5245                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5246                         break;
5247                 }
5248                 case OP_SQRT:
5249                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5250                         break;
5251                 case OP_IMIN:
5252                         g_assert (cfg->opt & MONO_OPT_CMOV);
5253                         g_assert (ins->dreg == ins->sreg1);
5254                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5255                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5256                         break;
5257                 case OP_IMIN_UN:
5258                         g_assert (cfg->opt & MONO_OPT_CMOV);
5259                         g_assert (ins->dreg == ins->sreg1);
5260                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5261                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5262                         break;
5263                 case OP_IMAX:
5264                         g_assert (cfg->opt & MONO_OPT_CMOV);
5265                         g_assert (ins->dreg == ins->sreg1);
5266                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5267                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5268                         break;
5269                 case OP_IMAX_UN:
5270                         g_assert (cfg->opt & MONO_OPT_CMOV);
5271                         g_assert (ins->dreg == ins->sreg1);
5272                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5273                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5274                         break;
5275                 case OP_LMIN:
5276                         g_assert (cfg->opt & MONO_OPT_CMOV);
5277                         g_assert (ins->dreg == ins->sreg1);
5278                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5279                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5280                         break;
5281                 case OP_LMIN_UN:
5282                         g_assert (cfg->opt & MONO_OPT_CMOV);
5283                         g_assert (ins->dreg == ins->sreg1);
5284                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5285                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5286                         break;
5287                 case OP_LMAX:
5288                         g_assert (cfg->opt & MONO_OPT_CMOV);
5289                         g_assert (ins->dreg == ins->sreg1);
5290                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5291                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5292                         break;
5293                 case OP_LMAX_UN:
5294                         g_assert (cfg->opt & MONO_OPT_CMOV);
5295                         g_assert (ins->dreg == ins->sreg1);
5296                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5297                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5298                         break;
5299                 case OP_X86_FPOP:
5300                         break;
5301                 case OP_FCOMPARE:
5302                         /*
5303                          * The two arguments are swapped because the fbranch instructions
5304                          * depend on this for the non-sse case to work.
5305                          */
5306                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5307                         break;
5308                 case OP_FCNEQ:
5309                 case OP_FCEQ: {
5310                         /* zeroing the register at the start results in
5311                          * shorter and faster code (we can also remove the widening op)
5312                          */
5313                         guchar *unordered_check;
5314                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5315                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5316                         unordered_check = code;
5317                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5318
5319                         if (ins->opcode == OP_FCEQ) {
5320                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5321                                 amd64_patch (unordered_check, code);
5322                         } else {
5323                                 guchar *jump_to_end;
5324                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5325                                 jump_to_end = code;
5326                                 x86_jump8 (code, 0);
5327                                 amd64_patch (unordered_check, code);
5328                                 amd64_inc_reg (code, ins->dreg);
5329                                 amd64_patch (jump_to_end, code);
5330                         }
5331                         break;
5332                 }
5333                 case OP_FCLT:
5334                 case OP_FCLT_UN:
5335                         /* zeroing the register at the start results in
5336                          * shorter and faster code (we can also remove the widening op)
5337                          */
5338                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5339                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5340                         if (ins->opcode == OP_FCLT_UN) {
5341                                 guchar *unordered_check = code;
5342                                 guchar *jump_to_end;
5343                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5344                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5345                                 jump_to_end = code;
5346                                 x86_jump8 (code, 0);
5347                                 amd64_patch (unordered_check, code);
5348                                 amd64_inc_reg (code, ins->dreg);
5349                                 amd64_patch (jump_to_end, code);
5350                         } else {
5351                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5352                         }
5353                         break;
5354                 case OP_FCLE: {
5355                         guchar *unordered_check;
5356                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5357                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5358                         unordered_check = code;
5359                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5360                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5361                         amd64_patch (unordered_check, code);
5362                         break;
5363                 }
5364                 case OP_FCGT:
5365                 case OP_FCGT_UN: {
5366                         /* zeroing the register at the start results in
5367                          * shorter and faster code (we can also remove the widening op)
5368                          */
5369                         guchar *unordered_check;
5370                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5371                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5372                         if (ins->opcode == OP_FCGT) {
5373                                 unordered_check = code;
5374                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5375                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5376                                 amd64_patch (unordered_check, code);
5377                         } else {
5378                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5379                         }
5380                         break;
5381                 }
5382                 case OP_FCGE: {
5383                         guchar *unordered_check;
5384                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5385                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5386                         unordered_check = code;
5387                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5388                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5389                         amd64_patch (unordered_check, code);
5390                         break;
5391                 }
5392
5393                 case OP_FCLT_MEMBASE:
5394                 case OP_FCGT_MEMBASE:
5395                 case OP_FCLT_UN_MEMBASE:
5396                 case OP_FCGT_UN_MEMBASE:
5397                 case OP_FCEQ_MEMBASE: {
5398                         guchar *unordered_check, *jump_to_end;
5399                         int x86_cond;
5400
5401                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5402                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5403
5404                         switch (ins->opcode) {
5405                         case OP_FCEQ_MEMBASE:
5406                                 x86_cond = X86_CC_EQ;
5407                                 break;
5408                         case OP_FCLT_MEMBASE:
5409                         case OP_FCLT_UN_MEMBASE:
5410                                 x86_cond = X86_CC_LT;
5411                                 break;
5412                         case OP_FCGT_MEMBASE:
5413                         case OP_FCGT_UN_MEMBASE:
5414                                 x86_cond = X86_CC_GT;
5415                                 break;
5416                         default:
5417                                 g_assert_not_reached ();
5418                         }
5419
5420                         unordered_check = code;
5421                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5422                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5423
5424                         switch (ins->opcode) {
5425                         case OP_FCEQ_MEMBASE:
5426                         case OP_FCLT_MEMBASE:
5427                         case OP_FCGT_MEMBASE:
5428                                 amd64_patch (unordered_check, code);
5429                                 break;
5430                         case OP_FCLT_UN_MEMBASE:
5431                         case OP_FCGT_UN_MEMBASE:
5432                                 jump_to_end = code;
5433                                 x86_jump8 (code, 0);
5434                                 amd64_patch (unordered_check, code);
5435                                 amd64_inc_reg (code, ins->dreg);
5436                                 amd64_patch (jump_to_end, code);
5437                                 break;
5438                         default:
5439                                 break;
5440                         }
5441                         break;
5442                 }
5443                 case OP_FBEQ: {
5444                         guchar *jump = code;
5445                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5446                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5447                         amd64_patch (jump, code);
5448                         break;
5449                 }
5450                 case OP_FBNE_UN:
5451                         /* Branch if C013 != 100 */
5452                         /* branch if !ZF or (PF|CF) */
5453                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5454                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5455                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5456                         break;
5457                 case OP_FBLT:
5458                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5459                         break;
5460                 case OP_FBLT_UN:
5461                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5462                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5463                         break;
5464                 case OP_FBGT:
5465                 case OP_FBGT_UN:
5466                         if (ins->opcode == OP_FBGT) {
5467                                 guchar *br1;
5468
5469                                 /* skip branch if C1=1 */
5470                                 br1 = code;
5471                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5472                                 /* branch if (C0 | C3) = 1 */
5473                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5474                                 amd64_patch (br1, code);
5475                                 break;
5476                         } else {
5477                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5478                         }
5479                         break;
5480                 case OP_FBGE: {
5481                         /* Branch if C013 == 100 or 001 */
5482                         guchar *br1;
5483
5484                         /* skip branch if C1=1 */
5485                         br1 = code;
5486                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5487                         /* branch if (C0 | C3) = 1 */
5488                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5489                         amd64_patch (br1, code);
5490                         break;
5491                 }
5492                 case OP_FBGE_UN:
5493                         /* Branch if C013 == 000 */
5494                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5495                         break;
5496                 case OP_FBLE: {
5497                         /* Branch if C013=000 or 100 */
5498                         guchar *br1;
5499
5500                         /* skip branch if C1=1 */
5501                         br1 = code;
5502                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5503                         /* branch if C0=0 */
5504                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5505                         amd64_patch (br1, code);
5506                         break;
5507                 }
5508                 case OP_FBLE_UN:
5509                         /* Branch if C013 != 001 */
5510                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5511                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5512                         break;
5513                 case OP_CKFINITE:
5514                         /* Transfer value to the fp stack */
5515                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5516                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5517                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5518
5519                         amd64_push_reg (code, AMD64_RAX);
5520                         amd64_fxam (code);
5521                         amd64_fnstsw (code);
5522                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5523                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5524                         amd64_pop_reg (code, AMD64_RAX);
5525                         amd64_fstp (code, 0);
5526                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5527                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5528                         break;
5529                 case OP_TLS_GET: {
5530                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5531                         break;
5532                 }
5533                 case OP_TLS_GET_REG:
5534                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5535                         break;
5536                 case OP_TLS_SET: {
5537                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5538                         break;
5539                 }
5540                 case OP_TLS_SET_REG: {
5541                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5542                         break;
5543                 }
5544                 case OP_MEMORY_BARRIER: {
5545                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5546                                 x86_mfence (code);
5547                         break;
5548                 }
5549                 case OP_ATOMIC_ADD_I4:
5550                 case OP_ATOMIC_ADD_I8: {
5551                         int dreg = ins->dreg;
5552                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5553
5554                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5555                                 dreg = AMD64_R11;
5556
5557                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5558                         amd64_prefix (code, X86_LOCK_PREFIX);
5559                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5560                         /* dreg contains the old value, add with sreg2 value */
5561                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5562
5563                         if (ins->dreg != dreg)
5564                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5565
5566                         break;
5567                 }
5568                 case OP_ATOMIC_EXCHANGE_I4:
5569                 case OP_ATOMIC_EXCHANGE_I8: {
5570                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5571
5572                         /* LOCK prefix is implied. */
5573                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5574                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5575                         break;
5576                 }
5577                 case OP_ATOMIC_CAS_I4:
5578                 case OP_ATOMIC_CAS_I8: {
5579                         guint32 size;
5580
5581                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5582                                 size = 8;
5583                         else
5584                                 size = 4;
5585
5586                         /*
5587                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5588                          * an explanation of how this works.
5589                          */
5590                         g_assert (ins->sreg3 == AMD64_RAX);
5591                         g_assert (ins->sreg1 != AMD64_RAX);
5592                         g_assert (ins->sreg1 != ins->sreg2);
5593
5594                         amd64_prefix (code, X86_LOCK_PREFIX);
5595                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5596
5597                         if (ins->dreg != AMD64_RAX)
5598                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5599                         break;
5600                 }
5601                 case OP_ATOMIC_LOAD_I1: {
5602                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5603                         break;
5604                 }
5605                 case OP_ATOMIC_LOAD_U1: {
5606                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5607                         break;
5608                 }
5609                 case OP_ATOMIC_LOAD_I2: {
5610                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5611                         break;
5612                 }
5613                 case OP_ATOMIC_LOAD_U2: {
5614                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5615                         break;
5616                 }
5617                 case OP_ATOMIC_LOAD_I4: {
5618                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5619                         break;
5620                 }
5621                 case OP_ATOMIC_LOAD_U4:
5622                 case OP_ATOMIC_LOAD_I8:
5623                 case OP_ATOMIC_LOAD_U8: {
5624                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5625                         break;
5626                 }
5627                 case OP_ATOMIC_LOAD_R4: {
5628                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5629                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5630                         break;
5631                 }
5632                 case OP_ATOMIC_LOAD_R8: {
5633                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5634                         break;
5635                 }
5636                 case OP_ATOMIC_STORE_I1:
5637                 case OP_ATOMIC_STORE_U1:
5638                 case OP_ATOMIC_STORE_I2:
5639                 case OP_ATOMIC_STORE_U2:
5640                 case OP_ATOMIC_STORE_I4:
5641                 case OP_ATOMIC_STORE_U4:
5642                 case OP_ATOMIC_STORE_I8:
5643                 case OP_ATOMIC_STORE_U8: {
5644                         int size;
5645
5646                         switch (ins->opcode) {
5647                         case OP_ATOMIC_STORE_I1:
5648                         case OP_ATOMIC_STORE_U1:
5649                                 size = 1;
5650                                 break;
5651                         case OP_ATOMIC_STORE_I2:
5652                         case OP_ATOMIC_STORE_U2:
5653                                 size = 2;
5654                                 break;
5655                         case OP_ATOMIC_STORE_I4:
5656                         case OP_ATOMIC_STORE_U4:
5657                                 size = 4;
5658                                 break;
5659                         case OP_ATOMIC_STORE_I8:
5660                         case OP_ATOMIC_STORE_U8:
5661                                 size = 8;
5662                                 break;
5663                         }
5664
5665                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5666
5667                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5668                                 x86_mfence (code);
5669                         break;
5670                 }
5671                 case OP_ATOMIC_STORE_R4: {
5672                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5673                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5674
5675                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5676                                 x86_mfence (code);
5677                         break;
5678                 }
5679                 case OP_ATOMIC_STORE_R8: {
5680                         x86_nop (code);
5681                         x86_nop (code);
5682                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5683                         x86_nop (code);
5684                         x86_nop (code);
5685
5686                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5687                                 x86_mfence (code);
5688                         break;
5689                 }
5690                 case OP_CARD_TABLE_WBARRIER: {
5691                         int ptr = ins->sreg1;
5692                         int value = ins->sreg2;
5693                         guchar *br = 0;
5694                         int nursery_shift, card_table_shift;
5695                         gpointer card_table_mask;
5696                         size_t nursery_size;
5697
5698                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5699                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5700                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5701
5702                         /*If either point to the stack we can simply avoid the WB. This happens due to
5703                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5704                          */
5705                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5706                                 continue;
5707
5708                         /*
5709                          * We need one register we can clobber, we choose EDX and make sreg1
5710                          * fixed EAX to work around limitations in the local register allocator.
5711                          * sreg2 might get allocated to EDX, but that is not a problem since
5712                          * we use it before clobbering EDX.
5713                          */
5714                         g_assert (ins->sreg1 == AMD64_RAX);
5715
5716                         /*
5717                          * This is the code we produce:
5718                          *
5719                          *   edx = value
5720                          *   edx >>= nursery_shift
5721                          *   cmp edx, (nursery_start >> nursery_shift)
5722                          *   jne done
5723                          *   edx = ptr
5724                          *   edx >>= card_table_shift
5725                          *   edx += cardtable
5726                          *   [edx] = 1
5727                          * done:
5728                          */
5729
5730                         if (mono_gc_card_table_nursery_check ()) {
5731                                 if (value != AMD64_RDX)
5732                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5733                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5734                                 if (shifted_nursery_start >> 31) {
5735                                         /*
5736                                          * The value we need to compare against is 64 bits, so we need
5737                                          * another spare register.  We use RBX, which we save and
5738                                          * restore.
5739                                          */
5740                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5741                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5742                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5743                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5744                                 } else {
5745                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5746                                 }
5747                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5748                         }
5749                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5750                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5751                         if (card_table_mask)
5752                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5753
5754                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5755                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5756
5757                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5758
5759                         if (mono_gc_card_table_nursery_check ())
5760                                 x86_patch (br, code);
5761                         break;
5762                 }
5763 #ifdef MONO_ARCH_SIMD_INTRINSICS
5764                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5765                 case OP_ADDPS:
5766                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5767                         break;
5768                 case OP_DIVPS:
5769                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5770                         break;
5771                 case OP_MULPS:
5772                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5773                         break;
5774                 case OP_SUBPS:
5775                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5776                         break;
5777                 case OP_MAXPS:
5778                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5779                         break;
5780                 case OP_MINPS:
5781                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5782                         break;
5783                 case OP_COMPPS:
5784                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5785                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5786                         break;
5787                 case OP_ANDPS:
5788                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5789                         break;
5790                 case OP_ANDNPS:
5791                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5792                         break;
5793                 case OP_ORPS:
5794                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5795                         break;
5796                 case OP_XORPS:
5797                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_SQRTPS:
5800                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5801                         break;
5802                 case OP_RSQRTPS:
5803                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5804                         break;
5805                 case OP_RCPPS:
5806                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5807                         break;
5808                 case OP_ADDSUBPS:
5809                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5810                         break;
5811                 case OP_HADDPS:
5812                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5813                         break;
5814                 case OP_HSUBPS:
5815                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5816                         break;
5817                 case OP_DUPPS_HIGH:
5818                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5819                         break;
5820                 case OP_DUPPS_LOW:
5821                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5822                         break;
5823
5824                 case OP_PSHUFLEW_HIGH:
5825                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5826                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5827                         break;
5828                 case OP_PSHUFLEW_LOW:
5829                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5830                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5831                         break;
5832                 case OP_PSHUFLED:
5833                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5834                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5835                         break;
5836                 case OP_SHUFPS:
5837                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5838                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5839                         break;
5840                 case OP_SHUFPD:
5841                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5842                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5843                         break;
5844
5845                 case OP_ADDPD:
5846                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_DIVPD:
5849                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851                 case OP_MULPD:
5852                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5853                         break;
5854                 case OP_SUBPD:
5855                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5856                         break;
5857                 case OP_MAXPD:
5858                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5859                         break;
5860                 case OP_MINPD:
5861                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5862                         break;
5863                 case OP_COMPPD:
5864                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5865                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5866                         break;
5867                 case OP_ANDPD:
5868                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_ANDNPD:
5871                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_ORPD:
5874                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 case OP_XORPD:
5877                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 case OP_SQRTPD:
5880                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5881                         break;
5882                 case OP_ADDSUBPD:
5883                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_HADDPD:
5886                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887                         break;
5888                 case OP_HSUBPD:
5889                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5890                         break;
5891                 case OP_DUPPD:
5892                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5893                         break;
5894
5895                 case OP_EXTRACT_MASK:
5896                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5897                         break;
5898
5899                 case OP_PAND:
5900                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902                 case OP_POR:
5903                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_PXOR:
5906                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5907                         break;
5908
5909                 case OP_PADDB:
5910                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_PADDW:
5913                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_PADDD:
5916                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_PADDQ:
5919                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921
5922                 case OP_PSUBB:
5923                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_PSUBW:
5926                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_PSUBD:
5929                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_PSUBQ:
5932                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934
5935                 case OP_PMAXB_UN:
5936                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_PMAXW_UN:
5939                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_PMAXD_UN:
5942                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944
5945                 case OP_PMAXB:
5946                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_PMAXW:
5949                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_PMAXD:
5952                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954
5955                 case OP_PAVGB_UN:
5956                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_PAVGW_UN:
5959                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961
5962                 case OP_PMINB_UN:
5963                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PMINW_UN:
5966                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968                 case OP_PMIND_UN:
5969                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971
5972                 case OP_PMINB:
5973                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMINW:
5976                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_PMIND:
5979                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981
5982                 case OP_PCMPEQB:
5983                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PCMPEQW:
5986                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_PCMPEQD:
5989                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_PCMPEQQ:
5992                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994
5995                 case OP_PCMPGTB:
5996                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PCMPGTW:
5999                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PCMPGTD:
6002                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_PCMPGTQ:
6005                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007
6008                 case OP_PSUM_ABS_DIFF:
6009                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011
6012                 case OP_UNPACK_LOWB:
6013                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_UNPACK_LOWW:
6016                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_UNPACK_LOWD:
6019                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_UNPACK_LOWQ:
6022                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_UNPACK_LOWPS:
6025                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_UNPACK_LOWPD:
6028                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030
6031                 case OP_UNPACK_HIGHB:
6032                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_UNPACK_HIGHW:
6035                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_UNPACK_HIGHD:
6038                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_UNPACK_HIGHQ:
6041                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_UNPACK_HIGHPS:
6044                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_UNPACK_HIGHPD:
6047                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049
6050                 case OP_PACKW:
6051                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_PACKD:
6054                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_PACKW_UN:
6057                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_PACKD_UN:
6060                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062
6063                 case OP_PADDB_SAT_UN:
6064                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_PSUBB_SAT_UN:
6067                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PADDW_SAT_UN:
6070                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PSUBW_SAT_UN:
6073                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075
6076                 case OP_PADDB_SAT:
6077                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PSUBB_SAT:
6080                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PADDW_SAT:
6083                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085                 case OP_PSUBW_SAT:
6086                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088
6089                 case OP_PMULW:
6090                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PMULD:
6093                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PMULQ:
6096                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_PMULW_HIGH_UN:
6099                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_PMULW_HIGH:
6102                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104
6105                 case OP_PSHRW:
6106                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6107                         break;
6108                 case OP_PSHRW_REG:
6109                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6110                         break;
6111
6112                 case OP_PSARW:
6113                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6114                         break;
6115                 case OP_PSARW_REG:
6116                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6117                         break;
6118
6119                 case OP_PSHLW:
6120                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6121                         break;
6122                 case OP_PSHLW_REG:
6123                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6124                         break;
6125
6126                 case OP_PSHRD:
6127                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6128                         break;
6129                 case OP_PSHRD_REG:
6130                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6131                         break;
6132
6133                 case OP_PSARD:
6134                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6135                         break;
6136                 case OP_PSARD_REG:
6137                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6138                         break;
6139
6140                 case OP_PSHLD:
6141                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6142                         break;
6143                 case OP_PSHLD_REG:
6144                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6145                         break;
6146
6147                 case OP_PSHRQ:
6148                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6149                         break;
6150                 case OP_PSHRQ_REG:
6151                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6152                         break;
6153
6154                 /*TODO: This is appart of the sse spec but not added
6155                 case OP_PSARQ:
6156                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6157                         break;
6158                 case OP_PSARQ_REG:
6159                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6160                         break;
6161                 */
6162
6163                 case OP_PSHLQ:
6164                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6165                         break;
6166                 case OP_PSHLQ_REG:
6167                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6168                         break;
6169                 case OP_CVTDQ2PD:
6170                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6171                         break;
6172                 case OP_CVTDQ2PS:
6173                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6174                         break;
6175                 case OP_CVTPD2DQ:
6176                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6177                         break;
6178                 case OP_CVTPD2PS:
6179                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6180                         break;
6181                 case OP_CVTPS2DQ:
6182                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6183                         break;
6184                 case OP_CVTPS2PD:
6185                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6186                         break;
6187                 case OP_CVTTPD2DQ:
6188                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6189                         break;
6190                 case OP_CVTTPS2DQ:
6191                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6192                         break;
6193
6194                 case OP_ICONV_TO_X:
6195                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6196                         break;
6197                 case OP_EXTRACT_I4:
6198                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6199                         break;
6200                 case OP_EXTRACT_I8:
6201                         if (ins->inst_c0) {
6202                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6203                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6204                         } else {
6205                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6206                         }
6207                         break;
6208                 case OP_EXTRACT_I1:
6209                 case OP_EXTRACT_U1:
6210                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6211                         if (ins->inst_c0)
6212                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6213                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6214                         break;
6215                 case OP_EXTRACT_I2:
6216                 case OP_EXTRACT_U2:
6217                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6218                         if (ins->inst_c0)
6219                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6220                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6221                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6222                         break;
6223                 case OP_EXTRACT_R8:
6224                         if (ins->inst_c0)
6225                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6226                         else
6227                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6228                         break;
6229                 case OP_INSERT_I2:
6230                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6231                         break;
6232                 case OP_EXTRACTX_U2:
6233                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6234                         break;
6235                 case OP_INSERTX_U1_SLOW:
6236                         /*sreg1 is the extracted ireg (scratch)
6237                         /sreg2 is the to be inserted ireg (scratch)
6238                         /dreg is the xreg to receive the value*/
6239
6240                         /*clear the bits from the extracted word*/
6241                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6242                         /*shift the value to insert if needed*/
6243                         if (ins->inst_c0 & 1)
6244                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6245                         /*join them together*/
6246                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6247                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6248                         break;
6249                 case OP_INSERTX_I4_SLOW:
6250                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6251                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6252                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6253                         break;
6254                 case OP_INSERTX_I8_SLOW:
6255                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6256                         if (ins->inst_c0)
6257                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6258                         else
6259                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6260                         break;
6261
6262                 case OP_INSERTX_R4_SLOW:
6263                         switch (ins->inst_c0) {
6264                         case 0:
6265                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6266                                 break;
6267                         case 1:
6268                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6269                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6270                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6271                                 break;
6272                         case 2:
6273                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6274                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6275                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6276                                 break;
6277                         case 3:
6278                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6279                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6280                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6281                                 break;
6282                         }
6283                         break;
6284                 case OP_INSERTX_R8_SLOW:
6285                         if (ins->inst_c0)
6286                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6287                         else
6288                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6289                         break;
6290                 case OP_STOREX_MEMBASE_REG:
6291                 case OP_STOREX_MEMBASE:
6292                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6293                         break;
6294                 case OP_LOADX_MEMBASE:
6295                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6296                         break;
6297                 case OP_LOADX_ALIGNED_MEMBASE:
6298                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6299                         break;
6300                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6301                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6302                         break;
6303                 case OP_STOREX_NTA_MEMBASE_REG:
6304                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6305                         break;
6306                 case OP_PREFETCH_MEMBASE:
6307                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6308                         break;
6309
6310                 case OP_XMOVE:
6311                         /*FIXME the peephole pass should have killed this*/
6312                         if (ins->dreg != ins->sreg1)
6313                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6314                         break;
6315                 case OP_XZERO:
6316                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6317                         break;
6318                 case OP_ICONV_TO_R8_RAW:
6319                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6320                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6321                         break;
6322
6323                 case OP_FCONV_TO_R8_X:
6324                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6325                         break;
6326
6327                 case OP_XCONV_R8_TO_I4:
6328                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6329                         switch (ins->backend.source_opcode) {
6330                         case OP_FCONV_TO_I1:
6331                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6332                                 break;
6333                         case OP_FCONV_TO_U1:
6334                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6335                                 break;
6336                         case OP_FCONV_TO_I2:
6337                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6338                                 break;
6339                         case OP_FCONV_TO_U2:
6340                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6341                                 break;
6342                         }
6343                         break;
6344
6345                 case OP_EXPAND_I2:
6346                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6347                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6348                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6349                         break;
6350                 case OP_EXPAND_I4:
6351                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6352                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6353                         break;
6354                 case OP_EXPAND_I8:
6355                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6356                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6357                         break;
6358                 case OP_EXPAND_R4:
6359                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6360                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6361                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6362                         break;
6363                 case OP_EXPAND_R8:
6364                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6365                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6366                         break;
6367 #endif
6368                 case OP_LIVERANGE_START: {
6369                         if (cfg->verbose_level > 1)
6370                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6371                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6372                         break;
6373                 }
6374                 case OP_LIVERANGE_END: {
6375                         if (cfg->verbose_level > 1)
6376                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6377                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6378                         break;
6379                 }
6380                 case OP_NACL_GC_SAFE_POINT: {
6381 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6382                         if (cfg->compile_aot)
6383                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6384                         else {
6385                                 guint8 *br [1];
6386
6387                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6388                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6389                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6390                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6391                                 amd64_patch (br[0], code);
6392                         }
6393 #endif
6394                         break;
6395                 }
6396                 case OP_GC_LIVENESS_DEF:
6397                 case OP_GC_LIVENESS_USE:
6398                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6399                         ins->backend.pc_offset = code - cfg->native_code;
6400                         break;
6401                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6402                         ins->backend.pc_offset = code - cfg->native_code;
6403                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6404                         break;
6405                 default:
6406                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6407                         g_assert_not_reached ();
6408                 }
6409
6410                 if ((code - cfg->native_code - offset) > max_len) {
6411 #if !defined(__native_client_codegen__)
6412                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6413                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6414                         g_assert_not_reached ();
6415 #endif
6416                 }
6417
6418                 last_ins = ins;
6419                 last_offset = offset;
6420         }
6421
6422         cfg->code_len = code - cfg->native_code;
6423 }
6424
6425 #endif /* DISABLE_JIT */
6426
6427 void
6428 mono_arch_register_lowlevel_calls (void)
6429 {
6430         /* The signature doesn't matter */
6431         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6432 }
6433
6434 void
6435 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6436 {
6437         MonoJumpInfo *patch_info;
6438         gboolean compile_aot = !run_cctors;
6439
6440         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6441                 unsigned char *ip = patch_info->ip.i + code;
6442                 unsigned char *target;
6443
6444                 if (compile_aot) {
6445                         switch (patch_info->type) {
6446                         case MONO_PATCH_INFO_BB:
6447                         case MONO_PATCH_INFO_LABEL:
6448                                 break;
6449                         default:
6450                                 /* No need to patch these */
6451                                 continue;
6452                         }
6453                 }
6454
6455                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6456
6457                 switch (patch_info->type) {
6458                 case MONO_PATCH_INFO_NONE:
6459                         continue;
6460                 case MONO_PATCH_INFO_METHOD_REL:
6461                 case MONO_PATCH_INFO_R8:
6462                 case MONO_PATCH_INFO_R4:
6463                         g_assert_not_reached ();
6464                         continue;
6465                 case MONO_PATCH_INFO_BB:
6466                         break;
6467                 default:
6468                         break;
6469                 }
6470
6471                 /*
6472                  * Debug code to help track down problems where the target of a near call is
6473                  * is not valid.
6474                  */
6475                 if (amd64_is_near_call (ip)) {
6476                         gint64 disp = (guint8*)target - (guint8*)ip;
6477
6478                         if (!amd64_is_imm32 (disp)) {
6479                                 printf ("TYPE: %d\n", patch_info->type);
6480                                 switch (patch_info->type) {
6481                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6482                                         printf ("V: %s\n", patch_info->data.name);
6483                                         break;
6484                                 case MONO_PATCH_INFO_METHOD_JUMP:
6485                                 case MONO_PATCH_INFO_METHOD:
6486                                         printf ("V: %s\n", patch_info->data.method->name);
6487                                         break;
6488                                 default:
6489                                         break;
6490                                 }
6491                         }
6492                 }
6493
6494                 amd64_patch (ip, (gpointer)target);
6495         }
6496 }
6497
6498 #ifndef DISABLE_JIT
6499
6500 static int
6501 get_max_epilog_size (MonoCompile *cfg)
6502 {
6503         int max_epilog_size = 16;
6504
6505         if (cfg->method->save_lmf)
6506                 max_epilog_size += 256;
6507
6508         if (mono_jit_trace_calls != NULL)
6509                 max_epilog_size += 50;
6510
6511         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6512                 max_epilog_size += 50;
6513
6514         max_epilog_size += (AMD64_NREG * 2);
6515
6516         return max_epilog_size;
6517 }
6518
6519 /*
6520  * This macro is used for testing whenever the unwinder works correctly at every point
6521  * where an async exception can happen.
6522  */
6523 /* This will generate a SIGSEGV at the given point in the code */
6524 #define async_exc_point(code) do { \
6525     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6526          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6527              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6528          cfg->arch.async_point_count ++; \
6529     } \
6530 } while (0)
6531
6532 guint8 *
6533 mono_arch_emit_prolog (MonoCompile *cfg)
6534 {
6535         MonoMethod *method = cfg->method;
6536         MonoBasicBlock *bb;
6537         MonoMethodSignature *sig;
6538         MonoInst *ins;
6539         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6540         guint8 *code;
6541         CallInfo *cinfo;
6542         MonoInst *lmf_var = cfg->lmf_var;
6543         gboolean args_clobbered = FALSE;
6544         gboolean trace = FALSE;
6545 #ifdef __native_client_codegen__
6546         guint alignment_check;
6547 #endif
6548
6549         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6550
6551 #if defined(__default_codegen__)
6552         code = cfg->native_code = g_malloc (cfg->code_size);
6553 #elif defined(__native_client_codegen__)
6554         /* native_code_alloc is not 32-byte aligned, native_code is. */
6555         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6556
6557         /* Align native_code to next nearest kNaclAlignment byte. */
6558         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6559         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6560
6561         code = cfg->native_code;
6562
6563         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6564         g_assert (alignment_check == 0);
6565 #endif
6566
6567         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6568                 trace = TRUE;
6569
6570         /* Amount of stack space allocated by register saving code */
6571         pos = 0;
6572
6573         /* Offset between RSP and the CFA */
6574         cfa_offset = 0;
6575
6576         /*
6577          * The prolog consists of the following parts:
6578          * FP present:
6579          * - push rbp, mov rbp, rsp
6580          * - save callee saved regs using pushes
6581          * - allocate frame
6582          * - save rgctx if needed
6583          * - save lmf if needed
6584          * FP not present:
6585          * - allocate frame
6586          * - save rgctx if needed
6587          * - save lmf if needed
6588          * - save callee saved regs using moves
6589          */
6590
6591         // CFA = sp + 8
6592         cfa_offset = 8;
6593         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6594         // IP saved at CFA - 8
6595         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6596         async_exc_point (code);
6597         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6598
6599         if (!cfg->arch.omit_fp) {
6600                 amd64_push_reg (code, AMD64_RBP);
6601                 cfa_offset += 8;
6602                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6603                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6604                 async_exc_point (code);
6605 #ifdef HOST_WIN32
6606                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6607 #endif
6608                 /* These are handled automatically by the stack marking code */
6609                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6610
6611                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6612                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6613                 async_exc_point (code);
6614 #ifdef HOST_WIN32
6615                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6616 #endif
6617         }
6618
6619         /* The param area is always at offset 0 from sp */
6620         /* This needs to be allocated here, since it has to come after the spill area */
6621         if (cfg->param_area) {
6622                 if (cfg->arch.omit_fp)
6623                         // FIXME:
6624                         g_assert_not_reached ();
6625                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6626         }
6627
6628         if (cfg->arch.omit_fp) {
6629                 /*
6630                  * On enter, the stack is misaligned by the pushing of the return
6631                  * address. It is either made aligned by the pushing of %rbp, or by
6632                  * this.
6633                  */
6634                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6635                 if ((alloc_size % 16) == 0) {
6636                         alloc_size += 8;
6637                         /* Mark the padding slot as NOREF */
6638                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6639                 }
6640         } else {
6641                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6642                 if (cfg->stack_offset != alloc_size) {
6643                         /* Mark the padding slot as NOREF */
6644                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6645                 }
6646                 cfg->arch.sp_fp_offset = alloc_size;
6647                 alloc_size -= pos;
6648         }
6649
6650         cfg->arch.stack_alloc_size = alloc_size;
6651
6652         /* Allocate stack frame */
6653         if (alloc_size) {
6654                 /* See mono_emit_stack_alloc */
6655 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6656                 guint32 remaining_size = alloc_size;
6657                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6658                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6659                 guint32 offset = code - cfg->native_code;
6660                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6661                         while (required_code_size >= (cfg->code_size - offset))
6662                                 cfg->code_size *= 2;
6663                         cfg->native_code = mono_realloc_native_code (cfg);
6664                         code = cfg->native_code + offset;
6665                         cfg->stat_code_reallocs++;
6666                 }
6667
6668                 while (remaining_size >= 0x1000) {
6669                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6670                         if (cfg->arch.omit_fp) {
6671                                 cfa_offset += 0x1000;
6672                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6673                         }
6674                         async_exc_point (code);
6675 #ifdef HOST_WIN32
6676                         if (cfg->arch.omit_fp)
6677                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6678 #endif
6679
6680                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6681                         remaining_size -= 0x1000;
6682                 }
6683                 if (remaining_size) {
6684                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6685                         if (cfg->arch.omit_fp) {
6686                                 cfa_offset += remaining_size;
6687                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6688                                 async_exc_point (code);
6689                         }
6690 #ifdef HOST_WIN32
6691                         if (cfg->arch.omit_fp)
6692                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6693 #endif
6694                 }
6695 #else
6696                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6697                 if (cfg->arch.omit_fp) {
6698                         cfa_offset += alloc_size;
6699                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6700                         async_exc_point (code);
6701                 }
6702 #endif
6703         }
6704
6705         /* Stack alignment check */
6706 #if 0
6707         {
6708                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6709                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6710                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6711                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6712                 amd64_breakpoint (code);
6713         }
6714 #endif
6715
6716         if (mini_get_debug_options ()->init_stacks) {
6717                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6718
6719                 /* Save registers to the red zone */
6720                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6721                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6722
6723                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6724                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6725                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6726
6727                 amd64_cld (code);
6728 #if defined(__default_codegen__)
6729                 amd64_prefix (code, X86_REP_PREFIX);
6730                 amd64_stosl (code);
6731 #elif defined(__native_client_codegen__)
6732                 /* NaCl stos pseudo-instruction */
6733                 amd64_codegen_pre (code);
6734                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6735                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6736                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6737                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6738                 amd64_prefix (code, X86_REP_PREFIX);
6739                 amd64_stosl (code);
6740                 amd64_codegen_post (code);
6741 #endif /* __native_client_codegen__ */
6742
6743                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6744                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6745         }
6746
6747         /* Save LMF */
6748         if (method->save_lmf)
6749                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6750
6751         /* Save callee saved registers */
6752         if (cfg->arch.omit_fp) {
6753                 save_area_offset = cfg->arch.reg_save_area_offset;
6754                 /* Save caller saved registers after sp is adjusted */
6755                 /* The registers are saved at the bottom of the frame */
6756                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6757         } else {
6758                 /* The registers are saved just below the saved rbp */
6759                 save_area_offset = cfg->arch.reg_save_area_offset;
6760         }
6761
6762         for (i = 0; i < AMD64_NREG; ++i) {
6763                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6764                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6765
6766                         if (cfg->arch.omit_fp) {
6767                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6768                                 /* These are handled automatically by the stack marking code */
6769                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6770                         } else {
6771                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6772                                 // FIXME: GC
6773                         }
6774
6775                         save_area_offset += 8;
6776                         async_exc_point (code);
6777                 }
6778         }
6779
6780         /* store runtime generic context */
6781         if (cfg->rgctx_var) {
6782                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6783                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6784
6785                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6786
6787                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6788                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6789         }
6790
6791         /* compute max_length in order to use short forward jumps */
6792         max_epilog_size = get_max_epilog_size (cfg);
6793         if (cfg->opt & MONO_OPT_BRANCH) {
6794                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6795                         MonoInst *ins;
6796                         int max_length = 0;
6797
6798                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6799                                 max_length += 6;
6800                         /* max alignment for loops */
6801                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6802                                 max_length += LOOP_ALIGNMENT;
6803 #ifdef __native_client_codegen__
6804                         /* max alignment for native client */
6805                         max_length += kNaClAlignment;
6806 #endif
6807
6808                         MONO_BB_FOR_EACH_INS (bb, ins) {
6809 #ifdef __native_client_codegen__
6810                                 {
6811                                         int space_in_block = kNaClAlignment -
6812                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6813                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6814                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6815                                                 max_length += space_in_block;
6816                                         }
6817                                 }
6818 #endif  /*__native_client_codegen__*/
6819                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6820                         }
6821
6822                         /* Take prolog and epilog instrumentation into account */
6823                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6824                                 max_length += max_epilog_size;
6825
6826                         bb->max_length = max_length;
6827                 }
6828         }
6829
6830         sig = mono_method_signature (method);
6831         pos = 0;
6832
6833         cinfo = cfg->arch.cinfo;
6834
6835         if (sig->ret->type != MONO_TYPE_VOID) {
6836                 /* Save volatile arguments to the stack */
6837                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6838                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6839         }
6840
6841         /* Keep this in sync with emit_load_volatile_arguments */
6842         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6843                 ArgInfo *ainfo = cinfo->args + i;
6844                 gint32 stack_offset;
6845                 MonoType *arg_type;
6846
6847                 ins = cfg->args [i];
6848
6849                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6850                         /* Unused arguments */
6851                         continue;
6852
6853                 if (sig->hasthis && (i == 0))
6854                         arg_type = &mono_defaults.object_class->byval_arg;
6855                 else
6856                         arg_type = sig->params [i - sig->hasthis];
6857
6858                 stack_offset = ainfo->offset + ARGS_OFFSET;
6859
6860                 if (cfg->globalra) {
6861                         /* All the other moves are done by the register allocator */
6862                         switch (ainfo->storage) {
6863                         case ArgInFloatSSEReg:
6864                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6865                                 break;
6866                         case ArgValuetypeInReg:
6867                                 for (quad = 0; quad < 2; quad ++) {
6868                                         switch (ainfo->pair_storage [quad]) {
6869                                         case ArgInIReg:
6870                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6871                                                 break;
6872                                         case ArgInFloatSSEReg:
6873                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6874                                                 break;
6875                                         case ArgInDoubleSSEReg:
6876                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6877                                                 break;
6878                                         case ArgNone:
6879                                                 break;
6880                                         default:
6881                                                 g_assert_not_reached ();
6882                                         }
6883                                 }
6884                                 break;
6885                         default:
6886                                 break;
6887                         }
6888
6889                         continue;
6890                 }
6891
6892                 /* Save volatile arguments to the stack */
6893                 if (ins->opcode != OP_REGVAR) {
6894                         switch (ainfo->storage) {
6895                         case ArgInIReg: {
6896                                 guint32 size = 8;
6897
6898                                 /* FIXME: I1 etc */
6899                                 /*
6900                                 if (stack_offset & 0x1)
6901                                         size = 1;
6902                                 else if (stack_offset & 0x2)
6903                                         size = 2;
6904                                 else if (stack_offset & 0x4)
6905                                         size = 4;
6906                                 else
6907                                         size = 8;
6908                                 */
6909                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6910
6911                                 /*
6912                                  * Save the original location of 'this',
6913                                  * get_generic_info_from_stack_frame () needs this to properly look up
6914                                  * the argument value during the handling of async exceptions.
6915                                  */
6916                                 if (ins == cfg->args [0]) {
6917                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6918                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6919                                 }
6920                                 break;
6921                         }
6922                         case ArgInFloatSSEReg:
6923                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6924                                 break;
6925                         case ArgInDoubleSSEReg:
6926                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6927                                 break;
6928                         case ArgValuetypeInReg:
6929                                 for (quad = 0; quad < 2; quad ++) {
6930                                         switch (ainfo->pair_storage [quad]) {
6931                                         case ArgInIReg:
6932                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6933                                                 break;
6934                                         case ArgInFloatSSEReg:
6935                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6936                                                 break;
6937                                         case ArgInDoubleSSEReg:
6938                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6939                                                 break;
6940                                         case ArgNone:
6941                                                 break;
6942                                         default:
6943                                                 g_assert_not_reached ();
6944                                         }
6945                                 }
6946                                 break;
6947                         case ArgValuetypeAddrInIReg:
6948                                 if (ainfo->pair_storage [0] == ArgInIReg)
6949                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6950                                 break;
6951                         default:
6952                                 break;
6953                         }
6954                 } else {
6955                         /* Argument allocated to (non-volatile) register */
6956                         switch (ainfo->storage) {
6957                         case ArgInIReg:
6958                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6959                                 break;
6960                         case ArgOnStack:
6961                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6962                                 break;
6963                         default:
6964                                 g_assert_not_reached ();
6965                         }
6966
6967                         if (ins == cfg->args [0]) {
6968                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6969                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6970                         }
6971                 }
6972         }
6973
6974         if (cfg->method->save_lmf)
6975                 args_clobbered = TRUE;
6976
6977         if (trace) {
6978                 args_clobbered = TRUE;
6979                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6980         }
6981
6982         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6983                 args_clobbered = TRUE;
6984
6985         /*
6986          * Optimize the common case of the first bblock making a call with the same
6987          * arguments as the method. This works because the arguments are still in their
6988          * original argument registers.
6989          * FIXME: Generalize this
6990          */
6991         if (!args_clobbered) {
6992                 MonoBasicBlock *first_bb = cfg->bb_entry;
6993                 MonoInst *next;
6994                 int filter = FILTER_IL_SEQ_POINT;
6995
6996                 next = mono_bb_first_inst (first_bb, filter);
6997                 if (!next && first_bb->next_bb) {
6998                         first_bb = first_bb->next_bb;
6999                         next = mono_bb_first_inst (first_bb, filter);
7000                 }
7001
7002                 if (first_bb->in_count > 1)
7003                         next = NULL;
7004
7005                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7006                         ArgInfo *ainfo = cinfo->args + i;
7007                         gboolean match = FALSE;
7008
7009                         ins = cfg->args [i];
7010                         if (ins->opcode != OP_REGVAR) {
7011                                 switch (ainfo->storage) {
7012                                 case ArgInIReg: {
7013                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7014                                                 if (next->dreg == ainfo->reg) {
7015                                                         NULLIFY_INS (next);
7016                                                         match = TRUE;
7017                                                 } else {
7018                                                         next->opcode = OP_MOVE;
7019                                                         next->sreg1 = ainfo->reg;
7020                                                         /* Only continue if the instruction doesn't change argument regs */
7021                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7022                                                                 match = TRUE;
7023                                                 }
7024                                         }
7025                                         break;
7026                                 }
7027                                 default:
7028                                         break;
7029                                 }
7030                         } else {
7031                                 /* Argument allocated to (non-volatile) register */
7032                                 switch (ainfo->storage) {
7033                                 case ArgInIReg:
7034                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7035                                                 NULLIFY_INS (next);
7036                                                 match = TRUE;
7037                                         }
7038                                         break;
7039                                 default:
7040                                         break;
7041                                 }
7042                         }
7043
7044                         if (match) {
7045                                 next = mono_inst_next (next, filter);
7046                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7047                                 if (!next)
7048                                         break;
7049                         }
7050                 }
7051         }
7052
7053         if (cfg->gen_seq_points_debug_data) {
7054                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7055
7056                 /* Initialize seq_point_info_var */
7057                 if (cfg->compile_aot) {
7058                         /* Initialize the variable from a GOT slot */
7059                         /* Same as OP_AOTCONST */
7060                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7061                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7062                         g_assert (info_var->opcode == OP_REGOFFSET);
7063                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7064                 }
7065
7066                 /* Initialize ss_trigger_page_var */
7067                 ins = cfg->arch.ss_trigger_page_var;
7068
7069                 g_assert (ins->opcode == OP_REGOFFSET);
7070
7071                 if (cfg->compile_aot) {
7072                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7073                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7074                 } else {
7075                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7076                 }
7077                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7078         }
7079
7080         cfg->code_len = code - cfg->native_code;
7081
7082         g_assert (cfg->code_len < cfg->code_size);
7083
7084         return code;
7085 }
7086
7087 void
7088 mono_arch_emit_epilog (MonoCompile *cfg)
7089 {
7090         MonoMethod *method = cfg->method;
7091         int quad, pos, i;
7092         guint8 *code;
7093         int max_epilog_size;
7094         CallInfo *cinfo;
7095         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7096         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7097
7098         max_epilog_size = get_max_epilog_size (cfg);
7099
7100         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7101                 cfg->code_size *= 2;
7102                 cfg->native_code = mono_realloc_native_code (cfg);
7103                 cfg->stat_code_reallocs++;
7104         }
7105         code = cfg->native_code + cfg->code_len;
7106
7107         cfg->has_unwind_info_for_epilog = TRUE;
7108
7109         /* Mark the start of the epilog */
7110         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7111
7112         /* Save the uwind state which is needed by the out-of-line code */
7113         mono_emit_unwind_op_remember_state (cfg, code);
7114
7115         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7116                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7117
7118         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7119         pos = 0;
7120
7121         if (method->save_lmf) {
7122                 /* check if we need to restore protection of the stack after a stack overflow */
7123                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7124                         guint8 *patch;
7125                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7126                         /* we load the value in a separate instruction: this mechanism may be
7127                          * used later as a safer way to do thread interruption
7128                          */
7129                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7130                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7131                         patch = code;
7132                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7133                         /* note that the call trampoline will preserve eax/edx */
7134                         x86_call_reg (code, X86_ECX);
7135                         x86_patch (patch, code);
7136                 } else {
7137                         /* FIXME: maybe save the jit tls in the prolog */
7138                 }
7139                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7140                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7141                 }
7142         }
7143
7144         /* Restore callee saved regs */
7145         for (i = 0; i < AMD64_NREG; ++i) {
7146                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7147                         /* Restore only used_int_regs, not arch.saved_iregs */
7148                         if (cfg->used_int_regs & (1 << i)) {
7149                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7150                                 mono_emit_unwind_op_same_value (cfg, code, i);
7151                                 async_exc_point (code);
7152                         }
7153                         save_area_offset += 8;
7154                 }
7155         }
7156
7157         /* Load returned vtypes into registers if needed */
7158         cinfo = cfg->arch.cinfo;
7159         if (cinfo->ret.storage == ArgValuetypeInReg) {
7160                 ArgInfo *ainfo = &cinfo->ret;
7161                 MonoInst *inst = cfg->ret;
7162
7163                 for (quad = 0; quad < 2; quad ++) {
7164                         switch (ainfo->pair_storage [quad]) {
7165                         case ArgInIReg:
7166                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7167                                 break;
7168                         case ArgInFloatSSEReg:
7169                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7170                                 break;
7171                         case ArgInDoubleSSEReg:
7172                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7173                                 break;
7174                         case ArgNone:
7175                                 break;
7176                         default:
7177                                 g_assert_not_reached ();
7178                         }
7179                 }
7180         }
7181
7182         if (cfg->arch.omit_fp) {
7183                 if (cfg->arch.stack_alloc_size) {
7184                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7185                 }
7186         } else {
7187                 amd64_leave (code);
7188                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7189         }
7190         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7191         async_exc_point (code);
7192         amd64_ret (code);
7193
7194         /* Restore the unwind state to be the same as before the epilog */
7195         mono_emit_unwind_op_restore_state (cfg, code);
7196
7197         cfg->code_len = code - cfg->native_code;
7198
7199         g_assert (cfg->code_len < cfg->code_size);
7200 }
7201
7202 void
7203 mono_arch_emit_exceptions (MonoCompile *cfg)
7204 {
7205         MonoJumpInfo *patch_info;
7206         int nthrows, i;
7207         guint8 *code;
7208         MonoClass *exc_classes [16];
7209         guint8 *exc_throw_start [16], *exc_throw_end [16];
7210         guint32 code_size = 0;
7211
7212         /* Compute needed space */
7213         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7214                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7215                         code_size += 40;
7216                 if (patch_info->type == MONO_PATCH_INFO_R8)
7217                         code_size += 8 + 15; /* sizeof (double) + alignment */
7218                 if (patch_info->type == MONO_PATCH_INFO_R4)
7219                         code_size += 4 + 15; /* sizeof (float) + alignment */
7220                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7221                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7222         }
7223
7224 #ifdef __native_client_codegen__
7225         /* Give us extra room on Native Client.  This could be   */
7226         /* more carefully calculated, but bundle alignment makes */
7227         /* it much trickier, so *2 like other places is good.    */
7228         code_size *= 2;
7229 #endif
7230
7231         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7232                 cfg->code_size *= 2;
7233                 cfg->native_code = mono_realloc_native_code (cfg);
7234                 cfg->stat_code_reallocs++;
7235         }
7236
7237         code = cfg->native_code + cfg->code_len;
7238
7239         /* add code to raise exceptions */
7240         nthrows = 0;
7241         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7242                 switch (patch_info->type) {
7243                 case MONO_PATCH_INFO_EXC: {
7244                         MonoClass *exc_class;
7245                         guint8 *buf, *buf2;
7246                         guint32 throw_ip;
7247
7248                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7249
7250                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7251                         g_assert (exc_class);
7252                         throw_ip = patch_info->ip.i;
7253
7254                         //x86_breakpoint (code);
7255                         /* Find a throw sequence for the same exception class */
7256                         for (i = 0; i < nthrows; ++i)
7257                                 if (exc_classes [i] == exc_class)
7258                                         break;
7259                         if (i < nthrows) {
7260                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7261                                 x86_jump_code (code, exc_throw_start [i]);
7262                                 patch_info->type = MONO_PATCH_INFO_NONE;
7263                         }
7264                         else {
7265                                 buf = code;
7266                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7267                                 buf2 = code;
7268
7269                                 if (nthrows < 16) {
7270                                         exc_classes [nthrows] = exc_class;
7271                                         exc_throw_start [nthrows] = code;
7272                                 }
7273                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7274
7275                                 patch_info->type = MONO_PATCH_INFO_NONE;
7276
7277                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7278
7279                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7280                                 while (buf < buf2)
7281                                         x86_nop (buf);
7282
7283                                 if (nthrows < 16) {
7284                                         exc_throw_end [nthrows] = code;
7285                                         nthrows ++;
7286                                 }
7287                         }
7288                         break;
7289                 }
7290                 default:
7291                         /* do nothing */
7292                         break;
7293                 }
7294                 g_assert(code < cfg->native_code + cfg->code_size);
7295         }
7296
7297         /* Handle relocations with RIP relative addressing */
7298         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7299                 gboolean remove = FALSE;
7300                 guint8 *orig_code = code;
7301
7302                 switch (patch_info->type) {
7303                 case MONO_PATCH_INFO_R8:
7304                 case MONO_PATCH_INFO_R4: {
7305                         guint8 *pos, *patch_pos;
7306                         guint32 target_pos;
7307
7308                         /* The SSE opcodes require a 16 byte alignment */
7309 #if defined(__default_codegen__)
7310                         code = (guint8*)ALIGN_TO (code, 16);
7311 #elif defined(__native_client_codegen__)
7312                         {
7313                                 /* Pad this out with HLT instructions  */
7314                                 /* or we can get garbage bytes emitted */
7315                                 /* which will fail validation          */
7316                                 guint8 *aligned_code;
7317                                 /* extra align to make room for  */
7318                                 /* mov/push below                      */
7319                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7320                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7321                                 /* The technique of hiding data in an  */
7322                                 /* instruction has a problem here: we  */
7323                                 /* need the data aligned to a 16-byte  */
7324                                 /* boundary but the instruction cannot */
7325                                 /* cross the bundle boundary. so only  */
7326                                 /* odd multiples of 16 can be used     */
7327                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7328                                         aligned_code += 16;
7329                                 }
7330                                 while (code < aligned_code) {
7331                                         *(code++) = 0xf4; /* hlt */
7332                                 }
7333                         }
7334 #endif
7335
7336                         pos = cfg->native_code + patch_info->ip.i;
7337                         if (IS_REX (pos [1])) {
7338                                 patch_pos = pos + 5;
7339                                 target_pos = code - pos - 9;
7340                         }
7341                         else {
7342                                 patch_pos = pos + 4;
7343                                 target_pos = code - pos - 8;
7344                         }
7345
7346                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7347 #ifdef __native_client_codegen__
7348                                 /* Hide 64-bit data in a         */
7349                                 /* "mov imm64, r11" instruction. */
7350                                 /* write it before the start of  */
7351                                 /* the data*/
7352                                 *(code-2) = 0x49; /* prefix      */
7353                                 *(code-1) = 0xbb; /* mov X, %r11 */
7354 #endif
7355                                 *(double*)code = *(double*)patch_info->data.target;
7356                                 code += sizeof (double);
7357                         } else {
7358 #ifdef __native_client_codegen__
7359                                 /* Hide 32-bit data in a        */
7360                                 /* "push imm32" instruction.    */
7361                                 *(code-1) = 0x68; /* push */
7362 #endif
7363                                 *(float*)code = *(float*)patch_info->data.target;
7364                                 code += sizeof (float);
7365                         }
7366
7367                         *(guint32*)(patch_pos) = target_pos;
7368
7369                         remove = TRUE;
7370                         break;
7371                 }
7372                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7373                         guint8 *pos;
7374
7375                         if (cfg->compile_aot)
7376                                 continue;
7377
7378                         /*loading is faster against aligned addresses.*/
7379                         code = (guint8*)ALIGN_TO (code, 8);
7380                         memset (orig_code, 0, code - orig_code);
7381
7382                         pos = cfg->native_code + patch_info->ip.i;
7383
7384                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7385                         if (IS_REX (pos [1]))
7386                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7387                         else
7388                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7389
7390                         *(gpointer*)code = (gpointer)patch_info->data.target;
7391                         code += sizeof (gpointer);
7392
7393                         remove = TRUE;
7394                         break;
7395                 }
7396                 default:
7397                         break;
7398                 }
7399
7400                 if (remove) {
7401                         if (patch_info == cfg->patch_info)
7402                                 cfg->patch_info = patch_info->next;
7403                         else {
7404                                 MonoJumpInfo *tmp;
7405
7406                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7407                                         ;
7408                                 tmp->next = patch_info->next;
7409                         }
7410                 }
7411                 g_assert (code < cfg->native_code + cfg->code_size);
7412         }
7413
7414         cfg->code_len = code - cfg->native_code;
7415
7416         g_assert (cfg->code_len < cfg->code_size);
7417
7418 }
7419
7420 #endif /* DISABLE_JIT */
7421
7422 void*
7423 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7424 {
7425         guchar *code = p;
7426         CallInfo *cinfo = NULL;
7427         MonoMethodSignature *sig;
7428         MonoInst *inst;
7429         int i, n, stack_area = 0;
7430
7431         /* Keep this in sync with mono_arch_get_argument_info */
7432
7433         if (enable_arguments) {
7434                 /* Allocate a new area on the stack and save arguments there */
7435                 sig = mono_method_signature (cfg->method);
7436
7437                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7438
7439                 n = sig->param_count + sig->hasthis;
7440
7441                 stack_area = ALIGN_TO (n * 8, 16);
7442
7443                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7444
7445                 for (i = 0; i < n; ++i) {
7446                         inst = cfg->args [i];
7447
7448                         if (inst->opcode == OP_REGVAR)
7449                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7450                         else {
7451                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7452                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7453                         }
7454                 }
7455         }
7456
7457         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7458         amd64_set_reg_template (code, AMD64_ARG_REG1);
7459         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7460         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7461
7462         if (enable_arguments)
7463                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7464
7465         return code;
7466 }
7467
7468 enum {
7469         SAVE_NONE,
7470         SAVE_STRUCT,
7471         SAVE_EAX,
7472         SAVE_EAX_EDX,
7473         SAVE_XMM
7474 };
7475
7476 void*
7477 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7478 {
7479         guchar *code = p;
7480         int save_mode = SAVE_NONE;
7481         MonoMethod *method = cfg->method;
7482         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7483         int i;
7484
7485         switch (ret_type->type) {
7486         case MONO_TYPE_VOID:
7487                 /* special case string .ctor icall */
7488                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7489                         save_mode = SAVE_EAX;
7490                 else
7491                         save_mode = SAVE_NONE;
7492                 break;
7493         case MONO_TYPE_I8:
7494         case MONO_TYPE_U8:
7495                 save_mode = SAVE_EAX;
7496                 break;
7497         case MONO_TYPE_R4:
7498         case MONO_TYPE_R8:
7499                 save_mode = SAVE_XMM;
7500                 break;
7501         case MONO_TYPE_GENERICINST:
7502                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7503                         save_mode = SAVE_EAX;
7504                         break;
7505                 }
7506                 /* Fall through */
7507         case MONO_TYPE_VALUETYPE:
7508                 save_mode = SAVE_STRUCT;
7509                 break;
7510         default:
7511                 save_mode = SAVE_EAX;
7512                 break;
7513         }
7514
7515         /* Save the result and copy it into the proper argument register */
7516         switch (save_mode) {
7517         case SAVE_EAX:
7518                 amd64_push_reg (code, AMD64_RAX);
7519                 /* Align stack */
7520                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7521                 if (enable_arguments)
7522                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7523                 break;
7524         case SAVE_STRUCT:
7525                 /* FIXME: */
7526                 if (enable_arguments)
7527                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7528                 break;
7529         case SAVE_XMM:
7530                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7531                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7532                 /* Align stack */
7533                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7534                 /*
7535                  * The result is already in the proper argument register so no copying
7536                  * needed.
7537                  */
7538                 break;
7539         case SAVE_NONE:
7540                 break;
7541         default:
7542                 g_assert_not_reached ();
7543         }
7544
7545         /* Set %al since this is a varargs call */
7546         if (save_mode == SAVE_XMM)
7547                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7548         else
7549                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7550
7551         if (preserve_argument_registers) {
7552                 for (i = 0; i < PARAM_REGS; ++i)
7553                         amd64_push_reg (code, param_regs [i]);
7554         }
7555
7556         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7557         amd64_set_reg_template (code, AMD64_ARG_REG1);
7558         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7559
7560         if (preserve_argument_registers) {
7561                 for (i = PARAM_REGS - 1; i >= 0; --i)
7562                         amd64_pop_reg (code, param_regs [i]);
7563         }
7564
7565         /* Restore result */
7566         switch (save_mode) {
7567         case SAVE_EAX:
7568                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7569                 amd64_pop_reg (code, AMD64_RAX);
7570                 break;
7571         case SAVE_STRUCT:
7572                 /* FIXME: */
7573                 break;
7574         case SAVE_XMM:
7575                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7576                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7577                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7578                 break;
7579         case SAVE_NONE:
7580                 break;
7581         default:
7582                 g_assert_not_reached ();
7583         }
7584
7585         return code;
7586 }
7587
7588 void
7589 mono_arch_flush_icache (guint8 *code, gint size)
7590 {
7591         /* Not needed */
7592 }
7593
7594 void
7595 mono_arch_flush_register_windows (void)
7596 {
7597 }
7598
7599 gboolean
7600 mono_arch_is_inst_imm (gint64 imm)
7601 {
7602         return amd64_is_imm32 (imm);
7603 }
7604
7605 /*
7606  * Determine whenever the trap whose info is in SIGINFO is caused by
7607  * integer overflow.
7608  */
7609 gboolean
7610 mono_arch_is_int_overflow (void *sigctx, void *info)
7611 {
7612         MonoContext ctx;
7613         guint8* rip;
7614         int reg;
7615         gint64 value;
7616
7617         mono_sigctx_to_monoctx (sigctx, &ctx);
7618
7619         rip = (guint8*)ctx.rip;
7620
7621         if (IS_REX (rip [0])) {
7622                 reg = amd64_rex_b (rip [0]);
7623                 rip ++;
7624         }
7625         else
7626                 reg = 0;
7627
7628         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7629                 /* idiv REG */
7630                 reg += x86_modrm_rm (rip [1]);
7631
7632                 switch (reg) {
7633                 case AMD64_RAX:
7634                         value = ctx.rax;
7635                         break;
7636                 case AMD64_RBX:
7637                         value = ctx.rbx;
7638                         break;
7639                 case AMD64_RCX:
7640                         value = ctx.rcx;
7641                         break;
7642                 case AMD64_RDX:
7643                         value = ctx.rdx;
7644                         break;
7645                 case AMD64_RBP:
7646                         value = ctx.rbp;
7647                         break;
7648                 case AMD64_RSP:
7649                         value = ctx.rsp;
7650                         break;
7651                 case AMD64_RSI:
7652                         value = ctx.rsi;
7653                         break;
7654                 case AMD64_RDI:
7655                         value = ctx.rdi;
7656                         break;
7657                 case AMD64_R12:
7658                         value = ctx.r12;
7659                         break;
7660                 case AMD64_R13:
7661                         value = ctx.r13;
7662                         break;
7663                 case AMD64_R14:
7664                         value = ctx.r14;
7665                         break;
7666                 case AMD64_R15:
7667                         value = ctx.r15;
7668                         break;
7669                 default:
7670                         g_assert_not_reached ();
7671                         reg = -1;
7672                 }
7673
7674                 if (value == -1)
7675                         return TRUE;
7676         }
7677
7678         return FALSE;
7679 }
7680
7681 guint32
7682 mono_arch_get_patch_offset (guint8 *code)
7683 {
7684         return 3;
7685 }
7686
7687 /**
7688  * mono_breakpoint_clean_code:
7689  *
7690  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7691  * breakpoints in the original code, they are removed in the copy.
7692  *
7693  * Returns TRUE if no sw breakpoint was present.
7694  */
7695 gboolean
7696 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7697 {
7698         int i;
7699         gboolean can_write = TRUE;
7700         /*
7701          * If method_start is non-NULL we need to perform bound checks, since we access memory
7702          * at code - offset we could go before the start of the method and end up in a different
7703          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7704          * instead.
7705          */
7706         if (!method_start || code - offset >= method_start) {
7707                 memcpy (buf, code - offset, size);
7708         } else {
7709                 int diff = code - method_start;
7710                 memset (buf, 0, size);
7711                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7712         }
7713         code -= offset;
7714         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7715                 int idx = mono_breakpoint_info_index [i];
7716                 guint8 *ptr;
7717                 if (idx < 1)
7718                         continue;
7719                 ptr = mono_breakpoint_info [idx].address;
7720                 if (ptr >= code && ptr < code + size) {
7721                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7722                         can_write = FALSE;
7723                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7724                         buf [ptr - code] = saved_byte;
7725                 }
7726         }
7727         return can_write;
7728 }
7729
7730 #if defined(__native_client_codegen__)
7731 /* For membase calls, we want the base register. for Native Client,  */
7732 /* all indirect calls have the following sequence with the given sizes: */
7733 /* mov %eXX,%eXX                                [2-3]   */
7734 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7735 /* and $0xffffffffffffffe0,%r11d                [4]     */
7736 /* add %r15,%r11                                [3]     */
7737 /* callq *%r11                                  [3]     */
7738
7739
7740 /* Determine if code points to a NaCl call-through-register sequence, */
7741 /* (i.e., the last 3 instructions listed above) */
7742 int
7743 is_nacl_call_reg_sequence(guint8* code)
7744 {
7745         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7746                                "\x4d\x03\xdf"     /* add */
7747                                "\x41\xff\xd3";   /* call */
7748         return memcmp(code, sequence, 10) == 0;
7749 }
7750
7751 /* Determine if code points to the first opcode of the mov membase component */
7752 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7753 /* (there could be a REX prefix before the opcode but it is ignored) */
7754 static int
7755 is_nacl_indirect_call_membase_sequence(guint8* code)
7756 {
7757                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7758         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7759                /* and that src reg = dest reg */
7760                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7761                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7762                IS_REX(code[2]) &&
7763                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7764                /* and has dst of r11 and base of r15 */
7765                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7766                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7767 }
7768 #endif /* __native_client_codegen__ */
7769
7770 int
7771 mono_arch_get_this_arg_reg (guint8 *code)
7772 {
7773         return AMD64_ARG_REG1;
7774 }
7775
7776 gpointer
7777 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7778 {
7779         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7780 }
7781
7782 #define MAX_ARCH_DELEGATE_PARAMS 10
7783
7784 static gpointer
7785 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7786 {
7787         guint8 *code, *start;
7788         int i;
7789
7790         if (has_target) {
7791                 start = code = mono_global_codeman_reserve (64);
7792
7793                 /* Replace the this argument with the target */
7794                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7795                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7796                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7797
7798                 g_assert ((code - start) < 64);
7799         } else {
7800                 start = code = mono_global_codeman_reserve (64);
7801
7802                 if (param_count == 0) {
7803                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7804                 } else {
7805                         /* We have to shift the arguments left */
7806                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7807                         for (i = 0; i < param_count; ++i) {
7808 #ifdef HOST_WIN32
7809                                 if (i < 3)
7810                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7811                                 else
7812                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7813 #else
7814                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7815 #endif
7816                         }
7817
7818                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7819                 }
7820                 g_assert ((code - start) < 64);
7821         }
7822
7823         nacl_global_codeman_validate (&start, 64, &code);
7824
7825         if (code_len)
7826                 *code_len = code - start;
7827
7828         if (mono_jit_map_is_enabled ()) {
7829                 char *buff;
7830                 if (has_target)
7831                         buff = (char*)"delegate_invoke_has_target";
7832                 else
7833                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7834                 mono_emit_jit_tramp (start, code - start, buff);
7835                 if (!has_target)
7836                         g_free (buff);
7837         }
7838         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7839
7840         return start;
7841 }
7842
7843 /*
7844  * mono_arch_get_delegate_invoke_impls:
7845  *
7846  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7847  * trampolines.
7848  */
7849 GSList*
7850 mono_arch_get_delegate_invoke_impls (void)
7851 {
7852         GSList *res = NULL;
7853         guint8 *code;
7854         guint32 code_len;
7855         int i;
7856         char *tramp_name;
7857
7858         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7859         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7860
7861         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7862                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7863                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7864                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7865                 g_free (tramp_name);
7866         }
7867
7868         return res;
7869 }
7870
7871 gpointer
7872 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7873 {
7874         guint8 *code, *start;
7875         int i;
7876
7877         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7878                 return NULL;
7879
7880         /* FIXME: Support more cases */
7881         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7882                 return NULL;
7883
7884         if (has_target) {
7885                 static guint8* cached = NULL;
7886
7887                 if (cached)
7888                         return cached;
7889
7890                 if (mono_aot_only)
7891                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7892                 else
7893                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7894
7895                 mono_memory_barrier ();
7896
7897                 cached = start;
7898         } else {
7899                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7900                 for (i = 0; i < sig->param_count; ++i)
7901                         if (!mono_is_regsize_var (sig->params [i]))
7902                                 return NULL;
7903                 if (sig->param_count > 4)
7904                         return NULL;
7905
7906                 code = cache [sig->param_count];
7907                 if (code)
7908                         return code;
7909
7910                 if (mono_aot_only) {
7911                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7912                         start = mono_aot_get_trampoline (name);
7913                         g_free (name);
7914                 } else {
7915                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7916                 }
7917
7918                 mono_memory_barrier ();
7919
7920                 cache [sig->param_count] = start;
7921         }
7922
7923         return start;
7924 }
7925
7926 gpointer
7927 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7928 {
7929         guint8 *code, *start;
7930         int size = 20;
7931
7932         start = code = mono_global_codeman_reserve (size);
7933
7934         /* Replace the this argument with the target */
7935         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7936         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7937
7938         if (load_imt_reg) {
7939                 /* Load the IMT reg */
7940                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7941         }
7942
7943         /* Load the vtable */
7944         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7945         amd64_jump_membase (code, AMD64_RAX, offset);
7946         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7947
7948         return start;
7949 }
7950
7951 void
7952 mono_arch_finish_init (void)
7953 {
7954 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7955         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7956 #endif
7957 }
7958
7959 void
7960 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7961 {
7962 }
7963
7964 #if defined(__default_codegen__)
7965 #define CMP_SIZE (6 + 1)
7966 #define CMP_REG_REG_SIZE (4 + 1)
7967 #define BR_SMALL_SIZE 2
7968 #define BR_LARGE_SIZE 6
7969 #define MOV_REG_IMM_SIZE 10
7970 #define MOV_REG_IMM_32BIT_SIZE 6
7971 #define JUMP_REG_SIZE (2 + 1)
7972 #elif defined(__native_client_codegen__)
7973 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7974 #define CMP_SIZE ((6 + 1) * 2 - 1)
7975 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7976 #define BR_SMALL_SIZE (2 * 2 - 1)
7977 #define BR_LARGE_SIZE (6 * 2 - 1)
7978 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7979 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7980 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7981 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7982 /* Jump membase's size is large and unpredictable    */
7983 /* in native client, just pad it out a whole bundle. */
7984 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7985 #endif
7986
7987 static int
7988 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7989 {
7990         int i, distance = 0;
7991         for (i = start; i < target; ++i)
7992                 distance += imt_entries [i]->chunk_size;
7993         return distance;
7994 }
7995
7996 /*
7997  * LOCKING: called with the domain lock held
7998  */
7999 gpointer
8000 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8001         gpointer fail_tramp)
8002 {
8003         int i;
8004         int size = 0;
8005         guint8 *code, *start;
8006         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8007
8008         for (i = 0; i < count; ++i) {
8009                 MonoIMTCheckItem *item = imt_entries [i];
8010                 if (item->is_equals) {
8011                         if (item->check_target_idx) {
8012                                 if (!item->compare_done) {
8013                                         if (amd64_is_imm32 (item->key))
8014                                                 item->chunk_size += CMP_SIZE;
8015                                         else
8016                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8017                                 }
8018                                 if (item->has_target_code) {
8019                                         item->chunk_size += MOV_REG_IMM_SIZE;
8020                                 } else {
8021                                         if (vtable_is_32bit)
8022                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8023                                         else
8024                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8025 #ifdef __native_client_codegen__
8026                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8027 #endif
8028                                 }
8029                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8030                         } else {
8031                                 if (fail_tramp) {
8032                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8033                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8034                                 } else {
8035                                         if (vtable_is_32bit)
8036                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8037                                         else
8038                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8039                                         item->chunk_size += JUMP_REG_SIZE;
8040                                         /* with assert below:
8041                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8042                                          */
8043 #ifdef __native_client_codegen__
8044                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8045 #endif
8046                                 }
8047                         }
8048                 } else {
8049                         if (amd64_is_imm32 (item->key))
8050                                 item->chunk_size += CMP_SIZE;
8051                         else
8052                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8053                         item->chunk_size += BR_LARGE_SIZE;
8054                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8055                 }
8056                 size += item->chunk_size;
8057         }
8058 #if defined(__native_client__) && defined(__native_client_codegen__)
8059         /* In Native Client, we don't re-use thunks, allocate from the */
8060         /* normal code manager paths. */
8061         code = mono_domain_code_reserve (domain, size);
8062 #else
8063         if (fail_tramp)
8064                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8065         else
8066                 code = mono_domain_code_reserve (domain, size);
8067 #endif
8068         start = code;
8069         for (i = 0; i < count; ++i) {
8070                 MonoIMTCheckItem *item = imt_entries [i];
8071                 item->code_target = code;
8072                 if (item->is_equals) {
8073                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8074
8075                         if (item->check_target_idx || fail_case) {
8076                                 if (!item->compare_done || fail_case) {
8077                                         if (amd64_is_imm32 (item->key))
8078                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8079                                         else {
8080                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8081                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8082                                         }
8083                                 }
8084                                 item->jmp_code = code;
8085                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8086                                 if (item->has_target_code) {
8087                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8088                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8089                                 } else {
8090                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8091                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8092                                 }
8093
8094                                 if (fail_case) {
8095                                         amd64_patch (item->jmp_code, code);
8096                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8097                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8098                                         item->jmp_code = NULL;
8099                                 }
8100                         } else {
8101                                 /* enable the commented code to assert on wrong method */
8102 #if 0
8103                                 if (amd64_is_imm32 (item->key))
8104                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8105                                 else {
8106                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8107                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8108                                 }
8109                                 item->jmp_code = code;
8110                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8111                                 /* See the comment below about R10 */
8112                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8113                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8114                                 amd64_patch (item->jmp_code, code);
8115                                 amd64_breakpoint (code);
8116                                 item->jmp_code = NULL;
8117 #else
8118                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8119                                    needs to be preserved.  R10 needs
8120                                    to be preserved for calls which
8121                                    require a runtime generic context,
8122                                    but interface calls don't. */
8123                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8124                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8125 #endif
8126                         }
8127                 } else {
8128                         if (amd64_is_imm32 (item->key))
8129                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8130                         else {
8131                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8132                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8133                         }
8134                         item->jmp_code = code;
8135                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8136                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8137                         else
8138                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8139                 }
8140                 g_assert (code - item->code_target <= item->chunk_size);
8141         }
8142         /* patch the branches to get to the target items */
8143         for (i = 0; i < count; ++i) {
8144                 MonoIMTCheckItem *item = imt_entries [i];
8145                 if (item->jmp_code) {
8146                         if (item->check_target_idx) {
8147                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8148                         }
8149                 }
8150         }
8151
8152         if (!fail_tramp)
8153                 mono_stats.imt_thunks_size += code - start;
8154         g_assert (code - start <= size);
8155
8156         nacl_domain_code_validate(domain, &start, size, &code);
8157         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8158
8159         return start;
8160 }
8161
8162 MonoMethod*
8163 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8164 {
8165         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8166 }
8167
8168 MonoVTable*
8169 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8170 {
8171         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8172 }
8173
8174 GSList*
8175 mono_arch_get_cie_program (void)
8176 {
8177         GSList *l = NULL;
8178
8179         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8180         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8181
8182         return l;
8183 }
8184
8185 #ifndef DISABLE_JIT
8186
8187 MonoInst*
8188 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8189 {
8190         MonoInst *ins = NULL;
8191         int opcode = 0;
8192
8193         if (cmethod->klass == mono_defaults.math_class) {
8194                 if (strcmp (cmethod->name, "Sin") == 0) {
8195                         opcode = OP_SIN;
8196                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8197                         opcode = OP_COS;
8198                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8199                         opcode = OP_SQRT;
8200                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8201                         opcode = OP_ABS;
8202                 }
8203
8204                 if (opcode && fsig->param_count == 1) {
8205                         MONO_INST_NEW (cfg, ins, opcode);
8206                         ins->type = STACK_R8;
8207                         ins->dreg = mono_alloc_freg (cfg);
8208                         ins->sreg1 = args [0]->dreg;
8209                         MONO_ADD_INS (cfg->cbb, ins);
8210                 }
8211
8212                 opcode = 0;
8213                 if (cfg->opt & MONO_OPT_CMOV) {
8214                         if (strcmp (cmethod->name, "Min") == 0) {
8215                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8216                                         opcode = OP_IMIN;
8217                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8218                                         opcode = OP_IMIN_UN;
8219                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8220                                         opcode = OP_LMIN;
8221                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8222                                         opcode = OP_LMIN_UN;
8223                         } else if (strcmp (cmethod->name, "Max") == 0) {
8224                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8225                                         opcode = OP_IMAX;
8226                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8227                                         opcode = OP_IMAX_UN;
8228                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8229                                         opcode = OP_LMAX;
8230                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8231                                         opcode = OP_LMAX_UN;
8232                         }
8233                 }
8234
8235                 if (opcode && fsig->param_count == 2) {
8236                         MONO_INST_NEW (cfg, ins, opcode);
8237                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8238                         ins->dreg = mono_alloc_ireg (cfg);
8239                         ins->sreg1 = args [0]->dreg;
8240                         ins->sreg2 = args [1]->dreg;
8241                         MONO_ADD_INS (cfg->cbb, ins);
8242                 }
8243
8244 #if 0
8245                 /* OP_FREM is not IEEE compatible */
8246                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8247                         MONO_INST_NEW (cfg, ins, OP_FREM);
8248                         ins->inst_i0 = args [0];
8249                         ins->inst_i1 = args [1];
8250                 }
8251 #endif
8252         }
8253
8254         return ins;
8255 }
8256 #endif
8257
8258 gboolean
8259 mono_arch_print_tree (MonoInst *tree, int arity)
8260 {
8261         return 0;
8262 }
8263
8264 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8265
8266 mgreg_t
8267 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8268 {
8269         switch (reg) {
8270         case AMD64_RCX: return ctx->rcx;
8271         case AMD64_RDX: return ctx->rdx;
8272         case AMD64_RBX: return ctx->rbx;
8273         case AMD64_RBP: return ctx->rbp;
8274         case AMD64_RSP: return ctx->rsp;
8275         default:
8276                 return _CTX_REG (ctx, rax, reg);
8277         }
8278 }
8279
8280 void
8281 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8282 {
8283         switch (reg) {
8284         case AMD64_RCX:
8285                 ctx->rcx = val;
8286                 break;
8287         case AMD64_RDX:
8288                 ctx->rdx = val;
8289                 break;
8290         case AMD64_RBX:
8291                 ctx->rbx = val;
8292                 break;
8293         case AMD64_RBP:
8294                 ctx->rbp = val;
8295                 break;
8296         case AMD64_RSP:
8297                 ctx->rsp = val;
8298                 break;
8299         default:
8300                 _CTX_REG (ctx, rax, reg) = val;
8301         }
8302 }
8303
8304 gpointer
8305 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8306 {
8307         gpointer *sp, old_value;
8308         char *bp;
8309
8310         /*Load the spvar*/
8311         bp = MONO_CONTEXT_GET_BP (ctx);
8312         sp = *(gpointer*)(bp + clause->exvar_offset);
8313
8314         old_value = *sp;
8315         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8316                 return old_value;
8317
8318         *sp = new_value;
8319
8320         return old_value;
8321 }
8322
8323 /*
8324  * mono_arch_emit_load_aotconst:
8325  *
8326  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8327  * TARGET from the mscorlib GOT in full-aot code.
8328  * On AMD64, the result is placed into R11.
8329  */
8330 guint8*
8331 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8332 {
8333         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8334         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8335
8336         return code;
8337 }
8338
8339 /*
8340  * mono_arch_get_trampolines:
8341  *
8342  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8343  * for AOT.
8344  */
8345 GSList *
8346 mono_arch_get_trampolines (gboolean aot)
8347 {
8348         return mono_amd64_get_exception_trampolines (aot);
8349 }
8350
8351 /* Soft Debug support */
8352 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8353
8354 /*
8355  * mono_arch_set_breakpoint:
8356  *
8357  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8358  * The location should contain code emitted by OP_SEQ_POINT.
8359  */
8360 void
8361 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8362 {
8363         guint8 *code = ip;
8364         guint8 *orig_code = code;
8365
8366         if (ji->from_aot) {
8367                 guint32 native_offset = ip - (guint8*)ji->code_start;
8368                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8369
8370                 g_assert (info->bp_addrs [native_offset] == 0);
8371                 info->bp_addrs [native_offset] = bp_trigger_page;
8372         } else {
8373                 /*
8374                  * In production, we will use int3 (has to fix the size in the md
8375                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8376                  * instead.
8377                  */
8378                 g_assert (code [0] == 0x90);
8379                 if (breakpoint_size == 8) {
8380                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8381                 } else {
8382                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8383                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8384                 }
8385
8386                 g_assert (code - orig_code == breakpoint_size);
8387         }
8388 }
8389
8390 /*
8391  * mono_arch_clear_breakpoint:
8392  *
8393  *   Clear the breakpoint at IP.
8394  */
8395 void
8396 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8397 {
8398         guint8 *code = ip;
8399         int i;
8400
8401         if (ji->from_aot) {
8402                 guint32 native_offset = ip - (guint8*)ji->code_start;
8403                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8404
8405                 g_assert (info->bp_addrs [native_offset] == 0);
8406                 info->bp_addrs [native_offset] = info;
8407         } else {
8408                 for (i = 0; i < breakpoint_size; ++i)
8409                         x86_nop (code);
8410         }
8411 }
8412
8413 gboolean
8414 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8415 {
8416 #ifdef HOST_WIN32
8417         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8418         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8419                 return TRUE;
8420         else
8421                 return FALSE;
8422 #else
8423         siginfo_t* sinfo = (siginfo_t*) info;
8424         /* Sometimes the address is off by 4 */
8425         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8426                 return TRUE;
8427         else
8428                 return FALSE;
8429 #endif
8430 }
8431
8432 /*
8433  * mono_arch_skip_breakpoint:
8434  *
8435  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8436  * we resume, the instruction is not executed again.
8437  */
8438 void
8439 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8440 {
8441         if (ji->from_aot) {
8442                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8443                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8444         } else {
8445                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8446         }
8447 }
8448
8449 /*
8450  * mono_arch_start_single_stepping:
8451  *
8452  *   Start single stepping.
8453  */
8454 void
8455 mono_arch_start_single_stepping (void)
8456 {
8457         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8458 }
8459
8460 /*
8461  * mono_arch_stop_single_stepping:
8462  *
8463  *   Stop single stepping.
8464  */
8465 void
8466 mono_arch_stop_single_stepping (void)
8467 {
8468         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8469 }
8470
8471 /*
8472  * mono_arch_is_single_step_event:
8473  *
8474  *   Return whenever the machine state in SIGCTX corresponds to a single
8475  * step event.
8476  */
8477 gboolean
8478 mono_arch_is_single_step_event (void *info, void *sigctx)
8479 {
8480 #ifdef HOST_WIN32
8481         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8482         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8483                 return TRUE;
8484         else
8485                 return FALSE;
8486 #else
8487         siginfo_t* sinfo = (siginfo_t*) info;
8488         /* Sometimes the address is off by 4 */
8489         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8490                 return TRUE;
8491         else
8492                 return FALSE;
8493 #endif
8494 }
8495
8496 /*
8497  * mono_arch_skip_single_step:
8498  *
8499  *   Modify CTX so the ip is placed after the single step trigger instruction,
8500  * we resume, the instruction is not executed again.
8501  */
8502 void
8503 mono_arch_skip_single_step (MonoContext *ctx)
8504 {
8505         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8506 }
8507
8508 /*
8509  * mono_arch_create_seq_point_info:
8510  *
8511  *   Return a pointer to a data structure which is used by the sequence
8512  * point implementation in AOTed code.
8513  */
8514 gpointer
8515 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8516 {
8517         SeqPointInfo *info;
8518         MonoJitInfo *ji;
8519         int i;
8520
8521         // FIXME: Add a free function
8522
8523         mono_domain_lock (domain);
8524         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8525                                                                 code);
8526         mono_domain_unlock (domain);
8527
8528         if (!info) {
8529                 ji = mono_jit_info_table_find (domain, (char*)code);
8530                 g_assert (ji);
8531
8532                 // FIXME: Optimize the size
8533                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8534
8535                 info->ss_trigger_page = ss_trigger_page;
8536                 info->bp_trigger_page = bp_trigger_page;
8537                 /* Initialize to a valid address */
8538                 for (i = 0; i < ji->code_size; ++i)
8539                         info->bp_addrs [i] = info;
8540
8541                 mono_domain_lock (domain);
8542                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8543                                                          code, info);
8544                 mono_domain_unlock (domain);
8545         }
8546
8547         return info;
8548 }
8549
8550 void
8551 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8552 {
8553         ext->lmf.previous_lmf = prev_lmf;
8554         /* Mark that this is a MonoLMFExt */
8555         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8556         ext->lmf.rsp = (gssize)ext;
8557 }
8558
8559 #endif
8560
8561 gboolean
8562 mono_arch_opcode_supported (int opcode)
8563 {
8564         switch (opcode) {
8565         case OP_ATOMIC_ADD_I4:
8566         case OP_ATOMIC_ADD_I8:
8567         case OP_ATOMIC_EXCHANGE_I4:
8568         case OP_ATOMIC_EXCHANGE_I8:
8569         case OP_ATOMIC_CAS_I4:
8570         case OP_ATOMIC_CAS_I8:
8571         case OP_ATOMIC_LOAD_I1:
8572         case OP_ATOMIC_LOAD_I2:
8573         case OP_ATOMIC_LOAD_I4:
8574         case OP_ATOMIC_LOAD_I8:
8575         case OP_ATOMIC_LOAD_U1:
8576         case OP_ATOMIC_LOAD_U2:
8577         case OP_ATOMIC_LOAD_U4:
8578         case OP_ATOMIC_LOAD_U8:
8579         case OP_ATOMIC_LOAD_R4:
8580         case OP_ATOMIC_LOAD_R8:
8581         case OP_ATOMIC_STORE_I1:
8582         case OP_ATOMIC_STORE_I2:
8583         case OP_ATOMIC_STORE_I4:
8584         case OP_ATOMIC_STORE_I8:
8585         case OP_ATOMIC_STORE_U1:
8586         case OP_ATOMIC_STORE_U2:
8587         case OP_ATOMIC_STORE_U4:
8588         case OP_ATOMIC_STORE_U8:
8589         case OP_ATOMIC_STORE_R4:
8590         case OP_ATOMIC_STORE_R8:
8591                 return TRUE;
8592         default:
8593                 return FALSE;
8594         }
8595 }