mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  67 static CRITICAL_SECTION mini_arch_mutex;
  68
  69 MonoBreakpointInfo
  70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  71
  72 /*
  73  * The code generated for sequence points reads from this location, which is
  74  * made read-only when single stepping is enabled.
  75  */
  76 static gpointer ss_trigger_page;
  77
  78 /* Enabled breakpoints read from this trigger page */
  79 static gpointer bp_trigger_page;
  80
  81 /* The size of the breakpoint sequence */
  82 static int breakpoint_size;
  83
  84 /* The size of the breakpoint instruction causing the actual fault */
  85 static int breakpoint_fault_size;
  86
  87 /* The size of the single step instruction causing the actual fault */
  88 static int single_step_fault_size;
  89
  90 #ifdef HOST_WIN32
  91 /* On Win64 always reserve first 32 bytes for first four arguments */
  92 #define ARGS_OFFSET 48
  93 #else
  94 #define ARGS_OFFSET 16
  95 #endif
  96 #define GP_SCRATCH_REG AMD64_R11
  97
  98 /*
  99  * AMD64 register usage:
 100  * - callee saved registers are used for global register allocation
 101  * - %r11 is used for materializing 64 bit constants in opcodes
 102  * - the rest is used for local allocation
 103  */
 104
 105 /*
 106  * Floating point comparison results:
 107  *                  ZF PF CF
 108  * A > B            0  0  0
 109  * A < B            0  0  1
 110  * A = B            1  0  0
 111  * A > B            0  0  0
 112  * UNORDERED        1  1  1
 113  */
 114
 115 const char*
 116 mono_arch_regname (int reg)
 117 {
 118         switch (reg) {
 119         case AMD64_RAX: return "%rax";
 120         case AMD64_RBX: return "%rbx";
 121         case AMD64_RCX: return "%rcx";
 122         case AMD64_RDX: return "%rdx";
 123         case AMD64_RSP: return "%rsp";
 124         case AMD64_RBP: return "%rbp";
 125         case AMD64_RDI: return "%rdi";
 126         case AMD64_RSI: return "%rsi";
 127         case AMD64_R8: return "%r8";
 128         case AMD64_R9: return "%r9";
 129         case AMD64_R10: return "%r10";
 130         case AMD64_R11: return "%r11";
 131         case AMD64_R12: return "%r12";
 132         case AMD64_R13: return "%r13";
 133         case AMD64_R14: return "%r14";
 134         case AMD64_R15: return "%r15";
 135         }
 136         return "unknown";
 137 }
 138
 139 static const char * packed_xmmregs [] = {
 140         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 141         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 142 };
 143
 144 static const char * single_xmmregs [] = {
 145         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 146         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 147 };
 148
 149 const char*
 150 mono_arch_fregname (int reg)
 151 {
 152         if (reg < AMD64_XMM_NREG)
 153                 return single_xmmregs [reg];
 154         else
 155                 return "unknown";
 156 }
 157
 158 const char *
 159 mono_arch_xregname (int reg)
 160 {
 161         if (reg < AMD64_XMM_NREG)
 162                 return packed_xmmregs [reg];
 163         else
 164                 return "unknown";
 165 }
 166
 167 G_GNUC_UNUSED static void
 168 break_count (void)
 169 {
 170 }
 171
 172 G_GNUC_UNUSED static gboolean
 173 debug_count (void)
 174 {
 175         static int count = 0;
 176         count ++;
 177
 178         if (!getenv ("COUNT"))
 179                 return TRUE;
 180
 181         if (count == atoi (getenv ("COUNT"))) {
 182                 break_count ();
 183         }
 184
 185         if (count > atoi (getenv ("COUNT"))) {
 186                 return FALSE;
 187         }
 188
 189         return TRUE;
 190 }
 191
 192 static gboolean
 193 debug_omit_fp (void)
 194 {
 195 #if 0
 196         return debug_count ();
 197 #else
 198         return TRUE;
 199 #endif
 200 }
 201
 202 static inline gboolean
 203 amd64_is_near_call (guint8 *code)
 204 {
 205         /* Skip REX */
 206         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 207                 code += 1;
 208
 209         return code [0] == 0xe8;
 210 }
 211
 212 static inline void
 213 amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         guint8 rex = 0;
 216
 217         /* Skip REX */
 218         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 219                 rex = code [0];
 220                 code += 1;
 221         }
 222
 223         if ((code [0] & 0xf8) == 0xb8) {
 224                 /* amd64_set_reg_template */
 225                 *(guint64*)(code + 1) = (guint64)target;
 226         }
 227         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 228                 /* mov 0(%rip), %dreg */
 229                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 230         }
 231         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 232                 /* call *<OFFSET>(%rip) */
 233                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 234         }
 235         else if ((code [0] == 0xe8)) {
 236                 /* call <DISP> */
 237                 gint64 disp = (guint8*)target - (guint8*)code;
 238                 g_assert (amd64_is_imm32 (disp));
 239                 x86_patch (code, (unsigned char*)target);
 240         }
 241         else
 242                 x86_patch (code, (unsigned char*)target);
 243 }
 244
 245 void
 246 mono_amd64_patch (unsigned char* code, gpointer target)
 247 {
 248         amd64_patch (code, target);
 249 }
 250
 251 typedef enum {
 252         ArgInIReg,
 253         ArgInFloatSSEReg,
 254         ArgInDoubleSSEReg,
 255         ArgOnStack,
 256         ArgValuetypeInReg,
 257         ArgValuetypeAddrInIReg,
 258         ArgNone /* only in pair_storage */
 259 } ArgStorage;
 260
 261 typedef struct {
 262         gint16 offset;
 263         gint8  reg;
 264         ArgStorage storage;
 265
 266         /* Only if storage == ArgValuetypeInReg */
 267         ArgStorage pair_storage [2];
 268         gint8 pair_regs [2];
 269 } ArgInfo;
 270
 271 typedef struct {
 272         int nargs;
 273         guint32 stack_usage;
 274         guint32 reg_usage;
 275         guint32 freg_usage;
 276         gboolean need_stack_align;
 277         gboolean vtype_retaddr;
 278         ArgInfo ret;
 279         ArgInfo sig_cookie;
 280         ArgInfo args [1];
 281 } CallInfo;
 282
 283 #define DEBUG(a) if (cfg->verbose_level > 1) a
 284
 285 #ifdef HOST_WIN32
 286 #define PARAM_REGS 4
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 289
 290 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #else
 292 #define PARAM_REGS 6
 293
 294 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 295
 296  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 297 #endif
 298
 299 static void inline
 300 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 301 {
 302     ainfo->offset = *stack_size;
 303
 304     if (*gr >= PARAM_REGS) {
 305                 ainfo->storage = ArgOnStack;
 306                 (*stack_size) += sizeof (gpointer);
 307     }
 308     else {
 309                 ainfo->storage = ArgInIReg;
 310                 ainfo->reg = param_regs [*gr];
 311                 (*gr) ++;
 312     }
 313 }
 314
 315 #ifdef HOST_WIN32
 316 #define FLOAT_PARAM_REGS 4
 317 #else
 318 #define FLOAT_PARAM_REGS 8
 319 #endif
 320
 321 static void inline
 322 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 323 {
 324     ainfo->offset = *stack_size;
 325
 326     if (*gr >= FLOAT_PARAM_REGS) {
 327                 ainfo->storage = ArgOnStack;
 328                 (*stack_size) += sizeof (gpointer);
 329     }
 330     else {
 331                 /* A double register */
 332                 if (is_double)
 333                         ainfo->storage = ArgInDoubleSSEReg;
 334                 else
 335                         ainfo->storage = ArgInFloatSSEReg;
 336                 ainfo->reg = *gr;
 337                 (*gr) += 1;
 338     }
 339 }
 340
 341 typedef enum ArgumentClass {
 342         ARG_CLASS_NO_CLASS,
 343         ARG_CLASS_MEMORY,
 344         ARG_CLASS_INTEGER,
 345         ARG_CLASS_SSE
 346 } ArgumentClass;
 347
 348 static ArgumentClass
 349 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 350 {
 351         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 352         MonoType *ptype;
 353
 354         ptype = mini_type_get_underlying_type (NULL, type);
 355         switch (ptype->type) {
 356         case MONO_TYPE_BOOLEAN:
 357         case MONO_TYPE_CHAR:
 358         case MONO_TYPE_I1:
 359         case MONO_TYPE_U1:
 360         case MONO_TYPE_I2:
 361         case MONO_TYPE_U2:
 362         case MONO_TYPE_I4:
 363         case MONO_TYPE_U4:
 364         case MONO_TYPE_I:
 365         case MONO_TYPE_U:
 366         case MONO_TYPE_STRING:
 367         case MONO_TYPE_OBJECT:
 368         case MONO_TYPE_CLASS:
 369         case MONO_TYPE_SZARRAY:
 370         case MONO_TYPE_PTR:
 371         case MONO_TYPE_FNPTR:
 372         case MONO_TYPE_ARRAY:
 373         case MONO_TYPE_I8:
 374         case MONO_TYPE_U8:
 375                 class2 = ARG_CLASS_INTEGER;
 376                 break;
 377         case MONO_TYPE_R4:
 378         case MONO_TYPE_R8:
 379 #ifdef HOST_WIN32
 380                 class2 = ARG_CLASS_INTEGER;
 381 #else
 382                 class2 = ARG_CLASS_SSE;
 383 #endif
 384                 break;
 385
 386         case MONO_TYPE_TYPEDBYREF:
 387                 g_assert_not_reached ();
 388
 389         case MONO_TYPE_GENERICINST:
 390                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 391                         class2 = ARG_CLASS_INTEGER;
 392                         break;
 393                 }
 394                 /* fall through */
 395         case MONO_TYPE_VALUETYPE: {
 396                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 397                 int i;
 398
 399                 for (i = 0; i < info->num_fields; ++i) {
 400                         class2 = class1;
 401                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 402                 }
 403                 break;
 404         }
 405         default:
 406                 g_assert_not_reached ();
 407         }
 408
 409         /* Merge */
 410         if (class1 == class2)
 411                 ;
 412         else if (class1 == ARG_CLASS_NO_CLASS)
 413                 class1 = class2;
 414         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 415                 class1 = ARG_CLASS_MEMORY;
 416         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 417                 class1 = ARG_CLASS_INTEGER;
 418         else
 419                 class1 = ARG_CLASS_SSE;
 420
 421         return class1;
 422 }
 423
 424 static void
 425 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 426                            gboolean is_return,
 427                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 428 {
 429         guint32 size, quad, nquads, i;
 430         ArgumentClass args [2];
 431         MonoMarshalType *info = NULL;
 432         MonoClass *klass;
 433         MonoGenericSharingContext tmp_gsctx;
 434         gboolean pass_on_stack = FALSE;
 435
 436         /*
 437          * The gsctx currently contains no data, it is only used for checking whenever
 438          * open types are allowed, some callers like mono_arch_get_argument_info ()
 439          * don't pass it to us, so work around that.
 440          */
 441         if (!gsctx)
 442                 gsctx = &tmp_gsctx;
 443
 444         klass = mono_class_from_mono_type (type);
 445         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 446 #ifndef HOST_WIN32
 447         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 448                 /* We pass and return vtypes of size 8 in a register */
 449         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 450                 pass_on_stack = TRUE;
 451         }
 452 #else
 453         if (!sig->pinvoke) {
 454                 pass_on_stack = TRUE;
 455         }
 456 #endif
 457
 458         if (pass_on_stack) {
 459                 /* Allways pass in memory */
 460                 ainfo->offset = *stack_size;
 461                 *stack_size += ALIGN_TO (size, 8);
 462                 ainfo->storage = ArgOnStack;
 463
 464                 return;
 465         }
 466
 467         /* FIXME: Handle structs smaller than 8 bytes */
 468         //if ((size % 8) != 0)
 469         //      NOT_IMPLEMENTED;
 470
 471         if (size > 8)
 472                 nquads = 2;
 473         else
 474                 nquads = 1;
 475
 476         if (!sig->pinvoke) {
 477                 /* Always pass in 1 or 2 integer registers */
 478                 args [0] = ARG_CLASS_INTEGER;
 479                 args [1] = ARG_CLASS_INTEGER;
 480                 /* Only the simplest cases are supported */
 481                 if (is_return && nquads != 1) {
 482                         args [0] = ARG_CLASS_MEMORY;
 483                         args [1] = ARG_CLASS_MEMORY;
 484                 }
 485         } else {
 486                 /*
 487                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 488                  * The X87 and SSEUP stuff is left out since there are no such types in
 489                  * the CLR.
 490                  */
 491                 info = mono_marshal_load_type_info (klass);
 492                 g_assert (info);
 493
 494 #ifndef HOST_WIN32
 495                 if (info->native_size > 16) {
 496                         ainfo->offset = *stack_size;
 497                         *stack_size += ALIGN_TO (info->native_size, 8);
 498                         ainfo->storage = ArgOnStack;
 499
 500                         return;
 501                 }
 502 #else
 503                 switch (info->native_size) {
 504                 case 1: case 2: case 4: case 8:
 505                         break;
 506                 default:
 507                         if (is_return) {
 508                                 ainfo->storage = ArgOnStack;
 509                                 ainfo->offset = *stack_size;
 510                                 *stack_size += ALIGN_TO (info->native_size, 8);
 511                         }
 512                         else {
 513                                 ainfo->storage = ArgValuetypeAddrInIReg;
 514
 515                                 if (*gr < PARAM_REGS) {
 516                                         ainfo->pair_storage [0] = ArgInIReg;
 517                                         ainfo->pair_regs [0] = param_regs [*gr];
 518                                         (*gr) ++;
 519                                 }
 520                                 else {
 521                                         ainfo->pair_storage [0] = ArgOnStack;
 522                                         ainfo->offset = *stack_size;
 523                                         *stack_size += 8;
 524                                 }
 525                         }
 526
 527                         return;
 528                 }
 529 #endif
 530
 531                 args [0] = ARG_CLASS_NO_CLASS;
 532                 args [1] = ARG_CLASS_NO_CLASS;
 533                 for (quad = 0; quad < nquads; ++quad) {
 534                         int size;
 535                         guint32 align;
 536                         ArgumentClass class1;
 537
 538                         if (info->num_fields == 0)
 539                                 class1 = ARG_CLASS_MEMORY;
 540                         else
 541                                 class1 = ARG_CLASS_NO_CLASS;
 542                         for (i = 0; i < info->num_fields; ++i) {
 543                                 size = mono_marshal_type_size (info->fields [i].field->type,
 544                                                                                            info->fields [i].mspec,
 545                                                                                            &align, TRUE, klass->unicode);
 546                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 547                                         /* Unaligned field */
 548                                         NOT_IMPLEMENTED;
 549                                 }
 550
 551                                 /* Skip fields in other quad */
 552                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 553                                         continue;
 554                                 if ((quad == 1) && (info->fields [i].offset < 8))
 555                                         continue;
 556
 557                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 558                         }
 559                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 560                         args [quad] = class1;
 561                 }
 562         }
 563
 564         /* Post merger cleanup */
 565         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 566                 args [0] = args [1] = ARG_CLASS_MEMORY;
 567
 568         /* Allocate registers */
 569         {
 570                 int orig_gr = *gr;
 571                 int orig_fr = *fr;
 572
 573                 ainfo->storage = ArgValuetypeInReg;
 574                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 575                 for (quad = 0; quad < nquads; ++quad) {
 576                         switch (args [quad]) {
 577                         case ARG_CLASS_INTEGER:
 578                                 if (*gr >= PARAM_REGS)
 579                                         args [quad] = ARG_CLASS_MEMORY;
 580                                 else {
 581                                         ainfo->pair_storage [quad] = ArgInIReg;
 582                                         if (is_return)
 583                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 584                                         else
 585                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 586                                         (*gr) ++;
 587                                 }
 588                                 break;
 589                         case ARG_CLASS_SSE:
 590                                 if (*fr >= FLOAT_PARAM_REGS)
 591                                         args [quad] = ARG_CLASS_MEMORY;
 592                                 else {
 593                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 594                                         ainfo->pair_regs [quad] = *fr;
 595                                         (*fr) ++;
 596                                 }
 597                                 break;
 598                         case ARG_CLASS_MEMORY:
 599                                 break;
 600                         default:
 601                                 g_assert_not_reached ();
 602                         }
 603                 }
 604
 605                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 606                         /* Revert possible register assignments */
 607                         *gr = orig_gr;
 608                         *fr = orig_fr;
 609
 610                         ainfo->offset = *stack_size;
 611                         if (sig->pinvoke)
 612                                 *stack_size += ALIGN_TO (info->native_size, 8);
 613                         else
 614                                 *stack_size += nquads * sizeof (gpointer);
 615                         ainfo->storage = ArgOnStack;
 616                 }
 617         }
 618 }
 619
 620 /*
 621  * get_call_info:
 622  *
 623  *  Obtain information about a call according to the calling convention.
 624  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 625  * Draft Version 0.23" document for more information.
 626  */
 627 static CallInfo*
 628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 629 {
 630         guint32 i, gr, fr;
 631         MonoType *ret_type;
 632         int n = sig->hasthis + sig->param_count;
 633         guint32 stack_size = 0;
 634         CallInfo *cinfo;
 635
 636         if (mp)
 637                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 638         else
 639                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 640
 641         cinfo->nargs = n;
 642
 643         gr = 0;
 644         fr = 0;
 645
 646         /* return value */
 647         {
 648                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 649                 switch (ret_type->type) {
 650                 case MONO_TYPE_BOOLEAN:
 651                 case MONO_TYPE_I1:
 652                 case MONO_TYPE_U1:
 653                 case MONO_TYPE_I2:
 654                 case MONO_TYPE_U2:
 655                 case MONO_TYPE_CHAR:
 656                 case MONO_TYPE_I4:
 657                 case MONO_TYPE_U4:
 658                 case MONO_TYPE_I:
 659                 case MONO_TYPE_U:
 660                 case MONO_TYPE_PTR:
 661                 case MONO_TYPE_FNPTR:
 662                 case MONO_TYPE_CLASS:
 663                 case MONO_TYPE_OBJECT:
 664                 case MONO_TYPE_SZARRAY:
 665                 case MONO_TYPE_ARRAY:
 666                 case MONO_TYPE_STRING:
 667                         cinfo->ret.storage = ArgInIReg;
 668                         cinfo->ret.reg = AMD64_RAX;
 669                         break;
 670                 case MONO_TYPE_U8:
 671                 case MONO_TYPE_I8:
 672                         cinfo->ret.storage = ArgInIReg;
 673                         cinfo->ret.reg = AMD64_RAX;
 674                         break;
 675                 case MONO_TYPE_R4:
 676                         cinfo->ret.storage = ArgInFloatSSEReg;
 677                         cinfo->ret.reg = AMD64_XMM0;
 678                         break;
 679                 case MONO_TYPE_R8:
 680                         cinfo->ret.storage = ArgInDoubleSSEReg;
 681                         cinfo->ret.reg = AMD64_XMM0;
 682                         break;
 683                 case MONO_TYPE_GENERICINST:
 684                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 685                                 cinfo->ret.storage = ArgInIReg;
 686                                 cinfo->ret.reg = AMD64_RAX;
 687                                 break;
 688                         }
 689                         /* fall through */
 690                 case MONO_TYPE_VALUETYPE: {
 691                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 692
 693                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 694                         if (cinfo->ret.storage == ArgOnStack) {
 695                                 cinfo->vtype_retaddr = TRUE;
 696                                 /* The caller passes the address where the value is stored */
 697                                 add_general (&gr, &stack_size, &cinfo->ret);
 698                         }
 699                         break;
 700                 }
 701                 case MONO_TYPE_TYPEDBYREF:
 702                         /* Same as a valuetype with size 24 */
 703                         add_general (&gr, &stack_size, &cinfo->ret);
 704                         ;
 705                         break;
 706                 case MONO_TYPE_VOID:
 707                         break;
 708                 default:
 709                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 710                 }
 711         }
 712
 713         /* this */
 714         if (sig->hasthis)
 715                 add_general (&gr, &stack_size, cinfo->args + 0);
 716
 717         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 718                 gr = PARAM_REGS;
 719                 fr = FLOAT_PARAM_REGS;
 720
 721                 /* Emit the signature cookie just before the implicit arguments */
 722                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 723         }
 724
 725         for (i = 0; i < sig->param_count; ++i) {
 726                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 727                 MonoType *ptype;
 728
 729 #ifdef HOST_WIN32
 730                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 731                 if (gr > fr)
 732                         fr = gr;
 733                 else if (fr > gr)
 734                         gr = fr;
 735 #endif
 736
 737                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 738                         /* We allways pass the sig cookie on the stack for simplicity */
 739                         /*
 740                          * Prevent implicit arguments + the sig cookie from being passed
 741                          * in registers.
 742                          */
 743                         gr = PARAM_REGS;
 744                         fr = FLOAT_PARAM_REGS;
 745
 746                         /* Emit the signature cookie just before the implicit arguments */
 747                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 748                 }
 749
 750                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 751                 switch (ptype->type) {
 752                 case MONO_TYPE_BOOLEAN:
 753                 case MONO_TYPE_I1:
 754                 case MONO_TYPE_U1:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_I2:
 758                 case MONO_TYPE_U2:
 759                 case MONO_TYPE_CHAR:
 760                         add_general (&gr, &stack_size, ainfo);
 761                         break;
 762                 case MONO_TYPE_I4:
 763                 case MONO_TYPE_U4:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_I:
 767                 case MONO_TYPE_U:
 768                 case MONO_TYPE_PTR:
 769                 case MONO_TYPE_FNPTR:
 770                 case MONO_TYPE_CLASS:
 771                 case MONO_TYPE_OBJECT:
 772                 case MONO_TYPE_STRING:
 773                 case MONO_TYPE_SZARRAY:
 774                 case MONO_TYPE_ARRAY:
 775                         add_general (&gr, &stack_size, ainfo);
 776                         break;
 777                 case MONO_TYPE_GENERICINST:
 778                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 779                                 add_general (&gr, &stack_size, ainfo);
 780                                 break;
 781                         }
 782                         /* fall through */
 783                 case MONO_TYPE_VALUETYPE:
 784                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 785                         break;
 786                 case MONO_TYPE_TYPEDBYREF:
 787 #ifdef HOST_WIN32
 788                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 789 #else
 790                         stack_size += sizeof (MonoTypedRef);
 791                         ainfo->storage = ArgOnStack;
 792 #endif
 793                         break;
 794                 case MONO_TYPE_U8:
 795                 case MONO_TYPE_I8:
 796                         add_general (&gr, &stack_size, ainfo);
 797                         break;
 798                 case MONO_TYPE_R4:
 799                         add_float (&fr, &stack_size, ainfo, FALSE);
 800                         break;
 801                 case MONO_TYPE_R8:
 802                         add_float (&fr, &stack_size, ainfo, TRUE);
 803                         break;
 804                 default:
 805                         g_assert_not_reached ();
 806                 }
 807         }
 808
 809         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 810                 gr = PARAM_REGS;
 811                 fr = FLOAT_PARAM_REGS;
 812
 813                 /* Emit the signature cookie just before the implicit arguments */
 814                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 815         }
 816
 817 #ifdef HOST_WIN32
 818         // There always is 32 bytes reserved on the stack when calling on Winx64
 819         stack_size += 0x20;
 820 #endif
 821
 822         if (stack_size & 0x8) {
 823                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 824                 cinfo->need_stack_align = TRUE;
 825                 stack_size += 8;
 826         }
 827
 828         cinfo->stack_usage = stack_size;
 829         cinfo->reg_usage = gr;
 830         cinfo->freg_usage = fr;
 831         return cinfo;
 832 }
 833
 834 /*
 835  * mono_arch_get_argument_info:
 836  * @csig:  a method signature
 837  * @param_count: the number of parameters to consider
 838  * @arg_info: an array to store the result infos
 839  *
 840  * Gathers information on parameters such as size, alignment and
 841  * padding. arg_info should be large enought to hold param_count + 1 entries.
 842  *
 843  * Returns the size of the argument area on the stack.
 844  */
 845 int
 846 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 847 {
 848         int k;
 849         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 850         guint32 args_size = cinfo->stack_usage;
 851
 852         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 853         if (csig->hasthis) {
 854                 arg_info [0].offset = 0;
 855         }
 856
 857         for (k = 0; k < param_count; k++) {
 858                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 859                 /* FIXME: */
 860                 arg_info [k + 1].size = 0;
 861         }
 862
 863         g_free (cinfo);
 864
 865         return args_size;
 866 }
 867
 868 static int
 869 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 870 {
 871 #ifndef _MSC_VER
 872         __asm__ __volatile__ ("cpuid"
 873                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 874                 : "a" (id));
 875 #else
 876         int info[4];
 877         __cpuid(info, id);
 878         *p_eax = info[0];
 879         *p_ebx = info[1];
 880         *p_ecx = info[2];
 881         *p_edx = info[3];
 882 #endif
 883         return 1;
 884 }
 885
 886 /*
 887  * Initialize the cpu to execute managed code.
 888  */
 889 void
 890 mono_arch_cpu_init (void)
 891 {
 892 #ifndef _MSC_VER
 893         guint16 fpcw;
 894
 895         /* spec compliance requires running with double precision */
 896         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 897         fpcw &= ~X86_FPCW_PRECC_MASK;
 898         fpcw |= X86_FPCW_PREC_DOUBLE;
 899         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 900         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 901 #else
 902         /* TODO: This is crashing on Win64 right now.
 903         * _control87 (_PC_53, MCW_PC);
 904         */
 905 #endif
 906 }
 907
 908 /*
 909  * Initialize architecture specific code.
 910  */
 911 void
 912 mono_arch_init (void)
 913 {
 914         int flags;
 915
 916         InitializeCriticalSection (&mini_arch_mutex);
 917
 918 #ifdef MONO_ARCH_NOMAP32BIT
 919         flags = MONO_MMAP_READ;
 920         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 921         breakpoint_size = 13;
 922         breakpoint_fault_size = 3;
 923         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 924         single_step_fault_size = 5;
 925 #else
 926         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 927         /* amd64_mov_reg_mem () */
 928         breakpoint_size = 8;
 929         breakpoint_fault_size = 8;
 930         single_step_fault_size = 8;
 931 #endif
 932
 933         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 934         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 935         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 936 }
 937
 938 /*
 939  * Cleanup architecture specific code.
 940  */
 941 void
 942 mono_arch_cleanup (void)
 943 {
 944         DeleteCriticalSection (&mini_arch_mutex);
 945 }
 946
 947 /*
 948  * This function returns the optimizations supported on this cpu.
 949  */
 950 guint32
 951 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 952 {
 953         int eax, ebx, ecx, edx;
 954         guint32 opts = 0;
 955
 956         /* FIXME: AMD64 */
 957
 958         *exclude_mask = 0;
 959         /* Feature Flags function, flags returned in EDX. */
 960         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 961                 if (edx & (1 << 15)) {
 962                         opts |= MONO_OPT_CMOV;
 963                         if (edx & 1)
 964                                 opts |= MONO_OPT_FCMOV;
 965                         else
 966                                 *exclude_mask |= MONO_OPT_FCMOV;
 967                 } else
 968                         *exclude_mask |= MONO_OPT_CMOV;
 969         }
 970
 971         return opts;
 972 }
 973
 974 /*
 975  * This function test for all SSE functions supported.
 976  *
 977  * Returns a bitmask corresponding to all supported versions.
 978  *
 979  */
 980 guint32
 981 mono_arch_cpu_enumerate_simd_versions (void)
 982 {
 983         int eax, ebx, ecx, edx;
 984         guint32 sse_opts = 0;
 985
 986         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 987                 if (edx & (1 << 25))
 988                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 989                 if (edx & (1 << 26))
 990                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 991                 if (ecx & (1 << 0))
 992                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 993                 if (ecx & (1 << 9))
 994                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 995                 if (ecx & (1 << 19))
 996                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 997                 if (ecx & (1 << 20))
 998                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 999         }
1000
1001         /* Yes, all this needs to be done to check for sse4a.
1002            See: "Amd: CPUID Specification"
1003          */
1004         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1005                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1006                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1007                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1008                         if (ecx & (1 << 6))
1009                                 sse_opts |= 1 << SIMD_VERSION_SSE4a;
1010                 }
1011         }
1012
1013         return sse_opts;
1014 }
1015
1016 #ifndef DISABLE_JIT
1017
1018 GList *
1019 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1020 {
1021         GList *vars = NULL;
1022         int i;
1023
1024         for (i = 0; i < cfg->num_varinfo; i++) {
1025                 MonoInst *ins = cfg->varinfo [i];
1026                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1027
1028                 /* unused vars */
1029                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1030                         continue;
1031
1032                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1033                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1034                         continue;
1035
1036                 if (mono_is_regsize_var (ins->inst_vtype)) {
1037                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1038                         g_assert (i == vmv->idx);
1039                         vars = g_list_prepend (vars, vmv);
1040                 }
1041         }
1042
1043         vars = mono_varlist_sort (cfg, vars, 0);
1044
1045         return vars;
1046 }
1047
1048 /**
1049  * mono_arch_compute_omit_fp:
1050  *
1051  *   Determine whenever the frame pointer can be eliminated.
1052  */
1053 static void
1054 mono_arch_compute_omit_fp (MonoCompile *cfg)
1055 {
1056         MonoMethodSignature *sig;
1057         MonoMethodHeader *header;
1058         int i, locals_size;
1059         CallInfo *cinfo;
1060
1061         if (cfg->arch.omit_fp_computed)
1062                 return;
1063
1064         header = cfg->header;
1065
1066         sig = mono_method_signature (cfg->method);
1067
1068         if (!cfg->arch.cinfo)
1069                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1070         cinfo = cfg->arch.cinfo;
1071
1072         /*
1073          * FIXME: Remove some of the restrictions.
1074          */
1075         cfg->arch.omit_fp = TRUE;
1076         cfg->arch.omit_fp_computed = TRUE;
1077
1078         if (cfg->disable_omit_fp)
1079                 cfg->arch.omit_fp = FALSE;
1080
1081         if (!debug_omit_fp ())
1082                 cfg->arch.omit_fp = FALSE;
1083         /*
1084         if (cfg->method->save_lmf)
1085                 cfg->arch.omit_fp = FALSE;
1086         */
1087         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1088                 cfg->arch.omit_fp = FALSE;
1089         if (header->num_clauses)
1090                 cfg->arch.omit_fp = FALSE;
1091         if (cfg->param_area)
1092                 cfg->arch.omit_fp = FALSE;
1093         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1094                 cfg->arch.omit_fp = FALSE;
1095         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1096                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1097                 cfg->arch.omit_fp = FALSE;
1098         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1099                 ArgInfo *ainfo = &cinfo->args [i];
1100
1101                 if (ainfo->storage == ArgOnStack) {
1102                         /*
1103                          * The stack offset can only be determined when the frame
1104                          * size is known.
1105                          */
1106                         cfg->arch.omit_fp = FALSE;
1107                 }
1108         }
1109
1110         locals_size = 0;
1111         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1112                 MonoInst *ins = cfg->varinfo [i];
1113                 int ialign;
1114
1115                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1116         }
1117 }
1118
1119 GList *
1120 mono_arch_get_global_int_regs (MonoCompile *cfg)
1121 {
1122         GList *regs = NULL;
1123
1124         mono_arch_compute_omit_fp (cfg);
1125
1126         if (cfg->globalra) {
1127                 if (cfg->arch.omit_fp)
1128                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1129
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1133                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1135
1136                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1137                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1138                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1139                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1140                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1141                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1142                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1143                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1144         } else {
1145                 if (cfg->arch.omit_fp)
1146                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1147
1148                 /* We use the callee saved registers for global allocation */
1149                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1150                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1151                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1152                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1153                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1154 #ifdef HOST_WIN32
1155                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1156                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1157 #endif
1158         }
1159
1160         return regs;
1161 }
1162
1163 GList*
1164 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1165 {
1166         GList *regs = NULL;
1167         int i;
1168
1169         /* All XMM registers */
1170         for (i = 0; i < 16; ++i)
1171                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1172
1173         return regs;
1174 }
1175
1176 GList*
1177 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1178 {
1179         static GList *r = NULL;
1180
1181         if (r == NULL) {
1182                 GList *regs = NULL;
1183
1184                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1185                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1186                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1187                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1188                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1189                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1190
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1192                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1193                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1194                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1195                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1196                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1197                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1198                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1199
1200                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1201         }
1202
1203         return r;
1204 }
1205
1206 GList*
1207 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1208 {
1209         int i;
1210         static GList *r = NULL;
1211
1212         if (r == NULL) {
1213                 GList *regs = NULL;
1214
1215                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1216                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1217
1218                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1219         }
1220
1221         return r;
1222 }
1223
1224 /*
1225  * mono_arch_regalloc_cost:
1226  *
1227  *  Return the cost, in number of memory references, of the action of
1228  * allocating the variable VMV into a register during global register
1229  * allocation.
1230  */
1231 guint32
1232 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1233 {
1234         MonoInst *ins = cfg->varinfo [vmv->idx];
1235
1236         if (cfg->method->save_lmf)
1237                 /* The register is already saved */
1238                 /* substract 1 for the invisible store in the prolog */
1239                 return (ins->opcode == OP_ARG) ? 0 : 1;
1240         else
1241                 /* push+pop */
1242                 return (ins->opcode == OP_ARG) ? 1 : 2;
1243 }
1244
1245 /*
1246  * mono_arch_fill_argument_info:
1247  *
1248  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1249  * of the method.
1250  */
1251 void
1252 mono_arch_fill_argument_info (MonoCompile *cfg)
1253 {
1254         MonoMethodSignature *sig;
1255         MonoMethodHeader *header;
1256         MonoInst *ins;
1257         int i;
1258         CallInfo *cinfo;
1259
1260         header = cfg->header;
1261
1262         sig = mono_method_signature (cfg->method);
1263
1264         cinfo = cfg->arch.cinfo;
1265
1266         /*
1267          * Contrary to mono_arch_allocate_vars (), the information should describe
1268          * where the arguments are at the beginning of the method, not where they can be
1269          * accessed during the execution of the method. The later makes no sense for the
1270          * global register allocator, since a variable can be in more than one location.
1271          */
1272         if (sig->ret->type != MONO_TYPE_VOID) {
1273                 switch (cinfo->ret.storage) {
1274                 case ArgInIReg:
1275                 case ArgInFloatSSEReg:
1276                 case ArgInDoubleSSEReg:
1277                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1278                                 cfg->vret_addr->opcode = OP_REGVAR;
1279                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1280                         }
1281                         else {
1282                                 cfg->ret->opcode = OP_REGVAR;
1283                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1284                         }
1285                         break;
1286                 case ArgValuetypeInReg:
1287                         cfg->ret->opcode = OP_REGOFFSET;
1288                         cfg->ret->inst_basereg = -1;
1289                         cfg->ret->inst_offset = -1;
1290                         break;
1291                 default:
1292                         g_assert_not_reached ();
1293                 }
1294         }
1295
1296         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1297                 ArgInfo *ainfo = &cinfo->args [i];
1298                 MonoType *arg_type;
1299
1300                 ins = cfg->args [i];
1301
1302                 if (sig->hasthis && (i == 0))
1303                         arg_type = &mono_defaults.object_class->byval_arg;
1304                 else
1305                         arg_type = sig->params [i - sig->hasthis];
1306
1307                 switch (ainfo->storage) {
1308                 case ArgInIReg:
1309                 case ArgInFloatSSEReg:
1310                 case ArgInDoubleSSEReg:
1311                         ins->opcode = OP_REGVAR;
1312                         ins->inst_c0 = ainfo->reg;
1313                         break;
1314                 case ArgOnStack:
1315                         ins->opcode = OP_REGOFFSET;
1316                         ins->inst_basereg = -1;
1317                         ins->inst_offset = -1;
1318                         break;
1319                 case ArgValuetypeInReg:
1320                         /* Dummy */
1321                         ins->opcode = OP_NOP;
1322                         break;
1323                 default:
1324                         g_assert_not_reached ();
1325                 }
1326         }
1327 }
1328
1329 void
1330 mono_arch_allocate_vars (MonoCompile *cfg)
1331 {
1332         MonoMethodSignature *sig;
1333         MonoMethodHeader *header;
1334         MonoInst *ins;
1335         int i, offset;
1336         guint32 locals_stack_size, locals_stack_align;
1337         gint32 *offsets;
1338         CallInfo *cinfo;
1339
1340         header = cfg->header;
1341
1342         sig = mono_method_signature (cfg->method);
1343
1344         cinfo = cfg->arch.cinfo;
1345
1346         mono_arch_compute_omit_fp (cfg);
1347
1348         /*
1349          * We use the ABI calling conventions for managed code as well.
1350          * Exception: valuetypes are only sometimes passed or returned in registers.
1351          */
1352
1353         /*
1354          * The stack looks like this:
1355          * <incoming arguments passed on the stack>
1356          * <return value>
1357          * <lmf/caller saved registers>
1358          * <locals>
1359          * <spill area>
1360          * <localloc area>  -> grows dynamically
1361          * <params area>
1362          */
1363
1364         if (cfg->arch.omit_fp) {
1365                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1366                 cfg->frame_reg = AMD64_RSP;
1367                 offset = 0;
1368         } else {
1369                 /* Locals are allocated backwards from %fp */
1370                 cfg->frame_reg = AMD64_RBP;
1371                 offset = 0;
1372         }
1373
1374         if (cfg->method->save_lmf) {
1375                 /* Reserve stack space for saving LMF */
1376                 if (cfg->arch.omit_fp) {
1377                         cfg->arch.lmf_offset = offset;
1378                         offset += sizeof (MonoLMF);
1379                 }
1380                 else {
1381                         offset += sizeof (MonoLMF);
1382                         cfg->arch.lmf_offset = -offset;
1383                 }
1384         } else {
1385                 if (cfg->arch.omit_fp)
1386                         cfg->arch.reg_save_area_offset = offset;
1387                 /* Reserve space for caller saved registers */
1388                 for (i = 0; i < AMD64_NREG; ++i)
1389                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1390                                 offset += sizeof (gpointer);
1391                         }
1392         }
1393
1394         if (sig->ret->type != MONO_TYPE_VOID) {
1395                 switch (cinfo->ret.storage) {
1396                 case ArgInIReg:
1397                 case ArgInFloatSSEReg:
1398                 case ArgInDoubleSSEReg:
1399                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1400                                 if (cfg->globalra) {
1401                                         cfg->vret_addr->opcode = OP_REGVAR;
1402                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1403                                 } else {
1404                                         /* The register is volatile */
1405                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1406                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1407                                         if (cfg->arch.omit_fp) {
1408                                                 cfg->vret_addr->inst_offset = offset;
1409                                                 offset += 8;
1410                                         } else {
1411                                                 offset += 8;
1412                                                 cfg->vret_addr->inst_offset = -offset;
1413                                         }
1414                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1415                                                 printf ("vret_addr =");
1416                                                 mono_print_ins (cfg->vret_addr);
1417                                         }
1418                                 }
1419                         }
1420                         else {
1421                                 cfg->ret->opcode = OP_REGVAR;
1422                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1423                         }
1424                         break;
1425                 case ArgValuetypeInReg:
1426                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1427                         cfg->ret->opcode = OP_REGOFFSET;
1428                         cfg->ret->inst_basereg = cfg->frame_reg;
1429                         if (cfg->arch.omit_fp) {
1430                                 cfg->ret->inst_offset = offset;
1431                                 offset += 16;
1432                         } else {
1433                                 offset += 16;
1434                                 cfg->ret->inst_offset = - offset;
1435                         }
1436                         break;
1437                 default:
1438                         g_assert_not_reached ();
1439                 }
1440                 if (!cfg->globalra)
1441                         cfg->ret->dreg = cfg->ret->inst_c0;
1442         }
1443
1444         /* Allocate locals */
1445         if (!cfg->globalra) {
1446                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1447                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1448                         char *mname = mono_method_full_name (cfg->method, TRUE);
1449                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1450                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1451                         g_free (mname);
1452                         return;
1453                 }
1454
1455                 if (locals_stack_align) {
1456                         offset += (locals_stack_align - 1);
1457                         offset &= ~(locals_stack_align - 1);
1458                 }
1459                 if (cfg->arch.omit_fp) {
1460                         cfg->locals_min_stack_offset = offset;
1461                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1462                 } else {
1463                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1464                         cfg->locals_max_stack_offset = - offset;
1465                 }
1466
1467                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1468                         if (offsets [i] != -1) {
1469                                 MonoInst *ins = cfg->varinfo [i];
1470                                 ins->opcode = OP_REGOFFSET;
1471                                 ins->inst_basereg = cfg->frame_reg;
1472                                 if (cfg->arch.omit_fp)
1473                                         ins->inst_offset = (offset + offsets [i]);
1474                                 else
1475                                         ins->inst_offset = - (offset + offsets [i]);
1476                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1477                         }
1478                 }
1479                 offset += locals_stack_size;
1480         }
1481
1482         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1483                 g_assert (!cfg->arch.omit_fp);
1484                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1485                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1486         }
1487
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ins = cfg->args [i];
1490                 if (ins->opcode != OP_REGVAR) {
1491                         ArgInfo *ainfo = &cinfo->args [i];
1492                         gboolean inreg = TRUE;
1493                         MonoType *arg_type;
1494
1495                         if (sig->hasthis && (i == 0))
1496                                 arg_type = &mono_defaults.object_class->byval_arg;
1497                         else
1498                                 arg_type = sig->params [i - sig->hasthis];
1499
1500                         if (cfg->globalra) {
1501                                 /* The new allocator needs info about the original locations of the arguments */
1502                                 switch (ainfo->storage) {
1503                                 case ArgInIReg:
1504                                 case ArgInFloatSSEReg:
1505                                 case ArgInDoubleSSEReg:
1506                                         ins->opcode = OP_REGVAR;
1507                                         ins->inst_c0 = ainfo->reg;
1508                                         break;
1509                                 case ArgOnStack:
1510                                         g_assert (!cfg->arch.omit_fp);
1511                                         ins->opcode = OP_REGOFFSET;
1512                                         ins->inst_basereg = cfg->frame_reg;
1513                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1514                                         break;
1515                                 case ArgValuetypeInReg:
1516                                         ins->opcode = OP_REGOFFSET;
1517                                         ins->inst_basereg = cfg->frame_reg;
1518                                         /* These arguments are saved to the stack in the prolog */
1519                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1520                                         if (cfg->arch.omit_fp) {
1521                                                 ins->inst_offset = offset;
1522                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1523                                         } else {
1524                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1525                                                 ins->inst_offset = - offset;
1526                                         }
1527                                         break;
1528                                 default:
1529                                         g_assert_not_reached ();
1530                                 }
1531
1532                                 continue;
1533                         }
1534
1535                         /* FIXME: Allocate volatile arguments to registers */
1536                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1537                                 inreg = FALSE;
1538
1539                         /*
1540                          * Under AMD64, all registers used to pass arguments to functions
1541                          * are volatile across calls.
1542                          * FIXME: Optimize this.
1543                          */
1544                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1545                                 inreg = FALSE;
1546
1547                         ins->opcode = OP_REGOFFSET;
1548
1549                         switch (ainfo->storage) {
1550                         case ArgInIReg:
1551                         case ArgInFloatSSEReg:
1552                         case ArgInDoubleSSEReg:
1553                                 if (inreg) {
1554                                         ins->opcode = OP_REGVAR;
1555                                         ins->dreg = ainfo->reg;
1556                                 }
1557                                 break;
1558                         case ArgOnStack:
1559                                 g_assert (!cfg->arch.omit_fp);
1560                                 ins->opcode = OP_REGOFFSET;
1561                                 ins->inst_basereg = cfg->frame_reg;
1562                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1563                                 break;
1564                         case ArgValuetypeInReg:
1565                                 break;
1566                         case ArgValuetypeAddrInIReg: {
1567                                 MonoInst *indir;
1568                                 g_assert (!cfg->arch.omit_fp);
1569
1570                                 MONO_INST_NEW (cfg, indir, 0);
1571                                 indir->opcode = OP_REGOFFSET;
1572                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1573                                         indir->inst_basereg = cfg->frame_reg;
1574                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1575                                         offset += (sizeof (gpointer));
1576                                         indir->inst_offset = - offset;
1577                                 }
1578                                 else {
1579                                         indir->inst_basereg = cfg->frame_reg;
1580                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1581                                 }
1582
1583                                 ins->opcode = OP_VTARG_ADDR;
1584                                 ins->inst_left = indir;
1585
1586                                 break;
1587                         }
1588                         default:
1589                                 NOT_IMPLEMENTED;
1590                         }
1591
1592                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1593                                 ins->opcode = OP_REGOFFSET;
1594                                 ins->inst_basereg = cfg->frame_reg;
1595                                 /* These arguments are saved to the stack in the prolog */
1596                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1597                                 if (cfg->arch.omit_fp) {
1598                                         ins->inst_offset = offset;
1599                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1600                                         // Arguments are yet supported by the stack map creation code
1601                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1602                                 } else {
1603                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1604                                         ins->inst_offset = - offset;
1605                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1606                                 }
1607                         }
1608                 }
1609         }
1610
1611         cfg->stack_offset = offset;
1612 }
1613
1614 void
1615 mono_arch_create_vars (MonoCompile *cfg)
1616 {
1617         MonoMethodSignature *sig;
1618         CallInfo *cinfo;
1619
1620         sig = mono_method_signature (cfg->method);
1621
1622         if (!cfg->arch.cinfo)
1623                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1624         cinfo = cfg->arch.cinfo;
1625
1626         if (cinfo->ret.storage == ArgValuetypeInReg)
1627                 cfg->ret_var_is_local = TRUE;
1628
1629         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1630                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1631                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1632                         printf ("vret_addr = ");
1633                         mono_print_ins (cfg->vret_addr);
1634                 }
1635         }
1636
1637         if (cfg->gen_seq_points) {
1638                 MonoInst *ins;
1639
1640             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1641                 ins->flags |= MONO_INST_VOLATILE;
1642                 cfg->arch.ss_trigger_page_var = ins;
1643         }
1644
1645 #ifdef MONO_AMD64_NO_PUSHES
1646         /*
1647          * When this is set, we pass arguments on the stack by moves, and by allocating
1648          * a bigger stack frame, instead of pushes.
1649          * Pushes complicate exception handling because the arguments on the stack have
1650          * to be popped each time a frame is unwound. They also make fp elimination
1651          * impossible.
1652          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1653          * on a new frame which doesn't include a param area.
1654          */
1655         cfg->arch.no_pushes = TRUE;
1656 #endif
1657 }
1658
1659 static void
1660 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1661 {
1662         MonoInst *ins;
1663
1664         switch (storage) {
1665         case ArgInIReg:
1666                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1667                 ins->dreg = mono_alloc_ireg (cfg);
1668                 ins->sreg1 = tree->dreg;
1669                 MONO_ADD_INS (cfg->cbb, ins);
1670                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1671                 break;
1672         case ArgInFloatSSEReg:
1673                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1674                 ins->dreg = mono_alloc_freg (cfg);
1675                 ins->sreg1 = tree->dreg;
1676                 MONO_ADD_INS (cfg->cbb, ins);
1677
1678                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1679                 break;
1680         case ArgInDoubleSSEReg:
1681                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1682                 ins->dreg = mono_alloc_freg (cfg);
1683                 ins->sreg1 = tree->dreg;
1684                 MONO_ADD_INS (cfg->cbb, ins);
1685
1686                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1687
1688                 break;
1689         default:
1690                 g_assert_not_reached ();
1691         }
1692 }
1693
1694 static int
1695 arg_storage_to_load_membase (ArgStorage storage)
1696 {
1697         switch (storage) {
1698         case ArgInIReg:
1699                 return OP_LOAD_MEMBASE;
1700         case ArgInDoubleSSEReg:
1701                 return OP_LOADR8_MEMBASE;
1702         case ArgInFloatSSEReg:
1703                 return OP_LOADR4_MEMBASE;
1704         default:
1705                 g_assert_not_reached ();
1706         }
1707
1708         return -1;
1709 }
1710
1711 static void
1712 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1713 {
1714         MonoInst *arg;
1715         MonoMethodSignature *tmp_sig;
1716         MonoInst *sig_arg;
1717
1718         if (call->tail_call)
1719                 NOT_IMPLEMENTED;
1720
1721         /* FIXME: Add support for signature tokens to AOT */
1722         cfg->disable_aot = TRUE;
1723
1724         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1725
1726         /*
1727          * mono_ArgIterator_Setup assumes the signature cookie is
1728          * passed first and all the arguments which were before it are
1729          * passed on the stack after the signature. So compensate by
1730          * passing a different signature.
1731          */
1732         tmp_sig = mono_metadata_signature_dup (call->signature);
1733         tmp_sig->param_count -= call->signature->sentinelpos;
1734         tmp_sig->sentinelpos = 0;
1735         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1736
1737         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1738         sig_arg->dreg = mono_alloc_ireg (cfg);
1739         sig_arg->inst_p0 = tmp_sig;
1740         MONO_ADD_INS (cfg->cbb, sig_arg);
1741
1742         if (cfg->arch.no_pushes) {
1743                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1744         } else {
1745                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1746                 arg->sreg1 = sig_arg->dreg;
1747                 MONO_ADD_INS (cfg->cbb, arg);
1748         }
1749 }
1750
1751 static inline LLVMArgStorage
1752 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1753 {
1754         switch (storage) {
1755         case ArgInIReg:
1756                 return LLVMArgInIReg;
1757         case ArgNone:
1758                 return LLVMArgNone;
1759         default:
1760                 g_assert_not_reached ();
1761                 return LLVMArgNone;
1762         }
1763 }
1764
1765 #ifdef ENABLE_LLVM
1766 LLVMCallInfo*
1767 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1768 {
1769         int i, n;
1770         CallInfo *cinfo;
1771         ArgInfo *ainfo;
1772         int j;
1773         LLVMCallInfo *linfo;
1774
1775         n = sig->param_count + sig->hasthis;
1776
1777         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1778
1779         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1780
1781         /*
1782          * LLVM always uses the native ABI while we use our own ABI, the
1783          * only difference is the handling of vtypes:
1784          * - we only pass/receive them in registers in some cases, and only
1785          *   in 1 or 2 integer registers.
1786          */
1787         if (cinfo->ret.storage == ArgValuetypeInReg) {
1788                 if (sig->pinvoke) {
1789                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1790                         cfg->disable_llvm = TRUE;
1791                         return linfo;
1792                 }
1793
1794                 linfo->ret.storage = LLVMArgVtypeInReg;
1795                 for (j = 0; j < 2; ++j)
1796                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1797         }
1798
1799         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1800                 /* Vtype returned using a hidden argument */
1801                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1802         }
1803
1804         for (i = 0; i < n; ++i) {
1805                 ainfo = cinfo->args + i;
1806
1807                 linfo->args [i].storage = LLVMArgNone;
1808
1809                 switch (ainfo->storage) {
1810                 case ArgInIReg:
1811                         linfo->args [i].storage = LLVMArgInIReg;
1812                         break;
1813                 case ArgInDoubleSSEReg:
1814                 case ArgInFloatSSEReg:
1815                         linfo->args [i].storage = LLVMArgInFPReg;
1816                         break;
1817                 case ArgOnStack:
1818                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1819                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1820                         } else {
1821                                 linfo->args [i].storage = LLVMArgInIReg;
1822                                 if (!sig->params [i - sig->hasthis]->byref) {
1823                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1824                                                 linfo->args [i].storage = LLVMArgInFPReg;
1825                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1826                                                 linfo->args [i].storage = LLVMArgInFPReg;
1827                                         }
1828                                 }
1829                         }
1830                         break;
1831                 case ArgValuetypeInReg:
1832                         if (sig->pinvoke) {
1833                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1834                                 cfg->disable_llvm = TRUE;
1835                                 return linfo;
1836                         }
1837
1838                         linfo->args [i].storage = LLVMArgVtypeInReg;
1839                         for (j = 0; j < 2; ++j)
1840                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1841                         break;
1842                 default:
1843                         cfg->exception_message = g_strdup ("ainfo->storage");
1844                         cfg->disable_llvm = TRUE;
1845                         break;
1846                 }
1847         }
1848
1849         return linfo;
1850 }
1851 #endif
1852
1853 void
1854 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1855 {
1856         MonoInst *arg, *in;
1857         MonoMethodSignature *sig;
1858         int i, n, stack_size;
1859         CallInfo *cinfo;
1860         ArgInfo *ainfo;
1861
1862         stack_size = 0;
1863
1864         sig = call->signature;
1865         n = sig->param_count + sig->hasthis;
1866
1867         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1868
1869         if (COMPILE_LLVM (cfg)) {
1870                 /* We shouldn't be called in the llvm case */
1871                 cfg->disable_llvm = TRUE;
1872                 return;
1873         }
1874
1875         if (cinfo->need_stack_align) {
1876                 if (!cfg->arch.no_pushes)
1877                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1878         }
1879
1880         /*
1881          * Emit all arguments which are passed on the stack to prevent register
1882          * allocation problems.
1883          */
1884         if (cfg->arch.no_pushes) {
1885                 for (i = 0; i < n; ++i) {
1886                         MonoType *t;
1887                         ainfo = cinfo->args + i;
1888
1889                         in = call->args [i];
1890
1891                         if (sig->hasthis && i == 0)
1892                                 t = &mono_defaults.object_class->byval_arg;
1893                         else
1894                                 t = sig->params [i - sig->hasthis];
1895
1896                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1897                                 if (!t->byref) {
1898                                         if (t->type == MONO_TYPE_R4)
1899                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1900                                         else if (t->type == MONO_TYPE_R8)
1901                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1902                                         else
1903                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1904                                 } else {
1905                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1906                                 }
1907                         }
1908                 }
1909         }
1910
1911         /*
1912          * Emit all parameters passed in registers in non-reverse order for better readability
1913          * and to help the optimization in emit_prolog ().
1914          */
1915         for (i = 0; i < n; ++i) {
1916                 ainfo = cinfo->args + i;
1917
1918                 in = call->args [i];
1919
1920                 if (ainfo->storage == ArgInIReg)
1921                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1922         }
1923
1924         for (i = n - 1; i >= 0; --i) {
1925                 ainfo = cinfo->args + i;
1926
1927                 in = call->args [i];
1928
1929                 switch (ainfo->storage) {
1930                 case ArgInIReg:
1931                         /* Already done */
1932                         break;
1933                 case ArgInFloatSSEReg:
1934                 case ArgInDoubleSSEReg:
1935                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1936                         break;
1937                 case ArgOnStack:
1938                 case ArgValuetypeInReg:
1939                 case ArgValuetypeAddrInIReg:
1940                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1941                                 MonoInst *call_inst = (MonoInst*)call;
1942                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1943                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1944                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1945                                 guint32 align;
1946                                 guint32 size;
1947
1948                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1949                                         size = sizeof (MonoTypedRef);
1950                                         align = sizeof (gpointer);
1951                                 }
1952                                 else {
1953                                         if (sig->pinvoke)
1954                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1955                                         else {
1956                                                 /*
1957                                                  * Other backends use mono_type_stack_size (), but that
1958                                                  * aligns the size to 8, which is larger than the size of
1959                                                  * the source, leading to reads of invalid memory if the
1960                                                  * source is at the end of address space.
1961                                                  */
1962                                                 size = mono_class_value_size (in->klass, &align);
1963                                         }
1964                                 }
1965                                 g_assert (in->klass);
1966
1967                                 if (size > 0) {
1968                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1969                                         arg->sreg1 = in->dreg;
1970                                         arg->klass = in->klass;
1971                                         arg->backend.size = size;
1972                                         arg->inst_p0 = call;
1973                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1974                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1975
1976                                         MONO_ADD_INS (cfg->cbb, arg);
1977                                 }
1978                         } else {
1979                                 if (cfg->arch.no_pushes) {
1980                                         /* Already done */
1981                                 } else {
1982                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1983                                         arg->sreg1 = in->dreg;
1984                                         if (!sig->params [i - sig->hasthis]->byref) {
1985                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1986                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1987                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1988                                                         arg->inst_destbasereg = X86_ESP;
1989                                                         arg->inst_offset = 0;
1990                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1991                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1992                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1993                                                         arg->inst_destbasereg = X86_ESP;
1994                                                         arg->inst_offset = 0;
1995                                                 }
1996                                         }
1997                                         MONO_ADD_INS (cfg->cbb, arg);
1998                                 }
1999                         }
2000                         break;
2001                 default:
2002                         g_assert_not_reached ();
2003                 }
2004
2005                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2006                         /* Emit the signature cookie just before the implicit arguments */
2007                         emit_sig_cookie (cfg, call, cinfo);
2008         }
2009
2010         /* Handle the case where there are no implicit arguments */
2011         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2012                 emit_sig_cookie (cfg, call, cinfo);
2013
2014         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2015                 MonoInst *vtarg;
2016
2017                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2018                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2019                                 /*
2020                                  * Tell the JIT to use a more efficient calling convention: call using
2021                                  * OP_CALL, compute the result location after the call, and save the
2022                                  * result there.
2023                                  */
2024                                 call->vret_in_reg = TRUE;
2025                                 /*
2026                                  * Nullify the instruction computing the vret addr to enable
2027                                  * future optimizations.
2028                                  */
2029                                 if (call->vret_var)
2030                                         NULLIFY_INS (call->vret_var);
2031                         } else {
2032                                 if (call->tail_call)
2033                                         NOT_IMPLEMENTED;
2034                                 /*
2035                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2036                                  * the stack. Push the address here, so the call instruction can
2037                                  * access it.
2038                                  */
2039                                 if (!cfg->arch.vret_addr_loc) {
2040                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2041                                         /* Prevent it from being register allocated or optimized away */
2042                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2043                                 }
2044
2045                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2046                         }
2047                 }
2048                 else {
2049                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2050                         vtarg->sreg1 = call->vret_var->dreg;
2051                         vtarg->dreg = mono_alloc_preg (cfg);
2052                         MONO_ADD_INS (cfg->cbb, vtarg);
2053
2054                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2055                 }
2056         }
2057
2058 #ifdef HOST_WIN32
2059         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2060                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2061         }
2062 #endif
2063
2064         if (cfg->method->save_lmf) {
2065                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2066                 MONO_ADD_INS (cfg->cbb, arg);
2067         }
2068
2069         call->stack_usage = cinfo->stack_usage;
2070 }
2071
2072 void
2073 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2074 {
2075         MonoInst *arg;
2076         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2077         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2078         int size = ins->backend.size;
2079
2080         if (ainfo->storage == ArgValuetypeInReg) {
2081                 MonoInst *load;
2082                 int part;
2083
2084                 for (part = 0; part < 2; ++part) {
2085                         if (ainfo->pair_storage [part] == ArgNone)
2086                                 continue;
2087
2088                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2089                         load->inst_basereg = src->dreg;
2090                         load->inst_offset = part * sizeof (gpointer);
2091
2092                         switch (ainfo->pair_storage [part]) {
2093                         case ArgInIReg:
2094                                 load->dreg = mono_alloc_ireg (cfg);
2095                                 break;
2096                         case ArgInDoubleSSEReg:
2097                         case ArgInFloatSSEReg:
2098                                 load->dreg = mono_alloc_freg (cfg);
2099                                 break;
2100                         default:
2101                                 g_assert_not_reached ();
2102                         }
2103                         MONO_ADD_INS (cfg->cbb, load);
2104
2105                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2106                 }
2107         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2108                 MonoInst *vtaddr, *load;
2109                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2110
2111                 g_assert (!cfg->arch.no_pushes);
2112
2113                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2114                 load->inst_p0 = vtaddr;
2115                 vtaddr->flags |= MONO_INST_INDIRECT;
2116                 load->type = STACK_MP;
2117                 load->klass = vtaddr->klass;
2118                 load->dreg = mono_alloc_ireg (cfg);
2119                 MONO_ADD_INS (cfg->cbb, load);
2120                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2121
2122                 if (ainfo->pair_storage [0] == ArgInIReg) {
2123                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2124                         arg->dreg = mono_alloc_ireg (cfg);
2125                         arg->sreg1 = load->dreg;
2126                         arg->inst_imm = 0;
2127                         MONO_ADD_INS (cfg->cbb, arg);
2128                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2129                 } else {
2130                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2131                         arg->sreg1 = load->dreg;
2132                         MONO_ADD_INS (cfg->cbb, arg);
2133                 }
2134         } else {
2135                 if (size == 8) {
2136                         if (cfg->arch.no_pushes) {
2137                                 int dreg = mono_alloc_ireg (cfg);
2138
2139                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2140                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2141                         } else {
2142                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2143                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2144                                 arg->inst_basereg = src->dreg;
2145                                 arg->inst_offset = 0;
2146                                 MONO_ADD_INS (cfg->cbb, arg);
2147                         }
2148                 } else if (size <= 40) {
2149                         if (cfg->arch.no_pushes) {
2150                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2151                         } else {
2152                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2153                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2154                         }
2155                 } else {
2156                         if (cfg->arch.no_pushes) {
2157                                 // FIXME: Code growth
2158                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2159                         } else {
2160                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2161                                 arg->inst_basereg = src->dreg;
2162                                 arg->inst_offset = 0;
2163                                 arg->inst_imm = size;
2164                                 MONO_ADD_INS (cfg->cbb, arg);
2165                         }
2166                 }
2167         }
2168 }
2169
2170 void
2171 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2172 {
2173         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2174
2175         if (ret->type == MONO_TYPE_R4) {
2176                 if (COMPILE_LLVM (cfg))
2177                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2178                 else
2179                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2180                 return;
2181         } else if (ret->type == MONO_TYPE_R8) {
2182                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2183                 return;
2184         }
2185
2186         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2187 }
2188
2189 #endif /* DISABLE_JIT */
2190
2191 #define EMIT_COND_BRANCH(ins,cond,sign) \
2192         if (ins->inst_true_bb->native_offset) { \
2193                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2194         } else { \
2195                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2196                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2197             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2198                         x86_branch8 (code, cond, 0, sign); \
2199                 else \
2200                         x86_branch32 (code, cond, 0, sign); \
2201 }
2202
2203 typedef struct {
2204         MonoMethodSignature *sig;
2205         CallInfo *cinfo;
2206 } ArchDynCallInfo;
2207
2208 typedef struct {
2209         mgreg_t regs [PARAM_REGS];
2210         mgreg_t res;
2211         guint8 *ret;
2212 } DynCallArgs;
2213
2214 static gboolean
2215 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2216 {
2217         int i;
2218
2219 #ifdef HOST_WIN32
2220         return FALSE;
2221 #endif
2222
2223         switch (cinfo->ret.storage) {
2224         case ArgNone:
2225         case ArgInIReg:
2226                 break;
2227         case ArgValuetypeInReg: {
2228                 ArgInfo *ainfo = &cinfo->ret;
2229
2230                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2231                         return FALSE;
2232                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2233                         return FALSE;
2234                 break;
2235         }
2236         default:
2237                 return FALSE;
2238         }
2239
2240         for (i = 0; i < cinfo->nargs; ++i) {
2241                 ArgInfo *ainfo = &cinfo->args [i];
2242                 switch (ainfo->storage) {
2243                 case ArgInIReg:
2244                         break;
2245                 case ArgValuetypeInReg:
2246                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2247                                 return FALSE;
2248                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2249                                 return FALSE;
2250                         break;
2251                 default:
2252                         return FALSE;
2253                 }
2254         }
2255
2256         return TRUE;
2257 }
2258
2259 /*
2260  * mono_arch_dyn_call_prepare:
2261  *
2262  *   Return a pointer to an arch-specific structure which contains information
2263  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2264  * supported for SIG.
2265  * This function is equivalent to ffi_prep_cif in libffi.
2266  */
2267 MonoDynCallInfo*
2268 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2269 {
2270         ArchDynCallInfo *info;
2271         CallInfo *cinfo;
2272
2273         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2274
2275         if (!dyn_call_supported (sig, cinfo)) {
2276                 g_free (cinfo);
2277                 return NULL;
2278         }
2279
2280         info = g_new0 (ArchDynCallInfo, 1);
2281         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2282         info->sig = sig;
2283         info->cinfo = cinfo;
2284
2285         return (MonoDynCallInfo*)info;
2286 }
2287
2288 /*
2289  * mono_arch_dyn_call_free:
2290  *
2291  *   Free a MonoDynCallInfo structure.
2292  */
2293 void
2294 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2295 {
2296         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2297
2298         g_free (ainfo->cinfo);
2299         g_free (ainfo);
2300 }
2301
2302 /*
2303  * mono_arch_get_start_dyn_call:
2304  *
2305  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2306  * store the result into BUF.
2307  * ARGS should be an array of pointers pointing to the arguments.
2308  * RET should point to a memory buffer large enought to hold the result of the
2309  * call.
2310  * This function should be as fast as possible, any work which does not depend
2311  * on the actual values of the arguments should be done in
2312  * mono_arch_dyn_call_prepare ().
2313  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2314  * libffi.
2315  */
2316 void
2317 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2318 {
2319         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2320         DynCallArgs *p = (DynCallArgs*)buf;
2321         int arg_index, greg, i;
2322         MonoMethodSignature *sig = dinfo->sig;
2323
2324         g_assert (buf_len >= sizeof (DynCallArgs));
2325
2326         p->res = 0;
2327         p->ret = ret;
2328
2329         arg_index = 0;
2330         greg = 0;
2331
2332         if (dinfo->cinfo->vtype_retaddr)
2333                 p->regs [greg ++] = (mgreg_t)ret;
2334
2335         if (sig->hasthis) {
2336                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2337         }
2338
2339         for (i = 0; i < sig->param_count; i++) {
2340                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2341                 gpointer *arg = args [arg_index ++];
2342
2343                 if (t->byref) {
2344                         p->regs [greg ++] = (mgreg_t)*(arg);
2345                         continue;
2346                 }
2347
2348                 switch (t->type) {
2349                 case MONO_TYPE_STRING:
2350                 case MONO_TYPE_CLASS:
2351                 case MONO_TYPE_ARRAY:
2352                 case MONO_TYPE_SZARRAY:
2353                 case MONO_TYPE_OBJECT:
2354                 case MONO_TYPE_PTR:
2355                 case MONO_TYPE_I:
2356                 case MONO_TYPE_U:
2357                 case MONO_TYPE_I8:
2358                 case MONO_TYPE_U8:
2359                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2360                         p->regs [greg ++] = (mgreg_t)*(arg);
2361                         break;
2362                 case MONO_TYPE_BOOLEAN:
2363                 case MONO_TYPE_U1:
2364                         p->regs [greg ++] = *(guint8*)(arg);
2365                         break;
2366                 case MONO_TYPE_I1:
2367                         p->regs [greg ++] = *(gint8*)(arg);
2368                         break;
2369                 case MONO_TYPE_I2:
2370                         p->regs [greg ++] = *(gint16*)(arg);
2371                         break;
2372                 case MONO_TYPE_U2:
2373                 case MONO_TYPE_CHAR:
2374                         p->regs [greg ++] = *(guint16*)(arg);
2375                         break;
2376                 case MONO_TYPE_I4:
2377                         p->regs [greg ++] = *(gint32*)(arg);
2378                         break;
2379                 case MONO_TYPE_U4:
2380                         p->regs [greg ++] = *(guint32*)(arg);
2381                         break;
2382                 case MONO_TYPE_GENERICINST:
2383                     if (MONO_TYPE_IS_REFERENCE (t)) {
2384                                 p->regs [greg ++] = (mgreg_t)*(arg);
2385                                 break;
2386                         } else {
2387                                 /* Fall through */
2388                         }
2389                 case MONO_TYPE_VALUETYPE: {
2390                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2391
2392                         g_assert (ainfo->storage == ArgValuetypeInReg);
2393                         if (ainfo->pair_storage [0] != ArgNone) {
2394                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2395                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2396                         }
2397                         if (ainfo->pair_storage [1] != ArgNone) {
2398                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2399                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2400                         }
2401                         break;
2402                 }
2403                 default:
2404                         g_assert_not_reached ();
2405                 }
2406         }
2407
2408         g_assert (greg <= PARAM_REGS);
2409 }
2410
2411 /*
2412  * mono_arch_finish_dyn_call:
2413  *
2414  *   Store the result of a dyn call into the return value buffer passed to
2415  * start_dyn_call ().
2416  * This function should be as fast as possible, any work which does not depend
2417  * on the actual values of the arguments should be done in
2418  * mono_arch_dyn_call_prepare ().
2419  */
2420 void
2421 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2422 {
2423         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2424         MonoMethodSignature *sig = dinfo->sig;
2425         guint8 *ret = ((DynCallArgs*)buf)->ret;
2426         mgreg_t res = ((DynCallArgs*)buf)->res;
2427
2428         switch (mono_type_get_underlying_type (sig->ret)->type) {
2429         case MONO_TYPE_VOID:
2430                 *(gpointer*)ret = NULL;
2431                 break;
2432         case MONO_TYPE_STRING:
2433         case MONO_TYPE_CLASS:
2434         case MONO_TYPE_ARRAY:
2435         case MONO_TYPE_SZARRAY:
2436         case MONO_TYPE_OBJECT:
2437         case MONO_TYPE_I:
2438         case MONO_TYPE_U:
2439         case MONO_TYPE_PTR:
2440                 *(gpointer*)ret = (gpointer)res;
2441                 break;
2442         case MONO_TYPE_I1:
2443                 *(gint8*)ret = res;
2444                 break;
2445         case MONO_TYPE_U1:
2446         case MONO_TYPE_BOOLEAN:
2447                 *(guint8*)ret = res;
2448                 break;
2449         case MONO_TYPE_I2:
2450                 *(gint16*)ret = res;
2451                 break;
2452         case MONO_TYPE_U2:
2453         case MONO_TYPE_CHAR:
2454                 *(guint16*)ret = res;
2455                 break;
2456         case MONO_TYPE_I4:
2457                 *(gint32*)ret = res;
2458                 break;
2459         case MONO_TYPE_U4:
2460                 *(guint32*)ret = res;
2461                 break;
2462         case MONO_TYPE_I8:
2463                 *(gint64*)ret = res;
2464                 break;
2465         case MONO_TYPE_U8:
2466                 *(guint64*)ret = res;
2467                 break;
2468         case MONO_TYPE_GENERICINST:
2469                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2470                         *(gpointer*)ret = (gpointer)res;
2471                         break;
2472                 } else {
2473                         /* Fall through */
2474                 }
2475         case MONO_TYPE_VALUETYPE:
2476                 if (dinfo->cinfo->vtype_retaddr) {
2477                         /* Nothing to do */
2478                 } else {
2479                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2480
2481                         g_assert (ainfo->storage == ArgValuetypeInReg);
2482
2483                         if (ainfo->pair_storage [0] != ArgNone) {
2484                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2485                                 ((mgreg_t*)ret)[0] = res;
2486                         }
2487
2488                         g_assert (ainfo->pair_storage [1] == ArgNone);
2489                 }
2490                 break;
2491         default:
2492                 g_assert_not_reached ();
2493         }
2494 }
2495
2496 /* emit an exception if condition is fail */
2497 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2498         do {                                                        \
2499                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2500                 if (tins == NULL) {                                                                             \
2501                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2502                                         MONO_PATCH_INFO_EXC, exc_name);  \
2503                         x86_branch32 (code, cond, 0, signed);               \
2504                 } else {        \
2505                         EMIT_COND_BRANCH (tins, cond, signed);  \
2506                 }                       \
2507         } while (0);
2508
2509 #define EMIT_FPCOMPARE(code) do { \
2510         amd64_fcompp (code); \
2511         amd64_fnstsw (code); \
2512 } while (0);
2513
2514 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2515     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2516         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2517         amd64_ ##op (code); \
2518         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2519         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2520 } while (0);
2521
2522 static guint8*
2523 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2524 {
2525         gboolean no_patch = FALSE;
2526
2527         /*
2528          * FIXME: Add support for thunks
2529          */
2530         {
2531                 gboolean near_call = FALSE;
2532
2533                 /*
2534                  * Indirect calls are expensive so try to make a near call if possible.
2535                  * The caller memory is allocated by the code manager so it is
2536                  * guaranteed to be at a 32 bit offset.
2537                  */
2538
2539                 if (patch_type != MONO_PATCH_INFO_ABS) {
2540                         /* The target is in memory allocated using the code manager */
2541                         near_call = TRUE;
2542
2543                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2544                                 if (((MonoMethod*)data)->klass->image->aot_module)
2545                                         /* The callee might be an AOT method */
2546                                         near_call = FALSE;
2547                                 if (((MonoMethod*)data)->dynamic)
2548                                         /* The target is in malloc-ed memory */
2549                                         near_call = FALSE;
2550                         }
2551
2552                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2553                                 /*
2554                                  * The call might go directly to a native function without
2555                                  * the wrapper.
2556                                  */
2557                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2558                                 if (mi) {
2559                                         gconstpointer target = mono_icall_get_wrapper (mi);
2560                                         if ((((guint64)target) >> 32) != 0)
2561                                                 near_call = FALSE;
2562                                 }
2563                         }
2564                 }
2565                 else {
2566                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2567                                 /*
2568                                  * This is not really an optimization, but required because the
2569                                  * generic class init trampolines use R11 to pass the vtable.
2570                                  */
2571                                 near_call = TRUE;
2572                         } else {
2573                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2574                                 if (info) {
2575                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2576                                                 strstr (cfg->method->name, info->name)) {
2577                                                 /* A call to the wrapped function */
2578                                                 if ((((guint64)data) >> 32) == 0)
2579                                                         near_call = TRUE;
2580                                                 no_patch = TRUE;
2581                                         }
2582                                         else if (info->func == info->wrapper) {
2583                                                 /* No wrapper */
2584                                                 if ((((guint64)info->func) >> 32) == 0)
2585                                                         near_call = TRUE;
2586                                         }
2587                                         else {
2588                                                 /* See the comment in mono_codegen () */
2589                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2590                                                         near_call = TRUE;
2591                                         }
2592                                 }
2593                                 else if ((((guint64)data) >> 32) == 0) {
2594                                         near_call = TRUE;
2595                                         no_patch = TRUE;
2596                                 }
2597                         }
2598                 }
2599
2600                 if (cfg->method->dynamic)
2601                         /* These methods are allocated using malloc */
2602                         near_call = FALSE;
2603
2604 #ifdef MONO_ARCH_NOMAP32BIT
2605                 near_call = FALSE;
2606 #endif
2607
2608                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2609                 if (optimize_for_xen)
2610                         near_call = FALSE;
2611
2612                 if (cfg->compile_aot) {
2613                         near_call = TRUE;
2614                         no_patch = TRUE;
2615                 }
2616
2617                 if (near_call) {
2618                         /*
2619                          * Align the call displacement to an address divisible by 4 so it does
2620                          * not span cache lines. This is required for code patching to work on SMP
2621                          * systems.
2622                          */
2623                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2624                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2625                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2626                         amd64_call_code (code, 0);
2627                 }
2628                 else {
2629                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2630                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2631                         amd64_call_reg (code, GP_SCRATCH_REG);
2632                 }
2633         }
2634
2635         return code;
2636 }
2637
2638 static inline guint8*
2639 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2640 {
2641 #ifdef HOST_WIN32
2642         if (win64_adjust_stack)
2643                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2644 #endif
2645         code = emit_call_body (cfg, code, patch_type, data);
2646 #ifdef HOST_WIN32
2647         if (win64_adjust_stack)
2648                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2649 #endif
2650
2651         return code;
2652 }
2653
2654 static inline int
2655 store_membase_imm_to_store_membase_reg (int opcode)
2656 {
2657         switch (opcode) {
2658         case OP_STORE_MEMBASE_IMM:
2659                 return OP_STORE_MEMBASE_REG;
2660         case OP_STOREI4_MEMBASE_IMM:
2661                 return OP_STOREI4_MEMBASE_REG;
2662         case OP_STOREI8_MEMBASE_IMM:
2663                 return OP_STOREI8_MEMBASE_REG;
2664         }
2665
2666         return -1;
2667 }
2668
2669 #ifndef DISABLE_JIT
2670
2671 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2672
2673 /*
2674  * mono_arch_peephole_pass_1:
2675  *
2676  *   Perform peephole opts which should/can be performed before local regalloc
2677  */
2678 void
2679 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2680 {
2681         MonoInst *ins, *n;
2682
2683         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2684                 MonoInst *last_ins = ins->prev;
2685
2686                 switch (ins->opcode) {
2687                 case OP_ADD_IMM:
2688                 case OP_IADD_IMM:
2689                 case OP_LADD_IMM:
2690                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2691                                 /*
2692                                  * X86_LEA is like ADD, but doesn't have the
2693                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2694                                  * its operand to 64 bit.
2695                                  */
2696                                 ins->opcode = OP_X86_LEA_MEMBASE;
2697                                 ins->inst_basereg = ins->sreg1;
2698                         }
2699                         break;
2700                 case OP_LXOR:
2701                 case OP_IXOR:
2702                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2703                                 MonoInst *ins2;
2704
2705                                 /*
2706                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2707                                  * the latter has length 2-3 instead of 6 (reverse constant
2708                                  * propagation). These instruction sequences are very common
2709                                  * in the initlocals bblock.
2710                                  */
2711                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2712                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2713                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2714                                                 ins2->sreg1 = ins->dreg;
2715                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2716                                                 /* Continue */
2717                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2718                                                 NULLIFY_INS (ins2);
2719                                                 /* Continue */
2720                                         } else {
2721                                                 break;
2722                                         }
2723                                 }
2724                         }
2725                         break;
2726                 case OP_COMPARE_IMM:
2727                 case OP_LCOMPARE_IMM:
2728                         /* OP_COMPARE_IMM (reg, 0)
2729                          * -->
2730                          * OP_AMD64_TEST_NULL (reg)
2731                          */
2732                         if (!ins->inst_imm)
2733                                 ins->opcode = OP_AMD64_TEST_NULL;
2734                         break;
2735                 case OP_ICOMPARE_IMM:
2736                         if (!ins->inst_imm)
2737                                 ins->opcode = OP_X86_TEST_NULL;
2738                         break;
2739                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2740                         /*
2741                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2742                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2743                          * -->
2744                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2745                          * OP_COMPARE_IMM reg, imm
2746                          *
2747                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2748                          */
2749                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2750                             ins->inst_basereg == last_ins->inst_destbasereg &&
2751                             ins->inst_offset == last_ins->inst_offset) {
2752                                         ins->opcode = OP_ICOMPARE_IMM;
2753                                         ins->sreg1 = last_ins->sreg1;
2754
2755                                         /* check if we can remove cmp reg,0 with test null */
2756                                         if (!ins->inst_imm)
2757                                                 ins->opcode = OP_X86_TEST_NULL;
2758                                 }
2759
2760                         break;
2761                 }
2762
2763                 mono_peephole_ins (bb, ins);
2764         }
2765 }
2766
2767 void
2768 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2769 {
2770         MonoInst *ins, *n;
2771
2772         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2773                 switch (ins->opcode) {
2774                 case OP_ICONST:
2775                 case OP_I8CONST: {
2776                         /* reg = 0 -> XOR (reg, reg) */
2777                         /* XOR sets cflags on x86, so we cant do it always */
2778                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2779                                 ins->opcode = OP_LXOR;
2780                                 ins->sreg1 = ins->dreg;
2781                                 ins->sreg2 = ins->dreg;
2782                                 /* Fall through */
2783                         } else {
2784                                 break;
2785                         }
2786                 }
2787                 case OP_LXOR:
2788                         /*
2789                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2790                          * 0 result into 64 bits.
2791                          */
2792                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2793                                 ins->opcode = OP_IXOR;
2794                         }
2795                         /* Fall through */
2796                 case OP_IXOR:
2797                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2798                                 MonoInst *ins2;
2799
2800                                 /*
2801                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2802                                  * the latter has length 2-3 instead of 6 (reverse constant
2803                                  * propagation). These instruction sequences are very common
2804                                  * in the initlocals bblock.
2805                                  */
2806                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2807                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2808                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2809                                                 ins2->sreg1 = ins->dreg;
2810                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2811                                                 /* Continue */
2812                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2813                                                 NULLIFY_INS (ins2);
2814                                                 /* Continue */
2815                                         } else {
2816                                                 break;
2817                                         }
2818                                 }
2819                         }
2820                         break;
2821                 case OP_IADD_IMM:
2822                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2823                                 ins->opcode = OP_X86_INC_REG;
2824                         break;
2825                 case OP_ISUB_IMM:
2826                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2827                                 ins->opcode = OP_X86_DEC_REG;
2828                         break;
2829                 }
2830
2831                 mono_peephole_ins (bb, ins);
2832         }
2833 }
2834
2835 #define NEW_INS(cfg,ins,dest,op) do {   \
2836                 MONO_INST_NEW ((cfg), (dest), (op)); \
2837         (dest)->cil_code = (ins)->cil_code; \
2838         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2839         } while (0)
2840
2841 /*
2842  * mono_arch_lowering_pass:
2843  *
2844  *  Converts complex opcodes into simpler ones so that each IR instruction
2845  * corresponds to one machine instruction.
2846  */
2847 void
2848 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2849 {
2850         MonoInst *ins, *n, *temp;
2851
2852         /*
2853          * FIXME: Need to add more instructions, but the current machine
2854          * description can't model some parts of the composite instructions like
2855          * cdq.
2856          */
2857         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2858                 switch (ins->opcode) {
2859                 case OP_DIV_IMM:
2860                 case OP_REM_IMM:
2861                 case OP_IDIV_IMM:
2862                 case OP_IDIV_UN_IMM:
2863                 case OP_IREM_UN_IMM:
2864                         mono_decompose_op_imm (cfg, bb, ins);
2865                         break;
2866                 case OP_IREM_IMM:
2867                         /* Keep the opcode if we can implement it efficiently */
2868                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2869                                 mono_decompose_op_imm (cfg, bb, ins);
2870                         break;
2871                 case OP_COMPARE_IMM:
2872                 case OP_LCOMPARE_IMM:
2873                         if (!amd64_is_imm32 (ins->inst_imm)) {
2874                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2875                                 temp->inst_c0 = ins->inst_imm;
2876                                 temp->dreg = mono_alloc_ireg (cfg);
2877                                 ins->opcode = OP_COMPARE;
2878                                 ins->sreg2 = temp->dreg;
2879                         }
2880                         break;
2881                 case OP_LOAD_MEMBASE:
2882                 case OP_LOADI8_MEMBASE:
2883                         if (!amd64_is_imm32 (ins->inst_offset)) {
2884                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2885                                 temp->inst_c0 = ins->inst_offset;
2886                                 temp->dreg = mono_alloc_ireg (cfg);
2887                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2888                                 ins->inst_indexreg = temp->dreg;
2889                         }
2890                         break;
2891                 case OP_STORE_MEMBASE_IMM:
2892                 case OP_STOREI8_MEMBASE_IMM:
2893                         if (!amd64_is_imm32 (ins->inst_imm)) {
2894                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2895                                 temp->inst_c0 = ins->inst_imm;
2896                                 temp->dreg = mono_alloc_ireg (cfg);
2897                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2898                                 ins->sreg1 = temp->dreg;
2899                         }
2900                         break;
2901 #ifdef MONO_ARCH_SIMD_INTRINSICS
2902                 case OP_EXPAND_I1: {
2903                                 int temp_reg1 = mono_alloc_ireg (cfg);
2904                                 int temp_reg2 = mono_alloc_ireg (cfg);
2905                                 int original_reg = ins->sreg1;
2906
2907                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2908                                 temp->sreg1 = original_reg;
2909                                 temp->dreg = temp_reg1;
2910
2911                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2912                                 temp->sreg1 = temp_reg1;
2913                                 temp->dreg = temp_reg2;
2914                                 temp->inst_imm = 8;
2915
2916                                 NEW_INS (cfg, ins, temp, OP_LOR);
2917                                 temp->sreg1 = temp->dreg = temp_reg2;
2918                                 temp->sreg2 = temp_reg1;
2919
2920                                 ins->opcode = OP_EXPAND_I2;
2921                                 ins->sreg1 = temp_reg2;
2922                         }
2923                         break;
2924 #endif
2925                 default:
2926                         break;
2927                 }
2928         }
2929
2930         bb->max_vreg = cfg->next_vreg;
2931 }
2932
2933 static const int
2934 branch_cc_table [] = {
2935         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2936         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2937         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2938 };
2939
2940 /* Maps CMP_... constants to X86_CC_... constants */
2941 static const int
2942 cc_table [] = {
2943         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2944         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2945 };
2946
2947 static const int
2948 cc_signed_table [] = {
2949         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2950         FALSE, FALSE, FALSE, FALSE
2951 };
2952
2953 /*#include "cprop.c"*/
2954
2955 static unsigned char*
2956 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2957 {
2958         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2959
2960         if (size == 1)
2961                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2962         else if (size == 2)
2963                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2964         return code;
2965 }
2966
2967 static unsigned char*
2968 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2969 {
2970         int sreg = tree->sreg1;
2971         int need_touch = FALSE;
2972
2973 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2974         if (!tree->flags & MONO_INST_INIT)
2975                 need_touch = TRUE;
2976 #endif
2977
2978         if (need_touch) {
2979                 guint8* br[5];
2980
2981                 /*
2982                  * Under Windows:
2983                  * If requested stack size is larger than one page,
2984                  * perform stack-touch operation
2985                  */
2986                 /*
2987                  * Generate stack probe code.
2988                  * Under Windows, it is necessary to allocate one page at a time,
2989                  * "touching" stack after each successful sub-allocation. This is
2990                  * because of the way stack growth is implemented - there is a
2991                  * guard page before the lowest stack page that is currently commited.
2992                  * Stack normally grows sequentially so OS traps access to the
2993                  * guard page and commits more pages when needed.
2994                  */
2995                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2996                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2997
2998                 br[2] = code; /* loop */
2999                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3000                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3001                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3002                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3003                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3004                 amd64_patch (br[3], br[2]);
3005                 amd64_test_reg_reg (code, sreg, sreg);
3006                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3007                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3008
3009                 br[1] = code; x86_jump8 (code, 0);
3010
3011                 amd64_patch (br[0], code);
3012                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3013                 amd64_patch (br[1], code);
3014                 amd64_patch (br[4], code);
3015         }
3016         else
3017                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3018
3019         if (tree->flags & MONO_INST_INIT) {
3020                 int offset = 0;
3021                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3022                         amd64_push_reg (code, AMD64_RAX);
3023                         offset += 8;
3024                 }
3025                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3026                         amd64_push_reg (code, AMD64_RCX);
3027                         offset += 8;
3028                 }
3029                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3030                         amd64_push_reg (code, AMD64_RDI);
3031                         offset += 8;
3032                 }
3033
3034                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3035                 if (sreg != AMD64_RCX)
3036                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3037                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3038
3039                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3040                 if (cfg->param_area && cfg->arch.no_pushes)
3041                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3042                 amd64_cld (code);
3043                 amd64_prefix (code, X86_REP_PREFIX);
3044                 amd64_stosl (code);
3045
3046                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3047                         amd64_pop_reg (code, AMD64_RDI);
3048                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3049                         amd64_pop_reg (code, AMD64_RCX);
3050                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3051                         amd64_pop_reg (code, AMD64_RAX);
3052         }
3053         return code;
3054 }
3055
3056 static guint8*
3057 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3058 {
3059         CallInfo *cinfo;
3060         guint32 quad;
3061
3062         /* Move return value to the target register */
3063         /* FIXME: do this in the local reg allocator */
3064         switch (ins->opcode) {
3065         case OP_CALL:
3066         case OP_CALL_REG:
3067         case OP_CALL_MEMBASE:
3068         case OP_LCALL:
3069         case OP_LCALL_REG:
3070         case OP_LCALL_MEMBASE:
3071                 g_assert (ins->dreg == AMD64_RAX);
3072                 break;
3073         case OP_FCALL:
3074         case OP_FCALL_REG:
3075         case OP_FCALL_MEMBASE:
3076                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3077                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3078                 }
3079                 else {
3080                         if (ins->dreg != AMD64_XMM0)
3081                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3082                 }
3083                 break;
3084         case OP_VCALL:
3085         case OP_VCALL_REG:
3086         case OP_VCALL_MEMBASE:
3087         case OP_VCALL2:
3088         case OP_VCALL2_REG:
3089         case OP_VCALL2_MEMBASE:
3090                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3091                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3092                         MonoInst *loc = cfg->arch.vret_addr_loc;
3093
3094                         /* Load the destination address */
3095                         g_assert (loc->opcode == OP_REGOFFSET);
3096                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3097
3098                         for (quad = 0; quad < 2; quad ++) {
3099                                 switch (cinfo->ret.pair_storage [quad]) {
3100                                 case ArgInIReg:
3101                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3102                                         break;
3103                                 case ArgInFloatSSEReg:
3104                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3105                                         break;
3106                                 case ArgInDoubleSSEReg:
3107                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3108                                         break;
3109                                 case ArgNone:
3110                                         break;
3111                                 default:
3112                                         NOT_IMPLEMENTED;
3113                                 }
3114                         }
3115                 }
3116                 break;
3117         }
3118
3119         return code;
3120 }
3121
3122 #endif /* DISABLE_JIT */
3123
3124 /*
3125  * mono_amd64_emit_tls_get:
3126  * @code: buffer to store code to
3127  * @dreg: hard register where to place the result
3128  * @tls_offset: offset info
3129  *
3130  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3131  * the dreg register the item in the thread local storage identified
3132  * by tls_offset.
3133  *
3134  * Returns: a pointer to the end of the stored code
3135  */
3136 guint8*
3137 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3138 {
3139 #ifdef HOST_WIN32
3140         g_assert (tls_offset < 64);
3141         x86_prefix (code, X86_GS_PREFIX);
3142         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3143 #else
3144         if (optimize_for_xen) {
3145                 x86_prefix (code, X86_FS_PREFIX);
3146                 amd64_mov_reg_mem (code, dreg, 0, 8);
3147                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3148         } else {
3149                 x86_prefix (code, X86_FS_PREFIX);
3150                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3151         }
3152 #endif
3153         return code;
3154 }
3155
3156 #define REAL_PRINT_REG(text,reg) \
3157 mono_assert (reg >= 0); \
3158 amd64_push_reg (code, AMD64_RAX); \
3159 amd64_push_reg (code, AMD64_RDX); \
3160 amd64_push_reg (code, AMD64_RCX); \
3161 amd64_push_reg (code, reg); \
3162 amd64_push_imm (code, reg); \
3163 amd64_push_imm (code, text " %d %p\n"); \
3164 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3165 amd64_call_reg (code, AMD64_RAX); \
3166 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3167 amd64_pop_reg (code, AMD64_RCX); \
3168 amd64_pop_reg (code, AMD64_RDX); \
3169 amd64_pop_reg (code, AMD64_RAX);
3170
3171 /* benchmark and set based on cpu */
3172 #define LOOP_ALIGNMENT 8
3173 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3174
3175 #ifndef DISABLE_JIT
3176
3177 void
3178 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3179 {
3180         MonoInst *ins;
3181         MonoCallInst *call;
3182         guint offset;
3183         guint8 *code = cfg->native_code + cfg->code_len;
3184         MonoInst *last_ins = NULL;
3185         guint last_offset = 0;
3186         int max_len;
3187
3188         /* Fix max_offset estimate for each successor bb */
3189         if (cfg->opt & MONO_OPT_BRANCH) {
3190                 int current_offset = cfg->code_len;
3191                 MonoBasicBlock *current_bb;
3192                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3193                         current_bb->max_offset = current_offset;
3194                         current_offset += current_bb->max_length;
3195                 }
3196         }
3197
3198         if (cfg->opt & MONO_OPT_LOOP) {
3199                 int pad, align = LOOP_ALIGNMENT;
3200                 /* set alignment depending on cpu */
3201                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3202                         pad = align - pad;
3203                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3204                         amd64_padding (code, pad);
3205                         cfg->code_len += pad;
3206                         bb->native_offset = cfg->code_len;
3207                 }
3208         }
3209
3210         if (cfg->verbose_level > 2)
3211                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3212
3213         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3214                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3215                 g_assert (!cfg->compile_aot);
3216
3217                 cov->data [bb->dfn].cil_code = bb->cil_code;
3218                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3219                 /* this is not thread save, but good enough */
3220                 amd64_inc_membase (code, AMD64_R11, 0);
3221         }
3222
3223         offset = code - cfg->native_code;
3224
3225         mono_debug_open_block (cfg, bb, offset);
3226
3227     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3228                 x86_breakpoint (code);
3229
3230         MONO_BB_FOR_EACH_INS (bb, ins) {
3231                 offset = code - cfg->native_code;
3232
3233                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3234
3235                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3236                         cfg->code_size *= 2;
3237                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3238                         code = cfg->native_code + offset;
3239                         mono_jit_stats.code_reallocs++;
3240                 }
3241
3242                 if (cfg->debug_info)
3243                         mono_debug_record_line_number (cfg, ins, offset);
3244
3245                 switch (ins->opcode) {
3246                 case OP_BIGMUL:
3247                         amd64_mul_reg (code, ins->sreg2, TRUE);
3248                         break;
3249                 case OP_BIGMUL_UN:
3250                         amd64_mul_reg (code, ins->sreg2, FALSE);
3251                         break;
3252                 case OP_X86_SETEQ_MEMBASE:
3253                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3254                         break;
3255                 case OP_STOREI1_MEMBASE_IMM:
3256                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3257                         break;
3258                 case OP_STOREI2_MEMBASE_IMM:
3259                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3260                         break;
3261                 case OP_STOREI4_MEMBASE_IMM:
3262                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3263                         break;
3264                 case OP_STOREI1_MEMBASE_REG:
3265                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3266                         break;
3267                 case OP_STOREI2_MEMBASE_REG:
3268                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3269                         break;
3270                 case OP_STORE_MEMBASE_REG:
3271                 case OP_STOREI8_MEMBASE_REG:
3272                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3273                         break;
3274                 case OP_STOREI4_MEMBASE_REG:
3275                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3276                         break;
3277                 case OP_STORE_MEMBASE_IMM:
3278                 case OP_STOREI8_MEMBASE_IMM:
3279                         g_assert (amd64_is_imm32 (ins->inst_imm));
3280                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3281                         break;
3282                 case OP_LOAD_MEM:
3283                 case OP_LOADI8_MEM:
3284                         // FIXME: Decompose this earlier
3285                         if (amd64_is_imm32 (ins->inst_imm))
3286                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3287                         else {
3288                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3289                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3290                         }
3291                         break;
3292                 case OP_LOADI4_MEM:
3293                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3294                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3295                         break;
3296                 case OP_LOADU4_MEM:
3297                         // FIXME: Decompose this earlier
3298                         if (amd64_is_imm32 (ins->inst_imm))
3299                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3300                         else {
3301                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3302                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3303                         }
3304                         break;
3305                 case OP_LOADU1_MEM:
3306                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3307                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3308                         break;
3309                 case OP_LOADU2_MEM:
3310                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3311                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3312                         break;
3313                 case OP_LOAD_MEMBASE:
3314                 case OP_LOADI8_MEMBASE:
3315                         g_assert (amd64_is_imm32 (ins->inst_offset));
3316                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3317                         break;
3318                 case OP_LOADI4_MEMBASE:
3319                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3320                         break;
3321                 case OP_LOADU4_MEMBASE:
3322                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3323                         break;
3324                 case OP_LOADU1_MEMBASE:
3325                         /* The cpu zero extends the result into 64 bits */
3326                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3327                         break;
3328                 case OP_LOADI1_MEMBASE:
3329                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3330                         break;
3331                 case OP_LOADU2_MEMBASE:
3332                         /* The cpu zero extends the result into 64 bits */
3333                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3334                         break;
3335                 case OP_LOADI2_MEMBASE:
3336                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3337                         break;
3338                 case OP_AMD64_LOADI8_MEMINDEX:
3339                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3340                         break;
3341                 case OP_LCONV_TO_I1:
3342                 case OP_ICONV_TO_I1:
3343                 case OP_SEXT_I1:
3344                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3345                         break;
3346                 case OP_LCONV_TO_I2:
3347                 case OP_ICONV_TO_I2:
3348                 case OP_SEXT_I2:
3349                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3350                         break;
3351                 case OP_LCONV_TO_U1:
3352                 case OP_ICONV_TO_U1:
3353                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3354                         break;
3355                 case OP_LCONV_TO_U2:
3356                 case OP_ICONV_TO_U2:
3357                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3358                         break;
3359                 case OP_ZEXT_I4:
3360                         /* Clean out the upper word */
3361                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3362                         break;
3363                 case OP_SEXT_I4:
3364                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3365                         break;
3366                 case OP_COMPARE:
3367                 case OP_LCOMPARE:
3368                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3369                         break;
3370                 case OP_COMPARE_IMM:
3371                 case OP_LCOMPARE_IMM:
3372                         g_assert (amd64_is_imm32 (ins->inst_imm));
3373                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3374                         break;
3375                 case OP_X86_COMPARE_REG_MEMBASE:
3376                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3377                         break;
3378                 case OP_X86_TEST_NULL:
3379                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3380                         break;
3381                 case OP_AMD64_TEST_NULL:
3382                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3383                         break;
3384
3385                 case OP_X86_ADD_REG_MEMBASE:
3386                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3387                         break;
3388                 case OP_X86_SUB_REG_MEMBASE:
3389                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3390                         break;
3391                 case OP_X86_AND_REG_MEMBASE:
3392                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3393                         break;
3394                 case OP_X86_OR_REG_MEMBASE:
3395                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3396                         break;
3397                 case OP_X86_XOR_REG_MEMBASE:
3398                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3399                         break;
3400
3401                 case OP_X86_ADD_MEMBASE_IMM:
3402                         /* FIXME: Make a 64 version too */
3403                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3404                         break;
3405                 case OP_X86_SUB_MEMBASE_IMM:
3406                         g_assert (amd64_is_imm32 (ins->inst_imm));
3407                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3408                         break;
3409                 case OP_X86_AND_MEMBASE_IMM:
3410                         g_assert (amd64_is_imm32 (ins->inst_imm));
3411                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3412                         break;
3413                 case OP_X86_OR_MEMBASE_IMM:
3414                         g_assert (amd64_is_imm32 (ins->inst_imm));
3415                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3416                         break;
3417                 case OP_X86_XOR_MEMBASE_IMM:
3418                         g_assert (amd64_is_imm32 (ins->inst_imm));
3419                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3420                         break;
3421                 case OP_X86_ADD_MEMBASE_REG:
3422                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3423                         break;
3424                 case OP_X86_SUB_MEMBASE_REG:
3425                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3426                         break;
3427                 case OP_X86_AND_MEMBASE_REG:
3428                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3429                         break;
3430                 case OP_X86_OR_MEMBASE_REG:
3431                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3432                         break;
3433                 case OP_X86_XOR_MEMBASE_REG:
3434                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3435                         break;
3436                 case OP_X86_INC_MEMBASE:
3437                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3438                         break;
3439                 case OP_X86_INC_REG:
3440                         amd64_inc_reg_size (code, ins->dreg, 4);
3441                         break;
3442                 case OP_X86_DEC_MEMBASE:
3443                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3444                         break;
3445                 case OP_X86_DEC_REG:
3446                         amd64_dec_reg_size (code, ins->dreg, 4);
3447                         break;
3448                 case OP_X86_MUL_REG_MEMBASE:
3449                 case OP_X86_MUL_MEMBASE_REG:
3450                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3451                         break;
3452                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3453                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3454                         break;
3455                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3456                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3457                         break;
3458                 case OP_AMD64_COMPARE_MEMBASE_REG:
3459                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3460                         break;
3461                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3462                         g_assert (amd64_is_imm32 (ins->inst_imm));
3463                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3464                         break;
3465                 case OP_X86_COMPARE_MEMBASE8_IMM:
3466                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3467                         break;
3468                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3469                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3470                         break;
3471                 case OP_AMD64_COMPARE_REG_MEMBASE:
3472                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3473                         break;
3474
3475                 case OP_AMD64_ADD_REG_MEMBASE:
3476                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3477                         break;
3478                 case OP_AMD64_SUB_REG_MEMBASE:
3479                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3480                         break;
3481                 case OP_AMD64_AND_REG_MEMBASE:
3482                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3483                         break;
3484                 case OP_AMD64_OR_REG_MEMBASE:
3485                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3486                         break;
3487                 case OP_AMD64_XOR_REG_MEMBASE:
3488                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3489                         break;
3490
3491                 case OP_AMD64_ADD_MEMBASE_REG:
3492                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3493                         break;
3494                 case OP_AMD64_SUB_MEMBASE_REG:
3495                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3496                         break;
3497                 case OP_AMD64_AND_MEMBASE_REG:
3498                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3499                         break;
3500                 case OP_AMD64_OR_MEMBASE_REG:
3501                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3502                         break;
3503                 case OP_AMD64_XOR_MEMBASE_REG:
3504                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3505                         break;
3506
3507                 case OP_AMD64_ADD_MEMBASE_IMM:
3508                         g_assert (amd64_is_imm32 (ins->inst_imm));
3509                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3510                         break;
3511                 case OP_AMD64_SUB_MEMBASE_IMM:
3512                         g_assert (amd64_is_imm32 (ins->inst_imm));
3513                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3514                         break;
3515                 case OP_AMD64_AND_MEMBASE_IMM:
3516                         g_assert (amd64_is_imm32 (ins->inst_imm));
3517                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3518                         break;
3519                 case OP_AMD64_OR_MEMBASE_IMM:
3520                         g_assert (amd64_is_imm32 (ins->inst_imm));
3521                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3522                         break;
3523                 case OP_AMD64_XOR_MEMBASE_IMM:
3524                         g_assert (amd64_is_imm32 (ins->inst_imm));
3525                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3526                         break;
3527
3528                 case OP_BREAK:
3529                         amd64_breakpoint (code);
3530                         break;
3531                 case OP_RELAXED_NOP:
3532                         x86_prefix (code, X86_REP_PREFIX);
3533                         x86_nop (code);
3534                         break;
3535                 case OP_HARD_NOP:
3536                         x86_nop (code);
3537                         break;
3538                 case OP_NOP:
3539                 case OP_DUMMY_USE:
3540                 case OP_DUMMY_STORE:
3541                 case OP_NOT_REACHED:
3542                 case OP_NOT_NULL:
3543                         break;
3544                 case OP_SEQ_POINT: {
3545                         int i;
3546
3547                         if (cfg->compile_aot)
3548                                 NOT_IMPLEMENTED;
3549
3550                         /*
3551                          * Read from the single stepping trigger page. This will cause a
3552                          * SIGSEGV when single stepping is enabled.
3553                          * We do this _before_ the breakpoint, so single stepping after
3554                          * a breakpoint is hit will step to the next IL offset.
3555                          */
3556                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3557                                 if (((guint64)ss_trigger_page >> 32) == 0)
3558                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3559                                 else {
3560                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3561
3562                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3563                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3564                                 }
3565                         }
3566
3567                         /*
3568                          * This is the address which is saved in seq points,
3569                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3570                          * from the address of the instruction causing the fault.
3571                          */
3572                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3573
3574                         /*
3575                          * A placeholder for a possible breakpoint inserted by
3576                          * mono_arch_set_breakpoint ().
3577                          */
3578                         for (i = 0; i < breakpoint_size; ++i)
3579                                 x86_nop (code);
3580                         break;
3581                 }
3582                 case OP_ADDCC:
3583                 case OP_LADD:
3584                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3585                         break;
3586                 case OP_ADC:
3587                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3588                         break;
3589                 case OP_ADD_IMM:
3590                 case OP_LADD_IMM:
3591                         g_assert (amd64_is_imm32 (ins->inst_imm));
3592                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3593                         break;
3594                 case OP_ADC_IMM:
3595                         g_assert (amd64_is_imm32 (ins->inst_imm));
3596                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3597                         break;
3598                 case OP_SUBCC:
3599                 case OP_LSUB:
3600                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3601                         break;
3602                 case OP_SBB:
3603                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3604                         break;
3605                 case OP_SUB_IMM:
3606                 case OP_LSUB_IMM:
3607                         g_assert (amd64_is_imm32 (ins->inst_imm));
3608                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3609                         break;
3610                 case OP_SBB_IMM:
3611                         g_assert (amd64_is_imm32 (ins->inst_imm));
3612                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3613                         break;
3614                 case OP_LAND:
3615                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3616                         break;
3617                 case OP_AND_IMM:
3618                 case OP_LAND_IMM:
3619                         g_assert (amd64_is_imm32 (ins->inst_imm));
3620                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3621                         break;
3622                 case OP_LMUL:
3623                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3624                         break;
3625                 case OP_MUL_IMM:
3626                 case OP_LMUL_IMM:
3627                 case OP_IMUL_IMM: {
3628                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3629
3630                         switch (ins->inst_imm) {
3631                         case 2:
3632                                 /* MOV r1, r2 */
3633                                 /* ADD r1, r1 */
3634                                 if (ins->dreg != ins->sreg1)
3635                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3636                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3637                                 break;
3638                         case 3:
3639                                 /* LEA r1, [r2 + r2*2] */
3640                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3641                                 break;
3642                         case 5:
3643                                 /* LEA r1, [r2 + r2*4] */
3644                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3645                                 break;
3646                         case 6:
3647                                 /* LEA r1, [r2 + r2*2] */
3648                                 /* ADD r1, r1          */
3649                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3650                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3651                                 break;
3652                         case 9:
3653                                 /* LEA r1, [r2 + r2*8] */
3654                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3655                                 break;
3656                         case 10:
3657                                 /* LEA r1, [r2 + r2*4] */
3658                                 /* ADD r1, r1          */
3659                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3660                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3661                                 break;
3662                         case 12:
3663                                 /* LEA r1, [r2 + r2*2] */
3664                                 /* SHL r1, 2           */
3665                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3666                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3667                                 break;
3668                         case 25:
3669                                 /* LEA r1, [r2 + r2*4] */
3670                                 /* LEA r1, [r1 + r1*4] */
3671                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3672                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3673                                 break;
3674                         case 100:
3675                                 /* LEA r1, [r2 + r2*4] */
3676                                 /* SHL r1, 2           */
3677                                 /* LEA r1, [r1 + r1*4] */
3678                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3679                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3680                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3681                                 break;
3682                         default:
3683                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3684                                 break;
3685                         }
3686                         break;
3687                 }
3688                 case OP_LDIV:
3689                 case OP_LREM:
3690                         /* Regalloc magic makes the div/rem cases the same */
3691                         if (ins->sreg2 == AMD64_RDX) {
3692                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3693                                 amd64_cdq (code);
3694                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3695                         } else {
3696                                 amd64_cdq (code);
3697                                 amd64_div_reg (code, ins->sreg2, TRUE);
3698                         }
3699                         break;
3700                 case OP_LDIV_UN:
3701                 case OP_LREM_UN:
3702                         if (ins->sreg2 == AMD64_RDX) {
3703                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3704                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3705                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3706                         } else {
3707                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3708                                 amd64_div_reg (code, ins->sreg2, FALSE);
3709                         }
3710                         break;
3711                 case OP_IDIV:
3712                 case OP_IREM:
3713                         if (ins->sreg2 == AMD64_RDX) {
3714                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3715                                 amd64_cdq_size (code, 4);
3716                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3717                         } else {
3718                                 amd64_cdq_size (code, 4);
3719                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3720                         }
3721                         break;
3722                 case OP_IDIV_UN:
3723                 case OP_IREM_UN:
3724                         if (ins->sreg2 == AMD64_RDX) {
3725                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3726                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3727                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3728                         } else {
3729                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3730                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3731                         }
3732                         break;
3733                 case OP_IREM_IMM: {
3734                         int power = mono_is_power_of_two (ins->inst_imm);
3735
3736                         g_assert (ins->sreg1 == X86_EAX);
3737                         g_assert (ins->dreg == X86_EAX);
3738                         g_assert (power >= 0);
3739
3740                         if (power == 0) {
3741                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3742                                 break;
3743                         }
3744
3745                         /* Based on gcc code */
3746
3747                         /* Add compensation for negative dividents */
3748                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3749                         if (power > 1)
3750                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3751                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3752                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3753                         /* Compute remainder */
3754                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3755                         /* Remove compensation */
3756                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3757                         break;
3758                 }
3759                 case OP_LMUL_OVF:
3760                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3761                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3762                         break;
3763                 case OP_LOR:
3764                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3765                         break;
3766                 case OP_OR_IMM:
3767                 case OP_LOR_IMM:
3768                         g_assert (amd64_is_imm32 (ins->inst_imm));
3769                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3770                         break;
3771                 case OP_LXOR:
3772                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3773                         break;
3774                 case OP_XOR_IMM:
3775                 case OP_LXOR_IMM:
3776                         g_assert (amd64_is_imm32 (ins->inst_imm));
3777                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3778                         break;
3779                 case OP_LSHL:
3780                         g_assert (ins->sreg2 == AMD64_RCX);
3781                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3782                         break;
3783                 case OP_LSHR:
3784                         g_assert (ins->sreg2 == AMD64_RCX);
3785                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3786                         break;
3787                 case OP_SHR_IMM:
3788                         g_assert (amd64_is_imm32 (ins->inst_imm));
3789                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3790                         break;
3791                 case OP_LSHR_IMM:
3792                         g_assert (amd64_is_imm32 (ins->inst_imm));
3793                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3794                         break;
3795                 case OP_SHR_UN_IMM:
3796                         g_assert (amd64_is_imm32 (ins->inst_imm));
3797                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3798                         break;
3799                 case OP_LSHR_UN_IMM:
3800                         g_assert (amd64_is_imm32 (ins->inst_imm));
3801                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3802                         break;
3803                 case OP_LSHR_UN:
3804                         g_assert (ins->sreg2 == AMD64_RCX);
3805                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3806                         break;
3807                 case OP_SHL_IMM:
3808                         g_assert (amd64_is_imm32 (ins->inst_imm));
3809                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3810                         break;
3811                 case OP_LSHL_IMM:
3812                         g_assert (amd64_is_imm32 (ins->inst_imm));
3813                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3814                         break;
3815
3816                 case OP_IADDCC:
3817                 case OP_IADD:
3818                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3819                         break;
3820                 case OP_IADC:
3821                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3822                         break;
3823                 case OP_IADD_IMM:
3824                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3825                         break;
3826                 case OP_IADC_IMM:
3827                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3828                         break;
3829                 case OP_ISUBCC:
3830                 case OP_ISUB:
3831                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3832                         break;
3833                 case OP_ISBB:
3834                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3835                         break;
3836                 case OP_ISUB_IMM:
3837                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3838                         break;
3839                 case OP_ISBB_IMM:
3840                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3841                         break;
3842                 case OP_IAND:
3843                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3844                         break;
3845                 case OP_IAND_IMM:
3846                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3847                         break;
3848                 case OP_IOR:
3849                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3850                         break;
3851                 case OP_IOR_IMM:
3852                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3853                         break;
3854                 case OP_IXOR:
3855                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3856                         break;
3857                 case OP_IXOR_IMM:
3858                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3859                         break;
3860                 case OP_INEG:
3861                         amd64_neg_reg_size (code, ins->sreg1, 4);
3862                         break;
3863                 case OP_INOT:
3864                         amd64_not_reg_size (code, ins->sreg1, 4);
3865                         break;
3866                 case OP_ISHL:
3867                         g_assert (ins->sreg2 == AMD64_RCX);
3868                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3869                         break;
3870                 case OP_ISHR:
3871                         g_assert (ins->sreg2 == AMD64_RCX);
3872                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3873                         break;
3874                 case OP_ISHR_IMM:
3875                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3876                         break;
3877                 case OP_ISHR_UN_IMM:
3878                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3879                         break;
3880                 case OP_ISHR_UN:
3881                         g_assert (ins->sreg2 == AMD64_RCX);
3882                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3883                         break;
3884                 case OP_ISHL_IMM:
3885                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3886                         break;
3887                 case OP_IMUL:
3888                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3889                         break;
3890                 case OP_IMUL_OVF:
3891                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3892                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3893                         break;
3894                 case OP_IMUL_OVF_UN:
3895                 case OP_LMUL_OVF_UN: {
3896                         /* the mul operation and the exception check should most likely be split */
3897                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3898                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3899                         /*g_assert (ins->sreg2 == X86_EAX);
3900                         g_assert (ins->dreg == X86_EAX);*/
3901                         if (ins->sreg2 == X86_EAX) {
3902                                 non_eax_reg = ins->sreg1;
3903                         } else if (ins->sreg1 == X86_EAX) {
3904                                 non_eax_reg = ins->sreg2;
3905                         } else {
3906                                 /* no need to save since we're going to store to it anyway */
3907                                 if (ins->dreg != X86_EAX) {
3908                                         saved_eax = TRUE;
3909                                         amd64_push_reg (code, X86_EAX);
3910                                 }
3911                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3912                                 non_eax_reg = ins->sreg2;
3913                         }
3914                         if (ins->dreg == X86_EDX) {
3915                                 if (!saved_eax) {
3916                                         saved_eax = TRUE;
3917                                         amd64_push_reg (code, X86_EAX);
3918                                 }
3919                         } else {
3920                                 saved_edx = TRUE;
3921                                 amd64_push_reg (code, X86_EDX);
3922                         }
3923                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3924                         /* save before the check since pop and mov don't change the flags */
3925                         if (ins->dreg != X86_EAX)
3926                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3927                         if (saved_edx)
3928                                 amd64_pop_reg (code, X86_EDX);
3929                         if (saved_eax)
3930                                 amd64_pop_reg (code, X86_EAX);
3931                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3932                         break;
3933                 }
3934                 case OP_ICOMPARE:
3935                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3936                         break;
3937                 case OP_ICOMPARE_IMM:
3938                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3939                         break;
3940                 case OP_IBEQ:
3941                 case OP_IBLT:
3942                 case OP_IBGT:
3943                 case OP_IBGE:
3944                 case OP_IBLE:
3945                 case OP_LBEQ:
3946                 case OP_LBLT:
3947                 case OP_LBGT:
3948                 case OP_LBGE:
3949                 case OP_LBLE:
3950                 case OP_IBNE_UN:
3951                 case OP_IBLT_UN:
3952                 case OP_IBGT_UN:
3953                 case OP_IBGE_UN:
3954                 case OP_IBLE_UN:
3955                 case OP_LBNE_UN:
3956                 case OP_LBLT_UN:
3957                 case OP_LBGT_UN:
3958                 case OP_LBGE_UN:
3959                 case OP_LBLE_UN:
3960                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3961                         break;
3962
3963                 case OP_CMOV_IEQ:
3964                 case OP_CMOV_IGE:
3965                 case OP_CMOV_IGT:
3966                 case OP_CMOV_ILE:
3967                 case OP_CMOV_ILT:
3968                 case OP_CMOV_INE_UN:
3969                 case OP_CMOV_IGE_UN:
3970                 case OP_CMOV_IGT_UN:
3971                 case OP_CMOV_ILE_UN:
3972                 case OP_CMOV_ILT_UN:
3973                 case OP_CMOV_LEQ:
3974                 case OP_CMOV_LGE:
3975                 case OP_CMOV_LGT:
3976                 case OP_CMOV_LLE:
3977                 case OP_CMOV_LLT:
3978                 case OP_CMOV_LNE_UN:
3979                 case OP_CMOV_LGE_UN:
3980                 case OP_CMOV_LGT_UN:
3981                 case OP_CMOV_LLE_UN:
3982                 case OP_CMOV_LLT_UN:
3983                         g_assert (ins->dreg == ins->sreg1);
3984                         /* This needs to operate on 64 bit values */
3985                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3986                         break;
3987
3988                 case OP_LNOT:
3989                         amd64_not_reg (code, ins->sreg1);
3990                         break;
3991                 case OP_LNEG:
3992                         amd64_neg_reg (code, ins->sreg1);
3993                         break;
3994
3995                 case OP_ICONST:
3996                 case OP_I8CONST:
3997                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3998                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3999                         else
4000                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4001                         break;
4002                 case OP_AOTCONST:
4003                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4004                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4005                         break;
4006                 case OP_JUMP_TABLE:
4007                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4008                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4009                         break;
4010                 case OP_MOVE:
4011                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4012                         break;
4013                 case OP_AMD64_SET_XMMREG_R4: {
4014                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4015                         break;
4016                 }
4017                 case OP_AMD64_SET_XMMREG_R8: {
4018                         if (ins->dreg != ins->sreg1)
4019                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4020                         break;
4021                 }
4022                 case OP_TAILCALL: {
4023                         /*
4024                          * Note: this 'frame destruction' logic is useful for tail calls, too.
4025                          * Keep in sync with the code in emit_epilog.
4026                          */
4027                         int pos = 0, i;
4028
4029                         /* FIXME: no tracing support... */
4030                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4031                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4032
4033                         g_assert (!cfg->method->save_lmf);
4034
4035                         if (cfg->arch.omit_fp) {
4036                                 guint32 save_offset = 0;
4037                                 /* Pop callee-saved registers */
4038                                 for (i = 0; i < AMD64_NREG; ++i)
4039                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4040                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4041                                                 save_offset += 8;
4042                                         }
4043                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4044                         }
4045                         else {
4046                                 for (i = 0; i < AMD64_NREG; ++i)
4047                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4048                                                 pos -= sizeof (gpointer);
4049
4050                                 if (pos)
4051                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4052
4053                                 /* Pop registers in reverse order */
4054                                 for (i = AMD64_NREG - 1; i > 0; --i)
4055                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4056                                                 amd64_pop_reg (code, i);
4057                                         }
4058
4059                                 amd64_leave (code);
4060                         }
4061
4062                         offset = code - cfg->native_code;
4063                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4064                         if (cfg->compile_aot)
4065                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4066                         else
4067                                 amd64_set_reg_template (code, AMD64_R11);
4068                         amd64_jump_reg (code, AMD64_R11);
4069                         break;
4070                 }
4071                 case OP_CHECK_THIS:
4072                         /* ensure ins->sreg1 is not NULL */
4073                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4074                         break;
4075                 case OP_ARGLIST: {
4076                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4077                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4078                         break;
4079                 }
4080                 case OP_CALL:
4081                 case OP_FCALL:
4082                 case OP_LCALL:
4083                 case OP_VCALL:
4084                 case OP_VCALL2:
4085                 case OP_VOIDCALL:
4086                         call = (MonoCallInst*)ins;
4087                         /*
4088                          * The AMD64 ABI forces callers to know about varargs.
4089                          */
4090                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4091                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4092                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4093                                 /*
4094                                  * Since the unmanaged calling convention doesn't contain a
4095                                  * 'vararg' entry, we have to treat every pinvoke call as a
4096                                  * potential vararg call.
4097                                  */
4098                                 guint32 nregs, i;
4099                                 nregs = 0;
4100                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4101                                         if (call->used_fregs & (1 << i))
4102                                                 nregs ++;
4103                                 if (!nregs)
4104                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4105                                 else
4106                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4107                         }
4108
4109                         if (ins->flags & MONO_INST_HAS_METHOD)
4110                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4111                         else
4112                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4113                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4114                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4115                         code = emit_move_return_value (cfg, ins, code);
4116                         break;
4117                 case OP_FCALL_REG:
4118                 case OP_LCALL_REG:
4119                 case OP_VCALL_REG:
4120                 case OP_VCALL2_REG:
4121                 case OP_VOIDCALL_REG:
4122                 case OP_CALL_REG:
4123                         call = (MonoCallInst*)ins;
4124
4125                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4126                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4127                                 ins->sreg1 = AMD64_R11;
4128                         }
4129
4130                         /*
4131                          * The AMD64 ABI forces callers to know about varargs.
4132                          */
4133                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4134                                 if (ins->sreg1 == AMD64_RAX) {
4135                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4136                                         ins->sreg1 = AMD64_R11;
4137                                 }
4138                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4139                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4140                                 /*
4141                                  * Since the unmanaged calling convention doesn't contain a
4142                                  * 'vararg' entry, we have to treat every pinvoke call as a
4143                                  * potential vararg call.
4144                                  */
4145                                 guint32 nregs, i;
4146                                 nregs = 0;
4147                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4148                                         if (call->used_fregs & (1 << i))
4149                                                 nregs ++;
4150                                 if (ins->sreg1 == AMD64_RAX) {
4151                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4152                                         ins->sreg1 = AMD64_R11;
4153                                 }
4154                                 if (!nregs)
4155                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4156                                 else
4157                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4158                         }
4159
4160                         amd64_call_reg (code, ins->sreg1);
4161                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4162                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4163                         code = emit_move_return_value (cfg, ins, code);
4164                         break;
4165                 case OP_FCALL_MEMBASE:
4166                 case OP_LCALL_MEMBASE:
4167                 case OP_VCALL_MEMBASE:
4168                 case OP_VCALL2_MEMBASE:
4169                 case OP_VOIDCALL_MEMBASE:
4170                 case OP_CALL_MEMBASE:
4171                         call = (MonoCallInst*)ins;
4172
4173                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4174                                 /*
4175                                  * Can't use R11 because it is clobbered by the trampoline
4176                                  * code, and the reg value is needed by get_vcall_slot_addr.
4177                                  */
4178                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4179                                 ins->sreg1 = AMD64_RAX;
4180                         }
4181
4182                         /*
4183                          * Emit a few nops to simplify get_vcall_slot ().
4184                          */
4185                         amd64_nop (code);
4186                         amd64_nop (code);
4187                         amd64_nop (code);
4188
4189                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4190                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4191                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4192                         code = emit_move_return_value (cfg, ins, code);
4193                         break;
4194                 case OP_DYN_CALL: {
4195                         int i;
4196                         MonoInst *var = cfg->dyn_call_var;
4197
4198                         g_assert (var->opcode == OP_REGOFFSET);
4199
4200                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4201                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4202                         /* r10 = ftn */
4203                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4204
4205                         /* Save args buffer */
4206                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4207
4208                         /* Set argument registers */
4209                         for (i = 0; i < PARAM_REGS; ++i)
4210                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4211
4212                         /* Make the call */
4213                         amd64_call_reg (code, AMD64_R10);
4214
4215                         /* Save result */
4216                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4217                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4218                         break;
4219                 }
4220                 case OP_AMD64_SAVE_SP_TO_LMF:
4221                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4222                         break;
4223                 case OP_X86_PUSH:
4224                         g_assert (!cfg->arch.no_pushes);
4225                         amd64_push_reg (code, ins->sreg1);
4226                         break;
4227                 case OP_X86_PUSH_IMM:
4228                         g_assert (!cfg->arch.no_pushes);
4229                         g_assert (amd64_is_imm32 (ins->inst_imm));
4230                         amd64_push_imm (code, ins->inst_imm);
4231                         break;
4232                 case OP_X86_PUSH_MEMBASE:
4233                         g_assert (!cfg->arch.no_pushes);
4234                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4235                         break;
4236                 case OP_X86_PUSH_OBJ: {
4237                         int size = ALIGN_TO (ins->inst_imm, 8);
4238
4239                         g_assert (!cfg->arch.no_pushes);
4240
4241                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4242                         amd64_push_reg (code, AMD64_RDI);
4243                         amd64_push_reg (code, AMD64_RSI);
4244                         amd64_push_reg (code, AMD64_RCX);
4245                         if (ins->inst_offset)
4246                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4247                         else
4248                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4249                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4250                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4251                         amd64_cld (code);
4252                         amd64_prefix (code, X86_REP_PREFIX);
4253                         amd64_movsd (code);
4254                         amd64_pop_reg (code, AMD64_RCX);
4255                         amd64_pop_reg (code, AMD64_RSI);
4256                         amd64_pop_reg (code, AMD64_RDI);
4257                         break;
4258                 }
4259                 case OP_X86_LEA:
4260                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4261                         break;
4262                 case OP_X86_LEA_MEMBASE:
4263                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4264                         break;
4265                 case OP_X86_XCHG:
4266                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4267                         break;
4268                 case OP_LOCALLOC:
4269                         /* keep alignment */
4270                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4271                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4272                         code = mono_emit_stack_alloc (cfg, code, ins);
4273                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4274                         if (cfg->param_area && cfg->arch.no_pushes)
4275                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4276                         break;
4277                 case OP_LOCALLOC_IMM: {
4278                         guint32 size = ins->inst_imm;
4279                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4280
4281                         if (ins->flags & MONO_INST_INIT) {
4282                                 if (size < 64) {
4283                                         int i;
4284
4285                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4286                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4287
4288                                         for (i = 0; i < size; i += 8)
4289                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4290                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4291                                 } else {
4292                                         amd64_mov_reg_imm (code, ins->dreg, size);
4293                                         ins->sreg1 = ins->dreg;
4294
4295                                         code = mono_emit_stack_alloc (cfg, code, ins);
4296                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4297                                 }
4298                         } else {
4299                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4300                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4301                         }
4302                         if (cfg->param_area && cfg->arch.no_pushes)
4303                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4304                         break;
4305                 }
4306                 case OP_THROW: {
4307                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4308                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4309                                              (gpointer)"mono_arch_throw_exception", FALSE);
4310                         break;
4311                 }
4312                 case OP_RETHROW: {
4313                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4314                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4315                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4316                         break;
4317                 }
4318                 case OP_CALL_HANDLER:
4319                         /* Align stack */
4320                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4321                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4322                         amd64_call_imm (code, 0);
4323                         /* Restore stack alignment */
4324                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4325                         break;
4326                 case OP_START_HANDLER: {
4327                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4328                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4329
4330                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4331                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4332                                 cfg->param_area && cfg->arch.no_pushes) {
4333                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4334                         }
4335                         break;
4336                 }
4337                 case OP_ENDFINALLY: {
4338                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4339                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4340                         amd64_ret (code);
4341                         break;
4342                 }
4343                 case OP_ENDFILTER: {
4344                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4345                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4346                         /* The local allocator will put the result into RAX */
4347                         amd64_ret (code);
4348                         break;
4349                 }
4350
4351                 case OP_LABEL:
4352                         ins->inst_c0 = code - cfg->native_code;
4353                         break;
4354                 case OP_BR:
4355                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4356                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4357                         //break;
4358                                 if (ins->inst_target_bb->native_offset) {
4359                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4360                                 } else {
4361                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4362                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4363                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4364                                                 x86_jump8 (code, 0);
4365                                         else
4366                                                 x86_jump32 (code, 0);
4367                         }
4368                         break;
4369                 case OP_BR_REG:
4370                         amd64_jump_reg (code, ins->sreg1);
4371                         break;
4372                 case OP_CEQ:
4373                 case OP_LCEQ:
4374                 case OP_ICEQ:
4375                 case OP_CLT:
4376                 case OP_LCLT:
4377                 case OP_ICLT:
4378                 case OP_CGT:
4379                 case OP_ICGT:
4380                 case OP_LCGT:
4381                 case OP_CLT_UN:
4382                 case OP_LCLT_UN:
4383                 case OP_ICLT_UN:
4384                 case OP_CGT_UN:
4385                 case OP_LCGT_UN:
4386                 case OP_ICGT_UN:
4387                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4388                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4389                         break;
4390                 case OP_COND_EXC_EQ:
4391                 case OP_COND_EXC_NE_UN:
4392                 case OP_COND_EXC_LT:
4393                 case OP_COND_EXC_LT_UN:
4394                 case OP_COND_EXC_GT:
4395                 case OP_COND_EXC_GT_UN:
4396                 case OP_COND_EXC_GE:
4397                 case OP_COND_EXC_GE_UN:
4398                 case OP_COND_EXC_LE:
4399                 case OP_COND_EXC_LE_UN:
4400                 case OP_COND_EXC_IEQ:
4401                 case OP_COND_EXC_INE_UN:
4402                 case OP_COND_EXC_ILT:
4403                 case OP_COND_EXC_ILT_UN:
4404                 case OP_COND_EXC_IGT:
4405                 case OP_COND_EXC_IGT_UN:
4406                 case OP_COND_EXC_IGE:
4407                 case OP_COND_EXC_IGE_UN:
4408                 case OP_COND_EXC_ILE:
4409                 case OP_COND_EXC_ILE_UN:
4410                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4411                         break;
4412                 case OP_COND_EXC_OV:
4413                 case OP_COND_EXC_NO:
4414                 case OP_COND_EXC_C:
4415                 case OP_COND_EXC_NC:
4416                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4417                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4418                         break;
4419                 case OP_COND_EXC_IOV:
4420                 case OP_COND_EXC_INO:
4421                 case OP_COND_EXC_IC:
4422                 case OP_COND_EXC_INC:
4423                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4424                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4425                         break;
4426
4427                 /* floating point opcodes */
4428                 case OP_R8CONST: {
4429                         double d = *(double *)ins->inst_p0;
4430
4431                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4432                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4433                         }
4434                         else {
4435                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4436                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4437                         }
4438                         break;
4439                 }
4440                 case OP_R4CONST: {
4441                         float f = *(float *)ins->inst_p0;
4442
4443                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4444                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4445                         }
4446                         else {
4447                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4448                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4449                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4450                         }
4451                         break;
4452                 }
4453                 case OP_STORER8_MEMBASE_REG:
4454                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4455                         break;
4456                 case OP_LOADR8_MEMBASE:
4457                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4458                         break;
4459                 case OP_STORER4_MEMBASE_REG:
4460                         /* This requires a double->single conversion */
4461                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4462                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4463                         break;
4464                 case OP_LOADR4_MEMBASE:
4465                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4466                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4467                         break;
4468                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4469                 case OP_ICONV_TO_R8:
4470                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4471                         break;
4472                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4473                 case OP_LCONV_TO_R8:
4474                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4475                         break;
4476                 case OP_FCONV_TO_R4:
4477                         /* FIXME: nothing to do ?? */
4478                         break;
4479                 case OP_FCONV_TO_I1:
4480                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4481                         break;
4482                 case OP_FCONV_TO_U1:
4483                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4484                         break;
4485                 case OP_FCONV_TO_I2:
4486                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4487                         break;
4488                 case OP_FCONV_TO_U2:
4489                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4490                         break;
4491                 case OP_FCONV_TO_U4:
4492                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4493                         break;
4494                 case OP_FCONV_TO_I4:
4495                 case OP_FCONV_TO_I:
4496                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4497                         break;
4498                 case OP_FCONV_TO_I8:
4499                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4500                         break;
4501                 case OP_LCONV_TO_R_UN: {
4502                         guint8 *br [2];
4503
4504                         /* Based on gcc code */
4505                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4506                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4507
4508                         /* Positive case */
4509                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4510                         br [1] = code; x86_jump8 (code, 0);
4511                         amd64_patch (br [0], code);
4512
4513                         /* Negative case */
4514                         /* Save to the red zone */
4515                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4516                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4517                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4518                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4519                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4520                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4521                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4522                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4523                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4524                         /* Restore */
4525                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4526                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4527                         amd64_patch (br [1], code);
4528                         break;
4529                 }
4530                 case OP_LCONV_TO_OVF_U4:
4531                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4532                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4533                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4534                         break;
4535                 case OP_LCONV_TO_OVF_I4_UN:
4536                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4537                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4538                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4539                         break;
4540                 case OP_FMOVE:
4541                         if (ins->dreg != ins->sreg1)
4542                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4543                         break;
4544                 case OP_FADD:
4545                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4546                         break;
4547                 case OP_FSUB:
4548                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4549                         break;
4550                 case OP_FMUL:
4551                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4552                         break;
4553                 case OP_FDIV:
4554                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4555                         break;
4556                 case OP_FNEG: {
4557                         static double r8_0 = -0.0;
4558
4559                         g_assert (ins->sreg1 == ins->dreg);
4560
4561                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4562                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4563                         break;
4564                 }
4565                 case OP_SIN:
4566                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4567                         break;
4568                 case OP_COS:
4569                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4570                         break;
4571                 case OP_ABS: {
4572                         static guint64 d = 0x7fffffffffffffffUL;
4573
4574                         g_assert (ins->sreg1 == ins->dreg);
4575
4576                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4577                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4578                         break;
4579                 }
4580                 case OP_SQRT:
4581                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4582                         break;
4583                 case OP_IMIN:
4584                         g_assert (cfg->opt & MONO_OPT_CMOV);
4585                         g_assert (ins->dreg == ins->sreg1);
4586                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4587                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4588                         break;
4589                 case OP_IMIN_UN:
4590                         g_assert (cfg->opt & MONO_OPT_CMOV);
4591                         g_assert (ins->dreg == ins->sreg1);
4592                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4593                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4594                         break;
4595                 case OP_IMAX:
4596                         g_assert (cfg->opt & MONO_OPT_CMOV);
4597                         g_assert (ins->dreg == ins->sreg1);
4598                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4599                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4600                         break;
4601                 case OP_IMAX_UN:
4602                         g_assert (cfg->opt & MONO_OPT_CMOV);
4603                         g_assert (ins->dreg == ins->sreg1);
4604                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4605                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4606                         break;
4607                 case OP_LMIN:
4608                         g_assert (cfg->opt & MONO_OPT_CMOV);
4609                         g_assert (ins->dreg == ins->sreg1);
4610                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4611                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4612                         break;
4613                 case OP_LMIN_UN:
4614                         g_assert (cfg->opt & MONO_OPT_CMOV);
4615                         g_assert (ins->dreg == ins->sreg1);
4616                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4617                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4618                         break;
4619                 case OP_LMAX:
4620                         g_assert (cfg->opt & MONO_OPT_CMOV);
4621                         g_assert (ins->dreg == ins->sreg1);
4622                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4623                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4624                         break;
4625                 case OP_LMAX_UN:
4626                         g_assert (cfg->opt & MONO_OPT_CMOV);
4627                         g_assert (ins->dreg == ins->sreg1);
4628                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4629                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4630                         break;
4631                 case OP_X86_FPOP:
4632                         break;
4633                 case OP_FCOMPARE:
4634                         /*
4635                          * The two arguments are swapped because the fbranch instructions
4636                          * depend on this for the non-sse case to work.
4637                          */
4638                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4639                         break;
4640                 case OP_FCEQ: {
4641                         /* zeroing the register at the start results in
4642                          * shorter and faster code (we can also remove the widening op)
4643                          */
4644                         guchar *unordered_check;
4645                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4646                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4647                         unordered_check = code;
4648                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4649                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4650                         amd64_patch (unordered_check, code);
4651                         break;
4652                 }
4653                 case OP_FCLT:
4654                 case OP_FCLT_UN:
4655                         /* zeroing the register at the start results in
4656                          * shorter and faster code (we can also remove the widening op)
4657                          */
4658                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4659                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4660                         if (ins->opcode == OP_FCLT_UN) {
4661                                 guchar *unordered_check = code;
4662                                 guchar *jump_to_end;
4663                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4664                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4665                                 jump_to_end = code;
4666                                 x86_jump8 (code, 0);
4667                                 amd64_patch (unordered_check, code);
4668                                 amd64_inc_reg (code, ins->dreg);
4669                                 amd64_patch (jump_to_end, code);
4670                         } else {
4671                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4672                         }
4673                         break;
4674                 case OP_FCGT:
4675                 case OP_FCGT_UN: {
4676                         /* zeroing the register at the start results in
4677                          * shorter and faster code (we can also remove the widening op)
4678                          */
4679                         guchar *unordered_check;
4680                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4681                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4682                         if (ins->opcode == OP_FCGT) {
4683                                 unordered_check = code;
4684                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4685                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4686                                 amd64_patch (unordered_check, code);
4687                         } else {
4688                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4689                         }
4690                         break;
4691                 }
4692                 case OP_FCLT_MEMBASE:
4693                 case OP_FCGT_MEMBASE:
4694                 case OP_FCLT_UN_MEMBASE:
4695                 case OP_FCGT_UN_MEMBASE:
4696                 case OP_FCEQ_MEMBASE: {
4697                         guchar *unordered_check, *jump_to_end;
4698                         int x86_cond;
4699
4700                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4701                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4702
4703                         switch (ins->opcode) {
4704                         case OP_FCEQ_MEMBASE:
4705                                 x86_cond = X86_CC_EQ;
4706                                 break;
4707                         case OP_FCLT_MEMBASE:
4708                         case OP_FCLT_UN_MEMBASE:
4709                                 x86_cond = X86_CC_LT;
4710                                 break;
4711                         case OP_FCGT_MEMBASE:
4712                         case OP_FCGT_UN_MEMBASE:
4713                                 x86_cond = X86_CC_GT;
4714                                 break;
4715                         default:
4716                                 g_assert_not_reached ();
4717                         }
4718
4719                         unordered_check = code;
4720                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4721                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4722
4723                         switch (ins->opcode) {
4724                         case OP_FCEQ_MEMBASE:
4725                         case OP_FCLT_MEMBASE:
4726                         case OP_FCGT_MEMBASE:
4727                                 amd64_patch (unordered_check, code);
4728                                 break;
4729                         case OP_FCLT_UN_MEMBASE:
4730                         case OP_FCGT_UN_MEMBASE:
4731                                 jump_to_end = code;
4732                                 x86_jump8 (code, 0);
4733                                 amd64_patch (unordered_check, code);
4734                                 amd64_inc_reg (code, ins->dreg);
4735                                 amd64_patch (jump_to_end, code);
4736                                 break;
4737                         default:
4738                                 break;
4739                         }
4740                         break;
4741                 }
4742                 case OP_FBEQ: {
4743                         guchar *jump = code;
4744                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4745                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4746                         amd64_patch (jump, code);
4747                         break;
4748                 }
4749                 case OP_FBNE_UN:
4750                         /* Branch if C013 != 100 */
4751                         /* branch if !ZF or (PF|CF) */
4752                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4753                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4754                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4755                         break;
4756                 case OP_FBLT:
4757                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4758                         break;
4759                 case OP_FBLT_UN:
4760                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4761                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4762                         break;
4763                 case OP_FBGT:
4764                 case OP_FBGT_UN:
4765                         if (ins->opcode == OP_FBGT) {
4766                                 guchar *br1;
4767
4768                                 /* skip branch if C1=1 */
4769                                 br1 = code;
4770                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4771                                 /* branch if (C0 | C3) = 1 */
4772                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4773                                 amd64_patch (br1, code);
4774                                 break;
4775                         } else {
4776                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4777                         }
4778                         break;
4779                 case OP_FBGE: {
4780                         /* Branch if C013 == 100 or 001 */
4781                         guchar *br1;
4782
4783                         /* skip branch if C1=1 */
4784                         br1 = code;
4785                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4786                         /* branch if (C0 | C3) = 1 */
4787                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4788                         amd64_patch (br1, code);
4789                         break;
4790                 }
4791                 case OP_FBGE_UN:
4792                         /* Branch if C013 == 000 */
4793                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4794                         break;
4795                 case OP_FBLE: {
4796                         /* Branch if C013=000 or 100 */
4797                         guchar *br1;
4798
4799                         /* skip branch if C1=1 */
4800                         br1 = code;
4801                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4802                         /* branch if C0=0 */
4803                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4804                         amd64_patch (br1, code);
4805                         break;
4806                 }
4807                 case OP_FBLE_UN:
4808                         /* Branch if C013 != 001 */
4809                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4810                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4811                         break;
4812                 case OP_CKFINITE:
4813                         /* Transfer value to the fp stack */
4814                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4815                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4816                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4817
4818                         amd64_push_reg (code, AMD64_RAX);
4819                         amd64_fxam (code);
4820                         amd64_fnstsw (code);
4821                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4822                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4823                         amd64_pop_reg (code, AMD64_RAX);
4824                         amd64_fstp (code, 0);
4825                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4826                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4827                         break;
4828                 case OP_TLS_GET: {
4829                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4830                         break;
4831                 }
4832                 case OP_MEMORY_BARRIER: {
4833                         /* Not needed on amd64 */
4834                         break;
4835                 }
4836                 case OP_ATOMIC_ADD_I4:
4837                 case OP_ATOMIC_ADD_I8: {
4838                         int dreg = ins->dreg;
4839                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4840
4841                         if (dreg == ins->inst_basereg)
4842                                 dreg = AMD64_R11;
4843
4844                         if (dreg != ins->sreg2)
4845                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4846
4847                         x86_prefix (code, X86_LOCK_PREFIX);
4848                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4849
4850                         if (dreg != ins->dreg)
4851                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4852
4853                         break;
4854                 }
4855                 case OP_ATOMIC_ADD_NEW_I4:
4856                 case OP_ATOMIC_ADD_NEW_I8: {
4857                         int dreg = ins->dreg;
4858                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4859
4860                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4861                                 dreg = AMD64_R11;
4862
4863                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4864                         amd64_prefix (code, X86_LOCK_PREFIX);
4865                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4866                         /* dreg contains the old value, add with sreg2 value */
4867                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4868
4869                         if (ins->dreg != dreg)
4870                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4871
4872                         break;
4873                 }
4874                 case OP_ATOMIC_EXCHANGE_I4:
4875                 case OP_ATOMIC_EXCHANGE_I8: {
4876                         guchar *br[2];
4877                         int sreg2 = ins->sreg2;
4878                         int breg = ins->inst_basereg;
4879                         guint32 size;
4880                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4881
4882                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4883                                 size = 8;
4884                         else
4885                                 size = 4;
4886
4887                         /*
4888                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4889                          * an explanation of how this works.
4890                          */
4891
4892                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4893                          * hack to overcome limits in x86 reg allocator
4894                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4895                          */
4896                         g_assert (ins->dreg == AMD64_RAX);
4897
4898                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4899                                 /* Highly unlikely, but possible */
4900                                 need_push = TRUE;
4901
4902                         /* The pushes invalidate rsp */
4903                         if ((breg == AMD64_RAX) || need_push) {
4904                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4905                                 breg = AMD64_R11;
4906                         }
4907
4908                         /* We need the EAX reg for the comparand */
4909                         if (ins->sreg2 == AMD64_RAX) {
4910                                 if (breg != AMD64_R11) {
4911                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4912                                         sreg2 = AMD64_R11;
4913                                 } else {
4914                                         g_assert (need_push);
4915                                         amd64_push_reg (code, AMD64_RDX);
4916                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4917                                         sreg2 = AMD64_RDX;
4918                                         rdx_pushed = TRUE;
4919                                 }
4920                         }
4921
4922                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4923
4924                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4925                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4926                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4927                         amd64_patch (br [1], br [0]);
4928
4929                         if (rdx_pushed)
4930                                 amd64_pop_reg (code, AMD64_RDX);
4931
4932                         break;
4933                 }
4934                 case OP_ATOMIC_CAS_I4:
4935                 case OP_ATOMIC_CAS_I8: {
4936                         guint32 size;
4937
4938                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4939                                 size = 8;
4940                         else
4941                                 size = 4;
4942
4943                         /*
4944                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4945                          * an explanation of how this works.
4946                          */
4947                         g_assert (ins->sreg3 == AMD64_RAX);
4948                         g_assert (ins->sreg1 != AMD64_RAX);
4949                         g_assert (ins->sreg1 != ins->sreg2);
4950
4951                         amd64_prefix (code, X86_LOCK_PREFIX);
4952                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4953
4954                         if (ins->dreg != AMD64_RAX)
4955                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4956                         break;
4957                 }
4958 #ifdef MONO_ARCH_SIMD_INTRINSICS
4959                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4960                 case OP_ADDPS:
4961                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4962                         break;
4963                 case OP_DIVPS:
4964                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4965                         break;
4966                 case OP_MULPS:
4967                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4968                         break;
4969                 case OP_SUBPS:
4970                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4971                         break;
4972                 case OP_MAXPS:
4973                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4974                         break;
4975                 case OP_MINPS:
4976                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4977                         break;
4978                 case OP_COMPPS:
4979                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4980                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4981                         break;
4982                 case OP_ANDPS:
4983                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4984                         break;
4985                 case OP_ANDNPS:
4986                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4987                         break;
4988                 case OP_ORPS:
4989                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4990                         break;
4991                 case OP_XORPS:
4992                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4993                         break;
4994                 case OP_SQRTPS:
4995                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4996                         break;
4997                 case OP_RSQRTPS:
4998                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4999                         break;
5000                 case OP_RCPPS:
5001                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5002                         break;
5003                 case OP_ADDSUBPS:
5004                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5005                         break;
5006                 case OP_HADDPS:
5007                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5008                         break;
5009                 case OP_HSUBPS:
5010                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5011                         break;
5012                 case OP_DUPPS_HIGH:
5013                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5014                         break;
5015                 case OP_DUPPS_LOW:
5016                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5017                         break;
5018
5019                 case OP_PSHUFLEW_HIGH:
5020                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5021                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5022                         break;
5023                 case OP_PSHUFLEW_LOW:
5024                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5025                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5026                         break;
5027                 case OP_PSHUFLED:
5028                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5029                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5030                         break;
5031
5032                 case OP_ADDPD:
5033                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5034                         break;
5035                 case OP_DIVPD:
5036                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5037                         break;
5038                 case OP_MULPD:
5039                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5040                         break;
5041                 case OP_SUBPD:
5042                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5043                         break;
5044                 case OP_MAXPD:
5045                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5046                         break;
5047                 case OP_MINPD:
5048                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5049                         break;
5050                 case OP_COMPPD:
5051                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5052                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5053                         break;
5054                 case OP_ANDPD:
5055                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5056                         break;
5057                 case OP_ANDNPD:
5058                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5059                         break;
5060                 case OP_ORPD:
5061                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5062                         break;
5063                 case OP_XORPD:
5064                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5065                         break;
5066                 case OP_SQRTPD:
5067                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5068                         break;
5069                 case OP_ADDSUBPD:
5070                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_HADDPD:
5073                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5074                         break;
5075                 case OP_HSUBPD:
5076                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078                 case OP_DUPPD:
5079                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5080                         break;
5081
5082                 case OP_EXTRACT_MASK:
5083                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5084                         break;
5085
5086                 case OP_PAND:
5087                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5088                         break;
5089                 case OP_POR:
5090                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5091                         break;
5092                 case OP_PXOR:
5093                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095
5096                 case OP_PADDB:
5097                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5098                         break;
5099                 case OP_PADDW:
5100                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5101                         break;
5102                 case OP_PADDD:
5103                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5104                         break;
5105                 case OP_PADDQ:
5106                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5107                         break;
5108
5109                 case OP_PSUBB:
5110                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5111                         break;
5112                 case OP_PSUBW:
5113                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5114                         break;
5115                 case OP_PSUBD:
5116                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5117                         break;
5118                 case OP_PSUBQ:
5119                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5120                         break;
5121
5122                 case OP_PMAXB_UN:
5123                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5124                         break;
5125                 case OP_PMAXW_UN:
5126                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5127                         break;
5128                 case OP_PMAXD_UN:
5129                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5130                         break;
5131
5132                 case OP_PMAXB:
5133                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5134                         break;
5135                 case OP_PMAXW:
5136                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5137                         break;
5138                 case OP_PMAXD:
5139                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5140                         break;
5141
5142                 case OP_PAVGB_UN:
5143                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5144                         break;
5145                 case OP_PAVGW_UN:
5146                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5147                         break;
5148
5149                 case OP_PMINB_UN:
5150                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5151                         break;
5152                 case OP_PMINW_UN:
5153                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5154                         break;
5155                 case OP_PMIND_UN:
5156                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5157                         break;
5158
5159                 case OP_PMINB:
5160                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5161                         break;
5162                 case OP_PMINW:
5163                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5164                         break;
5165                 case OP_PMIND:
5166                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5167                         break;
5168
5169                 case OP_PCMPEQB:
5170                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5171                         break;
5172                 case OP_PCMPEQW:
5173                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5174                         break;
5175                 case OP_PCMPEQD:
5176                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5177                         break;
5178                 case OP_PCMPEQQ:
5179                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5180                         break;
5181
5182                 case OP_PCMPGTB:
5183                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185                 case OP_PCMPGTW:
5186                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5187                         break;
5188                 case OP_PCMPGTD:
5189                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5190                         break;
5191                 case OP_PCMPGTQ:
5192                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5193                         break;
5194
5195                 case OP_PSUM_ABS_DIFF:
5196                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5197                         break;
5198
5199                 case OP_UNPACK_LOWB:
5200                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5201                         break;
5202                 case OP_UNPACK_LOWW:
5203                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5204                         break;
5205                 case OP_UNPACK_LOWD:
5206                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_UNPACK_LOWQ:
5209                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_UNPACK_LOWPS:
5212                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214                 case OP_UNPACK_LOWPD:
5215                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5216                         break;
5217
5218                 case OP_UNPACK_HIGHB:
5219                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5220                         break;
5221                 case OP_UNPACK_HIGHW:
5222                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5223                         break;
5224                 case OP_UNPACK_HIGHD:
5225                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227                 case OP_UNPACK_HIGHQ:
5228                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5229                         break;
5230                 case OP_UNPACK_HIGHPS:
5231                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5232                         break;
5233                 case OP_UNPACK_HIGHPD:
5234                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5235                         break;
5236
5237                 case OP_PACKW:
5238                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5239                         break;
5240                 case OP_PACKD:
5241                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5242                         break;
5243                 case OP_PACKW_UN:
5244                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5245                         break;
5246                 case OP_PACKD_UN:
5247                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5248                         break;
5249
5250                 case OP_PADDB_SAT_UN:
5251                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5252                         break;
5253                 case OP_PSUBB_SAT_UN:
5254                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5255                         break;
5256                 case OP_PADDW_SAT_UN:
5257                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5258                         break;
5259                 case OP_PSUBW_SAT_UN:
5260                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5261                         break;
5262
5263                 case OP_PADDB_SAT:
5264                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5265                         break;
5266                 case OP_PSUBB_SAT:
5267                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5268                         break;
5269                 case OP_PADDW_SAT:
5270                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5271                         break;
5272                 case OP_PSUBW_SAT:
5273                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5274                         break;
5275
5276                 case OP_PMULW:
5277                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5278                         break;
5279                 case OP_PMULD:
5280                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5281                         break;
5282                 case OP_PMULQ:
5283                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5284                         break;
5285                 case OP_PMULW_HIGH_UN:
5286                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5287                         break;
5288                 case OP_PMULW_HIGH:
5289                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5290                         break;
5291
5292                 case OP_PSHRW:
5293                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5294                         break;
5295                 case OP_PSHRW_REG:
5296                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5297                         break;
5298
5299                 case OP_PSARW:
5300                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5301                         break;
5302                 case OP_PSARW_REG:
5303                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5304                         break;
5305
5306                 case OP_PSHLW:
5307                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5308                         break;
5309                 case OP_PSHLW_REG:
5310                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5311                         break;
5312
5313                 case OP_PSHRD:
5314                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5315                         break;
5316                 case OP_PSHRD_REG:
5317                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5318                         break;
5319
5320                 case OP_PSARD:
5321                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5322                         break;
5323                 case OP_PSARD_REG:
5324                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5325                         break;
5326
5327                 case OP_PSHLD:
5328                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5329                         break;
5330                 case OP_PSHLD_REG:
5331                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5332                         break;
5333
5334                 case OP_PSHRQ:
5335                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5336                         break;
5337                 case OP_PSHRQ_REG:
5338                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5339                         break;
5340
5341                 /*TODO: This is appart of the sse spec but not added
5342                 case OP_PSARQ:
5343                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5344                         break;
5345                 case OP_PSARQ_REG:
5346                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5347                         break;
5348                 */
5349
5350                 case OP_PSHLQ:
5351                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5352                         break;
5353                 case OP_PSHLQ_REG:
5354                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5355                         break;
5356
5357                 case OP_ICONV_TO_X:
5358                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5359                         break;
5360                 case OP_EXTRACT_I4:
5361                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5362                         break;
5363                 case OP_EXTRACT_I8:
5364                         if (ins->inst_c0) {
5365                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5366                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5367                         } else {
5368                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5369                         }
5370                         break;
5371                 case OP_EXTRACT_I1:
5372                 case OP_EXTRACT_U1:
5373                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5374                         if (ins->inst_c0)
5375                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5376                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5377                         break;
5378                 case OP_EXTRACT_I2:
5379                 case OP_EXTRACT_U2:
5380                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5381                         if (ins->inst_c0)
5382                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5383                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5384                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5385                         break;
5386                 case OP_EXTRACT_R8:
5387                         if (ins->inst_c0)
5388                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5389                         else
5390                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5391                         break;
5392                 case OP_INSERT_I2:
5393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5394                         break;
5395                 case OP_EXTRACTX_U2:
5396                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5397                         break;
5398                 case OP_INSERTX_U1_SLOW:
5399                         /*sreg1 is the extracted ireg (scratch)
5400                         /sreg2 is the to be inserted ireg (scratch)
5401                         /dreg is the xreg to receive the value*/
5402
5403                         /*clear the bits from the extracted word*/
5404                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5405                         /*shift the value to insert if needed*/
5406                         if (ins->inst_c0 & 1)
5407                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5408                         /*join them together*/
5409                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5410                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5411                         break;
5412                 case OP_INSERTX_I4_SLOW:
5413                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5414                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5415                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5416                         break;
5417                 case OP_INSERTX_I8_SLOW:
5418                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5419                         if (ins->inst_c0)
5420                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5421                         else
5422                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5423                         break;
5424
5425                 case OP_INSERTX_R4_SLOW:
5426                         switch (ins->inst_c0) {
5427                         case 0:
5428                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5429                                 break;
5430                         case 1:
5431                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5432                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5433                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5434                                 break;
5435                         case 2:
5436                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5437                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5438                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5439                                 break;
5440                         case 3:
5441                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5442                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5443                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5444                                 break;
5445                         }
5446                         break;
5447                 case OP_INSERTX_R8_SLOW:
5448                         if (ins->inst_c0)
5449                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5450                         else
5451                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5452                         break;
5453                 case OP_STOREX_MEMBASE_REG:
5454                 case OP_STOREX_MEMBASE:
5455                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5456                         break;
5457                 case OP_LOADX_MEMBASE:
5458                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5459                         break;
5460                 case OP_LOADX_ALIGNED_MEMBASE:
5461                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5462                         break;
5463                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5464                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5465                         break;
5466                 case OP_STOREX_NTA_MEMBASE_REG:
5467                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5468                         break;
5469                 case OP_PREFETCH_MEMBASE:
5470                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5471                         break;
5472
5473                 case OP_XMOVE:
5474                         /*FIXME the peephole pass should have killed this*/
5475                         if (ins->dreg != ins->sreg1)
5476                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5477                         break;
5478                 case OP_XZERO:
5479                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5480                         break;
5481                 case OP_ICONV_TO_R8_RAW:
5482                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5483                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5484                         break;
5485
5486                 case OP_FCONV_TO_R8_X:
5487                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5488                         break;
5489
5490                 case OP_XCONV_R8_TO_I4:
5491                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5492                         switch (ins->backend.source_opcode) {
5493                         case OP_FCONV_TO_I1:
5494                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5495                                 break;
5496                         case OP_FCONV_TO_U1:
5497                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5498                                 break;
5499                         case OP_FCONV_TO_I2:
5500                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5501                                 break;
5502                         case OP_FCONV_TO_U2:
5503                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5504                                 break;
5505                         }
5506                         break;
5507
5508                 case OP_EXPAND_I2:
5509                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5510                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5511                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5512                         break;
5513                 case OP_EXPAND_I4:
5514                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5515                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5516                         break;
5517                 case OP_EXPAND_I8:
5518                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5519                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5520                         break;
5521                 case OP_EXPAND_R4:
5522                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5523                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5524                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5525                         break;
5526                 case OP_EXPAND_R8:
5527                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5528                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5529                         break;
5530 #endif
5531                 case OP_LIVERANGE_START: {
5532                         if (cfg->verbose_level > 1)
5533                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5534                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5535                         break;
5536                 }
5537                 case OP_LIVERANGE_END: {
5538                         if (cfg->verbose_level > 1)
5539                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5540                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5541                         break;
5542                 }
5543                 default:
5544                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5545                         g_assert_not_reached ();
5546                 }
5547
5548                 if ((code - cfg->native_code - offset) > max_len) {
5549                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5550                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5551                         g_assert_not_reached ();
5552                 }
5553
5554                 last_ins = ins;
5555                 last_offset = offset;
5556         }
5557
5558         cfg->code_len = code - cfg->native_code;
5559 }
5560
5561 #endif /* DISABLE_JIT */
5562
5563 void
5564 mono_arch_register_lowlevel_calls (void)
5565 {
5566         /* The signature doesn't matter */
5567         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5568 }
5569
5570 void
5571 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5572 {
5573         MonoJumpInfo *patch_info;
5574         gboolean compile_aot = !run_cctors;
5575
5576         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5577                 unsigned char *ip = patch_info->ip.i + code;
5578                 unsigned char *target;
5579
5580                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5581
5582                 if (compile_aot) {
5583                         switch (patch_info->type) {
5584                         case MONO_PATCH_INFO_BB:
5585                         case MONO_PATCH_INFO_LABEL:
5586                                 break;
5587                         default:
5588                                 /* No need to patch these */
5589                                 continue;
5590                         }
5591                 }
5592
5593                 switch (patch_info->type) {
5594                 case MONO_PATCH_INFO_NONE:
5595                         continue;
5596                 case MONO_PATCH_INFO_METHOD_REL:
5597                 case MONO_PATCH_INFO_R8:
5598                 case MONO_PATCH_INFO_R4:
5599                         g_assert_not_reached ();
5600                         continue;
5601                 case MONO_PATCH_INFO_BB:
5602                         break;
5603                 default:
5604                         break;
5605                 }
5606
5607                 /*
5608                  * Debug code to help track down problems where the target of a near call is
5609                  * is not valid.
5610                  */
5611                 if (amd64_is_near_call (ip)) {
5612                         gint64 disp = (guint8*)target - (guint8*)ip;
5613
5614                         if (!amd64_is_imm32 (disp)) {
5615                                 printf ("TYPE: %d\n", patch_info->type);
5616                                 switch (patch_info->type) {
5617                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5618                                         printf ("V: %s\n", patch_info->data.name);
5619                                         break;
5620                                 case MONO_PATCH_INFO_METHOD_JUMP:
5621                                 case MONO_PATCH_INFO_METHOD:
5622                                         printf ("V: %s\n", patch_info->data.method->name);
5623                                         break;
5624                                 default:
5625                                         break;
5626                                 }
5627                         }
5628                 }
5629
5630                 amd64_patch (ip, (gpointer)target);
5631         }
5632 }
5633
5634 #ifndef DISABLE_JIT
5635
5636 static int
5637 get_max_epilog_size (MonoCompile *cfg)
5638 {
5639         int max_epilog_size = 16;
5640
5641         if (cfg->method->save_lmf)
5642                 max_epilog_size += 256;
5643
5644         if (mono_jit_trace_calls != NULL)
5645                 max_epilog_size += 50;
5646
5647         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5648                 max_epilog_size += 50;
5649
5650         max_epilog_size += (AMD64_NREG * 2);
5651
5652         return max_epilog_size;
5653 }
5654
5655 /*
5656  * This macro is used for testing whenever the unwinder works correctly at every point
5657  * where an async exception can happen.
5658  */
5659 /* This will generate a SIGSEGV at the given point in the code */
5660 #define async_exc_point(code) do { \
5661     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5662          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5663              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5664          cfg->arch.async_point_count ++; \
5665     } \
5666 } while (0)
5667
5668 guint8 *
5669 mono_arch_emit_prolog (MonoCompile *cfg)
5670 {
5671         MonoMethod *method = cfg->method;
5672         MonoBasicBlock *bb;
5673         MonoMethodSignature *sig;
5674         MonoInst *ins;
5675         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5676         guint8 *code;
5677         CallInfo *cinfo;
5678         gint32 lmf_offset = cfg->arch.lmf_offset;
5679         gboolean args_clobbered = FALSE;
5680         gboolean trace = FALSE;
5681
5682         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5683
5684         code = cfg->native_code = g_malloc (cfg->code_size);
5685
5686         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5687                 trace = TRUE;
5688
5689         /* Amount of stack space allocated by register saving code */
5690         pos = 0;
5691
5692         /* Offset between RSP and the CFA */
5693         cfa_offset = 0;
5694
5695         /*
5696          * The prolog consists of the following parts:
5697          * FP present:
5698          * - push rbp, mov rbp, rsp
5699          * - save callee saved regs using pushes
5700          * - allocate frame
5701          * - save rgctx if needed
5702          * - save lmf if needed
5703          * FP not present:
5704          * - allocate frame
5705          * - save rgctx if needed
5706          * - save lmf if needed
5707          * - save callee saved regs using moves
5708          */
5709
5710         // CFA = sp + 8
5711         cfa_offset = 8;
5712         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5713         // IP saved at CFA - 8
5714         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5715         async_exc_point (code);
5716
5717         if (!cfg->arch.omit_fp) {
5718                 amd64_push_reg (code, AMD64_RBP);
5719                 cfa_offset += 8;
5720                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5721                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5722                 async_exc_point (code);
5723 #ifdef HOST_WIN32
5724                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5725 #endif
5726
5727                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5728                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5729                 async_exc_point (code);
5730 #ifdef HOST_WIN32
5731                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5732 #endif
5733         }
5734
5735         /* Save callee saved registers */
5736         if (!cfg->arch.omit_fp && !method->save_lmf) {
5737                 int offset = cfa_offset;
5738
5739                 for (i = 0; i < AMD64_NREG; ++i)
5740                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5741                                 amd64_push_reg (code, i);
5742                                 pos += sizeof (gpointer);
5743                                 offset += 8;
5744                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5745                                 async_exc_point (code);
5746                         }
5747         }
5748
5749         /* The param area is always at offset 0 from sp */
5750         /* This needs to be allocated here, since it has to come after the spill area */
5751         if (cfg->arch.no_pushes && cfg->param_area) {
5752                 if (cfg->arch.omit_fp)
5753                         // FIXME:
5754                         g_assert_not_reached ();
5755                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5756         }
5757
5758         if (cfg->arch.omit_fp) {
5759                 /*
5760                  * On enter, the stack is misaligned by the the pushing of the return
5761                  * address. It is either made aligned by the pushing of %rbp, or by
5762                  * this.
5763                  */
5764                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5765                 if ((alloc_size % 16) == 0)
5766                         alloc_size += 8;
5767         } else {
5768                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5769
5770                 alloc_size -= pos;
5771         }
5772
5773         cfg->arch.stack_alloc_size = alloc_size;
5774
5775         /* Allocate stack frame */
5776         if (alloc_size) {
5777                 /* See mono_emit_stack_alloc */
5778 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5779                 guint32 remaining_size = alloc_size;
5780                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5781                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5782                 guint32 offset = code - cfg->native_code;
5783                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5784                         while (required_code_size >= (cfg->code_size - offset))
5785                                 cfg->code_size *= 2;
5786                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5787                         code = cfg->native_code + offset;
5788                         mono_jit_stats.code_reallocs++;
5789                 }
5790
5791                 while (remaining_size >= 0x1000) {
5792                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5793                         if (cfg->arch.omit_fp) {
5794                                 cfa_offset += 0x1000;
5795                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5796                         }
5797                         async_exc_point (code);
5798 #ifdef HOST_WIN32
5799                         if (cfg->arch.omit_fp)
5800                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5801 #endif
5802
5803                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5804                         remaining_size -= 0x1000;
5805                 }
5806                 if (remaining_size) {
5807                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5808                         if (cfg->arch.omit_fp) {
5809                                 cfa_offset += remaining_size;
5810                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5811                                 async_exc_point (code);
5812                         }
5813 #ifdef HOST_WIN32
5814                         if (cfg->arch.omit_fp)
5815                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5816 #endif
5817                 }
5818 #else
5819                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5820                 if (cfg->arch.omit_fp) {
5821                         cfa_offset += alloc_size;
5822                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5823                         async_exc_point (code);
5824                 }
5825 #endif
5826         }
5827
5828         /* Stack alignment check */
5829 #if 0
5830         {
5831                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5832                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5833                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5834                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5835                 amd64_breakpoint (code);
5836         }
5837 #endif
5838
5839 #ifndef TARGET_WIN32
5840         if (mini_get_debug_options ()->init_stacks) {
5841                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5842
5843                 /* Save registers to the red zone */
5844                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5845                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5846
5847                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5848                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5849                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5850
5851                 amd64_cld (code);
5852                 amd64_prefix (code, X86_REP_PREFIX);
5853                 amd64_stosl (code);
5854
5855                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5856                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5857         }
5858 #endif
5859
5860         /* Save LMF */
5861         if (method->save_lmf) {
5862                 /*
5863                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5864                  */
5865                 /*
5866                  * sp is saved right before calls but we need to save it here too so
5867                  * async stack walks would work.
5868                  */
5869                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5870                 /* Skip method (only needed for trampoline LMF frames) */
5871                 /* Save callee saved regs */
5872                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5873                         int offset;
5874
5875                         switch (i) {
5876                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5877                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5878                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5879                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5880                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5881                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5882 #ifdef HOST_WIN32
5883                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5884                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5885 #endif
5886                         default:
5887                                 offset = -1;
5888                                 break;
5889                         }
5890
5891                         if (offset != -1) {
5892                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5893                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5894                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5895                         }
5896                 }
5897         }
5898
5899         /* Save callee saved registers */
5900         if (cfg->arch.omit_fp && !method->save_lmf) {
5901                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5902
5903                 /* Save caller saved registers after sp is adjusted */
5904                 /* The registers are saved at the bottom of the frame */
5905                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5906                 for (i = 0; i < AMD64_NREG; ++i)
5907                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5908                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5909                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5910                                 save_area_offset += 8;
5911                                 async_exc_point (code);
5912                         }
5913         }
5914
5915         /* store runtime generic context */
5916         if (cfg->rgctx_var) {
5917                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5918                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5919
5920                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5921         }
5922
5923         /* compute max_length in order to use short forward jumps */
5924         max_epilog_size = get_max_epilog_size (cfg);
5925         if (cfg->opt & MONO_OPT_BRANCH) {
5926                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5927                         MonoInst *ins;
5928                         int max_length = 0;
5929
5930                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5931                                 max_length += 6;
5932                         /* max alignment for loops */
5933                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5934                                 max_length += LOOP_ALIGNMENT;
5935
5936                         MONO_BB_FOR_EACH_INS (bb, ins) {
5937                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5938                         }
5939
5940                         /* Take prolog and epilog instrumentation into account */
5941                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5942                                 max_length += max_epilog_size;
5943
5944                         bb->max_length = max_length;
5945                 }
5946         }
5947
5948         sig = mono_method_signature (method);
5949         pos = 0;
5950
5951         cinfo = cfg->arch.cinfo;
5952
5953         if (sig->ret->type != MONO_TYPE_VOID) {
5954                 /* Save volatile arguments to the stack */
5955                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5956                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5957         }
5958
5959         /* Keep this in sync with emit_load_volatile_arguments */
5960         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5961                 ArgInfo *ainfo = cinfo->args + i;
5962                 gint32 stack_offset;
5963                 MonoType *arg_type;
5964
5965                 ins = cfg->args [i];
5966
5967                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5968                         /* Unused arguments */
5969                         continue;
5970
5971                 if (sig->hasthis && (i == 0))
5972                         arg_type = &mono_defaults.object_class->byval_arg;
5973                 else
5974                         arg_type = sig->params [i - sig->hasthis];
5975
5976                 stack_offset = ainfo->offset + ARGS_OFFSET;
5977
5978                 if (cfg->globalra) {
5979                         /* All the other moves are done by the register allocator */
5980                         switch (ainfo->storage) {
5981                         case ArgInFloatSSEReg:
5982                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5983                                 break;
5984                         case ArgValuetypeInReg:
5985                                 for (quad = 0; quad < 2; quad ++) {
5986                                         switch (ainfo->pair_storage [quad]) {
5987                                         case ArgInIReg:
5988                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5989                                                 break;
5990                                         case ArgInFloatSSEReg:
5991                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5992                                                 break;
5993                                         case ArgInDoubleSSEReg:
5994                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5995                                                 break;
5996                                         case ArgNone:
5997                                                 break;
5998                                         default:
5999                                                 g_assert_not_reached ();
6000                                         }
6001                                 }
6002                                 break;
6003                         default:
6004                                 break;
6005                         }
6006
6007                         continue;
6008                 }
6009
6010                 /* Save volatile arguments to the stack */
6011                 if (ins->opcode != OP_REGVAR) {
6012                         switch (ainfo->storage) {
6013                         case ArgInIReg: {
6014                                 guint32 size = 8;
6015
6016                                 /* FIXME: I1 etc */
6017                                 /*
6018                                 if (stack_offset & 0x1)
6019                                         size = 1;
6020                                 else if (stack_offset & 0x2)
6021                                         size = 2;
6022                                 else if (stack_offset & 0x4)
6023                                         size = 4;
6024                                 else
6025                                         size = 8;
6026                                 */
6027                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6028                                 break;
6029                         }
6030                         case ArgInFloatSSEReg:
6031                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6032                                 break;
6033                         case ArgInDoubleSSEReg:
6034                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6035                                 break;
6036                         case ArgValuetypeInReg:
6037                                 for (quad = 0; quad < 2; quad ++) {
6038                                         switch (ainfo->pair_storage [quad]) {
6039                                         case ArgInIReg:
6040                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6041                                                 break;
6042                                         case ArgInFloatSSEReg:
6043                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6044                                                 break;
6045                                         case ArgInDoubleSSEReg:
6046                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6047                                                 break;
6048                                         case ArgNone:
6049                                                 break;
6050                                         default:
6051                                                 g_assert_not_reached ();
6052                                         }
6053                                 }
6054                                 break;
6055                         case ArgValuetypeAddrInIReg:
6056                                 if (ainfo->pair_storage [0] == ArgInIReg)
6057                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6058                                 break;
6059                         default:
6060                                 break;
6061                         }
6062                 } else {
6063                         /* Argument allocated to (non-volatile) register */
6064                         switch (ainfo->storage) {
6065                         case ArgInIReg:
6066                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6067                                 break;
6068                         case ArgOnStack:
6069                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6070                                 break;
6071                         default:
6072                                 g_assert_not_reached ();
6073                         }
6074                 }
6075         }
6076
6077         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6078         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6079                 guint64 domain = (guint64)cfg->domain;
6080
6081                 args_clobbered = TRUE;
6082
6083                 /*
6084                  * The call might clobber argument registers, but they are already
6085                  * saved to the stack/global regs.
6086                  */
6087                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6088                         guint8 *buf, *no_domain_branch;
6089
6090                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6091                         if (cfg->compile_aot) {
6092                                 /* AOT code is only used in the root domain */
6093                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6094                         } else {
6095                                 if ((domain >> 32) == 0)
6096                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6097                                 else
6098                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6099                         }
6100                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6101                         no_domain_branch = code;
6102                         x86_branch8 (code, X86_CC_NE, 0, 0);
6103                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6104                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6105                         buf = code;
6106                         x86_branch8 (code, X86_CC_NE, 0, 0);
6107                         amd64_patch (no_domain_branch, code);
6108                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6109                                           (gpointer)"mono_jit_thread_attach", TRUE);
6110                         amd64_patch (buf, code);
6111 #ifdef HOST_WIN32
6112                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6113                         /* FIXME: Add a separate key for LMF to avoid this */
6114                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6115 #endif
6116                 } else {
6117                         g_assert (!cfg->compile_aot);
6118                         if (cfg->compile_aot) {
6119                                 /* AOT code is only used in the root domain */
6120                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6121                         } else {
6122                                 if ((domain >> 32) == 0)
6123                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6124                                 else
6125                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6126                         }
6127                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6128                                           (gpointer)"mono_jit_thread_attach", TRUE);
6129                 }
6130         }
6131
6132         if (method->save_lmf) {
6133                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6134                         /*
6135                          * Optimized version which uses the mono_lmf TLS variable instead of
6136                          * indirection through the mono_lmf_addr TLS variable.
6137                          */
6138                         /* %rax = previous_lmf */
6139                         x86_prefix (code, X86_FS_PREFIX);
6140                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6141
6142                         /* Save previous_lmf */
6143                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6144                         /* Set new lmf */
6145                         if (lmf_offset == 0) {
6146                                 x86_prefix (code, X86_FS_PREFIX);
6147                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6148                         } else {
6149                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6150                                 x86_prefix (code, X86_FS_PREFIX);
6151                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6152                         }
6153                 } else {
6154                         if (lmf_addr_tls_offset != -1) {
6155                                 /* Load lmf quicky using the FS register */
6156                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6157 #ifdef HOST_WIN32
6158                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6159                                 /* FIXME: Add a separate key for LMF to avoid this */
6160                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6161 #endif
6162                         }
6163                         else {
6164                                 /*
6165                                  * The call might clobber argument registers, but they are already
6166                                  * saved to the stack/global regs.
6167                                  */
6168                                 args_clobbered = TRUE;
6169                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6170                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6171                         }
6172
6173                         /* Save lmf_addr */
6174                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6175                         /* Save previous_lmf */
6176                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6177                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6178                         /* Set new lmf */
6179                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6180                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6181                 }
6182         }
6183
6184         if (trace) {
6185                 args_clobbered = TRUE;
6186                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6187         }
6188
6189         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6190                 args_clobbered = TRUE;
6191
6192         /*
6193          * Optimize the common case of the first bblock making a call with the same
6194          * arguments as the method. This works because the arguments are still in their
6195          * original argument registers.
6196          * FIXME: Generalize this
6197          */
6198         if (!args_clobbered) {
6199                 MonoBasicBlock *first_bb = cfg->bb_entry;
6200                 MonoInst *next;
6201
6202                 next = mono_bb_first_ins (first_bb);
6203                 if (!next && first_bb->next_bb) {
6204                         first_bb = first_bb->next_bb;
6205                         next = mono_bb_first_ins (first_bb);
6206                 }
6207
6208                 if (first_bb->in_count > 1)
6209                         next = NULL;
6210
6211                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6212                         ArgInfo *ainfo = cinfo->args + i;
6213                         gboolean match = FALSE;
6214
6215                         ins = cfg->args [i];
6216                         if (ins->opcode != OP_REGVAR) {
6217                                 switch (ainfo->storage) {
6218                                 case ArgInIReg: {
6219                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6220                                                 if (next->dreg == ainfo->reg) {
6221                                                         NULLIFY_INS (next);
6222                                                         match = TRUE;
6223                                                 } else {
6224                                                         next->opcode = OP_MOVE;
6225                                                         next->sreg1 = ainfo->reg;
6226                                                         /* Only continue if the instruction doesn't change argument regs */
6227                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6228                                                                 match = TRUE;
6229                                                 }
6230                                         }
6231                                         break;
6232                                 }
6233                                 default:
6234                                         break;
6235                                 }
6236                         } else {
6237                                 /* Argument allocated to (non-volatile) register */
6238                                 switch (ainfo->storage) {
6239                                 case ArgInIReg:
6240                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6241                                                 NULLIFY_INS (next);
6242                                                 match = TRUE;
6243                                         }
6244                                         break;
6245                                 default:
6246                                         break;
6247                                 }
6248                         }
6249
6250                         if (match) {
6251                                 next = next->next;
6252                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6253                                 if (!next)
6254                                         break;
6255                         }
6256                 }
6257         }
6258
6259         /* Initialize ss_trigger_page_var */
6260         if (cfg->arch.ss_trigger_page_var) {
6261                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6262
6263                 g_assert (!cfg->compile_aot);
6264                 g_assert (var->opcode == OP_REGOFFSET);
6265
6266                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6267                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6268         }
6269
6270         cfg->code_len = code - cfg->native_code;
6271
6272         g_assert (cfg->code_len < cfg->code_size);
6273
6274         return code;
6275 }
6276
6277 void
6278 mono_arch_emit_epilog (MonoCompile *cfg)
6279 {
6280         MonoMethod *method = cfg->method;
6281         int quad, pos, i;
6282         guint8 *code;
6283         int max_epilog_size;
6284         CallInfo *cinfo;
6285         gint32 lmf_offset = cfg->arch.lmf_offset;
6286
6287         max_epilog_size = get_max_epilog_size (cfg);
6288
6289         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6290                 cfg->code_size *= 2;
6291                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6292                 mono_jit_stats.code_reallocs++;
6293         }
6294
6295         code = cfg->native_code + cfg->code_len;
6296
6297         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6298                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6299
6300         /* the code restoring the registers must be kept in sync with OP_JMP */
6301         pos = 0;
6302
6303         if (method->save_lmf) {
6304                 /* check if we need to restore protection of the stack after a stack overflow */
6305                 if (mono_get_jit_tls_offset () != -1) {
6306                         guint8 *patch;
6307                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6308                         /* we load the value in a separate instruction: this mechanism may be
6309                          * used later as a safer way to do thread interruption
6310                          */
6311                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6312                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6313                         patch = code;
6314                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6315                         /* note that the call trampoline will preserve eax/edx */
6316                         x86_call_reg (code, X86_ECX);
6317                         x86_patch (patch, code);
6318                 } else {
6319                         /* FIXME: maybe save the jit tls in the prolog */
6320                 }
6321                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6322                         /*
6323                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6324                          * through the mono_lmf_addr TLS variable.
6325                          */
6326                         /* reg = previous_lmf */
6327                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6328                         x86_prefix (code, X86_FS_PREFIX);
6329                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6330                 } else {
6331                         /* Restore previous lmf */
6332                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6333                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6334                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6335                 }
6336
6337                 /* Restore caller saved regs */
6338                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6339                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6340                 }
6341                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6342                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6343                 }
6344                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6345                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6346                 }
6347                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6348                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6349                 }
6350                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6351                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6352                 }
6353                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6354                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6355                 }
6356 #ifdef HOST_WIN32
6357                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6358                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6359                 }
6360                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6361                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6362                 }
6363 #endif
6364         } else {
6365
6366                 if (cfg->arch.omit_fp) {
6367                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6368
6369                         for (i = 0; i < AMD64_NREG; ++i)
6370                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6371                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6372                                         save_area_offset += 8;
6373                                 }
6374                 }
6375                 else {
6376                         for (i = 0; i < AMD64_NREG; ++i)
6377                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6378                                         pos -= sizeof (gpointer);
6379
6380                         if (pos) {
6381                                 if (pos == - sizeof (gpointer)) {
6382                                         /* Only one register, so avoid lea */
6383                                         for (i = AMD64_NREG - 1; i > 0; --i)
6384                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6385                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6386                                                 }
6387                                 }
6388                                 else {
6389                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6390
6391                                         /* Pop registers in reverse order */
6392                                         for (i = AMD64_NREG - 1; i > 0; --i)
6393                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6394                                                         amd64_pop_reg (code, i);
6395                                                 }
6396                                 }
6397                         }
6398                 }
6399         }
6400
6401         /* Load returned vtypes into registers if needed */
6402         cinfo = cfg->arch.cinfo;
6403         if (cinfo->ret.storage == ArgValuetypeInReg) {
6404                 ArgInfo *ainfo = &cinfo->ret;
6405                 MonoInst *inst = cfg->ret;
6406
6407                 for (quad = 0; quad < 2; quad ++) {
6408                         switch (ainfo->pair_storage [quad]) {
6409                         case ArgInIReg:
6410                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6411                                 break;
6412                         case ArgInFloatSSEReg:
6413                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6414                                 break;
6415                         case ArgInDoubleSSEReg:
6416                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6417                                 break;
6418                         case ArgNone:
6419                                 break;
6420                         default:
6421                                 g_assert_not_reached ();
6422                         }
6423                 }
6424         }
6425
6426         if (cfg->arch.omit_fp) {
6427                 if (cfg->arch.stack_alloc_size)
6428                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6429         } else {
6430                 amd64_leave (code);
6431         }
6432         async_exc_point (code);
6433         amd64_ret (code);
6434
6435         cfg->code_len = code - cfg->native_code;
6436
6437         g_assert (cfg->code_len < cfg->code_size);
6438 }
6439
6440 void
6441 mono_arch_emit_exceptions (MonoCompile *cfg)
6442 {
6443         MonoJumpInfo *patch_info;
6444         int nthrows, i;
6445         guint8 *code;
6446         MonoClass *exc_classes [16];
6447         guint8 *exc_throw_start [16], *exc_throw_end [16];
6448         guint32 code_size = 0;
6449
6450         /* Compute needed space */
6451         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6452                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6453                         code_size += 40;
6454                 if (patch_info->type == MONO_PATCH_INFO_R8)
6455                         code_size += 8 + 15; /* sizeof (double) + alignment */
6456                 if (patch_info->type == MONO_PATCH_INFO_R4)
6457                         code_size += 4 + 15; /* sizeof (float) + alignment */
6458         }
6459
6460         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6461                 cfg->code_size *= 2;
6462                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6463                 mono_jit_stats.code_reallocs++;
6464         }
6465
6466         code = cfg->native_code + cfg->code_len;
6467
6468         /* add code to raise exceptions */
6469         nthrows = 0;
6470         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6471                 switch (patch_info->type) {
6472                 case MONO_PATCH_INFO_EXC: {
6473                         MonoClass *exc_class;
6474                         guint8 *buf, *buf2;
6475                         guint32 throw_ip;
6476
6477                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6478
6479                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6480                         g_assert (exc_class);
6481                         throw_ip = patch_info->ip.i;
6482
6483                         //x86_breakpoint (code);
6484                         /* Find a throw sequence for the same exception class */
6485                         for (i = 0; i < nthrows; ++i)
6486                                 if (exc_classes [i] == exc_class)
6487                                         break;
6488                         if (i < nthrows) {
6489                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6490                                 x86_jump_code (code, exc_throw_start [i]);
6491                                 patch_info->type = MONO_PATCH_INFO_NONE;
6492                         }
6493                         else {
6494                                 buf = code;
6495                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6496                                 buf2 = code;
6497
6498                                 if (nthrows < 16) {
6499                                         exc_classes [nthrows] = exc_class;
6500                                         exc_throw_start [nthrows] = code;
6501                                 }
6502                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6503
6504                                 patch_info->type = MONO_PATCH_INFO_NONE;
6505
6506                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6507
6508                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6509                                 while (buf < buf2)
6510                                         x86_nop (buf);
6511
6512                                 if (nthrows < 16) {
6513                                         exc_throw_end [nthrows] = code;
6514                                         nthrows ++;
6515                                 }
6516                         }
6517                         break;
6518                 }
6519                 default:
6520                         /* do nothing */
6521                         break;
6522                 }
6523         }
6524
6525         /* Handle relocations with RIP relative addressing */
6526         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6527                 gboolean remove = FALSE;
6528
6529                 switch (patch_info->type) {
6530                 case MONO_PATCH_INFO_R8:
6531                 case MONO_PATCH_INFO_R4: {
6532                         guint8 *pos;
6533
6534                         /* The SSE opcodes require a 16 byte alignment */
6535                         code = (guint8*)ALIGN_TO (code, 16);
6536
6537                         pos = cfg->native_code + patch_info->ip.i;
6538
6539                         if (IS_REX (pos [1]))
6540                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6541                         else
6542                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6543
6544                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6545                                 *(double*)code = *(double*)patch_info->data.target;
6546                                 code += sizeof (double);
6547                         } else {
6548                                 *(float*)code = *(float*)patch_info->data.target;
6549                                 code += sizeof (float);
6550                         }
6551
6552                         remove = TRUE;
6553                         break;
6554                 }
6555                 default:
6556                         break;
6557                 }
6558
6559                 if (remove) {
6560                         if (patch_info == cfg->patch_info)
6561                                 cfg->patch_info = patch_info->next;
6562                         else {
6563                                 MonoJumpInfo *tmp;
6564
6565                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6566                                         ;
6567                                 tmp->next = patch_info->next;
6568                         }
6569                 }
6570         }
6571
6572         cfg->code_len = code - cfg->native_code;
6573
6574         g_assert (cfg->code_len < cfg->code_size);
6575
6576 }
6577
6578 #endif /* DISABLE_JIT */
6579
6580 void*
6581 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6582 {
6583         guchar *code = p;
6584         CallInfo *cinfo = NULL;
6585         MonoMethodSignature *sig;
6586         MonoInst *inst;
6587         int i, n, stack_area = 0;
6588
6589         /* Keep this in sync with mono_arch_get_argument_info */
6590
6591         if (enable_arguments) {
6592                 /* Allocate a new area on the stack and save arguments there */
6593                 sig = mono_method_signature (cfg->method);
6594
6595                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6596
6597                 n = sig->param_count + sig->hasthis;
6598
6599                 stack_area = ALIGN_TO (n * 8, 16);
6600
6601                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6602
6603                 for (i = 0; i < n; ++i) {
6604                         inst = cfg->args [i];
6605
6606                         if (inst->opcode == OP_REGVAR)
6607                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6608                         else {
6609                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6610                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6611                         }
6612                 }
6613         }
6614
6615         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6616         amd64_set_reg_template (code, AMD64_ARG_REG1);
6617         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6618         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6619
6620         if (enable_arguments)
6621                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6622
6623         return code;
6624 }
6625
6626 enum {
6627         SAVE_NONE,
6628         SAVE_STRUCT,
6629         SAVE_EAX,
6630         SAVE_EAX_EDX,
6631         SAVE_XMM
6632 };
6633
6634 void*
6635 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6636 {
6637         guchar *code = p;
6638         int save_mode = SAVE_NONE;
6639         MonoMethod *method = cfg->method;
6640         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6641
6642         switch (ret_type->type) {
6643         case MONO_TYPE_VOID:
6644                 /* special case string .ctor icall */
6645                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6646                         save_mode = SAVE_EAX;
6647                 else
6648                         save_mode = SAVE_NONE;
6649                 break;
6650         case MONO_TYPE_I8:
6651         case MONO_TYPE_U8:
6652                 save_mode = SAVE_EAX;
6653                 break;
6654         case MONO_TYPE_R4:
6655         case MONO_TYPE_R8:
6656                 save_mode = SAVE_XMM;
6657                 break;
6658         case MONO_TYPE_GENERICINST:
6659                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6660                         save_mode = SAVE_EAX;
6661                         break;
6662                 }
6663                 /* Fall through */
6664         case MONO_TYPE_VALUETYPE:
6665                 save_mode = SAVE_STRUCT;
6666                 break;
6667         default:
6668                 save_mode = SAVE_EAX;
6669                 break;
6670         }
6671
6672         /* Save the result and copy it into the proper argument register */
6673         switch (save_mode) {
6674         case SAVE_EAX:
6675                 amd64_push_reg (code, AMD64_RAX);
6676                 /* Align stack */
6677                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6678                 if (enable_arguments)
6679                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6680                 break;
6681         case SAVE_STRUCT:
6682                 /* FIXME: */
6683                 if (enable_arguments)
6684                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6685                 break;
6686         case SAVE_XMM:
6687                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6688                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6689                 /* Align stack */
6690                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6691                 /*
6692                  * The result is already in the proper argument register so no copying
6693                  * needed.
6694                  */
6695                 break;
6696         case SAVE_NONE:
6697                 break;
6698         default:
6699                 g_assert_not_reached ();
6700         }
6701
6702         /* Set %al since this is a varargs call */
6703         if (save_mode == SAVE_XMM)
6704                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6705         else
6706                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6707
6708         if (preserve_argument_registers) {
6709                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6710                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6711         }
6712
6713         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6714         amd64_set_reg_template (code, AMD64_ARG_REG1);
6715         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6716
6717         if (preserve_argument_registers) {
6718                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6719                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6720         }
6721
6722         /* Restore result */
6723         switch (save_mode) {
6724         case SAVE_EAX:
6725                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6726                 amd64_pop_reg (code, AMD64_RAX);
6727                 break;
6728         case SAVE_STRUCT:
6729                 /* FIXME: */
6730                 break;
6731         case SAVE_XMM:
6732                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6733                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6734                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6735                 break;
6736         case SAVE_NONE:
6737                 break;
6738         default:
6739                 g_assert_not_reached ();
6740         }
6741
6742         return code;
6743 }
6744
6745 void
6746 mono_arch_flush_icache (guint8 *code, gint size)
6747 {
6748         /* Not needed */
6749 }
6750
6751 void
6752 mono_arch_flush_register_windows (void)
6753 {
6754 }
6755
6756 gboolean
6757 mono_arch_is_inst_imm (gint64 imm)
6758 {
6759         return amd64_is_imm32 (imm);
6760 }
6761
6762 /*
6763  * Determine whenever the trap whose info is in SIGINFO is caused by
6764  * integer overflow.
6765  */
6766 gboolean
6767 mono_arch_is_int_overflow (void *sigctx, void *info)
6768 {
6769         MonoContext ctx;
6770         guint8* rip;
6771         int reg;
6772         gint64 value;
6773
6774         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6775
6776         rip = (guint8*)ctx.rip;
6777
6778         if (IS_REX (rip [0])) {
6779                 reg = amd64_rex_b (rip [0]);
6780                 rip ++;
6781         }
6782         else
6783                 reg = 0;
6784
6785         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6786                 /* idiv REG */
6787                 reg += x86_modrm_rm (rip [1]);
6788
6789                 switch (reg) {
6790                 case AMD64_RAX:
6791                         value = ctx.rax;
6792                         break;
6793                 case AMD64_RBX:
6794                         value = ctx.rbx;
6795                         break;
6796                 case AMD64_RCX:
6797                         value = ctx.rcx;
6798                         break;
6799                 case AMD64_RDX:
6800                         value = ctx.rdx;
6801                         break;
6802                 case AMD64_RBP:
6803                         value = ctx.rbp;
6804                         break;
6805                 case AMD64_RSP:
6806                         value = ctx.rsp;
6807                         break;
6808                 case AMD64_RSI:
6809                         value = ctx.rsi;
6810                         break;
6811                 case AMD64_RDI:
6812                         value = ctx.rdi;
6813                         break;
6814                 case AMD64_R12:
6815                         value = ctx.r12;
6816                         break;
6817                 case AMD64_R13:
6818                         value = ctx.r13;
6819                         break;
6820                 case AMD64_R14:
6821                         value = ctx.r14;
6822                         break;
6823                 case AMD64_R15:
6824                         value = ctx.r15;
6825                         break;
6826                 default:
6827                         g_assert_not_reached ();
6828                         reg = -1;
6829                 }
6830
6831                 if (value == -1)
6832                         return TRUE;
6833         }
6834
6835         return FALSE;
6836 }
6837
6838 guint32
6839 mono_arch_get_patch_offset (guint8 *code)
6840 {
6841         return 3;
6842 }
6843
6844 /**
6845  * mono_breakpoint_clean_code:
6846  *
6847  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6848  * breakpoints in the original code, they are removed in the copy.
6849  *
6850  * Returns TRUE if no sw breakpoint was present.
6851  */
6852 gboolean
6853 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6854 {
6855         int i;
6856         gboolean can_write = TRUE;
6857         /*
6858          * If method_start is non-NULL we need to perform bound checks, since we access memory
6859          * at code - offset we could go before the start of the method and end up in a different
6860          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6861          * instead.
6862          */
6863         if (!method_start || code - offset >= method_start) {
6864                 memcpy (buf, code - offset, size);
6865         } else {
6866                 int diff = code - method_start;
6867                 memset (buf, 0, size);
6868                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6869         }
6870         code -= offset;
6871         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6872                 int idx = mono_breakpoint_info_index [i];
6873                 guint8 *ptr;
6874                 if (idx < 1)
6875                         continue;
6876                 ptr = mono_breakpoint_info [idx].address;
6877                 if (ptr >= code && ptr < code + size) {
6878                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6879                         can_write = FALSE;
6880                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6881                         buf [ptr - code] = saved_byte;
6882                 }
6883         }
6884         return can_write;
6885 }
6886
6887 gpointer
6888 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6889 {
6890         guint8 buf [10];
6891         guint32 reg;
6892         gint32 disp;
6893         guint8 rex = 0;
6894         MonoJitInfo *ji = NULL;
6895
6896 #ifdef ENABLE_LLVM
6897         /* code - 9 might be before the start of the method */
6898         /* FIXME: Avoid this expensive call somehow */
6899         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6900 #endif
6901
6902         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6903         code = buf + 9;
6904
6905         *displacement = 0;
6906
6907         code -= 7;
6908
6909         /*
6910          * A given byte sequence can match more than case here, so we have to be
6911          * really careful about the ordering of the cases. Longer sequences
6912          * come first.
6913          * There are two types of calls:
6914          * - direct calls: 0xff address_byte 8/32 bits displacement
6915          * - indirect calls: nop nop nop <call>
6916          * The nops make sure we don't confuse the instruction preceeding an indirect
6917          * call with a direct call.
6918          */
6919         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6920                 /* call OFFSET(%rip) */
6921                 disp = *(guint32*)(code + 3);
6922                 return (gpointer*)(code + disp + 7);
6923         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6924                 /* call *[reg+disp32] using indexed addressing */
6925                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6926                 if (IS_REX (code [-1])) {
6927                         rex = code [-1];
6928                         g_assert (amd64_rex_x (rex) == 0);
6929                 }
6930                 reg = amd64_sib_base (code [2]);
6931                 disp = *(gint32*)(code + 3);
6932         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6933                 /* call *[reg+disp32] */
6934                 if (IS_REX (code [0]))
6935                         rex = code [0];
6936                 reg = amd64_modrm_rm (code [2]);
6937                 disp = *(gint32*)(code + 3);
6938                 /* R10 is clobbered by the IMT thunk code */
6939                 g_assert (reg != AMD64_R10);
6940         } else if (code [2] == 0xe8) {
6941                 /* call <ADDR> */
6942                 return NULL;
6943         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6944                 /* call *[r12+disp8] using indexed addressing */
6945                 if (IS_REX (code [2]))
6946                         rex = code [2];
6947                 reg = amd64_sib_base (code [5]);
6948                 disp = *(gint8*)(code + 6);
6949         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6950                 /* call *%reg */
6951                 return NULL;
6952         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6953                 /* call *[reg+disp8] */
6954                 if (IS_REX (code [3]))
6955                         rex = code [3];
6956                 reg = amd64_modrm_rm (code [5]);
6957                 disp = *(gint8*)(code + 6);
6958                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6959         }
6960         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6961                 /* call *%reg */
6962                 if (IS_REX (code [4]))
6963                         rex = code [4];
6964                 reg = amd64_modrm_rm (code [6]);
6965                 disp = 0;
6966         }
6967         else
6968                 g_assert_not_reached ();
6969
6970         reg += amd64_rex_b (rex);
6971
6972         /* R11 is clobbered by the trampoline code */
6973         g_assert (reg != AMD64_R11);
6974
6975         *displacement = disp;
6976         return (gpointer)regs [reg];
6977 }
6978
6979 int
6980 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6981 {
6982         int this_reg = AMD64_ARG_REG1;
6983
6984         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6985                 CallInfo *cinfo;
6986
6987                 if (!gsctx && code)
6988                         gsctx = mono_get_generic_context_from_code (code);
6989
6990                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6991
6992                 if (cinfo->ret.storage != ArgValuetypeInReg)
6993                         this_reg = AMD64_ARG_REG2;
6994                 g_free (cinfo);
6995         }
6996
6997         return this_reg;
6998 }
6999
7000 gpointer
7001 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
7002 {
7003         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
7004 }
7005
7006 #define MAX_ARCH_DELEGATE_PARAMS 10
7007
7008 static gpointer
7009 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7010 {
7011         guint8 *code, *start;
7012         int i;
7013
7014         if (has_target) {
7015                 start = code = mono_global_codeman_reserve (64);
7016
7017                 /* Replace the this argument with the target */
7018                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7019                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7020                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7021
7022                 g_assert ((code - start) < 64);
7023         } else {
7024                 start = code = mono_global_codeman_reserve (64);
7025
7026                 if (param_count == 0) {
7027                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7028                 } else {
7029                         /* We have to shift the arguments left */
7030                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7031                         for (i = 0; i < param_count; ++i) {
7032 #ifdef HOST_WIN32
7033                                 if (i < 3)
7034                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7035                                 else
7036                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7037 #else
7038                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7039 #endif
7040                         }
7041
7042                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7043                 }
7044                 g_assert ((code - start) < 64);
7045         }
7046
7047         mono_debug_add_delegate_trampoline (start, code - start);
7048
7049         if (code_len)
7050                 *code_len = code - start;
7051
7052         return start;
7053 }
7054
7055 /*
7056  * mono_arch_get_delegate_invoke_impls:
7057  *
7058  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
7059  * trampolines.
7060  */
7061 GSList*
7062 mono_arch_get_delegate_invoke_impls (void)
7063 {
7064         GSList *res = NULL;
7065         guint8 *code;
7066         guint32 code_len;
7067         int i;
7068
7069         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7070         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
7071
7072         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7073                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7074                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
7075         }
7076
7077         return res;
7078 }
7079
7080 gpointer
7081 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7082 {
7083         guint8 *code, *start;
7084         int i;
7085
7086         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7087                 return NULL;
7088
7089         /* FIXME: Support more cases */
7090         if (MONO_TYPE_ISSTRUCT (sig->ret))
7091                 return NULL;
7092
7093         if (has_target) {
7094                 static guint8* cached = NULL;
7095
7096                 if (cached)
7097                         return cached;
7098
7099                 if (mono_aot_only)
7100                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7101                 else
7102                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7103
7104                 mono_memory_barrier ();
7105
7106                 cached = start;
7107         } else {
7108                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7109                 for (i = 0; i < sig->param_count; ++i)
7110                         if (!mono_is_regsize_var (sig->params [i]))
7111                                 return NULL;
7112                 if (sig->param_count > 4)
7113                         return NULL;
7114
7115                 code = cache [sig->param_count];
7116                 if (code)
7117                         return code;
7118
7119                 if (mono_aot_only) {
7120                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7121                         start = mono_aot_get_named_code (name);
7122                         g_free (name);
7123                 } else {
7124                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7125                 }
7126
7127                 mono_memory_barrier ();
7128
7129                 cache [sig->param_count] = start;
7130         }
7131
7132         return start;
7133 }
7134
7135 /*
7136  * Support for fast access to the thread-local lmf structure using the GS
7137  * segment register on NPTL + kernel 2.6.x.
7138  */
7139
7140 static gboolean tls_offset_inited = FALSE;
7141
7142 void
7143 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7144 {
7145         if (!tls_offset_inited) {
7146 #ifdef HOST_WIN32
7147                 /*
7148                  * We need to init this multiple times, since when we are first called, the key might not
7149                  * be initialized yet.
7150                  */
7151                 appdomain_tls_offset = mono_domain_get_tls_key ();
7152                 lmf_tls_offset = mono_get_jit_tls_key ();
7153                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7154
7155                 /* Only 64 tls entries can be accessed using inline code */
7156                 if (appdomain_tls_offset >= 64)
7157                         appdomain_tls_offset = -1;
7158                 if (lmf_tls_offset >= 64)
7159                         lmf_tls_offset = -1;
7160 #else
7161                 tls_offset_inited = TRUE;
7162 #ifdef MONO_XEN_OPT
7163                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7164 #endif
7165                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7166                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7167                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7168 #endif
7169         }
7170 }
7171
7172 void
7173 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7174 {
7175 }
7176
7177 #ifdef MONO_ARCH_HAVE_IMT
7178
7179 #define CMP_SIZE (6 + 1)
7180 #define CMP_REG_REG_SIZE (4 + 1)
7181 #define BR_SMALL_SIZE 2
7182 #define BR_LARGE_SIZE 6
7183 #define MOV_REG_IMM_SIZE 10
7184 #define MOV_REG_IMM_32BIT_SIZE 6
7185 #define JUMP_REG_SIZE (2 + 1)
7186
7187 static int
7188 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7189 {
7190         int i, distance = 0;
7191         for (i = start; i < target; ++i)
7192                 distance += imt_entries [i]->chunk_size;
7193         return distance;
7194 }
7195
7196 /*
7197  * LOCKING: called with the domain lock held
7198  */
7199 gpointer
7200 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7201         gpointer fail_tramp)
7202 {
7203         int i;
7204         int size = 0;
7205         guint8 *code, *start;
7206         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7207
7208         for (i = 0; i < count; ++i) {
7209                 MonoIMTCheckItem *item = imt_entries [i];
7210                 if (item->is_equals) {
7211                         if (item->check_target_idx) {
7212                                 if (!item->compare_done) {
7213                                         if (amd64_is_imm32 (item->key))
7214                                                 item->chunk_size += CMP_SIZE;
7215                                         else
7216                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7217                                 }
7218                                 if (item->has_target_code) {
7219                                         item->chunk_size += MOV_REG_IMM_SIZE;
7220                                 } else {
7221                                         if (vtable_is_32bit)
7222                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7223                                         else
7224                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7225                                 }
7226                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7227                         } else {
7228                                 if (fail_tramp) {
7229                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7230                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7231                                 } else {
7232                                         if (vtable_is_32bit)
7233                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7234                                         else
7235                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7236                                         item->chunk_size += JUMP_REG_SIZE;
7237                                         /* with assert below:
7238                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7239                                          */
7240                                 }
7241                         }
7242                 } else {
7243                         if (amd64_is_imm32 (item->key))
7244                                 item->chunk_size += CMP_SIZE;
7245                         else
7246                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7247                         item->chunk_size += BR_LARGE_SIZE;
7248                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7249                 }
7250                 size += item->chunk_size;
7251         }
7252         if (fail_tramp)
7253                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7254         else
7255                 code = mono_domain_code_reserve (domain, size);
7256         start = code;
7257         for (i = 0; i < count; ++i) {
7258                 MonoIMTCheckItem *item = imt_entries [i];
7259                 item->code_target = code;
7260                 if (item->is_equals) {
7261                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7262
7263                         if (item->check_target_idx || fail_case) {
7264                                 if (!item->compare_done || fail_case) {
7265                                         if (amd64_is_imm32 (item->key))
7266                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7267                                         else {
7268                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7269                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7270                                         }
7271                                 }
7272                                 item->jmp_code = code;
7273                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7274                                 /* See the comment below about R10 */
7275                                 if (item->has_target_code) {
7276                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7277                                         amd64_jump_reg (code, AMD64_R10);
7278                                 } else {
7279                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7280                                         amd64_jump_membase (code, AMD64_R10, 0);
7281                                 }
7282
7283                                 if (fail_case) {
7284                                         amd64_patch (item->jmp_code, code);
7285                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7286                                         amd64_jump_reg (code, AMD64_R10);
7287                                         item->jmp_code = NULL;
7288                                 }
7289                         } else {
7290                                 /* enable the commented code to assert on wrong method */
7291 #if 0
7292                                 if (amd64_is_imm32 (item->key))
7293                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7294                                 else {
7295                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7296                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7297                                 }
7298                                 item->jmp_code = code;
7299                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7300                                 /* See the comment below about R10 */
7301                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7302                                 amd64_jump_membase (code, AMD64_R10, 0);
7303                                 amd64_patch (item->jmp_code, code);
7304                                 amd64_breakpoint (code);
7305                                 item->jmp_code = NULL;
7306 #else
7307                                 /* We're using R10 here because R11
7308                                    needs to be preserved.  R10 needs
7309                                    to be preserved for calls which
7310                                    require a runtime generic context,
7311                                    but interface calls don't. */
7312                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7313                                 amd64_jump_membase (code, AMD64_R10, 0);
7314 #endif
7315                         }
7316                 } else {
7317                         if (amd64_is_imm32 (item->key))
7318                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7319                         else {
7320                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7321                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7322                         }
7323                         item->jmp_code = code;
7324                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7325                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7326                         else
7327                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7328                 }
7329                 g_assert (code - item->code_target <= item->chunk_size);
7330         }
7331         /* patch the branches to get to the target items */
7332         for (i = 0; i < count; ++i) {
7333                 MonoIMTCheckItem *item = imt_entries [i];
7334                 if (item->jmp_code) {
7335                         if (item->check_target_idx) {
7336                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7337                         }
7338                 }
7339         }
7340
7341         if (!fail_tramp)
7342                 mono_stats.imt_thunks_size += code - start;
7343         g_assert (code - start <= size);
7344
7345         return start;
7346 }
7347
7348 MonoMethod*
7349 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7350 {
7351         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7352 }
7353 #endif
7354
7355 MonoVTable*
7356 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7357 {
7358         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7359 }
7360
7361 GSList*
7362 mono_arch_get_cie_program (void)
7363 {
7364         GSList *l = NULL;
7365
7366         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7367         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7368
7369         return l;
7370 }
7371
7372 MonoInst*
7373 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7374 {
7375         MonoInst *ins = NULL;
7376         int opcode = 0;
7377
7378         if (cmethod->klass == mono_defaults.math_class) {
7379                 if (strcmp (cmethod->name, "Sin") == 0) {
7380                         opcode = OP_SIN;
7381                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7382                         opcode = OP_COS;
7383                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7384                         opcode = OP_SQRT;
7385                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7386                         opcode = OP_ABS;
7387                 }
7388
7389                 if (opcode) {
7390                         MONO_INST_NEW (cfg, ins, opcode);
7391                         ins->type = STACK_R8;
7392                         ins->dreg = mono_alloc_freg (cfg);
7393                         ins->sreg1 = args [0]->dreg;
7394                         MONO_ADD_INS (cfg->cbb, ins);
7395                 }
7396
7397                 opcode = 0;
7398                 if (cfg->opt & MONO_OPT_CMOV) {
7399                         if (strcmp (cmethod->name, "Min") == 0) {
7400                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7401                                         opcode = OP_IMIN;
7402                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7403                                         opcode = OP_IMIN_UN;
7404                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7405                                         opcode = OP_LMIN;
7406                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7407                                         opcode = OP_LMIN_UN;
7408                         } else if (strcmp (cmethod->name, "Max") == 0) {
7409                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7410                                         opcode = OP_IMAX;
7411                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7412                                         opcode = OP_IMAX_UN;
7413                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7414                                         opcode = OP_LMAX;
7415                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7416                                         opcode = OP_LMAX_UN;
7417                         }
7418                 }
7419
7420                 if (opcode) {
7421                         MONO_INST_NEW (cfg, ins, opcode);
7422                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7423                         ins->dreg = mono_alloc_ireg (cfg);
7424                         ins->sreg1 = args [0]->dreg;
7425                         ins->sreg2 = args [1]->dreg;
7426                         MONO_ADD_INS (cfg->cbb, ins);
7427                 }
7428
7429 #if 0
7430                 /* OP_FREM is not IEEE compatible */
7431                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7432                         MONO_INST_NEW (cfg, ins, OP_FREM);
7433                         ins->inst_i0 = args [0];
7434                         ins->inst_i1 = args [1];
7435                 }
7436 #endif
7437         }
7438
7439         /*
7440          * Can't implement CompareExchange methods this way since they have
7441          * three arguments.
7442          */
7443
7444         return ins;
7445 }
7446
7447 gboolean
7448 mono_arch_print_tree (MonoInst *tree, int arity)
7449 {
7450         return 0;
7451 }
7452
7453 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7454 {
7455         MonoInst* ins;
7456
7457         if (appdomain_tls_offset == -1)
7458                 return NULL;
7459
7460         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7461         ins->inst_offset = appdomain_tls_offset;
7462         return ins;
7463 }
7464
7465 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7466
7467 gpointer
7468 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7469 {
7470         switch (reg) {
7471         case AMD64_RCX: return (gpointer)ctx->rcx;
7472         case AMD64_RDX: return (gpointer)ctx->rdx;
7473         case AMD64_RBX: return (gpointer)ctx->rbx;
7474         case AMD64_RBP: return (gpointer)ctx->rbp;
7475         case AMD64_RSP: return (gpointer)ctx->rsp;
7476         default:
7477                 if (reg < 8)
7478                         return _CTX_REG (ctx, rax, reg);
7479                 else if (reg >= 12)
7480                         return _CTX_REG (ctx, r12, reg - 12);
7481                 else
7482                         g_assert_not_reached ();
7483         }
7484 }
7485
7486 /* Soft Debug support */
7487 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7488
7489 /*
7490  * mono_arch_set_breakpoint:
7491  *
7492  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7493  * The location should contain code emitted by OP_SEQ_POINT.
7494  */
7495 void
7496 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7497 {
7498         guint8 *code = ip;
7499         guint8 *orig_code = code;
7500
7501         /*
7502          * In production, we will use int3 (has to fix the size in the md
7503          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7504          * instead.
7505          */
7506         g_assert (code [0] == 0x90);
7507         if (breakpoint_size == 8) {
7508                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7509         } else {
7510                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7511                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7512         }
7513
7514         g_assert (code - orig_code == breakpoint_size);
7515 }
7516
7517 /*
7518  * mono_arch_clear_breakpoint:
7519  *
7520  *   Clear the breakpoint at IP.
7521  */
7522 void
7523 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7524 {
7525         guint8 *code = ip;
7526         int i;
7527
7528         for (i = 0; i < breakpoint_size; ++i)
7529                 x86_nop (code);
7530 }
7531
7532 gboolean
7533 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7534 {
7535 #ifdef HOST_WIN32
7536         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7537         return FALSE;
7538 #else
7539         siginfo_t* sinfo = (siginfo_t*) info;
7540         /* Sometimes the address is off by 4 */
7541         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7542                 return TRUE;
7543         else
7544                 return FALSE;
7545 #endif
7546 }
7547
7548 /*
7549  * mono_arch_get_ip_for_breakpoint:
7550  *
7551  *   Convert the ip in CTX to the address where a breakpoint was placed.
7552  */
7553 guint8*
7554 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7555 {
7556         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7557
7558         /* ip points to the instruction causing the fault */
7559         ip -= (breakpoint_size - breakpoint_fault_size);
7560
7561         return ip;
7562 }
7563
7564 /*
7565  * mono_arch_skip_breakpoint:
7566  *
7567  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7568  * we resume, the instruction is not executed again.
7569  */
7570 void
7571 mono_arch_skip_breakpoint (MonoContext *ctx)
7572 {
7573         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7574 }
7575
7576 /*
7577  * mono_arch_start_single_stepping:
7578  *
7579  *   Start single stepping.
7580  */
7581 void
7582 mono_arch_start_single_stepping (void)
7583 {
7584         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7585 }
7586
7587 /*
7588  * mono_arch_stop_single_stepping:
7589  *
7590  *   Stop single stepping.
7591  */
7592 void
7593 mono_arch_stop_single_stepping (void)
7594 {
7595         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7596 }
7597
7598 /*
7599  * mono_arch_is_single_step_event:
7600  *
7601  *   Return whenever the machine state in SIGCTX corresponds to a single
7602  * step event.
7603  */
7604 gboolean
7605 mono_arch_is_single_step_event (void *info, void *sigctx)
7606 {
7607 #ifdef HOST_WIN32
7608         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7609         return FALSE;
7610 #else
7611         siginfo_t* sinfo = (siginfo_t*) info;
7612         /* Sometimes the address is off by 4 */
7613         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7614                 return TRUE;
7615         else
7616                 return FALSE;
7617 #endif
7618 }
7619
7620 /*
7621  * mono_arch_get_ip_for_single_step:
7622  *
7623  *   Convert the ip in CTX to the address stored in seq_points.
7624  */
7625 guint8*
7626 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7627 {
7628         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7629
7630         ip += single_step_fault_size;
7631
7632         return ip;
7633 }
7634
7635 /*
7636  * mono_arch_skip_single_step:
7637  *
7638  *   Modify CTX so the ip is placed after the single step trigger instruction,
7639  * we resume, the instruction is not executed again.
7640  */
7641 void
7642 mono_arch_skip_single_step (MonoContext *ctx)
7643 {
7644         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7645 }
7646
7647 /*
7648  * mono_arch_create_seq_point_info:
7649  *
7650  *   Return a pointer to a data structure which is used by the sequence
7651  * point implementation in AOTed code.
7652  */
7653 gpointer
7654 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7655 {
7656         NOT_IMPLEMENTED;
7657         return NULL;
7658 }
7659
7660 #endif