2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
24 #include <mono/metadata/abi-details.h>
25 #include <mono/metadata/appdomain.h>
26 #include <mono/metadata/debug-helpers.h>
27 #include <mono/metadata/threads.h>
28 #include <mono/metadata/profiler-private.h>
29 #include <mono/metadata/mono-debug.h>
30 #include <mono/metadata/gc-internals.h>
31 #include <mono/utils/mono-math.h>
32 #include <mono/utils/mono-mmap.h>
33 #include <mono/utils/mono-memory-model.h>
34 #include <mono/utils/mono-tls.h>
35 #include <mono/utils/mono-hwcap-x86.h>
36 #include <mono/utils/mono-threads.h>
40 #include "mini-amd64.h"
41 #include "cpu-amd64.h"
42 #include "debugger-agent.h"
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
67 static mono_mutex_t mini_arch_mutex;
69 /* The single step trampoline */
70 static gpointer ss_trampoline;
72 /* The breakpoint trampoline */
73 static gpointer bp_trampoline;
75 /* Offset between fp and the first argument in the callee */
76 #define ARGS_OFFSET 16
77 #define GP_SCRATCH_REG AMD64_R11
80 * AMD64 register usage:
81 * - callee saved registers are used for global register allocation
82 * - %r11 is used for materializing 64 bit constants in opcodes
83 * - the rest is used for local allocation
87 * Floating point comparison results:
97 mono_arch_regname (int reg)
100 case AMD64_RAX: return "%rax";
101 case AMD64_RBX: return "%rbx";
102 case AMD64_RCX: return "%rcx";
103 case AMD64_RDX: return "%rdx";
104 case AMD64_RSP: return "%rsp";
105 case AMD64_RBP: return "%rbp";
106 case AMD64_RDI: return "%rdi";
107 case AMD64_RSI: return "%rsi";
108 case AMD64_R8: return "%r8";
109 case AMD64_R9: return "%r9";
110 case AMD64_R10: return "%r10";
111 case AMD64_R11: return "%r11";
112 case AMD64_R12: return "%r12";
113 case AMD64_R13: return "%r13";
114 case AMD64_R14: return "%r14";
115 case AMD64_R15: return "%r15";
120 static const char * packed_xmmregs [] = {
121 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
122 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
125 static const char * single_xmmregs [] = {
126 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
127 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
131 mono_arch_fregname (int reg)
133 if (reg < AMD64_XMM_NREG)
134 return single_xmmregs [reg];
140 mono_arch_xregname (int reg)
142 if (reg < AMD64_XMM_NREG)
143 return packed_xmmregs [reg];
152 return mono_debug_count ();
158 static inline gboolean
159 amd64_is_near_call (guint8 *code)
162 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
165 return code [0] == 0xe8;
168 static inline gboolean
169 amd64_use_imm32 (gint64 val)
171 if (mini_get_debug_options()->single_imm_size)
174 return amd64_is_imm32 (val);
177 #ifdef __native_client_codegen__
179 /* Keep track of instruction "depth", that is, the level of sub-instruction */
180 /* for any given instruction. For instance, amd64_call_reg resolves to */
181 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
182 /* We only want to force bundle alignment for the top level instruction, */
183 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
184 static MonoNativeTlsKey nacl_instruction_depth;
186 static MonoNativeTlsKey nacl_rex_tag;
187 static MonoNativeTlsKey nacl_legacy_prefix_tag;
190 amd64_nacl_clear_legacy_prefix_tag ()
192 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
196 amd64_nacl_tag_legacy_prefix (guint8* code)
198 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
199 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
203 amd64_nacl_tag_rex (guint8* code)
205 mono_native_tls_set_value (nacl_rex_tag, code);
209 amd64_nacl_get_legacy_prefix_tag ()
211 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
215 amd64_nacl_get_rex_tag ()
217 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
220 /* Increment the instruction "depth" described above */
222 amd64_nacl_instruction_pre ()
224 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
226 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
229 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
230 /* alignment if depth == 0 (top level instruction) */
231 /* IN: start, end pointers to instruction beginning and end */
232 /* OUT: start, end pointers to beginning and end after possible alignment */
233 /* GLOBALS: nacl_instruction_depth defined above */
235 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
237 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
239 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
241 g_assert ( depth >= 0 );
243 uintptr_t space_in_block;
245 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
246 /* if legacy prefix is present, and if it was emitted before */
247 /* the start of the instruction sequence, adjust the start */
248 if (prefix != NULL && prefix < *start) {
249 g_assert (*start - prefix <= 3);/* only 3 are allowed */
252 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
253 instlen = (uintptr_t)(*end - *start);
254 /* Only check for instructions which are less than */
255 /* kNaClAlignment. The only instructions that should ever */
256 /* be that long are call sequences, which are already */
257 /* padded out to align the return to the next bundle. */
258 if (instlen > space_in_block && instlen < kNaClAlignment) {
259 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
260 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
261 const size_t length = (size_t)((*end)-(*start));
262 g_assert (length < MAX_NACL_INST_LENGTH);
264 memcpy (copy_of_instruction, *start, length);
265 *start = mono_arch_nacl_pad (*start, space_in_block);
266 memcpy (*start, copy_of_instruction, length);
267 *end = *start + length;
269 amd64_nacl_clear_legacy_prefix_tag ();
270 amd64_nacl_tag_rex (NULL);
274 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
275 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
276 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
277 /* make sure the upper 32-bits are cleared, and use that register in the */
278 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
280 /* pointer to current instruction stream (in the */
281 /* middle of an instruction, after opcode is emitted) */
282 /* basereg/offset/dreg */
283 /* operands of normal membase address */
285 /* pointer to the end of the membase/memindex emit */
286 /* GLOBALS: nacl_rex_tag */
287 /* position in instruction stream that rex prefix was emitted */
288 /* nacl_legacy_prefix_tag */
289 /* (possibly NULL) position in instruction of legacy x86 prefix */
291 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
293 gint8 true_basereg = basereg;
295 /* Cache these values, they might change */
296 /* as new instructions are emitted below. */
297 guint8* rex_tag = amd64_nacl_get_rex_tag ();
298 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
300 /* 'basereg' is given masked to 0x7 at this point, so check */
301 /* the rex prefix to see if this is an extended register. */
302 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
306 #define X86_LEA_OPCODE (0x8D)
308 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
309 guint8* old_instruction_start;
311 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
312 /* 32-bits of the old base register (new index register) */
314 guint8* buf_ptr = buf;
317 g_assert (rex_tag != NULL);
319 if (IS_REX(*rex_tag)) {
320 /* The old rex.B should be the new rex.X */
321 if (*rex_tag & AMD64_REX_B) {
322 *rex_tag |= AMD64_REX_X;
324 /* Since our new base is %r15 set rex.B */
325 *rex_tag |= AMD64_REX_B;
327 /* Shift the instruction by one byte */
328 /* so we can insert a rex prefix */
329 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
331 /* New rex prefix only needs rex.B for %r15 base */
332 *rex_tag = AMD64_REX(AMD64_REX_B);
335 if (legacy_prefix_tag) {
336 old_instruction_start = legacy_prefix_tag;
338 old_instruction_start = rex_tag;
341 /* Clears the upper 32-bits of the previous base register */
342 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
343 insert_len = buf_ptr - buf;
345 /* Move the old instruction forward to make */
346 /* room for 'mov' stored in 'buf_ptr' */
347 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
349 memcpy (old_instruction_start, buf, insert_len);
351 /* Sandboxed replacement for the normal membase_emit */
352 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
355 /* Normal default behavior, emit membase memory location */
356 x86_membase_emit_body (*code, dreg, basereg, offset);
361 static inline unsigned char*
362 amd64_skip_nops (unsigned char* code)
367 if ( code[0] == 0x90) {
371 if ( code[0] == 0x66 && code[1] == 0x90) {
375 if (code[0] == 0x0f && code[1] == 0x1f
376 && code[2] == 0x00) {
380 if (code[0] == 0x0f && code[1] == 0x1f
381 && code[2] == 0x40 && code[3] == 0x00) {
385 if (code[0] == 0x0f && code[1] == 0x1f
386 && code[2] == 0x44 && code[3] == 0x00
387 && code[4] == 0x00) {
391 if (code[0] == 0x66 && code[1] == 0x0f
392 && code[2] == 0x1f && code[3] == 0x44
393 && code[4] == 0x00 && code[5] == 0x00) {
397 if (code[0] == 0x0f && code[1] == 0x1f
398 && code[2] == 0x80 && code[3] == 0x00
399 && code[4] == 0x00 && code[5] == 0x00
400 && code[6] == 0x00) {
404 if (code[0] == 0x0f && code[1] == 0x1f
405 && code[2] == 0x84 && code[3] == 0x00
406 && code[4] == 0x00 && code[5] == 0x00
407 && code[6] == 0x00 && code[7] == 0x00) {
416 mono_arch_nacl_skip_nops (guint8* code)
418 return amd64_skip_nops(code);
421 #endif /*__native_client_codegen__*/
424 amd64_patch (unsigned char* code, gpointer target)
428 #ifdef __native_client_codegen__
429 code = amd64_skip_nops (code);
431 #if defined(__native_client_codegen__) && defined(__native_client__)
432 if (nacl_is_code_address (code)) {
433 /* For tail calls, code is patched after being installed */
434 /* but not through the normal "patch callsite" method. */
435 unsigned char buf[kNaClAlignment];
436 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
438 memcpy (buf, aligned_code, kNaClAlignment);
439 /* Patch a temp buffer of bundle size, */
440 /* then install to actual location. */
441 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
442 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
446 target = nacl_modify_patch_target (target);
450 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
455 if ((code [0] & 0xf8) == 0xb8) {
456 /* amd64_set_reg_template */
457 *(guint64*)(code + 1) = (guint64)target;
459 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
460 /* mov 0(%rip), %dreg */
461 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
463 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
464 /* call *<OFFSET>(%rip) */
465 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
467 else if (code [0] == 0xe8) {
469 gint64 disp = (guint8*)target - (guint8*)code;
470 g_assert (amd64_is_imm32 (disp));
471 x86_patch (code, (unsigned char*)target);
474 x86_patch (code, (unsigned char*)target);
478 mono_amd64_patch (unsigned char* code, gpointer target)
480 amd64_patch (code, target);
483 #define DEBUG(a) if (cfg->verbose_level > 1) a
486 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
488 ainfo->offset = *stack_size;
490 if (*gr >= PARAM_REGS) {
491 ainfo->storage = ArgOnStack;
492 ainfo->arg_size = sizeof (mgreg_t);
493 /* Since the same stack slot size is used for all arg */
494 /* types, it needs to be big enough to hold them all */
495 (*stack_size) += sizeof(mgreg_t);
498 ainfo->storage = ArgInIReg;
499 ainfo->reg = param_regs [*gr];
505 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
507 ainfo->offset = *stack_size;
509 if (*gr >= FLOAT_PARAM_REGS) {
510 ainfo->storage = ArgOnStack;
511 ainfo->arg_size = sizeof (mgreg_t);
512 /* Since the same stack slot size is used for both float */
513 /* types, it needs to be big enough to hold them both */
514 (*stack_size) += sizeof(mgreg_t);
517 /* A double register */
519 ainfo->storage = ArgInDoubleSSEReg;
521 ainfo->storage = ArgInFloatSSEReg;
527 typedef enum ArgumentClass {
535 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
537 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
540 ptype = mini_get_underlying_type (type);
541 switch (ptype->type) {
550 case MONO_TYPE_STRING:
551 case MONO_TYPE_OBJECT:
552 case MONO_TYPE_CLASS:
553 case MONO_TYPE_SZARRAY:
555 case MONO_TYPE_FNPTR:
556 case MONO_TYPE_ARRAY:
559 class2 = ARG_CLASS_INTEGER;
564 class2 = ARG_CLASS_INTEGER;
566 class2 = ARG_CLASS_SSE;
570 case MONO_TYPE_TYPEDBYREF:
571 g_assert_not_reached ();
573 case MONO_TYPE_GENERICINST:
574 if (!mono_type_generic_inst_is_valuetype (ptype)) {
575 class2 = ARG_CLASS_INTEGER;
579 case MONO_TYPE_VALUETYPE: {
580 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
583 for (i = 0; i < info->num_fields; ++i) {
585 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
590 g_assert_not_reached ();
594 if (class1 == class2)
596 else if (class1 == ARG_CLASS_NO_CLASS)
598 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
599 class1 = ARG_CLASS_MEMORY;
600 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
601 class1 = ARG_CLASS_INTEGER;
603 class1 = ARG_CLASS_SSE;
607 #ifdef __native_client_codegen__
609 /* Default alignment for Native Client is 32-byte. */
610 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
612 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
613 /* Check that alignment doesn't cross an alignment boundary. */
615 mono_arch_nacl_pad(guint8 *code, int pad)
617 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
619 if (pad == 0) return code;
620 /* assertion: alignment cannot cross a block boundary */
621 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
622 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
623 while (pad >= kMaxPadding) {
624 amd64_padding (code, kMaxPadding);
627 if (pad != 0) amd64_padding (code, pad);
633 count_fields_nested (MonoClass *klass)
635 MonoMarshalType *info;
638 info = mono_marshal_load_type_info (klass);
641 for (i = 0; i < info->num_fields; ++i) {
642 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
643 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
651 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
653 MonoMarshalType *info;
656 info = mono_marshal_load_type_info (klass);
658 for (i = 0; i < info->num_fields; ++i) {
659 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
660 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
662 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
663 fields [index].offset += offset;
672 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
674 guint32 *gr, guint32 *fr, guint32 *stack_size)
676 guint32 size, i, nfields;
678 ArgumentClass arg_class;
679 MonoMarshalType *info = NULL;
680 MonoMarshalField *fields = NULL;
682 gboolean pass_on_stack = FALSE;
684 klass = mono_class_from_mono_type (type);
685 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
687 pass_on_stack = TRUE;
689 /* If this struct can't be split up naturally into 8-byte */
690 /* chunks (registers), pass it on the stack. */
691 if (sig->pinvoke && !pass_on_stack) {
695 info = mono_marshal_load_type_info (klass);
699 * Collect field information recursively to be able to
700 * handle nested structures.
702 nfields = count_fields_nested (klass);
703 fields = g_new0 (MonoMarshalField, nfields);
704 collect_field_info_nested (klass, fields, 0, 0);
706 for (i = 0; i < nfields; ++i) {
707 field_size = mono_marshal_type_size (fields [i].field->type,
709 &align, TRUE, klass->unicode);
710 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
711 pass_on_stack = TRUE;
718 /* Allways pass in memory */
719 ainfo->offset = *stack_size;
720 *stack_size += ALIGN_TO (size, 8);
721 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
723 ainfo->arg_size = ALIGN_TO (size, 8);
730 int n = mono_class_value_size (klass, NULL);
735 arg_class = ARG_CLASS_MEMORY;
737 /* Always pass in 1 integer register */
738 arg_class = ARG_CLASS_INTEGER;
743 ainfo->storage = ArgValuetypeInReg;
744 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
748 switch (info->native_size) {
749 case 1: case 2: case 4: case 8:
753 ainfo->storage = ArgValuetypeAddrInIReg;
754 ainfo->offset = *stack_size;
755 *stack_size += ALIGN_TO (info->native_size, 8);
758 ainfo->storage = ArgValuetypeAddrInIReg;
760 if (*gr < PARAM_REGS) {
761 ainfo->pair_storage [0] = ArgInIReg;
762 ainfo->pair_regs [0] = param_regs [*gr];
766 ainfo->pair_storage [0] = ArgOnStack;
767 ainfo->offset = *stack_size;
768 ainfo->arg_size = sizeof (mgreg_t);
779 ArgumentClass class1;
782 class1 = ARG_CLASS_MEMORY;
784 class1 = ARG_CLASS_NO_CLASS;
785 for (i = 0; i < nfields; ++i) {
786 size = mono_marshal_type_size (fields [i].field->type,
788 &align, TRUE, klass->unicode);
789 /* How far into this quad this data extends.*/
790 /* (8 is size of quad) */
791 argsize = fields [i].offset + size;
793 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
795 g_assert (class1 != ARG_CLASS_NO_CLASS);
801 /* Allocate registers */
806 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
809 ainfo->storage = ArgValuetypeInReg;
810 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
811 ainfo->pair_size [0] = argsize;
812 ainfo->pair_size [1] = 0;
815 case ARG_CLASS_INTEGER:
816 if (*gr >= PARAM_REGS)
817 arg_class = ARG_CLASS_MEMORY;
819 ainfo->pair_storage [0] = ArgInIReg;
821 ainfo->pair_regs [0] = return_regs [*gr];
823 ainfo->pair_regs [0] = param_regs [*gr];
828 if (*fr >= FLOAT_PARAM_REGS)
829 arg_class = ARG_CLASS_MEMORY;
832 ainfo->pair_storage [0] = ArgInFloatSSEReg;
834 ainfo->pair_storage [0] = ArgInDoubleSSEReg;
835 ainfo->pair_regs [0] = *fr;
839 case ARG_CLASS_MEMORY:
842 g_assert_not_reached ();
845 if (arg_class == ARG_CLASS_MEMORY) {
846 /* Revert possible register assignments */
850 ainfo->offset = *stack_size;
851 *stack_size += sizeof (mgreg_t);
852 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
854 ainfo->arg_size = sizeof (mgreg_t);
858 #endif /* TARGET_WIN32 */
861 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
863 guint32 *gr, guint32 *fr, guint32 *stack_size)
866 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
868 guint32 size, quad, nquads, i, nfields;
869 /* Keep track of the size used in each quad so we can */
870 /* use the right size when copying args/return vars. */
871 guint32 quadsize [2] = {8, 8};
872 ArgumentClass args [2];
873 MonoMarshalType *info = NULL;
874 MonoMarshalField *fields = NULL;
876 gboolean pass_on_stack = FALSE;
878 klass = mono_class_from_mono_type (type);
879 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
880 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
881 /* We pass and return vtypes of size 8 in a register */
882 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
883 pass_on_stack = TRUE;
886 /* If this struct can't be split up naturally into 8-byte */
887 /* chunks (registers), pass it on the stack. */
888 if (sig->pinvoke && !pass_on_stack) {
892 info = mono_marshal_load_type_info (klass);
896 * Collect field information recursively to be able to
897 * handle nested structures.
899 nfields = count_fields_nested (klass);
900 fields = g_new0 (MonoMarshalField, nfields);
901 collect_field_info_nested (klass, fields, 0, 0);
903 for (i = 0; i < nfields; ++i) {
904 field_size = mono_marshal_type_size (fields [i].field->type,
906 &align, TRUE, klass->unicode);
907 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
908 pass_on_stack = TRUE;
915 ainfo->storage = ArgValuetypeInReg;
916 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
921 /* Allways pass in memory */
922 ainfo->offset = *stack_size;
923 *stack_size += ALIGN_TO (size, 8);
924 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
926 ainfo->arg_size = ALIGN_TO (size, 8);
938 int n = mono_class_value_size (klass, NULL);
940 quadsize [0] = n >= 8 ? 8 : n;
941 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
943 /* Always pass in 1 or 2 integer registers */
944 args [0] = ARG_CLASS_INTEGER;
945 args [1] = ARG_CLASS_INTEGER;
946 /* Only the simplest cases are supported */
947 if (is_return && nquads != 1) {
948 args [0] = ARG_CLASS_MEMORY;
949 args [1] = ARG_CLASS_MEMORY;
953 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
954 * The X87 and SSEUP stuff is left out since there are no such types in
960 ainfo->storage = ArgValuetypeInReg;
961 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
965 if (info->native_size > 16) {
966 ainfo->offset = *stack_size;
967 *stack_size += ALIGN_TO (info->native_size, 8);
968 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
970 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
976 args [0] = ARG_CLASS_NO_CLASS;
977 args [1] = ARG_CLASS_NO_CLASS;
978 for (quad = 0; quad < nquads; ++quad) {
981 ArgumentClass class1;
984 class1 = ARG_CLASS_MEMORY;
986 class1 = ARG_CLASS_NO_CLASS;
987 for (i = 0; i < nfields; ++i) {
988 size = mono_marshal_type_size (fields [i].field->type,
990 &align, TRUE, klass->unicode);
991 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
992 /* Unaligned field */
996 /* Skip fields in other quad */
997 if ((quad == 0) && (fields [i].offset >= 8))
999 if ((quad == 1) && (fields [i].offset < 8))
1002 /* How far into this quad this data extends.*/
1003 /* (8 is size of quad) */
1004 quadsize [quad] = fields [i].offset + size - (quad * 8);
1006 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1008 g_assert (class1 != ARG_CLASS_NO_CLASS);
1009 args [quad] = class1;
1015 /* Post merger cleanup */
1016 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1017 args [0] = args [1] = ARG_CLASS_MEMORY;
1019 /* Allocate registers */
1024 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1026 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1029 ainfo->storage = ArgValuetypeInReg;
1030 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1031 g_assert (quadsize [0] <= 8);
1032 g_assert (quadsize [1] <= 8);
1033 ainfo->pair_size [0] = quadsize [0];
1034 ainfo->pair_size [1] = quadsize [1];
1035 ainfo->nregs = nquads;
1036 for (quad = 0; quad < nquads; ++quad) {
1037 switch (args [quad]) {
1038 case ARG_CLASS_INTEGER:
1039 if (*gr >= PARAM_REGS)
1040 args [quad] = ARG_CLASS_MEMORY;
1042 ainfo->pair_storage [quad] = ArgInIReg;
1044 ainfo->pair_regs [quad] = return_regs [*gr];
1046 ainfo->pair_regs [quad] = param_regs [*gr];
1051 if (*fr >= FLOAT_PARAM_REGS)
1052 args [quad] = ARG_CLASS_MEMORY;
1054 if (quadsize[quad] <= 4)
1055 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1056 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1057 ainfo->pair_regs [quad] = *fr;
1061 case ARG_CLASS_MEMORY:
1064 g_assert_not_reached ();
1068 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1070 /* Revert possible register assignments */
1074 ainfo->offset = *stack_size;
1076 arg_size = ALIGN_TO (info->native_size, 8);
1078 arg_size = nquads * sizeof(mgreg_t);
1079 *stack_size += arg_size;
1080 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1082 ainfo->arg_size = arg_size;
1085 #endif /* !TARGET_WIN32 */
1091 * Obtain information about a call according to the calling convention.
1092 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1093 * Draft Version 0.23" document for more information.
1096 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1098 guint32 i, gr, fr, pstart;
1100 int n = sig->hasthis + sig->param_count;
1101 guint32 stack_size = 0;
1103 gboolean is_pinvoke = sig->pinvoke;
1106 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1108 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1116 /* Reserve space where the callee can save the argument registers */
1117 stack_size = 4 * sizeof (mgreg_t);
1121 ret_type = mini_get_underlying_type (sig->ret);
1122 switch (ret_type->type) {
1132 case MONO_TYPE_FNPTR:
1133 case MONO_TYPE_CLASS:
1134 case MONO_TYPE_OBJECT:
1135 case MONO_TYPE_SZARRAY:
1136 case MONO_TYPE_ARRAY:
1137 case MONO_TYPE_STRING:
1138 cinfo->ret.storage = ArgInIReg;
1139 cinfo->ret.reg = AMD64_RAX;
1143 cinfo->ret.storage = ArgInIReg;
1144 cinfo->ret.reg = AMD64_RAX;
1147 cinfo->ret.storage = ArgInFloatSSEReg;
1148 cinfo->ret.reg = AMD64_XMM0;
1151 cinfo->ret.storage = ArgInDoubleSSEReg;
1152 cinfo->ret.reg = AMD64_XMM0;
1154 case MONO_TYPE_GENERICINST:
1155 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1156 cinfo->ret.storage = ArgInIReg;
1157 cinfo->ret.reg = AMD64_RAX;
1160 if (mini_is_gsharedvt_type (ret_type)) {
1161 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1162 cinfo->ret.is_gsharedvt_return_value = 1;
1166 case MONO_TYPE_VALUETYPE:
1167 case MONO_TYPE_TYPEDBYREF: {
1168 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1170 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1171 g_assert (cinfo->ret.storage != ArgInIReg);
1175 case MONO_TYPE_MVAR:
1176 g_assert (mini_is_gsharedvt_type (ret_type));
1177 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1178 cinfo->ret.is_gsharedvt_return_value = 1;
1180 case MONO_TYPE_VOID:
1183 g_error ("Can't handle as return value 0x%x", ret_type->type);
1188 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1189 * the first argument, allowing 'this' to be always passed in the first arg reg.
1190 * Also do this if the first argument is a reference type, since virtual calls
1191 * are sometimes made using calli without sig->hasthis set, like in the delegate
1194 if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1196 add_general (&gr, &stack_size, cinfo->args + 0);
1198 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1201 add_general (&gr, &stack_size, &cinfo->ret);
1202 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1203 cinfo->vret_arg_index = 1;
1207 add_general (&gr, &stack_size, cinfo->args + 0);
1209 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1210 add_general (&gr, &stack_size, &cinfo->ret);
1211 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1215 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1217 fr = FLOAT_PARAM_REGS;
1219 /* Emit the signature cookie just before the implicit arguments */
1220 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1223 for (i = pstart; i < sig->param_count; ++i) {
1224 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1228 /* The float param registers and other param registers must be the same index on Windows x64.*/
1235 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1236 /* We allways pass the sig cookie on the stack for simplicity */
1238 * Prevent implicit arguments + the sig cookie from being passed
1242 fr = FLOAT_PARAM_REGS;
1244 /* Emit the signature cookie just before the implicit arguments */
1245 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1248 ptype = mini_get_underlying_type (sig->params [i]);
1249 switch (ptype->type) {
1252 add_general (&gr, &stack_size, ainfo);
1256 add_general (&gr, &stack_size, ainfo);
1260 add_general (&gr, &stack_size, ainfo);
1265 case MONO_TYPE_FNPTR:
1266 case MONO_TYPE_CLASS:
1267 case MONO_TYPE_OBJECT:
1268 case MONO_TYPE_STRING:
1269 case MONO_TYPE_SZARRAY:
1270 case MONO_TYPE_ARRAY:
1271 add_general (&gr, &stack_size, ainfo);
1273 case MONO_TYPE_GENERICINST:
1274 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1275 add_general (&gr, &stack_size, ainfo);
1278 if (mini_is_gsharedvt_variable_type (ptype)) {
1279 /* gsharedvt arguments are passed by ref */
1280 add_general (&gr, &stack_size, ainfo);
1281 if (ainfo->storage == ArgInIReg)
1282 ainfo->storage = ArgGSharedVtInReg;
1284 ainfo->storage = ArgGSharedVtOnStack;
1288 case MONO_TYPE_VALUETYPE:
1289 case MONO_TYPE_TYPEDBYREF:
1290 add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1295 add_general (&gr, &stack_size, ainfo);
1298 add_float (&fr, &stack_size, ainfo, FALSE);
1301 add_float (&fr, &stack_size, ainfo, TRUE);
1304 case MONO_TYPE_MVAR:
1305 /* gsharedvt arguments are passed by ref */
1306 g_assert (mini_is_gsharedvt_type (ptype));
1307 add_general (&gr, &stack_size, ainfo);
1308 if (ainfo->storage == ArgInIReg)
1309 ainfo->storage = ArgGSharedVtInReg;
1311 ainfo->storage = ArgGSharedVtOnStack;
1314 g_assert_not_reached ();
1318 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1320 fr = FLOAT_PARAM_REGS;
1322 /* Emit the signature cookie just before the implicit arguments */
1323 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1326 cinfo->stack_usage = stack_size;
1327 cinfo->reg_usage = gr;
1328 cinfo->freg_usage = fr;
1333 * mono_arch_get_argument_info:
1334 * @csig: a method signature
1335 * @param_count: the number of parameters to consider
1336 * @arg_info: an array to store the result infos
1338 * Gathers information on parameters such as size, alignment and
1339 * padding. arg_info should be large enought to hold param_count + 1 entries.
1341 * Returns the size of the argument area on the stack.
1344 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1347 CallInfo *cinfo = get_call_info (NULL, csig);
1348 guint32 args_size = cinfo->stack_usage;
1350 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1351 if (csig->hasthis) {
1352 arg_info [0].offset = 0;
1355 for (k = 0; k < param_count; k++) {
1356 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1358 arg_info [k + 1].size = 0;
1367 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1371 MonoType *callee_ret;
1373 c1 = get_call_info (NULL, caller_sig);
1374 c2 = get_call_info (NULL, callee_sig);
1375 res = c1->stack_usage >= c2->stack_usage;
1376 callee_ret = mini_get_underlying_type (callee_sig->ret);
1377 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1378 /* An address on the callee's stack is passed as the first argument */
1388 * Initialize the cpu to execute managed code.
1391 mono_arch_cpu_init (void)
1396 /* spec compliance requires running with double precision */
1397 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1398 fpcw &= ~X86_FPCW_PRECC_MASK;
1399 fpcw |= X86_FPCW_PREC_DOUBLE;
1400 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1401 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1403 /* TODO: This is crashing on Win64 right now.
1404 * _control87 (_PC_53, MCW_PC);
1410 * Initialize architecture specific code.
1413 mono_arch_init (void)
1415 mono_os_mutex_init_recursive (&mini_arch_mutex);
1416 #if defined(__native_client_codegen__)
1417 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1418 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1419 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1420 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1423 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1424 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1425 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1426 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1427 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1428 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1432 bp_trampoline = mini_get_breakpoint_trampoline ();
1436 * Cleanup architecture specific code.
1439 mono_arch_cleanup (void)
1441 mono_os_mutex_destroy (&mini_arch_mutex);
1442 #if defined(__native_client_codegen__)
1443 mono_native_tls_free (nacl_instruction_depth);
1444 mono_native_tls_free (nacl_rex_tag);
1445 mono_native_tls_free (nacl_legacy_prefix_tag);
1450 * This function returns the optimizations supported on this cpu.
1453 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1459 if (mono_hwcap_x86_has_cmov) {
1460 opts |= MONO_OPT_CMOV;
1462 if (mono_hwcap_x86_has_fcmov)
1463 opts |= MONO_OPT_FCMOV;
1465 *exclude_mask |= MONO_OPT_FCMOV;
1467 *exclude_mask |= MONO_OPT_CMOV;
1474 * This function test for all SSE functions supported.
1476 * Returns a bitmask corresponding to all supported versions.
1480 mono_arch_cpu_enumerate_simd_versions (void)
1482 guint32 sse_opts = 0;
1484 if (mono_hwcap_x86_has_sse1)
1485 sse_opts |= SIMD_VERSION_SSE1;
1487 if (mono_hwcap_x86_has_sse2)
1488 sse_opts |= SIMD_VERSION_SSE2;
1490 if (mono_hwcap_x86_has_sse3)
1491 sse_opts |= SIMD_VERSION_SSE3;
1493 if (mono_hwcap_x86_has_ssse3)
1494 sse_opts |= SIMD_VERSION_SSSE3;
1496 if (mono_hwcap_x86_has_sse41)
1497 sse_opts |= SIMD_VERSION_SSE41;
1499 if (mono_hwcap_x86_has_sse42)
1500 sse_opts |= SIMD_VERSION_SSE42;
1502 if (mono_hwcap_x86_has_sse4a)
1503 sse_opts |= SIMD_VERSION_SSE4a;
1511 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1516 for (i = 0; i < cfg->num_varinfo; i++) {
1517 MonoInst *ins = cfg->varinfo [i];
1518 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1521 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1524 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1525 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1528 if (mono_is_regsize_var (ins->inst_vtype)) {
1529 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1530 g_assert (i == vmv->idx);
1531 vars = g_list_prepend (vars, vmv);
1535 vars = mono_varlist_sort (cfg, vars, 0);
1541 * mono_arch_compute_omit_fp:
1543 * Determine whenever the frame pointer can be eliminated.
1546 mono_arch_compute_omit_fp (MonoCompile *cfg)
1548 MonoMethodSignature *sig;
1549 MonoMethodHeader *header;
1553 if (cfg->arch.omit_fp_computed)
1556 header = cfg->header;
1558 sig = mono_method_signature (cfg->method);
1560 if (!cfg->arch.cinfo)
1561 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1562 cinfo = (CallInfo *)cfg->arch.cinfo;
1565 * FIXME: Remove some of the restrictions.
1567 cfg->arch.omit_fp = TRUE;
1568 cfg->arch.omit_fp_computed = TRUE;
1570 #ifdef __native_client_codegen__
1571 /* NaCl modules may not change the value of RBP, so it cannot be */
1572 /* used as a normal register, but it can be used as a frame pointer*/
1573 cfg->disable_omit_fp = TRUE;
1574 cfg->arch.omit_fp = FALSE;
1577 if (cfg->disable_omit_fp)
1578 cfg->arch.omit_fp = FALSE;
1580 if (!debug_omit_fp ())
1581 cfg->arch.omit_fp = FALSE;
1583 if (cfg->method->save_lmf)
1584 cfg->arch.omit_fp = FALSE;
1586 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1587 cfg->arch.omit_fp = FALSE;
1588 if (header->num_clauses)
1589 cfg->arch.omit_fp = FALSE;
1590 if (cfg->param_area)
1591 cfg->arch.omit_fp = FALSE;
1592 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1593 cfg->arch.omit_fp = FALSE;
1594 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1595 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1596 cfg->arch.omit_fp = FALSE;
1597 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1598 ArgInfo *ainfo = &cinfo->args [i];
1600 if (ainfo->storage == ArgOnStack) {
1602 * The stack offset can only be determined when the frame
1605 cfg->arch.omit_fp = FALSE;
1610 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1611 MonoInst *ins = cfg->varinfo [i];
1614 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1619 mono_arch_get_global_int_regs (MonoCompile *cfg)
1623 mono_arch_compute_omit_fp (cfg);
1625 if (cfg->arch.omit_fp)
1626 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1628 /* We use the callee saved registers for global allocation */
1629 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1630 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1631 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1632 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1633 #ifndef __native_client_codegen__
1634 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1637 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1638 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1645 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1650 /* All XMM registers */
1651 for (i = 0; i < 16; ++i)
1652 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1658 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1660 static GList *r = NULL;
1665 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1666 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1667 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1668 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1669 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1670 #ifndef __native_client_codegen__
1671 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1674 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1675 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1676 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1677 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1678 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1679 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1680 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1681 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1683 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1690 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1693 static GList *r = NULL;
1698 for (i = 0; i < AMD64_XMM_NREG; ++i)
1699 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1701 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1708 * mono_arch_regalloc_cost:
1710 * Return the cost, in number of memory references, of the action of
1711 * allocating the variable VMV into a register during global register
1715 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1717 MonoInst *ins = cfg->varinfo [vmv->idx];
1719 if (cfg->method->save_lmf)
1720 /* The register is already saved */
1721 /* substract 1 for the invisible store in the prolog */
1722 return (ins->opcode == OP_ARG) ? 0 : 1;
1725 return (ins->opcode == OP_ARG) ? 1 : 2;
1729 * mono_arch_fill_argument_info:
1731 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1735 mono_arch_fill_argument_info (MonoCompile *cfg)
1738 MonoMethodSignature *sig;
1743 sig = mono_method_signature (cfg->method);
1745 cinfo = (CallInfo *)cfg->arch.cinfo;
1746 sig_ret = mini_get_underlying_type (sig->ret);
1749 * Contrary to mono_arch_allocate_vars (), the information should describe
1750 * where the arguments are at the beginning of the method, not where they can be
1751 * accessed during the execution of the method. The later makes no sense for the
1752 * global register allocator, since a variable can be in more than one location.
1754 switch (cinfo->ret.storage) {
1756 case ArgInFloatSSEReg:
1757 case ArgInDoubleSSEReg:
1758 cfg->ret->opcode = OP_REGVAR;
1759 cfg->ret->inst_c0 = cinfo->ret.reg;
1761 case ArgValuetypeInReg:
1762 cfg->ret->opcode = OP_REGOFFSET;
1763 cfg->ret->inst_basereg = -1;
1764 cfg->ret->inst_offset = -1;
1769 g_assert_not_reached ();
1772 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1773 ArgInfo *ainfo = &cinfo->args [i];
1775 ins = cfg->args [i];
1777 switch (ainfo->storage) {
1779 case ArgInFloatSSEReg:
1780 case ArgInDoubleSSEReg:
1781 ins->opcode = OP_REGVAR;
1782 ins->inst_c0 = ainfo->reg;
1785 ins->opcode = OP_REGOFFSET;
1786 ins->inst_basereg = -1;
1787 ins->inst_offset = -1;
1789 case ArgValuetypeInReg:
1791 ins->opcode = OP_NOP;
1794 g_assert_not_reached ();
1800 mono_arch_allocate_vars (MonoCompile *cfg)
1803 MonoMethodSignature *sig;
1806 guint32 locals_stack_size, locals_stack_align;
1810 sig = mono_method_signature (cfg->method);
1812 cinfo = (CallInfo *)cfg->arch.cinfo;
1813 sig_ret = mini_get_underlying_type (sig->ret);
1815 mono_arch_compute_omit_fp (cfg);
1818 * We use the ABI calling conventions for managed code as well.
1819 * Exception: valuetypes are only sometimes passed or returned in registers.
1823 * The stack looks like this:
1824 * <incoming arguments passed on the stack>
1826 * <lmf/caller saved registers>
1829 * <localloc area> -> grows dynamically
1833 if (cfg->arch.omit_fp) {
1834 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1835 cfg->frame_reg = AMD64_RSP;
1838 /* Locals are allocated backwards from %fp */
1839 cfg->frame_reg = AMD64_RBP;
1843 cfg->arch.saved_iregs = cfg->used_int_regs;
1844 if (cfg->method->save_lmf)
1845 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1846 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1848 if (cfg->arch.omit_fp)
1849 cfg->arch.reg_save_area_offset = offset;
1850 /* Reserve space for callee saved registers */
1851 for (i = 0; i < AMD64_NREG; ++i)
1852 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1853 offset += sizeof(mgreg_t);
1855 if (!cfg->arch.omit_fp)
1856 cfg->arch.reg_save_area_offset = -offset;
1858 if (sig_ret->type != MONO_TYPE_VOID) {
1859 switch (cinfo->ret.storage) {
1861 case ArgInFloatSSEReg:
1862 case ArgInDoubleSSEReg:
1863 cfg->ret->opcode = OP_REGVAR;
1864 cfg->ret->inst_c0 = cinfo->ret.reg;
1865 cfg->ret->dreg = cinfo->ret.reg;
1867 case ArgValuetypeAddrInIReg:
1868 /* The register is volatile */
1869 cfg->vret_addr->opcode = OP_REGOFFSET;
1870 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1871 if (cfg->arch.omit_fp) {
1872 cfg->vret_addr->inst_offset = offset;
1876 cfg->vret_addr->inst_offset = -offset;
1878 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1879 printf ("vret_addr =");
1880 mono_print_ins (cfg->vret_addr);
1883 case ArgValuetypeInReg:
1884 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1885 cfg->ret->opcode = OP_REGOFFSET;
1886 cfg->ret->inst_basereg = cfg->frame_reg;
1887 if (cfg->arch.omit_fp) {
1888 cfg->ret->inst_offset = offset;
1889 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1891 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1892 cfg->ret->inst_offset = - offset;
1896 g_assert_not_reached ();
1900 /* Allocate locals */
1901 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1902 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1903 char *mname = mono_method_full_name (cfg->method, TRUE);
1904 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1909 if (locals_stack_align) {
1910 offset += (locals_stack_align - 1);
1911 offset &= ~(locals_stack_align - 1);
1913 if (cfg->arch.omit_fp) {
1914 cfg->locals_min_stack_offset = offset;
1915 cfg->locals_max_stack_offset = offset + locals_stack_size;
1917 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1918 cfg->locals_max_stack_offset = - offset;
1921 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1922 if (offsets [i] != -1) {
1923 MonoInst *ins = cfg->varinfo [i];
1924 ins->opcode = OP_REGOFFSET;
1925 ins->inst_basereg = cfg->frame_reg;
1926 if (cfg->arch.omit_fp)
1927 ins->inst_offset = (offset + offsets [i]);
1929 ins->inst_offset = - (offset + offsets [i]);
1930 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1933 offset += locals_stack_size;
1935 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1936 g_assert (!cfg->arch.omit_fp);
1937 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1938 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1941 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1942 ins = cfg->args [i];
1943 if (ins->opcode != OP_REGVAR) {
1944 ArgInfo *ainfo = &cinfo->args [i];
1945 gboolean inreg = TRUE;
1947 /* FIXME: Allocate volatile arguments to registers */
1948 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1952 * Under AMD64, all registers used to pass arguments to functions
1953 * are volatile across calls.
1954 * FIXME: Optimize this.
1956 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1959 ins->opcode = OP_REGOFFSET;
1961 switch (ainfo->storage) {
1963 case ArgInFloatSSEReg:
1964 case ArgInDoubleSSEReg:
1965 case ArgGSharedVtInReg:
1967 ins->opcode = OP_REGVAR;
1968 ins->dreg = ainfo->reg;
1972 case ArgGSharedVtOnStack:
1973 g_assert (!cfg->arch.omit_fp);
1974 ins->opcode = OP_REGOFFSET;
1975 ins->inst_basereg = cfg->frame_reg;
1976 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1978 case ArgValuetypeInReg:
1980 case ArgValuetypeAddrInIReg: {
1982 g_assert (!cfg->arch.omit_fp);
1984 MONO_INST_NEW (cfg, indir, 0);
1985 indir->opcode = OP_REGOFFSET;
1986 if (ainfo->pair_storage [0] == ArgInIReg) {
1987 indir->inst_basereg = cfg->frame_reg;
1988 offset = ALIGN_TO (offset, sizeof (gpointer));
1989 offset += (sizeof (gpointer));
1990 indir->inst_offset = - offset;
1993 indir->inst_basereg = cfg->frame_reg;
1994 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1997 ins->opcode = OP_VTARG_ADDR;
1998 ins->inst_left = indir;
2006 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2007 ins->opcode = OP_REGOFFSET;
2008 ins->inst_basereg = cfg->frame_reg;
2009 /* These arguments are saved to the stack in the prolog */
2010 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2011 if (cfg->arch.omit_fp) {
2012 ins->inst_offset = offset;
2013 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2014 // Arguments are yet supported by the stack map creation code
2015 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2017 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2018 ins->inst_offset = - offset;
2019 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2025 cfg->stack_offset = offset;
2029 mono_arch_create_vars (MonoCompile *cfg)
2031 MonoMethodSignature *sig;
2035 sig = mono_method_signature (cfg->method);
2037 if (!cfg->arch.cinfo)
2038 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2039 cinfo = (CallInfo *)cfg->arch.cinfo;
2041 if (cinfo->ret.storage == ArgValuetypeInReg)
2042 cfg->ret_var_is_local = TRUE;
2044 sig_ret = mini_get_underlying_type (sig->ret);
2045 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2046 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2047 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2048 printf ("vret_addr = ");
2049 mono_print_ins (cfg->vret_addr);
2053 if (cfg->gen_sdb_seq_points) {
2056 if (cfg->compile_aot) {
2057 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2058 ins->flags |= MONO_INST_VOLATILE;
2059 cfg->arch.seq_point_info_var = ins;
2061 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2062 ins->flags |= MONO_INST_VOLATILE;
2063 cfg->arch.ss_tramp_var = ins;
2065 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2066 ins->flags |= MONO_INST_VOLATILE;
2067 cfg->arch.bp_tramp_var = ins;
2070 if (cfg->method->save_lmf)
2071 cfg->create_lmf_var = TRUE;
2073 if (cfg->method->save_lmf) {
2075 #if !defined(TARGET_WIN32)
2076 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2077 cfg->lmf_ir_mono_lmf = TRUE;
2083 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2089 MONO_INST_NEW (cfg, ins, OP_MOVE);
2090 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2091 ins->sreg1 = tree->dreg;
2092 MONO_ADD_INS (cfg->cbb, ins);
2093 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2095 case ArgInFloatSSEReg:
2096 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2097 ins->dreg = mono_alloc_freg (cfg);
2098 ins->sreg1 = tree->dreg;
2099 MONO_ADD_INS (cfg->cbb, ins);
2101 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2103 case ArgInDoubleSSEReg:
2104 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2105 ins->dreg = mono_alloc_freg (cfg);
2106 ins->sreg1 = tree->dreg;
2107 MONO_ADD_INS (cfg->cbb, ins);
2109 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2113 g_assert_not_reached ();
2118 arg_storage_to_load_membase (ArgStorage storage)
2122 #if defined(__mono_ilp32__)
2123 return OP_LOADI8_MEMBASE;
2125 return OP_LOAD_MEMBASE;
2127 case ArgInDoubleSSEReg:
2128 return OP_LOADR8_MEMBASE;
2129 case ArgInFloatSSEReg:
2130 return OP_LOADR4_MEMBASE;
2132 g_assert_not_reached ();
2139 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2141 MonoMethodSignature *tmp_sig;
2144 if (call->tail_call)
2147 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2150 * mono_ArgIterator_Setup assumes the signature cookie is
2151 * passed first and all the arguments which were before it are
2152 * passed on the stack after the signature. So compensate by
2153 * passing a different signature.
2155 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2156 tmp_sig->param_count -= call->signature->sentinelpos;
2157 tmp_sig->sentinelpos = 0;
2158 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2160 sig_reg = mono_alloc_ireg (cfg);
2161 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2163 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2167 static inline LLVMArgStorage
2168 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2172 return LLVMArgInIReg;
2175 case ArgGSharedVtInReg:
2176 case ArgGSharedVtOnStack:
2177 return LLVMArgGSharedVt;
2179 g_assert_not_reached ();
2185 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2191 LLVMCallInfo *linfo;
2192 MonoType *t, *sig_ret;
2194 n = sig->param_count + sig->hasthis;
2195 sig_ret = mini_get_underlying_type (sig->ret);
2197 cinfo = get_call_info (cfg->mempool, sig);
2199 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2202 * LLVM always uses the native ABI while we use our own ABI, the
2203 * only difference is the handling of vtypes:
2204 * - we only pass/receive them in registers in some cases, and only
2205 * in 1 or 2 integer registers.
2207 switch (cinfo->ret.storage) {
2209 linfo->ret.storage = LLVMArgNone;
2212 case ArgInFloatSSEReg:
2213 case ArgInDoubleSSEReg:
2214 linfo->ret.storage = LLVMArgNormal;
2216 case ArgValuetypeInReg: {
2217 ainfo = &cinfo->ret;
2220 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2221 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2222 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2223 cfg->disable_llvm = TRUE;
2227 linfo->ret.storage = LLVMArgVtypeInReg;
2228 for (j = 0; j < 2; ++j)
2229 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2232 case ArgValuetypeAddrInIReg:
2233 /* Vtype returned using a hidden argument */
2234 linfo->ret.storage = LLVMArgVtypeRetAddr;
2235 linfo->vret_arg_index = cinfo->vret_arg_index;
2238 g_assert_not_reached ();
2242 for (i = 0; i < n; ++i) {
2243 ainfo = cinfo->args + i;
2245 if (i >= sig->hasthis)
2246 t = sig->params [i - sig->hasthis];
2248 t = &mono_defaults.int_class->byval_arg;
2250 linfo->args [i].storage = LLVMArgNone;
2252 switch (ainfo->storage) {
2254 linfo->args [i].storage = LLVMArgNormal;
2256 case ArgInDoubleSSEReg:
2257 case ArgInFloatSSEReg:
2258 linfo->args [i].storage = LLVMArgNormal;
2261 if (MONO_TYPE_ISSTRUCT (t))
2262 linfo->args [i].storage = LLVMArgVtypeByVal;
2264 linfo->args [i].storage = LLVMArgNormal;
2266 case ArgValuetypeInReg:
2268 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2269 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2270 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2271 cfg->disable_llvm = TRUE;
2275 linfo->args [i].storage = LLVMArgVtypeInReg;
2276 for (j = 0; j < 2; ++j)
2277 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2279 case ArgGSharedVtInReg:
2280 case ArgGSharedVtOnStack:
2281 linfo->args [i].storage = LLVMArgGSharedVt;
2284 cfg->exception_message = g_strdup ("ainfo->storage");
2285 cfg->disable_llvm = TRUE;
2295 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2298 MonoMethodSignature *sig;
2304 sig = call->signature;
2305 n = sig->param_count + sig->hasthis;
2307 cinfo = get_call_info (cfg->mempool, sig);
2311 if (COMPILE_LLVM (cfg)) {
2312 /* We shouldn't be called in the llvm case */
2313 cfg->disable_llvm = TRUE;
2318 * Emit all arguments which are passed on the stack to prevent register
2319 * allocation problems.
2321 for (i = 0; i < n; ++i) {
2323 ainfo = cinfo->args + i;
2325 in = call->args [i];
2327 if (sig->hasthis && i == 0)
2328 t = &mono_defaults.object_class->byval_arg;
2330 t = sig->params [i - sig->hasthis];
2332 t = mini_get_underlying_type (t);
2333 //XXX what about ArgGSharedVtOnStack here?
2334 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2336 if (t->type == MONO_TYPE_R4)
2337 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2338 else if (t->type == MONO_TYPE_R8)
2339 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2341 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2345 if (cfg->compute_gc_maps) {
2348 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2354 * Emit all parameters passed in registers in non-reverse order for better readability
2355 * and to help the optimization in emit_prolog ().
2357 for (i = 0; i < n; ++i) {
2358 ainfo = cinfo->args + i;
2360 in = call->args [i];
2362 if (ainfo->storage == ArgInIReg)
2363 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2366 for (i = n - 1; i >= 0; --i) {
2369 ainfo = cinfo->args + i;
2371 in = call->args [i];
2373 if (sig->hasthis && i == 0)
2374 t = &mono_defaults.object_class->byval_arg;
2376 t = sig->params [i - sig->hasthis];
2377 t = mini_get_underlying_type (t);
2379 switch (ainfo->storage) {
2383 case ArgInFloatSSEReg:
2384 case ArgInDoubleSSEReg:
2385 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2388 case ArgValuetypeInReg:
2389 case ArgValuetypeAddrInIReg:
2390 case ArgGSharedVtInReg:
2391 case ArgGSharedVtOnStack: {
2392 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2393 /* Already emitted above */
2395 //FIXME what about ArgGSharedVtOnStack ?
2396 if (ainfo->storage == ArgOnStack && call->tail_call) {
2397 MonoInst *call_inst = (MonoInst*)call;
2398 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2399 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2407 size = mono_type_native_stack_size (t, &align);
2410 * Other backends use mono_type_stack_size (), but that
2411 * aligns the size to 8, which is larger than the size of
2412 * the source, leading to reads of invalid memory if the
2413 * source is at the end of address space.
2415 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2418 if (size >= 10000) {
2419 /* Avoid asserts in emit_memcpy () */
2420 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2421 /* Continue normally */
2425 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2426 arg->sreg1 = in->dreg;
2427 arg->klass = mono_class_from_mono_type (t);
2428 arg->backend.size = size;
2429 arg->inst_p0 = call;
2430 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2431 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2433 MONO_ADD_INS (cfg->cbb, arg);
2438 g_assert_not_reached ();
2441 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2442 /* Emit the signature cookie just before the implicit arguments */
2443 emit_sig_cookie (cfg, call, cinfo);
2446 /* Handle the case where there are no implicit arguments */
2447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2448 emit_sig_cookie (cfg, call, cinfo);
2450 switch (cinfo->ret.storage) {
2451 case ArgValuetypeInReg:
2452 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2454 * Tell the JIT to use a more efficient calling convention: call using
2455 * OP_CALL, compute the result location after the call, and save the
2458 call->vret_in_reg = TRUE;
2460 * Nullify the instruction computing the vret addr to enable
2461 * future optimizations.
2464 NULLIFY_INS (call->vret_var);
2466 if (call->tail_call)
2469 * The valuetype is in RAX:RDX after the call, need to be copied to
2470 * the stack. Push the address here, so the call instruction can
2473 if (!cfg->arch.vret_addr_loc) {
2474 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2475 /* Prevent it from being register allocated or optimized away */
2476 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2479 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2482 case ArgValuetypeAddrInIReg: {
2484 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2485 vtarg->sreg1 = call->vret_var->dreg;
2486 vtarg->dreg = mono_alloc_preg (cfg);
2487 MONO_ADD_INS (cfg->cbb, vtarg);
2489 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2496 if (cfg->method->save_lmf) {
2497 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2498 MONO_ADD_INS (cfg->cbb, arg);
2501 call->stack_usage = cinfo->stack_usage;
2505 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2508 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2509 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2510 int size = ins->backend.size;
2512 switch (ainfo->storage) {
2513 case ArgValuetypeInReg: {
2517 for (part = 0; part < 2; ++part) {
2518 if (ainfo->pair_storage [part] == ArgNone)
2521 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2522 load->inst_basereg = src->dreg;
2523 load->inst_offset = part * sizeof(mgreg_t);
2525 switch (ainfo->pair_storage [part]) {
2527 load->dreg = mono_alloc_ireg (cfg);
2529 case ArgInDoubleSSEReg:
2530 case ArgInFloatSSEReg:
2531 load->dreg = mono_alloc_freg (cfg);
2534 g_assert_not_reached ();
2536 MONO_ADD_INS (cfg->cbb, load);
2538 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2542 case ArgValuetypeAddrInIReg: {
2543 MonoInst *vtaddr, *load;
2544 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2546 MONO_INST_NEW (cfg, load, OP_LDADDR);
2547 cfg->has_indirection = TRUE;
2548 load->inst_p0 = vtaddr;
2549 vtaddr->flags |= MONO_INST_INDIRECT;
2550 load->type = STACK_MP;
2551 load->klass = vtaddr->klass;
2552 load->dreg = mono_alloc_ireg (cfg);
2553 MONO_ADD_INS (cfg->cbb, load);
2554 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2556 if (ainfo->pair_storage [0] == ArgInIReg) {
2557 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2558 arg->dreg = mono_alloc_ireg (cfg);
2559 arg->sreg1 = load->dreg;
2561 MONO_ADD_INS (cfg->cbb, arg);
2562 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2564 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2568 case ArgGSharedVtInReg:
2570 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2572 case ArgGSharedVtOnStack:
2573 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2577 int dreg = mono_alloc_ireg (cfg);
2579 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2580 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2581 } else if (size <= 40) {
2582 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2584 // FIXME: Code growth
2585 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2588 if (cfg->compute_gc_maps) {
2590 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2596 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2598 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2600 if (ret->type == MONO_TYPE_R4) {
2601 if (COMPILE_LLVM (cfg))
2602 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2604 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2606 } else if (ret->type == MONO_TYPE_R8) {
2607 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2611 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2614 #endif /* DISABLE_JIT */
2616 #define EMIT_COND_BRANCH(ins,cond,sign) \
2617 if (ins->inst_true_bb->native_offset) { \
2618 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2620 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2621 if ((cfg->opt & MONO_OPT_BRANCH) && \
2622 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2623 x86_branch8 (code, cond, 0, sign); \
2625 x86_branch32 (code, cond, 0, sign); \
2629 MonoMethodSignature *sig;
2634 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2642 switch (cinfo->ret.storage) {
2645 case ArgInFloatSSEReg:
2646 case ArgInDoubleSSEReg:
2648 case ArgValuetypeInReg: {
2649 ArgInfo *ainfo = &cinfo->ret;
2651 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2653 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2661 for (i = 0; i < cinfo->nargs; ++i) {
2662 ArgInfo *ainfo = &cinfo->args [i];
2663 switch (ainfo->storage) {
2665 case ArgInFloatSSEReg:
2666 case ArgInDoubleSSEReg:
2668 case ArgValuetypeInReg:
2669 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2671 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2683 * mono_arch_dyn_call_prepare:
2685 * Return a pointer to an arch-specific structure which contains information
2686 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2687 * supported for SIG.
2688 * This function is equivalent to ffi_prep_cif in libffi.
2691 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2693 ArchDynCallInfo *info;
2696 cinfo = get_call_info (NULL, sig);
2698 if (!dyn_call_supported (sig, cinfo)) {
2703 info = g_new0 (ArchDynCallInfo, 1);
2704 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2706 info->cinfo = cinfo;
2708 return (MonoDynCallInfo*)info;
2712 * mono_arch_dyn_call_free:
2714 * Free a MonoDynCallInfo structure.
2717 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2719 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2721 g_free (ainfo->cinfo);
2725 #if !defined(__native_client__)
2726 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2727 #define GREG_TO_PTR(greg) (gpointer)(greg)
2729 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2730 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2731 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2735 * mono_arch_get_start_dyn_call:
2737 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2738 * store the result into BUF.
2739 * ARGS should be an array of pointers pointing to the arguments.
2740 * RET should point to a memory buffer large enought to hold the result of the
2742 * This function should be as fast as possible, any work which does not depend
2743 * on the actual values of the arguments should be done in
2744 * mono_arch_dyn_call_prepare ().
2745 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2749 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2751 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2752 DynCallArgs *p = (DynCallArgs*)buf;
2753 int arg_index, greg, freg, i, pindex;
2754 MonoMethodSignature *sig = dinfo->sig;
2755 int buffer_offset = 0;
2757 g_assert (buf_len >= sizeof (DynCallArgs));
2767 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2768 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2773 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2774 p->regs [greg ++] = PTR_TO_GREG(ret);
2776 for (i = pindex; i < sig->param_count; i++) {
2777 MonoType *t = mini_get_underlying_type (sig->params [i]);
2778 gpointer *arg = args [arg_index ++];
2781 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2786 case MONO_TYPE_STRING:
2787 case MONO_TYPE_CLASS:
2788 case MONO_TYPE_ARRAY:
2789 case MONO_TYPE_SZARRAY:
2790 case MONO_TYPE_OBJECT:
2794 #if !defined(__mono_ilp32__)
2798 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2799 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2801 #if defined(__mono_ilp32__)
2804 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2805 p->regs [greg ++] = *(guint64*)(arg);
2809 p->regs [greg ++] = *(guint8*)(arg);
2812 p->regs [greg ++] = *(gint8*)(arg);
2815 p->regs [greg ++] = *(gint16*)(arg);
2818 p->regs [greg ++] = *(guint16*)(arg);
2821 p->regs [greg ++] = *(gint32*)(arg);
2824 p->regs [greg ++] = *(guint32*)(arg);
2826 case MONO_TYPE_R4: {
2829 *(float*)&d = *(float*)(arg);
2831 p->fregs [freg ++] = d;
2836 p->fregs [freg ++] = *(double*)(arg);
2838 case MONO_TYPE_GENERICINST:
2839 if (MONO_TYPE_IS_REFERENCE (t)) {
2840 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2842 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2843 MonoClass *klass = mono_class_from_mono_type (t);
2844 guint8 *nullable_buf;
2847 size = mono_class_value_size (klass, NULL);
2848 nullable_buf = p->buffer + buffer_offset;
2849 buffer_offset += size;
2850 g_assert (buffer_offset <= 256);
2852 /* The argument pointed to by arg is either a boxed vtype or null */
2853 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2855 arg = (gpointer*)nullable_buf;
2861 case MONO_TYPE_VALUETYPE: {
2862 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2864 g_assert (ainfo->storage == ArgValuetypeInReg);
2865 if (ainfo->pair_storage [0] != ArgNone) {
2866 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2867 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2869 if (ainfo->pair_storage [1] != ArgNone) {
2870 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2871 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2876 g_assert_not_reached ();
2880 g_assert (greg <= PARAM_REGS);
2884 * mono_arch_finish_dyn_call:
2886 * Store the result of a dyn call into the return value buffer passed to
2887 * start_dyn_call ().
2888 * This function should be as fast as possible, any work which does not depend
2889 * on the actual values of the arguments should be done in
2890 * mono_arch_dyn_call_prepare ().
2893 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2895 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2896 MonoMethodSignature *sig = dinfo->sig;
2897 DynCallArgs *dargs = (DynCallArgs*)buf;
2898 guint8 *ret = dargs->ret;
2899 mgreg_t res = dargs->res;
2900 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2902 switch (sig_ret->type) {
2903 case MONO_TYPE_VOID:
2904 *(gpointer*)ret = NULL;
2906 case MONO_TYPE_STRING:
2907 case MONO_TYPE_CLASS:
2908 case MONO_TYPE_ARRAY:
2909 case MONO_TYPE_SZARRAY:
2910 case MONO_TYPE_OBJECT:
2914 *(gpointer*)ret = GREG_TO_PTR(res);
2920 *(guint8*)ret = res;
2923 *(gint16*)ret = res;
2926 *(guint16*)ret = res;
2929 *(gint32*)ret = res;
2932 *(guint32*)ret = res;
2935 *(gint64*)ret = res;
2938 *(guint64*)ret = res;
2941 *(float*)ret = *(float*)&(dargs->fregs [0]);
2944 *(double*)ret = dargs->fregs [0];
2946 case MONO_TYPE_GENERICINST:
2947 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2948 *(gpointer*)ret = GREG_TO_PTR(res);
2953 case MONO_TYPE_VALUETYPE:
2954 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2957 ArgInfo *ainfo = &dinfo->cinfo->ret;
2959 g_assert (ainfo->storage == ArgValuetypeInReg);
2961 if (ainfo->pair_storage [0] != ArgNone) {
2962 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2963 ((mgreg_t*)ret)[0] = res;
2966 g_assert (ainfo->pair_storage [1] == ArgNone);
2970 g_assert_not_reached ();
2974 /* emit an exception if condition is fail */
2975 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2977 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2978 if (tins == NULL) { \
2979 mono_add_patch_info (cfg, code - cfg->native_code, \
2980 MONO_PATCH_INFO_EXC, exc_name); \
2981 x86_branch32 (code, cond, 0, signed); \
2983 EMIT_COND_BRANCH (tins, cond, signed); \
2987 #define EMIT_FPCOMPARE(code) do { \
2988 amd64_fcompp (code); \
2989 amd64_fnstsw (code); \
2992 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2993 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2994 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2995 amd64_ ##op (code); \
2996 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2997 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3001 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3003 gboolean no_patch = FALSE;
3006 * FIXME: Add support for thunks
3009 gboolean near_call = FALSE;
3012 * Indirect calls are expensive so try to make a near call if possible.
3013 * The caller memory is allocated by the code manager so it is
3014 * guaranteed to be at a 32 bit offset.
3017 if (patch_type != MONO_PATCH_INFO_ABS) {
3018 /* The target is in memory allocated using the code manager */
3021 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3022 if (((MonoMethod*)data)->klass->image->aot_module)
3023 /* The callee might be an AOT method */
3025 if (((MonoMethod*)data)->dynamic)
3026 /* The target is in malloc-ed memory */
3030 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3032 * The call might go directly to a native function without
3035 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3037 gconstpointer target = mono_icall_get_wrapper (mi);
3038 if ((((guint64)target) >> 32) != 0)
3044 MonoJumpInfo *jinfo = NULL;
3046 if (cfg->abs_patches)
3047 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3049 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3050 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3051 if (mi && (((guint64)mi->func) >> 32) == 0)
3056 * This is not really an optimization, but required because the
3057 * generic class init trampolines use R11 to pass the vtable.
3062 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3064 if (info->func == info->wrapper) {
3066 if ((((guint64)info->func) >> 32) == 0)
3070 /* See the comment in mono_codegen () */
3071 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3075 else if ((((guint64)data) >> 32) == 0) {
3082 if (cfg->method->dynamic)
3083 /* These methods are allocated using malloc */
3086 #ifdef MONO_ARCH_NOMAP32BIT
3089 #if defined(__native_client__)
3090 /* Always use near_call == TRUE for Native Client */
3093 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3094 if (optimize_for_xen)
3097 if (cfg->compile_aot) {
3104 * Align the call displacement to an address divisible by 4 so it does
3105 * not span cache lines. This is required for code patching to work on SMP
3108 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3109 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3110 amd64_padding (code, pad_size);
3112 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3113 amd64_call_code (code, 0);
3116 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3117 amd64_set_reg_template (code, GP_SCRATCH_REG);
3118 amd64_call_reg (code, GP_SCRATCH_REG);
3125 static inline guint8*
3126 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3129 if (win64_adjust_stack)
3130 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3132 code = emit_call_body (cfg, code, patch_type, data);
3134 if (win64_adjust_stack)
3135 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3142 store_membase_imm_to_store_membase_reg (int opcode)
3145 case OP_STORE_MEMBASE_IMM:
3146 return OP_STORE_MEMBASE_REG;
3147 case OP_STOREI4_MEMBASE_IMM:
3148 return OP_STOREI4_MEMBASE_REG;
3149 case OP_STOREI8_MEMBASE_IMM:
3150 return OP_STOREI8_MEMBASE_REG;
3158 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3161 * mono_arch_peephole_pass_1:
3163 * Perform peephole opts which should/can be performed before local regalloc
3166 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3170 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3171 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3173 switch (ins->opcode) {
3177 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3179 * X86_LEA is like ADD, but doesn't have the
3180 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3181 * its operand to 64 bit.
3183 ins->opcode = OP_X86_LEA_MEMBASE;
3184 ins->inst_basereg = ins->sreg1;
3189 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3193 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3194 * the latter has length 2-3 instead of 6 (reverse constant
3195 * propagation). These instruction sequences are very common
3196 * in the initlocals bblock.
3198 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3199 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3200 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3201 ins2->sreg1 = ins->dreg;
3202 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3204 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3207 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3215 case OP_COMPARE_IMM:
3216 case OP_LCOMPARE_IMM:
3217 /* OP_COMPARE_IMM (reg, 0)
3219 * OP_AMD64_TEST_NULL (reg)
3222 ins->opcode = OP_AMD64_TEST_NULL;
3224 case OP_ICOMPARE_IMM:
3226 ins->opcode = OP_X86_TEST_NULL;
3228 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3230 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3231 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3233 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3234 * OP_COMPARE_IMM reg, imm
3236 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3238 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3239 ins->inst_basereg == last_ins->inst_destbasereg &&
3240 ins->inst_offset == last_ins->inst_offset) {
3241 ins->opcode = OP_ICOMPARE_IMM;
3242 ins->sreg1 = last_ins->sreg1;
3244 /* check if we can remove cmp reg,0 with test null */
3246 ins->opcode = OP_X86_TEST_NULL;
3252 mono_peephole_ins (bb, ins);
3257 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3261 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3262 switch (ins->opcode) {
3265 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3266 /* reg = 0 -> XOR (reg, reg) */
3267 /* XOR sets cflags on x86, so we cant do it always */
3268 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3269 ins->opcode = OP_LXOR;
3270 ins->sreg1 = ins->dreg;
3271 ins->sreg2 = ins->dreg;
3279 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3280 * 0 result into 64 bits.
3282 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3283 ins->opcode = OP_IXOR;
3287 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3291 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3292 * the latter has length 2-3 instead of 6 (reverse constant
3293 * propagation). These instruction sequences are very common
3294 * in the initlocals bblock.
3296 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3297 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3298 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3299 ins2->sreg1 = ins->dreg;
3300 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3302 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3305 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3314 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3315 ins->opcode = OP_X86_INC_REG;
3318 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3319 ins->opcode = OP_X86_DEC_REG;
3323 mono_peephole_ins (bb, ins);
3327 #define NEW_INS(cfg,ins,dest,op) do { \
3328 MONO_INST_NEW ((cfg), (dest), (op)); \
3329 (dest)->cil_code = (ins)->cil_code; \
3330 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3334 * mono_arch_lowering_pass:
3336 * Converts complex opcodes into simpler ones so that each IR instruction
3337 * corresponds to one machine instruction.
3340 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3342 MonoInst *ins, *n, *temp;
3345 * FIXME: Need to add more instructions, but the current machine
3346 * description can't model some parts of the composite instructions like
3349 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3350 switch (ins->opcode) {
3354 case OP_IDIV_UN_IMM:
3355 case OP_IREM_UN_IMM:
3358 mono_decompose_op_imm (cfg, bb, ins);
3360 case OP_COMPARE_IMM:
3361 case OP_LCOMPARE_IMM:
3362 if (!amd64_use_imm32 (ins->inst_imm)) {
3363 NEW_INS (cfg, ins, temp, OP_I8CONST);
3364 temp->inst_c0 = ins->inst_imm;
3365 temp->dreg = mono_alloc_ireg (cfg);
3366 ins->opcode = OP_COMPARE;
3367 ins->sreg2 = temp->dreg;
3370 #ifndef __mono_ilp32__
3371 case OP_LOAD_MEMBASE:
3373 case OP_LOADI8_MEMBASE:
3374 #ifndef __native_client_codegen__
3375 /* Don't generate memindex opcodes (to simplify */
3376 /* read sandboxing) */
3377 if (!amd64_use_imm32 (ins->inst_offset)) {
3378 NEW_INS (cfg, ins, temp, OP_I8CONST);
3379 temp->inst_c0 = ins->inst_offset;
3380 temp->dreg = mono_alloc_ireg (cfg);
3381 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3382 ins->inst_indexreg = temp->dreg;
3386 #ifndef __mono_ilp32__
3387 case OP_STORE_MEMBASE_IMM:
3389 case OP_STOREI8_MEMBASE_IMM:
3390 if (!amd64_use_imm32 (ins->inst_imm)) {
3391 NEW_INS (cfg, ins, temp, OP_I8CONST);
3392 temp->inst_c0 = ins->inst_imm;
3393 temp->dreg = mono_alloc_ireg (cfg);
3394 ins->opcode = OP_STOREI8_MEMBASE_REG;
3395 ins->sreg1 = temp->dreg;
3398 #ifdef MONO_ARCH_SIMD_INTRINSICS
3399 case OP_EXPAND_I1: {
3400 int temp_reg1 = mono_alloc_ireg (cfg);
3401 int temp_reg2 = mono_alloc_ireg (cfg);
3402 int original_reg = ins->sreg1;
3404 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3405 temp->sreg1 = original_reg;
3406 temp->dreg = temp_reg1;
3408 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3409 temp->sreg1 = temp_reg1;
3410 temp->dreg = temp_reg2;
3413 NEW_INS (cfg, ins, temp, OP_LOR);
3414 temp->sreg1 = temp->dreg = temp_reg2;
3415 temp->sreg2 = temp_reg1;
3417 ins->opcode = OP_EXPAND_I2;
3418 ins->sreg1 = temp_reg2;
3427 bb->max_vreg = cfg->next_vreg;
3431 branch_cc_table [] = {
3432 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3433 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3434 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3437 /* Maps CMP_... constants to X86_CC_... constants */
3440 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3441 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3445 cc_signed_table [] = {
3446 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3447 FALSE, FALSE, FALSE, FALSE
3450 /*#include "cprop.c"*/
3452 static unsigned char*
3453 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3456 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3458 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3461 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3463 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3467 static unsigned char*
3468 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3470 int sreg = tree->sreg1;
3471 int need_touch = FALSE;
3473 #if defined(TARGET_WIN32)
3475 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3476 if (!tree->flags & MONO_INST_INIT)
3485 * If requested stack size is larger than one page,
3486 * perform stack-touch operation
3489 * Generate stack probe code.
3490 * Under Windows, it is necessary to allocate one page at a time,
3491 * "touching" stack after each successful sub-allocation. This is
3492 * because of the way stack growth is implemented - there is a
3493 * guard page before the lowest stack page that is currently commited.
3494 * Stack normally grows sequentially so OS traps access to the
3495 * guard page and commits more pages when needed.
3497 amd64_test_reg_imm (code, sreg, ~0xFFF);
3498 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3500 br[2] = code; /* loop */
3501 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3502 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3503 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3504 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3505 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3506 amd64_patch (br[3], br[2]);
3507 amd64_test_reg_reg (code, sreg, sreg);
3508 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3509 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3511 br[1] = code; x86_jump8 (code, 0);
3513 amd64_patch (br[0], code);
3514 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3515 amd64_patch (br[1], code);
3516 amd64_patch (br[4], code);
3519 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3521 if (tree->flags & MONO_INST_INIT) {
3523 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3524 amd64_push_reg (code, AMD64_RAX);
3527 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3528 amd64_push_reg (code, AMD64_RCX);
3531 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3532 amd64_push_reg (code, AMD64_RDI);
3536 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3537 if (sreg != AMD64_RCX)
3538 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3539 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3541 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3542 if (cfg->param_area)
3543 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3545 #if defined(__default_codegen__)
3546 amd64_prefix (code, X86_REP_PREFIX);
3548 #elif defined(__native_client_codegen__)
3549 /* NaCl stos pseudo-instruction */
3550 amd64_codegen_pre(code);
3551 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3552 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3553 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3554 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3555 amd64_prefix (code, X86_REP_PREFIX);
3557 amd64_codegen_post(code);
3558 #endif /* __native_client_codegen__ */
3560 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3561 amd64_pop_reg (code, AMD64_RDI);
3562 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3563 amd64_pop_reg (code, AMD64_RCX);
3564 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3565 amd64_pop_reg (code, AMD64_RAX);
3571 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3576 /* Move return value to the target register */
3577 /* FIXME: do this in the local reg allocator */
3578 switch (ins->opcode) {
3581 case OP_CALL_MEMBASE:
3584 case OP_LCALL_MEMBASE:
3585 g_assert (ins->dreg == AMD64_RAX);
3589 case OP_FCALL_MEMBASE: {
3590 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3591 if (rtype->type == MONO_TYPE_R4) {
3592 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3595 if (ins->dreg != AMD64_XMM0)
3596 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3602 case OP_RCALL_MEMBASE:
3603 if (ins->dreg != AMD64_XMM0)
3604 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3608 case OP_VCALL_MEMBASE:
3611 case OP_VCALL2_MEMBASE:
3612 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3613 if (cinfo->ret.storage == ArgValuetypeInReg) {
3614 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3616 /* Load the destination address */
3617 g_assert (loc->opcode == OP_REGOFFSET);
3618 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3620 for (quad = 0; quad < 2; quad ++) {
3621 switch (cinfo->ret.pair_storage [quad]) {
3623 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3625 case ArgInFloatSSEReg:
3626 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3628 case ArgInDoubleSSEReg:
3629 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3644 #endif /* DISABLE_JIT */
3647 static int tls_gs_offset;
3651 mono_amd64_have_tls_get (void)
3654 static gboolean have_tls_get = FALSE;
3655 static gboolean inited = FALSE;
3658 return have_tls_get;
3660 #if MONO_HAVE_FAST_TLS
3661 guint8 *ins = (guint8*)pthread_getspecific;
3664 * We're looking for these two instructions:
3666 * mov %gs:[offset](,%rdi,8),%rax
3669 have_tls_get = ins [0] == 0x65 &&
3679 tls_gs_offset = ins[5];
3682 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3683 * For that version we're looking for these instructions:
3687 * mov %gs:[offset](,%rdi,8),%rax
3691 if (!have_tls_get) {
3692 have_tls_get = ins [0] == 0x55 &&
3707 tls_gs_offset = ins[9];
3713 return have_tls_get;
3714 #elif defined(TARGET_ANDROID)
3722 mono_amd64_get_tls_gs_offset (void)
3725 return tls_gs_offset;
3727 g_assert_not_reached ();
3733 * mono_amd64_emit_tls_get:
3734 * @code: buffer to store code to
3735 * @dreg: hard register where to place the result
3736 * @tls_offset: offset info
3738 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3739 * the dreg register the item in the thread local storage identified
3742 * Returns: a pointer to the end of the stored code
3745 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3748 if (tls_offset < 64) {
3749 x86_prefix (code, X86_GS_PREFIX);
3750 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3754 g_assert (tls_offset < 0x440);
3755 /* Load TEB->TlsExpansionSlots */
3756 x86_prefix (code, X86_GS_PREFIX);
3757 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3758 amd64_test_reg_reg (code, dreg, dreg);
3760 amd64_branch (code, X86_CC_EQ, code, TRUE);
3761 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3762 amd64_patch (buf [0], code);
3764 #elif defined(__APPLE__)
3765 x86_prefix (code, X86_GS_PREFIX);
3766 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3768 if (optimize_for_xen) {
3769 x86_prefix (code, X86_FS_PREFIX);
3770 amd64_mov_reg_mem (code, dreg, 0, 8);
3771 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3773 x86_prefix (code, X86_FS_PREFIX);
3774 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3781 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3783 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3785 if (dreg != offset_reg)
3786 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3787 amd64_prefix (code, X86_GS_PREFIX);
3788 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3789 #elif defined(__linux__)
3792 if (dreg == offset_reg) {
3793 /* Use a temporary reg by saving it to the redzone */
3794 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3795 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3796 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3797 offset_reg = tmpreg;
3799 x86_prefix (code, X86_FS_PREFIX);
3800 amd64_mov_reg_mem (code, dreg, 0, 8);
3801 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3803 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3805 g_assert_not_reached ();
3811 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3814 g_assert_not_reached ();
3815 #elif defined(__APPLE__)
3816 x86_prefix (code, X86_GS_PREFIX);
3817 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3819 g_assert (!optimize_for_xen);
3820 x86_prefix (code, X86_FS_PREFIX);
3821 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3827 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3829 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3831 g_assert_not_reached ();
3832 #elif defined(__APPLE__)
3833 x86_prefix (code, X86_GS_PREFIX);
3834 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3836 x86_prefix (code, X86_FS_PREFIX);
3837 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3843 * mono_arch_translate_tls_offset:
3845 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3848 mono_arch_translate_tls_offset (int offset)
3851 return tls_gs_offset + (offset * 8);
3860 * Emit code to initialize an LMF structure at LMF_OFFSET.
3863 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3866 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3869 * sp is saved right before calls but we need to save it here too so
3870 * async stack walks would work.
3872 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3874 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3875 if (cfg->arch.omit_fp && cfa_offset != -1)
3876 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3878 /* These can't contain refs */
3879 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3880 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3881 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3882 /* These are handled automatically by the stack marking code */
3883 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3888 /* benchmark and set based on cpu */
3889 #define LOOP_ALIGNMENT 8
3890 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3894 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3899 guint8 *code = cfg->native_code + cfg->code_len;
3902 /* Fix max_offset estimate for each successor bb */
3903 if (cfg->opt & MONO_OPT_BRANCH) {
3904 int current_offset = cfg->code_len;
3905 MonoBasicBlock *current_bb;
3906 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3907 current_bb->max_offset = current_offset;
3908 current_offset += current_bb->max_length;
3912 if (cfg->opt & MONO_OPT_LOOP) {
3913 int pad, align = LOOP_ALIGNMENT;
3914 /* set alignment depending on cpu */
3915 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3917 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3918 amd64_padding (code, pad);
3919 cfg->code_len += pad;
3920 bb->native_offset = cfg->code_len;
3924 #if defined(__native_client_codegen__)
3925 /* For Native Client, all indirect call/jump targets must be */
3926 /* 32-byte aligned. Exception handler blocks are jumped to */
3927 /* indirectly as well. */
3928 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3929 (bb->flags & BB_EXCEPTION_HANDLER);
3931 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3932 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3933 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3934 cfg->code_len += pad;
3935 bb->native_offset = cfg->code_len;
3937 #endif /*__native_client_codegen__*/
3939 if (cfg->verbose_level > 2)
3940 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3942 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3943 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3944 g_assert (!cfg->compile_aot);
3946 cov->data [bb->dfn].cil_code = bb->cil_code;
3947 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3948 /* this is not thread save, but good enough */
3949 amd64_inc_membase (code, AMD64_R11, 0);
3952 offset = code - cfg->native_code;
3954 mono_debug_open_block (cfg, bb, offset);
3956 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3957 x86_breakpoint (code);
3959 MONO_BB_FOR_EACH_INS (bb, ins) {
3960 offset = code - cfg->native_code;
3962 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3964 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3966 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3967 cfg->code_size *= 2;
3968 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3969 code = cfg->native_code + offset;
3970 cfg->stat_code_reallocs++;
3973 if (cfg->debug_info)
3974 mono_debug_record_line_number (cfg, ins, offset);
3976 switch (ins->opcode) {
3978 amd64_mul_reg (code, ins->sreg2, TRUE);
3981 amd64_mul_reg (code, ins->sreg2, FALSE);
3983 case OP_X86_SETEQ_MEMBASE:
3984 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3986 case OP_STOREI1_MEMBASE_IMM:
3987 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3989 case OP_STOREI2_MEMBASE_IMM:
3990 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3992 case OP_STOREI4_MEMBASE_IMM:
3993 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3995 case OP_STOREI1_MEMBASE_REG:
3996 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3998 case OP_STOREI2_MEMBASE_REG:
3999 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4001 /* In AMD64 NaCl, pointers are 4 bytes, */
4002 /* so STORE_* != STOREI8_*. Likewise below. */
4003 case OP_STORE_MEMBASE_REG:
4004 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4006 case OP_STOREI8_MEMBASE_REG:
4007 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4009 case OP_STOREI4_MEMBASE_REG:
4010 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4012 case OP_STORE_MEMBASE_IMM:
4013 #ifndef __native_client_codegen__
4014 /* In NaCl, this could be a PCONST type, which could */
4015 /* mean a pointer type was copied directly into the */
4016 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4017 /* the value would be 0x00000000FFFFFFFF which is */
4018 /* not proper for an imm32 unless you cast it. */
4019 g_assert (amd64_is_imm32 (ins->inst_imm));
4021 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4023 case OP_STOREI8_MEMBASE_IMM:
4024 g_assert (amd64_is_imm32 (ins->inst_imm));
4025 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4028 #ifdef __mono_ilp32__
4029 /* In ILP32, pointers are 4 bytes, so separate these */
4030 /* cases, use literal 8 below where we really want 8 */
4031 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4032 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4036 // FIXME: Decompose this earlier
4037 if (amd64_use_imm32 (ins->inst_imm))
4038 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4040 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4041 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4045 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4046 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4049 // FIXME: Decompose this earlier
4050 if (amd64_use_imm32 (ins->inst_imm))
4051 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4053 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4054 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4058 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4059 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4062 /* For NaCl, pointers are 4 bytes, so separate these */
4063 /* cases, use literal 8 below where we really want 8 */
4064 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4065 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4067 case OP_LOAD_MEMBASE:
4068 g_assert (amd64_is_imm32 (ins->inst_offset));
4069 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4071 case OP_LOADI8_MEMBASE:
4072 /* Use literal 8 instead of sizeof pointer or */
4073 /* register, we really want 8 for this opcode */
4074 g_assert (amd64_is_imm32 (ins->inst_offset));
4075 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4077 case OP_LOADI4_MEMBASE:
4078 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4080 case OP_LOADU4_MEMBASE:
4081 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4083 case OP_LOADU1_MEMBASE:
4084 /* The cpu zero extends the result into 64 bits */
4085 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4087 case OP_LOADI1_MEMBASE:
4088 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4090 case OP_LOADU2_MEMBASE:
4091 /* The cpu zero extends the result into 64 bits */
4092 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4094 case OP_LOADI2_MEMBASE:
4095 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4097 case OP_AMD64_LOADI8_MEMINDEX:
4098 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4100 case OP_LCONV_TO_I1:
4101 case OP_ICONV_TO_I1:
4103 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4105 case OP_LCONV_TO_I2:
4106 case OP_ICONV_TO_I2:
4108 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4110 case OP_LCONV_TO_U1:
4111 case OP_ICONV_TO_U1:
4112 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4114 case OP_LCONV_TO_U2:
4115 case OP_ICONV_TO_U2:
4116 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4119 /* Clean out the upper word */
4120 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4123 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4127 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4129 case OP_COMPARE_IMM:
4130 #if defined(__mono_ilp32__)
4131 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4132 g_assert (amd64_is_imm32 (ins->inst_imm));
4133 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4136 case OP_LCOMPARE_IMM:
4137 g_assert (amd64_is_imm32 (ins->inst_imm));
4138 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4140 case OP_X86_COMPARE_REG_MEMBASE:
4141 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4143 case OP_X86_TEST_NULL:
4144 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4146 case OP_AMD64_TEST_NULL:
4147 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4150 case OP_X86_ADD_REG_MEMBASE:
4151 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4153 case OP_X86_SUB_REG_MEMBASE:
4154 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4156 case OP_X86_AND_REG_MEMBASE:
4157 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4159 case OP_X86_OR_REG_MEMBASE:
4160 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4162 case OP_X86_XOR_REG_MEMBASE:
4163 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4166 case OP_X86_ADD_MEMBASE_IMM:
4167 /* FIXME: Make a 64 version too */
4168 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4170 case OP_X86_SUB_MEMBASE_IMM:
4171 g_assert (amd64_is_imm32 (ins->inst_imm));
4172 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4174 case OP_X86_AND_MEMBASE_IMM:
4175 g_assert (amd64_is_imm32 (ins->inst_imm));
4176 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4178 case OP_X86_OR_MEMBASE_IMM:
4179 g_assert (amd64_is_imm32 (ins->inst_imm));
4180 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4182 case OP_X86_XOR_MEMBASE_IMM:
4183 g_assert (amd64_is_imm32 (ins->inst_imm));
4184 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4186 case OP_X86_ADD_MEMBASE_REG:
4187 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4189 case OP_X86_SUB_MEMBASE_REG:
4190 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4192 case OP_X86_AND_MEMBASE_REG:
4193 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4195 case OP_X86_OR_MEMBASE_REG:
4196 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4198 case OP_X86_XOR_MEMBASE_REG:
4199 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4201 case OP_X86_INC_MEMBASE:
4202 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4204 case OP_X86_INC_REG:
4205 amd64_inc_reg_size (code, ins->dreg, 4);
4207 case OP_X86_DEC_MEMBASE:
4208 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4210 case OP_X86_DEC_REG:
4211 amd64_dec_reg_size (code, ins->dreg, 4);
4213 case OP_X86_MUL_REG_MEMBASE:
4214 case OP_X86_MUL_MEMBASE_REG:
4215 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4217 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4218 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4220 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4221 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4223 case OP_AMD64_COMPARE_MEMBASE_REG:
4224 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4226 case OP_AMD64_COMPARE_MEMBASE_IMM:
4227 g_assert (amd64_is_imm32 (ins->inst_imm));
4228 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4230 case OP_X86_COMPARE_MEMBASE8_IMM:
4231 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4233 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4234 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4236 case OP_AMD64_COMPARE_REG_MEMBASE:
4237 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4240 case OP_AMD64_ADD_REG_MEMBASE:
4241 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4243 case OP_AMD64_SUB_REG_MEMBASE:
4244 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4246 case OP_AMD64_AND_REG_MEMBASE:
4247 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4249 case OP_AMD64_OR_REG_MEMBASE:
4250 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4252 case OP_AMD64_XOR_REG_MEMBASE:
4253 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4256 case OP_AMD64_ADD_MEMBASE_REG:
4257 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4259 case OP_AMD64_SUB_MEMBASE_REG:
4260 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4262 case OP_AMD64_AND_MEMBASE_REG:
4263 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4265 case OP_AMD64_OR_MEMBASE_REG:
4266 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4268 case OP_AMD64_XOR_MEMBASE_REG:
4269 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4272 case OP_AMD64_ADD_MEMBASE_IMM:
4273 g_assert (amd64_is_imm32 (ins->inst_imm));
4274 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4276 case OP_AMD64_SUB_MEMBASE_IMM:
4277 g_assert (amd64_is_imm32 (ins->inst_imm));
4278 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4280 case OP_AMD64_AND_MEMBASE_IMM:
4281 g_assert (amd64_is_imm32 (ins->inst_imm));
4282 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4284 case OP_AMD64_OR_MEMBASE_IMM:
4285 g_assert (amd64_is_imm32 (ins->inst_imm));
4286 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4288 case OP_AMD64_XOR_MEMBASE_IMM:
4289 g_assert (amd64_is_imm32 (ins->inst_imm));
4290 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4294 amd64_breakpoint (code);
4296 case OP_RELAXED_NOP:
4297 x86_prefix (code, X86_REP_PREFIX);
4305 case OP_DUMMY_STORE:
4306 case OP_DUMMY_ICONST:
4307 case OP_DUMMY_R8CONST:
4308 case OP_NOT_REACHED:
4311 case OP_IL_SEQ_POINT:
4312 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4314 case OP_SEQ_POINT: {
4315 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4316 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4319 /* Load ss_tramp_var */
4320 /* This is equal to &ss_trampoline */
4321 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4322 /* Load the trampoline address */
4323 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4324 /* Call it if it is non-null */
4325 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4327 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4328 amd64_call_reg (code, AMD64_R11);
4329 amd64_patch (label, code);
4333 * This is the address which is saved in seq points,
4335 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4337 if (cfg->compile_aot) {
4338 guint32 offset = code - cfg->native_code;
4340 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4344 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4345 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4346 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4347 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4348 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4350 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4351 /* Call the trampoline */
4352 amd64_call_reg (code, AMD64_R11);
4353 amd64_patch (label, code);
4355 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4359 * Emit a test+branch against a constant, the constant will be overwritten
4360 * by mono_arch_set_breakpoint () to cause the test to fail.
4362 amd64_mov_reg_imm (code, AMD64_R11, 0);
4363 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4365 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4368 g_assert (var->opcode == OP_REGOFFSET);
4369 /* Load bp_tramp_var */
4370 /* This is equal to &bp_trampoline */
4371 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4372 /* Call the trampoline */
4373 amd64_call_membase (code, AMD64_R11, 0);
4374 amd64_patch (label, code);
4377 * Add an additional nop so skipping the bp doesn't cause the ip to point
4378 * to another IL offset.
4386 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4389 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4393 g_assert (amd64_is_imm32 (ins->inst_imm));
4394 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4397 g_assert (amd64_is_imm32 (ins->inst_imm));
4398 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4403 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4406 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4410 g_assert (amd64_is_imm32 (ins->inst_imm));
4411 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4414 g_assert (amd64_is_imm32 (ins->inst_imm));
4415 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4418 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4422 g_assert (amd64_is_imm32 (ins->inst_imm));
4423 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4426 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4431 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4433 switch (ins->inst_imm) {
4437 if (ins->dreg != ins->sreg1)
4438 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4439 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4442 /* LEA r1, [r2 + r2*2] */
4443 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4446 /* LEA r1, [r2 + r2*4] */
4447 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4450 /* LEA r1, [r2 + r2*2] */
4452 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4453 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4456 /* LEA r1, [r2 + r2*8] */
4457 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4460 /* LEA r1, [r2 + r2*4] */
4462 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4463 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4466 /* LEA r1, [r2 + r2*2] */
4468 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4469 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4472 /* LEA r1, [r2 + r2*4] */
4473 /* LEA r1, [r1 + r1*4] */
4474 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4475 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4478 /* LEA r1, [r2 + r2*4] */
4480 /* LEA r1, [r1 + r1*4] */
4481 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4482 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4483 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4486 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4493 #if defined( __native_client_codegen__ )
4494 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4495 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4497 /* Regalloc magic makes the div/rem cases the same */
4498 if (ins->sreg2 == AMD64_RDX) {
4499 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4501 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4504 amd64_div_reg (code, ins->sreg2, TRUE);
4509 #if defined( __native_client_codegen__ )
4510 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4511 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4513 if (ins->sreg2 == AMD64_RDX) {
4514 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4515 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4516 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4518 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4519 amd64_div_reg (code, ins->sreg2, FALSE);
4524 #if defined( __native_client_codegen__ )
4525 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4526 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4528 if (ins->sreg2 == AMD64_RDX) {
4529 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4530 amd64_cdq_size (code, 4);
4531 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4533 amd64_cdq_size (code, 4);
4534 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4539 #if defined( __native_client_codegen__ )
4540 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4541 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4543 if (ins->sreg2 == AMD64_RDX) {
4544 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4545 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4546 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4548 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4549 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4553 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4554 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4557 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4561 g_assert (amd64_is_imm32 (ins->inst_imm));
4562 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4565 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4569 g_assert (amd64_is_imm32 (ins->inst_imm));
4570 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4573 g_assert (ins->sreg2 == AMD64_RCX);
4574 amd64_shift_reg (code, X86_SHL, ins->dreg);
4577 g_assert (ins->sreg2 == AMD64_RCX);
4578 amd64_shift_reg (code, X86_SAR, ins->dreg);
4582 g_assert (amd64_is_imm32 (ins->inst_imm));
4583 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4586 g_assert (amd64_is_imm32 (ins->inst_imm));
4587 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4589 case OP_LSHR_UN_IMM:
4590 g_assert (amd64_is_imm32 (ins->inst_imm));
4591 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4594 g_assert (ins->sreg2 == AMD64_RCX);
4595 amd64_shift_reg (code, X86_SHR, ins->dreg);
4599 g_assert (amd64_is_imm32 (ins->inst_imm));
4600 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4605 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4608 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4611 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4614 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4618 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4621 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4624 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4627 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4630 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4633 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4636 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4639 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4642 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4645 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4648 amd64_neg_reg_size (code, ins->sreg1, 4);
4651 amd64_not_reg_size (code, ins->sreg1, 4);
4654 g_assert (ins->sreg2 == AMD64_RCX);
4655 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4658 g_assert (ins->sreg2 == AMD64_RCX);
4659 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4662 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4664 case OP_ISHR_UN_IMM:
4665 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4668 g_assert (ins->sreg2 == AMD64_RCX);
4669 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4672 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4675 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4678 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4679 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4681 case OP_IMUL_OVF_UN:
4682 case OP_LMUL_OVF_UN: {
4683 /* the mul operation and the exception check should most likely be split */
4684 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4685 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4686 /*g_assert (ins->sreg2 == X86_EAX);
4687 g_assert (ins->dreg == X86_EAX);*/
4688 if (ins->sreg2 == X86_EAX) {
4689 non_eax_reg = ins->sreg1;
4690 } else if (ins->sreg1 == X86_EAX) {
4691 non_eax_reg = ins->sreg2;
4693 /* no need to save since we're going to store to it anyway */
4694 if (ins->dreg != X86_EAX) {
4696 amd64_push_reg (code, X86_EAX);
4698 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4699 non_eax_reg = ins->sreg2;
4701 if (ins->dreg == X86_EDX) {
4704 amd64_push_reg (code, X86_EAX);
4708 amd64_push_reg (code, X86_EDX);
4710 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4711 /* save before the check since pop and mov don't change the flags */
4712 if (ins->dreg != X86_EAX)
4713 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4715 amd64_pop_reg (code, X86_EDX);
4717 amd64_pop_reg (code, X86_EAX);
4718 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4722 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4724 case OP_ICOMPARE_IMM:
4725 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4747 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4755 case OP_CMOV_INE_UN:
4756 case OP_CMOV_IGE_UN:
4757 case OP_CMOV_IGT_UN:
4758 case OP_CMOV_ILE_UN:
4759 case OP_CMOV_ILT_UN:
4765 case OP_CMOV_LNE_UN:
4766 case OP_CMOV_LGE_UN:
4767 case OP_CMOV_LGT_UN:
4768 case OP_CMOV_LLE_UN:
4769 case OP_CMOV_LLT_UN:
4770 g_assert (ins->dreg == ins->sreg1);
4771 /* This needs to operate on 64 bit values */
4772 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4776 amd64_not_reg (code, ins->sreg1);
4779 amd64_neg_reg (code, ins->sreg1);
4784 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4785 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4787 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4790 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4791 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4794 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4795 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4798 if (ins->dreg != ins->sreg1)
4799 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4801 case OP_AMD64_SET_XMMREG_R4: {
4803 if (ins->dreg != ins->sreg1)
4804 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4806 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4810 case OP_AMD64_SET_XMMREG_R8: {
4811 if (ins->dreg != ins->sreg1)
4812 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4816 MonoCallInst *call = (MonoCallInst*)ins;
4817 int i, save_area_offset;
4819 g_assert (!cfg->method->save_lmf);
4821 /* Restore callee saved registers */
4822 save_area_offset = cfg->arch.reg_save_area_offset;
4823 for (i = 0; i < AMD64_NREG; ++i)
4824 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4825 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4826 save_area_offset += 8;
4829 if (cfg->arch.omit_fp) {
4830 if (cfg->arch.stack_alloc_size)
4831 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4833 if (call->stack_usage)
4836 /* Copy arguments on the stack to our argument area */
4837 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4838 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4839 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4845 offset = code - cfg->native_code;
4846 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4847 if (cfg->compile_aot)
4848 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4850 amd64_set_reg_template (code, AMD64_R11);
4851 amd64_jump_reg (code, AMD64_R11);
4852 ins->flags |= MONO_INST_GC_CALLSITE;
4853 ins->backend.pc_offset = code - cfg->native_code;
4857 /* ensure ins->sreg1 is not NULL */
4858 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4861 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4862 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4872 call = (MonoCallInst*)ins;
4874 * The AMD64 ABI forces callers to know about varargs.
4876 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4877 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4878 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4880 * Since the unmanaged calling convention doesn't contain a
4881 * 'vararg' entry, we have to treat every pinvoke call as a
4882 * potential vararg call.
4886 for (i = 0; i < AMD64_XMM_NREG; ++i)
4887 if (call->used_fregs & (1 << i))
4890 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4892 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4895 if (ins->flags & MONO_INST_HAS_METHOD)
4896 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4898 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4899 ins->flags |= MONO_INST_GC_CALLSITE;
4900 ins->backend.pc_offset = code - cfg->native_code;
4901 code = emit_move_return_value (cfg, ins, code);
4908 case OP_VOIDCALL_REG:
4910 call = (MonoCallInst*)ins;
4912 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4913 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4914 ins->sreg1 = AMD64_R11;
4918 * The AMD64 ABI forces callers to know about varargs.
4920 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4921 if (ins->sreg1 == AMD64_RAX) {
4922 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4923 ins->sreg1 = AMD64_R11;
4925 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4926 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4928 * Since the unmanaged calling convention doesn't contain a
4929 * 'vararg' entry, we have to treat every pinvoke call as a
4930 * potential vararg call.
4934 for (i = 0; i < AMD64_XMM_NREG; ++i)
4935 if (call->used_fregs & (1 << i))
4937 if (ins->sreg1 == AMD64_RAX) {
4938 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4939 ins->sreg1 = AMD64_R11;
4942 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4944 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4947 amd64_call_reg (code, ins->sreg1);
4948 ins->flags |= MONO_INST_GC_CALLSITE;
4949 ins->backend.pc_offset = code - cfg->native_code;
4950 code = emit_move_return_value (cfg, ins, code);
4952 case OP_FCALL_MEMBASE:
4953 case OP_RCALL_MEMBASE:
4954 case OP_LCALL_MEMBASE:
4955 case OP_VCALL_MEMBASE:
4956 case OP_VCALL2_MEMBASE:
4957 case OP_VOIDCALL_MEMBASE:
4958 case OP_CALL_MEMBASE:
4959 call = (MonoCallInst*)ins;
4961 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4962 ins->flags |= MONO_INST_GC_CALLSITE;
4963 ins->backend.pc_offset = code - cfg->native_code;
4964 code = emit_move_return_value (cfg, ins, code);
4968 MonoInst *var = cfg->dyn_call_var;
4971 g_assert (var->opcode == OP_REGOFFSET);
4973 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4974 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4976 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4978 /* Save args buffer */
4979 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4981 /* Set fp arg regs */
4982 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4983 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4985 amd64_branch8 (code, X86_CC_Z, -1, 1);
4986 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4987 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4988 amd64_patch (label, code);
4990 /* Set argument registers */
4991 for (i = 0; i < PARAM_REGS; ++i)
4992 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4995 amd64_call_reg (code, AMD64_R10);
4997 ins->flags |= MONO_INST_GC_CALLSITE;
4998 ins->backend.pc_offset = code - cfg->native_code;
5001 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5002 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5003 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5006 case OP_AMD64_SAVE_SP_TO_LMF: {
5007 MonoInst *lmf_var = cfg->lmf_var;
5008 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5012 g_assert_not_reached ();
5013 amd64_push_reg (code, ins->sreg1);
5015 case OP_X86_PUSH_IMM:
5016 g_assert_not_reached ();
5017 g_assert (amd64_is_imm32 (ins->inst_imm));
5018 amd64_push_imm (code, ins->inst_imm);
5020 case OP_X86_PUSH_MEMBASE:
5021 g_assert_not_reached ();
5022 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5024 case OP_X86_PUSH_OBJ: {
5025 int size = ALIGN_TO (ins->inst_imm, 8);
5027 g_assert_not_reached ();
5029 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5030 amd64_push_reg (code, AMD64_RDI);
5031 amd64_push_reg (code, AMD64_RSI);
5032 amd64_push_reg (code, AMD64_RCX);
5033 if (ins->inst_offset)
5034 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5036 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5037 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5038 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5040 amd64_prefix (code, X86_REP_PREFIX);
5042 amd64_pop_reg (code, AMD64_RCX);
5043 amd64_pop_reg (code, AMD64_RSI);
5044 amd64_pop_reg (code, AMD64_RDI);
5047 case OP_GENERIC_CLASS_INIT: {
5048 static int byte_offset = -1;
5049 static guint8 bitmask;
5052 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5054 if (byte_offset < 0)
5055 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5057 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5059 amd64_branch8 (code, X86_CC_NZ, -1, 1);
5061 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5062 ins->flags |= MONO_INST_GC_CALLSITE;
5063 ins->backend.pc_offset = code - cfg->native_code;
5065 x86_patch (jump, code);
5070 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5072 case OP_X86_LEA_MEMBASE:
5073 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5076 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5079 /* keep alignment */
5080 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5081 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5082 code = mono_emit_stack_alloc (cfg, code, ins);
5083 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5084 if (cfg->param_area)
5085 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5087 case OP_LOCALLOC_IMM: {
5088 guint32 size = ins->inst_imm;
5089 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5091 if (ins->flags & MONO_INST_INIT) {
5095 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5096 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5098 for (i = 0; i < size; i += 8)
5099 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5100 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5102 amd64_mov_reg_imm (code, ins->dreg, size);
5103 ins->sreg1 = ins->dreg;
5105 code = mono_emit_stack_alloc (cfg, code, ins);
5106 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5109 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5110 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5112 if (cfg->param_area)
5113 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5117 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5118 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5119 (gpointer)"mono_arch_throw_exception", FALSE);
5120 ins->flags |= MONO_INST_GC_CALLSITE;
5121 ins->backend.pc_offset = code - cfg->native_code;
5125 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5126 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5127 (gpointer)"mono_arch_rethrow_exception", FALSE);
5128 ins->flags |= MONO_INST_GC_CALLSITE;
5129 ins->backend.pc_offset = code - cfg->native_code;
5132 case OP_CALL_HANDLER:
5134 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5135 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5136 amd64_call_imm (code, 0);
5137 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5138 /* Restore stack alignment */
5139 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5141 case OP_START_HANDLER: {
5142 /* Even though we're saving RSP, use sizeof */
5143 /* gpointer because spvar is of type IntPtr */
5144 /* see: mono_create_spvar_for_region */
5145 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5146 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5148 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5149 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5151 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5155 case OP_ENDFINALLY: {
5156 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5157 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5161 case OP_ENDFILTER: {
5162 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5163 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5164 /* The local allocator will put the result into RAX */
5169 if (ins->dreg != AMD64_RAX)
5170 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5173 ins->inst_c0 = code - cfg->native_code;
5176 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5177 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5179 if (ins->inst_target_bb->native_offset) {
5180 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5182 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5183 if ((cfg->opt & MONO_OPT_BRANCH) &&
5184 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5185 x86_jump8 (code, 0);
5187 x86_jump32 (code, 0);
5191 amd64_jump_reg (code, ins->sreg1);
5214 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5215 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5217 case OP_COND_EXC_EQ:
5218 case OP_COND_EXC_NE_UN:
5219 case OP_COND_EXC_LT:
5220 case OP_COND_EXC_LT_UN:
5221 case OP_COND_EXC_GT:
5222 case OP_COND_EXC_GT_UN:
5223 case OP_COND_EXC_GE:
5224 case OP_COND_EXC_GE_UN:
5225 case OP_COND_EXC_LE:
5226 case OP_COND_EXC_LE_UN:
5227 case OP_COND_EXC_IEQ:
5228 case OP_COND_EXC_INE_UN:
5229 case OP_COND_EXC_ILT:
5230 case OP_COND_EXC_ILT_UN:
5231 case OP_COND_EXC_IGT:
5232 case OP_COND_EXC_IGT_UN:
5233 case OP_COND_EXC_IGE:
5234 case OP_COND_EXC_IGE_UN:
5235 case OP_COND_EXC_ILE:
5236 case OP_COND_EXC_ILE_UN:
5237 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5239 case OP_COND_EXC_OV:
5240 case OP_COND_EXC_NO:
5242 case OP_COND_EXC_NC:
5243 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5244 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5246 case OP_COND_EXC_IOV:
5247 case OP_COND_EXC_INO:
5248 case OP_COND_EXC_IC:
5249 case OP_COND_EXC_INC:
5250 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5251 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5254 /* floating point opcodes */
5256 double d = *(double *)ins->inst_p0;
5258 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5259 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5262 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5263 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5268 float f = *(float *)ins->inst_p0;
5270 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5272 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5274 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5277 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5278 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5280 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5284 case OP_STORER8_MEMBASE_REG:
5285 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5287 case OP_LOADR8_MEMBASE:
5288 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5290 case OP_STORER4_MEMBASE_REG:
5292 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5294 /* This requires a double->single conversion */
5295 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5296 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5299 case OP_LOADR4_MEMBASE:
5301 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5303 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5304 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5307 case OP_ICONV_TO_R4:
5309 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5311 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5312 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5315 case OP_ICONV_TO_R8:
5316 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5318 case OP_LCONV_TO_R4:
5320 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5322 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5323 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5326 case OP_LCONV_TO_R8:
5327 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5329 case OP_FCONV_TO_R4:
5331 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5333 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5334 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5337 case OP_FCONV_TO_I1:
5338 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5340 case OP_FCONV_TO_U1:
5341 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5343 case OP_FCONV_TO_I2:
5344 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5346 case OP_FCONV_TO_U2:
5347 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5349 case OP_FCONV_TO_U4:
5350 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5352 case OP_FCONV_TO_I4:
5354 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5356 case OP_FCONV_TO_I8:
5357 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5360 case OP_RCONV_TO_I1:
5361 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5362 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5364 case OP_RCONV_TO_U1:
5365 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5366 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5368 case OP_RCONV_TO_I2:
5369 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5370 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5372 case OP_RCONV_TO_U2:
5373 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5374 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5376 case OP_RCONV_TO_I4:
5377 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5379 case OP_RCONV_TO_U4:
5380 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5382 case OP_RCONV_TO_I8:
5383 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5385 case OP_RCONV_TO_R8:
5386 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5388 case OP_RCONV_TO_R4:
5389 if (ins->dreg != ins->sreg1)
5390 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5393 case OP_LCONV_TO_R_UN: {
5396 /* Based on gcc code */
5397 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5398 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5401 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5402 br [1] = code; x86_jump8 (code, 0);
5403 amd64_patch (br [0], code);
5406 /* Save to the red zone */
5407 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5408 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5409 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5410 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5411 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5412 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5413 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5414 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5415 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5417 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5418 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5419 amd64_patch (br [1], code);
5422 case OP_LCONV_TO_OVF_U4:
5423 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5424 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5425 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5427 case OP_LCONV_TO_OVF_I4_UN:
5428 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5429 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5430 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5433 if (ins->dreg != ins->sreg1)
5434 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5437 if (ins->dreg != ins->sreg1)
5438 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5440 case OP_MOVE_F_TO_I4:
5442 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5444 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5445 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5448 case OP_MOVE_I4_TO_F:
5449 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5451 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5453 case OP_MOVE_F_TO_I8:
5454 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5456 case OP_MOVE_I8_TO_F:
5457 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5460 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5463 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5466 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5469 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5472 static double r8_0 = -0.0;
5474 g_assert (ins->sreg1 == ins->dreg);
5476 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5477 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5481 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5484 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5487 static guint64 d = 0x7fffffffffffffffUL;
5489 g_assert (ins->sreg1 == ins->dreg);
5491 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5492 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5496 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5500 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5503 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5506 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5509 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5512 static float r4_0 = -0.0;
5514 g_assert (ins->sreg1 == ins->dreg);
5516 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5517 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5518 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5523 g_assert (cfg->opt & MONO_OPT_CMOV);
5524 g_assert (ins->dreg == ins->sreg1);
5525 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5526 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5529 g_assert (cfg->opt & MONO_OPT_CMOV);
5530 g_assert (ins->dreg == ins->sreg1);
5531 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5532 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5535 g_assert (cfg->opt & MONO_OPT_CMOV);
5536 g_assert (ins->dreg == ins->sreg1);
5537 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5538 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5541 g_assert (cfg->opt & MONO_OPT_CMOV);
5542 g_assert (ins->dreg == ins->sreg1);
5543 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5544 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5547 g_assert (cfg->opt & MONO_OPT_CMOV);
5548 g_assert (ins->dreg == ins->sreg1);
5549 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5550 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5553 g_assert (cfg->opt & MONO_OPT_CMOV);
5554 g_assert (ins->dreg == ins->sreg1);
5555 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5556 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5559 g_assert (cfg->opt & MONO_OPT_CMOV);
5560 g_assert (ins->dreg == ins->sreg1);
5561 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5562 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5565 g_assert (cfg->opt & MONO_OPT_CMOV);
5566 g_assert (ins->dreg == ins->sreg1);
5567 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5568 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5574 * The two arguments are swapped because the fbranch instructions
5575 * depend on this for the non-sse case to work.
5577 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5581 * FIXME: Get rid of this.
5582 * The two arguments are swapped because the fbranch instructions
5583 * depend on this for the non-sse case to work.
5585 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5589 /* zeroing the register at the start results in
5590 * shorter and faster code (we can also remove the widening op)
5592 guchar *unordered_check;
5594 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5595 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5596 unordered_check = code;
5597 x86_branch8 (code, X86_CC_P, 0, FALSE);
5599 if (ins->opcode == OP_FCEQ) {
5600 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5601 amd64_patch (unordered_check, code);
5603 guchar *jump_to_end;
5604 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5606 x86_jump8 (code, 0);
5607 amd64_patch (unordered_check, code);
5608 amd64_inc_reg (code, ins->dreg);
5609 amd64_patch (jump_to_end, code);
5615 /* zeroing the register at the start results in
5616 * shorter and faster code (we can also remove the widening op)
5618 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5619 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5620 if (ins->opcode == OP_FCLT_UN) {
5621 guchar *unordered_check = code;
5622 guchar *jump_to_end;
5623 x86_branch8 (code, X86_CC_P, 0, FALSE);
5624 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5626 x86_jump8 (code, 0);
5627 amd64_patch (unordered_check, code);
5628 amd64_inc_reg (code, ins->dreg);
5629 amd64_patch (jump_to_end, code);
5631 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5636 guchar *unordered_check;
5637 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5638 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5639 unordered_check = code;
5640 x86_branch8 (code, X86_CC_P, 0, FALSE);
5641 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5642 amd64_patch (unordered_check, code);
5647 /* zeroing the register at the start results in
5648 * shorter and faster code (we can also remove the widening op)
5650 guchar *unordered_check;
5652 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5653 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5654 if (ins->opcode == OP_FCGT) {
5655 unordered_check = code;
5656 x86_branch8 (code, X86_CC_P, 0, FALSE);
5657 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5658 amd64_patch (unordered_check, code);
5660 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5665 guchar *unordered_check;
5666 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5667 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5668 unordered_check = code;
5669 x86_branch8 (code, X86_CC_P, 0, FALSE);
5670 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5671 amd64_patch (unordered_check, code);
5681 gboolean unordered = FALSE;
5683 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5684 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5686 switch (ins->opcode) {
5688 x86_cond = X86_CC_EQ;
5691 x86_cond = X86_CC_LT;
5694 x86_cond = X86_CC_GT;
5697 x86_cond = X86_CC_GT;
5701 x86_cond = X86_CC_LT;
5705 g_assert_not_reached ();
5710 guchar *unordered_check;
5711 guchar *jump_to_end;
5713 unordered_check = code;
5714 x86_branch8 (code, X86_CC_P, 0, FALSE);
5715 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5717 x86_jump8 (code, 0);
5718 amd64_patch (unordered_check, code);
5719 amd64_inc_reg (code, ins->dreg);
5720 amd64_patch (jump_to_end, code);
5722 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5726 case OP_FCLT_MEMBASE:
5727 case OP_FCGT_MEMBASE:
5728 case OP_FCLT_UN_MEMBASE:
5729 case OP_FCGT_UN_MEMBASE:
5730 case OP_FCEQ_MEMBASE: {
5731 guchar *unordered_check, *jump_to_end;
5734 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5735 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5737 switch (ins->opcode) {
5738 case OP_FCEQ_MEMBASE:
5739 x86_cond = X86_CC_EQ;
5741 case OP_FCLT_MEMBASE:
5742 case OP_FCLT_UN_MEMBASE:
5743 x86_cond = X86_CC_LT;
5745 case OP_FCGT_MEMBASE:
5746 case OP_FCGT_UN_MEMBASE:
5747 x86_cond = X86_CC_GT;
5750 g_assert_not_reached ();
5753 unordered_check = code;
5754 x86_branch8 (code, X86_CC_P, 0, FALSE);
5755 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5757 switch (ins->opcode) {
5758 case OP_FCEQ_MEMBASE:
5759 case OP_FCLT_MEMBASE:
5760 case OP_FCGT_MEMBASE:
5761 amd64_patch (unordered_check, code);
5763 case OP_FCLT_UN_MEMBASE:
5764 case OP_FCGT_UN_MEMBASE:
5766 x86_jump8 (code, 0);
5767 amd64_patch (unordered_check, code);
5768 amd64_inc_reg (code, ins->dreg);
5769 amd64_patch (jump_to_end, code);
5777 guchar *jump = code;
5778 x86_branch8 (code, X86_CC_P, 0, TRUE);
5779 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5780 amd64_patch (jump, code);
5784 /* Branch if C013 != 100 */
5785 /* branch if !ZF or (PF|CF) */
5786 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5787 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5788 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5791 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5794 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5795 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5799 if (ins->opcode == OP_FBGT) {
5802 /* skip branch if C1=1 */
5804 x86_branch8 (code, X86_CC_P, 0, FALSE);
5805 /* branch if (C0 | C3) = 1 */
5806 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5807 amd64_patch (br1, code);
5810 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5814 /* Branch if C013 == 100 or 001 */
5817 /* skip branch if C1=1 */
5819 x86_branch8 (code, X86_CC_P, 0, FALSE);
5820 /* branch if (C0 | C3) = 1 */
5821 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5822 amd64_patch (br1, code);
5826 /* Branch if C013 == 000 */
5827 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5830 /* Branch if C013=000 or 100 */
5833 /* skip branch if C1=1 */
5835 x86_branch8 (code, X86_CC_P, 0, FALSE);
5836 /* branch if C0=0 */
5837 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5838 amd64_patch (br1, code);
5842 /* Branch if C013 != 001 */
5843 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5844 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5847 /* Transfer value to the fp stack */
5848 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5849 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5850 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5852 amd64_push_reg (code, AMD64_RAX);
5854 amd64_fnstsw (code);
5855 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5856 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5857 amd64_pop_reg (code, AMD64_RAX);
5858 amd64_fstp (code, 0);
5859 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5860 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5863 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5866 case OP_TLS_GET_REG:
5867 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5870 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5873 case OP_TLS_SET_REG: {
5874 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5877 case OP_MEMORY_BARRIER: {
5878 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5882 case OP_ATOMIC_ADD_I4:
5883 case OP_ATOMIC_ADD_I8: {
5884 int dreg = ins->dreg;
5885 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5887 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5890 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5891 amd64_prefix (code, X86_LOCK_PREFIX);
5892 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5893 /* dreg contains the old value, add with sreg2 value */
5894 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5896 if (ins->dreg != dreg)
5897 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5901 case OP_ATOMIC_EXCHANGE_I4:
5902 case OP_ATOMIC_EXCHANGE_I8: {
5903 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5905 /* LOCK prefix is implied. */
5906 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5907 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5908 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5911 case OP_ATOMIC_CAS_I4:
5912 case OP_ATOMIC_CAS_I8: {
5915 if (ins->opcode == OP_ATOMIC_CAS_I8)
5921 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5922 * an explanation of how this works.
5924 g_assert (ins->sreg3 == AMD64_RAX);
5925 g_assert (ins->sreg1 != AMD64_RAX);
5926 g_assert (ins->sreg1 != ins->sreg2);
5928 amd64_prefix (code, X86_LOCK_PREFIX);
5929 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5931 if (ins->dreg != AMD64_RAX)
5932 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5935 case OP_ATOMIC_LOAD_I1: {
5936 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5939 case OP_ATOMIC_LOAD_U1: {
5940 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5943 case OP_ATOMIC_LOAD_I2: {
5944 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5947 case OP_ATOMIC_LOAD_U2: {
5948 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5951 case OP_ATOMIC_LOAD_I4: {
5952 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5955 case OP_ATOMIC_LOAD_U4:
5956 case OP_ATOMIC_LOAD_I8:
5957 case OP_ATOMIC_LOAD_U8: {
5958 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5961 case OP_ATOMIC_LOAD_R4: {
5962 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5963 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5966 case OP_ATOMIC_LOAD_R8: {
5967 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5970 case OP_ATOMIC_STORE_I1:
5971 case OP_ATOMIC_STORE_U1:
5972 case OP_ATOMIC_STORE_I2:
5973 case OP_ATOMIC_STORE_U2:
5974 case OP_ATOMIC_STORE_I4:
5975 case OP_ATOMIC_STORE_U4:
5976 case OP_ATOMIC_STORE_I8:
5977 case OP_ATOMIC_STORE_U8: {
5980 switch (ins->opcode) {
5981 case OP_ATOMIC_STORE_I1:
5982 case OP_ATOMIC_STORE_U1:
5985 case OP_ATOMIC_STORE_I2:
5986 case OP_ATOMIC_STORE_U2:
5989 case OP_ATOMIC_STORE_I4:
5990 case OP_ATOMIC_STORE_U4:
5993 case OP_ATOMIC_STORE_I8:
5994 case OP_ATOMIC_STORE_U8:
5999 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6001 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6005 case OP_ATOMIC_STORE_R4: {
6006 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6007 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6009 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6013 case OP_ATOMIC_STORE_R8: {
6016 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6020 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6024 case OP_CARD_TABLE_WBARRIER: {
6025 int ptr = ins->sreg1;
6026 int value = ins->sreg2;
6028 int nursery_shift, card_table_shift;
6029 gpointer card_table_mask;
6030 size_t nursery_size;
6032 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6033 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6034 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6036 /*If either point to the stack we can simply avoid the WB. This happens due to
6037 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6039 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6043 * We need one register we can clobber, we choose EDX and make sreg1
6044 * fixed EAX to work around limitations in the local register allocator.
6045 * sreg2 might get allocated to EDX, but that is not a problem since
6046 * we use it before clobbering EDX.
6048 g_assert (ins->sreg1 == AMD64_RAX);
6051 * This is the code we produce:
6054 * edx >>= nursery_shift
6055 * cmp edx, (nursery_start >> nursery_shift)
6058 * edx >>= card_table_shift
6064 if (mono_gc_card_table_nursery_check ()) {
6065 if (value != AMD64_RDX)
6066 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6067 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6068 if (shifted_nursery_start >> 31) {
6070 * The value we need to compare against is 64 bits, so we need
6071 * another spare register. We use RBX, which we save and
6074 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6075 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6076 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6077 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6079 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6081 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6083 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6084 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6085 if (card_table_mask)
6086 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6088 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6089 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6091 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6093 if (mono_gc_card_table_nursery_check ())
6094 x86_patch (br, code);
6097 #ifdef MONO_ARCH_SIMD_INTRINSICS
6098 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6100 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6103 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6106 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6112 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6115 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6118 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6119 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6122 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6125 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6128 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6131 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6134 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6137 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6140 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6143 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6146 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6149 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6152 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6155 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6158 case OP_PSHUFLEW_HIGH:
6159 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6160 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6162 case OP_PSHUFLEW_LOW:
6163 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6164 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6167 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6168 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6171 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6172 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6175 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6176 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6180 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6183 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6192 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6195 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6198 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6199 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6202 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6205 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6208 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6211 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6214 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6217 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6220 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6223 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6226 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6229 case OP_EXTRACT_MASK:
6230 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6234 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6237 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6240 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6244 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6247 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6250 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6253 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6257 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6260 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6263 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6266 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6270 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6273 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6276 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6280 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6283 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6286 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6290 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6293 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6297 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6300 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6303 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6307 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6310 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6313 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6317 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6320 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6323 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6326 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6330 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6333 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6336 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6339 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6342 case OP_PSUM_ABS_DIFF:
6343 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6346 case OP_UNPACK_LOWB:
6347 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6349 case OP_UNPACK_LOWW:
6350 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6352 case OP_UNPACK_LOWD:
6353 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6355 case OP_UNPACK_LOWQ:
6356 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6358 case OP_UNPACK_LOWPS:
6359 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6361 case OP_UNPACK_LOWPD:
6362 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6365 case OP_UNPACK_HIGHB:
6366 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6368 case OP_UNPACK_HIGHW:
6369 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6371 case OP_UNPACK_HIGHD:
6372 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6374 case OP_UNPACK_HIGHQ:
6375 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6377 case OP_UNPACK_HIGHPS:
6378 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6380 case OP_UNPACK_HIGHPD:
6381 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6385 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6388 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6391 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6394 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6397 case OP_PADDB_SAT_UN:
6398 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6400 case OP_PSUBB_SAT_UN:
6401 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6403 case OP_PADDW_SAT_UN:
6404 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6406 case OP_PSUBW_SAT_UN:
6407 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6411 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6414 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6417 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6420 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6424 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6427 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6430 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6432 case OP_PMULW_HIGH_UN:
6433 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6436 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6440 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6443 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6447 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6450 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6454 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6457 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6461 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6464 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6468 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6471 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6475 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6478 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6482 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6485 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6488 /*TODO: This is appart of the sse spec but not added
6490 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6493 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6498 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6501 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6504 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6507 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6510 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6513 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6516 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6519 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6522 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6525 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6529 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6532 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6536 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6537 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6539 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6544 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6546 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6547 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6551 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6553 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6554 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6555 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6559 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6561 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6564 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6566 case OP_EXTRACTX_U2:
6567 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6569 case OP_INSERTX_U1_SLOW:
6570 /*sreg1 is the extracted ireg (scratch)
6571 /sreg2 is the to be inserted ireg (scratch)
6572 /dreg is the xreg to receive the value*/
6574 /*clear the bits from the extracted word*/
6575 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6576 /*shift the value to insert if needed*/
6577 if (ins->inst_c0 & 1)
6578 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6579 /*join them together*/
6580 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6581 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6583 case OP_INSERTX_I4_SLOW:
6584 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6585 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6586 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6588 case OP_INSERTX_I8_SLOW:
6589 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6591 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6593 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6596 case OP_INSERTX_R4_SLOW:
6597 switch (ins->inst_c0) {
6600 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6602 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6605 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6607 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6609 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6610 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6613 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6615 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6617 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6618 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6621 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6623 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6625 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6626 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6630 case OP_INSERTX_R8_SLOW:
6632 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6634 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6636 case OP_STOREX_MEMBASE_REG:
6637 case OP_STOREX_MEMBASE:
6638 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6640 case OP_LOADX_MEMBASE:
6641 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6643 case OP_LOADX_ALIGNED_MEMBASE:
6644 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6646 case OP_STOREX_ALIGNED_MEMBASE_REG:
6647 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6649 case OP_STOREX_NTA_MEMBASE_REG:
6650 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6652 case OP_PREFETCH_MEMBASE:
6653 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6657 /*FIXME the peephole pass should have killed this*/
6658 if (ins->dreg != ins->sreg1)
6659 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6662 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6664 case OP_ICONV_TO_R4_RAW:
6665 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6668 case OP_FCONV_TO_R8_X:
6669 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6672 case OP_XCONV_R8_TO_I4:
6673 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6674 switch (ins->backend.source_opcode) {
6675 case OP_FCONV_TO_I1:
6676 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6678 case OP_FCONV_TO_U1:
6679 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6681 case OP_FCONV_TO_I2:
6682 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6684 case OP_FCONV_TO_U2:
6685 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6691 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6692 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6693 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6696 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6697 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6700 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6701 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6705 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6707 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6708 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6710 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6713 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6714 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6717 case OP_LIVERANGE_START: {
6718 if (cfg->verbose_level > 1)
6719 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6720 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6723 case OP_LIVERANGE_END: {
6724 if (cfg->verbose_level > 1)
6725 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6726 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6729 case OP_GC_SAFE_POINT: {
6730 const char *polling_func = NULL;
6731 int compare_val = 0;
6734 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6735 polling_func = "mono_nacl_gc";
6736 compare_val = 0xFFFFFFFF;
6738 g_assert (mono_threads_is_coop_enabled ());
6739 polling_func = "mono_threads_state_poll";
6743 amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6744 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6745 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6746 amd64_patch (br[0], code);
6750 case OP_GC_LIVENESS_DEF:
6751 case OP_GC_LIVENESS_USE:
6752 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6753 ins->backend.pc_offset = code - cfg->native_code;
6755 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6756 ins->backend.pc_offset = code - cfg->native_code;
6757 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6760 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6761 g_assert_not_reached ();
6764 if ((code - cfg->native_code - offset) > max_len) {
6765 #if !defined(__native_client_codegen__)
6766 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6767 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6768 g_assert_not_reached ();
6773 cfg->code_len = code - cfg->native_code;
6776 #endif /* DISABLE_JIT */
6779 mono_arch_register_lowlevel_calls (void)
6781 /* The signature doesn't matter */
6782 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6786 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6788 unsigned char *ip = ji->ip.i + code;
6791 * Debug code to help track down problems where the target of a near call is
6794 if (amd64_is_near_call (ip)) {
6795 gint64 disp = (guint8*)target - (guint8*)ip;
6797 if (!amd64_is_imm32 (disp)) {
6798 printf ("TYPE: %d\n", ji->type);
6800 case MONO_PATCH_INFO_INTERNAL_METHOD:
6801 printf ("V: %s\n", ji->data.name);
6803 case MONO_PATCH_INFO_METHOD_JUMP:
6804 case MONO_PATCH_INFO_METHOD:
6805 printf ("V: %s\n", ji->data.method->name);
6813 amd64_patch (ip, (gpointer)target);
6819 get_max_epilog_size (MonoCompile *cfg)
6821 int max_epilog_size = 16;
6823 if (cfg->method->save_lmf)
6824 max_epilog_size += 256;
6826 if (mono_jit_trace_calls != NULL)
6827 max_epilog_size += 50;
6829 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6830 max_epilog_size += 50;
6832 max_epilog_size += (AMD64_NREG * 2);
6834 return max_epilog_size;
6838 * This macro is used for testing whenever the unwinder works correctly at every point
6839 * where an async exception can happen.
6841 /* This will generate a SIGSEGV at the given point in the code */
6842 #define async_exc_point(code) do { \
6843 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6844 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6845 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6846 cfg->arch.async_point_count ++; \
6851 mono_arch_emit_prolog (MonoCompile *cfg)
6853 MonoMethod *method = cfg->method;
6855 MonoMethodSignature *sig;
6857 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6860 MonoInst *lmf_var = cfg->lmf_var;
6861 gboolean args_clobbered = FALSE;
6862 gboolean trace = FALSE;
6863 #ifdef __native_client_codegen__
6864 guint alignment_check;
6867 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6869 #if defined(__default_codegen__)
6870 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6871 #elif defined(__native_client_codegen__)
6872 /* native_code_alloc is not 32-byte aligned, native_code is. */
6873 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6875 /* Align native_code to next nearest kNaclAlignment byte. */
6876 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6877 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6879 code = cfg->native_code;
6881 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6882 g_assert (alignment_check == 0);
6885 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6888 /* Amount of stack space allocated by register saving code */
6891 /* Offset between RSP and the CFA */
6895 * The prolog consists of the following parts:
6897 * - push rbp, mov rbp, rsp
6898 * - save callee saved regs using pushes
6900 * - save rgctx if needed
6901 * - save lmf if needed
6904 * - save rgctx if needed
6905 * - save lmf if needed
6906 * - save callee saved regs using moves
6911 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6912 // IP saved at CFA - 8
6913 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6914 async_exc_point (code);
6915 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6917 if (!cfg->arch.omit_fp) {
6918 amd64_push_reg (code, AMD64_RBP);
6920 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6921 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6922 async_exc_point (code);
6924 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6926 /* These are handled automatically by the stack marking code */
6927 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6929 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6930 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6931 async_exc_point (code);
6933 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6937 /* The param area is always at offset 0 from sp */
6938 /* This needs to be allocated here, since it has to come after the spill area */
6939 if (cfg->param_area) {
6940 if (cfg->arch.omit_fp)
6942 g_assert_not_reached ();
6943 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6946 if (cfg->arch.omit_fp) {
6948 * On enter, the stack is misaligned by the pushing of the return
6949 * address. It is either made aligned by the pushing of %rbp, or by
6952 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6953 if ((alloc_size % 16) == 0) {
6955 /* Mark the padding slot as NOREF */
6956 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6959 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6960 if (cfg->stack_offset != alloc_size) {
6961 /* Mark the padding slot as NOREF */
6962 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6964 cfg->arch.sp_fp_offset = alloc_size;
6968 cfg->arch.stack_alloc_size = alloc_size;
6970 /* Allocate stack frame */
6972 /* See mono_emit_stack_alloc */
6973 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6974 guint32 remaining_size = alloc_size;
6975 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6976 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6977 guint32 offset = code - cfg->native_code;
6978 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6979 while (required_code_size >= (cfg->code_size - offset))
6980 cfg->code_size *= 2;
6981 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6982 code = cfg->native_code + offset;
6983 cfg->stat_code_reallocs++;
6986 while (remaining_size >= 0x1000) {
6987 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6988 if (cfg->arch.omit_fp) {
6989 cfa_offset += 0x1000;
6990 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6992 async_exc_point (code);
6994 if (cfg->arch.omit_fp)
6995 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6998 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6999 remaining_size -= 0x1000;
7001 if (remaining_size) {
7002 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7003 if (cfg->arch.omit_fp) {
7004 cfa_offset += remaining_size;
7005 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7006 async_exc_point (code);
7009 if (cfg->arch.omit_fp)
7010 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7014 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7015 if (cfg->arch.omit_fp) {
7016 cfa_offset += alloc_size;
7017 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7018 async_exc_point (code);
7023 /* Stack alignment check */
7028 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7029 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7030 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7032 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
7033 amd64_breakpoint (code);
7034 amd64_patch (buf, code);
7038 if (mini_get_debug_options ()->init_stacks) {
7039 /* Fill the stack frame with a dummy value to force deterministic behavior */
7041 /* Save registers to the red zone */
7042 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7043 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7045 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7046 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7047 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7050 #if defined(__default_codegen__)
7051 amd64_prefix (code, X86_REP_PREFIX);
7053 #elif defined(__native_client_codegen__)
7054 /* NaCl stos pseudo-instruction */
7055 amd64_codegen_pre (code);
7056 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
7057 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7058 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7059 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7060 amd64_prefix (code, X86_REP_PREFIX);
7062 amd64_codegen_post (code);
7063 #endif /* __native_client_codegen__ */
7065 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7066 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7070 if (method->save_lmf)
7071 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7073 /* Save callee saved registers */
7074 if (cfg->arch.omit_fp) {
7075 save_area_offset = cfg->arch.reg_save_area_offset;
7076 /* Save caller saved registers after sp is adjusted */
7077 /* The registers are saved at the bottom of the frame */
7078 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7080 /* The registers are saved just below the saved rbp */
7081 save_area_offset = cfg->arch.reg_save_area_offset;
7084 for (i = 0; i < AMD64_NREG; ++i) {
7085 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7086 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7088 if (cfg->arch.omit_fp) {
7089 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7090 /* These are handled automatically by the stack marking code */
7091 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7093 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7097 save_area_offset += 8;
7098 async_exc_point (code);
7102 /* store runtime generic context */
7103 if (cfg->rgctx_var) {
7104 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7105 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7107 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7109 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7110 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7113 /* compute max_length in order to use short forward jumps */
7114 max_epilog_size = get_max_epilog_size (cfg);
7115 if (cfg->opt & MONO_OPT_BRANCH) {
7116 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7120 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7122 /* max alignment for loops */
7123 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7124 max_length += LOOP_ALIGNMENT;
7125 #ifdef __native_client_codegen__
7126 /* max alignment for native client */
7127 max_length += kNaClAlignment;
7130 MONO_BB_FOR_EACH_INS (bb, ins) {
7131 #ifdef __native_client_codegen__
7133 int space_in_block = kNaClAlignment -
7134 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7135 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7136 if (space_in_block < max_len && max_len < kNaClAlignment) {
7137 max_length += space_in_block;
7140 #endif /*__native_client_codegen__*/
7141 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7144 /* Take prolog and epilog instrumentation into account */
7145 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7146 max_length += max_epilog_size;
7148 bb->max_length = max_length;
7152 sig = mono_method_signature (method);
7155 cinfo = (CallInfo *)cfg->arch.cinfo;
7157 if (sig->ret->type != MONO_TYPE_VOID) {
7158 /* Save volatile arguments to the stack */
7159 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7160 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7163 /* Keep this in sync with emit_load_volatile_arguments */
7164 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7165 ArgInfo *ainfo = cinfo->args + i;
7167 ins = cfg->args [i];
7169 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7170 /* Unused arguments */
7173 /* Save volatile arguments to the stack */
7174 if (ins->opcode != OP_REGVAR) {
7175 switch (ainfo->storage) {
7181 if (stack_offset & 0x1)
7183 else if (stack_offset & 0x2)
7185 else if (stack_offset & 0x4)
7190 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7193 * Save the original location of 'this',
7194 * get_generic_info_from_stack_frame () needs this to properly look up
7195 * the argument value during the handling of async exceptions.
7197 if (ins == cfg->args [0]) {
7198 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7199 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7203 case ArgInFloatSSEReg:
7204 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7206 case ArgInDoubleSSEReg:
7207 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7209 case ArgValuetypeInReg:
7210 for (quad = 0; quad < 2; quad ++) {
7211 switch (ainfo->pair_storage [quad]) {
7213 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7215 case ArgInFloatSSEReg:
7216 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7218 case ArgInDoubleSSEReg:
7219 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7224 g_assert_not_reached ();
7228 case ArgValuetypeAddrInIReg:
7229 if (ainfo->pair_storage [0] == ArgInIReg)
7230 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7232 case ArgGSharedVtInReg:
7233 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7239 /* Argument allocated to (non-volatile) register */
7240 switch (ainfo->storage) {
7242 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7245 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7248 g_assert_not_reached ();
7251 if (ins == cfg->args [0]) {
7252 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7253 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7258 if (cfg->method->save_lmf)
7259 args_clobbered = TRUE;
7262 args_clobbered = TRUE;
7263 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7266 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7267 args_clobbered = TRUE;
7270 * Optimize the common case of the first bblock making a call with the same
7271 * arguments as the method. This works because the arguments are still in their
7272 * original argument registers.
7273 * FIXME: Generalize this
7275 if (!args_clobbered) {
7276 MonoBasicBlock *first_bb = cfg->bb_entry;
7278 int filter = FILTER_IL_SEQ_POINT;
7280 next = mono_bb_first_inst (first_bb, filter);
7281 if (!next && first_bb->next_bb) {
7282 first_bb = first_bb->next_bb;
7283 next = mono_bb_first_inst (first_bb, filter);
7286 if (first_bb->in_count > 1)
7289 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7290 ArgInfo *ainfo = cinfo->args + i;
7291 gboolean match = FALSE;
7293 ins = cfg->args [i];
7294 if (ins->opcode != OP_REGVAR) {
7295 switch (ainfo->storage) {
7297 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7298 if (next->dreg == ainfo->reg) {
7302 next->opcode = OP_MOVE;
7303 next->sreg1 = ainfo->reg;
7304 /* Only continue if the instruction doesn't change argument regs */
7305 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7315 /* Argument allocated to (non-volatile) register */
7316 switch (ainfo->storage) {
7318 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7329 next = mono_inst_next (next, filter);
7330 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7337 if (cfg->gen_sdb_seq_points) {
7338 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7340 /* Initialize seq_point_info_var */
7341 if (cfg->compile_aot) {
7342 /* Initialize the variable from a GOT slot */
7343 /* Same as OP_AOTCONST */
7344 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7345 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7346 g_assert (info_var->opcode == OP_REGOFFSET);
7347 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7350 if (cfg->compile_aot) {
7351 /* Initialize ss_tramp_var */
7352 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7353 g_assert (ins->opcode == OP_REGOFFSET);
7355 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7356 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7357 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7359 /* Initialize ss_tramp_var */
7360 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7361 g_assert (ins->opcode == OP_REGOFFSET);
7363 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7364 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7366 /* Initialize bp_tramp_var */
7367 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7368 g_assert (ins->opcode == OP_REGOFFSET);
7370 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7371 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7375 cfg->code_len = code - cfg->native_code;
7377 g_assert (cfg->code_len < cfg->code_size);
7383 mono_arch_emit_epilog (MonoCompile *cfg)
7385 MonoMethod *method = cfg->method;
7388 int max_epilog_size;
7390 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7391 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7393 max_epilog_size = get_max_epilog_size (cfg);
7395 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7396 cfg->code_size *= 2;
7397 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7398 cfg->stat_code_reallocs++;
7400 code = cfg->native_code + cfg->code_len;
7402 cfg->has_unwind_info_for_epilog = TRUE;
7404 /* Mark the start of the epilog */
7405 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7407 /* Save the uwind state which is needed by the out-of-line code */
7408 mono_emit_unwind_op_remember_state (cfg, code);
7410 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7411 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7413 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7415 if (method->save_lmf) {
7416 /* check if we need to restore protection of the stack after a stack overflow */
7417 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7419 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7420 /* we load the value in a separate instruction: this mechanism may be
7421 * used later as a safer way to do thread interruption
7423 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7424 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7426 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7427 /* note that the call trampoline will preserve eax/edx */
7428 x86_call_reg (code, X86_ECX);
7429 x86_patch (patch, code);
7431 /* FIXME: maybe save the jit tls in the prolog */
7433 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7434 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7438 /* Restore callee saved regs */
7439 for (i = 0; i < AMD64_NREG; ++i) {
7440 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7441 /* Restore only used_int_regs, not arch.saved_iregs */
7442 if (cfg->used_int_regs & (1 << i)) {
7443 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7444 mono_emit_unwind_op_same_value (cfg, code, i);
7445 async_exc_point (code);
7447 save_area_offset += 8;
7451 /* Load returned vtypes into registers if needed */
7452 cinfo = (CallInfo *)cfg->arch.cinfo;
7453 if (cinfo->ret.storage == ArgValuetypeInReg) {
7454 ArgInfo *ainfo = &cinfo->ret;
7455 MonoInst *inst = cfg->ret;
7457 for (quad = 0; quad < 2; quad ++) {
7458 switch (ainfo->pair_storage [quad]) {
7460 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7462 case ArgInFloatSSEReg:
7463 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7465 case ArgInDoubleSSEReg:
7466 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7471 g_assert_not_reached ();
7476 if (cfg->arch.omit_fp) {
7477 if (cfg->arch.stack_alloc_size) {
7478 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7482 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7484 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7485 async_exc_point (code);
7488 /* Restore the unwind state to be the same as before the epilog */
7489 mono_emit_unwind_op_restore_state (cfg, code);
7491 cfg->code_len = code - cfg->native_code;
7493 g_assert (cfg->code_len < cfg->code_size);
7497 mono_arch_emit_exceptions (MonoCompile *cfg)
7499 MonoJumpInfo *patch_info;
7502 MonoClass *exc_classes [16];
7503 guint8 *exc_throw_start [16], *exc_throw_end [16];
7504 guint32 code_size = 0;
7506 /* Compute needed space */
7507 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7508 if (patch_info->type == MONO_PATCH_INFO_EXC)
7510 if (patch_info->type == MONO_PATCH_INFO_R8)
7511 code_size += 8 + 15; /* sizeof (double) + alignment */
7512 if (patch_info->type == MONO_PATCH_INFO_R4)
7513 code_size += 4 + 15; /* sizeof (float) + alignment */
7514 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7515 code_size += 8 + 7; /*sizeof (void*) + alignment */
7518 #ifdef __native_client_codegen__
7519 /* Give us extra room on Native Client. This could be */
7520 /* more carefully calculated, but bundle alignment makes */
7521 /* it much trickier, so *2 like other places is good. */
7525 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7526 cfg->code_size *= 2;
7527 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7528 cfg->stat_code_reallocs++;
7531 code = cfg->native_code + cfg->code_len;
7533 /* add code to raise exceptions */
7535 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7536 switch (patch_info->type) {
7537 case MONO_PATCH_INFO_EXC: {
7538 MonoClass *exc_class;
7542 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7544 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7545 throw_ip = patch_info->ip.i;
7547 //x86_breakpoint (code);
7548 /* Find a throw sequence for the same exception class */
7549 for (i = 0; i < nthrows; ++i)
7550 if (exc_classes [i] == exc_class)
7553 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7554 x86_jump_code (code, exc_throw_start [i]);
7555 patch_info->type = MONO_PATCH_INFO_NONE;
7559 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7563 exc_classes [nthrows] = exc_class;
7564 exc_throw_start [nthrows] = code;
7566 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7568 patch_info->type = MONO_PATCH_INFO_NONE;
7570 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7572 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7577 exc_throw_end [nthrows] = code;
7587 g_assert(code < cfg->native_code + cfg->code_size);
7590 /* Handle relocations with RIP relative addressing */
7591 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7592 gboolean remove = FALSE;
7593 guint8 *orig_code = code;
7595 switch (patch_info->type) {
7596 case MONO_PATCH_INFO_R8:
7597 case MONO_PATCH_INFO_R4: {
7598 guint8 *pos, *patch_pos;
7601 /* The SSE opcodes require a 16 byte alignment */
7602 #if defined(__default_codegen__)
7603 code = (guint8*)ALIGN_TO (code, 16);
7604 #elif defined(__native_client_codegen__)
7606 /* Pad this out with HLT instructions */
7607 /* or we can get garbage bytes emitted */
7608 /* which will fail validation */
7609 guint8 *aligned_code;
7610 /* extra align to make room for */
7611 /* mov/push below */
7612 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7613 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7614 /* The technique of hiding data in an */
7615 /* instruction has a problem here: we */
7616 /* need the data aligned to a 16-byte */
7617 /* boundary but the instruction cannot */
7618 /* cross the bundle boundary. so only */
7619 /* odd multiples of 16 can be used */
7620 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7623 while (code < aligned_code) {
7624 *(code++) = 0xf4; /* hlt */
7629 pos = cfg->native_code + patch_info->ip.i;
7630 if (IS_REX (pos [1])) {
7631 patch_pos = pos + 5;
7632 target_pos = code - pos - 9;
7635 patch_pos = pos + 4;
7636 target_pos = code - pos - 8;
7639 if (patch_info->type == MONO_PATCH_INFO_R8) {
7640 #ifdef __native_client_codegen__
7641 /* Hide 64-bit data in a */
7642 /* "mov imm64, r11" instruction. */
7643 /* write it before the start of */
7645 *(code-2) = 0x49; /* prefix */
7646 *(code-1) = 0xbb; /* mov X, %r11 */
7648 *(double*)code = *(double*)patch_info->data.target;
7649 code += sizeof (double);
7651 #ifdef __native_client_codegen__
7652 /* Hide 32-bit data in a */
7653 /* "push imm32" instruction. */
7654 *(code-1) = 0x68; /* push */
7656 *(float*)code = *(float*)patch_info->data.target;
7657 code += sizeof (float);
7660 *(guint32*)(patch_pos) = target_pos;
7665 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7668 if (cfg->compile_aot)
7671 /*loading is faster against aligned addresses.*/
7672 code = (guint8*)ALIGN_TO (code, 8);
7673 memset (orig_code, 0, code - orig_code);
7675 pos = cfg->native_code + patch_info->ip.i;
7677 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7678 if (IS_REX (pos [1]))
7679 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7681 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7683 *(gpointer*)code = (gpointer)patch_info->data.target;
7684 code += sizeof (gpointer);
7694 if (patch_info == cfg->patch_info)
7695 cfg->patch_info = patch_info->next;
7699 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7701 tmp->next = patch_info->next;
7704 g_assert (code < cfg->native_code + cfg->code_size);
7707 cfg->code_len = code - cfg->native_code;
7709 g_assert (cfg->code_len < cfg->code_size);
7713 #endif /* DISABLE_JIT */
7716 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7718 guchar *code = (guchar *)p;
7719 MonoMethodSignature *sig;
7721 int i, n, stack_area = 0;
7723 /* Keep this in sync with mono_arch_get_argument_info */
7725 if (enable_arguments) {
7726 /* Allocate a new area on the stack and save arguments there */
7727 sig = mono_method_signature (cfg->method);
7729 n = sig->param_count + sig->hasthis;
7731 stack_area = ALIGN_TO (n * 8, 16);
7733 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7735 for (i = 0; i < n; ++i) {
7736 inst = cfg->args [i];
7738 if (inst->opcode == OP_REGVAR)
7739 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7741 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7742 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7747 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7748 amd64_set_reg_template (code, AMD64_ARG_REG1);
7749 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7750 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7752 if (enable_arguments)
7753 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7767 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7769 guchar *code = (guchar *)p;
7770 int save_mode = SAVE_NONE;
7771 MonoMethod *method = cfg->method;
7772 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7775 switch (ret_type->type) {
7776 case MONO_TYPE_VOID:
7777 /* special case string .ctor icall */
7778 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7779 save_mode = SAVE_EAX;
7781 save_mode = SAVE_NONE;
7785 save_mode = SAVE_EAX;
7789 save_mode = SAVE_XMM;
7791 case MONO_TYPE_GENERICINST:
7792 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7793 save_mode = SAVE_EAX;
7797 case MONO_TYPE_VALUETYPE:
7798 save_mode = SAVE_STRUCT;
7801 save_mode = SAVE_EAX;
7805 /* Save the result and copy it into the proper argument register */
7806 switch (save_mode) {
7808 amd64_push_reg (code, AMD64_RAX);
7810 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7811 if (enable_arguments)
7812 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7816 if (enable_arguments)
7817 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7820 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7821 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7823 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7825 * The result is already in the proper argument register so no copying
7832 g_assert_not_reached ();
7835 /* Set %al since this is a varargs call */
7836 if (save_mode == SAVE_XMM)
7837 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7839 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7841 if (preserve_argument_registers) {
7842 for (i = 0; i < PARAM_REGS; ++i)
7843 amd64_push_reg (code, param_regs [i]);
7846 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7847 amd64_set_reg_template (code, AMD64_ARG_REG1);
7848 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7850 if (preserve_argument_registers) {
7851 for (i = PARAM_REGS - 1; i >= 0; --i)
7852 amd64_pop_reg (code, param_regs [i]);
7855 /* Restore result */
7856 switch (save_mode) {
7858 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7859 amd64_pop_reg (code, AMD64_RAX);
7865 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7866 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7867 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7872 g_assert_not_reached ();
7879 mono_arch_flush_icache (guint8 *code, gint size)
7885 mono_arch_flush_register_windows (void)
7890 mono_arch_is_inst_imm (gint64 imm)
7892 return amd64_use_imm32 (imm);
7896 * Determine whenever the trap whose info is in SIGINFO is caused by
7900 mono_arch_is_int_overflow (void *sigctx, void *info)
7907 mono_sigctx_to_monoctx (sigctx, &ctx);
7909 rip = (guint8*)ctx.gregs [AMD64_RIP];
7911 if (IS_REX (rip [0])) {
7912 reg = amd64_rex_b (rip [0]);
7918 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7920 reg += x86_modrm_rm (rip [1]);
7922 value = ctx.gregs [reg];
7932 mono_arch_get_patch_offset (guint8 *code)
7938 * mono_breakpoint_clean_code:
7940 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7941 * breakpoints in the original code, they are removed in the copy.
7943 * Returns TRUE if no sw breakpoint was present.
7946 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7949 * If method_start is non-NULL we need to perform bound checks, since we access memory
7950 * at code - offset we could go before the start of the method and end up in a different
7951 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7954 if (!method_start || code - offset >= method_start) {
7955 memcpy (buf, code - offset, size);
7957 int diff = code - method_start;
7958 memset (buf, 0, size);
7959 memcpy (buf + offset - diff, method_start, diff + size - offset);
7964 #if defined(__native_client_codegen__)
7965 /* For membase calls, we want the base register. for Native Client, */
7966 /* all indirect calls have the following sequence with the given sizes: */
7967 /* mov %eXX,%eXX [2-3] */
7968 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7969 /* and $0xffffffffffffffe0,%r11d [4] */
7970 /* add %r15,%r11 [3] */
7971 /* callq *%r11 [3] */
7974 /* Determine if code points to a NaCl call-through-register sequence, */
7975 /* (i.e., the last 3 instructions listed above) */
7977 is_nacl_call_reg_sequence(guint8* code)
7979 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7980 "\x4d\x03\xdf" /* add */
7981 "\x41\xff\xd3"; /* call */
7982 return memcmp(code, sequence, 10) == 0;
7985 /* Determine if code points to the first opcode of the mov membase component */
7986 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7987 /* (there could be a REX prefix before the opcode but it is ignored) */
7989 is_nacl_indirect_call_membase_sequence(guint8* code)
7991 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7992 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7993 /* and that src reg = dest reg */
7994 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7995 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7997 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7998 /* and has dst of r11 and base of r15 */
7999 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8000 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8002 #endif /* __native_client_codegen__ */
8005 mono_arch_get_this_arg_reg (guint8 *code)
8007 return AMD64_ARG_REG1;
8011 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8013 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8016 #define MAX_ARCH_DELEGATE_PARAMS 10
8019 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8021 guint8 *code, *start;
8022 GSList *unwind_ops = NULL;
8025 unwind_ops = mono_arch_get_cie_program ();
8028 start = code = (guint8 *)mono_global_codeman_reserve (64);
8030 /* Replace the this argument with the target */
8031 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8032 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8033 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8035 g_assert ((code - start) < 64);
8037 start = code = (guint8 *)mono_global_codeman_reserve (64);
8039 if (param_count == 0) {
8040 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8042 /* We have to shift the arguments left */
8043 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8044 for (i = 0; i < param_count; ++i) {
8047 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8049 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8051 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8055 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8057 g_assert ((code - start) < 64);
8060 nacl_global_codeman_validate (&start, 64, &code);
8061 mono_arch_flush_icache (start, code - start);
8064 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8066 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8067 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8071 if (mono_jit_map_is_enabled ()) {
8074 buff = (char*)"delegate_invoke_has_target";
8076 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8077 mono_emit_jit_tramp (start, code - start, buff);
8081 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8086 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8089 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8091 guint8 *code, *start;
8096 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8099 start = code = (guint8 *)mono_global_codeman_reserve (size);
8101 unwind_ops = mono_arch_get_cie_program ();
8103 /* Replace the this argument with the target */
8104 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8105 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8108 /* Load the IMT reg */
8109 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8112 /* Load the vtable */
8113 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8114 amd64_jump_membase (code, AMD64_RAX, offset);
8115 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8118 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8120 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8121 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8122 g_free (tramp_name);
8128 * mono_arch_get_delegate_invoke_impls:
8130 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8134 mono_arch_get_delegate_invoke_impls (void)
8137 MonoTrampInfo *info;
8140 get_delegate_invoke_impl (&info, TRUE, 0);
8141 res = g_slist_prepend (res, info);
8143 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8144 get_delegate_invoke_impl (&info, FALSE, i);
8145 res = g_slist_prepend (res, info);
8148 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8149 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8150 res = g_slist_prepend (res, info);
8152 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8153 res = g_slist_prepend (res, info);
8160 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8162 guint8 *code, *start;
8165 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8168 /* FIXME: Support more cases */
8169 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8173 static guint8* cached = NULL;
8178 if (mono_aot_only) {
8179 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8181 MonoTrampInfo *info;
8182 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8183 mono_tramp_info_register (info, NULL);
8186 mono_memory_barrier ();
8190 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8191 for (i = 0; i < sig->param_count; ++i)
8192 if (!mono_is_regsize_var (sig->params [i]))
8194 if (sig->param_count > 4)
8197 code = cache [sig->param_count];
8201 if (mono_aot_only) {
8202 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8203 start = (guint8 *)mono_aot_get_trampoline (name);
8206 MonoTrampInfo *info;
8207 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8208 mono_tramp_info_register (info, NULL);
8211 mono_memory_barrier ();
8213 cache [sig->param_count] = start;
8220 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8222 MonoTrampInfo *info;
8225 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8227 mono_tramp_info_register (info, NULL);
8232 mono_arch_finish_init (void)
8234 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8235 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8240 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8244 #if defined(__default_codegen__)
8245 #define CMP_SIZE (6 + 1)
8246 #define CMP_REG_REG_SIZE (4 + 1)
8247 #define BR_SMALL_SIZE 2
8248 #define BR_LARGE_SIZE 6
8249 #define MOV_REG_IMM_SIZE 10
8250 #define MOV_REG_IMM_32BIT_SIZE 6
8251 #define JUMP_REG_SIZE (2 + 1)
8252 #elif defined(__native_client_codegen__)
8253 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8254 #define CMP_SIZE ((6 + 1) * 2 - 1)
8255 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8256 #define BR_SMALL_SIZE (2 * 2 - 1)
8257 #define BR_LARGE_SIZE (6 * 2 - 1)
8258 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8259 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8260 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8261 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8262 /* Jump membase's size is large and unpredictable */
8263 /* in native client, just pad it out a whole bundle. */
8264 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8268 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8270 int i, distance = 0;
8271 for (i = start; i < target; ++i)
8272 distance += imt_entries [i]->chunk_size;
8277 * LOCKING: called with the domain lock held
8280 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8281 gpointer fail_tramp)
8285 guint8 *code, *start;
8286 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8289 for (i = 0; i < count; ++i) {
8290 MonoIMTCheckItem *item = imt_entries [i];
8291 if (item->is_equals) {
8292 if (item->check_target_idx) {
8293 if (!item->compare_done) {
8294 if (amd64_use_imm32 ((gint64)item->key))
8295 item->chunk_size += CMP_SIZE;
8297 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8299 if (item->has_target_code) {
8300 item->chunk_size += MOV_REG_IMM_SIZE;
8302 if (vtable_is_32bit)
8303 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8305 item->chunk_size += MOV_REG_IMM_SIZE;
8306 #ifdef __native_client_codegen__
8307 item->chunk_size += JUMP_MEMBASE_SIZE;
8310 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8313 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8314 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8316 if (vtable_is_32bit)
8317 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8319 item->chunk_size += MOV_REG_IMM_SIZE;
8320 item->chunk_size += JUMP_REG_SIZE;
8321 /* with assert below:
8322 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8324 #ifdef __native_client_codegen__
8325 item->chunk_size += JUMP_MEMBASE_SIZE;
8330 if (amd64_use_imm32 ((gint64)item->key))
8331 item->chunk_size += CMP_SIZE;
8333 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8334 item->chunk_size += BR_LARGE_SIZE;
8335 imt_entries [item->check_target_idx]->compare_done = TRUE;
8337 size += item->chunk_size;
8339 #if defined(__native_client__) && defined(__native_client_codegen__)
8340 /* In Native Client, we don't re-use thunks, allocate from the */
8341 /* normal code manager paths. */
8342 code = mono_domain_code_reserve (domain, size);
8345 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8347 code = (guint8 *)mono_domain_code_reserve (domain, size);
8351 unwind_ops = mono_arch_get_cie_program ();
8353 for (i = 0; i < count; ++i) {
8354 MonoIMTCheckItem *item = imt_entries [i];
8355 item->code_target = code;
8356 if (item->is_equals) {
8357 gboolean fail_case = !item->check_target_idx && fail_tramp;
8359 if (item->check_target_idx || fail_case) {
8360 if (!item->compare_done || fail_case) {
8361 if (amd64_use_imm32 ((gint64)item->key))
8362 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8364 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8365 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8368 item->jmp_code = code;
8369 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8370 if (item->has_target_code) {
8371 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8372 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8374 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8375 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8379 amd64_patch (item->jmp_code, code);
8380 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8381 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8382 item->jmp_code = NULL;
8385 /* enable the commented code to assert on wrong method */
8387 if (amd64_is_imm32 (item->key))
8388 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8390 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8391 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8393 item->jmp_code = code;
8394 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8395 /* See the comment below about R10 */
8396 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8397 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8398 amd64_patch (item->jmp_code, code);
8399 amd64_breakpoint (code);
8400 item->jmp_code = NULL;
8402 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8403 needs to be preserved. R10 needs
8404 to be preserved for calls which
8405 require a runtime generic context,
8406 but interface calls don't. */
8407 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8408 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8412 if (amd64_use_imm32 ((gint64)item->key))
8413 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8415 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8416 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8418 item->jmp_code = code;
8419 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8420 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8422 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8424 g_assert (code - item->code_target <= item->chunk_size);
8426 /* patch the branches to get to the target items */
8427 for (i = 0; i < count; ++i) {
8428 MonoIMTCheckItem *item = imt_entries [i];
8429 if (item->jmp_code) {
8430 if (item->check_target_idx) {
8431 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8437 mono_stats.imt_thunks_size += code - start;
8438 g_assert (code - start <= size);
8440 nacl_domain_code_validate(domain, &start, size, &code);
8441 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8443 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8449 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8451 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8455 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8457 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8461 mono_arch_get_cie_program (void)
8465 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8466 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8474 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8476 MonoInst *ins = NULL;
8479 if (cmethod->klass == mono_defaults.math_class) {
8480 if (strcmp (cmethod->name, "Sin") == 0) {
8482 } else if (strcmp (cmethod->name, "Cos") == 0) {
8484 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8486 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8490 if (opcode && fsig->param_count == 1) {
8491 MONO_INST_NEW (cfg, ins, opcode);
8492 ins->type = STACK_R8;
8493 ins->dreg = mono_alloc_freg (cfg);
8494 ins->sreg1 = args [0]->dreg;
8495 MONO_ADD_INS (cfg->cbb, ins);
8499 if (cfg->opt & MONO_OPT_CMOV) {
8500 if (strcmp (cmethod->name, "Min") == 0) {
8501 if (fsig->params [0]->type == MONO_TYPE_I4)
8503 if (fsig->params [0]->type == MONO_TYPE_U4)
8504 opcode = OP_IMIN_UN;
8505 else if (fsig->params [0]->type == MONO_TYPE_I8)
8507 else if (fsig->params [0]->type == MONO_TYPE_U8)
8508 opcode = OP_LMIN_UN;
8509 } else if (strcmp (cmethod->name, "Max") == 0) {
8510 if (fsig->params [0]->type == MONO_TYPE_I4)
8512 if (fsig->params [0]->type == MONO_TYPE_U4)
8513 opcode = OP_IMAX_UN;
8514 else if (fsig->params [0]->type == MONO_TYPE_I8)
8516 else if (fsig->params [0]->type == MONO_TYPE_U8)
8517 opcode = OP_LMAX_UN;
8521 if (opcode && fsig->param_count == 2) {
8522 MONO_INST_NEW (cfg, ins, opcode);
8523 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8524 ins->dreg = mono_alloc_ireg (cfg);
8525 ins->sreg1 = args [0]->dreg;
8526 ins->sreg2 = args [1]->dreg;
8527 MONO_ADD_INS (cfg->cbb, ins);
8531 /* OP_FREM is not IEEE compatible */
8532 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8533 MONO_INST_NEW (cfg, ins, OP_FREM);
8534 ins->inst_i0 = args [0];
8535 ins->inst_i1 = args [1];
8545 mono_arch_print_tree (MonoInst *tree, int arity)
8551 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8553 return ctx->gregs [reg];
8557 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8559 ctx->gregs [reg] = val;
8563 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8565 gpointer *sp, old_value;
8569 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8570 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8573 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8582 * mono_arch_emit_load_aotconst:
8584 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8585 * TARGET from the mscorlib GOT in full-aot code.
8586 * On AMD64, the result is placed into R11.
8589 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8591 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8592 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8598 * mono_arch_get_trampolines:
8600 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8604 mono_arch_get_trampolines (gboolean aot)
8606 return mono_amd64_get_exception_trampolines (aot);
8609 /* Soft Debug support */
8610 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8613 * mono_arch_set_breakpoint:
8615 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8616 * The location should contain code emitted by OP_SEQ_POINT.
8619 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8624 guint32 native_offset = ip - (guint8*)ji->code_start;
8625 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8627 g_assert (info->bp_addrs [native_offset] == 0);
8628 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8630 /* ip points to a mov r11, 0 */
8631 g_assert (code [0] == 0x41);
8632 g_assert (code [1] == 0xbb);
8633 amd64_mov_reg_imm (code, AMD64_R11, 1);
8638 * mono_arch_clear_breakpoint:
8640 * Clear the breakpoint at IP.
8643 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8648 guint32 native_offset = ip - (guint8*)ji->code_start;
8649 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8651 info->bp_addrs [native_offset] = NULL;
8653 amd64_mov_reg_imm (code, AMD64_R11, 0);
8658 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8660 /* We use soft breakpoints on amd64 */
8665 * mono_arch_skip_breakpoint:
8667 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8668 * we resume, the instruction is not executed again.
8671 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8673 g_assert_not_reached ();
8677 * mono_arch_start_single_stepping:
8679 * Start single stepping.
8682 mono_arch_start_single_stepping (void)
8684 ss_trampoline = mini_get_single_step_trampoline ();
8688 * mono_arch_stop_single_stepping:
8690 * Stop single stepping.
8693 mono_arch_stop_single_stepping (void)
8695 ss_trampoline = NULL;
8699 * mono_arch_is_single_step_event:
8701 * Return whenever the machine state in SIGCTX corresponds to a single
8705 mono_arch_is_single_step_event (void *info, void *sigctx)
8707 /* We use soft breakpoints on amd64 */
8712 * mono_arch_skip_single_step:
8714 * Modify CTX so the ip is placed after the single step trigger instruction,
8715 * we resume, the instruction is not executed again.
8718 mono_arch_skip_single_step (MonoContext *ctx)
8720 g_assert_not_reached ();
8724 * mono_arch_create_seq_point_info:
8726 * Return a pointer to a data structure which is used by the sequence
8727 * point implementation in AOTed code.
8730 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8735 // FIXME: Add a free function
8737 mono_domain_lock (domain);
8738 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8740 mono_domain_unlock (domain);
8743 ji = mono_jit_info_table_find (domain, (char*)code);
8746 // FIXME: Optimize the size
8747 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8749 info->ss_tramp_addr = &ss_trampoline;
8751 mono_domain_lock (domain);
8752 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8754 mono_domain_unlock (domain);
8761 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8763 ext->lmf.previous_lmf = prev_lmf;
8764 /* Mark that this is a MonoLMFExt */
8765 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8766 ext->lmf.rsp = (gssize)ext;
8772 mono_arch_opcode_supported (int opcode)
8775 case OP_ATOMIC_ADD_I4:
8776 case OP_ATOMIC_ADD_I8:
8777 case OP_ATOMIC_EXCHANGE_I4:
8778 case OP_ATOMIC_EXCHANGE_I8:
8779 case OP_ATOMIC_CAS_I4:
8780 case OP_ATOMIC_CAS_I8:
8781 case OP_ATOMIC_LOAD_I1:
8782 case OP_ATOMIC_LOAD_I2:
8783 case OP_ATOMIC_LOAD_I4:
8784 case OP_ATOMIC_LOAD_I8:
8785 case OP_ATOMIC_LOAD_U1:
8786 case OP_ATOMIC_LOAD_U2:
8787 case OP_ATOMIC_LOAD_U4:
8788 case OP_ATOMIC_LOAD_U8:
8789 case OP_ATOMIC_LOAD_R4:
8790 case OP_ATOMIC_LOAD_R8:
8791 case OP_ATOMIC_STORE_I1:
8792 case OP_ATOMIC_STORE_I2:
8793 case OP_ATOMIC_STORE_I4:
8794 case OP_ATOMIC_STORE_I8:
8795 case OP_ATOMIC_STORE_U1:
8796 case OP_ATOMIC_STORE_U2:
8797 case OP_ATOMIC_STORE_U4:
8798 case OP_ATOMIC_STORE_U8:
8799 case OP_ATOMIC_STORE_R4:
8800 case OP_ATOMIC_STORE_R8:
8808 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8810 return get_call_info (mp, sig);