2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-mmap.h>
31 #include "mini-amd64.h"
32 #include "cpu-amd64.h"
33 #include "debugger-agent.h"
36 * Can't define this in mini-amd64.h cause that would turn on the generic code in
39 #define MONO_ARCH_IMT_REG AMD64_R11
41 static gint lmf_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
43 static gint appdomain_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
67 static CRITICAL_SECTION mini_arch_mutex;
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 * The code generated for sequence points reads from this location, which is
74 * made read-only when single stepping is enabled.
76 static gpointer ss_trigger_page;
78 /* Enabled breakpoints read from this trigger page */
79 static gpointer bp_trigger_page;
81 /* The size of the breakpoint sequence */
82 static int breakpoint_size;
84 /* The size of the breakpoint instruction causing the actual fault */
85 static int breakpoint_fault_size;
87 /* The size of the single step instruction causing the actual fault */
88 static int single_step_fault_size;
91 /* On Win64 always reserve first 32 bytes for first four arguments */
92 #define ARGS_OFFSET 48
94 #define ARGS_OFFSET 16
96 #define GP_SCRATCH_REG AMD64_R11
99 * AMD64 register usage:
100 * - callee saved registers are used for global register allocation
101 * - %r11 is used for materializing 64 bit constants in opcodes
102 * - the rest is used for local allocation
106 * Floating point comparison results:
116 mono_arch_regname (int reg)
119 case AMD64_RAX: return "%rax";
120 case AMD64_RBX: return "%rbx";
121 case AMD64_RCX: return "%rcx";
122 case AMD64_RDX: return "%rdx";
123 case AMD64_RSP: return "%rsp";
124 case AMD64_RBP: return "%rbp";
125 case AMD64_RDI: return "%rdi";
126 case AMD64_RSI: return "%rsi";
127 case AMD64_R8: return "%r8";
128 case AMD64_R9: return "%r9";
129 case AMD64_R10: return "%r10";
130 case AMD64_R11: return "%r11";
131 case AMD64_R12: return "%r12";
132 case AMD64_R13: return "%r13";
133 case AMD64_R14: return "%r14";
134 case AMD64_R15: return "%r15";
139 static const char * packed_xmmregs [] = {
140 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
141 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
144 static const char * single_xmmregs [] = {
145 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
146 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
150 mono_arch_fregname (int reg)
152 if (reg < AMD64_XMM_NREG)
153 return single_xmmregs [reg];
159 mono_arch_xregname (int reg)
161 if (reg < AMD64_XMM_NREG)
162 return packed_xmmregs [reg];
167 G_GNUC_UNUSED static void
172 G_GNUC_UNUSED static gboolean
175 static int count = 0;
178 if (!getenv ("COUNT"))
181 if (count == atoi (getenv ("COUNT"))) {
185 if (count > atoi (getenv ("COUNT"))) {
196 return debug_count ();
202 static inline gboolean
203 amd64_is_near_call (guint8 *code)
206 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
209 return code [0] == 0xe8;
213 amd64_patch (unsigned char* code, gpointer target)
218 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
223 if ((code [0] & 0xf8) == 0xb8) {
224 /* amd64_set_reg_template */
225 *(guint64*)(code + 1) = (guint64)target;
227 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
228 /* mov 0(%rip), %dreg */
229 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
231 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
232 /* call *<OFFSET>(%rip) */
233 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
235 else if ((code [0] == 0xe8)) {
237 gint64 disp = (guint8*)target - (guint8*)code;
238 g_assert (amd64_is_imm32 (disp));
239 x86_patch (code, (unsigned char*)target);
242 x86_patch (code, (unsigned char*)target);
246 mono_amd64_patch (unsigned char* code, gpointer target)
248 amd64_patch (code, target);
257 ArgValuetypeAddrInIReg,
258 ArgNone /* only in pair_storage */
266 /* Only if storage == ArgValuetypeInReg */
267 ArgStorage pair_storage [2];
276 gboolean need_stack_align;
277 gboolean vtype_retaddr;
283 #define DEBUG(a) if (cfg->verbose_level > 1) a
288 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
290 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
294 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
296 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
300 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
302 ainfo->offset = *stack_size;
304 if (*gr >= PARAM_REGS) {
305 ainfo->storage = ArgOnStack;
306 (*stack_size) += sizeof (gpointer);
309 ainfo->storage = ArgInIReg;
310 ainfo->reg = param_regs [*gr];
316 #define FLOAT_PARAM_REGS 4
318 #define FLOAT_PARAM_REGS 8
322 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
324 ainfo->offset = *stack_size;
326 if (*gr >= FLOAT_PARAM_REGS) {
327 ainfo->storage = ArgOnStack;
328 (*stack_size) += sizeof (gpointer);
331 /* A double register */
333 ainfo->storage = ArgInDoubleSSEReg;
335 ainfo->storage = ArgInFloatSSEReg;
341 typedef enum ArgumentClass {
349 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
351 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
354 ptype = mini_type_get_underlying_type (NULL, type);
355 switch (ptype->type) {
356 case MONO_TYPE_BOOLEAN:
366 case MONO_TYPE_STRING:
367 case MONO_TYPE_OBJECT:
368 case MONO_TYPE_CLASS:
369 case MONO_TYPE_SZARRAY:
371 case MONO_TYPE_FNPTR:
372 case MONO_TYPE_ARRAY:
375 class2 = ARG_CLASS_INTEGER;
380 class2 = ARG_CLASS_INTEGER;
382 class2 = ARG_CLASS_SSE;
386 case MONO_TYPE_TYPEDBYREF:
387 g_assert_not_reached ();
389 case MONO_TYPE_GENERICINST:
390 if (!mono_type_generic_inst_is_valuetype (ptype)) {
391 class2 = ARG_CLASS_INTEGER;
395 case MONO_TYPE_VALUETYPE: {
396 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
399 for (i = 0; i < info->num_fields; ++i) {
401 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
406 g_assert_not_reached ();
410 if (class1 == class2)
412 else if (class1 == ARG_CLASS_NO_CLASS)
414 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
415 class1 = ARG_CLASS_MEMORY;
416 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
417 class1 = ARG_CLASS_INTEGER;
419 class1 = ARG_CLASS_SSE;
425 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
427 guint32 *gr, guint32 *fr, guint32 *stack_size)
429 guint32 size, quad, nquads, i;
430 ArgumentClass args [2];
431 MonoMarshalType *info = NULL;
433 MonoGenericSharingContext tmp_gsctx;
434 gboolean pass_on_stack = FALSE;
437 * The gsctx currently contains no data, it is only used for checking whenever
438 * open types are allowed, some callers like mono_arch_get_argument_info ()
439 * don't pass it to us, so work around that.
444 klass = mono_class_from_mono_type (type);
445 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
447 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
448 /* We pass and return vtypes of size 8 in a register */
449 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
450 pass_on_stack = TRUE;
454 pass_on_stack = TRUE;
459 /* Allways pass in memory */
460 ainfo->offset = *stack_size;
461 *stack_size += ALIGN_TO (size, 8);
462 ainfo->storage = ArgOnStack;
467 /* FIXME: Handle structs smaller than 8 bytes */
468 //if ((size % 8) != 0)
477 /* Always pass in 1 or 2 integer registers */
478 args [0] = ARG_CLASS_INTEGER;
479 args [1] = ARG_CLASS_INTEGER;
480 /* Only the simplest cases are supported */
481 if (is_return && nquads != 1) {
482 args [0] = ARG_CLASS_MEMORY;
483 args [1] = ARG_CLASS_MEMORY;
487 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
488 * The X87 and SSEUP stuff is left out since there are no such types in
491 info = mono_marshal_load_type_info (klass);
495 if (info->native_size > 16) {
496 ainfo->offset = *stack_size;
497 *stack_size += ALIGN_TO (info->native_size, 8);
498 ainfo->storage = ArgOnStack;
503 switch (info->native_size) {
504 case 1: case 2: case 4: case 8:
508 ainfo->storage = ArgOnStack;
509 ainfo->offset = *stack_size;
510 *stack_size += ALIGN_TO (info->native_size, 8);
513 ainfo->storage = ArgValuetypeAddrInIReg;
515 if (*gr < PARAM_REGS) {
516 ainfo->pair_storage [0] = ArgInIReg;
517 ainfo->pair_regs [0] = param_regs [*gr];
521 ainfo->pair_storage [0] = ArgOnStack;
522 ainfo->offset = *stack_size;
531 args [0] = ARG_CLASS_NO_CLASS;
532 args [1] = ARG_CLASS_NO_CLASS;
533 for (quad = 0; quad < nquads; ++quad) {
536 ArgumentClass class1;
538 if (info->num_fields == 0)
539 class1 = ARG_CLASS_MEMORY;
541 class1 = ARG_CLASS_NO_CLASS;
542 for (i = 0; i < info->num_fields; ++i) {
543 size = mono_marshal_type_size (info->fields [i].field->type,
544 info->fields [i].mspec,
545 &align, TRUE, klass->unicode);
546 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
547 /* Unaligned field */
551 /* Skip fields in other quad */
552 if ((quad == 0) && (info->fields [i].offset >= 8))
554 if ((quad == 1) && (info->fields [i].offset < 8))
557 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
559 g_assert (class1 != ARG_CLASS_NO_CLASS);
560 args [quad] = class1;
564 /* Post merger cleanup */
565 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
566 args [0] = args [1] = ARG_CLASS_MEMORY;
568 /* Allocate registers */
573 ainfo->storage = ArgValuetypeInReg;
574 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
575 for (quad = 0; quad < nquads; ++quad) {
576 switch (args [quad]) {
577 case ARG_CLASS_INTEGER:
578 if (*gr >= PARAM_REGS)
579 args [quad] = ARG_CLASS_MEMORY;
581 ainfo->pair_storage [quad] = ArgInIReg;
583 ainfo->pair_regs [quad] = return_regs [*gr];
585 ainfo->pair_regs [quad] = param_regs [*gr];
590 if (*fr >= FLOAT_PARAM_REGS)
591 args [quad] = ARG_CLASS_MEMORY;
593 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
594 ainfo->pair_regs [quad] = *fr;
598 case ARG_CLASS_MEMORY:
601 g_assert_not_reached ();
605 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
606 /* Revert possible register assignments */
610 ainfo->offset = *stack_size;
612 *stack_size += ALIGN_TO (info->native_size, 8);
614 *stack_size += nquads * sizeof (gpointer);
615 ainfo->storage = ArgOnStack;
623 * Obtain information about a call according to the calling convention.
624 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
625 * Draft Version 0.23" document for more information.
628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
632 int n = sig->hasthis + sig->param_count;
633 guint32 stack_size = 0;
637 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
639 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
648 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
649 switch (ret_type->type) {
650 case MONO_TYPE_BOOLEAN:
661 case MONO_TYPE_FNPTR:
662 case MONO_TYPE_CLASS:
663 case MONO_TYPE_OBJECT:
664 case MONO_TYPE_SZARRAY:
665 case MONO_TYPE_ARRAY:
666 case MONO_TYPE_STRING:
667 cinfo->ret.storage = ArgInIReg;
668 cinfo->ret.reg = AMD64_RAX;
672 cinfo->ret.storage = ArgInIReg;
673 cinfo->ret.reg = AMD64_RAX;
676 cinfo->ret.storage = ArgInFloatSSEReg;
677 cinfo->ret.reg = AMD64_XMM0;
680 cinfo->ret.storage = ArgInDoubleSSEReg;
681 cinfo->ret.reg = AMD64_XMM0;
683 case MONO_TYPE_GENERICINST:
684 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
685 cinfo->ret.storage = ArgInIReg;
686 cinfo->ret.reg = AMD64_RAX;
690 case MONO_TYPE_VALUETYPE: {
691 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
693 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
694 if (cinfo->ret.storage == ArgOnStack) {
695 cinfo->vtype_retaddr = TRUE;
696 /* The caller passes the address where the value is stored */
697 add_general (&gr, &stack_size, &cinfo->ret);
701 case MONO_TYPE_TYPEDBYREF:
702 /* Same as a valuetype with size 24 */
703 add_general (&gr, &stack_size, &cinfo->ret);
709 g_error ("Can't handle as return value 0x%x", sig->ret->type);
715 add_general (&gr, &stack_size, cinfo->args + 0);
717 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
719 fr = FLOAT_PARAM_REGS;
721 /* Emit the signature cookie just before the implicit arguments */
722 add_general (&gr, &stack_size, &cinfo->sig_cookie);
725 for (i = 0; i < sig->param_count; ++i) {
726 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
730 /* The float param registers and other param registers must be the same index on Windows x64.*/
737 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
738 /* We allways pass the sig cookie on the stack for simplicity */
740 * Prevent implicit arguments + the sig cookie from being passed
744 fr = FLOAT_PARAM_REGS;
746 /* Emit the signature cookie just before the implicit arguments */
747 add_general (&gr, &stack_size, &cinfo->sig_cookie);
750 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
751 switch (ptype->type) {
752 case MONO_TYPE_BOOLEAN:
755 add_general (&gr, &stack_size, ainfo);
760 add_general (&gr, &stack_size, ainfo);
764 add_general (&gr, &stack_size, ainfo);
769 case MONO_TYPE_FNPTR:
770 case MONO_TYPE_CLASS:
771 case MONO_TYPE_OBJECT:
772 case MONO_TYPE_STRING:
773 case MONO_TYPE_SZARRAY:
774 case MONO_TYPE_ARRAY:
775 add_general (&gr, &stack_size, ainfo);
777 case MONO_TYPE_GENERICINST:
778 if (!mono_type_generic_inst_is_valuetype (ptype)) {
779 add_general (&gr, &stack_size, ainfo);
783 case MONO_TYPE_VALUETYPE:
784 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
786 case MONO_TYPE_TYPEDBYREF:
788 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
790 stack_size += sizeof (MonoTypedRef);
791 ainfo->storage = ArgOnStack;
796 add_general (&gr, &stack_size, ainfo);
799 add_float (&fr, &stack_size, ainfo, FALSE);
802 add_float (&fr, &stack_size, ainfo, TRUE);
805 g_assert_not_reached ();
809 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
811 fr = FLOAT_PARAM_REGS;
813 /* Emit the signature cookie just before the implicit arguments */
814 add_general (&gr, &stack_size, &cinfo->sig_cookie);
818 // There always is 32 bytes reserved on the stack when calling on Winx64
822 if (stack_size & 0x8) {
823 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
824 cinfo->need_stack_align = TRUE;
828 cinfo->stack_usage = stack_size;
829 cinfo->reg_usage = gr;
830 cinfo->freg_usage = fr;
835 * mono_arch_get_argument_info:
836 * @csig: a method signature
837 * @param_count: the number of parameters to consider
838 * @arg_info: an array to store the result infos
840 * Gathers information on parameters such as size, alignment and
841 * padding. arg_info should be large enought to hold param_count + 1 entries.
843 * Returns the size of the argument area on the stack.
846 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
849 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
850 guint32 args_size = cinfo->stack_usage;
852 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
854 arg_info [0].offset = 0;
857 for (k = 0; k < param_count; k++) {
858 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
860 arg_info [k + 1].size = 0;
869 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
872 __asm__ __volatile__ ("cpuid"
873 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
887 * Initialize the cpu to execute managed code.
890 mono_arch_cpu_init (void)
895 /* spec compliance requires running with double precision */
896 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
897 fpcw &= ~X86_FPCW_PRECC_MASK;
898 fpcw |= X86_FPCW_PREC_DOUBLE;
899 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
900 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
902 /* TODO: This is crashing on Win64 right now.
903 * _control87 (_PC_53, MCW_PC);
909 * Initialize architecture specific code.
912 mono_arch_init (void)
916 InitializeCriticalSection (&mini_arch_mutex);
918 #ifdef MONO_ARCH_NOMAP32BIT
919 flags = MONO_MMAP_READ;
920 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
921 breakpoint_size = 13;
922 breakpoint_fault_size = 3;
923 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
924 single_step_fault_size = 5;
926 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
927 /* amd64_mov_reg_mem () */
929 breakpoint_fault_size = 8;
930 single_step_fault_size = 8;
933 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
934 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
935 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
939 * Cleanup architecture specific code.
942 mono_arch_cleanup (void)
944 DeleteCriticalSection (&mini_arch_mutex);
948 * This function returns the optimizations supported on this cpu.
951 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
953 int eax, ebx, ecx, edx;
959 /* Feature Flags function, flags returned in EDX. */
960 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
961 if (edx & (1 << 15)) {
962 opts |= MONO_OPT_CMOV;
964 opts |= MONO_OPT_FCMOV;
966 *exclude_mask |= MONO_OPT_FCMOV;
968 *exclude_mask |= MONO_OPT_CMOV;
975 * This function test for all SSE functions supported.
977 * Returns a bitmask corresponding to all supported versions.
981 mono_arch_cpu_enumerate_simd_versions (void)
983 int eax, ebx, ecx, edx;
984 guint32 sse_opts = 0;
986 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
988 sse_opts |= SIMD_VERSION_SSE1;
990 sse_opts |= SIMD_VERSION_SSE2;
992 sse_opts |= SIMD_VERSION_SSE3;
994 sse_opts |= SIMD_VERSION_SSSE3;
996 sse_opts |= SIMD_VERSION_SSE41;
998 sse_opts |= SIMD_VERSION_SSE42;
1001 /* Yes, all this needs to be done to check for sse4a.
1002 See: "Amd: CPUID Specification"
1004 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1005 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1006 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1007 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1009 sse_opts |= SIMD_VERSION_SSE4a;
1019 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1024 for (i = 0; i < cfg->num_varinfo; i++) {
1025 MonoInst *ins = cfg->varinfo [i];
1026 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1029 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1032 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1033 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1036 if (mono_is_regsize_var (ins->inst_vtype)) {
1037 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1038 g_assert (i == vmv->idx);
1039 vars = g_list_prepend (vars, vmv);
1043 vars = mono_varlist_sort (cfg, vars, 0);
1049 * mono_arch_compute_omit_fp:
1051 * Determine whenever the frame pointer can be eliminated.
1054 mono_arch_compute_omit_fp (MonoCompile *cfg)
1056 MonoMethodSignature *sig;
1057 MonoMethodHeader *header;
1061 if (cfg->arch.omit_fp_computed)
1064 header = cfg->header;
1066 sig = mono_method_signature (cfg->method);
1068 if (!cfg->arch.cinfo)
1069 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1070 cinfo = cfg->arch.cinfo;
1073 * FIXME: Remove some of the restrictions.
1075 cfg->arch.omit_fp = TRUE;
1076 cfg->arch.omit_fp_computed = TRUE;
1078 if (cfg->disable_omit_fp)
1079 cfg->arch.omit_fp = FALSE;
1081 if (!debug_omit_fp ())
1082 cfg->arch.omit_fp = FALSE;
1084 if (cfg->method->save_lmf)
1085 cfg->arch.omit_fp = FALSE;
1087 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1088 cfg->arch.omit_fp = FALSE;
1089 if (header->num_clauses)
1090 cfg->arch.omit_fp = FALSE;
1091 if (cfg->param_area)
1092 cfg->arch.omit_fp = FALSE;
1093 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1094 cfg->arch.omit_fp = FALSE;
1095 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1096 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1097 cfg->arch.omit_fp = FALSE;
1098 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1099 ArgInfo *ainfo = &cinfo->args [i];
1101 if (ainfo->storage == ArgOnStack) {
1103 * The stack offset can only be determined when the frame
1106 cfg->arch.omit_fp = FALSE;
1111 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1112 MonoInst *ins = cfg->varinfo [i];
1115 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1120 mono_arch_get_global_int_regs (MonoCompile *cfg)
1124 mono_arch_compute_omit_fp (cfg);
1126 if (cfg->globalra) {
1127 if (cfg->arch.omit_fp)
1128 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1130 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1131 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1132 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1133 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1134 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1136 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1137 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1138 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1139 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1140 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1141 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1142 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1143 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1145 if (cfg->arch.omit_fp)
1146 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1148 /* We use the callee saved registers for global allocation */
1149 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1150 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1151 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1152 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1153 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1155 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1156 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1164 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1169 /* All XMM registers */
1170 for (i = 0; i < 16; ++i)
1171 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1177 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1179 static GList *r = NULL;
1184 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1185 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1186 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1187 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1188 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1189 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1191 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1192 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1193 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1194 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1195 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1196 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1197 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1198 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1200 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1207 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1210 static GList *r = NULL;
1215 for (i = 0; i < AMD64_XMM_NREG; ++i)
1216 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1218 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1225 * mono_arch_regalloc_cost:
1227 * Return the cost, in number of memory references, of the action of
1228 * allocating the variable VMV into a register during global register
1232 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1234 MonoInst *ins = cfg->varinfo [vmv->idx];
1236 if (cfg->method->save_lmf)
1237 /* The register is already saved */
1238 /* substract 1 for the invisible store in the prolog */
1239 return (ins->opcode == OP_ARG) ? 0 : 1;
1242 return (ins->opcode == OP_ARG) ? 1 : 2;
1246 * mono_arch_fill_argument_info:
1248 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1252 mono_arch_fill_argument_info (MonoCompile *cfg)
1254 MonoMethodSignature *sig;
1255 MonoMethodHeader *header;
1260 header = cfg->header;
1262 sig = mono_method_signature (cfg->method);
1264 cinfo = cfg->arch.cinfo;
1267 * Contrary to mono_arch_allocate_vars (), the information should describe
1268 * where the arguments are at the beginning of the method, not where they can be
1269 * accessed during the execution of the method. The later makes no sense for the
1270 * global register allocator, since a variable can be in more than one location.
1272 if (sig->ret->type != MONO_TYPE_VOID) {
1273 switch (cinfo->ret.storage) {
1275 case ArgInFloatSSEReg:
1276 case ArgInDoubleSSEReg:
1277 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1278 cfg->vret_addr->opcode = OP_REGVAR;
1279 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1282 cfg->ret->opcode = OP_REGVAR;
1283 cfg->ret->inst_c0 = cinfo->ret.reg;
1286 case ArgValuetypeInReg:
1287 cfg->ret->opcode = OP_REGOFFSET;
1288 cfg->ret->inst_basereg = -1;
1289 cfg->ret->inst_offset = -1;
1292 g_assert_not_reached ();
1296 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1297 ArgInfo *ainfo = &cinfo->args [i];
1300 ins = cfg->args [i];
1302 if (sig->hasthis && (i == 0))
1303 arg_type = &mono_defaults.object_class->byval_arg;
1305 arg_type = sig->params [i - sig->hasthis];
1307 switch (ainfo->storage) {
1309 case ArgInFloatSSEReg:
1310 case ArgInDoubleSSEReg:
1311 ins->opcode = OP_REGVAR;
1312 ins->inst_c0 = ainfo->reg;
1315 ins->opcode = OP_REGOFFSET;
1316 ins->inst_basereg = -1;
1317 ins->inst_offset = -1;
1319 case ArgValuetypeInReg:
1321 ins->opcode = OP_NOP;
1324 g_assert_not_reached ();
1330 mono_arch_allocate_vars (MonoCompile *cfg)
1332 MonoMethodSignature *sig;
1333 MonoMethodHeader *header;
1336 guint32 locals_stack_size, locals_stack_align;
1340 header = cfg->header;
1342 sig = mono_method_signature (cfg->method);
1344 cinfo = cfg->arch.cinfo;
1346 mono_arch_compute_omit_fp (cfg);
1349 * We use the ABI calling conventions for managed code as well.
1350 * Exception: valuetypes are only sometimes passed or returned in registers.
1354 * The stack looks like this:
1355 * <incoming arguments passed on the stack>
1357 * <lmf/caller saved registers>
1360 * <localloc area> -> grows dynamically
1364 if (cfg->arch.omit_fp) {
1365 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1366 cfg->frame_reg = AMD64_RSP;
1369 /* Locals are allocated backwards from %fp */
1370 cfg->frame_reg = AMD64_RBP;
1374 if (cfg->method->save_lmf) {
1375 /* Reserve stack space for saving LMF */
1376 if (cfg->arch.omit_fp) {
1377 cfg->arch.lmf_offset = offset;
1378 offset += sizeof (MonoLMF);
1381 offset += sizeof (MonoLMF);
1382 cfg->arch.lmf_offset = -offset;
1385 if (cfg->arch.omit_fp)
1386 cfg->arch.reg_save_area_offset = offset;
1387 /* Reserve space for caller saved registers */
1388 for (i = 0; i < AMD64_NREG; ++i)
1389 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1390 offset += sizeof (gpointer);
1394 if (sig->ret->type != MONO_TYPE_VOID) {
1395 switch (cinfo->ret.storage) {
1397 case ArgInFloatSSEReg:
1398 case ArgInDoubleSSEReg:
1399 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1400 if (cfg->globalra) {
1401 cfg->vret_addr->opcode = OP_REGVAR;
1402 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1404 /* The register is volatile */
1405 cfg->vret_addr->opcode = OP_REGOFFSET;
1406 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1407 if (cfg->arch.omit_fp) {
1408 cfg->vret_addr->inst_offset = offset;
1412 cfg->vret_addr->inst_offset = -offset;
1414 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1415 printf ("vret_addr =");
1416 mono_print_ins (cfg->vret_addr);
1421 cfg->ret->opcode = OP_REGVAR;
1422 cfg->ret->inst_c0 = cinfo->ret.reg;
1425 case ArgValuetypeInReg:
1426 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1427 cfg->ret->opcode = OP_REGOFFSET;
1428 cfg->ret->inst_basereg = cfg->frame_reg;
1429 if (cfg->arch.omit_fp) {
1430 cfg->ret->inst_offset = offset;
1434 cfg->ret->inst_offset = - offset;
1438 g_assert_not_reached ();
1441 cfg->ret->dreg = cfg->ret->inst_c0;
1444 /* Allocate locals */
1445 if (!cfg->globalra) {
1446 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1447 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1448 char *mname = mono_method_full_name (cfg->method, TRUE);
1449 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1450 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1455 if (locals_stack_align) {
1456 offset += (locals_stack_align - 1);
1457 offset &= ~(locals_stack_align - 1);
1459 if (cfg->arch.omit_fp) {
1460 cfg->locals_min_stack_offset = offset;
1461 cfg->locals_max_stack_offset = offset + locals_stack_size;
1463 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1464 cfg->locals_max_stack_offset = - offset;
1467 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1468 if (offsets [i] != -1) {
1469 MonoInst *ins = cfg->varinfo [i];
1470 ins->opcode = OP_REGOFFSET;
1471 ins->inst_basereg = cfg->frame_reg;
1472 if (cfg->arch.omit_fp)
1473 ins->inst_offset = (offset + offsets [i]);
1475 ins->inst_offset = - (offset + offsets [i]);
1476 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1479 offset += locals_stack_size;
1482 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1483 g_assert (!cfg->arch.omit_fp);
1484 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1485 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1488 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489 ins = cfg->args [i];
1490 if (ins->opcode != OP_REGVAR) {
1491 ArgInfo *ainfo = &cinfo->args [i];
1492 gboolean inreg = TRUE;
1495 if (sig->hasthis && (i == 0))
1496 arg_type = &mono_defaults.object_class->byval_arg;
1498 arg_type = sig->params [i - sig->hasthis];
1500 if (cfg->globalra) {
1501 /* The new allocator needs info about the original locations of the arguments */
1502 switch (ainfo->storage) {
1504 case ArgInFloatSSEReg:
1505 case ArgInDoubleSSEReg:
1506 ins->opcode = OP_REGVAR;
1507 ins->inst_c0 = ainfo->reg;
1510 g_assert (!cfg->arch.omit_fp);
1511 ins->opcode = OP_REGOFFSET;
1512 ins->inst_basereg = cfg->frame_reg;
1513 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1515 case ArgValuetypeInReg:
1516 ins->opcode = OP_REGOFFSET;
1517 ins->inst_basereg = cfg->frame_reg;
1518 /* These arguments are saved to the stack in the prolog */
1519 offset = ALIGN_TO (offset, sizeof (gpointer));
1520 if (cfg->arch.omit_fp) {
1521 ins->inst_offset = offset;
1522 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1524 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1525 ins->inst_offset = - offset;
1529 g_assert_not_reached ();
1535 /* FIXME: Allocate volatile arguments to registers */
1536 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1540 * Under AMD64, all registers used to pass arguments to functions
1541 * are volatile across calls.
1542 * FIXME: Optimize this.
1544 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1547 ins->opcode = OP_REGOFFSET;
1549 switch (ainfo->storage) {
1551 case ArgInFloatSSEReg:
1552 case ArgInDoubleSSEReg:
1554 ins->opcode = OP_REGVAR;
1555 ins->dreg = ainfo->reg;
1559 g_assert (!cfg->arch.omit_fp);
1560 ins->opcode = OP_REGOFFSET;
1561 ins->inst_basereg = cfg->frame_reg;
1562 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1564 case ArgValuetypeInReg:
1566 case ArgValuetypeAddrInIReg: {
1568 g_assert (!cfg->arch.omit_fp);
1570 MONO_INST_NEW (cfg, indir, 0);
1571 indir->opcode = OP_REGOFFSET;
1572 if (ainfo->pair_storage [0] == ArgInIReg) {
1573 indir->inst_basereg = cfg->frame_reg;
1574 offset = ALIGN_TO (offset, sizeof (gpointer));
1575 offset += (sizeof (gpointer));
1576 indir->inst_offset = - offset;
1579 indir->inst_basereg = cfg->frame_reg;
1580 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1583 ins->opcode = OP_VTARG_ADDR;
1584 ins->inst_left = indir;
1592 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1593 ins->opcode = OP_REGOFFSET;
1594 ins->inst_basereg = cfg->frame_reg;
1595 /* These arguments are saved to the stack in the prolog */
1596 offset = ALIGN_TO (offset, sizeof (gpointer));
1597 if (cfg->arch.omit_fp) {
1598 ins->inst_offset = offset;
1599 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1600 // Arguments are yet supported by the stack map creation code
1601 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1603 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1604 ins->inst_offset = - offset;
1605 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1611 cfg->stack_offset = offset;
1615 mono_arch_create_vars (MonoCompile *cfg)
1617 MonoMethodSignature *sig;
1620 sig = mono_method_signature (cfg->method);
1622 if (!cfg->arch.cinfo)
1623 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1624 cinfo = cfg->arch.cinfo;
1626 if (cinfo->ret.storage == ArgValuetypeInReg)
1627 cfg->ret_var_is_local = TRUE;
1629 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1630 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1631 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1632 printf ("vret_addr = ");
1633 mono_print_ins (cfg->vret_addr);
1637 if (cfg->gen_seq_points) {
1640 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1641 ins->flags |= MONO_INST_VOLATILE;
1642 cfg->arch.ss_trigger_page_var = ins;
1645 #ifdef MONO_AMD64_NO_PUSHES
1647 * When this is set, we pass arguments on the stack by moves, and by allocating
1648 * a bigger stack frame, instead of pushes.
1649 * Pushes complicate exception handling because the arguments on the stack have
1650 * to be popped each time a frame is unwound. They also make fp elimination
1652 * FIXME: This doesn't work inside filter/finally clauses, since those execute
1653 * on a new frame which doesn't include a param area.
1655 cfg->arch.no_pushes = TRUE;
1660 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1666 MONO_INST_NEW (cfg, ins, OP_MOVE);
1667 ins->dreg = mono_alloc_ireg (cfg);
1668 ins->sreg1 = tree->dreg;
1669 MONO_ADD_INS (cfg->cbb, ins);
1670 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1672 case ArgInFloatSSEReg:
1673 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1674 ins->dreg = mono_alloc_freg (cfg);
1675 ins->sreg1 = tree->dreg;
1676 MONO_ADD_INS (cfg->cbb, ins);
1678 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1680 case ArgInDoubleSSEReg:
1681 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1682 ins->dreg = mono_alloc_freg (cfg);
1683 ins->sreg1 = tree->dreg;
1684 MONO_ADD_INS (cfg->cbb, ins);
1686 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1690 g_assert_not_reached ();
1695 arg_storage_to_load_membase (ArgStorage storage)
1699 return OP_LOAD_MEMBASE;
1700 case ArgInDoubleSSEReg:
1701 return OP_LOADR8_MEMBASE;
1702 case ArgInFloatSSEReg:
1703 return OP_LOADR4_MEMBASE;
1705 g_assert_not_reached ();
1712 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1715 MonoMethodSignature *tmp_sig;
1718 if (call->tail_call)
1721 /* FIXME: Add support for signature tokens to AOT */
1722 cfg->disable_aot = TRUE;
1724 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1727 * mono_ArgIterator_Setup assumes the signature cookie is
1728 * passed first and all the arguments which were before it are
1729 * passed on the stack after the signature. So compensate by
1730 * passing a different signature.
1732 tmp_sig = mono_metadata_signature_dup (call->signature);
1733 tmp_sig->param_count -= call->signature->sentinelpos;
1734 tmp_sig->sentinelpos = 0;
1735 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1737 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1738 sig_arg->dreg = mono_alloc_ireg (cfg);
1739 sig_arg->inst_p0 = tmp_sig;
1740 MONO_ADD_INS (cfg->cbb, sig_arg);
1742 if (cfg->arch.no_pushes) {
1743 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1745 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1746 arg->sreg1 = sig_arg->dreg;
1747 MONO_ADD_INS (cfg->cbb, arg);
1751 static inline LLVMArgStorage
1752 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1756 return LLVMArgInIReg;
1760 g_assert_not_reached ();
1767 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1773 LLVMCallInfo *linfo;
1776 n = sig->param_count + sig->hasthis;
1778 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1780 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1783 * LLVM always uses the native ABI while we use our own ABI, the
1784 * only difference is the handling of vtypes:
1785 * - we only pass/receive them in registers in some cases, and only
1786 * in 1 or 2 integer registers.
1788 if (cinfo->ret.storage == ArgValuetypeInReg) {
1790 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1791 cfg->disable_llvm = TRUE;
1795 linfo->ret.storage = LLVMArgVtypeInReg;
1796 for (j = 0; j < 2; ++j)
1797 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1800 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1801 /* Vtype returned using a hidden argument */
1802 linfo->ret.storage = LLVMArgVtypeRetAddr;
1805 for (i = 0; i < n; ++i) {
1806 ainfo = cinfo->args + i;
1808 if (i >= sig->hasthis)
1809 t = sig->params [i - sig->hasthis];
1811 t = &mono_defaults.int_class->byval_arg;
1813 linfo->args [i].storage = LLVMArgNone;
1815 switch (ainfo->storage) {
1817 linfo->args [i].storage = LLVMArgInIReg;
1819 case ArgInDoubleSSEReg:
1820 case ArgInFloatSSEReg:
1821 linfo->args [i].storage = LLVMArgInFPReg;
1824 if (MONO_TYPE_ISSTRUCT (t)) {
1825 linfo->args [i].storage = LLVMArgVtypeByVal;
1827 linfo->args [i].storage = LLVMArgInIReg;
1829 if (t->type == MONO_TYPE_R4)
1830 linfo->args [i].storage = LLVMArgInFPReg;
1831 else if (t->type == MONO_TYPE_R8)
1832 linfo->args [i].storage = LLVMArgInFPReg;
1836 case ArgValuetypeInReg:
1838 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1839 cfg->disable_llvm = TRUE;
1843 linfo->args [i].storage = LLVMArgVtypeInReg;
1844 for (j = 0; j < 2; ++j)
1845 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1848 cfg->exception_message = g_strdup ("ainfo->storage");
1849 cfg->disable_llvm = TRUE;
1859 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1862 MonoMethodSignature *sig;
1863 int i, n, stack_size;
1869 sig = call->signature;
1870 n = sig->param_count + sig->hasthis;
1872 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1874 if (COMPILE_LLVM (cfg)) {
1875 /* We shouldn't be called in the llvm case */
1876 cfg->disable_llvm = TRUE;
1880 if (cinfo->need_stack_align) {
1881 if (!cfg->arch.no_pushes)
1882 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1886 * Emit all arguments which are passed on the stack to prevent register
1887 * allocation problems.
1889 if (cfg->arch.no_pushes) {
1890 for (i = 0; i < n; ++i) {
1892 ainfo = cinfo->args + i;
1894 in = call->args [i];
1896 if (sig->hasthis && i == 0)
1897 t = &mono_defaults.object_class->byval_arg;
1899 t = sig->params [i - sig->hasthis];
1901 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1903 if (t->type == MONO_TYPE_R4)
1904 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1905 else if (t->type == MONO_TYPE_R8)
1906 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1908 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1910 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1917 * Emit all parameters passed in registers in non-reverse order for better readability
1918 * and to help the optimization in emit_prolog ().
1920 for (i = 0; i < n; ++i) {
1921 ainfo = cinfo->args + i;
1923 in = call->args [i];
1925 if (ainfo->storage == ArgInIReg)
1926 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1929 for (i = n - 1; i >= 0; --i) {
1930 ainfo = cinfo->args + i;
1932 in = call->args [i];
1934 switch (ainfo->storage) {
1938 case ArgInFloatSSEReg:
1939 case ArgInDoubleSSEReg:
1940 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1943 case ArgValuetypeInReg:
1944 case ArgValuetypeAddrInIReg:
1945 if (ainfo->storage == ArgOnStack && call->tail_call) {
1946 MonoInst *call_inst = (MonoInst*)call;
1947 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1948 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1949 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1953 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1954 size = sizeof (MonoTypedRef);
1955 align = sizeof (gpointer);
1959 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1962 * Other backends use mono_type_stack_size (), but that
1963 * aligns the size to 8, which is larger than the size of
1964 * the source, leading to reads of invalid memory if the
1965 * source is at the end of address space.
1967 size = mono_class_value_size (in->klass, &align);
1970 g_assert (in->klass);
1972 if (ainfo->storage == ArgOnStack && size >= 10000) {
1973 /* Avoid asserts in emit_memcpy () */
1974 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1975 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
1976 /* Continue normally */
1980 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1981 arg->sreg1 = in->dreg;
1982 arg->klass = in->klass;
1983 arg->backend.size = size;
1984 arg->inst_p0 = call;
1985 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1986 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1988 MONO_ADD_INS (cfg->cbb, arg);
1991 if (cfg->arch.no_pushes) {
1994 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1995 arg->sreg1 = in->dreg;
1996 if (!sig->params [i - sig->hasthis]->byref) {
1997 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1998 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1999 arg->opcode = OP_STORER4_MEMBASE_REG;
2000 arg->inst_destbasereg = X86_ESP;
2001 arg->inst_offset = 0;
2002 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2003 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2004 arg->opcode = OP_STORER8_MEMBASE_REG;
2005 arg->inst_destbasereg = X86_ESP;
2006 arg->inst_offset = 0;
2009 MONO_ADD_INS (cfg->cbb, arg);
2014 g_assert_not_reached ();
2017 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2018 /* Emit the signature cookie just before the implicit arguments */
2019 emit_sig_cookie (cfg, call, cinfo);
2022 /* Handle the case where there are no implicit arguments */
2023 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2024 emit_sig_cookie (cfg, call, cinfo);
2026 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2029 if (cinfo->ret.storage == ArgValuetypeInReg) {
2030 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2032 * Tell the JIT to use a more efficient calling convention: call using
2033 * OP_CALL, compute the result location after the call, and save the
2036 call->vret_in_reg = TRUE;
2038 * Nullify the instruction computing the vret addr to enable
2039 * future optimizations.
2042 NULLIFY_INS (call->vret_var);
2044 if (call->tail_call)
2047 * The valuetype is in RAX:RDX after the call, need to be copied to
2048 * the stack. Push the address here, so the call instruction can
2051 if (!cfg->arch.vret_addr_loc) {
2052 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2053 /* Prevent it from being register allocated or optimized away */
2054 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2057 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2061 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2062 vtarg->sreg1 = call->vret_var->dreg;
2063 vtarg->dreg = mono_alloc_preg (cfg);
2064 MONO_ADD_INS (cfg->cbb, vtarg);
2066 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2071 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2072 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2076 if (cfg->method->save_lmf) {
2077 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2078 MONO_ADD_INS (cfg->cbb, arg);
2081 call->stack_usage = cinfo->stack_usage;
2085 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2088 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2089 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2090 int size = ins->backend.size;
2092 if (ainfo->storage == ArgValuetypeInReg) {
2096 for (part = 0; part < 2; ++part) {
2097 if (ainfo->pair_storage [part] == ArgNone)
2100 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2101 load->inst_basereg = src->dreg;
2102 load->inst_offset = part * sizeof (gpointer);
2104 switch (ainfo->pair_storage [part]) {
2106 load->dreg = mono_alloc_ireg (cfg);
2108 case ArgInDoubleSSEReg:
2109 case ArgInFloatSSEReg:
2110 load->dreg = mono_alloc_freg (cfg);
2113 g_assert_not_reached ();
2115 MONO_ADD_INS (cfg->cbb, load);
2117 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2119 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2120 MonoInst *vtaddr, *load;
2121 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2123 g_assert (!cfg->arch.no_pushes);
2125 MONO_INST_NEW (cfg, load, OP_LDADDR);
2126 load->inst_p0 = vtaddr;
2127 vtaddr->flags |= MONO_INST_INDIRECT;
2128 load->type = STACK_MP;
2129 load->klass = vtaddr->klass;
2130 load->dreg = mono_alloc_ireg (cfg);
2131 MONO_ADD_INS (cfg->cbb, load);
2132 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2134 if (ainfo->pair_storage [0] == ArgInIReg) {
2135 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2136 arg->dreg = mono_alloc_ireg (cfg);
2137 arg->sreg1 = load->dreg;
2139 MONO_ADD_INS (cfg->cbb, arg);
2140 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2142 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2143 arg->sreg1 = load->dreg;
2144 MONO_ADD_INS (cfg->cbb, arg);
2148 if (cfg->arch.no_pushes) {
2149 int dreg = mono_alloc_ireg (cfg);
2151 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2152 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2154 /* Can't use this for < 8 since it does an 8 byte memory load */
2155 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2156 arg->inst_basereg = src->dreg;
2157 arg->inst_offset = 0;
2158 MONO_ADD_INS (cfg->cbb, arg);
2160 } else if (size <= 40) {
2161 if (cfg->arch.no_pushes) {
2162 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2164 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2165 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2168 if (cfg->arch.no_pushes) {
2169 // FIXME: Code growth
2170 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2172 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2173 arg->inst_basereg = src->dreg;
2174 arg->inst_offset = 0;
2175 arg->inst_imm = size;
2176 MONO_ADD_INS (cfg->cbb, arg);
2183 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2185 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2187 if (ret->type == MONO_TYPE_R4) {
2188 if (COMPILE_LLVM (cfg))
2189 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2191 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2193 } else if (ret->type == MONO_TYPE_R8) {
2194 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2198 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2201 #endif /* DISABLE_JIT */
2203 #define EMIT_COND_BRANCH(ins,cond,sign) \
2204 if (ins->inst_true_bb->native_offset) { \
2205 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2207 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2208 if ((cfg->opt & MONO_OPT_BRANCH) && \
2209 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2210 x86_branch8 (code, cond, 0, sign); \
2212 x86_branch32 (code, cond, 0, sign); \
2216 MonoMethodSignature *sig;
2221 mgreg_t regs [PARAM_REGS];
2227 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2235 switch (cinfo->ret.storage) {
2239 case ArgValuetypeInReg: {
2240 ArgInfo *ainfo = &cinfo->ret;
2242 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2244 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2252 for (i = 0; i < cinfo->nargs; ++i) {
2253 ArgInfo *ainfo = &cinfo->args [i];
2254 switch (ainfo->storage) {
2257 case ArgValuetypeInReg:
2258 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2260 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2272 * mono_arch_dyn_call_prepare:
2274 * Return a pointer to an arch-specific structure which contains information
2275 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2276 * supported for SIG.
2277 * This function is equivalent to ffi_prep_cif in libffi.
2280 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2282 ArchDynCallInfo *info;
2285 cinfo = get_call_info (NULL, NULL, sig, FALSE);
2287 if (!dyn_call_supported (sig, cinfo)) {
2292 info = g_new0 (ArchDynCallInfo, 1);
2293 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2295 info->cinfo = cinfo;
2297 return (MonoDynCallInfo*)info;
2301 * mono_arch_dyn_call_free:
2303 * Free a MonoDynCallInfo structure.
2306 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2308 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2310 g_free (ainfo->cinfo);
2315 * mono_arch_get_start_dyn_call:
2317 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2318 * store the result into BUF.
2319 * ARGS should be an array of pointers pointing to the arguments.
2320 * RET should point to a memory buffer large enought to hold the result of the
2322 * This function should be as fast as possible, any work which does not depend
2323 * on the actual values of the arguments should be done in
2324 * mono_arch_dyn_call_prepare ().
2325 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2329 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2331 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2332 DynCallArgs *p = (DynCallArgs*)buf;
2333 int arg_index, greg, i;
2334 MonoMethodSignature *sig = dinfo->sig;
2336 g_assert (buf_len >= sizeof (DynCallArgs));
2344 if (dinfo->cinfo->vtype_retaddr)
2345 p->regs [greg ++] = (mgreg_t)ret;
2348 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2351 for (i = 0; i < sig->param_count; i++) {
2352 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2353 gpointer *arg = args [arg_index ++];
2356 p->regs [greg ++] = (mgreg_t)*(arg);
2361 case MONO_TYPE_STRING:
2362 case MONO_TYPE_CLASS:
2363 case MONO_TYPE_ARRAY:
2364 case MONO_TYPE_SZARRAY:
2365 case MONO_TYPE_OBJECT:
2371 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2372 p->regs [greg ++] = (mgreg_t)*(arg);
2374 case MONO_TYPE_BOOLEAN:
2376 p->regs [greg ++] = *(guint8*)(arg);
2379 p->regs [greg ++] = *(gint8*)(arg);
2382 p->regs [greg ++] = *(gint16*)(arg);
2385 case MONO_TYPE_CHAR:
2386 p->regs [greg ++] = *(guint16*)(arg);
2389 p->regs [greg ++] = *(gint32*)(arg);
2392 p->regs [greg ++] = *(guint32*)(arg);
2394 case MONO_TYPE_GENERICINST:
2395 if (MONO_TYPE_IS_REFERENCE (t)) {
2396 p->regs [greg ++] = (mgreg_t)*(arg);
2401 case MONO_TYPE_VALUETYPE: {
2402 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2404 g_assert (ainfo->storage == ArgValuetypeInReg);
2405 if (ainfo->pair_storage [0] != ArgNone) {
2406 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2407 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2409 if (ainfo->pair_storage [1] != ArgNone) {
2410 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2411 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2416 g_assert_not_reached ();
2420 g_assert (greg <= PARAM_REGS);
2424 * mono_arch_finish_dyn_call:
2426 * Store the result of a dyn call into the return value buffer passed to
2427 * start_dyn_call ().
2428 * This function should be as fast as possible, any work which does not depend
2429 * on the actual values of the arguments should be done in
2430 * mono_arch_dyn_call_prepare ().
2433 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2435 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2436 MonoMethodSignature *sig = dinfo->sig;
2437 guint8 *ret = ((DynCallArgs*)buf)->ret;
2438 mgreg_t res = ((DynCallArgs*)buf)->res;
2440 switch (mono_type_get_underlying_type (sig->ret)->type) {
2441 case MONO_TYPE_VOID:
2442 *(gpointer*)ret = NULL;
2444 case MONO_TYPE_STRING:
2445 case MONO_TYPE_CLASS:
2446 case MONO_TYPE_ARRAY:
2447 case MONO_TYPE_SZARRAY:
2448 case MONO_TYPE_OBJECT:
2452 *(gpointer*)ret = (gpointer)res;
2458 case MONO_TYPE_BOOLEAN:
2459 *(guint8*)ret = res;
2462 *(gint16*)ret = res;
2465 case MONO_TYPE_CHAR:
2466 *(guint16*)ret = res;
2469 *(gint32*)ret = res;
2472 *(guint32*)ret = res;
2475 *(gint64*)ret = res;
2478 *(guint64*)ret = res;
2480 case MONO_TYPE_GENERICINST:
2481 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2482 *(gpointer*)ret = (gpointer)res;
2487 case MONO_TYPE_VALUETYPE:
2488 if (dinfo->cinfo->vtype_retaddr) {
2491 ArgInfo *ainfo = &dinfo->cinfo->ret;
2493 g_assert (ainfo->storage == ArgValuetypeInReg);
2495 if (ainfo->pair_storage [0] != ArgNone) {
2496 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2497 ((mgreg_t*)ret)[0] = res;
2500 g_assert (ainfo->pair_storage [1] == ArgNone);
2504 g_assert_not_reached ();
2508 /* emit an exception if condition is fail */
2509 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2511 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2512 if (tins == NULL) { \
2513 mono_add_patch_info (cfg, code - cfg->native_code, \
2514 MONO_PATCH_INFO_EXC, exc_name); \
2515 x86_branch32 (code, cond, 0, signed); \
2517 EMIT_COND_BRANCH (tins, cond, signed); \
2521 #define EMIT_FPCOMPARE(code) do { \
2522 amd64_fcompp (code); \
2523 amd64_fnstsw (code); \
2526 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2527 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2528 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2529 amd64_ ##op (code); \
2530 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2531 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2535 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2537 gboolean no_patch = FALSE;
2540 * FIXME: Add support for thunks
2543 gboolean near_call = FALSE;
2546 * Indirect calls are expensive so try to make a near call if possible.
2547 * The caller memory is allocated by the code manager so it is
2548 * guaranteed to be at a 32 bit offset.
2551 if (patch_type != MONO_PATCH_INFO_ABS) {
2552 /* The target is in memory allocated using the code manager */
2555 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2556 if (((MonoMethod*)data)->klass->image->aot_module)
2557 /* The callee might be an AOT method */
2559 if (((MonoMethod*)data)->dynamic)
2560 /* The target is in malloc-ed memory */
2564 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2566 * The call might go directly to a native function without
2569 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2571 gconstpointer target = mono_icall_get_wrapper (mi);
2572 if ((((guint64)target) >> 32) != 0)
2578 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2580 * This is not really an optimization, but required because the
2581 * generic class init trampolines use R11 to pass the vtable.
2585 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2587 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2588 strstr (cfg->method->name, info->name)) {
2589 /* A call to the wrapped function */
2590 if ((((guint64)data) >> 32) == 0)
2594 else if (info->func == info->wrapper) {
2596 if ((((guint64)info->func) >> 32) == 0)
2600 /* See the comment in mono_codegen () */
2601 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2605 else if ((((guint64)data) >> 32) == 0) {
2612 if (cfg->method->dynamic)
2613 /* These methods are allocated using malloc */
2616 #ifdef MONO_ARCH_NOMAP32BIT
2620 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2621 if (optimize_for_xen)
2624 if (cfg->compile_aot) {
2631 * Align the call displacement to an address divisible by 4 so it does
2632 * not span cache lines. This is required for code patching to work on SMP
2635 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2636 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2637 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2638 amd64_call_code (code, 0);
2641 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2642 amd64_set_reg_template (code, GP_SCRATCH_REG);
2643 amd64_call_reg (code, GP_SCRATCH_REG);
2650 static inline guint8*
2651 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2654 if (win64_adjust_stack)
2655 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2657 code = emit_call_body (cfg, code, patch_type, data);
2659 if (win64_adjust_stack)
2660 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2667 store_membase_imm_to_store_membase_reg (int opcode)
2670 case OP_STORE_MEMBASE_IMM:
2671 return OP_STORE_MEMBASE_REG;
2672 case OP_STOREI4_MEMBASE_IMM:
2673 return OP_STOREI4_MEMBASE_REG;
2674 case OP_STOREI8_MEMBASE_IMM:
2675 return OP_STOREI8_MEMBASE_REG;
2683 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2686 * mono_arch_peephole_pass_1:
2688 * Perform peephole opts which should/can be performed before local regalloc
2691 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2695 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2696 MonoInst *last_ins = ins->prev;
2698 switch (ins->opcode) {
2702 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2704 * X86_LEA is like ADD, but doesn't have the
2705 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2706 * its operand to 64 bit.
2708 ins->opcode = OP_X86_LEA_MEMBASE;
2709 ins->inst_basereg = ins->sreg1;
2714 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2718 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2719 * the latter has length 2-3 instead of 6 (reverse constant
2720 * propagation). These instruction sequences are very common
2721 * in the initlocals bblock.
2723 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2724 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2725 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2726 ins2->sreg1 = ins->dreg;
2727 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2729 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2738 case OP_COMPARE_IMM:
2739 case OP_LCOMPARE_IMM:
2740 /* OP_COMPARE_IMM (reg, 0)
2742 * OP_AMD64_TEST_NULL (reg)
2745 ins->opcode = OP_AMD64_TEST_NULL;
2747 case OP_ICOMPARE_IMM:
2749 ins->opcode = OP_X86_TEST_NULL;
2751 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2753 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2754 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2756 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2757 * OP_COMPARE_IMM reg, imm
2759 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2761 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2762 ins->inst_basereg == last_ins->inst_destbasereg &&
2763 ins->inst_offset == last_ins->inst_offset) {
2764 ins->opcode = OP_ICOMPARE_IMM;
2765 ins->sreg1 = last_ins->sreg1;
2767 /* check if we can remove cmp reg,0 with test null */
2769 ins->opcode = OP_X86_TEST_NULL;
2775 mono_peephole_ins (bb, ins);
2780 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2784 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2785 switch (ins->opcode) {
2788 /* reg = 0 -> XOR (reg, reg) */
2789 /* XOR sets cflags on x86, so we cant do it always */
2790 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2791 ins->opcode = OP_LXOR;
2792 ins->sreg1 = ins->dreg;
2793 ins->sreg2 = ins->dreg;
2801 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2802 * 0 result into 64 bits.
2804 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2805 ins->opcode = OP_IXOR;
2809 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2813 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2814 * the latter has length 2-3 instead of 6 (reverse constant
2815 * propagation). These instruction sequences are very common
2816 * in the initlocals bblock.
2818 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2819 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2820 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2821 ins2->sreg1 = ins->dreg;
2822 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2824 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2834 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2835 ins->opcode = OP_X86_INC_REG;
2838 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2839 ins->opcode = OP_X86_DEC_REG;
2843 mono_peephole_ins (bb, ins);
2847 #define NEW_INS(cfg,ins,dest,op) do { \
2848 MONO_INST_NEW ((cfg), (dest), (op)); \
2849 (dest)->cil_code = (ins)->cil_code; \
2850 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2854 * mono_arch_lowering_pass:
2856 * Converts complex opcodes into simpler ones so that each IR instruction
2857 * corresponds to one machine instruction.
2860 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2862 MonoInst *ins, *n, *temp;
2865 * FIXME: Need to add more instructions, but the current machine
2866 * description can't model some parts of the composite instructions like
2869 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2870 switch (ins->opcode) {
2874 case OP_IDIV_UN_IMM:
2875 case OP_IREM_UN_IMM:
2876 mono_decompose_op_imm (cfg, bb, ins);
2879 /* Keep the opcode if we can implement it efficiently */
2880 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2881 mono_decompose_op_imm (cfg, bb, ins);
2883 case OP_COMPARE_IMM:
2884 case OP_LCOMPARE_IMM:
2885 if (!amd64_is_imm32 (ins->inst_imm)) {
2886 NEW_INS (cfg, ins, temp, OP_I8CONST);
2887 temp->inst_c0 = ins->inst_imm;
2888 temp->dreg = mono_alloc_ireg (cfg);
2889 ins->opcode = OP_COMPARE;
2890 ins->sreg2 = temp->dreg;
2893 case OP_LOAD_MEMBASE:
2894 case OP_LOADI8_MEMBASE:
2895 if (!amd64_is_imm32 (ins->inst_offset)) {
2896 NEW_INS (cfg, ins, temp, OP_I8CONST);
2897 temp->inst_c0 = ins->inst_offset;
2898 temp->dreg = mono_alloc_ireg (cfg);
2899 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2900 ins->inst_indexreg = temp->dreg;
2903 case OP_STORE_MEMBASE_IMM:
2904 case OP_STOREI8_MEMBASE_IMM:
2905 if (!amd64_is_imm32 (ins->inst_imm)) {
2906 NEW_INS (cfg, ins, temp, OP_I8CONST);
2907 temp->inst_c0 = ins->inst_imm;
2908 temp->dreg = mono_alloc_ireg (cfg);
2909 ins->opcode = OP_STOREI8_MEMBASE_REG;
2910 ins->sreg1 = temp->dreg;
2913 #ifdef MONO_ARCH_SIMD_INTRINSICS
2914 case OP_EXPAND_I1: {
2915 int temp_reg1 = mono_alloc_ireg (cfg);
2916 int temp_reg2 = mono_alloc_ireg (cfg);
2917 int original_reg = ins->sreg1;
2919 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2920 temp->sreg1 = original_reg;
2921 temp->dreg = temp_reg1;
2923 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2924 temp->sreg1 = temp_reg1;
2925 temp->dreg = temp_reg2;
2928 NEW_INS (cfg, ins, temp, OP_LOR);
2929 temp->sreg1 = temp->dreg = temp_reg2;
2930 temp->sreg2 = temp_reg1;
2932 ins->opcode = OP_EXPAND_I2;
2933 ins->sreg1 = temp_reg2;
2942 bb->max_vreg = cfg->next_vreg;
2946 branch_cc_table [] = {
2947 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2948 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2949 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2952 /* Maps CMP_... constants to X86_CC_... constants */
2955 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2956 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2960 cc_signed_table [] = {
2961 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2962 FALSE, FALSE, FALSE, FALSE
2965 /*#include "cprop.c"*/
2967 static unsigned char*
2968 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2970 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2973 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2975 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2979 static unsigned char*
2980 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2982 int sreg = tree->sreg1;
2983 int need_touch = FALSE;
2985 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2986 if (!tree->flags & MONO_INST_INIT)
2995 * If requested stack size is larger than one page,
2996 * perform stack-touch operation
2999 * Generate stack probe code.
3000 * Under Windows, it is necessary to allocate one page at a time,
3001 * "touching" stack after each successful sub-allocation. This is
3002 * because of the way stack growth is implemented - there is a
3003 * guard page before the lowest stack page that is currently commited.
3004 * Stack normally grows sequentially so OS traps access to the
3005 * guard page and commits more pages when needed.
3007 amd64_test_reg_imm (code, sreg, ~0xFFF);
3008 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3010 br[2] = code; /* loop */
3011 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3012 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3013 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3014 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3015 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3016 amd64_patch (br[3], br[2]);
3017 amd64_test_reg_reg (code, sreg, sreg);
3018 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3019 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3021 br[1] = code; x86_jump8 (code, 0);
3023 amd64_patch (br[0], code);
3024 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3025 amd64_patch (br[1], code);
3026 amd64_patch (br[4], code);
3029 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3031 if (tree->flags & MONO_INST_INIT) {
3033 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3034 amd64_push_reg (code, AMD64_RAX);
3037 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3038 amd64_push_reg (code, AMD64_RCX);
3041 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3042 amd64_push_reg (code, AMD64_RDI);
3046 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3047 if (sreg != AMD64_RCX)
3048 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3049 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3051 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3052 if (cfg->param_area && cfg->arch.no_pushes)
3053 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3055 amd64_prefix (code, X86_REP_PREFIX);
3058 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3059 amd64_pop_reg (code, AMD64_RDI);
3060 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3061 amd64_pop_reg (code, AMD64_RCX);
3062 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3063 amd64_pop_reg (code, AMD64_RAX);
3069 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3074 /* Move return value to the target register */
3075 /* FIXME: do this in the local reg allocator */
3076 switch (ins->opcode) {
3079 case OP_CALL_MEMBASE:
3082 case OP_LCALL_MEMBASE:
3083 g_assert (ins->dreg == AMD64_RAX);
3087 case OP_FCALL_MEMBASE:
3088 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3089 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3092 if (ins->dreg != AMD64_XMM0)
3093 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3098 case OP_VCALL_MEMBASE:
3101 case OP_VCALL2_MEMBASE:
3102 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3103 if (cinfo->ret.storage == ArgValuetypeInReg) {
3104 MonoInst *loc = cfg->arch.vret_addr_loc;
3106 /* Load the destination address */
3107 g_assert (loc->opcode == OP_REGOFFSET);
3108 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3110 for (quad = 0; quad < 2; quad ++) {
3111 switch (cinfo->ret.pair_storage [quad]) {
3113 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3115 case ArgInFloatSSEReg:
3116 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3118 case ArgInDoubleSSEReg:
3119 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3134 #endif /* DISABLE_JIT */
3137 * mono_amd64_emit_tls_get:
3138 * @code: buffer to store code to
3139 * @dreg: hard register where to place the result
3140 * @tls_offset: offset info
3142 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3143 * the dreg register the item in the thread local storage identified
3146 * Returns: a pointer to the end of the stored code
3149 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3152 g_assert (tls_offset < 64);
3153 x86_prefix (code, X86_GS_PREFIX);
3154 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3156 if (optimize_for_xen) {
3157 x86_prefix (code, X86_FS_PREFIX);
3158 amd64_mov_reg_mem (code, dreg, 0, 8);
3159 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3161 x86_prefix (code, X86_FS_PREFIX);
3162 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3168 #define REAL_PRINT_REG(text,reg) \
3169 mono_assert (reg >= 0); \
3170 amd64_push_reg (code, AMD64_RAX); \
3171 amd64_push_reg (code, AMD64_RDX); \
3172 amd64_push_reg (code, AMD64_RCX); \
3173 amd64_push_reg (code, reg); \
3174 amd64_push_imm (code, reg); \
3175 amd64_push_imm (code, text " %d %p\n"); \
3176 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3177 amd64_call_reg (code, AMD64_RAX); \
3178 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3179 amd64_pop_reg (code, AMD64_RCX); \
3180 amd64_pop_reg (code, AMD64_RDX); \
3181 amd64_pop_reg (code, AMD64_RAX);
3183 /* benchmark and set based on cpu */
3184 #define LOOP_ALIGNMENT 8
3185 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3190 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3195 guint8 *code = cfg->native_code + cfg->code_len;
3196 MonoInst *last_ins = NULL;
3197 guint last_offset = 0;
3200 /* Fix max_offset estimate for each successor bb */
3201 if (cfg->opt & MONO_OPT_BRANCH) {
3202 int current_offset = cfg->code_len;
3203 MonoBasicBlock *current_bb;
3204 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3205 current_bb->max_offset = current_offset;
3206 current_offset += current_bb->max_length;
3210 if (cfg->opt & MONO_OPT_LOOP) {
3211 int pad, align = LOOP_ALIGNMENT;
3212 /* set alignment depending on cpu */
3213 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3215 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3216 amd64_padding (code, pad);
3217 cfg->code_len += pad;
3218 bb->native_offset = cfg->code_len;
3222 if (cfg->verbose_level > 2)
3223 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3225 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3226 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3227 g_assert (!cfg->compile_aot);
3229 cov->data [bb->dfn].cil_code = bb->cil_code;
3230 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3231 /* this is not thread save, but good enough */
3232 amd64_inc_membase (code, AMD64_R11, 0);
3235 offset = code - cfg->native_code;
3237 mono_debug_open_block (cfg, bb, offset);
3239 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3240 x86_breakpoint (code);
3242 MONO_BB_FOR_EACH_INS (bb, ins) {
3243 offset = code - cfg->native_code;
3245 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3247 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3248 cfg->code_size *= 2;
3249 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3250 code = cfg->native_code + offset;
3251 mono_jit_stats.code_reallocs++;
3254 if (cfg->debug_info)
3255 mono_debug_record_line_number (cfg, ins, offset);
3257 switch (ins->opcode) {
3259 amd64_mul_reg (code, ins->sreg2, TRUE);
3262 amd64_mul_reg (code, ins->sreg2, FALSE);
3264 case OP_X86_SETEQ_MEMBASE:
3265 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3267 case OP_STOREI1_MEMBASE_IMM:
3268 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3270 case OP_STOREI2_MEMBASE_IMM:
3271 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3273 case OP_STOREI4_MEMBASE_IMM:
3274 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3276 case OP_STOREI1_MEMBASE_REG:
3277 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3279 case OP_STOREI2_MEMBASE_REG:
3280 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3282 case OP_STORE_MEMBASE_REG:
3283 case OP_STOREI8_MEMBASE_REG:
3284 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3286 case OP_STOREI4_MEMBASE_REG:
3287 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3289 case OP_STORE_MEMBASE_IMM:
3290 case OP_STOREI8_MEMBASE_IMM:
3291 g_assert (amd64_is_imm32 (ins->inst_imm));
3292 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3296 // FIXME: Decompose this earlier
3297 if (amd64_is_imm32 (ins->inst_imm))
3298 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3300 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3301 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3305 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3306 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3309 // FIXME: Decompose this earlier
3310 if (amd64_is_imm32 (ins->inst_imm))
3311 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3313 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3314 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3318 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3319 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3322 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3323 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3325 case OP_LOAD_MEMBASE:
3326 case OP_LOADI8_MEMBASE:
3327 g_assert (amd64_is_imm32 (ins->inst_offset));
3328 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3330 case OP_LOADI4_MEMBASE:
3331 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3333 case OP_LOADU4_MEMBASE:
3334 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3336 case OP_LOADU1_MEMBASE:
3337 /* The cpu zero extends the result into 64 bits */
3338 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3340 case OP_LOADI1_MEMBASE:
3341 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3343 case OP_LOADU2_MEMBASE:
3344 /* The cpu zero extends the result into 64 bits */
3345 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3347 case OP_LOADI2_MEMBASE:
3348 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3350 case OP_AMD64_LOADI8_MEMINDEX:
3351 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3353 case OP_LCONV_TO_I1:
3354 case OP_ICONV_TO_I1:
3356 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3358 case OP_LCONV_TO_I2:
3359 case OP_ICONV_TO_I2:
3361 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3363 case OP_LCONV_TO_U1:
3364 case OP_ICONV_TO_U1:
3365 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3367 case OP_LCONV_TO_U2:
3368 case OP_ICONV_TO_U2:
3369 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3372 /* Clean out the upper word */
3373 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3376 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3380 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3382 case OP_COMPARE_IMM:
3383 case OP_LCOMPARE_IMM:
3384 g_assert (amd64_is_imm32 (ins->inst_imm));
3385 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3387 case OP_X86_COMPARE_REG_MEMBASE:
3388 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3390 case OP_X86_TEST_NULL:
3391 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3393 case OP_AMD64_TEST_NULL:
3394 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3397 case OP_X86_ADD_REG_MEMBASE:
3398 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3400 case OP_X86_SUB_REG_MEMBASE:
3401 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3403 case OP_X86_AND_REG_MEMBASE:
3404 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3406 case OP_X86_OR_REG_MEMBASE:
3407 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3409 case OP_X86_XOR_REG_MEMBASE:
3410 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3413 case OP_X86_ADD_MEMBASE_IMM:
3414 /* FIXME: Make a 64 version too */
3415 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3417 case OP_X86_SUB_MEMBASE_IMM:
3418 g_assert (amd64_is_imm32 (ins->inst_imm));
3419 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3421 case OP_X86_AND_MEMBASE_IMM:
3422 g_assert (amd64_is_imm32 (ins->inst_imm));
3423 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3425 case OP_X86_OR_MEMBASE_IMM:
3426 g_assert (amd64_is_imm32 (ins->inst_imm));
3427 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3429 case OP_X86_XOR_MEMBASE_IMM:
3430 g_assert (amd64_is_imm32 (ins->inst_imm));
3431 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3433 case OP_X86_ADD_MEMBASE_REG:
3434 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3436 case OP_X86_SUB_MEMBASE_REG:
3437 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3439 case OP_X86_AND_MEMBASE_REG:
3440 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3442 case OP_X86_OR_MEMBASE_REG:
3443 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3445 case OP_X86_XOR_MEMBASE_REG:
3446 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3448 case OP_X86_INC_MEMBASE:
3449 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3451 case OP_X86_INC_REG:
3452 amd64_inc_reg_size (code, ins->dreg, 4);
3454 case OP_X86_DEC_MEMBASE:
3455 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3457 case OP_X86_DEC_REG:
3458 amd64_dec_reg_size (code, ins->dreg, 4);
3460 case OP_X86_MUL_REG_MEMBASE:
3461 case OP_X86_MUL_MEMBASE_REG:
3462 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3464 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3465 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3467 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3468 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3470 case OP_AMD64_COMPARE_MEMBASE_REG:
3471 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3473 case OP_AMD64_COMPARE_MEMBASE_IMM:
3474 g_assert (amd64_is_imm32 (ins->inst_imm));
3475 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3477 case OP_X86_COMPARE_MEMBASE8_IMM:
3478 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3480 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3481 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3483 case OP_AMD64_COMPARE_REG_MEMBASE:
3484 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3487 case OP_AMD64_ADD_REG_MEMBASE:
3488 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3490 case OP_AMD64_SUB_REG_MEMBASE:
3491 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3493 case OP_AMD64_AND_REG_MEMBASE:
3494 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3496 case OP_AMD64_OR_REG_MEMBASE:
3497 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3499 case OP_AMD64_XOR_REG_MEMBASE:
3500 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3503 case OP_AMD64_ADD_MEMBASE_REG:
3504 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3506 case OP_AMD64_SUB_MEMBASE_REG:
3507 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3509 case OP_AMD64_AND_MEMBASE_REG:
3510 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3512 case OP_AMD64_OR_MEMBASE_REG:
3513 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3515 case OP_AMD64_XOR_MEMBASE_REG:
3516 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3519 case OP_AMD64_ADD_MEMBASE_IMM:
3520 g_assert (amd64_is_imm32 (ins->inst_imm));
3521 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3523 case OP_AMD64_SUB_MEMBASE_IMM:
3524 g_assert (amd64_is_imm32 (ins->inst_imm));
3525 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3527 case OP_AMD64_AND_MEMBASE_IMM:
3528 g_assert (amd64_is_imm32 (ins->inst_imm));
3529 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3531 case OP_AMD64_OR_MEMBASE_IMM:
3532 g_assert (amd64_is_imm32 (ins->inst_imm));
3533 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3535 case OP_AMD64_XOR_MEMBASE_IMM:
3536 g_assert (amd64_is_imm32 (ins->inst_imm));
3537 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3541 amd64_breakpoint (code);
3543 case OP_RELAXED_NOP:
3544 x86_prefix (code, X86_REP_PREFIX);
3552 case OP_DUMMY_STORE:
3553 case OP_NOT_REACHED:
3556 case OP_SEQ_POINT: {
3559 if (cfg->compile_aot)
3563 * Read from the single stepping trigger page. This will cause a
3564 * SIGSEGV when single stepping is enabled.
3565 * We do this _before_ the breakpoint, so single stepping after
3566 * a breakpoint is hit will step to the next IL offset.
3568 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3569 if (((guint64)ss_trigger_page >> 32) == 0)
3570 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3572 MonoInst *var = cfg->arch.ss_trigger_page_var;
3574 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3575 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3580 * This is the address which is saved in seq points,
3581 * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3582 * from the address of the instruction causing the fault.
3584 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3587 * A placeholder for a possible breakpoint inserted by
3588 * mono_arch_set_breakpoint ().
3590 for (i = 0; i < breakpoint_size; ++i)
3596 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3599 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3603 g_assert (amd64_is_imm32 (ins->inst_imm));
3604 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3607 g_assert (amd64_is_imm32 (ins->inst_imm));
3608 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3612 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3615 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3619 g_assert (amd64_is_imm32 (ins->inst_imm));
3620 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3623 g_assert (amd64_is_imm32 (ins->inst_imm));
3624 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3627 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3631 g_assert (amd64_is_imm32 (ins->inst_imm));
3632 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3635 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3640 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3642 switch (ins->inst_imm) {
3646 if (ins->dreg != ins->sreg1)
3647 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3648 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3651 /* LEA r1, [r2 + r2*2] */
3652 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3655 /* LEA r1, [r2 + r2*4] */
3656 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3659 /* LEA r1, [r2 + r2*2] */
3661 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3662 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3665 /* LEA r1, [r2 + r2*8] */
3666 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3669 /* LEA r1, [r2 + r2*4] */
3671 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3672 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3675 /* LEA r1, [r2 + r2*2] */
3677 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3678 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3681 /* LEA r1, [r2 + r2*4] */
3682 /* LEA r1, [r1 + r1*4] */
3683 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3684 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3687 /* LEA r1, [r2 + r2*4] */
3689 /* LEA r1, [r1 + r1*4] */
3690 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3691 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3692 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3695 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3702 /* Regalloc magic makes the div/rem cases the same */
3703 if (ins->sreg2 == AMD64_RDX) {
3704 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3706 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3709 amd64_div_reg (code, ins->sreg2, TRUE);
3714 if (ins->sreg2 == AMD64_RDX) {
3715 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3716 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3717 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3719 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3720 amd64_div_reg (code, ins->sreg2, FALSE);
3725 if (ins->sreg2 == AMD64_RDX) {
3726 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3727 amd64_cdq_size (code, 4);
3728 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3730 amd64_cdq_size (code, 4);
3731 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3736 if (ins->sreg2 == AMD64_RDX) {
3737 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3738 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3739 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3741 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3742 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3746 int power = mono_is_power_of_two (ins->inst_imm);
3748 g_assert (ins->sreg1 == X86_EAX);
3749 g_assert (ins->dreg == X86_EAX);
3750 g_assert (power >= 0);
3753 amd64_mov_reg_imm (code, ins->dreg, 0);
3757 /* Based on gcc code */
3759 /* Add compensation for negative dividents */
3760 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3762 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3763 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3764 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3765 /* Compute remainder */
3766 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3767 /* Remove compensation */
3768 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3772 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3773 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3776 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3780 g_assert (amd64_is_imm32 (ins->inst_imm));
3781 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3784 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3788 g_assert (amd64_is_imm32 (ins->inst_imm));
3789 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3792 g_assert (ins->sreg2 == AMD64_RCX);
3793 amd64_shift_reg (code, X86_SHL, ins->dreg);
3796 g_assert (ins->sreg2 == AMD64_RCX);
3797 amd64_shift_reg (code, X86_SAR, ins->dreg);
3800 g_assert (amd64_is_imm32 (ins->inst_imm));
3801 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3804 g_assert (amd64_is_imm32 (ins->inst_imm));
3805 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3808 g_assert (amd64_is_imm32 (ins->inst_imm));
3809 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3811 case OP_LSHR_UN_IMM:
3812 g_assert (amd64_is_imm32 (ins->inst_imm));
3813 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3816 g_assert (ins->sreg2 == AMD64_RCX);
3817 amd64_shift_reg (code, X86_SHR, ins->dreg);
3820 g_assert (amd64_is_imm32 (ins->inst_imm));
3821 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3824 g_assert (amd64_is_imm32 (ins->inst_imm));
3825 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3830 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3833 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3836 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3839 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3843 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3846 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3849 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3852 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3855 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3858 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3861 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3864 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3867 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3870 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3873 amd64_neg_reg_size (code, ins->sreg1, 4);
3876 amd64_not_reg_size (code, ins->sreg1, 4);
3879 g_assert (ins->sreg2 == AMD64_RCX);
3880 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3883 g_assert (ins->sreg2 == AMD64_RCX);
3884 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3887 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3889 case OP_ISHR_UN_IMM:
3890 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3893 g_assert (ins->sreg2 == AMD64_RCX);
3894 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3897 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3900 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3903 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3904 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3906 case OP_IMUL_OVF_UN:
3907 case OP_LMUL_OVF_UN: {
3908 /* the mul operation and the exception check should most likely be split */
3909 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3910 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3911 /*g_assert (ins->sreg2 == X86_EAX);
3912 g_assert (ins->dreg == X86_EAX);*/
3913 if (ins->sreg2 == X86_EAX) {
3914 non_eax_reg = ins->sreg1;
3915 } else if (ins->sreg1 == X86_EAX) {
3916 non_eax_reg = ins->sreg2;
3918 /* no need to save since we're going to store to it anyway */
3919 if (ins->dreg != X86_EAX) {
3921 amd64_push_reg (code, X86_EAX);
3923 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3924 non_eax_reg = ins->sreg2;
3926 if (ins->dreg == X86_EDX) {
3929 amd64_push_reg (code, X86_EAX);
3933 amd64_push_reg (code, X86_EDX);
3935 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3936 /* save before the check since pop and mov don't change the flags */
3937 if (ins->dreg != X86_EAX)
3938 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3940 amd64_pop_reg (code, X86_EDX);
3942 amd64_pop_reg (code, X86_EAX);
3943 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3947 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3949 case OP_ICOMPARE_IMM:
3950 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3972 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3980 case OP_CMOV_INE_UN:
3981 case OP_CMOV_IGE_UN:
3982 case OP_CMOV_IGT_UN:
3983 case OP_CMOV_ILE_UN:
3984 case OP_CMOV_ILT_UN:
3990 case OP_CMOV_LNE_UN:
3991 case OP_CMOV_LGE_UN:
3992 case OP_CMOV_LGT_UN:
3993 case OP_CMOV_LLE_UN:
3994 case OP_CMOV_LLT_UN:
3995 g_assert (ins->dreg == ins->sreg1);
3996 /* This needs to operate on 64 bit values */
3997 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4001 amd64_not_reg (code, ins->sreg1);
4004 amd64_neg_reg (code, ins->sreg1);
4009 if ((((guint64)ins->inst_c0) >> 32) == 0)
4010 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4012 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4015 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4016 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4019 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4020 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4023 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4025 case OP_AMD64_SET_XMMREG_R4: {
4026 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4029 case OP_AMD64_SET_XMMREG_R8: {
4030 if (ins->dreg != ins->sreg1)
4031 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4036 * Note: this 'frame destruction' logic is useful for tail calls, too.
4037 * Keep in sync with the code in emit_epilog.
4041 /* FIXME: no tracing support... */
4042 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4043 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4045 g_assert (!cfg->method->save_lmf);
4047 if (cfg->arch.omit_fp) {
4048 guint32 save_offset = 0;
4049 /* Pop callee-saved registers */
4050 for (i = 0; i < AMD64_NREG; ++i)
4051 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4052 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4055 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4058 for (i = 0; i < AMD64_NREG; ++i)
4059 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4060 pos -= sizeof (gpointer);
4063 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4065 /* Pop registers in reverse order */
4066 for (i = AMD64_NREG - 1; i > 0; --i)
4067 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4068 amd64_pop_reg (code, i);
4074 offset = code - cfg->native_code;
4075 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4076 if (cfg->compile_aot)
4077 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4079 amd64_set_reg_template (code, AMD64_R11);
4080 amd64_jump_reg (code, AMD64_R11);
4084 /* ensure ins->sreg1 is not NULL */
4085 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4088 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4089 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4098 call = (MonoCallInst*)ins;
4100 * The AMD64 ABI forces callers to know about varargs.
4102 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4103 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4104 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4106 * Since the unmanaged calling convention doesn't contain a
4107 * 'vararg' entry, we have to treat every pinvoke call as a
4108 * potential vararg call.
4112 for (i = 0; i < AMD64_XMM_NREG; ++i)
4113 if (call->used_fregs & (1 << i))
4116 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4118 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4121 if (ins->flags & MONO_INST_HAS_METHOD)
4122 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4124 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4125 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4126 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4127 code = emit_move_return_value (cfg, ins, code);
4133 case OP_VOIDCALL_REG:
4135 call = (MonoCallInst*)ins;
4137 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4138 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4139 ins->sreg1 = AMD64_R11;
4143 * The AMD64 ABI forces callers to know about varargs.
4145 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4146 if (ins->sreg1 == AMD64_RAX) {
4147 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4148 ins->sreg1 = AMD64_R11;
4150 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4151 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4153 * Since the unmanaged calling convention doesn't contain a
4154 * 'vararg' entry, we have to treat every pinvoke call as a
4155 * potential vararg call.
4159 for (i = 0; i < AMD64_XMM_NREG; ++i)
4160 if (call->used_fregs & (1 << i))
4162 if (ins->sreg1 == AMD64_RAX) {
4163 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4164 ins->sreg1 = AMD64_R11;
4167 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4169 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4172 amd64_call_reg (code, ins->sreg1);
4173 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4174 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4175 code = emit_move_return_value (cfg, ins, code);
4177 case OP_FCALL_MEMBASE:
4178 case OP_LCALL_MEMBASE:
4179 case OP_VCALL_MEMBASE:
4180 case OP_VCALL2_MEMBASE:
4181 case OP_VOIDCALL_MEMBASE:
4182 case OP_CALL_MEMBASE:
4183 call = (MonoCallInst*)ins;
4185 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4187 * Can't use R11 because it is clobbered by the trampoline
4188 * code, and the reg value is needed by get_vcall_slot_addr.
4190 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4191 ins->sreg1 = AMD64_RAX;
4195 * Emit a few nops to simplify get_vcall_slot ().
4201 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4202 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4203 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4204 code = emit_move_return_value (cfg, ins, code);
4208 MonoInst *var = cfg->dyn_call_var;
4210 g_assert (var->opcode == OP_REGOFFSET);
4212 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4213 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4215 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4217 /* Save args buffer */
4218 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4220 /* Set argument registers */
4221 for (i = 0; i < PARAM_REGS; ++i)
4222 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4225 amd64_call_reg (code, AMD64_R10);
4228 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4229 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4232 case OP_AMD64_SAVE_SP_TO_LMF:
4233 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4236 g_assert (!cfg->arch.no_pushes);
4237 amd64_push_reg (code, ins->sreg1);
4239 case OP_X86_PUSH_IMM:
4240 g_assert (!cfg->arch.no_pushes);
4241 g_assert (amd64_is_imm32 (ins->inst_imm));
4242 amd64_push_imm (code, ins->inst_imm);
4244 case OP_X86_PUSH_MEMBASE:
4245 g_assert (!cfg->arch.no_pushes);
4246 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4248 case OP_X86_PUSH_OBJ: {
4249 int size = ALIGN_TO (ins->inst_imm, 8);
4251 g_assert (!cfg->arch.no_pushes);
4253 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4254 amd64_push_reg (code, AMD64_RDI);
4255 amd64_push_reg (code, AMD64_RSI);
4256 amd64_push_reg (code, AMD64_RCX);
4257 if (ins->inst_offset)
4258 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4260 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4261 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4262 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4264 amd64_prefix (code, X86_REP_PREFIX);
4266 amd64_pop_reg (code, AMD64_RCX);
4267 amd64_pop_reg (code, AMD64_RSI);
4268 amd64_pop_reg (code, AMD64_RDI);
4272 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4274 case OP_X86_LEA_MEMBASE:
4275 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4278 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4281 /* keep alignment */
4282 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4283 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4284 code = mono_emit_stack_alloc (cfg, code, ins);
4285 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4286 if (cfg->param_area && cfg->arch.no_pushes)
4287 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4289 case OP_LOCALLOC_IMM: {
4290 guint32 size = ins->inst_imm;
4291 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4293 if (ins->flags & MONO_INST_INIT) {
4297 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4298 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4300 for (i = 0; i < size; i += 8)
4301 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4302 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4304 amd64_mov_reg_imm (code, ins->dreg, size);
4305 ins->sreg1 = ins->dreg;
4307 code = mono_emit_stack_alloc (cfg, code, ins);
4308 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4311 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4312 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4314 if (cfg->param_area && cfg->arch.no_pushes)
4315 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4319 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4320 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4321 (gpointer)"mono_arch_throw_exception", FALSE);
4325 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4326 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4327 (gpointer)"mono_arch_rethrow_exception", FALSE);
4330 case OP_CALL_HANDLER:
4332 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4333 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4334 amd64_call_imm (code, 0);
4335 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4336 /* Restore stack alignment */
4337 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4339 case OP_START_HANDLER: {
4340 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4341 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4343 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4344 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4345 cfg->param_area && cfg->arch.no_pushes) {
4346 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4350 case OP_ENDFINALLY: {
4351 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4352 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4356 case OP_ENDFILTER: {
4357 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4358 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4359 /* The local allocator will put the result into RAX */
4365 ins->inst_c0 = code - cfg->native_code;
4368 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4369 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4371 if (ins->inst_target_bb->native_offset) {
4372 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4374 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4375 if ((cfg->opt & MONO_OPT_BRANCH) &&
4376 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4377 x86_jump8 (code, 0);
4379 x86_jump32 (code, 0);
4383 amd64_jump_reg (code, ins->sreg1);
4400 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4401 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4403 case OP_COND_EXC_EQ:
4404 case OP_COND_EXC_NE_UN:
4405 case OP_COND_EXC_LT:
4406 case OP_COND_EXC_LT_UN:
4407 case OP_COND_EXC_GT:
4408 case OP_COND_EXC_GT_UN:
4409 case OP_COND_EXC_GE:
4410 case OP_COND_EXC_GE_UN:
4411 case OP_COND_EXC_LE:
4412 case OP_COND_EXC_LE_UN:
4413 case OP_COND_EXC_IEQ:
4414 case OP_COND_EXC_INE_UN:
4415 case OP_COND_EXC_ILT:
4416 case OP_COND_EXC_ILT_UN:
4417 case OP_COND_EXC_IGT:
4418 case OP_COND_EXC_IGT_UN:
4419 case OP_COND_EXC_IGE:
4420 case OP_COND_EXC_IGE_UN:
4421 case OP_COND_EXC_ILE:
4422 case OP_COND_EXC_ILE_UN:
4423 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4425 case OP_COND_EXC_OV:
4426 case OP_COND_EXC_NO:
4428 case OP_COND_EXC_NC:
4429 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4430 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4432 case OP_COND_EXC_IOV:
4433 case OP_COND_EXC_INO:
4434 case OP_COND_EXC_IC:
4435 case OP_COND_EXC_INC:
4436 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4437 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4440 /* floating point opcodes */
4442 double d = *(double *)ins->inst_p0;
4444 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4445 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4448 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4449 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4454 float f = *(float *)ins->inst_p0;
4456 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4457 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4460 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4461 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4462 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4466 case OP_STORER8_MEMBASE_REG:
4467 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4469 case OP_LOADR8_MEMBASE:
4470 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4472 case OP_STORER4_MEMBASE_REG:
4473 /* This requires a double->single conversion */
4474 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4475 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4477 case OP_LOADR4_MEMBASE:
4478 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4479 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4481 case OP_ICONV_TO_R4: /* FIXME: change precision */
4482 case OP_ICONV_TO_R8:
4483 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4485 case OP_LCONV_TO_R4: /* FIXME: change precision */
4486 case OP_LCONV_TO_R8:
4487 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4489 case OP_FCONV_TO_R4:
4490 /* FIXME: nothing to do ?? */
4492 case OP_FCONV_TO_I1:
4493 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4495 case OP_FCONV_TO_U1:
4496 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4498 case OP_FCONV_TO_I2:
4499 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4501 case OP_FCONV_TO_U2:
4502 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4504 case OP_FCONV_TO_U4:
4505 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4507 case OP_FCONV_TO_I4:
4509 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4511 case OP_FCONV_TO_I8:
4512 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4514 case OP_LCONV_TO_R_UN: {
4517 /* Based on gcc code */
4518 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4519 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4522 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4523 br [1] = code; x86_jump8 (code, 0);
4524 amd64_patch (br [0], code);
4527 /* Save to the red zone */
4528 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4529 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4530 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4531 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4532 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4533 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4534 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4535 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4536 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4538 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4539 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4540 amd64_patch (br [1], code);
4543 case OP_LCONV_TO_OVF_U4:
4544 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4545 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4546 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4548 case OP_LCONV_TO_OVF_I4_UN:
4549 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4550 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4551 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4554 if (ins->dreg != ins->sreg1)
4555 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4558 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4561 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4564 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4567 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4570 static double r8_0 = -0.0;
4572 g_assert (ins->sreg1 == ins->dreg);
4574 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4575 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4579 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4582 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4585 static guint64 d = 0x7fffffffffffffffUL;
4587 g_assert (ins->sreg1 == ins->dreg);
4589 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4590 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4594 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4597 g_assert (cfg->opt & MONO_OPT_CMOV);
4598 g_assert (ins->dreg == ins->sreg1);
4599 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4600 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4603 g_assert (cfg->opt & MONO_OPT_CMOV);
4604 g_assert (ins->dreg == ins->sreg1);
4605 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4606 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4609 g_assert (cfg->opt & MONO_OPT_CMOV);
4610 g_assert (ins->dreg == ins->sreg1);
4611 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4612 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4615 g_assert (cfg->opt & MONO_OPT_CMOV);
4616 g_assert (ins->dreg == ins->sreg1);
4617 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4618 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4621 g_assert (cfg->opt & MONO_OPT_CMOV);
4622 g_assert (ins->dreg == ins->sreg1);
4623 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4624 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4627 g_assert (cfg->opt & MONO_OPT_CMOV);
4628 g_assert (ins->dreg == ins->sreg1);
4629 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4630 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4633 g_assert (cfg->opt & MONO_OPT_CMOV);
4634 g_assert (ins->dreg == ins->sreg1);
4635 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4636 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4639 g_assert (cfg->opt & MONO_OPT_CMOV);
4640 g_assert (ins->dreg == ins->sreg1);
4641 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4642 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4648 * The two arguments are swapped because the fbranch instructions
4649 * depend on this for the non-sse case to work.
4651 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4654 /* zeroing the register at the start results in
4655 * shorter and faster code (we can also remove the widening op)
4657 guchar *unordered_check;
4658 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4659 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4660 unordered_check = code;
4661 x86_branch8 (code, X86_CC_P, 0, FALSE);
4662 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4663 amd64_patch (unordered_check, code);
4668 /* zeroing the register at the start results in
4669 * shorter and faster code (we can also remove the widening op)
4671 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4672 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4673 if (ins->opcode == OP_FCLT_UN) {
4674 guchar *unordered_check = code;
4675 guchar *jump_to_end;
4676 x86_branch8 (code, X86_CC_P, 0, FALSE);
4677 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4679 x86_jump8 (code, 0);
4680 amd64_patch (unordered_check, code);
4681 amd64_inc_reg (code, ins->dreg);
4682 amd64_patch (jump_to_end, code);
4684 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4689 /* zeroing the register at the start results in
4690 * shorter and faster code (we can also remove the widening op)
4692 guchar *unordered_check;
4693 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4694 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4695 if (ins->opcode == OP_FCGT) {
4696 unordered_check = code;
4697 x86_branch8 (code, X86_CC_P, 0, FALSE);
4698 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4699 amd64_patch (unordered_check, code);
4701 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4705 case OP_FCLT_MEMBASE:
4706 case OP_FCGT_MEMBASE:
4707 case OP_FCLT_UN_MEMBASE:
4708 case OP_FCGT_UN_MEMBASE:
4709 case OP_FCEQ_MEMBASE: {
4710 guchar *unordered_check, *jump_to_end;
4713 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4714 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4716 switch (ins->opcode) {
4717 case OP_FCEQ_MEMBASE:
4718 x86_cond = X86_CC_EQ;
4720 case OP_FCLT_MEMBASE:
4721 case OP_FCLT_UN_MEMBASE:
4722 x86_cond = X86_CC_LT;
4724 case OP_FCGT_MEMBASE:
4725 case OP_FCGT_UN_MEMBASE:
4726 x86_cond = X86_CC_GT;
4729 g_assert_not_reached ();
4732 unordered_check = code;
4733 x86_branch8 (code, X86_CC_P, 0, FALSE);
4734 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4736 switch (ins->opcode) {
4737 case OP_FCEQ_MEMBASE:
4738 case OP_FCLT_MEMBASE:
4739 case OP_FCGT_MEMBASE:
4740 amd64_patch (unordered_check, code);
4742 case OP_FCLT_UN_MEMBASE:
4743 case OP_FCGT_UN_MEMBASE:
4745 x86_jump8 (code, 0);
4746 amd64_patch (unordered_check, code);
4747 amd64_inc_reg (code, ins->dreg);
4748 amd64_patch (jump_to_end, code);
4756 guchar *jump = code;
4757 x86_branch8 (code, X86_CC_P, 0, TRUE);
4758 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4759 amd64_patch (jump, code);
4763 /* Branch if C013 != 100 */
4764 /* branch if !ZF or (PF|CF) */
4765 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4766 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4767 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4770 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4773 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4774 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4778 if (ins->opcode == OP_FBGT) {
4781 /* skip branch if C1=1 */
4783 x86_branch8 (code, X86_CC_P, 0, FALSE);
4784 /* branch if (C0 | C3) = 1 */
4785 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4786 amd64_patch (br1, code);
4789 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4793 /* Branch if C013 == 100 or 001 */
4796 /* skip branch if C1=1 */
4798 x86_branch8 (code, X86_CC_P, 0, FALSE);
4799 /* branch if (C0 | C3) = 1 */
4800 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4801 amd64_patch (br1, code);
4805 /* Branch if C013 == 000 */
4806 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4809 /* Branch if C013=000 or 100 */
4812 /* skip branch if C1=1 */
4814 x86_branch8 (code, X86_CC_P, 0, FALSE);
4815 /* branch if C0=0 */
4816 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4817 amd64_patch (br1, code);
4821 /* Branch if C013 != 001 */
4822 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4823 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4826 /* Transfer value to the fp stack */
4827 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4828 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4829 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4831 amd64_push_reg (code, AMD64_RAX);
4833 amd64_fnstsw (code);
4834 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4835 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4836 amd64_pop_reg (code, AMD64_RAX);
4837 amd64_fstp (code, 0);
4838 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4839 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4842 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4845 case OP_MEMORY_BARRIER: {
4846 /* Not needed on amd64 */
4849 case OP_ATOMIC_ADD_I4:
4850 case OP_ATOMIC_ADD_I8: {
4851 int dreg = ins->dreg;
4852 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4854 if (dreg == ins->inst_basereg)
4857 if (dreg != ins->sreg2)
4858 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4860 x86_prefix (code, X86_LOCK_PREFIX);
4861 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4863 if (dreg != ins->dreg)
4864 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4868 case OP_ATOMIC_ADD_NEW_I4:
4869 case OP_ATOMIC_ADD_NEW_I8: {
4870 int dreg = ins->dreg;
4871 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4873 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4876 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4877 amd64_prefix (code, X86_LOCK_PREFIX);
4878 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4879 /* dreg contains the old value, add with sreg2 value */
4880 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4882 if (ins->dreg != dreg)
4883 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4887 case OP_ATOMIC_EXCHANGE_I4:
4888 case OP_ATOMIC_EXCHANGE_I8: {
4890 int sreg2 = ins->sreg2;
4891 int breg = ins->inst_basereg;
4893 gboolean need_push = FALSE, rdx_pushed = FALSE;
4895 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4901 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4902 * an explanation of how this works.
4905 /* cmpxchg uses eax as comperand, need to make sure we can use it
4906 * hack to overcome limits in x86 reg allocator
4907 * (req: dreg == eax and sreg2 != eax and breg != eax)
4909 g_assert (ins->dreg == AMD64_RAX);
4911 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4912 /* Highly unlikely, but possible */
4915 /* The pushes invalidate rsp */
4916 if ((breg == AMD64_RAX) || need_push) {
4917 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4921 /* We need the EAX reg for the comparand */
4922 if (ins->sreg2 == AMD64_RAX) {
4923 if (breg != AMD64_R11) {
4924 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4927 g_assert (need_push);
4928 amd64_push_reg (code, AMD64_RDX);
4929 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4935 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4937 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4938 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4939 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4940 amd64_patch (br [1], br [0]);
4943 amd64_pop_reg (code, AMD64_RDX);
4947 case OP_ATOMIC_CAS_I4:
4948 case OP_ATOMIC_CAS_I8: {
4951 if (ins->opcode == OP_ATOMIC_CAS_I8)
4957 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4958 * an explanation of how this works.
4960 g_assert (ins->sreg3 == AMD64_RAX);
4961 g_assert (ins->sreg1 != AMD64_RAX);
4962 g_assert (ins->sreg1 != ins->sreg2);
4964 amd64_prefix (code, X86_LOCK_PREFIX);
4965 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4967 if (ins->dreg != AMD64_RAX)
4968 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4971 #ifdef MONO_ARCH_SIMD_INTRINSICS
4972 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4974 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4977 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4980 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4983 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4986 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4989 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4992 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4993 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4996 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4999 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5002 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5005 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5008 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5011 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5014 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5017 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5020 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5023 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5026 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5029 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5032 case OP_PSHUFLEW_HIGH:
5033 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5034 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5036 case OP_PSHUFLEW_LOW:
5037 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5038 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5041 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5042 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5046 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5049 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5052 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5055 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5058 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5061 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5064 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5065 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5068 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5071 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5074 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5077 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5080 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5083 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5086 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5089 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5092 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5095 case OP_EXTRACT_MASK:
5096 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5100 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5103 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5106 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5110 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5113 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5116 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5119 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5123 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5126 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5129 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5132 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5136 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5139 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5142 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5146 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5149 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5152 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5156 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5159 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5163 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5166 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5169 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5173 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5176 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5179 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5183 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5186 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5189 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5192 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5196 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5199 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5202 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5205 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5208 case OP_PSUM_ABS_DIFF:
5209 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5212 case OP_UNPACK_LOWB:
5213 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5215 case OP_UNPACK_LOWW:
5216 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5218 case OP_UNPACK_LOWD:
5219 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5221 case OP_UNPACK_LOWQ:
5222 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5224 case OP_UNPACK_LOWPS:
5225 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5227 case OP_UNPACK_LOWPD:
5228 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5231 case OP_UNPACK_HIGHB:
5232 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5234 case OP_UNPACK_HIGHW:
5235 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5237 case OP_UNPACK_HIGHD:
5238 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5240 case OP_UNPACK_HIGHQ:
5241 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5243 case OP_UNPACK_HIGHPS:
5244 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5246 case OP_UNPACK_HIGHPD:
5247 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5251 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5254 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5257 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5260 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5263 case OP_PADDB_SAT_UN:
5264 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5266 case OP_PSUBB_SAT_UN:
5267 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5269 case OP_PADDW_SAT_UN:
5270 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5272 case OP_PSUBW_SAT_UN:
5273 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5277 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5280 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5283 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5286 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5290 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5293 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5296 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5298 case OP_PMULW_HIGH_UN:
5299 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5302 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5306 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5309 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5313 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5316 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5320 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5323 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5327 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5330 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5334 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5337 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5341 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5344 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5348 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5351 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5354 /*TODO: This is appart of the sse spec but not added
5356 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5359 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5364 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5367 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5371 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5374 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5378 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5379 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5381 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5386 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5388 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5389 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5393 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5395 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5396 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5397 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5401 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5403 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5406 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5408 case OP_EXTRACTX_U2:
5409 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5411 case OP_INSERTX_U1_SLOW:
5412 /*sreg1 is the extracted ireg (scratch)
5413 /sreg2 is the to be inserted ireg (scratch)
5414 /dreg is the xreg to receive the value*/
5416 /*clear the bits from the extracted word*/
5417 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5418 /*shift the value to insert if needed*/
5419 if (ins->inst_c0 & 1)
5420 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5421 /*join them together*/
5422 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5423 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5425 case OP_INSERTX_I4_SLOW:
5426 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5427 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5428 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5430 case OP_INSERTX_I8_SLOW:
5431 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5433 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5435 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5438 case OP_INSERTX_R4_SLOW:
5439 switch (ins->inst_c0) {
5441 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5444 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5445 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5446 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5449 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5450 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5451 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5454 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5455 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5456 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5460 case OP_INSERTX_R8_SLOW:
5462 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5464 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5466 case OP_STOREX_MEMBASE_REG:
5467 case OP_STOREX_MEMBASE:
5468 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5470 case OP_LOADX_MEMBASE:
5471 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5473 case OP_LOADX_ALIGNED_MEMBASE:
5474 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5476 case OP_STOREX_ALIGNED_MEMBASE_REG:
5477 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5479 case OP_STOREX_NTA_MEMBASE_REG:
5480 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5482 case OP_PREFETCH_MEMBASE:
5483 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5487 /*FIXME the peephole pass should have killed this*/
5488 if (ins->dreg != ins->sreg1)
5489 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5492 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5494 case OP_ICONV_TO_R8_RAW:
5495 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5496 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5499 case OP_FCONV_TO_R8_X:
5500 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5503 case OP_XCONV_R8_TO_I4:
5504 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5505 switch (ins->backend.source_opcode) {
5506 case OP_FCONV_TO_I1:
5507 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5509 case OP_FCONV_TO_U1:
5510 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5512 case OP_FCONV_TO_I2:
5513 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5515 case OP_FCONV_TO_U2:
5516 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5522 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5523 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5524 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5527 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5528 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5531 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5532 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5535 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5536 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5537 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5540 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5541 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5544 case OP_LIVERANGE_START: {
5545 if (cfg->verbose_level > 1)
5546 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5547 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5550 case OP_LIVERANGE_END: {
5551 if (cfg->verbose_level > 1)
5552 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5553 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5557 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5558 g_assert_not_reached ();
5561 if ((code - cfg->native_code - offset) > max_len) {
5562 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5563 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5564 g_assert_not_reached ();
5568 last_offset = offset;
5571 cfg->code_len = code - cfg->native_code;
5574 #endif /* DISABLE_JIT */
5577 mono_arch_register_lowlevel_calls (void)
5579 /* The signature doesn't matter */
5580 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5584 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5586 MonoJumpInfo *patch_info;
5587 gboolean compile_aot = !run_cctors;
5589 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5590 unsigned char *ip = patch_info->ip.i + code;
5591 unsigned char *target;
5593 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5596 switch (patch_info->type) {
5597 case MONO_PATCH_INFO_BB:
5598 case MONO_PATCH_INFO_LABEL:
5601 /* No need to patch these */
5606 switch (patch_info->type) {
5607 case MONO_PATCH_INFO_NONE:
5609 case MONO_PATCH_INFO_METHOD_REL:
5610 case MONO_PATCH_INFO_R8:
5611 case MONO_PATCH_INFO_R4:
5612 g_assert_not_reached ();
5614 case MONO_PATCH_INFO_BB:
5621 * Debug code to help track down problems where the target of a near call is
5624 if (amd64_is_near_call (ip)) {
5625 gint64 disp = (guint8*)target - (guint8*)ip;
5627 if (!amd64_is_imm32 (disp)) {
5628 printf ("TYPE: %d\n", patch_info->type);
5629 switch (patch_info->type) {
5630 case MONO_PATCH_INFO_INTERNAL_METHOD:
5631 printf ("V: %s\n", patch_info->data.name);
5633 case MONO_PATCH_INFO_METHOD_JUMP:
5634 case MONO_PATCH_INFO_METHOD:
5635 printf ("V: %s\n", patch_info->data.method->name);
5643 amd64_patch (ip, (gpointer)target);
5650 get_max_epilog_size (MonoCompile *cfg)
5652 int max_epilog_size = 16;
5654 if (cfg->method->save_lmf)
5655 max_epilog_size += 256;
5657 if (mono_jit_trace_calls != NULL)
5658 max_epilog_size += 50;
5660 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5661 max_epilog_size += 50;
5663 max_epilog_size += (AMD64_NREG * 2);
5665 return max_epilog_size;
5669 * This macro is used for testing whenever the unwinder works correctly at every point
5670 * where an async exception can happen.
5672 /* This will generate a SIGSEGV at the given point in the code */
5673 #define async_exc_point(code) do { \
5674 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5675 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5676 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5677 cfg->arch.async_point_count ++; \
5682 mono_arch_emit_prolog (MonoCompile *cfg)
5684 MonoMethod *method = cfg->method;
5686 MonoMethodSignature *sig;
5688 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5691 gint32 lmf_offset = cfg->arch.lmf_offset;
5692 gboolean args_clobbered = FALSE;
5693 gboolean trace = FALSE;
5695 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5697 code = cfg->native_code = g_malloc (cfg->code_size);
5699 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5702 /* Amount of stack space allocated by register saving code */
5705 /* Offset between RSP and the CFA */
5709 * The prolog consists of the following parts:
5711 * - push rbp, mov rbp, rsp
5712 * - save callee saved regs using pushes
5714 * - save rgctx if needed
5715 * - save lmf if needed
5718 * - save rgctx if needed
5719 * - save lmf if needed
5720 * - save callee saved regs using moves
5725 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5726 // IP saved at CFA - 8
5727 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5728 async_exc_point (code);
5730 if (!cfg->arch.omit_fp) {
5731 amd64_push_reg (code, AMD64_RBP);
5733 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5734 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5735 async_exc_point (code);
5737 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5740 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5741 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5742 async_exc_point (code);
5744 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5748 /* Save callee saved registers */
5749 if (!cfg->arch.omit_fp && !method->save_lmf) {
5750 int offset = cfa_offset;
5752 for (i = 0; i < AMD64_NREG; ++i)
5753 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5754 amd64_push_reg (code, i);
5755 pos += sizeof (gpointer);
5757 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5758 async_exc_point (code);
5762 /* The param area is always at offset 0 from sp */
5763 /* This needs to be allocated here, since it has to come after the spill area */
5764 if (cfg->arch.no_pushes && cfg->param_area) {
5765 if (cfg->arch.omit_fp)
5767 g_assert_not_reached ();
5768 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5771 if (cfg->arch.omit_fp) {
5773 * On enter, the stack is misaligned by the the pushing of the return
5774 * address. It is either made aligned by the pushing of %rbp, or by
5777 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5778 if ((alloc_size % 16) == 0)
5781 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5786 cfg->arch.stack_alloc_size = alloc_size;
5788 /* Allocate stack frame */
5790 /* See mono_emit_stack_alloc */
5791 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5792 guint32 remaining_size = alloc_size;
5793 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5794 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5795 guint32 offset = code - cfg->native_code;
5796 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5797 while (required_code_size >= (cfg->code_size - offset))
5798 cfg->code_size *= 2;
5799 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5800 code = cfg->native_code + offset;
5801 mono_jit_stats.code_reallocs++;
5804 while (remaining_size >= 0x1000) {
5805 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5806 if (cfg->arch.omit_fp) {
5807 cfa_offset += 0x1000;
5808 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5810 async_exc_point (code);
5812 if (cfg->arch.omit_fp)
5813 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5816 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5817 remaining_size -= 0x1000;
5819 if (remaining_size) {
5820 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5821 if (cfg->arch.omit_fp) {
5822 cfa_offset += remaining_size;
5823 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5824 async_exc_point (code);
5827 if (cfg->arch.omit_fp)
5828 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5832 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5833 if (cfg->arch.omit_fp) {
5834 cfa_offset += alloc_size;
5835 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5836 async_exc_point (code);
5841 /* Stack alignment check */
5844 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5845 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5846 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5847 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5848 amd64_breakpoint (code);
5852 #ifndef TARGET_WIN32
5853 if (mini_get_debug_options ()->init_stacks) {
5854 /* Fill the stack frame with a dummy value to force deterministic behavior */
5856 /* Save registers to the red zone */
5857 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5858 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5860 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5861 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5862 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5865 amd64_prefix (code, X86_REP_PREFIX);
5868 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5869 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5874 if (method->save_lmf) {
5876 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5879 * sp is saved right before calls but we need to save it here too so
5880 * async stack walks would work.
5882 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5883 /* Skip method (only needed for trampoline LMF frames) */
5884 /* Save callee saved regs */
5885 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5889 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5890 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5891 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5892 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5893 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5894 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5896 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5897 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5905 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5906 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5907 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5912 /* Save callee saved registers */
5913 if (cfg->arch.omit_fp && !method->save_lmf) {
5914 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5916 /* Save caller saved registers after sp is adjusted */
5917 /* The registers are saved at the bottom of the frame */
5918 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5919 for (i = 0; i < AMD64_NREG; ++i)
5920 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5921 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5922 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5923 save_area_offset += 8;
5924 async_exc_point (code);
5928 /* store runtime generic context */
5929 if (cfg->rgctx_var) {
5930 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5931 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5933 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5936 /* compute max_length in order to use short forward jumps */
5937 max_epilog_size = get_max_epilog_size (cfg);
5938 if (cfg->opt & MONO_OPT_BRANCH) {
5939 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5943 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5945 /* max alignment for loops */
5946 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5947 max_length += LOOP_ALIGNMENT;
5949 MONO_BB_FOR_EACH_INS (bb, ins) {
5950 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5953 /* Take prolog and epilog instrumentation into account */
5954 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5955 max_length += max_epilog_size;
5957 bb->max_length = max_length;
5961 sig = mono_method_signature (method);
5964 cinfo = cfg->arch.cinfo;
5966 if (sig->ret->type != MONO_TYPE_VOID) {
5967 /* Save volatile arguments to the stack */
5968 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5969 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5972 /* Keep this in sync with emit_load_volatile_arguments */
5973 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5974 ArgInfo *ainfo = cinfo->args + i;
5975 gint32 stack_offset;
5978 ins = cfg->args [i];
5980 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5981 /* Unused arguments */
5984 if (sig->hasthis && (i == 0))
5985 arg_type = &mono_defaults.object_class->byval_arg;
5987 arg_type = sig->params [i - sig->hasthis];
5989 stack_offset = ainfo->offset + ARGS_OFFSET;
5991 if (cfg->globalra) {
5992 /* All the other moves are done by the register allocator */
5993 switch (ainfo->storage) {
5994 case ArgInFloatSSEReg:
5995 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5997 case ArgValuetypeInReg:
5998 for (quad = 0; quad < 2; quad ++) {
5999 switch (ainfo->pair_storage [quad]) {
6001 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6003 case ArgInFloatSSEReg:
6004 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6006 case ArgInDoubleSSEReg:
6007 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6012 g_assert_not_reached ();
6023 /* Save volatile arguments to the stack */
6024 if (ins->opcode != OP_REGVAR) {
6025 switch (ainfo->storage) {
6031 if (stack_offset & 0x1)
6033 else if (stack_offset & 0x2)
6035 else if (stack_offset & 0x4)
6040 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6043 case ArgInFloatSSEReg:
6044 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6046 case ArgInDoubleSSEReg:
6047 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6049 case ArgValuetypeInReg:
6050 for (quad = 0; quad < 2; quad ++) {
6051 switch (ainfo->pair_storage [quad]) {
6053 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6055 case ArgInFloatSSEReg:
6056 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6058 case ArgInDoubleSSEReg:
6059 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6064 g_assert_not_reached ();
6068 case ArgValuetypeAddrInIReg:
6069 if (ainfo->pair_storage [0] == ArgInIReg)
6070 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6076 /* Argument allocated to (non-volatile) register */
6077 switch (ainfo->storage) {
6079 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6082 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6085 g_assert_not_reached ();
6090 /* Might need to attach the thread to the JIT or change the domain for the callback */
6091 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6092 guint64 domain = (guint64)cfg->domain;
6094 args_clobbered = TRUE;
6097 * The call might clobber argument registers, but they are already
6098 * saved to the stack/global regs.
6100 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6101 guint8 *buf, *no_domain_branch;
6103 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6104 if (cfg->compile_aot) {
6105 /* AOT code is only used in the root domain */
6106 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6108 if ((domain >> 32) == 0)
6109 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6111 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6113 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6114 no_domain_branch = code;
6115 x86_branch8 (code, X86_CC_NE, 0, 0);
6116 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6117 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6119 x86_branch8 (code, X86_CC_NE, 0, 0);
6120 amd64_patch (no_domain_branch, code);
6121 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6122 (gpointer)"mono_jit_thread_attach", TRUE);
6123 amd64_patch (buf, code);
6125 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6126 /* FIXME: Add a separate key for LMF to avoid this */
6127 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6130 g_assert (!cfg->compile_aot);
6131 if (cfg->compile_aot) {
6132 /* AOT code is only used in the root domain */
6133 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6135 if ((domain >> 32) == 0)
6136 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6138 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6140 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6141 (gpointer)"mono_jit_thread_attach", TRUE);
6145 if (method->save_lmf) {
6146 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6148 * Optimized version which uses the mono_lmf TLS variable instead of
6149 * indirection through the mono_lmf_addr TLS variable.
6151 /* %rax = previous_lmf */
6152 x86_prefix (code, X86_FS_PREFIX);
6153 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6155 /* Save previous_lmf */
6156 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6158 if (lmf_offset == 0) {
6159 x86_prefix (code, X86_FS_PREFIX);
6160 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6162 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6163 x86_prefix (code, X86_FS_PREFIX);
6164 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6167 if (lmf_addr_tls_offset != -1) {
6168 /* Load lmf quicky using the FS register */
6169 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6171 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6172 /* FIXME: Add a separate key for LMF to avoid this */
6173 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6178 * The call might clobber argument registers, but they are already
6179 * saved to the stack/global regs.
6181 args_clobbered = TRUE;
6182 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6183 (gpointer)"mono_get_lmf_addr", TRUE);
6187 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6188 /* Save previous_lmf */
6189 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6190 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6192 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6193 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6198 args_clobbered = TRUE;
6199 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6202 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6203 args_clobbered = TRUE;
6206 * Optimize the common case of the first bblock making a call with the same
6207 * arguments as the method. This works because the arguments are still in their
6208 * original argument registers.
6209 * FIXME: Generalize this
6211 if (!args_clobbered) {
6212 MonoBasicBlock *first_bb = cfg->bb_entry;
6215 next = mono_bb_first_ins (first_bb);
6216 if (!next && first_bb->next_bb) {
6217 first_bb = first_bb->next_bb;
6218 next = mono_bb_first_ins (first_bb);
6221 if (first_bb->in_count > 1)
6224 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6225 ArgInfo *ainfo = cinfo->args + i;
6226 gboolean match = FALSE;
6228 ins = cfg->args [i];
6229 if (ins->opcode != OP_REGVAR) {
6230 switch (ainfo->storage) {
6232 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6233 if (next->dreg == ainfo->reg) {
6237 next->opcode = OP_MOVE;
6238 next->sreg1 = ainfo->reg;
6239 /* Only continue if the instruction doesn't change argument regs */
6240 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6250 /* Argument allocated to (non-volatile) register */
6251 switch (ainfo->storage) {
6253 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6265 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6272 /* Initialize ss_trigger_page_var */
6273 if (cfg->arch.ss_trigger_page_var) {
6274 MonoInst *var = cfg->arch.ss_trigger_page_var;
6276 g_assert (!cfg->compile_aot);
6277 g_assert (var->opcode == OP_REGOFFSET);
6279 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6280 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6283 cfg->code_len = code - cfg->native_code;
6285 g_assert (cfg->code_len < cfg->code_size);
6291 mono_arch_emit_epilog (MonoCompile *cfg)
6293 MonoMethod *method = cfg->method;
6296 int max_epilog_size;
6298 gint32 lmf_offset = cfg->arch.lmf_offset;
6300 max_epilog_size = get_max_epilog_size (cfg);
6302 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6303 cfg->code_size *= 2;
6304 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6305 mono_jit_stats.code_reallocs++;
6308 code = cfg->native_code + cfg->code_len;
6310 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6311 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6313 /* the code restoring the registers must be kept in sync with OP_JMP */
6316 if (method->save_lmf) {
6317 /* check if we need to restore protection of the stack after a stack overflow */
6318 if (mono_get_jit_tls_offset () != -1) {
6320 code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6321 /* we load the value in a separate instruction: this mechanism may be
6322 * used later as a safer way to do thread interruption
6324 amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6325 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6327 x86_branch8 (code, X86_CC_Z, 0, FALSE);
6328 /* note that the call trampoline will preserve eax/edx */
6329 x86_call_reg (code, X86_ECX);
6330 x86_patch (patch, code);
6332 /* FIXME: maybe save the jit tls in the prolog */
6334 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6336 * Optimized version which uses the mono_lmf TLS variable instead of indirection
6337 * through the mono_lmf_addr TLS variable.
6339 /* reg = previous_lmf */
6340 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6341 x86_prefix (code, X86_FS_PREFIX);
6342 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6344 /* Restore previous lmf */
6345 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6346 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6347 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6350 /* Restore caller saved regs */
6351 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6352 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6354 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6355 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6357 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6358 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6360 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6361 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6363 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6364 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6366 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6367 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6370 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6371 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6373 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6374 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6379 if (cfg->arch.omit_fp) {
6380 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6382 for (i = 0; i < AMD64_NREG; ++i)
6383 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6384 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6385 save_area_offset += 8;
6389 for (i = 0; i < AMD64_NREG; ++i)
6390 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6391 pos -= sizeof (gpointer);
6394 if (pos == - sizeof (gpointer)) {
6395 /* Only one register, so avoid lea */
6396 for (i = AMD64_NREG - 1; i > 0; --i)
6397 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6398 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6402 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6404 /* Pop registers in reverse order */
6405 for (i = AMD64_NREG - 1; i > 0; --i)
6406 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6407 amd64_pop_reg (code, i);
6414 /* Load returned vtypes into registers if needed */
6415 cinfo = cfg->arch.cinfo;
6416 if (cinfo->ret.storage == ArgValuetypeInReg) {
6417 ArgInfo *ainfo = &cinfo->ret;
6418 MonoInst *inst = cfg->ret;
6420 for (quad = 0; quad < 2; quad ++) {
6421 switch (ainfo->pair_storage [quad]) {
6423 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6425 case ArgInFloatSSEReg:
6426 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6428 case ArgInDoubleSSEReg:
6429 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6434 g_assert_not_reached ();
6439 if (cfg->arch.omit_fp) {
6440 if (cfg->arch.stack_alloc_size)
6441 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6445 async_exc_point (code);
6448 cfg->code_len = code - cfg->native_code;
6450 g_assert (cfg->code_len < cfg->code_size);
6454 mono_arch_emit_exceptions (MonoCompile *cfg)
6456 MonoJumpInfo *patch_info;
6459 MonoClass *exc_classes [16];
6460 guint8 *exc_throw_start [16], *exc_throw_end [16];
6461 guint32 code_size = 0;
6463 /* Compute needed space */
6464 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6465 if (patch_info->type == MONO_PATCH_INFO_EXC)
6467 if (patch_info->type == MONO_PATCH_INFO_R8)
6468 code_size += 8 + 15; /* sizeof (double) + alignment */
6469 if (patch_info->type == MONO_PATCH_INFO_R4)
6470 code_size += 4 + 15; /* sizeof (float) + alignment */
6473 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6474 cfg->code_size *= 2;
6475 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6476 mono_jit_stats.code_reallocs++;
6479 code = cfg->native_code + cfg->code_len;
6481 /* add code to raise exceptions */
6483 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6484 switch (patch_info->type) {
6485 case MONO_PATCH_INFO_EXC: {
6486 MonoClass *exc_class;
6490 amd64_patch (patch_info->ip.i + cfg->native_code, code);
6492 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6493 g_assert (exc_class);
6494 throw_ip = patch_info->ip.i;
6496 //x86_breakpoint (code);
6497 /* Find a throw sequence for the same exception class */
6498 for (i = 0; i < nthrows; ++i)
6499 if (exc_classes [i] == exc_class)
6502 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6503 x86_jump_code (code, exc_throw_start [i]);
6504 patch_info->type = MONO_PATCH_INFO_NONE;
6508 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6512 exc_classes [nthrows] = exc_class;
6513 exc_throw_start [nthrows] = code;
6515 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6517 patch_info->type = MONO_PATCH_INFO_NONE;
6519 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6521 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6526 exc_throw_end [nthrows] = code;
6538 /* Handle relocations with RIP relative addressing */
6539 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6540 gboolean remove = FALSE;
6542 switch (patch_info->type) {
6543 case MONO_PATCH_INFO_R8:
6544 case MONO_PATCH_INFO_R4: {
6547 /* The SSE opcodes require a 16 byte alignment */
6548 code = (guint8*)ALIGN_TO (code, 16);
6550 pos = cfg->native_code + patch_info->ip.i;
6552 if (IS_REX (pos [1]))
6553 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6555 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6557 if (patch_info->type == MONO_PATCH_INFO_R8) {
6558 *(double*)code = *(double*)patch_info->data.target;
6559 code += sizeof (double);
6561 *(float*)code = *(float*)patch_info->data.target;
6562 code += sizeof (float);
6573 if (patch_info == cfg->patch_info)
6574 cfg->patch_info = patch_info->next;
6578 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6580 tmp->next = patch_info->next;
6585 cfg->code_len = code - cfg->native_code;
6587 g_assert (cfg->code_len < cfg->code_size);
6591 #endif /* DISABLE_JIT */
6594 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6597 CallInfo *cinfo = NULL;
6598 MonoMethodSignature *sig;
6600 int i, n, stack_area = 0;
6602 /* Keep this in sync with mono_arch_get_argument_info */
6604 if (enable_arguments) {
6605 /* Allocate a new area on the stack and save arguments there */
6606 sig = mono_method_signature (cfg->method);
6608 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6610 n = sig->param_count + sig->hasthis;
6612 stack_area = ALIGN_TO (n * 8, 16);
6614 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6616 for (i = 0; i < n; ++i) {
6617 inst = cfg->args [i];
6619 if (inst->opcode == OP_REGVAR)
6620 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6622 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6623 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6628 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6629 amd64_set_reg_template (code, AMD64_ARG_REG1);
6630 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6631 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6633 if (enable_arguments)
6634 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6648 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6651 int save_mode = SAVE_NONE;
6652 MonoMethod *method = cfg->method;
6653 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6655 switch (ret_type->type) {
6656 case MONO_TYPE_VOID:
6657 /* special case string .ctor icall */
6658 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6659 save_mode = SAVE_EAX;
6661 save_mode = SAVE_NONE;
6665 save_mode = SAVE_EAX;
6669 save_mode = SAVE_XMM;
6671 case MONO_TYPE_GENERICINST:
6672 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6673 save_mode = SAVE_EAX;
6677 case MONO_TYPE_VALUETYPE:
6678 save_mode = SAVE_STRUCT;
6681 save_mode = SAVE_EAX;
6685 /* Save the result and copy it into the proper argument register */
6686 switch (save_mode) {
6688 amd64_push_reg (code, AMD64_RAX);
6690 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6691 if (enable_arguments)
6692 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6696 if (enable_arguments)
6697 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6700 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6701 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6703 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6705 * The result is already in the proper argument register so no copying
6712 g_assert_not_reached ();
6715 /* Set %al since this is a varargs call */
6716 if (save_mode == SAVE_XMM)
6717 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6719 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6721 if (preserve_argument_registers) {
6722 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6723 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6726 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6727 amd64_set_reg_template (code, AMD64_ARG_REG1);
6728 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6730 if (preserve_argument_registers) {
6731 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6732 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6735 /* Restore result */
6736 switch (save_mode) {
6738 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6739 amd64_pop_reg (code, AMD64_RAX);
6745 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6746 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6747 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6752 g_assert_not_reached ();
6759 mono_arch_flush_icache (guint8 *code, gint size)
6765 mono_arch_flush_register_windows (void)
6770 mono_arch_is_inst_imm (gint64 imm)
6772 return amd64_is_imm32 (imm);
6776 * Determine whenever the trap whose info is in SIGINFO is caused by
6780 mono_arch_is_int_overflow (void *sigctx, void *info)
6787 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6789 rip = (guint8*)ctx.rip;
6791 if (IS_REX (rip [0])) {
6792 reg = amd64_rex_b (rip [0]);
6798 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6800 reg += x86_modrm_rm (rip [1]);
6840 g_assert_not_reached ();
6852 mono_arch_get_patch_offset (guint8 *code)
6858 * mono_breakpoint_clean_code:
6860 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6861 * breakpoints in the original code, they are removed in the copy.
6863 * Returns TRUE if no sw breakpoint was present.
6866 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6869 gboolean can_write = TRUE;
6871 * If method_start is non-NULL we need to perform bound checks, since we access memory
6872 * at code - offset we could go before the start of the method and end up in a different
6873 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6876 if (!method_start || code - offset >= method_start) {
6877 memcpy (buf, code - offset, size);
6879 int diff = code - method_start;
6880 memset (buf, 0, size);
6881 memcpy (buf + offset - diff, method_start, diff + size - offset);
6884 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6885 int idx = mono_breakpoint_info_index [i];
6889 ptr = mono_breakpoint_info [idx].address;
6890 if (ptr >= code && ptr < code + size) {
6891 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6893 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6894 buf [ptr - code] = saved_byte;
6901 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6907 MonoJitInfo *ji = NULL;
6910 /* code - 9 might be before the start of the method */
6911 /* FIXME: Avoid this expensive call somehow */
6912 ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6915 mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6923 * A given byte sequence can match more than case here, so we have to be
6924 * really careful about the ordering of the cases. Longer sequences
6926 * There are two types of calls:
6927 * - direct calls: 0xff address_byte 8/32 bits displacement
6928 * - indirect calls: nop nop nop <call>
6929 * The nops make sure we don't confuse the instruction preceeding an indirect
6930 * call with a direct call.
6932 if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6933 /* call OFFSET(%rip) */
6934 disp = *(guint32*)(code + 3);
6935 return (gpointer*)(code + disp + 7);
6936 } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6937 /* call *[reg+disp32] using indexed addressing */
6938 /* The LLVM JIT emits this, and we emit it too for %r12 */
6939 if (IS_REX (code [-1])) {
6941 g_assert (amd64_rex_x (rex) == 0);
6943 reg = amd64_sib_base (code [2]);
6944 disp = *(gint32*)(code + 3);
6945 } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6946 /* call *[reg+disp32] */
6947 if (IS_REX (code [0]))
6949 reg = amd64_modrm_rm (code [2]);
6950 disp = *(gint32*)(code + 3);
6951 /* R10 is clobbered by the IMT thunk code */
6952 g_assert (reg != AMD64_R10);
6953 } else if (code [2] == 0xe8) {
6956 } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6957 /* call *[r12+disp8] using indexed addressing */
6958 if (IS_REX (code [2]))
6960 reg = amd64_sib_base (code [5]);
6961 disp = *(gint8*)(code + 6);
6962 } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6965 } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6966 /* call *[reg+disp8] */
6967 if (IS_REX (code [3]))
6969 reg = amd64_modrm_rm (code [5]);
6970 disp = *(gint8*)(code + 6);
6971 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6973 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6975 if (IS_REX (code [4]))
6977 reg = amd64_modrm_rm (code [6]);
6981 g_assert_not_reached ();
6983 reg += amd64_rex_b (rex);
6985 /* R11 is clobbered by the trampoline code */
6986 g_assert (reg != AMD64_R11);
6988 *displacement = disp;
6989 return (gpointer)regs [reg];
6993 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6995 int this_reg = AMD64_ARG_REG1;
6997 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
7001 gsctx = mono_get_generic_context_from_code (code);
7003 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
7005 if (cinfo->ret.storage != ArgValuetypeInReg)
7006 this_reg = AMD64_ARG_REG2;
7014 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
7016 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
7019 #define MAX_ARCH_DELEGATE_PARAMS 10
7022 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7024 guint8 *code, *start;
7028 start = code = mono_global_codeman_reserve (64);
7030 /* Replace the this argument with the target */
7031 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7032 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7033 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7035 g_assert ((code - start) < 64);
7037 start = code = mono_global_codeman_reserve (64);
7039 if (param_count == 0) {
7040 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7042 /* We have to shift the arguments left */
7043 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7044 for (i = 0; i < param_count; ++i) {
7047 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7049 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7051 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7055 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7057 g_assert ((code - start) < 64);
7060 mono_debug_add_delegate_trampoline (start, code - start);
7063 *code_len = code - start;
7069 * mono_arch_get_delegate_invoke_impls:
7071 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7075 mono_arch_get_delegate_invoke_impls (void)
7082 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7083 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7085 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7086 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7087 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7094 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7096 guint8 *code, *start;
7099 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7102 /* FIXME: Support more cases */
7103 if (MONO_TYPE_ISSTRUCT (sig->ret))
7107 static guint8* cached = NULL;
7113 start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7115 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7117 mono_memory_barrier ();
7121 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7122 for (i = 0; i < sig->param_count; ++i)
7123 if (!mono_is_regsize_var (sig->params [i]))
7125 if (sig->param_count > 4)
7128 code = cache [sig->param_count];
7132 if (mono_aot_only) {
7133 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7134 start = mono_aot_get_named_code (name);
7137 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7140 mono_memory_barrier ();
7142 cache [sig->param_count] = start;
7149 * Support for fast access to the thread-local lmf structure using the GS
7150 * segment register on NPTL + kernel 2.6.x.
7153 static gboolean tls_offset_inited = FALSE;
7156 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7158 if (!tls_offset_inited) {
7161 * We need to init this multiple times, since when we are first called, the key might not
7162 * be initialized yet.
7164 appdomain_tls_offset = mono_domain_get_tls_key ();
7165 lmf_tls_offset = mono_get_jit_tls_key ();
7166 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7168 /* Only 64 tls entries can be accessed using inline code */
7169 if (appdomain_tls_offset >= 64)
7170 appdomain_tls_offset = -1;
7171 if (lmf_tls_offset >= 64)
7172 lmf_tls_offset = -1;
7174 tls_offset_inited = TRUE;
7176 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7178 appdomain_tls_offset = mono_domain_get_tls_offset ();
7179 lmf_tls_offset = mono_get_lmf_tls_offset ();
7180 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7186 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7190 #ifdef MONO_ARCH_HAVE_IMT
7192 #define CMP_SIZE (6 + 1)
7193 #define CMP_REG_REG_SIZE (4 + 1)
7194 #define BR_SMALL_SIZE 2
7195 #define BR_LARGE_SIZE 6
7196 #define MOV_REG_IMM_SIZE 10
7197 #define MOV_REG_IMM_32BIT_SIZE 6
7198 #define JUMP_REG_SIZE (2 + 1)
7201 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7203 int i, distance = 0;
7204 for (i = start; i < target; ++i)
7205 distance += imt_entries [i]->chunk_size;
7210 * LOCKING: called with the domain lock held
7213 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7214 gpointer fail_tramp)
7218 guint8 *code, *start;
7219 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7221 for (i = 0; i < count; ++i) {
7222 MonoIMTCheckItem *item = imt_entries [i];
7223 if (item->is_equals) {
7224 if (item->check_target_idx) {
7225 if (!item->compare_done) {
7226 if (amd64_is_imm32 (item->key))
7227 item->chunk_size += CMP_SIZE;
7229 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7231 if (item->has_target_code) {
7232 item->chunk_size += MOV_REG_IMM_SIZE;
7234 if (vtable_is_32bit)
7235 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7237 item->chunk_size += MOV_REG_IMM_SIZE;
7239 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7242 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7243 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7245 if (vtable_is_32bit)
7246 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7248 item->chunk_size += MOV_REG_IMM_SIZE;
7249 item->chunk_size += JUMP_REG_SIZE;
7250 /* with assert below:
7251 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7256 if (amd64_is_imm32 (item->key))
7257 item->chunk_size += CMP_SIZE;
7259 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7260 item->chunk_size += BR_LARGE_SIZE;
7261 imt_entries [item->check_target_idx]->compare_done = TRUE;
7263 size += item->chunk_size;
7266 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7268 code = mono_domain_code_reserve (domain, size);
7270 for (i = 0; i < count; ++i) {
7271 MonoIMTCheckItem *item = imt_entries [i];
7272 item->code_target = code;
7273 if (item->is_equals) {
7274 gboolean fail_case = !item->check_target_idx && fail_tramp;
7276 if (item->check_target_idx || fail_case) {
7277 if (!item->compare_done || fail_case) {
7278 if (amd64_is_imm32 (item->key))
7279 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7281 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7282 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7285 item->jmp_code = code;
7286 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7287 /* See the comment below about R10 */
7288 if (item->has_target_code) {
7289 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7290 amd64_jump_reg (code, AMD64_R10);
7292 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7293 amd64_jump_membase (code, AMD64_R10, 0);
7297 amd64_patch (item->jmp_code, code);
7298 amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7299 amd64_jump_reg (code, AMD64_R10);
7300 item->jmp_code = NULL;
7303 /* enable the commented code to assert on wrong method */
7305 if (amd64_is_imm32 (item->key))
7306 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7308 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7309 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7311 item->jmp_code = code;
7312 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7313 /* See the comment below about R10 */
7314 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7315 amd64_jump_membase (code, AMD64_R10, 0);
7316 amd64_patch (item->jmp_code, code);
7317 amd64_breakpoint (code);
7318 item->jmp_code = NULL;
7320 /* We're using R10 here because R11
7321 needs to be preserved. R10 needs
7322 to be preserved for calls which
7323 require a runtime generic context,
7324 but interface calls don't. */
7325 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7326 amd64_jump_membase (code, AMD64_R10, 0);
7330 if (amd64_is_imm32 (item->key))
7331 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7333 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7334 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7336 item->jmp_code = code;
7337 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7338 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7340 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7342 g_assert (code - item->code_target <= item->chunk_size);
7344 /* patch the branches to get to the target items */
7345 for (i = 0; i < count; ++i) {
7346 MonoIMTCheckItem *item = imt_entries [i];
7347 if (item->jmp_code) {
7348 if (item->check_target_idx) {
7349 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7355 mono_stats.imt_thunks_size += code - start;
7356 g_assert (code - start <= size);
7362 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7364 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7369 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7371 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7375 mono_arch_get_cie_program (void)
7379 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7380 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7386 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7388 MonoInst *ins = NULL;
7391 if (cmethod->klass == mono_defaults.math_class) {
7392 if (strcmp (cmethod->name, "Sin") == 0) {
7394 } else if (strcmp (cmethod->name, "Cos") == 0) {
7396 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7398 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7403 MONO_INST_NEW (cfg, ins, opcode);
7404 ins->type = STACK_R8;
7405 ins->dreg = mono_alloc_freg (cfg);
7406 ins->sreg1 = args [0]->dreg;
7407 MONO_ADD_INS (cfg->cbb, ins);
7411 if (cfg->opt & MONO_OPT_CMOV) {
7412 if (strcmp (cmethod->name, "Min") == 0) {
7413 if (fsig->params [0]->type == MONO_TYPE_I4)
7415 if (fsig->params [0]->type == MONO_TYPE_U4)
7416 opcode = OP_IMIN_UN;
7417 else if (fsig->params [0]->type == MONO_TYPE_I8)
7419 else if (fsig->params [0]->type == MONO_TYPE_U8)
7420 opcode = OP_LMIN_UN;
7421 } else if (strcmp (cmethod->name, "Max") == 0) {
7422 if (fsig->params [0]->type == MONO_TYPE_I4)
7424 if (fsig->params [0]->type == MONO_TYPE_U4)
7425 opcode = OP_IMAX_UN;
7426 else if (fsig->params [0]->type == MONO_TYPE_I8)
7428 else if (fsig->params [0]->type == MONO_TYPE_U8)
7429 opcode = OP_LMAX_UN;
7434 MONO_INST_NEW (cfg, ins, opcode);
7435 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7436 ins->dreg = mono_alloc_ireg (cfg);
7437 ins->sreg1 = args [0]->dreg;
7438 ins->sreg2 = args [1]->dreg;
7439 MONO_ADD_INS (cfg->cbb, ins);
7443 /* OP_FREM is not IEEE compatible */
7444 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7445 MONO_INST_NEW (cfg, ins, OP_FREM);
7446 ins->inst_i0 = args [0];
7447 ins->inst_i1 = args [1];
7453 * Can't implement CompareExchange methods this way since they have
7461 mono_arch_print_tree (MonoInst *tree, int arity)
7466 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7470 if (appdomain_tls_offset == -1)
7473 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7474 ins->inst_offset = appdomain_tls_offset;
7478 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7481 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7484 case AMD64_RCX: return (gpointer)ctx->rcx;
7485 case AMD64_RDX: return (gpointer)ctx->rdx;
7486 case AMD64_RBX: return (gpointer)ctx->rbx;
7487 case AMD64_RBP: return (gpointer)ctx->rbp;
7488 case AMD64_RSP: return (gpointer)ctx->rsp;
7491 return _CTX_REG (ctx, rax, reg);
7493 return _CTX_REG (ctx, r12, reg - 12);
7495 g_assert_not_reached ();
7499 /* Soft Debug support */
7500 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7503 * mono_arch_set_breakpoint:
7505 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7506 * The location should contain code emitted by OP_SEQ_POINT.
7509 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7512 guint8 *orig_code = code;
7515 * In production, we will use int3 (has to fix the size in the md
7516 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7519 g_assert (code [0] == 0x90);
7520 if (breakpoint_size == 8) {
7521 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7523 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7524 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7527 g_assert (code - orig_code == breakpoint_size);
7531 * mono_arch_clear_breakpoint:
7533 * Clear the breakpoint at IP.
7536 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7541 for (i = 0; i < breakpoint_size; ++i)
7546 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7549 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7552 siginfo_t* sinfo = (siginfo_t*) info;
7553 /* Sometimes the address is off by 4 */
7554 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7562 * mono_arch_get_ip_for_breakpoint:
7564 * Convert the ip in CTX to the address where a breakpoint was placed.
7567 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7569 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7571 /* ip points to the instruction causing the fault */
7572 ip -= (breakpoint_size - breakpoint_fault_size);
7578 * mono_arch_skip_breakpoint:
7580 * Modify CTX so the ip is placed after the breakpoint instruction, so when
7581 * we resume, the instruction is not executed again.
7584 mono_arch_skip_breakpoint (MonoContext *ctx)
7586 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7590 * mono_arch_start_single_stepping:
7592 * Start single stepping.
7595 mono_arch_start_single_stepping (void)
7597 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7601 * mono_arch_stop_single_stepping:
7603 * Stop single stepping.
7606 mono_arch_stop_single_stepping (void)
7608 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7612 * mono_arch_is_single_step_event:
7614 * Return whenever the machine state in SIGCTX corresponds to a single
7618 mono_arch_is_single_step_event (void *info, void *sigctx)
7621 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7624 siginfo_t* sinfo = (siginfo_t*) info;
7625 /* Sometimes the address is off by 4 */
7626 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7634 * mono_arch_get_ip_for_single_step:
7636 * Convert the ip in CTX to the address stored in seq_points.
7639 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7641 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7643 ip += single_step_fault_size;
7649 * mono_arch_skip_single_step:
7651 * Modify CTX so the ip is placed after the single step trigger instruction,
7652 * we resume, the instruction is not executed again.
7655 mono_arch_skip_single_step (MonoContext *ctx)
7657 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7661 * mono_arch_create_seq_point_info:
7663 * Return a pointer to a data structure which is used by the sequence
7664 * point implementation in AOTed code.
7667 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)