mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  67 static CRITICAL_SECTION mini_arch_mutex;
  68
  69 MonoBreakpointInfo
  70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  71
  72 /*
  73  * The code generated for sequence points reads from this location, which is
  74  * made read-only when single stepping is enabled.
  75  */
  76 static gpointer ss_trigger_page;
  77
  78 /* Enabled breakpoints read from this trigger page */
  79 static gpointer bp_trigger_page;
  80
  81 /* The size of the breakpoint sequence */
  82 static int breakpoint_size;
  83
  84 /* The size of the breakpoint instruction causing the actual fault */
  85 static int breakpoint_fault_size;
  86
  87 /* The size of the single step instruction causing the actual fault */
  88 static int single_step_fault_size;
  89
  90 #ifdef HOST_WIN32
  91 /* On Win64 always reserve first 32 bytes for first four arguments */
  92 #define ARGS_OFFSET 48
  93 #else
  94 #define ARGS_OFFSET 16
  95 #endif
  96 #define GP_SCRATCH_REG AMD64_R11
  97
  98 /*
  99  * AMD64 register usage:
 100  * - callee saved registers are used for global register allocation
 101  * - %r11 is used for materializing 64 bit constants in opcodes
 102  * - the rest is used for local allocation
 103  */
 104
 105 /*
 106  * Floating point comparison results:
 107  *                  ZF PF CF
 108  * A > B            0  0  0
 109  * A < B            0  0  1
 110  * A = B            1  0  0
 111  * A > B            0  0  0
 112  * UNORDERED        1  1  1
 113  */
 114
 115 const char*
 116 mono_arch_regname (int reg)
 117 {
 118         switch (reg) {
 119         case AMD64_RAX: return "%rax";
 120         case AMD64_RBX: return "%rbx";
 121         case AMD64_RCX: return "%rcx";
 122         case AMD64_RDX: return "%rdx";
 123         case AMD64_RSP: return "%rsp";
 124         case AMD64_RBP: return "%rbp";
 125         case AMD64_RDI: return "%rdi";
 126         case AMD64_RSI: return "%rsi";
 127         case AMD64_R8: return "%r8";
 128         case AMD64_R9: return "%r9";
 129         case AMD64_R10: return "%r10";
 130         case AMD64_R11: return "%r11";
 131         case AMD64_R12: return "%r12";
 132         case AMD64_R13: return "%r13";
 133         case AMD64_R14: return "%r14";
 134         case AMD64_R15: return "%r15";
 135         }
 136         return "unknown";
 137 }
 138
 139 static const char * packed_xmmregs [] = {
 140         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 141         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 142 };
 143
 144 static const char * single_xmmregs [] = {
 145         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 146         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 147 };
 148
 149 const char*
 150 mono_arch_fregname (int reg)
 151 {
 152         if (reg < AMD64_XMM_NREG)
 153                 return single_xmmregs [reg];
 154         else
 155                 return "unknown";
 156 }
 157
 158 const char *
 159 mono_arch_xregname (int reg)
 160 {
 161         if (reg < AMD64_XMM_NREG)
 162                 return packed_xmmregs [reg];
 163         else
 164                 return "unknown";
 165 }
 166
 167 G_GNUC_UNUSED static void
 168 break_count (void)
 169 {
 170 }
 171
 172 G_GNUC_UNUSED static gboolean
 173 debug_count (void)
 174 {
 175         static int count = 0;
 176         count ++;
 177
 178         if (!getenv ("COUNT"))
 179                 return TRUE;
 180
 181         if (count == atoi (getenv ("COUNT"))) {
 182                 break_count ();
 183         }
 184
 185         if (count > atoi (getenv ("COUNT"))) {
 186                 return FALSE;
 187         }
 188
 189         return TRUE;
 190 }
 191
 192 static gboolean
 193 debug_omit_fp (void)
 194 {
 195 #if 0
 196         return debug_count ();
 197 #else
 198         return TRUE;
 199 #endif
 200 }
 201
 202 static inline gboolean
 203 amd64_is_near_call (guint8 *code)
 204 {
 205         /* Skip REX */
 206         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 207                 code += 1;
 208
 209         return code [0] == 0xe8;
 210 }
 211
 212 static inline void
 213 amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         guint8 rex = 0;
 216
 217         /* Skip REX */
 218         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 219                 rex = code [0];
 220                 code += 1;
 221         }
 222
 223         if ((code [0] & 0xf8) == 0xb8) {
 224                 /* amd64_set_reg_template */
 225                 *(guint64*)(code + 1) = (guint64)target;
 226         }
 227         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 228                 /* mov 0(%rip), %dreg */
 229                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 230         }
 231         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 232                 /* call *<OFFSET>(%rip) */
 233                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 234         }
 235         else if ((code [0] == 0xe8)) {
 236                 /* call <DISP> */
 237                 gint64 disp = (guint8*)target - (guint8*)code;
 238                 g_assert (amd64_is_imm32 (disp));
 239                 x86_patch (code, (unsigned char*)target);
 240         }
 241         else
 242                 x86_patch (code, (unsigned char*)target);
 243 }
 244
 245 void
 246 mono_amd64_patch (unsigned char* code, gpointer target)
 247 {
 248         amd64_patch (code, target);
 249 }
 250
 251 typedef enum {
 252         ArgInIReg,
 253         ArgInFloatSSEReg,
 254         ArgInDoubleSSEReg,
 255         ArgOnStack,
 256         ArgValuetypeInReg,
 257         ArgValuetypeAddrInIReg,
 258         ArgNone /* only in pair_storage */
 259 } ArgStorage;
 260
 261 typedef struct {
 262         gint16 offset;
 263         gint8  reg;
 264         ArgStorage storage;
 265
 266         /* Only if storage == ArgValuetypeInReg */
 267         ArgStorage pair_storage [2];
 268         gint8 pair_regs [2];
 269 } ArgInfo;
 270
 271 typedef struct {
 272         int nargs;
 273         guint32 stack_usage;
 274         guint32 reg_usage;
 275         guint32 freg_usage;
 276         gboolean need_stack_align;
 277         gboolean vtype_retaddr;
 278         ArgInfo ret;
 279         ArgInfo sig_cookie;
 280         ArgInfo args [1];
 281 } CallInfo;
 282
 283 #define DEBUG(a) if (cfg->verbose_level > 1) a
 284
 285 #ifdef HOST_WIN32
 286 #define PARAM_REGS 4
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 289
 290 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #else
 292 #define PARAM_REGS 6
 293
 294 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 295
 296  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 297 #endif
 298
 299 static void inline
 300 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 301 {
 302     ainfo->offset = *stack_size;
 303
 304     if (*gr >= PARAM_REGS) {
 305                 ainfo->storage = ArgOnStack;
 306                 (*stack_size) += sizeof (gpointer);
 307     }
 308     else {
 309                 ainfo->storage = ArgInIReg;
 310                 ainfo->reg = param_regs [*gr];
 311                 (*gr) ++;
 312     }
 313 }
 314
 315 #ifdef HOST_WIN32
 316 #define FLOAT_PARAM_REGS 4
 317 #else
 318 #define FLOAT_PARAM_REGS 8
 319 #endif
 320
 321 static void inline
 322 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 323 {
 324     ainfo->offset = *stack_size;
 325
 326     if (*gr >= FLOAT_PARAM_REGS) {
 327                 ainfo->storage = ArgOnStack;
 328                 (*stack_size) += sizeof (gpointer);
 329     }
 330     else {
 331                 /* A double register */
 332                 if (is_double)
 333                         ainfo->storage = ArgInDoubleSSEReg;
 334                 else
 335                         ainfo->storage = ArgInFloatSSEReg;
 336                 ainfo->reg = *gr;
 337                 (*gr) += 1;
 338     }
 339 }
 340
 341 typedef enum ArgumentClass {
 342         ARG_CLASS_NO_CLASS,
 343         ARG_CLASS_MEMORY,
 344         ARG_CLASS_INTEGER,
 345         ARG_CLASS_SSE
 346 } ArgumentClass;
 347
 348 static ArgumentClass
 349 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 350 {
 351         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 352         MonoType *ptype;
 353
 354         ptype = mini_type_get_underlying_type (NULL, type);
 355         switch (ptype->type) {
 356         case MONO_TYPE_BOOLEAN:
 357         case MONO_TYPE_CHAR:
 358         case MONO_TYPE_I1:
 359         case MONO_TYPE_U1:
 360         case MONO_TYPE_I2:
 361         case MONO_TYPE_U2:
 362         case MONO_TYPE_I4:
 363         case MONO_TYPE_U4:
 364         case MONO_TYPE_I:
 365         case MONO_TYPE_U:
 366         case MONO_TYPE_STRING:
 367         case MONO_TYPE_OBJECT:
 368         case MONO_TYPE_CLASS:
 369         case MONO_TYPE_SZARRAY:
 370         case MONO_TYPE_PTR:
 371         case MONO_TYPE_FNPTR:
 372         case MONO_TYPE_ARRAY:
 373         case MONO_TYPE_I8:
 374         case MONO_TYPE_U8:
 375                 class2 = ARG_CLASS_INTEGER;
 376                 break;
 377         case MONO_TYPE_R4:
 378         case MONO_TYPE_R8:
 379 #ifdef HOST_WIN32
 380                 class2 = ARG_CLASS_INTEGER;
 381 #else
 382                 class2 = ARG_CLASS_SSE;
 383 #endif
 384                 break;
 385
 386         case MONO_TYPE_TYPEDBYREF:
 387                 g_assert_not_reached ();
 388
 389         case MONO_TYPE_GENERICINST:
 390                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 391                         class2 = ARG_CLASS_INTEGER;
 392                         break;
 393                 }
 394                 /* fall through */
 395         case MONO_TYPE_VALUETYPE: {
 396                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 397                 int i;
 398
 399                 for (i = 0; i < info->num_fields; ++i) {
 400                         class2 = class1;
 401                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 402                 }
 403                 break;
 404         }
 405         default:
 406                 g_assert_not_reached ();
 407         }
 408
 409         /* Merge */
 410         if (class1 == class2)
 411                 ;
 412         else if (class1 == ARG_CLASS_NO_CLASS)
 413                 class1 = class2;
 414         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 415                 class1 = ARG_CLASS_MEMORY;
 416         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 417                 class1 = ARG_CLASS_INTEGER;
 418         else
 419                 class1 = ARG_CLASS_SSE;
 420
 421         return class1;
 422 }
 423
 424 static void
 425 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 426                            gboolean is_return,
 427                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 428 {
 429         guint32 size, quad, nquads, i;
 430         ArgumentClass args [2];
 431         MonoMarshalType *info = NULL;
 432         MonoClass *klass;
 433         MonoGenericSharingContext tmp_gsctx;
 434         gboolean pass_on_stack = FALSE;
 435
 436         /*
 437          * The gsctx currently contains no data, it is only used for checking whenever
 438          * open types are allowed, some callers like mono_arch_get_argument_info ()
 439          * don't pass it to us, so work around that.
 440          */
 441         if (!gsctx)
 442                 gsctx = &tmp_gsctx;
 443
 444         klass = mono_class_from_mono_type (type);
 445         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 446 #ifndef HOST_WIN32
 447         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 448                 /* We pass and return vtypes of size 8 in a register */
 449         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 450                 pass_on_stack = TRUE;
 451         }
 452 #else
 453         if (!sig->pinvoke) {
 454                 pass_on_stack = TRUE;
 455         }
 456 #endif
 457
 458         if (pass_on_stack) {
 459                 /* Allways pass in memory */
 460                 ainfo->offset = *stack_size;
 461                 *stack_size += ALIGN_TO (size, 8);
 462                 ainfo->storage = ArgOnStack;
 463
 464                 return;
 465         }
 466
 467         /* FIXME: Handle structs smaller than 8 bytes */
 468         //if ((size % 8) != 0)
 469         //      NOT_IMPLEMENTED;
 470
 471         if (size > 8)
 472                 nquads = 2;
 473         else
 474                 nquads = 1;
 475
 476         if (!sig->pinvoke) {
 477                 /* Always pass in 1 or 2 integer registers */
 478                 args [0] = ARG_CLASS_INTEGER;
 479                 args [1] = ARG_CLASS_INTEGER;
 480                 /* Only the simplest cases are supported */
 481                 if (is_return && nquads != 1) {
 482                         args [0] = ARG_CLASS_MEMORY;
 483                         args [1] = ARG_CLASS_MEMORY;
 484                 }
 485         } else {
 486                 /*
 487                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 488                  * The X87 and SSEUP stuff is left out since there are no such types in
 489                  * the CLR.
 490                  */
 491                 info = mono_marshal_load_type_info (klass);
 492                 g_assert (info);
 493
 494 #ifndef HOST_WIN32
 495                 if (info->native_size > 16) {
 496                         ainfo->offset = *stack_size;
 497                         *stack_size += ALIGN_TO (info->native_size, 8);
 498                         ainfo->storage = ArgOnStack;
 499
 500                         return;
 501                 }
 502 #else
 503                 switch (info->native_size) {
 504                 case 1: case 2: case 4: case 8:
 505                         break;
 506                 default:
 507                         if (is_return) {
 508                                 ainfo->storage = ArgOnStack;
 509                                 ainfo->offset = *stack_size;
 510                                 *stack_size += ALIGN_TO (info->native_size, 8);
 511                         }
 512                         else {
 513                                 ainfo->storage = ArgValuetypeAddrInIReg;
 514
 515                                 if (*gr < PARAM_REGS) {
 516                                         ainfo->pair_storage [0] = ArgInIReg;
 517                                         ainfo->pair_regs [0] = param_regs [*gr];
 518                                         (*gr) ++;
 519                                 }
 520                                 else {
 521                                         ainfo->pair_storage [0] = ArgOnStack;
 522                                         ainfo->offset = *stack_size;
 523                                         *stack_size += 8;
 524                                 }
 525                         }
 526
 527                         return;
 528                 }
 529 #endif
 530
 531                 args [0] = ARG_CLASS_NO_CLASS;
 532                 args [1] = ARG_CLASS_NO_CLASS;
 533                 for (quad = 0; quad < nquads; ++quad) {
 534                         int size;
 535                         guint32 align;
 536                         ArgumentClass class1;
 537
 538                         if (info->num_fields == 0)
 539                                 class1 = ARG_CLASS_MEMORY;
 540                         else
 541                                 class1 = ARG_CLASS_NO_CLASS;
 542                         for (i = 0; i < info->num_fields; ++i) {
 543                                 size = mono_marshal_type_size (info->fields [i].field->type,
 544                                                                                            info->fields [i].mspec,
 545                                                                                            &align, TRUE, klass->unicode);
 546                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 547                                         /* Unaligned field */
 548                                         NOT_IMPLEMENTED;
 549                                 }
 550
 551                                 /* Skip fields in other quad */
 552                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 553                                         continue;
 554                                 if ((quad == 1) && (info->fields [i].offset < 8))
 555                                         continue;
 556
 557                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 558                         }
 559                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 560                         args [quad] = class1;
 561                 }
 562         }
 563
 564         /* Post merger cleanup */
 565         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 566                 args [0] = args [1] = ARG_CLASS_MEMORY;
 567
 568         /* Allocate registers */
 569         {
 570                 int orig_gr = *gr;
 571                 int orig_fr = *fr;
 572
 573                 ainfo->storage = ArgValuetypeInReg;
 574                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 575                 for (quad = 0; quad < nquads; ++quad) {
 576                         switch (args [quad]) {
 577                         case ARG_CLASS_INTEGER:
 578                                 if (*gr >= PARAM_REGS)
 579                                         args [quad] = ARG_CLASS_MEMORY;
 580                                 else {
 581                                         ainfo->pair_storage [quad] = ArgInIReg;
 582                                         if (is_return)
 583                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 584                                         else
 585                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 586                                         (*gr) ++;
 587                                 }
 588                                 break;
 589                         case ARG_CLASS_SSE:
 590                                 if (*fr >= FLOAT_PARAM_REGS)
 591                                         args [quad] = ARG_CLASS_MEMORY;
 592                                 else {
 593                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 594                                         ainfo->pair_regs [quad] = *fr;
 595                                         (*fr) ++;
 596                                 }
 597                                 break;
 598                         case ARG_CLASS_MEMORY:
 599                                 break;
 600                         default:
 601                                 g_assert_not_reached ();
 602                         }
 603                 }
 604
 605                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 606                         /* Revert possible register assignments */
 607                         *gr = orig_gr;
 608                         *fr = orig_fr;
 609
 610                         ainfo->offset = *stack_size;
 611                         if (sig->pinvoke)
 612                                 *stack_size += ALIGN_TO (info->native_size, 8);
 613                         else
 614                                 *stack_size += nquads * sizeof (gpointer);
 615                         ainfo->storage = ArgOnStack;
 616                 }
 617         }
 618 }
 619
 620 /*
 621  * get_call_info:
 622  *
 623  *  Obtain information about a call according to the calling convention.
 624  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 625  * Draft Version 0.23" document for more information.
 626  */
 627 static CallInfo*
 628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 629 {
 630         guint32 i, gr, fr;
 631         MonoType *ret_type;
 632         int n = sig->hasthis + sig->param_count;
 633         guint32 stack_size = 0;
 634         CallInfo *cinfo;
 635
 636         if (mp)
 637                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 638         else
 639                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 640
 641         cinfo->nargs = n;
 642
 643         gr = 0;
 644         fr = 0;
 645
 646         /* return value */
 647         {
 648                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 649                 switch (ret_type->type) {
 650                 case MONO_TYPE_BOOLEAN:
 651                 case MONO_TYPE_I1:
 652                 case MONO_TYPE_U1:
 653                 case MONO_TYPE_I2:
 654                 case MONO_TYPE_U2:
 655                 case MONO_TYPE_CHAR:
 656                 case MONO_TYPE_I4:
 657                 case MONO_TYPE_U4:
 658                 case MONO_TYPE_I:
 659                 case MONO_TYPE_U:
 660                 case MONO_TYPE_PTR:
 661                 case MONO_TYPE_FNPTR:
 662                 case MONO_TYPE_CLASS:
 663                 case MONO_TYPE_OBJECT:
 664                 case MONO_TYPE_SZARRAY:
 665                 case MONO_TYPE_ARRAY:
 666                 case MONO_TYPE_STRING:
 667                         cinfo->ret.storage = ArgInIReg;
 668                         cinfo->ret.reg = AMD64_RAX;
 669                         break;
 670                 case MONO_TYPE_U8:
 671                 case MONO_TYPE_I8:
 672                         cinfo->ret.storage = ArgInIReg;
 673                         cinfo->ret.reg = AMD64_RAX;
 674                         break;
 675                 case MONO_TYPE_R4:
 676                         cinfo->ret.storage = ArgInFloatSSEReg;
 677                         cinfo->ret.reg = AMD64_XMM0;
 678                         break;
 679                 case MONO_TYPE_R8:
 680                         cinfo->ret.storage = ArgInDoubleSSEReg;
 681                         cinfo->ret.reg = AMD64_XMM0;
 682                         break;
 683                 case MONO_TYPE_GENERICINST:
 684                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 685                                 cinfo->ret.storage = ArgInIReg;
 686                                 cinfo->ret.reg = AMD64_RAX;
 687                                 break;
 688                         }
 689                         /* fall through */
 690                 case MONO_TYPE_VALUETYPE: {
 691                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 692
 693                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 694                         if (cinfo->ret.storage == ArgOnStack) {
 695                                 cinfo->vtype_retaddr = TRUE;
 696                                 /* The caller passes the address where the value is stored */
 697                                 add_general (&gr, &stack_size, &cinfo->ret);
 698                         }
 699                         break;
 700                 }
 701                 case MONO_TYPE_TYPEDBYREF:
 702                         /* Same as a valuetype with size 24 */
 703                         add_general (&gr, &stack_size, &cinfo->ret);
 704                         ;
 705                         break;
 706                 case MONO_TYPE_VOID:
 707                         break;
 708                 default:
 709                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 710                 }
 711         }
 712
 713         /* this */
 714         if (sig->hasthis)
 715                 add_general (&gr, &stack_size, cinfo->args + 0);
 716
 717         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 718                 gr = PARAM_REGS;
 719                 fr = FLOAT_PARAM_REGS;
 720
 721                 /* Emit the signature cookie just before the implicit arguments */
 722                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 723         }
 724
 725         for (i = 0; i < sig->param_count; ++i) {
 726                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 727                 MonoType *ptype;
 728
 729 #ifdef HOST_WIN32
 730                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 731                 if (gr > fr)
 732                         fr = gr;
 733                 else if (fr > gr)
 734                         gr = fr;
 735 #endif
 736
 737                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 738                         /* We allways pass the sig cookie on the stack for simplicity */
 739                         /*
 740                          * Prevent implicit arguments + the sig cookie from being passed
 741                          * in registers.
 742                          */
 743                         gr = PARAM_REGS;
 744                         fr = FLOAT_PARAM_REGS;
 745
 746                         /* Emit the signature cookie just before the implicit arguments */
 747                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 748                 }
 749
 750                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 751                 switch (ptype->type) {
 752                 case MONO_TYPE_BOOLEAN:
 753                 case MONO_TYPE_I1:
 754                 case MONO_TYPE_U1:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_I2:
 758                 case MONO_TYPE_U2:
 759                 case MONO_TYPE_CHAR:
 760                         add_general (&gr, &stack_size, ainfo);
 761                         break;
 762                 case MONO_TYPE_I4:
 763                 case MONO_TYPE_U4:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_I:
 767                 case MONO_TYPE_U:
 768                 case MONO_TYPE_PTR:
 769                 case MONO_TYPE_FNPTR:
 770                 case MONO_TYPE_CLASS:
 771                 case MONO_TYPE_OBJECT:
 772                 case MONO_TYPE_STRING:
 773                 case MONO_TYPE_SZARRAY:
 774                 case MONO_TYPE_ARRAY:
 775                         add_general (&gr, &stack_size, ainfo);
 776                         break;
 777                 case MONO_TYPE_GENERICINST:
 778                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 779                                 add_general (&gr, &stack_size, ainfo);
 780                                 break;
 781                         }
 782                         /* fall through */
 783                 case MONO_TYPE_VALUETYPE:
 784                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 785                         break;
 786                 case MONO_TYPE_TYPEDBYREF:
 787 #ifdef HOST_WIN32
 788                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 789 #else
 790                         stack_size += sizeof (MonoTypedRef);
 791                         ainfo->storage = ArgOnStack;
 792 #endif
 793                         break;
 794                 case MONO_TYPE_U8:
 795                 case MONO_TYPE_I8:
 796                         add_general (&gr, &stack_size, ainfo);
 797                         break;
 798                 case MONO_TYPE_R4:
 799                         add_float (&fr, &stack_size, ainfo, FALSE);
 800                         break;
 801                 case MONO_TYPE_R8:
 802                         add_float (&fr, &stack_size, ainfo, TRUE);
 803                         break;
 804                 default:
 805                         g_assert_not_reached ();
 806                 }
 807         }
 808
 809         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 810                 gr = PARAM_REGS;
 811                 fr = FLOAT_PARAM_REGS;
 812
 813                 /* Emit the signature cookie just before the implicit arguments */
 814                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 815         }
 816
 817 #ifdef HOST_WIN32
 818         // There always is 32 bytes reserved on the stack when calling on Winx64
 819         stack_size += 0x20;
 820 #endif
 821
 822         if (stack_size & 0x8) {
 823                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 824                 cinfo->need_stack_align = TRUE;
 825                 stack_size += 8;
 826         }
 827
 828         cinfo->stack_usage = stack_size;
 829         cinfo->reg_usage = gr;
 830         cinfo->freg_usage = fr;
 831         return cinfo;
 832 }
 833
 834 /*
 835  * mono_arch_get_argument_info:
 836  * @csig:  a method signature
 837  * @param_count: the number of parameters to consider
 838  * @arg_info: an array to store the result infos
 839  *
 840  * Gathers information on parameters such as size, alignment and
 841  * padding. arg_info should be large enought to hold param_count + 1 entries.
 842  *
 843  * Returns the size of the argument area on the stack.
 844  */
 845 int
 846 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 847 {
 848         int k;
 849         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 850         guint32 args_size = cinfo->stack_usage;
 851
 852         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 853         if (csig->hasthis) {
 854                 arg_info [0].offset = 0;
 855         }
 856
 857         for (k = 0; k < param_count; k++) {
 858                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 859                 /* FIXME: */
 860                 arg_info [k + 1].size = 0;
 861         }
 862
 863         g_free (cinfo);
 864
 865         return args_size;
 866 }
 867
 868 static int
 869 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 870 {
 871 #ifndef _MSC_VER
 872         __asm__ __volatile__ ("cpuid"
 873                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 874                 : "a" (id));
 875 #else
 876         int info[4];
 877         __cpuid(info, id);
 878         *p_eax = info[0];
 879         *p_ebx = info[1];
 880         *p_ecx = info[2];
 881         *p_edx = info[3];
 882 #endif
 883         return 1;
 884 }
 885
 886 /*
 887  * Initialize the cpu to execute managed code.
 888  */
 889 void
 890 mono_arch_cpu_init (void)
 891 {
 892 #ifndef _MSC_VER
 893         guint16 fpcw;
 894
 895         /* spec compliance requires running with double precision */
 896         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 897         fpcw &= ~X86_FPCW_PRECC_MASK;
 898         fpcw |= X86_FPCW_PREC_DOUBLE;
 899         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 900         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 901 #else
 902         /* TODO: This is crashing on Win64 right now.
 903         * _control87 (_PC_53, MCW_PC);
 904         */
 905 #endif
 906 }
 907
 908 /*
 909  * Initialize architecture specific code.
 910  */
 911 void
 912 mono_arch_init (void)
 913 {
 914         int flags;
 915
 916         InitializeCriticalSection (&mini_arch_mutex);
 917
 918 #ifdef MONO_ARCH_NOMAP32BIT
 919         flags = MONO_MMAP_READ;
 920         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 921         breakpoint_size = 13;
 922         breakpoint_fault_size = 3;
 923         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 924         single_step_fault_size = 5;
 925 #else
 926         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 927         /* amd64_mov_reg_mem () */
 928         breakpoint_size = 8;
 929         breakpoint_fault_size = 8;
 930         single_step_fault_size = 8;
 931 #endif
 932
 933         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 934         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 935         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 936 }
 937
 938 /*
 939  * Cleanup architecture specific code.
 940  */
 941 void
 942 mono_arch_cleanup (void)
 943 {
 944         DeleteCriticalSection (&mini_arch_mutex);
 945 }
 946
 947 /*
 948  * This function returns the optimizations supported on this cpu.
 949  */
 950 guint32
 951 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 952 {
 953         int eax, ebx, ecx, edx;
 954         guint32 opts = 0;
 955
 956         /* FIXME: AMD64 */
 957
 958         *exclude_mask = 0;
 959         /* Feature Flags function, flags returned in EDX. */
 960         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 961                 if (edx & (1 << 15)) {
 962                         opts |= MONO_OPT_CMOV;
 963                         if (edx & 1)
 964                                 opts |= MONO_OPT_FCMOV;
 965                         else
 966                                 *exclude_mask |= MONO_OPT_FCMOV;
 967                 } else
 968                         *exclude_mask |= MONO_OPT_CMOV;
 969         }
 970
 971         return opts;
 972 }
 973
 974 /*
 975  * This function test for all SSE functions supported.
 976  *
 977  * Returns a bitmask corresponding to all supported versions.
 978  *
 979  */
 980 guint32
 981 mono_arch_cpu_enumerate_simd_versions (void)
 982 {
 983         int eax, ebx, ecx, edx;
 984         guint32 sse_opts = 0;
 985
 986         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 987                 if (edx & (1 << 25))
 988                         sse_opts |= SIMD_VERSION_SSE1;
 989                 if (edx & (1 << 26))
 990                         sse_opts |= SIMD_VERSION_SSE2;
 991                 if (ecx & (1 << 0))
 992                         sse_opts |= SIMD_VERSION_SSE3;
 993                 if (ecx & (1 << 9))
 994                         sse_opts |= SIMD_VERSION_SSSE3;
 995                 if (ecx & (1 << 19))
 996                         sse_opts |= SIMD_VERSION_SSE41;
 997                 if (ecx & (1 << 20))
 998                         sse_opts |= SIMD_VERSION_SSE42;
 999         }
1000
1001         /* Yes, all this needs to be done to check for sse4a.
1002            See: "Amd: CPUID Specification"
1003          */
1004         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1005                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1006                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1007                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1008                         if (ecx & (1 << 6))
1009                                 sse_opts |= SIMD_VERSION_SSE4a;
1010                 }
1011         }
1012
1013         return sse_opts;
1014 }
1015
1016 #ifndef DISABLE_JIT
1017
1018 GList *
1019 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1020 {
1021         GList *vars = NULL;
1022         int i;
1023
1024         for (i = 0; i < cfg->num_varinfo; i++) {
1025                 MonoInst *ins = cfg->varinfo [i];
1026                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1027
1028                 /* unused vars */
1029                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1030                         continue;
1031
1032                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1033                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1034                         continue;
1035
1036                 if (mono_is_regsize_var (ins->inst_vtype)) {
1037                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1038                         g_assert (i == vmv->idx);
1039                         vars = g_list_prepend (vars, vmv);
1040                 }
1041         }
1042
1043         vars = mono_varlist_sort (cfg, vars, 0);
1044
1045         return vars;
1046 }
1047
1048 /**
1049  * mono_arch_compute_omit_fp:
1050  *
1051  *   Determine whenever the frame pointer can be eliminated.
1052  */
1053 static void
1054 mono_arch_compute_omit_fp (MonoCompile *cfg)
1055 {
1056         MonoMethodSignature *sig;
1057         MonoMethodHeader *header;
1058         int i, locals_size;
1059         CallInfo *cinfo;
1060
1061         if (cfg->arch.omit_fp_computed)
1062                 return;
1063
1064         header = cfg->header;
1065
1066         sig = mono_method_signature (cfg->method);
1067
1068         if (!cfg->arch.cinfo)
1069                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1070         cinfo = cfg->arch.cinfo;
1071
1072         /*
1073          * FIXME: Remove some of the restrictions.
1074          */
1075         cfg->arch.omit_fp = TRUE;
1076         cfg->arch.omit_fp_computed = TRUE;
1077
1078         if (cfg->disable_omit_fp)
1079                 cfg->arch.omit_fp = FALSE;
1080
1081         if (!debug_omit_fp ())
1082                 cfg->arch.omit_fp = FALSE;
1083         /*
1084         if (cfg->method->save_lmf)
1085                 cfg->arch.omit_fp = FALSE;
1086         */
1087         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1088                 cfg->arch.omit_fp = FALSE;
1089         if (header->num_clauses)
1090                 cfg->arch.omit_fp = FALSE;
1091         if (cfg->param_area)
1092                 cfg->arch.omit_fp = FALSE;
1093         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1094                 cfg->arch.omit_fp = FALSE;
1095         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1096                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1097                 cfg->arch.omit_fp = FALSE;
1098         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1099                 ArgInfo *ainfo = &cinfo->args [i];
1100
1101                 if (ainfo->storage == ArgOnStack) {
1102                         /*
1103                          * The stack offset can only be determined when the frame
1104                          * size is known.
1105                          */
1106                         cfg->arch.omit_fp = FALSE;
1107                 }
1108         }
1109
1110         locals_size = 0;
1111         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1112                 MonoInst *ins = cfg->varinfo [i];
1113                 int ialign;
1114
1115                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1116         }
1117 }
1118
1119 GList *
1120 mono_arch_get_global_int_regs (MonoCompile *cfg)
1121 {
1122         GList *regs = NULL;
1123
1124         mono_arch_compute_omit_fp (cfg);
1125
1126         if (cfg->globalra) {
1127                 if (cfg->arch.omit_fp)
1128                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1129
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1133                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1135
1136                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1137                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1138                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1139                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1140                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1141                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1142                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1143                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1144         } else {
1145                 if (cfg->arch.omit_fp)
1146                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1147
1148                 /* We use the callee saved registers for global allocation */
1149                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1150                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1151                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1152                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1153                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1154 #ifdef HOST_WIN32
1155                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1156                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1157 #endif
1158         }
1159
1160         return regs;
1161 }
1162
1163 GList*
1164 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1165 {
1166         GList *regs = NULL;
1167         int i;
1168
1169         /* All XMM registers */
1170         for (i = 0; i < 16; ++i)
1171                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1172
1173         return regs;
1174 }
1175
1176 GList*
1177 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1178 {
1179         static GList *r = NULL;
1180
1181         if (r == NULL) {
1182                 GList *regs = NULL;
1183
1184                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1185                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1186                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1187                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1188                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1189                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1190
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1192                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1193                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1194                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1195                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1196                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1197                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1198                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1199
1200                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1201         }
1202
1203         return r;
1204 }
1205
1206 GList*
1207 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1208 {
1209         int i;
1210         static GList *r = NULL;
1211
1212         if (r == NULL) {
1213                 GList *regs = NULL;
1214
1215                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1216                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1217
1218                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1219         }
1220
1221         return r;
1222 }
1223
1224 /*
1225  * mono_arch_regalloc_cost:
1226  *
1227  *  Return the cost, in number of memory references, of the action of
1228  * allocating the variable VMV into a register during global register
1229  * allocation.
1230  */
1231 guint32
1232 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1233 {
1234         MonoInst *ins = cfg->varinfo [vmv->idx];
1235
1236         if (cfg->method->save_lmf)
1237                 /* The register is already saved */
1238                 /* substract 1 for the invisible store in the prolog */
1239                 return (ins->opcode == OP_ARG) ? 0 : 1;
1240         else
1241                 /* push+pop */
1242                 return (ins->opcode == OP_ARG) ? 1 : 2;
1243 }
1244
1245 /*
1246  * mono_arch_fill_argument_info:
1247  *
1248  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1249  * of the method.
1250  */
1251 void
1252 mono_arch_fill_argument_info (MonoCompile *cfg)
1253 {
1254         MonoMethodSignature *sig;
1255         MonoMethodHeader *header;
1256         MonoInst *ins;
1257         int i;
1258         CallInfo *cinfo;
1259
1260         header = cfg->header;
1261
1262         sig = mono_method_signature (cfg->method);
1263
1264         cinfo = cfg->arch.cinfo;
1265
1266         /*
1267          * Contrary to mono_arch_allocate_vars (), the information should describe
1268          * where the arguments are at the beginning of the method, not where they can be
1269          * accessed during the execution of the method. The later makes no sense for the
1270          * global register allocator, since a variable can be in more than one location.
1271          */
1272         if (sig->ret->type != MONO_TYPE_VOID) {
1273                 switch (cinfo->ret.storage) {
1274                 case ArgInIReg:
1275                 case ArgInFloatSSEReg:
1276                 case ArgInDoubleSSEReg:
1277                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1278                                 cfg->vret_addr->opcode = OP_REGVAR;
1279                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1280                         }
1281                         else {
1282                                 cfg->ret->opcode = OP_REGVAR;
1283                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1284                         }
1285                         break;
1286                 case ArgValuetypeInReg:
1287                         cfg->ret->opcode = OP_REGOFFSET;
1288                         cfg->ret->inst_basereg = -1;
1289                         cfg->ret->inst_offset = -1;
1290                         break;
1291                 default:
1292                         g_assert_not_reached ();
1293                 }
1294         }
1295
1296         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1297                 ArgInfo *ainfo = &cinfo->args [i];
1298                 MonoType *arg_type;
1299
1300                 ins = cfg->args [i];
1301
1302                 if (sig->hasthis && (i == 0))
1303                         arg_type = &mono_defaults.object_class->byval_arg;
1304                 else
1305                         arg_type = sig->params [i - sig->hasthis];
1306
1307                 switch (ainfo->storage) {
1308                 case ArgInIReg:
1309                 case ArgInFloatSSEReg:
1310                 case ArgInDoubleSSEReg:
1311                         ins->opcode = OP_REGVAR;
1312                         ins->inst_c0 = ainfo->reg;
1313                         break;
1314                 case ArgOnStack:
1315                         ins->opcode = OP_REGOFFSET;
1316                         ins->inst_basereg = -1;
1317                         ins->inst_offset = -1;
1318                         break;
1319                 case ArgValuetypeInReg:
1320                         /* Dummy */
1321                         ins->opcode = OP_NOP;
1322                         break;
1323                 default:
1324                         g_assert_not_reached ();
1325                 }
1326         }
1327 }
1328
1329 void
1330 mono_arch_allocate_vars (MonoCompile *cfg)
1331 {
1332         MonoMethodSignature *sig;
1333         MonoMethodHeader *header;
1334         MonoInst *ins;
1335         int i, offset;
1336         guint32 locals_stack_size, locals_stack_align;
1337         gint32 *offsets;
1338         CallInfo *cinfo;
1339
1340         header = cfg->header;
1341
1342         sig = mono_method_signature (cfg->method);
1343
1344         cinfo = cfg->arch.cinfo;
1345
1346         mono_arch_compute_omit_fp (cfg);
1347
1348         /*
1349          * We use the ABI calling conventions for managed code as well.
1350          * Exception: valuetypes are only sometimes passed or returned in registers.
1351          */
1352
1353         /*
1354          * The stack looks like this:
1355          * <incoming arguments passed on the stack>
1356          * <return value>
1357          * <lmf/caller saved registers>
1358          * <locals>
1359          * <spill area>
1360          * <localloc area>  -> grows dynamically
1361          * <params area>
1362          */
1363
1364         if (cfg->arch.omit_fp) {
1365                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1366                 cfg->frame_reg = AMD64_RSP;
1367                 offset = 0;
1368         } else {
1369                 /* Locals are allocated backwards from %fp */
1370                 cfg->frame_reg = AMD64_RBP;
1371                 offset = 0;
1372         }
1373
1374         if (cfg->method->save_lmf) {
1375                 /* Reserve stack space for saving LMF */
1376                 if (cfg->arch.omit_fp) {
1377                         cfg->arch.lmf_offset = offset;
1378                         offset += sizeof (MonoLMF);
1379                 }
1380                 else {
1381                         offset += sizeof (MonoLMF);
1382                         cfg->arch.lmf_offset = -offset;
1383                 }
1384         } else {
1385                 if (cfg->arch.omit_fp)
1386                         cfg->arch.reg_save_area_offset = offset;
1387                 /* Reserve space for caller saved registers */
1388                 for (i = 0; i < AMD64_NREG; ++i)
1389                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1390                                 offset += sizeof (gpointer);
1391                         }
1392         }
1393
1394         if (sig->ret->type != MONO_TYPE_VOID) {
1395                 switch (cinfo->ret.storage) {
1396                 case ArgInIReg:
1397                 case ArgInFloatSSEReg:
1398                 case ArgInDoubleSSEReg:
1399                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1400                                 if (cfg->globalra) {
1401                                         cfg->vret_addr->opcode = OP_REGVAR;
1402                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1403                                 } else {
1404                                         /* The register is volatile */
1405                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1406                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1407                                         if (cfg->arch.omit_fp) {
1408                                                 cfg->vret_addr->inst_offset = offset;
1409                                                 offset += 8;
1410                                         } else {
1411                                                 offset += 8;
1412                                                 cfg->vret_addr->inst_offset = -offset;
1413                                         }
1414                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1415                                                 printf ("vret_addr =");
1416                                                 mono_print_ins (cfg->vret_addr);
1417                                         }
1418                                 }
1419                         }
1420                         else {
1421                                 cfg->ret->opcode = OP_REGVAR;
1422                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1423                         }
1424                         break;
1425                 case ArgValuetypeInReg:
1426                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1427                         cfg->ret->opcode = OP_REGOFFSET;
1428                         cfg->ret->inst_basereg = cfg->frame_reg;
1429                         if (cfg->arch.omit_fp) {
1430                                 cfg->ret->inst_offset = offset;
1431                                 offset += 16;
1432                         } else {
1433                                 offset += 16;
1434                                 cfg->ret->inst_offset = - offset;
1435                         }
1436                         break;
1437                 default:
1438                         g_assert_not_reached ();
1439                 }
1440                 if (!cfg->globalra)
1441                         cfg->ret->dreg = cfg->ret->inst_c0;
1442         }
1443
1444         /* Allocate locals */
1445         if (!cfg->globalra) {
1446                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1447                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1448                         char *mname = mono_method_full_name (cfg->method, TRUE);
1449                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1450                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1451                         g_free (mname);
1452                         return;
1453                 }
1454
1455                 if (locals_stack_align) {
1456                         offset += (locals_stack_align - 1);
1457                         offset &= ~(locals_stack_align - 1);
1458                 }
1459                 if (cfg->arch.omit_fp) {
1460                         cfg->locals_min_stack_offset = offset;
1461                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1462                 } else {
1463                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1464                         cfg->locals_max_stack_offset = - offset;
1465                 }
1466
1467                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1468                         if (offsets [i] != -1) {
1469                                 MonoInst *ins = cfg->varinfo [i];
1470                                 ins->opcode = OP_REGOFFSET;
1471                                 ins->inst_basereg = cfg->frame_reg;
1472                                 if (cfg->arch.omit_fp)
1473                                         ins->inst_offset = (offset + offsets [i]);
1474                                 else
1475                                         ins->inst_offset = - (offset + offsets [i]);
1476                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1477                         }
1478                 }
1479                 offset += locals_stack_size;
1480         }
1481
1482         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1483                 g_assert (!cfg->arch.omit_fp);
1484                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1485                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1486         }
1487
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ins = cfg->args [i];
1490                 if (ins->opcode != OP_REGVAR) {
1491                         ArgInfo *ainfo = &cinfo->args [i];
1492                         gboolean inreg = TRUE;
1493                         MonoType *arg_type;
1494
1495                         if (sig->hasthis && (i == 0))
1496                                 arg_type = &mono_defaults.object_class->byval_arg;
1497                         else
1498                                 arg_type = sig->params [i - sig->hasthis];
1499
1500                         if (cfg->globalra) {
1501                                 /* The new allocator needs info about the original locations of the arguments */
1502                                 switch (ainfo->storage) {
1503                                 case ArgInIReg:
1504                                 case ArgInFloatSSEReg:
1505                                 case ArgInDoubleSSEReg:
1506                                         ins->opcode = OP_REGVAR;
1507                                         ins->inst_c0 = ainfo->reg;
1508                                         break;
1509                                 case ArgOnStack:
1510                                         g_assert (!cfg->arch.omit_fp);
1511                                         ins->opcode = OP_REGOFFSET;
1512                                         ins->inst_basereg = cfg->frame_reg;
1513                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1514                                         break;
1515                                 case ArgValuetypeInReg:
1516                                         ins->opcode = OP_REGOFFSET;
1517                                         ins->inst_basereg = cfg->frame_reg;
1518                                         /* These arguments are saved to the stack in the prolog */
1519                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1520                                         if (cfg->arch.omit_fp) {
1521                                                 ins->inst_offset = offset;
1522                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1523                                         } else {
1524                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1525                                                 ins->inst_offset = - offset;
1526                                         }
1527                                         break;
1528                                 default:
1529                                         g_assert_not_reached ();
1530                                 }
1531
1532                                 continue;
1533                         }
1534
1535                         /* FIXME: Allocate volatile arguments to registers */
1536                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1537                                 inreg = FALSE;
1538
1539                         /*
1540                          * Under AMD64, all registers used to pass arguments to functions
1541                          * are volatile across calls.
1542                          * FIXME: Optimize this.
1543                          */
1544                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1545                                 inreg = FALSE;
1546
1547                         ins->opcode = OP_REGOFFSET;
1548
1549                         switch (ainfo->storage) {
1550                         case ArgInIReg:
1551                         case ArgInFloatSSEReg:
1552                         case ArgInDoubleSSEReg:
1553                                 if (inreg) {
1554                                         ins->opcode = OP_REGVAR;
1555                                         ins->dreg = ainfo->reg;
1556                                 }
1557                                 break;
1558                         case ArgOnStack:
1559                                 g_assert (!cfg->arch.omit_fp);
1560                                 ins->opcode = OP_REGOFFSET;
1561                                 ins->inst_basereg = cfg->frame_reg;
1562                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1563                                 break;
1564                         case ArgValuetypeInReg:
1565                                 break;
1566                         case ArgValuetypeAddrInIReg: {
1567                                 MonoInst *indir;
1568                                 g_assert (!cfg->arch.omit_fp);
1569
1570                                 MONO_INST_NEW (cfg, indir, 0);
1571                                 indir->opcode = OP_REGOFFSET;
1572                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1573                                         indir->inst_basereg = cfg->frame_reg;
1574                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1575                                         offset += (sizeof (gpointer));
1576                                         indir->inst_offset = - offset;
1577                                 }
1578                                 else {
1579                                         indir->inst_basereg = cfg->frame_reg;
1580                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1581                                 }
1582
1583                                 ins->opcode = OP_VTARG_ADDR;
1584                                 ins->inst_left = indir;
1585
1586                                 break;
1587                         }
1588                         default:
1589                                 NOT_IMPLEMENTED;
1590                         }
1591
1592                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1593                                 ins->opcode = OP_REGOFFSET;
1594                                 ins->inst_basereg = cfg->frame_reg;
1595                                 /* These arguments are saved to the stack in the prolog */
1596                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1597                                 if (cfg->arch.omit_fp) {
1598                                         ins->inst_offset = offset;
1599                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1600                                         // Arguments are yet supported by the stack map creation code
1601                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1602                                 } else {
1603                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1604                                         ins->inst_offset = - offset;
1605                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1606                                 }
1607                         }
1608                 }
1609         }
1610
1611         cfg->stack_offset = offset;
1612 }
1613
1614 void
1615 mono_arch_create_vars (MonoCompile *cfg)
1616 {
1617         MonoMethodSignature *sig;
1618         CallInfo *cinfo;
1619
1620         sig = mono_method_signature (cfg->method);
1621
1622         if (!cfg->arch.cinfo)
1623                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1624         cinfo = cfg->arch.cinfo;
1625
1626         if (cinfo->ret.storage == ArgValuetypeInReg)
1627                 cfg->ret_var_is_local = TRUE;
1628
1629         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1630                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1631                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1632                         printf ("vret_addr = ");
1633                         mono_print_ins (cfg->vret_addr);
1634                 }
1635         }
1636
1637         if (cfg->gen_seq_points) {
1638                 MonoInst *ins;
1639
1640             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1641                 ins->flags |= MONO_INST_VOLATILE;
1642                 cfg->arch.ss_trigger_page_var = ins;
1643         }
1644
1645 #ifdef MONO_AMD64_NO_PUSHES
1646         /*
1647          * When this is set, we pass arguments on the stack by moves, and by allocating
1648          * a bigger stack frame, instead of pushes.
1649          * Pushes complicate exception handling because the arguments on the stack have
1650          * to be popped each time a frame is unwound. They also make fp elimination
1651          * impossible.
1652          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1653          * on a new frame which doesn't include a param area.
1654          */
1655         cfg->arch.no_pushes = TRUE;
1656 #endif
1657 }
1658
1659 static void
1660 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1661 {
1662         MonoInst *ins;
1663
1664         switch (storage) {
1665         case ArgInIReg:
1666                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1667                 ins->dreg = mono_alloc_ireg (cfg);
1668                 ins->sreg1 = tree->dreg;
1669                 MONO_ADD_INS (cfg->cbb, ins);
1670                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1671                 break;
1672         case ArgInFloatSSEReg:
1673                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1674                 ins->dreg = mono_alloc_freg (cfg);
1675                 ins->sreg1 = tree->dreg;
1676                 MONO_ADD_INS (cfg->cbb, ins);
1677
1678                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1679                 break;
1680         case ArgInDoubleSSEReg:
1681                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1682                 ins->dreg = mono_alloc_freg (cfg);
1683                 ins->sreg1 = tree->dreg;
1684                 MONO_ADD_INS (cfg->cbb, ins);
1685
1686                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1687
1688                 break;
1689         default:
1690                 g_assert_not_reached ();
1691         }
1692 }
1693
1694 static int
1695 arg_storage_to_load_membase (ArgStorage storage)
1696 {
1697         switch (storage) {
1698         case ArgInIReg:
1699                 return OP_LOAD_MEMBASE;
1700         case ArgInDoubleSSEReg:
1701                 return OP_LOADR8_MEMBASE;
1702         case ArgInFloatSSEReg:
1703                 return OP_LOADR4_MEMBASE;
1704         default:
1705                 g_assert_not_reached ();
1706         }
1707
1708         return -1;
1709 }
1710
1711 static void
1712 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1713 {
1714         MonoInst *arg;
1715         MonoMethodSignature *tmp_sig;
1716         MonoInst *sig_arg;
1717
1718         if (call->tail_call)
1719                 NOT_IMPLEMENTED;
1720
1721         /* FIXME: Add support for signature tokens to AOT */
1722         cfg->disable_aot = TRUE;
1723
1724         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1725
1726         /*
1727          * mono_ArgIterator_Setup assumes the signature cookie is
1728          * passed first and all the arguments which were before it are
1729          * passed on the stack after the signature. So compensate by
1730          * passing a different signature.
1731          */
1732         tmp_sig = mono_metadata_signature_dup (call->signature);
1733         tmp_sig->param_count -= call->signature->sentinelpos;
1734         tmp_sig->sentinelpos = 0;
1735         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1736
1737         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1738         sig_arg->dreg = mono_alloc_ireg (cfg);
1739         sig_arg->inst_p0 = tmp_sig;
1740         MONO_ADD_INS (cfg->cbb, sig_arg);
1741
1742         if (cfg->arch.no_pushes) {
1743                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1744         } else {
1745                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1746                 arg->sreg1 = sig_arg->dreg;
1747                 MONO_ADD_INS (cfg->cbb, arg);
1748         }
1749 }
1750
1751 static inline LLVMArgStorage
1752 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1753 {
1754         switch (storage) {
1755         case ArgInIReg:
1756                 return LLVMArgInIReg;
1757         case ArgNone:
1758                 return LLVMArgNone;
1759         default:
1760                 g_assert_not_reached ();
1761                 return LLVMArgNone;
1762         }
1763 }
1764
1765 #ifdef ENABLE_LLVM
1766 LLVMCallInfo*
1767 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1768 {
1769         int i, n;
1770         CallInfo *cinfo;
1771         ArgInfo *ainfo;
1772         int j;
1773         LLVMCallInfo *linfo;
1774         MonoType *t;
1775
1776         n = sig->param_count + sig->hasthis;
1777
1778         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1779
1780         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1781
1782         /*
1783          * LLVM always uses the native ABI while we use our own ABI, the
1784          * only difference is the handling of vtypes:
1785          * - we only pass/receive them in registers in some cases, and only
1786          *   in 1 or 2 integer registers.
1787          */
1788         if (cinfo->ret.storage == ArgValuetypeInReg) {
1789                 if (sig->pinvoke) {
1790                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1791                         cfg->disable_llvm = TRUE;
1792                         return linfo;
1793                 }
1794
1795                 linfo->ret.storage = LLVMArgVtypeInReg;
1796                 for (j = 0; j < 2; ++j)
1797                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1798         }
1799
1800         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1801                 /* Vtype returned using a hidden argument */
1802                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1803         }
1804
1805         for (i = 0; i < n; ++i) {
1806                 ainfo = cinfo->args + i;
1807
1808                 if (i >= sig->hasthis)
1809                         t = sig->params [i - sig->hasthis];
1810                 else
1811                         t = &mono_defaults.int_class->byval_arg;
1812
1813                 linfo->args [i].storage = LLVMArgNone;
1814
1815                 switch (ainfo->storage) {
1816                 case ArgInIReg:
1817                         linfo->args [i].storage = LLVMArgInIReg;
1818                         break;
1819                 case ArgInDoubleSSEReg:
1820                 case ArgInFloatSSEReg:
1821                         linfo->args [i].storage = LLVMArgInFPReg;
1822                         break;
1823                 case ArgOnStack:
1824                         if (MONO_TYPE_ISSTRUCT (t)) {
1825                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1826                         } else {
1827                                 linfo->args [i].storage = LLVMArgInIReg;
1828                                 if (!t->byref) {
1829                                         if (t->type == MONO_TYPE_R4)
1830                                                 linfo->args [i].storage = LLVMArgInFPReg;
1831                                         else if (t->type == MONO_TYPE_R8)
1832                                                 linfo->args [i].storage = LLVMArgInFPReg;
1833                                 }
1834                         }
1835                         break;
1836                 case ArgValuetypeInReg:
1837                         if (sig->pinvoke) {
1838                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1839                                 cfg->disable_llvm = TRUE;
1840                                 return linfo;
1841                         }
1842
1843                         linfo->args [i].storage = LLVMArgVtypeInReg;
1844                         for (j = 0; j < 2; ++j)
1845                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1846                         break;
1847                 default:
1848                         cfg->exception_message = g_strdup ("ainfo->storage");
1849                         cfg->disable_llvm = TRUE;
1850                         break;
1851                 }
1852         }
1853
1854         return linfo;
1855 }
1856 #endif
1857
1858 void
1859 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1860 {
1861         MonoInst *arg, *in;
1862         MonoMethodSignature *sig;
1863         int i, n, stack_size;
1864         CallInfo *cinfo;
1865         ArgInfo *ainfo;
1866
1867         stack_size = 0;
1868
1869         sig = call->signature;
1870         n = sig->param_count + sig->hasthis;
1871
1872         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1873
1874         if (COMPILE_LLVM (cfg)) {
1875                 /* We shouldn't be called in the llvm case */
1876                 cfg->disable_llvm = TRUE;
1877                 return;
1878         }
1879
1880         if (cinfo->need_stack_align) {
1881                 if (!cfg->arch.no_pushes)
1882                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1883         }
1884
1885         /*
1886          * Emit all arguments which are passed on the stack to prevent register
1887          * allocation problems.
1888          */
1889         if (cfg->arch.no_pushes) {
1890                 for (i = 0; i < n; ++i) {
1891                         MonoType *t;
1892                         ainfo = cinfo->args + i;
1893
1894                         in = call->args [i];
1895
1896                         if (sig->hasthis && i == 0)
1897                                 t = &mono_defaults.object_class->byval_arg;
1898                         else
1899                                 t = sig->params [i - sig->hasthis];
1900
1901                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1902                                 if (!t->byref) {
1903                                         if (t->type == MONO_TYPE_R4)
1904                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1905                                         else if (t->type == MONO_TYPE_R8)
1906                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1907                                         else
1908                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1909                                 } else {
1910                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1911                                 }
1912                         }
1913                 }
1914         }
1915
1916         /*
1917          * Emit all parameters passed in registers in non-reverse order for better readability
1918          * and to help the optimization in emit_prolog ().
1919          */
1920         for (i = 0; i < n; ++i) {
1921                 ainfo = cinfo->args + i;
1922
1923                 in = call->args [i];
1924
1925                 if (ainfo->storage == ArgInIReg)
1926                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1927         }
1928
1929         for (i = n - 1; i >= 0; --i) {
1930                 ainfo = cinfo->args + i;
1931
1932                 in = call->args [i];
1933
1934                 switch (ainfo->storage) {
1935                 case ArgInIReg:
1936                         /* Already done */
1937                         break;
1938                 case ArgInFloatSSEReg:
1939                 case ArgInDoubleSSEReg:
1940                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1941                         break;
1942                 case ArgOnStack:
1943                 case ArgValuetypeInReg:
1944                 case ArgValuetypeAddrInIReg:
1945                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1946                                 MonoInst *call_inst = (MonoInst*)call;
1947                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1948                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1949                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1950                                 guint32 align;
1951                                 guint32 size;
1952
1953                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1954                                         size = sizeof (MonoTypedRef);
1955                                         align = sizeof (gpointer);
1956                                 }
1957                                 else {
1958                                         if (sig->pinvoke)
1959                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1960                                         else {
1961                                                 /*
1962                                                  * Other backends use mono_type_stack_size (), but that
1963                                                  * aligns the size to 8, which is larger than the size of
1964                                                  * the source, leading to reads of invalid memory if the
1965                                                  * source is at the end of address space.
1966                                                  */
1967                                                 size = mono_class_value_size (in->klass, &align);
1968                                         }
1969                                 }
1970                                 g_assert (in->klass);
1971
1972                                 if (size > 0) {
1973                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1974                                         arg->sreg1 = in->dreg;
1975                                         arg->klass = in->klass;
1976                                         arg->backend.size = size;
1977                                         arg->inst_p0 = call;
1978                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1979                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1980
1981                                         MONO_ADD_INS (cfg->cbb, arg);
1982                                 }
1983                         } else {
1984                                 if (cfg->arch.no_pushes) {
1985                                         /* Already done */
1986                                 } else {
1987                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1988                                         arg->sreg1 = in->dreg;
1989                                         if (!sig->params [i - sig->hasthis]->byref) {
1990                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1991                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1992                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1993                                                         arg->inst_destbasereg = X86_ESP;
1994                                                         arg->inst_offset = 0;
1995                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1996                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1997                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1998                                                         arg->inst_destbasereg = X86_ESP;
1999                                                         arg->inst_offset = 0;
2000                                                 }
2001                                         }
2002                                         MONO_ADD_INS (cfg->cbb, arg);
2003                                 }
2004                         }
2005                         break;
2006                 default:
2007                         g_assert_not_reached ();
2008                 }
2009
2010                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2011                         /* Emit the signature cookie just before the implicit arguments */
2012                         emit_sig_cookie (cfg, call, cinfo);
2013         }
2014
2015         /* Handle the case where there are no implicit arguments */
2016         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2017                 emit_sig_cookie (cfg, call, cinfo);
2018
2019         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2020                 MonoInst *vtarg;
2021
2022                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2023                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2024                                 /*
2025                                  * Tell the JIT to use a more efficient calling convention: call using
2026                                  * OP_CALL, compute the result location after the call, and save the
2027                                  * result there.
2028                                  */
2029                                 call->vret_in_reg = TRUE;
2030                                 /*
2031                                  * Nullify the instruction computing the vret addr to enable
2032                                  * future optimizations.
2033                                  */
2034                                 if (call->vret_var)
2035                                         NULLIFY_INS (call->vret_var);
2036                         } else {
2037                                 if (call->tail_call)
2038                                         NOT_IMPLEMENTED;
2039                                 /*
2040                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2041                                  * the stack. Push the address here, so the call instruction can
2042                                  * access it.
2043                                  */
2044                                 if (!cfg->arch.vret_addr_loc) {
2045                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2046                                         /* Prevent it from being register allocated or optimized away */
2047                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2048                                 }
2049
2050                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2051                         }
2052                 }
2053                 else {
2054                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2055                         vtarg->sreg1 = call->vret_var->dreg;
2056                         vtarg->dreg = mono_alloc_preg (cfg);
2057                         MONO_ADD_INS (cfg->cbb, vtarg);
2058
2059                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2060                 }
2061         }
2062
2063 #ifdef HOST_WIN32
2064         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2065                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2066         }
2067 #endif
2068
2069         if (cfg->method->save_lmf) {
2070                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2071                 MONO_ADD_INS (cfg->cbb, arg);
2072         }
2073
2074         call->stack_usage = cinfo->stack_usage;
2075 }
2076
2077 void
2078 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2079 {
2080         MonoInst *arg;
2081         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2082         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2083         int size = ins->backend.size;
2084
2085         if (ainfo->storage == ArgValuetypeInReg) {
2086                 MonoInst *load;
2087                 int part;
2088
2089                 for (part = 0; part < 2; ++part) {
2090                         if (ainfo->pair_storage [part] == ArgNone)
2091                                 continue;
2092
2093                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2094                         load->inst_basereg = src->dreg;
2095                         load->inst_offset = part * sizeof (gpointer);
2096
2097                         switch (ainfo->pair_storage [part]) {
2098                         case ArgInIReg:
2099                                 load->dreg = mono_alloc_ireg (cfg);
2100                                 break;
2101                         case ArgInDoubleSSEReg:
2102                         case ArgInFloatSSEReg:
2103                                 load->dreg = mono_alloc_freg (cfg);
2104                                 break;
2105                         default:
2106                                 g_assert_not_reached ();
2107                         }
2108                         MONO_ADD_INS (cfg->cbb, load);
2109
2110                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2111                 }
2112         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2113                 MonoInst *vtaddr, *load;
2114                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2115
2116                 g_assert (!cfg->arch.no_pushes);
2117
2118                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2119                 load->inst_p0 = vtaddr;
2120                 vtaddr->flags |= MONO_INST_INDIRECT;
2121                 load->type = STACK_MP;
2122                 load->klass = vtaddr->klass;
2123                 load->dreg = mono_alloc_ireg (cfg);
2124                 MONO_ADD_INS (cfg->cbb, load);
2125                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2126
2127                 if (ainfo->pair_storage [0] == ArgInIReg) {
2128                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2129                         arg->dreg = mono_alloc_ireg (cfg);
2130                         arg->sreg1 = load->dreg;
2131                         arg->inst_imm = 0;
2132                         MONO_ADD_INS (cfg->cbb, arg);
2133                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2134                 } else {
2135                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2136                         arg->sreg1 = load->dreg;
2137                         MONO_ADD_INS (cfg->cbb, arg);
2138                 }
2139         } else {
2140                 if (size == 8) {
2141                         if (cfg->arch.no_pushes) {
2142                                 int dreg = mono_alloc_ireg (cfg);
2143
2144                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2145                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2146                         } else {
2147                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2148                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2149                                 arg->inst_basereg = src->dreg;
2150                                 arg->inst_offset = 0;
2151                                 MONO_ADD_INS (cfg->cbb, arg);
2152                         }
2153                 } else if (size <= 40) {
2154                         if (cfg->arch.no_pushes) {
2155                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2156                         } else {
2157                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2158                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2159                         }
2160                 } else {
2161                         if (cfg->arch.no_pushes) {
2162                                 // FIXME: Code growth
2163                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2164                         } else {
2165                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2166                                 arg->inst_basereg = src->dreg;
2167                                 arg->inst_offset = 0;
2168                                 arg->inst_imm = size;
2169                                 MONO_ADD_INS (cfg->cbb, arg);
2170                         }
2171                 }
2172         }
2173 }
2174
2175 void
2176 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2177 {
2178         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2179
2180         if (ret->type == MONO_TYPE_R4) {
2181                 if (COMPILE_LLVM (cfg))
2182                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2183                 else
2184                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2185                 return;
2186         } else if (ret->type == MONO_TYPE_R8) {
2187                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2188                 return;
2189         }
2190
2191         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2192 }
2193
2194 #endif /* DISABLE_JIT */
2195
2196 #define EMIT_COND_BRANCH(ins,cond,sign) \
2197         if (ins->inst_true_bb->native_offset) { \
2198                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2199         } else { \
2200                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2201                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2202             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2203                         x86_branch8 (code, cond, 0, sign); \
2204                 else \
2205                         x86_branch32 (code, cond, 0, sign); \
2206 }
2207
2208 typedef struct {
2209         MonoMethodSignature *sig;
2210         CallInfo *cinfo;
2211 } ArchDynCallInfo;
2212
2213 typedef struct {
2214         mgreg_t regs [PARAM_REGS];
2215         mgreg_t res;
2216         guint8 *ret;
2217 } DynCallArgs;
2218
2219 static gboolean
2220 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2221 {
2222         int i;
2223
2224 #ifdef HOST_WIN32
2225         return FALSE;
2226 #endif
2227
2228         switch (cinfo->ret.storage) {
2229         case ArgNone:
2230         case ArgInIReg:
2231                 break;
2232         case ArgValuetypeInReg: {
2233                 ArgInfo *ainfo = &cinfo->ret;
2234
2235                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2236                         return FALSE;
2237                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2238                         return FALSE;
2239                 break;
2240         }
2241         default:
2242                 return FALSE;
2243         }
2244
2245         for (i = 0; i < cinfo->nargs; ++i) {
2246                 ArgInfo *ainfo = &cinfo->args [i];
2247                 switch (ainfo->storage) {
2248                 case ArgInIReg:
2249                         break;
2250                 case ArgValuetypeInReg:
2251                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2252                                 return FALSE;
2253                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2254                                 return FALSE;
2255                         break;
2256                 default:
2257                         return FALSE;
2258                 }
2259         }
2260
2261         return TRUE;
2262 }
2263
2264 /*
2265  * mono_arch_dyn_call_prepare:
2266  *
2267  *   Return a pointer to an arch-specific structure which contains information
2268  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2269  * supported for SIG.
2270  * This function is equivalent to ffi_prep_cif in libffi.
2271  */
2272 MonoDynCallInfo*
2273 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2274 {
2275         ArchDynCallInfo *info;
2276         CallInfo *cinfo;
2277
2278         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2279
2280         if (!dyn_call_supported (sig, cinfo)) {
2281                 g_free (cinfo);
2282                 return NULL;
2283         }
2284
2285         info = g_new0 (ArchDynCallInfo, 1);
2286         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2287         info->sig = sig;
2288         info->cinfo = cinfo;
2289
2290         return (MonoDynCallInfo*)info;
2291 }
2292
2293 /*
2294  * mono_arch_dyn_call_free:
2295  *
2296  *   Free a MonoDynCallInfo structure.
2297  */
2298 void
2299 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2300 {
2301         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2302
2303         g_free (ainfo->cinfo);
2304         g_free (ainfo);
2305 }
2306
2307 /*
2308  * mono_arch_get_start_dyn_call:
2309  *
2310  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2311  * store the result into BUF.
2312  * ARGS should be an array of pointers pointing to the arguments.
2313  * RET should point to a memory buffer large enought to hold the result of the
2314  * call.
2315  * This function should be as fast as possible, any work which does not depend
2316  * on the actual values of the arguments should be done in
2317  * mono_arch_dyn_call_prepare ().
2318  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2319  * libffi.
2320  */
2321 void
2322 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2323 {
2324         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2325         DynCallArgs *p = (DynCallArgs*)buf;
2326         int arg_index, greg, i;
2327         MonoMethodSignature *sig = dinfo->sig;
2328
2329         g_assert (buf_len >= sizeof (DynCallArgs));
2330
2331         p->res = 0;
2332         p->ret = ret;
2333
2334         arg_index = 0;
2335         greg = 0;
2336
2337         if (dinfo->cinfo->vtype_retaddr)
2338                 p->regs [greg ++] = (mgreg_t)ret;
2339
2340         if (sig->hasthis) {
2341                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2342         }
2343
2344         for (i = 0; i < sig->param_count; i++) {
2345                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2346                 gpointer *arg = args [arg_index ++];
2347
2348                 if (t->byref) {
2349                         p->regs [greg ++] = (mgreg_t)*(arg);
2350                         continue;
2351                 }
2352
2353                 switch (t->type) {
2354                 case MONO_TYPE_STRING:
2355                 case MONO_TYPE_CLASS:
2356                 case MONO_TYPE_ARRAY:
2357                 case MONO_TYPE_SZARRAY:
2358                 case MONO_TYPE_OBJECT:
2359                 case MONO_TYPE_PTR:
2360                 case MONO_TYPE_I:
2361                 case MONO_TYPE_U:
2362                 case MONO_TYPE_I8:
2363                 case MONO_TYPE_U8:
2364                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2365                         p->regs [greg ++] = (mgreg_t)*(arg);
2366                         break;
2367                 case MONO_TYPE_BOOLEAN:
2368                 case MONO_TYPE_U1:
2369                         p->regs [greg ++] = *(guint8*)(arg);
2370                         break;
2371                 case MONO_TYPE_I1:
2372                         p->regs [greg ++] = *(gint8*)(arg);
2373                         break;
2374                 case MONO_TYPE_I2:
2375                         p->regs [greg ++] = *(gint16*)(arg);
2376                         break;
2377                 case MONO_TYPE_U2:
2378                 case MONO_TYPE_CHAR:
2379                         p->regs [greg ++] = *(guint16*)(arg);
2380                         break;
2381                 case MONO_TYPE_I4:
2382                         p->regs [greg ++] = *(gint32*)(arg);
2383                         break;
2384                 case MONO_TYPE_U4:
2385                         p->regs [greg ++] = *(guint32*)(arg);
2386                         break;
2387                 case MONO_TYPE_GENERICINST:
2388                     if (MONO_TYPE_IS_REFERENCE (t)) {
2389                                 p->regs [greg ++] = (mgreg_t)*(arg);
2390                                 break;
2391                         } else {
2392                                 /* Fall through */
2393                         }
2394                 case MONO_TYPE_VALUETYPE: {
2395                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2396
2397                         g_assert (ainfo->storage == ArgValuetypeInReg);
2398                         if (ainfo->pair_storage [0] != ArgNone) {
2399                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2400                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2401                         }
2402                         if (ainfo->pair_storage [1] != ArgNone) {
2403                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2404                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2405                         }
2406                         break;
2407                 }
2408                 default:
2409                         g_assert_not_reached ();
2410                 }
2411         }
2412
2413         g_assert (greg <= PARAM_REGS);
2414 }
2415
2416 /*
2417  * mono_arch_finish_dyn_call:
2418  *
2419  *   Store the result of a dyn call into the return value buffer passed to
2420  * start_dyn_call ().
2421  * This function should be as fast as possible, any work which does not depend
2422  * on the actual values of the arguments should be done in
2423  * mono_arch_dyn_call_prepare ().
2424  */
2425 void
2426 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2427 {
2428         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2429         MonoMethodSignature *sig = dinfo->sig;
2430         guint8 *ret = ((DynCallArgs*)buf)->ret;
2431         mgreg_t res = ((DynCallArgs*)buf)->res;
2432
2433         switch (mono_type_get_underlying_type (sig->ret)->type) {
2434         case MONO_TYPE_VOID:
2435                 *(gpointer*)ret = NULL;
2436                 break;
2437         case MONO_TYPE_STRING:
2438         case MONO_TYPE_CLASS:
2439         case MONO_TYPE_ARRAY:
2440         case MONO_TYPE_SZARRAY:
2441         case MONO_TYPE_OBJECT:
2442         case MONO_TYPE_I:
2443         case MONO_TYPE_U:
2444         case MONO_TYPE_PTR:
2445                 *(gpointer*)ret = (gpointer)res;
2446                 break;
2447         case MONO_TYPE_I1:
2448                 *(gint8*)ret = res;
2449                 break;
2450         case MONO_TYPE_U1:
2451         case MONO_TYPE_BOOLEAN:
2452                 *(guint8*)ret = res;
2453                 break;
2454         case MONO_TYPE_I2:
2455                 *(gint16*)ret = res;
2456                 break;
2457         case MONO_TYPE_U2:
2458         case MONO_TYPE_CHAR:
2459                 *(guint16*)ret = res;
2460                 break;
2461         case MONO_TYPE_I4:
2462                 *(gint32*)ret = res;
2463                 break;
2464         case MONO_TYPE_U4:
2465                 *(guint32*)ret = res;
2466                 break;
2467         case MONO_TYPE_I8:
2468                 *(gint64*)ret = res;
2469                 break;
2470         case MONO_TYPE_U8:
2471                 *(guint64*)ret = res;
2472                 break;
2473         case MONO_TYPE_GENERICINST:
2474                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2475                         *(gpointer*)ret = (gpointer)res;
2476                         break;
2477                 } else {
2478                         /* Fall through */
2479                 }
2480         case MONO_TYPE_VALUETYPE:
2481                 if (dinfo->cinfo->vtype_retaddr) {
2482                         /* Nothing to do */
2483                 } else {
2484                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2485
2486                         g_assert (ainfo->storage == ArgValuetypeInReg);
2487
2488                         if (ainfo->pair_storage [0] != ArgNone) {
2489                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2490                                 ((mgreg_t*)ret)[0] = res;
2491                         }
2492
2493                         g_assert (ainfo->pair_storage [1] == ArgNone);
2494                 }
2495                 break;
2496         default:
2497                 g_assert_not_reached ();
2498         }
2499 }
2500
2501 /* emit an exception if condition is fail */
2502 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2503         do {                                                        \
2504                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2505                 if (tins == NULL) {                                                                             \
2506                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2507                                         MONO_PATCH_INFO_EXC, exc_name);  \
2508                         x86_branch32 (code, cond, 0, signed);               \
2509                 } else {        \
2510                         EMIT_COND_BRANCH (tins, cond, signed);  \
2511                 }                       \
2512         } while (0);
2513
2514 #define EMIT_FPCOMPARE(code) do { \
2515         amd64_fcompp (code); \
2516         amd64_fnstsw (code); \
2517 } while (0);
2518
2519 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2520     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2521         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2522         amd64_ ##op (code); \
2523         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2524         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2525 } while (0);
2526
2527 static guint8*
2528 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2529 {
2530         gboolean no_patch = FALSE;
2531
2532         /*
2533          * FIXME: Add support for thunks
2534          */
2535         {
2536                 gboolean near_call = FALSE;
2537
2538                 /*
2539                  * Indirect calls are expensive so try to make a near call if possible.
2540                  * The caller memory is allocated by the code manager so it is
2541                  * guaranteed to be at a 32 bit offset.
2542                  */
2543
2544                 if (patch_type != MONO_PATCH_INFO_ABS) {
2545                         /* The target is in memory allocated using the code manager */
2546                         near_call = TRUE;
2547
2548                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2549                                 if (((MonoMethod*)data)->klass->image->aot_module)
2550                                         /* The callee might be an AOT method */
2551                                         near_call = FALSE;
2552                                 if (((MonoMethod*)data)->dynamic)
2553                                         /* The target is in malloc-ed memory */
2554                                         near_call = FALSE;
2555                         }
2556
2557                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2558                                 /*
2559                                  * The call might go directly to a native function without
2560                                  * the wrapper.
2561                                  */
2562                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2563                                 if (mi) {
2564                                         gconstpointer target = mono_icall_get_wrapper (mi);
2565                                         if ((((guint64)target) >> 32) != 0)
2566                                                 near_call = FALSE;
2567                                 }
2568                         }
2569                 }
2570                 else {
2571                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2572                                 /*
2573                                  * This is not really an optimization, but required because the
2574                                  * generic class init trampolines use R11 to pass the vtable.
2575                                  */
2576                                 near_call = TRUE;
2577                         } else {
2578                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2579                                 if (info) {
2580                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2581                                                 strstr (cfg->method->name, info->name)) {
2582                                                 /* A call to the wrapped function */
2583                                                 if ((((guint64)data) >> 32) == 0)
2584                                                         near_call = TRUE;
2585                                                 no_patch = TRUE;
2586                                         }
2587                                         else if (info->func == info->wrapper) {
2588                                                 /* No wrapper */
2589                                                 if ((((guint64)info->func) >> 32) == 0)
2590                                                         near_call = TRUE;
2591                                         }
2592                                         else {
2593                                                 /* See the comment in mono_codegen () */
2594                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2595                                                         near_call = TRUE;
2596                                         }
2597                                 }
2598                                 else if ((((guint64)data) >> 32) == 0) {
2599                                         near_call = TRUE;
2600                                         no_patch = TRUE;
2601                                 }
2602                         }
2603                 }
2604
2605                 if (cfg->method->dynamic)
2606                         /* These methods are allocated using malloc */
2607                         near_call = FALSE;
2608
2609 #ifdef MONO_ARCH_NOMAP32BIT
2610                 near_call = FALSE;
2611 #endif
2612
2613                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2614                 if (optimize_for_xen)
2615                         near_call = FALSE;
2616
2617                 if (cfg->compile_aot) {
2618                         near_call = TRUE;
2619                         no_patch = TRUE;
2620                 }
2621
2622                 if (near_call) {
2623                         /*
2624                          * Align the call displacement to an address divisible by 4 so it does
2625                          * not span cache lines. This is required for code patching to work on SMP
2626                          * systems.
2627                          */
2628                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2629                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2630                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2631                         amd64_call_code (code, 0);
2632                 }
2633                 else {
2634                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2635                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2636                         amd64_call_reg (code, GP_SCRATCH_REG);
2637                 }
2638         }
2639
2640         return code;
2641 }
2642
2643 static inline guint8*
2644 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2645 {
2646 #ifdef HOST_WIN32
2647         if (win64_adjust_stack)
2648                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2649 #endif
2650         code = emit_call_body (cfg, code, patch_type, data);
2651 #ifdef HOST_WIN32
2652         if (win64_adjust_stack)
2653                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2654 #endif
2655
2656         return code;
2657 }
2658
2659 static inline int
2660 store_membase_imm_to_store_membase_reg (int opcode)
2661 {
2662         switch (opcode) {
2663         case OP_STORE_MEMBASE_IMM:
2664                 return OP_STORE_MEMBASE_REG;
2665         case OP_STOREI4_MEMBASE_IMM:
2666                 return OP_STOREI4_MEMBASE_REG;
2667         case OP_STOREI8_MEMBASE_IMM:
2668                 return OP_STOREI8_MEMBASE_REG;
2669         }
2670
2671         return -1;
2672 }
2673
2674 #ifndef DISABLE_JIT
2675
2676 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2677
2678 /*
2679  * mono_arch_peephole_pass_1:
2680  *
2681  *   Perform peephole opts which should/can be performed before local regalloc
2682  */
2683 void
2684 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2685 {
2686         MonoInst *ins, *n;
2687
2688         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2689                 MonoInst *last_ins = ins->prev;
2690
2691                 switch (ins->opcode) {
2692                 case OP_ADD_IMM:
2693                 case OP_IADD_IMM:
2694                 case OP_LADD_IMM:
2695                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2696                                 /*
2697                                  * X86_LEA is like ADD, but doesn't have the
2698                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2699                                  * its operand to 64 bit.
2700                                  */
2701                                 ins->opcode = OP_X86_LEA_MEMBASE;
2702                                 ins->inst_basereg = ins->sreg1;
2703                         }
2704                         break;
2705                 case OP_LXOR:
2706                 case OP_IXOR:
2707                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2708                                 MonoInst *ins2;
2709
2710                                 /*
2711                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2712                                  * the latter has length 2-3 instead of 6 (reverse constant
2713                                  * propagation). These instruction sequences are very common
2714                                  * in the initlocals bblock.
2715                                  */
2716                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2717                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2718                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2719                                                 ins2->sreg1 = ins->dreg;
2720                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2721                                                 /* Continue */
2722                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2723                                                 NULLIFY_INS (ins2);
2724                                                 /* Continue */
2725                                         } else {
2726                                                 break;
2727                                         }
2728                                 }
2729                         }
2730                         break;
2731                 case OP_COMPARE_IMM:
2732                 case OP_LCOMPARE_IMM:
2733                         /* OP_COMPARE_IMM (reg, 0)
2734                          * -->
2735                          * OP_AMD64_TEST_NULL (reg)
2736                          */
2737                         if (!ins->inst_imm)
2738                                 ins->opcode = OP_AMD64_TEST_NULL;
2739                         break;
2740                 case OP_ICOMPARE_IMM:
2741                         if (!ins->inst_imm)
2742                                 ins->opcode = OP_X86_TEST_NULL;
2743                         break;
2744                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2745                         /*
2746                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2747                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2748                          * -->
2749                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2750                          * OP_COMPARE_IMM reg, imm
2751                          *
2752                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2753                          */
2754                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2755                             ins->inst_basereg == last_ins->inst_destbasereg &&
2756                             ins->inst_offset == last_ins->inst_offset) {
2757                                         ins->opcode = OP_ICOMPARE_IMM;
2758                                         ins->sreg1 = last_ins->sreg1;
2759
2760                                         /* check if we can remove cmp reg,0 with test null */
2761                                         if (!ins->inst_imm)
2762                                                 ins->opcode = OP_X86_TEST_NULL;
2763                                 }
2764
2765                         break;
2766                 }
2767
2768                 mono_peephole_ins (bb, ins);
2769         }
2770 }
2771
2772 void
2773 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2774 {
2775         MonoInst *ins, *n;
2776
2777         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2778                 switch (ins->opcode) {
2779                 case OP_ICONST:
2780                 case OP_I8CONST: {
2781                         /* reg = 0 -> XOR (reg, reg) */
2782                         /* XOR sets cflags on x86, so we cant do it always */
2783                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2784                                 ins->opcode = OP_LXOR;
2785                                 ins->sreg1 = ins->dreg;
2786                                 ins->sreg2 = ins->dreg;
2787                                 /* Fall through */
2788                         } else {
2789                                 break;
2790                         }
2791                 }
2792                 case OP_LXOR:
2793                         /*
2794                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2795                          * 0 result into 64 bits.
2796                          */
2797                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2798                                 ins->opcode = OP_IXOR;
2799                         }
2800                         /* Fall through */
2801                 case OP_IXOR:
2802                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2803                                 MonoInst *ins2;
2804
2805                                 /*
2806                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2807                                  * the latter has length 2-3 instead of 6 (reverse constant
2808                                  * propagation). These instruction sequences are very common
2809                                  * in the initlocals bblock.
2810                                  */
2811                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2812                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2813                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2814                                                 ins2->sreg1 = ins->dreg;
2815                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2816                                                 /* Continue */
2817                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2818                                                 NULLIFY_INS (ins2);
2819                                                 /* Continue */
2820                                         } else {
2821                                                 break;
2822                                         }
2823                                 }
2824                         }
2825                         break;
2826                 case OP_IADD_IMM:
2827                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2828                                 ins->opcode = OP_X86_INC_REG;
2829                         break;
2830                 case OP_ISUB_IMM:
2831                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2832                                 ins->opcode = OP_X86_DEC_REG;
2833                         break;
2834                 }
2835
2836                 mono_peephole_ins (bb, ins);
2837         }
2838 }
2839
2840 #define NEW_INS(cfg,ins,dest,op) do {   \
2841                 MONO_INST_NEW ((cfg), (dest), (op)); \
2842         (dest)->cil_code = (ins)->cil_code; \
2843         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2844         } while (0)
2845
2846 /*
2847  * mono_arch_lowering_pass:
2848  *
2849  *  Converts complex opcodes into simpler ones so that each IR instruction
2850  * corresponds to one machine instruction.
2851  */
2852 void
2853 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2854 {
2855         MonoInst *ins, *n, *temp;
2856
2857         /*
2858          * FIXME: Need to add more instructions, but the current machine
2859          * description can't model some parts of the composite instructions like
2860          * cdq.
2861          */
2862         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2863                 switch (ins->opcode) {
2864                 case OP_DIV_IMM:
2865                 case OP_REM_IMM:
2866                 case OP_IDIV_IMM:
2867                 case OP_IDIV_UN_IMM:
2868                 case OP_IREM_UN_IMM:
2869                         mono_decompose_op_imm (cfg, bb, ins);
2870                         break;
2871                 case OP_IREM_IMM:
2872                         /* Keep the opcode if we can implement it efficiently */
2873                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2874                                 mono_decompose_op_imm (cfg, bb, ins);
2875                         break;
2876                 case OP_COMPARE_IMM:
2877                 case OP_LCOMPARE_IMM:
2878                         if (!amd64_is_imm32 (ins->inst_imm)) {
2879                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2880                                 temp->inst_c0 = ins->inst_imm;
2881                                 temp->dreg = mono_alloc_ireg (cfg);
2882                                 ins->opcode = OP_COMPARE;
2883                                 ins->sreg2 = temp->dreg;
2884                         }
2885                         break;
2886                 case OP_LOAD_MEMBASE:
2887                 case OP_LOADI8_MEMBASE:
2888                         if (!amd64_is_imm32 (ins->inst_offset)) {
2889                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2890                                 temp->inst_c0 = ins->inst_offset;
2891                                 temp->dreg = mono_alloc_ireg (cfg);
2892                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2893                                 ins->inst_indexreg = temp->dreg;
2894                         }
2895                         break;
2896                 case OP_STORE_MEMBASE_IMM:
2897                 case OP_STOREI8_MEMBASE_IMM:
2898                         if (!amd64_is_imm32 (ins->inst_imm)) {
2899                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2900                                 temp->inst_c0 = ins->inst_imm;
2901                                 temp->dreg = mono_alloc_ireg (cfg);
2902                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2903                                 ins->sreg1 = temp->dreg;
2904                         }
2905                         break;
2906 #ifdef MONO_ARCH_SIMD_INTRINSICS
2907                 case OP_EXPAND_I1: {
2908                                 int temp_reg1 = mono_alloc_ireg (cfg);
2909                                 int temp_reg2 = mono_alloc_ireg (cfg);
2910                                 int original_reg = ins->sreg1;
2911
2912                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2913                                 temp->sreg1 = original_reg;
2914                                 temp->dreg = temp_reg1;
2915
2916                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2917                                 temp->sreg1 = temp_reg1;
2918                                 temp->dreg = temp_reg2;
2919                                 temp->inst_imm = 8;
2920
2921                                 NEW_INS (cfg, ins, temp, OP_LOR);
2922                                 temp->sreg1 = temp->dreg = temp_reg2;
2923                                 temp->sreg2 = temp_reg1;
2924
2925                                 ins->opcode = OP_EXPAND_I2;
2926                                 ins->sreg1 = temp_reg2;
2927                         }
2928                         break;
2929 #endif
2930                 default:
2931                         break;
2932                 }
2933         }
2934
2935         bb->max_vreg = cfg->next_vreg;
2936 }
2937
2938 static const int
2939 branch_cc_table [] = {
2940         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2941         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2942         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2943 };
2944
2945 /* Maps CMP_... constants to X86_CC_... constants */
2946 static const int
2947 cc_table [] = {
2948         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2949         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2950 };
2951
2952 static const int
2953 cc_signed_table [] = {
2954         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2955         FALSE, FALSE, FALSE, FALSE
2956 };
2957
2958 /*#include "cprop.c"*/
2959
2960 static unsigned char*
2961 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2962 {
2963         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2964
2965         if (size == 1)
2966                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2967         else if (size == 2)
2968                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2969         return code;
2970 }
2971
2972 static unsigned char*
2973 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2974 {
2975         int sreg = tree->sreg1;
2976         int need_touch = FALSE;
2977
2978 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2979         if (!tree->flags & MONO_INST_INIT)
2980                 need_touch = TRUE;
2981 #endif
2982
2983         if (need_touch) {
2984                 guint8* br[5];
2985
2986                 /*
2987                  * Under Windows:
2988                  * If requested stack size is larger than one page,
2989                  * perform stack-touch operation
2990                  */
2991                 /*
2992                  * Generate stack probe code.
2993                  * Under Windows, it is necessary to allocate one page at a time,
2994                  * "touching" stack after each successful sub-allocation. This is
2995                  * because of the way stack growth is implemented - there is a
2996                  * guard page before the lowest stack page that is currently commited.
2997                  * Stack normally grows sequentially so OS traps access to the
2998                  * guard page and commits more pages when needed.
2999                  */
3000                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3001                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3002
3003                 br[2] = code; /* loop */
3004                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3005                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3006                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3007                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3008                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3009                 amd64_patch (br[3], br[2]);
3010                 amd64_test_reg_reg (code, sreg, sreg);
3011                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3012                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3013
3014                 br[1] = code; x86_jump8 (code, 0);
3015
3016                 amd64_patch (br[0], code);
3017                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3018                 amd64_patch (br[1], code);
3019                 amd64_patch (br[4], code);
3020         }
3021         else
3022                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3023
3024         if (tree->flags & MONO_INST_INIT) {
3025                 int offset = 0;
3026                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3027                         amd64_push_reg (code, AMD64_RAX);
3028                         offset += 8;
3029                 }
3030                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3031                         amd64_push_reg (code, AMD64_RCX);
3032                         offset += 8;
3033                 }
3034                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3035                         amd64_push_reg (code, AMD64_RDI);
3036                         offset += 8;
3037                 }
3038
3039                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3040                 if (sreg != AMD64_RCX)
3041                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3042                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3043
3044                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3045                 if (cfg->param_area && cfg->arch.no_pushes)
3046                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3047                 amd64_cld (code);
3048                 amd64_prefix (code, X86_REP_PREFIX);
3049                 amd64_stosl (code);
3050
3051                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3052                         amd64_pop_reg (code, AMD64_RDI);
3053                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3054                         amd64_pop_reg (code, AMD64_RCX);
3055                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3056                         amd64_pop_reg (code, AMD64_RAX);
3057         }
3058         return code;
3059 }
3060
3061 static guint8*
3062 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3063 {
3064         CallInfo *cinfo;
3065         guint32 quad;
3066
3067         /* Move return value to the target register */
3068         /* FIXME: do this in the local reg allocator */
3069         switch (ins->opcode) {
3070         case OP_CALL:
3071         case OP_CALL_REG:
3072         case OP_CALL_MEMBASE:
3073         case OP_LCALL:
3074         case OP_LCALL_REG:
3075         case OP_LCALL_MEMBASE:
3076                 g_assert (ins->dreg == AMD64_RAX);
3077                 break;
3078         case OP_FCALL:
3079         case OP_FCALL_REG:
3080         case OP_FCALL_MEMBASE:
3081                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3082                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3083                 }
3084                 else {
3085                         if (ins->dreg != AMD64_XMM0)
3086                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3087                 }
3088                 break;
3089         case OP_VCALL:
3090         case OP_VCALL_REG:
3091         case OP_VCALL_MEMBASE:
3092         case OP_VCALL2:
3093         case OP_VCALL2_REG:
3094         case OP_VCALL2_MEMBASE:
3095                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3096                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3097                         MonoInst *loc = cfg->arch.vret_addr_loc;
3098
3099                         /* Load the destination address */
3100                         g_assert (loc->opcode == OP_REGOFFSET);
3101                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3102
3103                         for (quad = 0; quad < 2; quad ++) {
3104                                 switch (cinfo->ret.pair_storage [quad]) {
3105                                 case ArgInIReg:
3106                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3107                                         break;
3108                                 case ArgInFloatSSEReg:
3109                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3110                                         break;
3111                                 case ArgInDoubleSSEReg:
3112                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3113                                         break;
3114                                 case ArgNone:
3115                                         break;
3116                                 default:
3117                                         NOT_IMPLEMENTED;
3118                                 }
3119                         }
3120                 }
3121                 break;
3122         }
3123
3124         return code;
3125 }
3126
3127 #endif /* DISABLE_JIT */
3128
3129 /*
3130  * mono_amd64_emit_tls_get:
3131  * @code: buffer to store code to
3132  * @dreg: hard register where to place the result
3133  * @tls_offset: offset info
3134  *
3135  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3136  * the dreg register the item in the thread local storage identified
3137  * by tls_offset.
3138  *
3139  * Returns: a pointer to the end of the stored code
3140  */
3141 guint8*
3142 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3143 {
3144 #ifdef HOST_WIN32
3145         g_assert (tls_offset < 64);
3146         x86_prefix (code, X86_GS_PREFIX);
3147         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3148 #else
3149         if (optimize_for_xen) {
3150                 x86_prefix (code, X86_FS_PREFIX);
3151                 amd64_mov_reg_mem (code, dreg, 0, 8);
3152                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3153         } else {
3154                 x86_prefix (code, X86_FS_PREFIX);
3155                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3156         }
3157 #endif
3158         return code;
3159 }
3160
3161 #define REAL_PRINT_REG(text,reg) \
3162 mono_assert (reg >= 0); \
3163 amd64_push_reg (code, AMD64_RAX); \
3164 amd64_push_reg (code, AMD64_RDX); \
3165 amd64_push_reg (code, AMD64_RCX); \
3166 amd64_push_reg (code, reg); \
3167 amd64_push_imm (code, reg); \
3168 amd64_push_imm (code, text " %d %p\n"); \
3169 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3170 amd64_call_reg (code, AMD64_RAX); \
3171 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3172 amd64_pop_reg (code, AMD64_RCX); \
3173 amd64_pop_reg (code, AMD64_RDX); \
3174 amd64_pop_reg (code, AMD64_RAX);
3175
3176 /* benchmark and set based on cpu */
3177 #define LOOP_ALIGNMENT 8
3178 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3179
3180 #ifndef DISABLE_JIT
3181
3182 void
3183 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3184 {
3185         MonoInst *ins;
3186         MonoCallInst *call;
3187         guint offset;
3188         guint8 *code = cfg->native_code + cfg->code_len;
3189         MonoInst *last_ins = NULL;
3190         guint last_offset = 0;
3191         int max_len;
3192
3193         /* Fix max_offset estimate for each successor bb */
3194         if (cfg->opt & MONO_OPT_BRANCH) {
3195                 int current_offset = cfg->code_len;
3196                 MonoBasicBlock *current_bb;
3197                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3198                         current_bb->max_offset = current_offset;
3199                         current_offset += current_bb->max_length;
3200                 }
3201         }
3202
3203         if (cfg->opt & MONO_OPT_LOOP) {
3204                 int pad, align = LOOP_ALIGNMENT;
3205                 /* set alignment depending on cpu */
3206                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3207                         pad = align - pad;
3208                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3209                         amd64_padding (code, pad);
3210                         cfg->code_len += pad;
3211                         bb->native_offset = cfg->code_len;
3212                 }
3213         }
3214
3215         if (cfg->verbose_level > 2)
3216                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3217
3218         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3219                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3220                 g_assert (!cfg->compile_aot);
3221
3222                 cov->data [bb->dfn].cil_code = bb->cil_code;
3223                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3224                 /* this is not thread save, but good enough */
3225                 amd64_inc_membase (code, AMD64_R11, 0);
3226         }
3227
3228         offset = code - cfg->native_code;
3229
3230         mono_debug_open_block (cfg, bb, offset);
3231
3232     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3233                 x86_breakpoint (code);
3234
3235         MONO_BB_FOR_EACH_INS (bb, ins) {
3236                 offset = code - cfg->native_code;
3237
3238                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3239
3240                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3241                         cfg->code_size *= 2;
3242                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3243                         code = cfg->native_code + offset;
3244                         mono_jit_stats.code_reallocs++;
3245                 }
3246
3247                 if (cfg->debug_info)
3248                         mono_debug_record_line_number (cfg, ins, offset);
3249
3250                 switch (ins->opcode) {
3251                 case OP_BIGMUL:
3252                         amd64_mul_reg (code, ins->sreg2, TRUE);
3253                         break;
3254                 case OP_BIGMUL_UN:
3255                         amd64_mul_reg (code, ins->sreg2, FALSE);
3256                         break;
3257                 case OP_X86_SETEQ_MEMBASE:
3258                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3259                         break;
3260                 case OP_STOREI1_MEMBASE_IMM:
3261                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3262                         break;
3263                 case OP_STOREI2_MEMBASE_IMM:
3264                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3265                         break;
3266                 case OP_STOREI4_MEMBASE_IMM:
3267                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3268                         break;
3269                 case OP_STOREI1_MEMBASE_REG:
3270                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3271                         break;
3272                 case OP_STOREI2_MEMBASE_REG:
3273                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3274                         break;
3275                 case OP_STORE_MEMBASE_REG:
3276                 case OP_STOREI8_MEMBASE_REG:
3277                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3278                         break;
3279                 case OP_STOREI4_MEMBASE_REG:
3280                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3281                         break;
3282                 case OP_STORE_MEMBASE_IMM:
3283                 case OP_STOREI8_MEMBASE_IMM:
3284                         g_assert (amd64_is_imm32 (ins->inst_imm));
3285                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3286                         break;
3287                 case OP_LOAD_MEM:
3288                 case OP_LOADI8_MEM:
3289                         // FIXME: Decompose this earlier
3290                         if (amd64_is_imm32 (ins->inst_imm))
3291                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3292                         else {
3293                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3294                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3295                         }
3296                         break;
3297                 case OP_LOADI4_MEM:
3298                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3299                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3300                         break;
3301                 case OP_LOADU4_MEM:
3302                         // FIXME: Decompose this earlier
3303                         if (amd64_is_imm32 (ins->inst_imm))
3304                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3305                         else {
3306                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3307                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3308                         }
3309                         break;
3310                 case OP_LOADU1_MEM:
3311                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3312                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3313                         break;
3314                 case OP_LOADU2_MEM:
3315                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3316                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3317                         break;
3318                 case OP_LOAD_MEMBASE:
3319                 case OP_LOADI8_MEMBASE:
3320                         g_assert (amd64_is_imm32 (ins->inst_offset));
3321                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3322                         break;
3323                 case OP_LOADI4_MEMBASE:
3324                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3325                         break;
3326                 case OP_LOADU4_MEMBASE:
3327                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3328                         break;
3329                 case OP_LOADU1_MEMBASE:
3330                         /* The cpu zero extends the result into 64 bits */
3331                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3332                         break;
3333                 case OP_LOADI1_MEMBASE:
3334                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3335                         break;
3336                 case OP_LOADU2_MEMBASE:
3337                         /* The cpu zero extends the result into 64 bits */
3338                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3339                         break;
3340                 case OP_LOADI2_MEMBASE:
3341                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3342                         break;
3343                 case OP_AMD64_LOADI8_MEMINDEX:
3344                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3345                         break;
3346                 case OP_LCONV_TO_I1:
3347                 case OP_ICONV_TO_I1:
3348                 case OP_SEXT_I1:
3349                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3350                         break;
3351                 case OP_LCONV_TO_I2:
3352                 case OP_ICONV_TO_I2:
3353                 case OP_SEXT_I2:
3354                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3355                         break;
3356                 case OP_LCONV_TO_U1:
3357                 case OP_ICONV_TO_U1:
3358                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3359                         break;
3360                 case OP_LCONV_TO_U2:
3361                 case OP_ICONV_TO_U2:
3362                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3363                         break;
3364                 case OP_ZEXT_I4:
3365                         /* Clean out the upper word */
3366                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3367                         break;
3368                 case OP_SEXT_I4:
3369                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3370                         break;
3371                 case OP_COMPARE:
3372                 case OP_LCOMPARE:
3373                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3374                         break;
3375                 case OP_COMPARE_IMM:
3376                 case OP_LCOMPARE_IMM:
3377                         g_assert (amd64_is_imm32 (ins->inst_imm));
3378                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3379                         break;
3380                 case OP_X86_COMPARE_REG_MEMBASE:
3381                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3382                         break;
3383                 case OP_X86_TEST_NULL:
3384                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3385                         break;
3386                 case OP_AMD64_TEST_NULL:
3387                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3388                         break;
3389
3390                 case OP_X86_ADD_REG_MEMBASE:
3391                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3392                         break;
3393                 case OP_X86_SUB_REG_MEMBASE:
3394                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3395                         break;
3396                 case OP_X86_AND_REG_MEMBASE:
3397                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3398                         break;
3399                 case OP_X86_OR_REG_MEMBASE:
3400                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3401                         break;
3402                 case OP_X86_XOR_REG_MEMBASE:
3403                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3404                         break;
3405
3406                 case OP_X86_ADD_MEMBASE_IMM:
3407                         /* FIXME: Make a 64 version too */
3408                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3409                         break;
3410                 case OP_X86_SUB_MEMBASE_IMM:
3411                         g_assert (amd64_is_imm32 (ins->inst_imm));
3412                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3413                         break;
3414                 case OP_X86_AND_MEMBASE_IMM:
3415                         g_assert (amd64_is_imm32 (ins->inst_imm));
3416                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3417                         break;
3418                 case OP_X86_OR_MEMBASE_IMM:
3419                         g_assert (amd64_is_imm32 (ins->inst_imm));
3420                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3421                         break;
3422                 case OP_X86_XOR_MEMBASE_IMM:
3423                         g_assert (amd64_is_imm32 (ins->inst_imm));
3424                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3425                         break;
3426                 case OP_X86_ADD_MEMBASE_REG:
3427                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3428                         break;
3429                 case OP_X86_SUB_MEMBASE_REG:
3430                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3431                         break;
3432                 case OP_X86_AND_MEMBASE_REG:
3433                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3434                         break;
3435                 case OP_X86_OR_MEMBASE_REG:
3436                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3437                         break;
3438                 case OP_X86_XOR_MEMBASE_REG:
3439                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3440                         break;
3441                 case OP_X86_INC_MEMBASE:
3442                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3443                         break;
3444                 case OP_X86_INC_REG:
3445                         amd64_inc_reg_size (code, ins->dreg, 4);
3446                         break;
3447                 case OP_X86_DEC_MEMBASE:
3448                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3449                         break;
3450                 case OP_X86_DEC_REG:
3451                         amd64_dec_reg_size (code, ins->dreg, 4);
3452                         break;
3453                 case OP_X86_MUL_REG_MEMBASE:
3454                 case OP_X86_MUL_MEMBASE_REG:
3455                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3456                         break;
3457                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3458                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3459                         break;
3460                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3461                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3462                         break;
3463                 case OP_AMD64_COMPARE_MEMBASE_REG:
3464                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3465                         break;
3466                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3467                         g_assert (amd64_is_imm32 (ins->inst_imm));
3468                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3469                         break;
3470                 case OP_X86_COMPARE_MEMBASE8_IMM:
3471                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3472                         break;
3473                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3474                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3475                         break;
3476                 case OP_AMD64_COMPARE_REG_MEMBASE:
3477                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3478                         break;
3479
3480                 case OP_AMD64_ADD_REG_MEMBASE:
3481                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3482                         break;
3483                 case OP_AMD64_SUB_REG_MEMBASE:
3484                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3485                         break;
3486                 case OP_AMD64_AND_REG_MEMBASE:
3487                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3488                         break;
3489                 case OP_AMD64_OR_REG_MEMBASE:
3490                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3491                         break;
3492                 case OP_AMD64_XOR_REG_MEMBASE:
3493                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3494                         break;
3495
3496                 case OP_AMD64_ADD_MEMBASE_REG:
3497                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3498                         break;
3499                 case OP_AMD64_SUB_MEMBASE_REG:
3500                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3501                         break;
3502                 case OP_AMD64_AND_MEMBASE_REG:
3503                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3504                         break;
3505                 case OP_AMD64_OR_MEMBASE_REG:
3506                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3507                         break;
3508                 case OP_AMD64_XOR_MEMBASE_REG:
3509                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3510                         break;
3511
3512                 case OP_AMD64_ADD_MEMBASE_IMM:
3513                         g_assert (amd64_is_imm32 (ins->inst_imm));
3514                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3515                         break;
3516                 case OP_AMD64_SUB_MEMBASE_IMM:
3517                         g_assert (amd64_is_imm32 (ins->inst_imm));
3518                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3519                         break;
3520                 case OP_AMD64_AND_MEMBASE_IMM:
3521                         g_assert (amd64_is_imm32 (ins->inst_imm));
3522                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3523                         break;
3524                 case OP_AMD64_OR_MEMBASE_IMM:
3525                         g_assert (amd64_is_imm32 (ins->inst_imm));
3526                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3527                         break;
3528                 case OP_AMD64_XOR_MEMBASE_IMM:
3529                         g_assert (amd64_is_imm32 (ins->inst_imm));
3530                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3531                         break;
3532
3533                 case OP_BREAK:
3534                         amd64_breakpoint (code);
3535                         break;
3536                 case OP_RELAXED_NOP:
3537                         x86_prefix (code, X86_REP_PREFIX);
3538                         x86_nop (code);
3539                         break;
3540                 case OP_HARD_NOP:
3541                         x86_nop (code);
3542                         break;
3543                 case OP_NOP:
3544                 case OP_DUMMY_USE:
3545                 case OP_DUMMY_STORE:
3546                 case OP_NOT_REACHED:
3547                 case OP_NOT_NULL:
3548                         break;
3549                 case OP_SEQ_POINT: {
3550                         int i;
3551
3552                         if (cfg->compile_aot)
3553                                 NOT_IMPLEMENTED;
3554
3555                         /*
3556                          * Read from the single stepping trigger page. This will cause a
3557                          * SIGSEGV when single stepping is enabled.
3558                          * We do this _before_ the breakpoint, so single stepping after
3559                          * a breakpoint is hit will step to the next IL offset.
3560                          */
3561                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3562                                 if (((guint64)ss_trigger_page >> 32) == 0)
3563                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3564                                 else {
3565                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3566
3567                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3568                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3569                                 }
3570                         }
3571
3572                         /*
3573                          * This is the address which is saved in seq points,
3574                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3575                          * from the address of the instruction causing the fault.
3576                          */
3577                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3578
3579                         /*
3580                          * A placeholder for a possible breakpoint inserted by
3581                          * mono_arch_set_breakpoint ().
3582                          */
3583                         for (i = 0; i < breakpoint_size; ++i)
3584                                 x86_nop (code);
3585                         break;
3586                 }
3587                 case OP_ADDCC:
3588                 case OP_LADD:
3589                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3590                         break;
3591                 case OP_ADC:
3592                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3593                         break;
3594                 case OP_ADD_IMM:
3595                 case OP_LADD_IMM:
3596                         g_assert (amd64_is_imm32 (ins->inst_imm));
3597                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3598                         break;
3599                 case OP_ADC_IMM:
3600                         g_assert (amd64_is_imm32 (ins->inst_imm));
3601                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3602                         break;
3603                 case OP_SUBCC:
3604                 case OP_LSUB:
3605                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3606                         break;
3607                 case OP_SBB:
3608                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3609                         break;
3610                 case OP_SUB_IMM:
3611                 case OP_LSUB_IMM:
3612                         g_assert (amd64_is_imm32 (ins->inst_imm));
3613                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3614                         break;
3615                 case OP_SBB_IMM:
3616                         g_assert (amd64_is_imm32 (ins->inst_imm));
3617                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3618                         break;
3619                 case OP_LAND:
3620                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3621                         break;
3622                 case OP_AND_IMM:
3623                 case OP_LAND_IMM:
3624                         g_assert (amd64_is_imm32 (ins->inst_imm));
3625                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3626                         break;
3627                 case OP_LMUL:
3628                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3629                         break;
3630                 case OP_MUL_IMM:
3631                 case OP_LMUL_IMM:
3632                 case OP_IMUL_IMM: {
3633                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3634
3635                         switch (ins->inst_imm) {
3636                         case 2:
3637                                 /* MOV r1, r2 */
3638                                 /* ADD r1, r1 */
3639                                 if (ins->dreg != ins->sreg1)
3640                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3641                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3642                                 break;
3643                         case 3:
3644                                 /* LEA r1, [r2 + r2*2] */
3645                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3646                                 break;
3647                         case 5:
3648                                 /* LEA r1, [r2 + r2*4] */
3649                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3650                                 break;
3651                         case 6:
3652                                 /* LEA r1, [r2 + r2*2] */
3653                                 /* ADD r1, r1          */
3654                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3655                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3656                                 break;
3657                         case 9:
3658                                 /* LEA r1, [r2 + r2*8] */
3659                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3660                                 break;
3661                         case 10:
3662                                 /* LEA r1, [r2 + r2*4] */
3663                                 /* ADD r1, r1          */
3664                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3665                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3666                                 break;
3667                         case 12:
3668                                 /* LEA r1, [r2 + r2*2] */
3669                                 /* SHL r1, 2           */
3670                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3671                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3672                                 break;
3673                         case 25:
3674                                 /* LEA r1, [r2 + r2*4] */
3675                                 /* LEA r1, [r1 + r1*4] */
3676                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3677                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3678                                 break;
3679                         case 100:
3680                                 /* LEA r1, [r2 + r2*4] */
3681                                 /* SHL r1, 2           */
3682                                 /* LEA r1, [r1 + r1*4] */
3683                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3684                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3685                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3686                                 break;
3687                         default:
3688                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3689                                 break;
3690                         }
3691                         break;
3692                 }
3693                 case OP_LDIV:
3694                 case OP_LREM:
3695                         /* Regalloc magic makes the div/rem cases the same */
3696                         if (ins->sreg2 == AMD64_RDX) {
3697                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3698                                 amd64_cdq (code);
3699                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3700                         } else {
3701                                 amd64_cdq (code);
3702                                 amd64_div_reg (code, ins->sreg2, TRUE);
3703                         }
3704                         break;
3705                 case OP_LDIV_UN:
3706                 case OP_LREM_UN:
3707                         if (ins->sreg2 == AMD64_RDX) {
3708                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3709                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3710                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3711                         } else {
3712                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3713                                 amd64_div_reg (code, ins->sreg2, FALSE);
3714                         }
3715                         break;
3716                 case OP_IDIV:
3717                 case OP_IREM:
3718                         if (ins->sreg2 == AMD64_RDX) {
3719                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3720                                 amd64_cdq_size (code, 4);
3721                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3722                         } else {
3723                                 amd64_cdq_size (code, 4);
3724                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3725                         }
3726                         break;
3727                 case OP_IDIV_UN:
3728                 case OP_IREM_UN:
3729                         if (ins->sreg2 == AMD64_RDX) {
3730                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3731                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3732                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3733                         } else {
3734                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3735                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3736                         }
3737                         break;
3738                 case OP_IREM_IMM: {
3739                         int power = mono_is_power_of_two (ins->inst_imm);
3740
3741                         g_assert (ins->sreg1 == X86_EAX);
3742                         g_assert (ins->dreg == X86_EAX);
3743                         g_assert (power >= 0);
3744
3745                         if (power == 0) {
3746                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3747                                 break;
3748                         }
3749
3750                         /* Based on gcc code */
3751
3752                         /* Add compensation for negative dividents */
3753                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3754                         if (power > 1)
3755                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3756                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3757                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3758                         /* Compute remainder */
3759                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3760                         /* Remove compensation */
3761                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3762                         break;
3763                 }
3764                 case OP_LMUL_OVF:
3765                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3766                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3767                         break;
3768                 case OP_LOR:
3769                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3770                         break;
3771                 case OP_OR_IMM:
3772                 case OP_LOR_IMM:
3773                         g_assert (amd64_is_imm32 (ins->inst_imm));
3774                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3775                         break;
3776                 case OP_LXOR:
3777                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3778                         break;
3779                 case OP_XOR_IMM:
3780                 case OP_LXOR_IMM:
3781                         g_assert (amd64_is_imm32 (ins->inst_imm));
3782                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3783                         break;
3784                 case OP_LSHL:
3785                         g_assert (ins->sreg2 == AMD64_RCX);
3786                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3787                         break;
3788                 case OP_LSHR:
3789                         g_assert (ins->sreg2 == AMD64_RCX);
3790                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3791                         break;
3792                 case OP_SHR_IMM:
3793                         g_assert (amd64_is_imm32 (ins->inst_imm));
3794                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3795                         break;
3796                 case OP_LSHR_IMM:
3797                         g_assert (amd64_is_imm32 (ins->inst_imm));
3798                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3799                         break;
3800                 case OP_SHR_UN_IMM:
3801                         g_assert (amd64_is_imm32 (ins->inst_imm));
3802                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3803                         break;
3804                 case OP_LSHR_UN_IMM:
3805                         g_assert (amd64_is_imm32 (ins->inst_imm));
3806                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3807                         break;
3808                 case OP_LSHR_UN:
3809                         g_assert (ins->sreg2 == AMD64_RCX);
3810                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3811                         break;
3812                 case OP_SHL_IMM:
3813                         g_assert (amd64_is_imm32 (ins->inst_imm));
3814                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3815                         break;
3816                 case OP_LSHL_IMM:
3817                         g_assert (amd64_is_imm32 (ins->inst_imm));
3818                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3819                         break;
3820
3821                 case OP_IADDCC:
3822                 case OP_IADD:
3823                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3824                         break;
3825                 case OP_IADC:
3826                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3827                         break;
3828                 case OP_IADD_IMM:
3829                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3830                         break;
3831                 case OP_IADC_IMM:
3832                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3833                         break;
3834                 case OP_ISUBCC:
3835                 case OP_ISUB:
3836                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3837                         break;
3838                 case OP_ISBB:
3839                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3840                         break;
3841                 case OP_ISUB_IMM:
3842                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3843                         break;
3844                 case OP_ISBB_IMM:
3845                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3846                         break;
3847                 case OP_IAND:
3848                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3849                         break;
3850                 case OP_IAND_IMM:
3851                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3852                         break;
3853                 case OP_IOR:
3854                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3855                         break;
3856                 case OP_IOR_IMM:
3857                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3858                         break;
3859                 case OP_IXOR:
3860                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3861                         break;
3862                 case OP_IXOR_IMM:
3863                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3864                         break;
3865                 case OP_INEG:
3866                         amd64_neg_reg_size (code, ins->sreg1, 4);
3867                         break;
3868                 case OP_INOT:
3869                         amd64_not_reg_size (code, ins->sreg1, 4);
3870                         break;
3871                 case OP_ISHL:
3872                         g_assert (ins->sreg2 == AMD64_RCX);
3873                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3874                         break;
3875                 case OP_ISHR:
3876                         g_assert (ins->sreg2 == AMD64_RCX);
3877                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3878                         break;
3879                 case OP_ISHR_IMM:
3880                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3881                         break;
3882                 case OP_ISHR_UN_IMM:
3883                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3884                         break;
3885                 case OP_ISHR_UN:
3886                         g_assert (ins->sreg2 == AMD64_RCX);
3887                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3888                         break;
3889                 case OP_ISHL_IMM:
3890                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3891                         break;
3892                 case OP_IMUL:
3893                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3894                         break;
3895                 case OP_IMUL_OVF:
3896                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3897                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3898                         break;
3899                 case OP_IMUL_OVF_UN:
3900                 case OP_LMUL_OVF_UN: {
3901                         /* the mul operation and the exception check should most likely be split */
3902                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3903                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3904                         /*g_assert (ins->sreg2 == X86_EAX);
3905                         g_assert (ins->dreg == X86_EAX);*/
3906                         if (ins->sreg2 == X86_EAX) {
3907                                 non_eax_reg = ins->sreg1;
3908                         } else if (ins->sreg1 == X86_EAX) {
3909                                 non_eax_reg = ins->sreg2;
3910                         } else {
3911                                 /* no need to save since we're going to store to it anyway */
3912                                 if (ins->dreg != X86_EAX) {
3913                                         saved_eax = TRUE;
3914                                         amd64_push_reg (code, X86_EAX);
3915                                 }
3916                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3917                                 non_eax_reg = ins->sreg2;
3918                         }
3919                         if (ins->dreg == X86_EDX) {
3920                                 if (!saved_eax) {
3921                                         saved_eax = TRUE;
3922                                         amd64_push_reg (code, X86_EAX);
3923                                 }
3924                         } else {
3925                                 saved_edx = TRUE;
3926                                 amd64_push_reg (code, X86_EDX);
3927                         }
3928                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3929                         /* save before the check since pop and mov don't change the flags */
3930                         if (ins->dreg != X86_EAX)
3931                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3932                         if (saved_edx)
3933                                 amd64_pop_reg (code, X86_EDX);
3934                         if (saved_eax)
3935                                 amd64_pop_reg (code, X86_EAX);
3936                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3937                         break;
3938                 }
3939                 case OP_ICOMPARE:
3940                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3941                         break;
3942                 case OP_ICOMPARE_IMM:
3943                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3944                         break;
3945                 case OP_IBEQ:
3946                 case OP_IBLT:
3947                 case OP_IBGT:
3948                 case OP_IBGE:
3949                 case OP_IBLE:
3950                 case OP_LBEQ:
3951                 case OP_LBLT:
3952                 case OP_LBGT:
3953                 case OP_LBGE:
3954                 case OP_LBLE:
3955                 case OP_IBNE_UN:
3956                 case OP_IBLT_UN:
3957                 case OP_IBGT_UN:
3958                 case OP_IBGE_UN:
3959                 case OP_IBLE_UN:
3960                 case OP_LBNE_UN:
3961                 case OP_LBLT_UN:
3962                 case OP_LBGT_UN:
3963                 case OP_LBGE_UN:
3964                 case OP_LBLE_UN:
3965                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3966                         break;
3967
3968                 case OP_CMOV_IEQ:
3969                 case OP_CMOV_IGE:
3970                 case OP_CMOV_IGT:
3971                 case OP_CMOV_ILE:
3972                 case OP_CMOV_ILT:
3973                 case OP_CMOV_INE_UN:
3974                 case OP_CMOV_IGE_UN:
3975                 case OP_CMOV_IGT_UN:
3976                 case OP_CMOV_ILE_UN:
3977                 case OP_CMOV_ILT_UN:
3978                 case OP_CMOV_LEQ:
3979                 case OP_CMOV_LGE:
3980                 case OP_CMOV_LGT:
3981                 case OP_CMOV_LLE:
3982                 case OP_CMOV_LLT:
3983                 case OP_CMOV_LNE_UN:
3984                 case OP_CMOV_LGE_UN:
3985                 case OP_CMOV_LGT_UN:
3986                 case OP_CMOV_LLE_UN:
3987                 case OP_CMOV_LLT_UN:
3988                         g_assert (ins->dreg == ins->sreg1);
3989                         /* This needs to operate on 64 bit values */
3990                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3991                         break;
3992
3993                 case OP_LNOT:
3994                         amd64_not_reg (code, ins->sreg1);
3995                         break;
3996                 case OP_LNEG:
3997                         amd64_neg_reg (code, ins->sreg1);
3998                         break;
3999
4000                 case OP_ICONST:
4001                 case OP_I8CONST:
4002                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4003                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4004                         else
4005                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4006                         break;
4007                 case OP_AOTCONST:
4008                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4009                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4010                         break;
4011                 case OP_JUMP_TABLE:
4012                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4013                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4014                         break;
4015                 case OP_MOVE:
4016                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4017                         break;
4018                 case OP_AMD64_SET_XMMREG_R4: {
4019                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4020                         break;
4021                 }
4022                 case OP_AMD64_SET_XMMREG_R8: {
4023                         if (ins->dreg != ins->sreg1)
4024                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4025                         break;
4026                 }
4027                 case OP_TAILCALL: {
4028                         /*
4029                          * Note: this 'frame destruction' logic is useful for tail calls, too.
4030                          * Keep in sync with the code in emit_epilog.
4031                          */
4032                         int pos = 0, i;
4033
4034                         /* FIXME: no tracing support... */
4035                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4036                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4037
4038                         g_assert (!cfg->method->save_lmf);
4039
4040                         if (cfg->arch.omit_fp) {
4041                                 guint32 save_offset = 0;
4042                                 /* Pop callee-saved registers */
4043                                 for (i = 0; i < AMD64_NREG; ++i)
4044                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4045                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4046                                                 save_offset += 8;
4047                                         }
4048                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4049                         }
4050                         else {
4051                                 for (i = 0; i < AMD64_NREG; ++i)
4052                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4053                                                 pos -= sizeof (gpointer);
4054
4055                                 if (pos)
4056                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4057
4058                                 /* Pop registers in reverse order */
4059                                 for (i = AMD64_NREG - 1; i > 0; --i)
4060                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4061                                                 amd64_pop_reg (code, i);
4062                                         }
4063
4064                                 amd64_leave (code);
4065                         }
4066
4067                         offset = code - cfg->native_code;
4068                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4069                         if (cfg->compile_aot)
4070                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4071                         else
4072                                 amd64_set_reg_template (code, AMD64_R11);
4073                         amd64_jump_reg (code, AMD64_R11);
4074                         break;
4075                 }
4076                 case OP_CHECK_THIS:
4077                         /* ensure ins->sreg1 is not NULL */
4078                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4079                         break;
4080                 case OP_ARGLIST: {
4081                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4082                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4083                         break;
4084                 }
4085                 case OP_CALL:
4086                 case OP_FCALL:
4087                 case OP_LCALL:
4088                 case OP_VCALL:
4089                 case OP_VCALL2:
4090                 case OP_VOIDCALL:
4091                         call = (MonoCallInst*)ins;
4092                         /*
4093                          * The AMD64 ABI forces callers to know about varargs.
4094                          */
4095                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4096                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4097                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4098                                 /*
4099                                  * Since the unmanaged calling convention doesn't contain a
4100                                  * 'vararg' entry, we have to treat every pinvoke call as a
4101                                  * potential vararg call.
4102                                  */
4103                                 guint32 nregs, i;
4104                                 nregs = 0;
4105                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4106                                         if (call->used_fregs & (1 << i))
4107                                                 nregs ++;
4108                                 if (!nregs)
4109                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4110                                 else
4111                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4112                         }
4113
4114                         if (ins->flags & MONO_INST_HAS_METHOD)
4115                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4116                         else
4117                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4118                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4119                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4120                         code = emit_move_return_value (cfg, ins, code);
4121                         break;
4122                 case OP_FCALL_REG:
4123                 case OP_LCALL_REG:
4124                 case OP_VCALL_REG:
4125                 case OP_VCALL2_REG:
4126                 case OP_VOIDCALL_REG:
4127                 case OP_CALL_REG:
4128                         call = (MonoCallInst*)ins;
4129
4130                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4131                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4132                                 ins->sreg1 = AMD64_R11;
4133                         }
4134
4135                         /*
4136                          * The AMD64 ABI forces callers to know about varargs.
4137                          */
4138                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4139                                 if (ins->sreg1 == AMD64_RAX) {
4140                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4141                                         ins->sreg1 = AMD64_R11;
4142                                 }
4143                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4144                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4145                                 /*
4146                                  * Since the unmanaged calling convention doesn't contain a
4147                                  * 'vararg' entry, we have to treat every pinvoke call as a
4148                                  * potential vararg call.
4149                                  */
4150                                 guint32 nregs, i;
4151                                 nregs = 0;
4152                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4153                                         if (call->used_fregs & (1 << i))
4154                                                 nregs ++;
4155                                 if (ins->sreg1 == AMD64_RAX) {
4156                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4157                                         ins->sreg1 = AMD64_R11;
4158                                 }
4159                                 if (!nregs)
4160                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4161                                 else
4162                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4163                         }
4164
4165                         amd64_call_reg (code, ins->sreg1);
4166                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4167                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4168                         code = emit_move_return_value (cfg, ins, code);
4169                         break;
4170                 case OP_FCALL_MEMBASE:
4171                 case OP_LCALL_MEMBASE:
4172                 case OP_VCALL_MEMBASE:
4173                 case OP_VCALL2_MEMBASE:
4174                 case OP_VOIDCALL_MEMBASE:
4175                 case OP_CALL_MEMBASE:
4176                         call = (MonoCallInst*)ins;
4177
4178                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4179                                 /*
4180                                  * Can't use R11 because it is clobbered by the trampoline
4181                                  * code, and the reg value is needed by get_vcall_slot_addr.
4182                                  */
4183                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4184                                 ins->sreg1 = AMD64_RAX;
4185                         }
4186
4187                         /*
4188                          * Emit a few nops to simplify get_vcall_slot ().
4189                          */
4190                         amd64_nop (code);
4191                         amd64_nop (code);
4192                         amd64_nop (code);
4193
4194                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4195                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4196                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4197                         code = emit_move_return_value (cfg, ins, code);
4198                         break;
4199                 case OP_DYN_CALL: {
4200                         int i;
4201                         MonoInst *var = cfg->dyn_call_var;
4202
4203                         g_assert (var->opcode == OP_REGOFFSET);
4204
4205                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4206                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4207                         /* r10 = ftn */
4208                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4209
4210                         /* Save args buffer */
4211                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4212
4213                         /* Set argument registers */
4214                         for (i = 0; i < PARAM_REGS; ++i)
4215                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4216
4217                         /* Make the call */
4218                         amd64_call_reg (code, AMD64_R10);
4219
4220                         /* Save result */
4221                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4222                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4223                         break;
4224                 }
4225                 case OP_AMD64_SAVE_SP_TO_LMF:
4226                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4227                         break;
4228                 case OP_X86_PUSH:
4229                         g_assert (!cfg->arch.no_pushes);
4230                         amd64_push_reg (code, ins->sreg1);
4231                         break;
4232                 case OP_X86_PUSH_IMM:
4233                         g_assert (!cfg->arch.no_pushes);
4234                         g_assert (amd64_is_imm32 (ins->inst_imm));
4235                         amd64_push_imm (code, ins->inst_imm);
4236                         break;
4237                 case OP_X86_PUSH_MEMBASE:
4238                         g_assert (!cfg->arch.no_pushes);
4239                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4240                         break;
4241                 case OP_X86_PUSH_OBJ: {
4242                         int size = ALIGN_TO (ins->inst_imm, 8);
4243
4244                         g_assert (!cfg->arch.no_pushes);
4245
4246                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4247                         amd64_push_reg (code, AMD64_RDI);
4248                         amd64_push_reg (code, AMD64_RSI);
4249                         amd64_push_reg (code, AMD64_RCX);
4250                         if (ins->inst_offset)
4251                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4252                         else
4253                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4254                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4255                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4256                         amd64_cld (code);
4257                         amd64_prefix (code, X86_REP_PREFIX);
4258                         amd64_movsd (code);
4259                         amd64_pop_reg (code, AMD64_RCX);
4260                         amd64_pop_reg (code, AMD64_RSI);
4261                         amd64_pop_reg (code, AMD64_RDI);
4262                         break;
4263                 }
4264                 case OP_X86_LEA:
4265                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4266                         break;
4267                 case OP_X86_LEA_MEMBASE:
4268                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4269                         break;
4270                 case OP_X86_XCHG:
4271                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4272                         break;
4273                 case OP_LOCALLOC:
4274                         /* keep alignment */
4275                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4276                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4277                         code = mono_emit_stack_alloc (cfg, code, ins);
4278                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4279                         if (cfg->param_area && cfg->arch.no_pushes)
4280                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4281                         break;
4282                 case OP_LOCALLOC_IMM: {
4283                         guint32 size = ins->inst_imm;
4284                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4285
4286                         if (ins->flags & MONO_INST_INIT) {
4287                                 if (size < 64) {
4288                                         int i;
4289
4290                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4291                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4292
4293                                         for (i = 0; i < size; i += 8)
4294                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4295                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4296                                 } else {
4297                                         amd64_mov_reg_imm (code, ins->dreg, size);
4298                                         ins->sreg1 = ins->dreg;
4299
4300                                         code = mono_emit_stack_alloc (cfg, code, ins);
4301                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4302                                 }
4303                         } else {
4304                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4305                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4306                         }
4307                         if (cfg->param_area && cfg->arch.no_pushes)
4308                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4309                         break;
4310                 }
4311                 case OP_THROW: {
4312                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4313                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4314                                              (gpointer)"mono_arch_throw_exception", FALSE);
4315                         break;
4316                 }
4317                 case OP_RETHROW: {
4318                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4319                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4320                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4321                         break;
4322                 }
4323                 case OP_CALL_HANDLER:
4324                         /* Align stack */
4325                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4326                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4327                         amd64_call_imm (code, 0);
4328                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4329                         /* Restore stack alignment */
4330                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4331                         break;
4332                 case OP_START_HANDLER: {
4333                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4334                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4335
4336                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4337                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4338                                 cfg->param_area && cfg->arch.no_pushes) {
4339                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4340                         }
4341                         break;
4342                 }
4343                 case OP_ENDFINALLY: {
4344                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4345                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4346                         amd64_ret (code);
4347                         break;
4348                 }
4349                 case OP_ENDFILTER: {
4350                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4351                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4352                         /* The local allocator will put the result into RAX */
4353                         amd64_ret (code);
4354                         break;
4355                 }
4356
4357                 case OP_LABEL:
4358                         ins->inst_c0 = code - cfg->native_code;
4359                         break;
4360                 case OP_BR:
4361                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4362                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4363                         //break;
4364                                 if (ins->inst_target_bb->native_offset) {
4365                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4366                                 } else {
4367                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4368                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4369                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4370                                                 x86_jump8 (code, 0);
4371                                         else
4372                                                 x86_jump32 (code, 0);
4373                         }
4374                         break;
4375                 case OP_BR_REG:
4376                         amd64_jump_reg (code, ins->sreg1);
4377                         break;
4378                 case OP_CEQ:
4379                 case OP_LCEQ:
4380                 case OP_ICEQ:
4381                 case OP_CLT:
4382                 case OP_LCLT:
4383                 case OP_ICLT:
4384                 case OP_CGT:
4385                 case OP_ICGT:
4386                 case OP_LCGT:
4387                 case OP_CLT_UN:
4388                 case OP_LCLT_UN:
4389                 case OP_ICLT_UN:
4390                 case OP_CGT_UN:
4391                 case OP_LCGT_UN:
4392                 case OP_ICGT_UN:
4393                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4394                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4395                         break;
4396                 case OP_COND_EXC_EQ:
4397                 case OP_COND_EXC_NE_UN:
4398                 case OP_COND_EXC_LT:
4399                 case OP_COND_EXC_LT_UN:
4400                 case OP_COND_EXC_GT:
4401                 case OP_COND_EXC_GT_UN:
4402                 case OP_COND_EXC_GE:
4403                 case OP_COND_EXC_GE_UN:
4404                 case OP_COND_EXC_LE:
4405                 case OP_COND_EXC_LE_UN:
4406                 case OP_COND_EXC_IEQ:
4407                 case OP_COND_EXC_INE_UN:
4408                 case OP_COND_EXC_ILT:
4409                 case OP_COND_EXC_ILT_UN:
4410                 case OP_COND_EXC_IGT:
4411                 case OP_COND_EXC_IGT_UN:
4412                 case OP_COND_EXC_IGE:
4413                 case OP_COND_EXC_IGE_UN:
4414                 case OP_COND_EXC_ILE:
4415                 case OP_COND_EXC_ILE_UN:
4416                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4417                         break;
4418                 case OP_COND_EXC_OV:
4419                 case OP_COND_EXC_NO:
4420                 case OP_COND_EXC_C:
4421                 case OP_COND_EXC_NC:
4422                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4423                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4424                         break;
4425                 case OP_COND_EXC_IOV:
4426                 case OP_COND_EXC_INO:
4427                 case OP_COND_EXC_IC:
4428                 case OP_COND_EXC_INC:
4429                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4430                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4431                         break;
4432
4433                 /* floating point opcodes */
4434                 case OP_R8CONST: {
4435                         double d = *(double *)ins->inst_p0;
4436
4437                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4438                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4439                         }
4440                         else {
4441                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4442                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4443                         }
4444                         break;
4445                 }
4446                 case OP_R4CONST: {
4447                         float f = *(float *)ins->inst_p0;
4448
4449                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4450                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4451                         }
4452                         else {
4453                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4454                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4455                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4456                         }
4457                         break;
4458                 }
4459                 case OP_STORER8_MEMBASE_REG:
4460                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4461                         break;
4462                 case OP_LOADR8_MEMBASE:
4463                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4464                         break;
4465                 case OP_STORER4_MEMBASE_REG:
4466                         /* This requires a double->single conversion */
4467                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4468                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4469                         break;
4470                 case OP_LOADR4_MEMBASE:
4471                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4472                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4473                         break;
4474                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4475                 case OP_ICONV_TO_R8:
4476                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4477                         break;
4478                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4479                 case OP_LCONV_TO_R8:
4480                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4481                         break;
4482                 case OP_FCONV_TO_R4:
4483                         /* FIXME: nothing to do ?? */
4484                         break;
4485                 case OP_FCONV_TO_I1:
4486                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4487                         break;
4488                 case OP_FCONV_TO_U1:
4489                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4490                         break;
4491                 case OP_FCONV_TO_I2:
4492                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4493                         break;
4494                 case OP_FCONV_TO_U2:
4495                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4496                         break;
4497                 case OP_FCONV_TO_U4:
4498                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4499                         break;
4500                 case OP_FCONV_TO_I4:
4501                 case OP_FCONV_TO_I:
4502                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4503                         break;
4504                 case OP_FCONV_TO_I8:
4505                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4506                         break;
4507                 case OP_LCONV_TO_R_UN: {
4508                         guint8 *br [2];
4509
4510                         /* Based on gcc code */
4511                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4512                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4513
4514                         /* Positive case */
4515                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4516                         br [1] = code; x86_jump8 (code, 0);
4517                         amd64_patch (br [0], code);
4518
4519                         /* Negative case */
4520                         /* Save to the red zone */
4521                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4522                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4523                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4524                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4525                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4526                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4527                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4528                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4529                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4530                         /* Restore */
4531                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4532                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4533                         amd64_patch (br [1], code);
4534                         break;
4535                 }
4536                 case OP_LCONV_TO_OVF_U4:
4537                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4538                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4539                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4540                         break;
4541                 case OP_LCONV_TO_OVF_I4_UN:
4542                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4543                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4544                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4545                         break;
4546                 case OP_FMOVE:
4547                         if (ins->dreg != ins->sreg1)
4548                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4549                         break;
4550                 case OP_FADD:
4551                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4552                         break;
4553                 case OP_FSUB:
4554                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4555                         break;
4556                 case OP_FMUL:
4557                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4558                         break;
4559                 case OP_FDIV:
4560                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4561                         break;
4562                 case OP_FNEG: {
4563                         static double r8_0 = -0.0;
4564
4565                         g_assert (ins->sreg1 == ins->dreg);
4566
4567                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4568                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4569                         break;
4570                 }
4571                 case OP_SIN:
4572                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4573                         break;
4574                 case OP_COS:
4575                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4576                         break;
4577                 case OP_ABS: {
4578                         static guint64 d = 0x7fffffffffffffffUL;
4579
4580                         g_assert (ins->sreg1 == ins->dreg);
4581
4582                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4583                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4584                         break;
4585                 }
4586                 case OP_SQRT:
4587                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4588                         break;
4589                 case OP_IMIN:
4590                         g_assert (cfg->opt & MONO_OPT_CMOV);
4591                         g_assert (ins->dreg == ins->sreg1);
4592                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4593                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4594                         break;
4595                 case OP_IMIN_UN:
4596                         g_assert (cfg->opt & MONO_OPT_CMOV);
4597                         g_assert (ins->dreg == ins->sreg1);
4598                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4599                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4600                         break;
4601                 case OP_IMAX:
4602                         g_assert (cfg->opt & MONO_OPT_CMOV);
4603                         g_assert (ins->dreg == ins->sreg1);
4604                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4605                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4606                         break;
4607                 case OP_IMAX_UN:
4608                         g_assert (cfg->opt & MONO_OPT_CMOV);
4609                         g_assert (ins->dreg == ins->sreg1);
4610                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4611                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4612                         break;
4613                 case OP_LMIN:
4614                         g_assert (cfg->opt & MONO_OPT_CMOV);
4615                         g_assert (ins->dreg == ins->sreg1);
4616                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4617                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4618                         break;
4619                 case OP_LMIN_UN:
4620                         g_assert (cfg->opt & MONO_OPT_CMOV);
4621                         g_assert (ins->dreg == ins->sreg1);
4622                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4623                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4624                         break;
4625                 case OP_LMAX:
4626                         g_assert (cfg->opt & MONO_OPT_CMOV);
4627                         g_assert (ins->dreg == ins->sreg1);
4628                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4629                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4630                         break;
4631                 case OP_LMAX_UN:
4632                         g_assert (cfg->opt & MONO_OPT_CMOV);
4633                         g_assert (ins->dreg == ins->sreg1);
4634                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4635                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4636                         break;
4637                 case OP_X86_FPOP:
4638                         break;
4639                 case OP_FCOMPARE:
4640                         /*
4641                          * The two arguments are swapped because the fbranch instructions
4642                          * depend on this for the non-sse case to work.
4643                          */
4644                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4645                         break;
4646                 case OP_FCEQ: {
4647                         /* zeroing the register at the start results in
4648                          * shorter and faster code (we can also remove the widening op)
4649                          */
4650                         guchar *unordered_check;
4651                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4652                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4653                         unordered_check = code;
4654                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4655                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4656                         amd64_patch (unordered_check, code);
4657                         break;
4658                 }
4659                 case OP_FCLT:
4660                 case OP_FCLT_UN:
4661                         /* zeroing the register at the start results in
4662                          * shorter and faster code (we can also remove the widening op)
4663                          */
4664                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4665                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4666                         if (ins->opcode == OP_FCLT_UN) {
4667                                 guchar *unordered_check = code;
4668                                 guchar *jump_to_end;
4669                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4670                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4671                                 jump_to_end = code;
4672                                 x86_jump8 (code, 0);
4673                                 amd64_patch (unordered_check, code);
4674                                 amd64_inc_reg (code, ins->dreg);
4675                                 amd64_patch (jump_to_end, code);
4676                         } else {
4677                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4678                         }
4679                         break;
4680                 case OP_FCGT:
4681                 case OP_FCGT_UN: {
4682                         /* zeroing the register at the start results in
4683                          * shorter and faster code (we can also remove the widening op)
4684                          */
4685                         guchar *unordered_check;
4686                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4687                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4688                         if (ins->opcode == OP_FCGT) {
4689                                 unordered_check = code;
4690                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4691                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4692                                 amd64_patch (unordered_check, code);
4693                         } else {
4694                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4695                         }
4696                         break;
4697                 }
4698                 case OP_FCLT_MEMBASE:
4699                 case OP_FCGT_MEMBASE:
4700                 case OP_FCLT_UN_MEMBASE:
4701                 case OP_FCGT_UN_MEMBASE:
4702                 case OP_FCEQ_MEMBASE: {
4703                         guchar *unordered_check, *jump_to_end;
4704                         int x86_cond;
4705
4706                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4707                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4708
4709                         switch (ins->opcode) {
4710                         case OP_FCEQ_MEMBASE:
4711                                 x86_cond = X86_CC_EQ;
4712                                 break;
4713                         case OP_FCLT_MEMBASE:
4714                         case OP_FCLT_UN_MEMBASE:
4715                                 x86_cond = X86_CC_LT;
4716                                 break;
4717                         case OP_FCGT_MEMBASE:
4718                         case OP_FCGT_UN_MEMBASE:
4719                                 x86_cond = X86_CC_GT;
4720                                 break;
4721                         default:
4722                                 g_assert_not_reached ();
4723                         }
4724
4725                         unordered_check = code;
4726                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4727                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4728
4729                         switch (ins->opcode) {
4730                         case OP_FCEQ_MEMBASE:
4731                         case OP_FCLT_MEMBASE:
4732                         case OP_FCGT_MEMBASE:
4733                                 amd64_patch (unordered_check, code);
4734                                 break;
4735                         case OP_FCLT_UN_MEMBASE:
4736                         case OP_FCGT_UN_MEMBASE:
4737                                 jump_to_end = code;
4738                                 x86_jump8 (code, 0);
4739                                 amd64_patch (unordered_check, code);
4740                                 amd64_inc_reg (code, ins->dreg);
4741                                 amd64_patch (jump_to_end, code);
4742                                 break;
4743                         default:
4744                                 break;
4745                         }
4746                         break;
4747                 }
4748                 case OP_FBEQ: {
4749                         guchar *jump = code;
4750                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4751                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4752                         amd64_patch (jump, code);
4753                         break;
4754                 }
4755                 case OP_FBNE_UN:
4756                         /* Branch if C013 != 100 */
4757                         /* branch if !ZF or (PF|CF) */
4758                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4759                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4760                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4761                         break;
4762                 case OP_FBLT:
4763                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4764                         break;
4765                 case OP_FBLT_UN:
4766                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4767                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4768                         break;
4769                 case OP_FBGT:
4770                 case OP_FBGT_UN:
4771                         if (ins->opcode == OP_FBGT) {
4772                                 guchar *br1;
4773
4774                                 /* skip branch if C1=1 */
4775                                 br1 = code;
4776                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4777                                 /* branch if (C0 | C3) = 1 */
4778                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4779                                 amd64_patch (br1, code);
4780                                 break;
4781                         } else {
4782                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4783                         }
4784                         break;
4785                 case OP_FBGE: {
4786                         /* Branch if C013 == 100 or 001 */
4787                         guchar *br1;
4788
4789                         /* skip branch if C1=1 */
4790                         br1 = code;
4791                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4792                         /* branch if (C0 | C3) = 1 */
4793                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4794                         amd64_patch (br1, code);
4795                         break;
4796                 }
4797                 case OP_FBGE_UN:
4798                         /* Branch if C013 == 000 */
4799                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4800                         break;
4801                 case OP_FBLE: {
4802                         /* Branch if C013=000 or 100 */
4803                         guchar *br1;
4804
4805                         /* skip branch if C1=1 */
4806                         br1 = code;
4807                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4808                         /* branch if C0=0 */
4809                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4810                         amd64_patch (br1, code);
4811                         break;
4812                 }
4813                 case OP_FBLE_UN:
4814                         /* Branch if C013 != 001 */
4815                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4816                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4817                         break;
4818                 case OP_CKFINITE:
4819                         /* Transfer value to the fp stack */
4820                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4821                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4822                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4823
4824                         amd64_push_reg (code, AMD64_RAX);
4825                         amd64_fxam (code);
4826                         amd64_fnstsw (code);
4827                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4828                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4829                         amd64_pop_reg (code, AMD64_RAX);
4830                         amd64_fstp (code, 0);
4831                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4832                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4833                         break;
4834                 case OP_TLS_GET: {
4835                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4836                         break;
4837                 }
4838                 case OP_MEMORY_BARRIER: {
4839                         /* Not needed on amd64 */
4840                         break;
4841                 }
4842                 case OP_ATOMIC_ADD_I4:
4843                 case OP_ATOMIC_ADD_I8: {
4844                         int dreg = ins->dreg;
4845                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4846
4847                         if (dreg == ins->inst_basereg)
4848                                 dreg = AMD64_R11;
4849
4850                         if (dreg != ins->sreg2)
4851                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4852
4853                         x86_prefix (code, X86_LOCK_PREFIX);
4854                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4855
4856                         if (dreg != ins->dreg)
4857                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4858
4859                         break;
4860                 }
4861                 case OP_ATOMIC_ADD_NEW_I4:
4862                 case OP_ATOMIC_ADD_NEW_I8: {
4863                         int dreg = ins->dreg;
4864                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4865
4866                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4867                                 dreg = AMD64_R11;
4868
4869                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4870                         amd64_prefix (code, X86_LOCK_PREFIX);
4871                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4872                         /* dreg contains the old value, add with sreg2 value */
4873                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4874
4875                         if (ins->dreg != dreg)
4876                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4877
4878                         break;
4879                 }
4880                 case OP_ATOMIC_EXCHANGE_I4:
4881                 case OP_ATOMIC_EXCHANGE_I8: {
4882                         guchar *br[2];
4883                         int sreg2 = ins->sreg2;
4884                         int breg = ins->inst_basereg;
4885                         guint32 size;
4886                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4887
4888                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4889                                 size = 8;
4890                         else
4891                                 size = 4;
4892
4893                         /*
4894                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4895                          * an explanation of how this works.
4896                          */
4897
4898                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4899                          * hack to overcome limits in x86 reg allocator
4900                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4901                          */
4902                         g_assert (ins->dreg == AMD64_RAX);
4903
4904                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4905                                 /* Highly unlikely, but possible */
4906                                 need_push = TRUE;
4907
4908                         /* The pushes invalidate rsp */
4909                         if ((breg == AMD64_RAX) || need_push) {
4910                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4911                                 breg = AMD64_R11;
4912                         }
4913
4914                         /* We need the EAX reg for the comparand */
4915                         if (ins->sreg2 == AMD64_RAX) {
4916                                 if (breg != AMD64_R11) {
4917                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4918                                         sreg2 = AMD64_R11;
4919                                 } else {
4920                                         g_assert (need_push);
4921                                         amd64_push_reg (code, AMD64_RDX);
4922                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4923                                         sreg2 = AMD64_RDX;
4924                                         rdx_pushed = TRUE;
4925                                 }
4926                         }
4927
4928                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4929
4930                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4931                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4932                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4933                         amd64_patch (br [1], br [0]);
4934
4935                         if (rdx_pushed)
4936                                 amd64_pop_reg (code, AMD64_RDX);
4937
4938                         break;
4939                 }
4940                 case OP_ATOMIC_CAS_I4:
4941                 case OP_ATOMIC_CAS_I8: {
4942                         guint32 size;
4943
4944                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4945                                 size = 8;
4946                         else
4947                                 size = 4;
4948
4949                         /*
4950                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4951                          * an explanation of how this works.
4952                          */
4953                         g_assert (ins->sreg3 == AMD64_RAX);
4954                         g_assert (ins->sreg1 != AMD64_RAX);
4955                         g_assert (ins->sreg1 != ins->sreg2);
4956
4957                         amd64_prefix (code, X86_LOCK_PREFIX);
4958                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4959
4960                         if (ins->dreg != AMD64_RAX)
4961                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4962                         break;
4963                 }
4964 #ifdef MONO_ARCH_SIMD_INTRINSICS
4965                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4966                 case OP_ADDPS:
4967                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4968                         break;
4969                 case OP_DIVPS:
4970                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4971                         break;
4972                 case OP_MULPS:
4973                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4974                         break;
4975                 case OP_SUBPS:
4976                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4977                         break;
4978                 case OP_MAXPS:
4979                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4980                         break;
4981                 case OP_MINPS:
4982                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4983                         break;
4984                 case OP_COMPPS:
4985                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4986                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4987                         break;
4988                 case OP_ANDPS:
4989                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4990                         break;
4991                 case OP_ANDNPS:
4992                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4993                         break;
4994                 case OP_ORPS:
4995                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4996                         break;
4997                 case OP_XORPS:
4998                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4999                         break;
5000                 case OP_SQRTPS:
5001                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5002                         break;
5003                 case OP_RSQRTPS:
5004                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5005                         break;
5006                 case OP_RCPPS:
5007                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5008                         break;
5009                 case OP_ADDSUBPS:
5010                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5011                         break;
5012                 case OP_HADDPS:
5013                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5014                         break;
5015                 case OP_HSUBPS:
5016                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5017                         break;
5018                 case OP_DUPPS_HIGH:
5019                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5020                         break;
5021                 case OP_DUPPS_LOW:
5022                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5023                         break;
5024
5025                 case OP_PSHUFLEW_HIGH:
5026                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5027                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5028                         break;
5029                 case OP_PSHUFLEW_LOW:
5030                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5031                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5032                         break;
5033                 case OP_PSHUFLED:
5034                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5035                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5036                         break;
5037
5038                 case OP_ADDPD:
5039                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5040                         break;
5041                 case OP_DIVPD:
5042                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5043                         break;
5044                 case OP_MULPD:
5045                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5046                         break;
5047                 case OP_SUBPD:
5048                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5049                         break;
5050                 case OP_MAXPD:
5051                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5052                         break;
5053                 case OP_MINPD:
5054                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5055                         break;
5056                 case OP_COMPPD:
5057                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5058                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5059                         break;
5060                 case OP_ANDPD:
5061                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5062                         break;
5063                 case OP_ANDNPD:
5064                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5065                         break;
5066                 case OP_ORPD:
5067                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5068                         break;
5069                 case OP_XORPD:
5070                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_SQRTPD:
5073                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5074                         break;
5075                 case OP_ADDSUBPD:
5076                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078                 case OP_HADDPD:
5079                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5080                         break;
5081                 case OP_HSUBPD:
5082                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5083                         break;
5084                 case OP_DUPPD:
5085                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5086                         break;
5087
5088                 case OP_EXTRACT_MASK:
5089                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5090                         break;
5091
5092                 case OP_PAND:
5093                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095                 case OP_POR:
5096                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5097                         break;
5098                 case OP_PXOR:
5099                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5100                         break;
5101
5102                 case OP_PADDB:
5103                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5104                         break;
5105                 case OP_PADDW:
5106                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5107                         break;
5108                 case OP_PADDD:
5109                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5110                         break;
5111                 case OP_PADDQ:
5112                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5113                         break;
5114
5115                 case OP_PSUBB:
5116                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5117                         break;
5118                 case OP_PSUBW:
5119                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5120                         break;
5121                 case OP_PSUBD:
5122                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5123                         break;
5124                 case OP_PSUBQ:
5125                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5126                         break;
5127
5128                 case OP_PMAXB_UN:
5129                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5130                         break;
5131                 case OP_PMAXW_UN:
5132                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5133                         break;
5134                 case OP_PMAXD_UN:
5135                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5136                         break;
5137
5138                 case OP_PMAXB:
5139                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5140                         break;
5141                 case OP_PMAXW:
5142                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5143                         break;
5144                 case OP_PMAXD:
5145                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5146                         break;
5147
5148                 case OP_PAVGB_UN:
5149                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5150                         break;
5151                 case OP_PAVGW_UN:
5152                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5153                         break;
5154
5155                 case OP_PMINB_UN:
5156                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5157                         break;
5158                 case OP_PMINW_UN:
5159                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5160                         break;
5161                 case OP_PMIND_UN:
5162                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5163                         break;
5164
5165                 case OP_PMINB:
5166                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5167                         break;
5168                 case OP_PMINW:
5169                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5170                         break;
5171                 case OP_PMIND:
5172                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5173                         break;
5174
5175                 case OP_PCMPEQB:
5176                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5177                         break;
5178                 case OP_PCMPEQW:
5179                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5180                         break;
5181                 case OP_PCMPEQD:
5182                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5183                         break;
5184                 case OP_PCMPEQQ:
5185                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5186                         break;
5187
5188                 case OP_PCMPGTB:
5189                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5190                         break;
5191                 case OP_PCMPGTW:
5192                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5193                         break;
5194                 case OP_PCMPGTD:
5195                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5196                         break;
5197                 case OP_PCMPGTQ:
5198                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5199                         break;
5200
5201                 case OP_PSUM_ABS_DIFF:
5202                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5203                         break;
5204
5205                 case OP_UNPACK_LOWB:
5206                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_UNPACK_LOWW:
5209                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_UNPACK_LOWD:
5212                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214                 case OP_UNPACK_LOWQ:
5215                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5216                         break;
5217                 case OP_UNPACK_LOWPS:
5218                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5219                         break;
5220                 case OP_UNPACK_LOWPD:
5221                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5222                         break;
5223
5224                 case OP_UNPACK_HIGHB:
5225                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227                 case OP_UNPACK_HIGHW:
5228                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5229                         break;
5230                 case OP_UNPACK_HIGHD:
5231                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5232                         break;
5233                 case OP_UNPACK_HIGHQ:
5234                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5235                         break;
5236                 case OP_UNPACK_HIGHPS:
5237                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5238                         break;
5239                 case OP_UNPACK_HIGHPD:
5240                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5241                         break;
5242
5243                 case OP_PACKW:
5244                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5245                         break;
5246                 case OP_PACKD:
5247                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5248                         break;
5249                 case OP_PACKW_UN:
5250                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5251                         break;
5252                 case OP_PACKD_UN:
5253                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5254                         break;
5255
5256                 case OP_PADDB_SAT_UN:
5257                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5258                         break;
5259                 case OP_PSUBB_SAT_UN:
5260                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5261                         break;
5262                 case OP_PADDW_SAT_UN:
5263                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5264                         break;
5265                 case OP_PSUBW_SAT_UN:
5266                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5267                         break;
5268
5269                 case OP_PADDB_SAT:
5270                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5271                         break;
5272                 case OP_PSUBB_SAT:
5273                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5274                         break;
5275                 case OP_PADDW_SAT:
5276                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5277                         break;
5278                 case OP_PSUBW_SAT:
5279                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5280                         break;
5281
5282                 case OP_PMULW:
5283                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5284                         break;
5285                 case OP_PMULD:
5286                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5287                         break;
5288                 case OP_PMULQ:
5289                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5290                         break;
5291                 case OP_PMULW_HIGH_UN:
5292                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5293                         break;
5294                 case OP_PMULW_HIGH:
5295                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         break;
5297
5298                 case OP_PSHRW:
5299                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5300                         break;
5301                 case OP_PSHRW_REG:
5302                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5303                         break;
5304
5305                 case OP_PSARW:
5306                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5307                         break;
5308                 case OP_PSARW_REG:
5309                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5310                         break;
5311
5312                 case OP_PSHLW:
5313                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5314                         break;
5315                 case OP_PSHLW_REG:
5316                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5317                         break;
5318
5319                 case OP_PSHRD:
5320                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5321                         break;
5322                 case OP_PSHRD_REG:
5323                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5324                         break;
5325
5326                 case OP_PSARD:
5327                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5328                         break;
5329                 case OP_PSARD_REG:
5330                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5331                         break;
5332
5333                 case OP_PSHLD:
5334                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5335                         break;
5336                 case OP_PSHLD_REG:
5337                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5338                         break;
5339
5340                 case OP_PSHRQ:
5341                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5342                         break;
5343                 case OP_PSHRQ_REG:
5344                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5345                         break;
5346
5347                 /*TODO: This is appart of the sse spec but not added
5348                 case OP_PSARQ:
5349                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5350                         break;
5351                 case OP_PSARQ_REG:
5352                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5353                         break;
5354                 */
5355
5356                 case OP_PSHLQ:
5357                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5358                         break;
5359                 case OP_PSHLQ_REG:
5360                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5361                         break;
5362
5363                 case OP_ICONV_TO_X:
5364                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5365                         break;
5366                 case OP_EXTRACT_I4:
5367                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5368                         break;
5369                 case OP_EXTRACT_I8:
5370                         if (ins->inst_c0) {
5371                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5372                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5373                         } else {
5374                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5375                         }
5376                         break;
5377                 case OP_EXTRACT_I1:
5378                 case OP_EXTRACT_U1:
5379                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5380                         if (ins->inst_c0)
5381                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5382                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5383                         break;
5384                 case OP_EXTRACT_I2:
5385                 case OP_EXTRACT_U2:
5386                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5387                         if (ins->inst_c0)
5388                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5389                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5390                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5391                         break;
5392                 case OP_EXTRACT_R8:
5393                         if (ins->inst_c0)
5394                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5395                         else
5396                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5397                         break;
5398                 case OP_INSERT_I2:
5399                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5400                         break;
5401                 case OP_EXTRACTX_U2:
5402                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5403                         break;
5404                 case OP_INSERTX_U1_SLOW:
5405                         /*sreg1 is the extracted ireg (scratch)
5406                         /sreg2 is the to be inserted ireg (scratch)
5407                         /dreg is the xreg to receive the value*/
5408
5409                         /*clear the bits from the extracted word*/
5410                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5411                         /*shift the value to insert if needed*/
5412                         if (ins->inst_c0 & 1)
5413                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5414                         /*join them together*/
5415                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5416                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5417                         break;
5418                 case OP_INSERTX_I4_SLOW:
5419                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5420                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5421                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5422                         break;
5423                 case OP_INSERTX_I8_SLOW:
5424                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5425                         if (ins->inst_c0)
5426                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5427                         else
5428                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5429                         break;
5430
5431                 case OP_INSERTX_R4_SLOW:
5432                         switch (ins->inst_c0) {
5433                         case 0:
5434                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5435                                 break;
5436                         case 1:
5437                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5438                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5439                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5440                                 break;
5441                         case 2:
5442                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5443                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5444                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5445                                 break;
5446                         case 3:
5447                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5448                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5449                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5450                                 break;
5451                         }
5452                         break;
5453                 case OP_INSERTX_R8_SLOW:
5454                         if (ins->inst_c0)
5455                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5456                         else
5457                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5458                         break;
5459                 case OP_STOREX_MEMBASE_REG:
5460                 case OP_STOREX_MEMBASE:
5461                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5462                         break;
5463                 case OP_LOADX_MEMBASE:
5464                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5465                         break;
5466                 case OP_LOADX_ALIGNED_MEMBASE:
5467                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5468                         break;
5469                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5470                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5471                         break;
5472                 case OP_STOREX_NTA_MEMBASE_REG:
5473                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5474                         break;
5475                 case OP_PREFETCH_MEMBASE:
5476                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5477                         break;
5478
5479                 case OP_XMOVE:
5480                         /*FIXME the peephole pass should have killed this*/
5481                         if (ins->dreg != ins->sreg1)
5482                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5483                         break;
5484                 case OP_XZERO:
5485                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5486                         break;
5487                 case OP_ICONV_TO_R8_RAW:
5488                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5489                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5490                         break;
5491
5492                 case OP_FCONV_TO_R8_X:
5493                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5494                         break;
5495
5496                 case OP_XCONV_R8_TO_I4:
5497                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5498                         switch (ins->backend.source_opcode) {
5499                         case OP_FCONV_TO_I1:
5500                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5501                                 break;
5502                         case OP_FCONV_TO_U1:
5503                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5504                                 break;
5505                         case OP_FCONV_TO_I2:
5506                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5507                                 break;
5508                         case OP_FCONV_TO_U2:
5509                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5510                                 break;
5511                         }
5512                         break;
5513
5514                 case OP_EXPAND_I2:
5515                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5516                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5517                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5518                         break;
5519                 case OP_EXPAND_I4:
5520                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5521                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5522                         break;
5523                 case OP_EXPAND_I8:
5524                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5525                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5526                         break;
5527                 case OP_EXPAND_R4:
5528                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5529                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5530                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5531                         break;
5532                 case OP_EXPAND_R8:
5533                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5534                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5535                         break;
5536 #endif
5537                 case OP_LIVERANGE_START: {
5538                         if (cfg->verbose_level > 1)
5539                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5540                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5541                         break;
5542                 }
5543                 case OP_LIVERANGE_END: {
5544                         if (cfg->verbose_level > 1)
5545                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5546                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5547                         break;
5548                 }
5549                 default:
5550                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5551                         g_assert_not_reached ();
5552                 }
5553
5554                 if ((code - cfg->native_code - offset) > max_len) {
5555                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5556                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5557                         g_assert_not_reached ();
5558                 }
5559
5560                 last_ins = ins;
5561                 last_offset = offset;
5562         }
5563
5564         cfg->code_len = code - cfg->native_code;
5565 }
5566
5567 #endif /* DISABLE_JIT */
5568
5569 void
5570 mono_arch_register_lowlevel_calls (void)
5571 {
5572         /* The signature doesn't matter */
5573         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5574 }
5575
5576 void
5577 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5578 {
5579         MonoJumpInfo *patch_info;
5580         gboolean compile_aot = !run_cctors;
5581
5582         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5583                 unsigned char *ip = patch_info->ip.i + code;
5584                 unsigned char *target;
5585
5586                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5587
5588                 if (compile_aot) {
5589                         switch (patch_info->type) {
5590                         case MONO_PATCH_INFO_BB:
5591                         case MONO_PATCH_INFO_LABEL:
5592                                 break;
5593                         default:
5594                                 /* No need to patch these */
5595                                 continue;
5596                         }
5597                 }
5598
5599                 switch (patch_info->type) {
5600                 case MONO_PATCH_INFO_NONE:
5601                         continue;
5602                 case MONO_PATCH_INFO_METHOD_REL:
5603                 case MONO_PATCH_INFO_R8:
5604                 case MONO_PATCH_INFO_R4:
5605                         g_assert_not_reached ();
5606                         continue;
5607                 case MONO_PATCH_INFO_BB:
5608                         break;
5609                 default:
5610                         break;
5611                 }
5612
5613                 /*
5614                  * Debug code to help track down problems where the target of a near call is
5615                  * is not valid.
5616                  */
5617                 if (amd64_is_near_call (ip)) {
5618                         gint64 disp = (guint8*)target - (guint8*)ip;
5619
5620                         if (!amd64_is_imm32 (disp)) {
5621                                 printf ("TYPE: %d\n", patch_info->type);
5622                                 switch (patch_info->type) {
5623                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5624                                         printf ("V: %s\n", patch_info->data.name);
5625                                         break;
5626                                 case MONO_PATCH_INFO_METHOD_JUMP:
5627                                 case MONO_PATCH_INFO_METHOD:
5628                                         printf ("V: %s\n", patch_info->data.method->name);
5629                                         break;
5630                                 default:
5631                                         break;
5632                                 }
5633                         }
5634                 }
5635
5636                 amd64_patch (ip, (gpointer)target);
5637         }
5638 }
5639
5640 #ifndef DISABLE_JIT
5641
5642 static int
5643 get_max_epilog_size (MonoCompile *cfg)
5644 {
5645         int max_epilog_size = 16;
5646
5647         if (cfg->method->save_lmf)
5648                 max_epilog_size += 256;
5649
5650         if (mono_jit_trace_calls != NULL)
5651                 max_epilog_size += 50;
5652
5653         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5654                 max_epilog_size += 50;
5655
5656         max_epilog_size += (AMD64_NREG * 2);
5657
5658         return max_epilog_size;
5659 }
5660
5661 /*
5662  * This macro is used for testing whenever the unwinder works correctly at every point
5663  * where an async exception can happen.
5664  */
5665 /* This will generate a SIGSEGV at the given point in the code */
5666 #define async_exc_point(code) do { \
5667     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5668          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5669              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5670          cfg->arch.async_point_count ++; \
5671     } \
5672 } while (0)
5673
5674 guint8 *
5675 mono_arch_emit_prolog (MonoCompile *cfg)
5676 {
5677         MonoMethod *method = cfg->method;
5678         MonoBasicBlock *bb;
5679         MonoMethodSignature *sig;
5680         MonoInst *ins;
5681         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5682         guint8 *code;
5683         CallInfo *cinfo;
5684         gint32 lmf_offset = cfg->arch.lmf_offset;
5685         gboolean args_clobbered = FALSE;
5686         gboolean trace = FALSE;
5687
5688         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5689
5690         code = cfg->native_code = g_malloc (cfg->code_size);
5691
5692         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5693                 trace = TRUE;
5694
5695         /* Amount of stack space allocated by register saving code */
5696         pos = 0;
5697
5698         /* Offset between RSP and the CFA */
5699         cfa_offset = 0;
5700
5701         /*
5702          * The prolog consists of the following parts:
5703          * FP present:
5704          * - push rbp, mov rbp, rsp
5705          * - save callee saved regs using pushes
5706          * - allocate frame
5707          * - save rgctx if needed
5708          * - save lmf if needed
5709          * FP not present:
5710          * - allocate frame
5711          * - save rgctx if needed
5712          * - save lmf if needed
5713          * - save callee saved regs using moves
5714          */
5715
5716         // CFA = sp + 8
5717         cfa_offset = 8;
5718         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5719         // IP saved at CFA - 8
5720         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5721         async_exc_point (code);
5722
5723         if (!cfg->arch.omit_fp) {
5724                 amd64_push_reg (code, AMD64_RBP);
5725                 cfa_offset += 8;
5726                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5727                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5728                 async_exc_point (code);
5729 #ifdef HOST_WIN32
5730                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5731 #endif
5732
5733                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5734                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5735                 async_exc_point (code);
5736 #ifdef HOST_WIN32
5737                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5738 #endif
5739         }
5740
5741         /* Save callee saved registers */
5742         if (!cfg->arch.omit_fp && !method->save_lmf) {
5743                 int offset = cfa_offset;
5744
5745                 for (i = 0; i < AMD64_NREG; ++i)
5746                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5747                                 amd64_push_reg (code, i);
5748                                 pos += sizeof (gpointer);
5749                                 offset += 8;
5750                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5751                                 async_exc_point (code);
5752                         }
5753         }
5754
5755         /* The param area is always at offset 0 from sp */
5756         /* This needs to be allocated here, since it has to come after the spill area */
5757         if (cfg->arch.no_pushes && cfg->param_area) {
5758                 if (cfg->arch.omit_fp)
5759                         // FIXME:
5760                         g_assert_not_reached ();
5761                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5762         }
5763
5764         if (cfg->arch.omit_fp) {
5765                 /*
5766                  * On enter, the stack is misaligned by the the pushing of the return
5767                  * address. It is either made aligned by the pushing of %rbp, or by
5768                  * this.
5769                  */
5770                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5771                 if ((alloc_size % 16) == 0)
5772                         alloc_size += 8;
5773         } else {
5774                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5775
5776                 alloc_size -= pos;
5777         }
5778
5779         cfg->arch.stack_alloc_size = alloc_size;
5780
5781         /* Allocate stack frame */
5782         if (alloc_size) {
5783                 /* See mono_emit_stack_alloc */
5784 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5785                 guint32 remaining_size = alloc_size;
5786                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5787                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5788                 guint32 offset = code - cfg->native_code;
5789                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5790                         while (required_code_size >= (cfg->code_size - offset))
5791                                 cfg->code_size *= 2;
5792                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5793                         code = cfg->native_code + offset;
5794                         mono_jit_stats.code_reallocs++;
5795                 }
5796
5797                 while (remaining_size >= 0x1000) {
5798                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5799                         if (cfg->arch.omit_fp) {
5800                                 cfa_offset += 0x1000;
5801                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5802                         }
5803                         async_exc_point (code);
5804 #ifdef HOST_WIN32
5805                         if (cfg->arch.omit_fp)
5806                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5807 #endif
5808
5809                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5810                         remaining_size -= 0x1000;
5811                 }
5812                 if (remaining_size) {
5813                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5814                         if (cfg->arch.omit_fp) {
5815                                 cfa_offset += remaining_size;
5816                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5817                                 async_exc_point (code);
5818                         }
5819 #ifdef HOST_WIN32
5820                         if (cfg->arch.omit_fp)
5821                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5822 #endif
5823                 }
5824 #else
5825                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5826                 if (cfg->arch.omit_fp) {
5827                         cfa_offset += alloc_size;
5828                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5829                         async_exc_point (code);
5830                 }
5831 #endif
5832         }
5833
5834         /* Stack alignment check */
5835 #if 0
5836         {
5837                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5838                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5839                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5840                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5841                 amd64_breakpoint (code);
5842         }
5843 #endif
5844
5845 #ifndef TARGET_WIN32
5846         if (mini_get_debug_options ()->init_stacks) {
5847                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5848
5849                 /* Save registers to the red zone */
5850                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5851                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5852
5853                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5854                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5855                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5856
5857                 amd64_cld (code);
5858                 amd64_prefix (code, X86_REP_PREFIX);
5859                 amd64_stosl (code);
5860
5861                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5862                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5863         }
5864 #endif
5865
5866         /* Save LMF */
5867         if (method->save_lmf) {
5868                 /*
5869                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5870                  */
5871                 /*
5872                  * sp is saved right before calls but we need to save it here too so
5873                  * async stack walks would work.
5874                  */
5875                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5876                 /* Skip method (only needed for trampoline LMF frames) */
5877                 /* Save callee saved regs */
5878                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5879                         int offset;
5880
5881                         switch (i) {
5882                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5883                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5884                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5885                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5886                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5887                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5888 #ifdef HOST_WIN32
5889                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5890                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5891 #endif
5892                         default:
5893                                 offset = -1;
5894                                 break;
5895                         }
5896
5897                         if (offset != -1) {
5898                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5899                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5900                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5901                         }
5902                 }
5903         }
5904
5905         /* Save callee saved registers */
5906         if (cfg->arch.omit_fp && !method->save_lmf) {
5907                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5908
5909                 /* Save caller saved registers after sp is adjusted */
5910                 /* The registers are saved at the bottom of the frame */
5911                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5912                 for (i = 0; i < AMD64_NREG; ++i)
5913                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5914                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5915                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5916                                 save_area_offset += 8;
5917                                 async_exc_point (code);
5918                         }
5919         }
5920
5921         /* store runtime generic context */
5922         if (cfg->rgctx_var) {
5923                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5924                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5925
5926                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5927         }
5928
5929         /* compute max_length in order to use short forward jumps */
5930         max_epilog_size = get_max_epilog_size (cfg);
5931         if (cfg->opt & MONO_OPT_BRANCH) {
5932                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5933                         MonoInst *ins;
5934                         int max_length = 0;
5935
5936                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5937                                 max_length += 6;
5938                         /* max alignment for loops */
5939                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5940                                 max_length += LOOP_ALIGNMENT;
5941
5942                         MONO_BB_FOR_EACH_INS (bb, ins) {
5943                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5944                         }
5945
5946                         /* Take prolog and epilog instrumentation into account */
5947                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5948                                 max_length += max_epilog_size;
5949
5950                         bb->max_length = max_length;
5951                 }
5952         }
5953
5954         sig = mono_method_signature (method);
5955         pos = 0;
5956
5957         cinfo = cfg->arch.cinfo;
5958
5959         if (sig->ret->type != MONO_TYPE_VOID) {
5960                 /* Save volatile arguments to the stack */
5961                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5962                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5963         }
5964
5965         /* Keep this in sync with emit_load_volatile_arguments */
5966         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5967                 ArgInfo *ainfo = cinfo->args + i;
5968                 gint32 stack_offset;
5969                 MonoType *arg_type;
5970
5971                 ins = cfg->args [i];
5972
5973                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5974                         /* Unused arguments */
5975                         continue;
5976
5977                 if (sig->hasthis && (i == 0))
5978                         arg_type = &mono_defaults.object_class->byval_arg;
5979                 else
5980                         arg_type = sig->params [i - sig->hasthis];
5981
5982                 stack_offset = ainfo->offset + ARGS_OFFSET;
5983
5984                 if (cfg->globalra) {
5985                         /* All the other moves are done by the register allocator */
5986                         switch (ainfo->storage) {
5987                         case ArgInFloatSSEReg:
5988                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5989                                 break;
5990                         case ArgValuetypeInReg:
5991                                 for (quad = 0; quad < 2; quad ++) {
5992                                         switch (ainfo->pair_storage [quad]) {
5993                                         case ArgInIReg:
5994                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5995                                                 break;
5996                                         case ArgInFloatSSEReg:
5997                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5998                                                 break;
5999                                         case ArgInDoubleSSEReg:
6000                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6001                                                 break;
6002                                         case ArgNone:
6003                                                 break;
6004                                         default:
6005                                                 g_assert_not_reached ();
6006                                         }
6007                                 }
6008                                 break;
6009                         default:
6010                                 break;
6011                         }
6012
6013                         continue;
6014                 }
6015
6016                 /* Save volatile arguments to the stack */
6017                 if (ins->opcode != OP_REGVAR) {
6018                         switch (ainfo->storage) {
6019                         case ArgInIReg: {
6020                                 guint32 size = 8;
6021
6022                                 /* FIXME: I1 etc */
6023                                 /*
6024                                 if (stack_offset & 0x1)
6025                                         size = 1;
6026                                 else if (stack_offset & 0x2)
6027                                         size = 2;
6028                                 else if (stack_offset & 0x4)
6029                                         size = 4;
6030                                 else
6031                                         size = 8;
6032                                 */
6033                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6034                                 break;
6035                         }
6036                         case ArgInFloatSSEReg:
6037                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6038                                 break;
6039                         case ArgInDoubleSSEReg:
6040                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6041                                 break;
6042                         case ArgValuetypeInReg:
6043                                 for (quad = 0; quad < 2; quad ++) {
6044                                         switch (ainfo->pair_storage [quad]) {
6045                                         case ArgInIReg:
6046                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6047                                                 break;
6048                                         case ArgInFloatSSEReg:
6049                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6050                                                 break;
6051                                         case ArgInDoubleSSEReg:
6052                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6053                                                 break;
6054                                         case ArgNone:
6055                                                 break;
6056                                         default:
6057                                                 g_assert_not_reached ();
6058                                         }
6059                                 }
6060                                 break;
6061                         case ArgValuetypeAddrInIReg:
6062                                 if (ainfo->pair_storage [0] == ArgInIReg)
6063                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6064                                 break;
6065                         default:
6066                                 break;
6067                         }
6068                 } else {
6069                         /* Argument allocated to (non-volatile) register */
6070                         switch (ainfo->storage) {
6071                         case ArgInIReg:
6072                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6073                                 break;
6074                         case ArgOnStack:
6075                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6076                                 break;
6077                         default:
6078                                 g_assert_not_reached ();
6079                         }
6080                 }
6081         }
6082
6083         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6084         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6085                 guint64 domain = (guint64)cfg->domain;
6086
6087                 args_clobbered = TRUE;
6088
6089                 /*
6090                  * The call might clobber argument registers, but they are already
6091                  * saved to the stack/global regs.
6092                  */
6093                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6094                         guint8 *buf, *no_domain_branch;
6095
6096                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6097                         if (cfg->compile_aot) {
6098                                 /* AOT code is only used in the root domain */
6099                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6100                         } else {
6101                                 if ((domain >> 32) == 0)
6102                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6103                                 else
6104                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6105                         }
6106                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6107                         no_domain_branch = code;
6108                         x86_branch8 (code, X86_CC_NE, 0, 0);
6109                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6110                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6111                         buf = code;
6112                         x86_branch8 (code, X86_CC_NE, 0, 0);
6113                         amd64_patch (no_domain_branch, code);
6114                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6115                                           (gpointer)"mono_jit_thread_attach", TRUE);
6116                         amd64_patch (buf, code);
6117 #ifdef HOST_WIN32
6118                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6119                         /* FIXME: Add a separate key for LMF to avoid this */
6120                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6121 #endif
6122                 } else {
6123                         g_assert (!cfg->compile_aot);
6124                         if (cfg->compile_aot) {
6125                                 /* AOT code is only used in the root domain */
6126                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6127                         } else {
6128                                 if ((domain >> 32) == 0)
6129                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6130                                 else
6131                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6132                         }
6133                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6134                                           (gpointer)"mono_jit_thread_attach", TRUE);
6135                 }
6136         }
6137
6138         if (method->save_lmf) {
6139                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6140                         /*
6141                          * Optimized version which uses the mono_lmf TLS variable instead of
6142                          * indirection through the mono_lmf_addr TLS variable.
6143                          */
6144                         /* %rax = previous_lmf */
6145                         x86_prefix (code, X86_FS_PREFIX);
6146                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6147
6148                         /* Save previous_lmf */
6149                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6150                         /* Set new lmf */
6151                         if (lmf_offset == 0) {
6152                                 x86_prefix (code, X86_FS_PREFIX);
6153                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6154                         } else {
6155                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6156                                 x86_prefix (code, X86_FS_PREFIX);
6157                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6158                         }
6159                 } else {
6160                         if (lmf_addr_tls_offset != -1) {
6161                                 /* Load lmf quicky using the FS register */
6162                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6163 #ifdef HOST_WIN32
6164                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6165                                 /* FIXME: Add a separate key for LMF to avoid this */
6166                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6167 #endif
6168                         }
6169                         else {
6170                                 /*
6171                                  * The call might clobber argument registers, but they are already
6172                                  * saved to the stack/global regs.
6173                                  */
6174                                 args_clobbered = TRUE;
6175                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6176                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6177                         }
6178
6179                         /* Save lmf_addr */
6180                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6181                         /* Save previous_lmf */
6182                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6183                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6184                         /* Set new lmf */
6185                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6186                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6187                 }
6188         }
6189
6190         if (trace) {
6191                 args_clobbered = TRUE;
6192                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6193         }
6194
6195         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6196                 args_clobbered = TRUE;
6197
6198         /*
6199          * Optimize the common case of the first bblock making a call with the same
6200          * arguments as the method. This works because the arguments are still in their
6201          * original argument registers.
6202          * FIXME: Generalize this
6203          */
6204         if (!args_clobbered) {
6205                 MonoBasicBlock *first_bb = cfg->bb_entry;
6206                 MonoInst *next;
6207
6208                 next = mono_bb_first_ins (first_bb);
6209                 if (!next && first_bb->next_bb) {
6210                         first_bb = first_bb->next_bb;
6211                         next = mono_bb_first_ins (first_bb);
6212                 }
6213
6214                 if (first_bb->in_count > 1)
6215                         next = NULL;
6216
6217                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6218                         ArgInfo *ainfo = cinfo->args + i;
6219                         gboolean match = FALSE;
6220
6221                         ins = cfg->args [i];
6222                         if (ins->opcode != OP_REGVAR) {
6223                                 switch (ainfo->storage) {
6224                                 case ArgInIReg: {
6225                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6226                                                 if (next->dreg == ainfo->reg) {
6227                                                         NULLIFY_INS (next);
6228                                                         match = TRUE;
6229                                                 } else {
6230                                                         next->opcode = OP_MOVE;
6231                                                         next->sreg1 = ainfo->reg;
6232                                                         /* Only continue if the instruction doesn't change argument regs */
6233                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6234                                                                 match = TRUE;
6235                                                 }
6236                                         }
6237                                         break;
6238                                 }
6239                                 default:
6240                                         break;
6241                                 }
6242                         } else {
6243                                 /* Argument allocated to (non-volatile) register */
6244                                 switch (ainfo->storage) {
6245                                 case ArgInIReg:
6246                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6247                                                 NULLIFY_INS (next);
6248                                                 match = TRUE;
6249                                         }
6250                                         break;
6251                                 default:
6252                                         break;
6253                                 }
6254                         }
6255
6256                         if (match) {
6257                                 next = next->next;
6258                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6259                                 if (!next)
6260                                         break;
6261                         }
6262                 }
6263         }
6264
6265         /* Initialize ss_trigger_page_var */
6266         if (cfg->arch.ss_trigger_page_var) {
6267                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6268
6269                 g_assert (!cfg->compile_aot);
6270                 g_assert (var->opcode == OP_REGOFFSET);
6271
6272                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6273                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6274         }
6275
6276         cfg->code_len = code - cfg->native_code;
6277
6278         g_assert (cfg->code_len < cfg->code_size);
6279
6280         return code;
6281 }
6282
6283 void
6284 mono_arch_emit_epilog (MonoCompile *cfg)
6285 {
6286         MonoMethod *method = cfg->method;
6287         int quad, pos, i;
6288         guint8 *code;
6289         int max_epilog_size;
6290         CallInfo *cinfo;
6291         gint32 lmf_offset = cfg->arch.lmf_offset;
6292
6293         max_epilog_size = get_max_epilog_size (cfg);
6294
6295         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6296                 cfg->code_size *= 2;
6297                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6298                 mono_jit_stats.code_reallocs++;
6299         }
6300
6301         code = cfg->native_code + cfg->code_len;
6302
6303         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6304                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6305
6306         /* the code restoring the registers must be kept in sync with OP_JMP */
6307         pos = 0;
6308
6309         if (method->save_lmf) {
6310                 /* check if we need to restore protection of the stack after a stack overflow */
6311                 if (mono_get_jit_tls_offset () != -1) {
6312                         guint8 *patch;
6313                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6314                         /* we load the value in a separate instruction: this mechanism may be
6315                          * used later as a safer way to do thread interruption
6316                          */
6317                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6318                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6319                         patch = code;
6320                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6321                         /* note that the call trampoline will preserve eax/edx */
6322                         x86_call_reg (code, X86_ECX);
6323                         x86_patch (patch, code);
6324                 } else {
6325                         /* FIXME: maybe save the jit tls in the prolog */
6326                 }
6327                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6328                         /*
6329                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6330                          * through the mono_lmf_addr TLS variable.
6331                          */
6332                         /* reg = previous_lmf */
6333                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6334                         x86_prefix (code, X86_FS_PREFIX);
6335                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6336                 } else {
6337                         /* Restore previous lmf */
6338                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6339                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6340                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6341                 }
6342
6343                 /* Restore caller saved regs */
6344                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6345                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6346                 }
6347                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6348                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6349                 }
6350                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6351                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6352                 }
6353                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6354                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6355                 }
6356                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6357                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6358                 }
6359                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6360                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6361                 }
6362 #ifdef HOST_WIN32
6363                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6364                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6365                 }
6366                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6367                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6368                 }
6369 #endif
6370         } else {
6371
6372                 if (cfg->arch.omit_fp) {
6373                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6374
6375                         for (i = 0; i < AMD64_NREG; ++i)
6376                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6377                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6378                                         save_area_offset += 8;
6379                                 }
6380                 }
6381                 else {
6382                         for (i = 0; i < AMD64_NREG; ++i)
6383                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6384                                         pos -= sizeof (gpointer);
6385
6386                         if (pos) {
6387                                 if (pos == - sizeof (gpointer)) {
6388                                         /* Only one register, so avoid lea */
6389                                         for (i = AMD64_NREG - 1; i > 0; --i)
6390                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6391                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6392                                                 }
6393                                 }
6394                                 else {
6395                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6396
6397                                         /* Pop registers in reverse order */
6398                                         for (i = AMD64_NREG - 1; i > 0; --i)
6399                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6400                                                         amd64_pop_reg (code, i);
6401                                                 }
6402                                 }
6403                         }
6404                 }
6405         }
6406
6407         /* Load returned vtypes into registers if needed */
6408         cinfo = cfg->arch.cinfo;
6409         if (cinfo->ret.storage == ArgValuetypeInReg) {
6410                 ArgInfo *ainfo = &cinfo->ret;
6411                 MonoInst *inst = cfg->ret;
6412
6413                 for (quad = 0; quad < 2; quad ++) {
6414                         switch (ainfo->pair_storage [quad]) {
6415                         case ArgInIReg:
6416                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6417                                 break;
6418                         case ArgInFloatSSEReg:
6419                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6420                                 break;
6421                         case ArgInDoubleSSEReg:
6422                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6423                                 break;
6424                         case ArgNone:
6425                                 break;
6426                         default:
6427                                 g_assert_not_reached ();
6428                         }
6429                 }
6430         }
6431
6432         if (cfg->arch.omit_fp) {
6433                 if (cfg->arch.stack_alloc_size)
6434                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6435         } else {
6436                 amd64_leave (code);
6437         }
6438         async_exc_point (code);
6439         amd64_ret (code);
6440
6441         cfg->code_len = code - cfg->native_code;
6442
6443         g_assert (cfg->code_len < cfg->code_size);
6444 }
6445
6446 void
6447 mono_arch_emit_exceptions (MonoCompile *cfg)
6448 {
6449         MonoJumpInfo *patch_info;
6450         int nthrows, i;
6451         guint8 *code;
6452         MonoClass *exc_classes [16];
6453         guint8 *exc_throw_start [16], *exc_throw_end [16];
6454         guint32 code_size = 0;
6455
6456         /* Compute needed space */
6457         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6458                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6459                         code_size += 40;
6460                 if (patch_info->type == MONO_PATCH_INFO_R8)
6461                         code_size += 8 + 15; /* sizeof (double) + alignment */
6462                 if (patch_info->type == MONO_PATCH_INFO_R4)
6463                         code_size += 4 + 15; /* sizeof (float) + alignment */
6464         }
6465
6466         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6467                 cfg->code_size *= 2;
6468                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6469                 mono_jit_stats.code_reallocs++;
6470         }
6471
6472         code = cfg->native_code + cfg->code_len;
6473
6474         /* add code to raise exceptions */
6475         nthrows = 0;
6476         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6477                 switch (patch_info->type) {
6478                 case MONO_PATCH_INFO_EXC: {
6479                         MonoClass *exc_class;
6480                         guint8 *buf, *buf2;
6481                         guint32 throw_ip;
6482
6483                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6484
6485                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6486                         g_assert (exc_class);
6487                         throw_ip = patch_info->ip.i;
6488
6489                         //x86_breakpoint (code);
6490                         /* Find a throw sequence for the same exception class */
6491                         for (i = 0; i < nthrows; ++i)
6492                                 if (exc_classes [i] == exc_class)
6493                                         break;
6494                         if (i < nthrows) {
6495                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6496                                 x86_jump_code (code, exc_throw_start [i]);
6497                                 patch_info->type = MONO_PATCH_INFO_NONE;
6498                         }
6499                         else {
6500                                 buf = code;
6501                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6502                                 buf2 = code;
6503
6504                                 if (nthrows < 16) {
6505                                         exc_classes [nthrows] = exc_class;
6506                                         exc_throw_start [nthrows] = code;
6507                                 }
6508                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6509
6510                                 patch_info->type = MONO_PATCH_INFO_NONE;
6511
6512                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6513
6514                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6515                                 while (buf < buf2)
6516                                         x86_nop (buf);
6517
6518                                 if (nthrows < 16) {
6519                                         exc_throw_end [nthrows] = code;
6520                                         nthrows ++;
6521                                 }
6522                         }
6523                         break;
6524                 }
6525                 default:
6526                         /* do nothing */
6527                         break;
6528                 }
6529         }
6530
6531         /* Handle relocations with RIP relative addressing */
6532         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6533                 gboolean remove = FALSE;
6534
6535                 switch (patch_info->type) {
6536                 case MONO_PATCH_INFO_R8:
6537                 case MONO_PATCH_INFO_R4: {
6538                         guint8 *pos;
6539
6540                         /* The SSE opcodes require a 16 byte alignment */
6541                         code = (guint8*)ALIGN_TO (code, 16);
6542
6543                         pos = cfg->native_code + patch_info->ip.i;
6544
6545                         if (IS_REX (pos [1]))
6546                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6547                         else
6548                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6549
6550                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6551                                 *(double*)code = *(double*)patch_info->data.target;
6552                                 code += sizeof (double);
6553                         } else {
6554                                 *(float*)code = *(float*)patch_info->data.target;
6555                                 code += sizeof (float);
6556                         }
6557
6558                         remove = TRUE;
6559                         break;
6560                 }
6561                 default:
6562                         break;
6563                 }
6564
6565                 if (remove) {
6566                         if (patch_info == cfg->patch_info)
6567                                 cfg->patch_info = patch_info->next;
6568                         else {
6569                                 MonoJumpInfo *tmp;
6570
6571                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6572                                         ;
6573                                 tmp->next = patch_info->next;
6574                         }
6575                 }
6576         }
6577
6578         cfg->code_len = code - cfg->native_code;
6579
6580         g_assert (cfg->code_len < cfg->code_size);
6581
6582 }
6583
6584 #endif /* DISABLE_JIT */
6585
6586 void*
6587 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6588 {
6589         guchar *code = p;
6590         CallInfo *cinfo = NULL;
6591         MonoMethodSignature *sig;
6592         MonoInst *inst;
6593         int i, n, stack_area = 0;
6594
6595         /* Keep this in sync with mono_arch_get_argument_info */
6596
6597         if (enable_arguments) {
6598                 /* Allocate a new area on the stack and save arguments there */
6599                 sig = mono_method_signature (cfg->method);
6600
6601                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6602
6603                 n = sig->param_count + sig->hasthis;
6604
6605                 stack_area = ALIGN_TO (n * 8, 16);
6606
6607                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6608
6609                 for (i = 0; i < n; ++i) {
6610                         inst = cfg->args [i];
6611
6612                         if (inst->opcode == OP_REGVAR)
6613                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6614                         else {
6615                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6616                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6617                         }
6618                 }
6619         }
6620
6621         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6622         amd64_set_reg_template (code, AMD64_ARG_REG1);
6623         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6624         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6625
6626         if (enable_arguments)
6627                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6628
6629         return code;
6630 }
6631
6632 enum {
6633         SAVE_NONE,
6634         SAVE_STRUCT,
6635         SAVE_EAX,
6636         SAVE_EAX_EDX,
6637         SAVE_XMM
6638 };
6639
6640 void*
6641 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6642 {
6643         guchar *code = p;
6644         int save_mode = SAVE_NONE;
6645         MonoMethod *method = cfg->method;
6646         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6647
6648         switch (ret_type->type) {
6649         case MONO_TYPE_VOID:
6650                 /* special case string .ctor icall */
6651                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6652                         save_mode = SAVE_EAX;
6653                 else
6654                         save_mode = SAVE_NONE;
6655                 break;
6656         case MONO_TYPE_I8:
6657         case MONO_TYPE_U8:
6658                 save_mode = SAVE_EAX;
6659                 break;
6660         case MONO_TYPE_R4:
6661         case MONO_TYPE_R8:
6662                 save_mode = SAVE_XMM;
6663                 break;
6664         case MONO_TYPE_GENERICINST:
6665                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6666                         save_mode = SAVE_EAX;
6667                         break;
6668                 }
6669                 /* Fall through */
6670         case MONO_TYPE_VALUETYPE:
6671                 save_mode = SAVE_STRUCT;
6672                 break;
6673         default:
6674                 save_mode = SAVE_EAX;
6675                 break;
6676         }
6677
6678         /* Save the result and copy it into the proper argument register */
6679         switch (save_mode) {
6680         case SAVE_EAX:
6681                 amd64_push_reg (code, AMD64_RAX);
6682                 /* Align stack */
6683                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6684                 if (enable_arguments)
6685                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6686                 break;
6687         case SAVE_STRUCT:
6688                 /* FIXME: */
6689                 if (enable_arguments)
6690                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6691                 break;
6692         case SAVE_XMM:
6693                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6694                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6695                 /* Align stack */
6696                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6697                 /*
6698                  * The result is already in the proper argument register so no copying
6699                  * needed.
6700                  */
6701                 break;
6702         case SAVE_NONE:
6703                 break;
6704         default:
6705                 g_assert_not_reached ();
6706         }
6707
6708         /* Set %al since this is a varargs call */
6709         if (save_mode == SAVE_XMM)
6710                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6711         else
6712                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6713
6714         if (preserve_argument_registers) {
6715                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6716                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6717         }
6718
6719         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6720         amd64_set_reg_template (code, AMD64_ARG_REG1);
6721         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6722
6723         if (preserve_argument_registers) {
6724                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6725                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6726         }
6727
6728         /* Restore result */
6729         switch (save_mode) {
6730         case SAVE_EAX:
6731                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6732                 amd64_pop_reg (code, AMD64_RAX);
6733                 break;
6734         case SAVE_STRUCT:
6735                 /* FIXME: */
6736                 break;
6737         case SAVE_XMM:
6738                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6739                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6740                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6741                 break;
6742         case SAVE_NONE:
6743                 break;
6744         default:
6745                 g_assert_not_reached ();
6746         }
6747
6748         return code;
6749 }
6750
6751 void
6752 mono_arch_flush_icache (guint8 *code, gint size)
6753 {
6754         /* Not needed */
6755 }
6756
6757 void
6758 mono_arch_flush_register_windows (void)
6759 {
6760 }
6761
6762 gboolean
6763 mono_arch_is_inst_imm (gint64 imm)
6764 {
6765         return amd64_is_imm32 (imm);
6766 }
6767
6768 /*
6769  * Determine whenever the trap whose info is in SIGINFO is caused by
6770  * integer overflow.
6771  */
6772 gboolean
6773 mono_arch_is_int_overflow (void *sigctx, void *info)
6774 {
6775         MonoContext ctx;
6776         guint8* rip;
6777         int reg;
6778         gint64 value;
6779
6780         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6781
6782         rip = (guint8*)ctx.rip;
6783
6784         if (IS_REX (rip [0])) {
6785                 reg = amd64_rex_b (rip [0]);
6786                 rip ++;
6787         }
6788         else
6789                 reg = 0;
6790
6791         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6792                 /* idiv REG */
6793                 reg += x86_modrm_rm (rip [1]);
6794
6795                 switch (reg) {
6796                 case AMD64_RAX:
6797                         value = ctx.rax;
6798                         break;
6799                 case AMD64_RBX:
6800                         value = ctx.rbx;
6801                         break;
6802                 case AMD64_RCX:
6803                         value = ctx.rcx;
6804                         break;
6805                 case AMD64_RDX:
6806                         value = ctx.rdx;
6807                         break;
6808                 case AMD64_RBP:
6809                         value = ctx.rbp;
6810                         break;
6811                 case AMD64_RSP:
6812                         value = ctx.rsp;
6813                         break;
6814                 case AMD64_RSI:
6815                         value = ctx.rsi;
6816                         break;
6817                 case AMD64_RDI:
6818                         value = ctx.rdi;
6819                         break;
6820                 case AMD64_R12:
6821                         value = ctx.r12;
6822                         break;
6823                 case AMD64_R13:
6824                         value = ctx.r13;
6825                         break;
6826                 case AMD64_R14:
6827                         value = ctx.r14;
6828                         break;
6829                 case AMD64_R15:
6830                         value = ctx.r15;
6831                         break;
6832                 default:
6833                         g_assert_not_reached ();
6834                         reg = -1;
6835                 }
6836
6837                 if (value == -1)
6838                         return TRUE;
6839         }
6840
6841         return FALSE;
6842 }
6843
6844 guint32
6845 mono_arch_get_patch_offset (guint8 *code)
6846 {
6847         return 3;
6848 }
6849
6850 /**
6851  * mono_breakpoint_clean_code:
6852  *
6853  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6854  * breakpoints in the original code, they are removed in the copy.
6855  *
6856  * Returns TRUE if no sw breakpoint was present.
6857  */
6858 gboolean
6859 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6860 {
6861         int i;
6862         gboolean can_write = TRUE;
6863         /*
6864          * If method_start is non-NULL we need to perform bound checks, since we access memory
6865          * at code - offset we could go before the start of the method and end up in a different
6866          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6867          * instead.
6868          */
6869         if (!method_start || code - offset >= method_start) {
6870                 memcpy (buf, code - offset, size);
6871         } else {
6872                 int diff = code - method_start;
6873                 memset (buf, 0, size);
6874                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6875         }
6876         code -= offset;
6877         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6878                 int idx = mono_breakpoint_info_index [i];
6879                 guint8 *ptr;
6880                 if (idx < 1)
6881                         continue;
6882                 ptr = mono_breakpoint_info [idx].address;
6883                 if (ptr >= code && ptr < code + size) {
6884                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6885                         can_write = FALSE;
6886                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6887                         buf [ptr - code] = saved_byte;
6888                 }
6889         }
6890         return can_write;
6891 }
6892
6893 gpointer
6894 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6895 {
6896         guint8 buf [10];
6897         guint32 reg;
6898         gint32 disp;
6899         guint8 rex = 0;
6900         MonoJitInfo *ji = NULL;
6901
6902 #ifdef ENABLE_LLVM
6903         /* code - 9 might be before the start of the method */
6904         /* FIXME: Avoid this expensive call somehow */
6905         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6906 #endif
6907
6908         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6909         code = buf + 9;
6910
6911         *displacement = 0;
6912
6913         code -= 7;
6914
6915         /*
6916          * A given byte sequence can match more than case here, so we have to be
6917          * really careful about the ordering of the cases. Longer sequences
6918          * come first.
6919          * There are two types of calls:
6920          * - direct calls: 0xff address_byte 8/32 bits displacement
6921          * - indirect calls: nop nop nop <call>
6922          * The nops make sure we don't confuse the instruction preceeding an indirect
6923          * call with a direct call.
6924          */
6925         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6926                 /* call OFFSET(%rip) */
6927                 disp = *(guint32*)(code + 3);
6928                 return (gpointer*)(code + disp + 7);
6929         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6930                 /* call *[reg+disp32] using indexed addressing */
6931                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6932                 if (IS_REX (code [-1])) {
6933                         rex = code [-1];
6934                         g_assert (amd64_rex_x (rex) == 0);
6935                 }
6936                 reg = amd64_sib_base (code [2]);
6937                 disp = *(gint32*)(code + 3);
6938         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6939                 /* call *[reg+disp32] */
6940                 if (IS_REX (code [0]))
6941                         rex = code [0];
6942                 reg = amd64_modrm_rm (code [2]);
6943                 disp = *(gint32*)(code + 3);
6944                 /* R10 is clobbered by the IMT thunk code */
6945                 g_assert (reg != AMD64_R10);
6946         } else if (code [2] == 0xe8) {
6947                 /* call <ADDR> */
6948                 return NULL;
6949         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6950                 /* call *[r12+disp8] using indexed addressing */
6951                 if (IS_REX (code [2]))
6952                         rex = code [2];
6953                 reg = amd64_sib_base (code [5]);
6954                 disp = *(gint8*)(code + 6);
6955         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6956                 /* call *%reg */
6957                 return NULL;
6958         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6959                 /* call *[reg+disp8] */
6960                 if (IS_REX (code [3]))
6961                         rex = code [3];
6962                 reg = amd64_modrm_rm (code [5]);
6963                 disp = *(gint8*)(code + 6);
6964                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6965         }
6966         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6967                 /* call *%reg */
6968                 if (IS_REX (code [4]))
6969                         rex = code [4];
6970                 reg = amd64_modrm_rm (code [6]);
6971                 disp = 0;
6972         }
6973         else
6974                 g_assert_not_reached ();
6975
6976         reg += amd64_rex_b (rex);
6977
6978         /* R11 is clobbered by the trampoline code */
6979         g_assert (reg != AMD64_R11);
6980
6981         *displacement = disp;
6982         return (gpointer)regs [reg];
6983 }
6984
6985 int
6986 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6987 {
6988         int this_reg = AMD64_ARG_REG1;
6989
6990         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6991                 CallInfo *cinfo;
6992
6993                 if (!gsctx && code)
6994                         gsctx = mono_get_generic_context_from_code (code);
6995
6996                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6997
6998                 if (cinfo->ret.storage != ArgValuetypeInReg)
6999                         this_reg = AMD64_ARG_REG2;
7000                 g_free (cinfo);
7001         }
7002
7003         return this_reg;
7004 }
7005
7006 gpointer
7007 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
7008 {
7009         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
7010 }
7011
7012 #define MAX_ARCH_DELEGATE_PARAMS 10
7013
7014 static gpointer
7015 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7016 {
7017         guint8 *code, *start;
7018         int i;
7019
7020         if (has_target) {
7021                 start = code = mono_global_codeman_reserve (64);
7022
7023                 /* Replace the this argument with the target */
7024                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7025                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7026                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7027
7028                 g_assert ((code - start) < 64);
7029         } else {
7030                 start = code = mono_global_codeman_reserve (64);
7031
7032                 if (param_count == 0) {
7033                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7034                 } else {
7035                         /* We have to shift the arguments left */
7036                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7037                         for (i = 0; i < param_count; ++i) {
7038 #ifdef HOST_WIN32
7039                                 if (i < 3)
7040                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7041                                 else
7042                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7043 #else
7044                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7045 #endif
7046                         }
7047
7048                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7049                 }
7050                 g_assert ((code - start) < 64);
7051         }
7052
7053         mono_debug_add_delegate_trampoline (start, code - start);
7054
7055         if (code_len)
7056                 *code_len = code - start;
7057
7058         return start;
7059 }
7060
7061 /*
7062  * mono_arch_get_delegate_invoke_impls:
7063  *
7064  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
7065  * trampolines.
7066  */
7067 GSList*
7068 mono_arch_get_delegate_invoke_impls (void)
7069 {
7070         GSList *res = NULL;
7071         guint8 *code;
7072         guint32 code_len;
7073         int i;
7074
7075         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7076         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
7077
7078         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7079                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7080                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
7081         }
7082
7083         return res;
7084 }
7085
7086 gpointer
7087 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7088 {
7089         guint8 *code, *start;
7090         int i;
7091
7092         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7093                 return NULL;
7094
7095         /* FIXME: Support more cases */
7096         if (MONO_TYPE_ISSTRUCT (sig->ret))
7097                 return NULL;
7098
7099         if (has_target) {
7100                 static guint8* cached = NULL;
7101
7102                 if (cached)
7103                         return cached;
7104
7105                 if (mono_aot_only)
7106                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7107                 else
7108                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7109
7110                 mono_memory_barrier ();
7111
7112                 cached = start;
7113         } else {
7114                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7115                 for (i = 0; i < sig->param_count; ++i)
7116                         if (!mono_is_regsize_var (sig->params [i]))
7117                                 return NULL;
7118                 if (sig->param_count > 4)
7119                         return NULL;
7120
7121                 code = cache [sig->param_count];
7122                 if (code)
7123                         return code;
7124
7125                 if (mono_aot_only) {
7126                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7127                         start = mono_aot_get_named_code (name);
7128                         g_free (name);
7129                 } else {
7130                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7131                 }
7132
7133                 mono_memory_barrier ();
7134
7135                 cache [sig->param_count] = start;
7136         }
7137
7138         return start;
7139 }
7140
7141 /*
7142  * Support for fast access to the thread-local lmf structure using the GS
7143  * segment register on NPTL + kernel 2.6.x.
7144  */
7145
7146 static gboolean tls_offset_inited = FALSE;
7147
7148 void
7149 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7150 {
7151         if (!tls_offset_inited) {
7152 #ifdef HOST_WIN32
7153                 /*
7154                  * We need to init this multiple times, since when we are first called, the key might not
7155                  * be initialized yet.
7156                  */
7157                 appdomain_tls_offset = mono_domain_get_tls_key ();
7158                 lmf_tls_offset = mono_get_jit_tls_key ();
7159                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7160
7161                 /* Only 64 tls entries can be accessed using inline code */
7162                 if (appdomain_tls_offset >= 64)
7163                         appdomain_tls_offset = -1;
7164                 if (lmf_tls_offset >= 64)
7165                         lmf_tls_offset = -1;
7166 #else
7167                 tls_offset_inited = TRUE;
7168 #ifdef MONO_XEN_OPT
7169                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7170 #endif
7171                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7172                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7173                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7174 #endif
7175         }
7176 }
7177
7178 void
7179 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7180 {
7181 }
7182
7183 #ifdef MONO_ARCH_HAVE_IMT
7184
7185 #define CMP_SIZE (6 + 1)
7186 #define CMP_REG_REG_SIZE (4 + 1)
7187 #define BR_SMALL_SIZE 2
7188 #define BR_LARGE_SIZE 6
7189 #define MOV_REG_IMM_SIZE 10
7190 #define MOV_REG_IMM_32BIT_SIZE 6
7191 #define JUMP_REG_SIZE (2 + 1)
7192
7193 static int
7194 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7195 {
7196         int i, distance = 0;
7197         for (i = start; i < target; ++i)
7198                 distance += imt_entries [i]->chunk_size;
7199         return distance;
7200 }
7201
7202 /*
7203  * LOCKING: called with the domain lock held
7204  */
7205 gpointer
7206 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7207         gpointer fail_tramp)
7208 {
7209         int i;
7210         int size = 0;
7211         guint8 *code, *start;
7212         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7213
7214         for (i = 0; i < count; ++i) {
7215                 MonoIMTCheckItem *item = imt_entries [i];
7216                 if (item->is_equals) {
7217                         if (item->check_target_idx) {
7218                                 if (!item->compare_done) {
7219                                         if (amd64_is_imm32 (item->key))
7220                                                 item->chunk_size += CMP_SIZE;
7221                                         else
7222                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7223                                 }
7224                                 if (item->has_target_code) {
7225                                         item->chunk_size += MOV_REG_IMM_SIZE;
7226                                 } else {
7227                                         if (vtable_is_32bit)
7228                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7229                                         else
7230                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7231                                 }
7232                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7233                         } else {
7234                                 if (fail_tramp) {
7235                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7236                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7237                                 } else {
7238                                         if (vtable_is_32bit)
7239                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7240                                         else
7241                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7242                                         item->chunk_size += JUMP_REG_SIZE;
7243                                         /* with assert below:
7244                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7245                                          */
7246                                 }
7247                         }
7248                 } else {
7249                         if (amd64_is_imm32 (item->key))
7250                                 item->chunk_size += CMP_SIZE;
7251                         else
7252                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7253                         item->chunk_size += BR_LARGE_SIZE;
7254                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7255                 }
7256                 size += item->chunk_size;
7257         }
7258         if (fail_tramp)
7259                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7260         else
7261                 code = mono_domain_code_reserve (domain, size);
7262         start = code;
7263         for (i = 0; i < count; ++i) {
7264                 MonoIMTCheckItem *item = imt_entries [i];
7265                 item->code_target = code;
7266                 if (item->is_equals) {
7267                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7268
7269                         if (item->check_target_idx || fail_case) {
7270                                 if (!item->compare_done || fail_case) {
7271                                         if (amd64_is_imm32 (item->key))
7272                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7273                                         else {
7274                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7275                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7276                                         }
7277                                 }
7278                                 item->jmp_code = code;
7279                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7280                                 /* See the comment below about R10 */
7281                                 if (item->has_target_code) {
7282                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7283                                         amd64_jump_reg (code, AMD64_R10);
7284                                 } else {
7285                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7286                                         amd64_jump_membase (code, AMD64_R10, 0);
7287                                 }
7288
7289                                 if (fail_case) {
7290                                         amd64_patch (item->jmp_code, code);
7291                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7292                                         amd64_jump_reg (code, AMD64_R10);
7293                                         item->jmp_code = NULL;
7294                                 }
7295                         } else {
7296                                 /* enable the commented code to assert on wrong method */
7297 #if 0
7298                                 if (amd64_is_imm32 (item->key))
7299                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7300                                 else {
7301                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7302                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7303                                 }
7304                                 item->jmp_code = code;
7305                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7306                                 /* See the comment below about R10 */
7307                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7308                                 amd64_jump_membase (code, AMD64_R10, 0);
7309                                 amd64_patch (item->jmp_code, code);
7310                                 amd64_breakpoint (code);
7311                                 item->jmp_code = NULL;
7312 #else
7313                                 /* We're using R10 here because R11
7314                                    needs to be preserved.  R10 needs
7315                                    to be preserved for calls which
7316                                    require a runtime generic context,
7317                                    but interface calls don't. */
7318                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7319                                 amd64_jump_membase (code, AMD64_R10, 0);
7320 #endif
7321                         }
7322                 } else {
7323                         if (amd64_is_imm32 (item->key))
7324                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7325                         else {
7326                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7327                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7328                         }
7329                         item->jmp_code = code;
7330                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7331                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7332                         else
7333                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7334                 }
7335                 g_assert (code - item->code_target <= item->chunk_size);
7336         }
7337         /* patch the branches to get to the target items */
7338         for (i = 0; i < count; ++i) {
7339                 MonoIMTCheckItem *item = imt_entries [i];
7340                 if (item->jmp_code) {
7341                         if (item->check_target_idx) {
7342                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7343                         }
7344                 }
7345         }
7346
7347         if (!fail_tramp)
7348                 mono_stats.imt_thunks_size += code - start;
7349         g_assert (code - start <= size);
7350
7351         return start;
7352 }
7353
7354 MonoMethod*
7355 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7356 {
7357         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7358 }
7359 #endif
7360
7361 MonoVTable*
7362 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7363 {
7364         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7365 }
7366
7367 GSList*
7368 mono_arch_get_cie_program (void)
7369 {
7370         GSList *l = NULL;
7371
7372         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7373         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7374
7375         return l;
7376 }
7377
7378 MonoInst*
7379 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7380 {
7381         MonoInst *ins = NULL;
7382         int opcode = 0;
7383
7384         if (cmethod->klass == mono_defaults.math_class) {
7385                 if (strcmp (cmethod->name, "Sin") == 0) {
7386                         opcode = OP_SIN;
7387                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7388                         opcode = OP_COS;
7389                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7390                         opcode = OP_SQRT;
7391                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7392                         opcode = OP_ABS;
7393                 }
7394
7395                 if (opcode) {
7396                         MONO_INST_NEW (cfg, ins, opcode);
7397                         ins->type = STACK_R8;
7398                         ins->dreg = mono_alloc_freg (cfg);
7399                         ins->sreg1 = args [0]->dreg;
7400                         MONO_ADD_INS (cfg->cbb, ins);
7401                 }
7402
7403                 opcode = 0;
7404                 if (cfg->opt & MONO_OPT_CMOV) {
7405                         if (strcmp (cmethod->name, "Min") == 0) {
7406                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7407                                         opcode = OP_IMIN;
7408                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7409                                         opcode = OP_IMIN_UN;
7410                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7411                                         opcode = OP_LMIN;
7412                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7413                                         opcode = OP_LMIN_UN;
7414                         } else if (strcmp (cmethod->name, "Max") == 0) {
7415                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7416                                         opcode = OP_IMAX;
7417                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7418                                         opcode = OP_IMAX_UN;
7419                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7420                                         opcode = OP_LMAX;
7421                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7422                                         opcode = OP_LMAX_UN;
7423                         }
7424                 }
7425
7426                 if (opcode) {
7427                         MONO_INST_NEW (cfg, ins, opcode);
7428                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7429                         ins->dreg = mono_alloc_ireg (cfg);
7430                         ins->sreg1 = args [0]->dreg;
7431                         ins->sreg2 = args [1]->dreg;
7432                         MONO_ADD_INS (cfg->cbb, ins);
7433                 }
7434
7435 #if 0
7436                 /* OP_FREM is not IEEE compatible */
7437                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7438                         MONO_INST_NEW (cfg, ins, OP_FREM);
7439                         ins->inst_i0 = args [0];
7440                         ins->inst_i1 = args [1];
7441                 }
7442 #endif
7443         }
7444
7445         /*
7446          * Can't implement CompareExchange methods this way since they have
7447          * three arguments.
7448          */
7449
7450         return ins;
7451 }
7452
7453 gboolean
7454 mono_arch_print_tree (MonoInst *tree, int arity)
7455 {
7456         return 0;
7457 }
7458
7459 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7460 {
7461         MonoInst* ins;
7462
7463         if (appdomain_tls_offset == -1)
7464                 return NULL;
7465
7466         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7467         ins->inst_offset = appdomain_tls_offset;
7468         return ins;
7469 }
7470
7471 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7472
7473 gpointer
7474 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7475 {
7476         switch (reg) {
7477         case AMD64_RCX: return (gpointer)ctx->rcx;
7478         case AMD64_RDX: return (gpointer)ctx->rdx;
7479         case AMD64_RBX: return (gpointer)ctx->rbx;
7480         case AMD64_RBP: return (gpointer)ctx->rbp;
7481         case AMD64_RSP: return (gpointer)ctx->rsp;
7482         default:
7483                 if (reg < 8)
7484                         return _CTX_REG (ctx, rax, reg);
7485                 else if (reg >= 12)
7486                         return _CTX_REG (ctx, r12, reg - 12);
7487                 else
7488                         g_assert_not_reached ();
7489         }
7490 }
7491
7492 /* Soft Debug support */
7493 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7494
7495 /*
7496  * mono_arch_set_breakpoint:
7497  *
7498  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7499  * The location should contain code emitted by OP_SEQ_POINT.
7500  */
7501 void
7502 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7503 {
7504         guint8 *code = ip;
7505         guint8 *orig_code = code;
7506
7507         /*
7508          * In production, we will use int3 (has to fix the size in the md
7509          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7510          * instead.
7511          */
7512         g_assert (code [0] == 0x90);
7513         if (breakpoint_size == 8) {
7514                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7515         } else {
7516                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7517                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7518         }
7519
7520         g_assert (code - orig_code == breakpoint_size);
7521 }
7522
7523 /*
7524  * mono_arch_clear_breakpoint:
7525  *
7526  *   Clear the breakpoint at IP.
7527  */
7528 void
7529 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7530 {
7531         guint8 *code = ip;
7532         int i;
7533
7534         for (i = 0; i < breakpoint_size; ++i)
7535                 x86_nop (code);
7536 }
7537
7538 gboolean
7539 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7540 {
7541 #ifdef HOST_WIN32
7542         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7543         return FALSE;
7544 #else
7545         siginfo_t* sinfo = (siginfo_t*) info;
7546         /* Sometimes the address is off by 4 */
7547         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7548                 return TRUE;
7549         else
7550                 return FALSE;
7551 #endif
7552 }
7553
7554 /*
7555  * mono_arch_get_ip_for_breakpoint:
7556  *
7557  *   Convert the ip in CTX to the address where a breakpoint was placed.
7558  */
7559 guint8*
7560 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7561 {
7562         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7563
7564         /* ip points to the instruction causing the fault */
7565         ip -= (breakpoint_size - breakpoint_fault_size);
7566
7567         return ip;
7568 }
7569
7570 /*
7571  * mono_arch_skip_breakpoint:
7572  *
7573  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7574  * we resume, the instruction is not executed again.
7575  */
7576 void
7577 mono_arch_skip_breakpoint (MonoContext *ctx)
7578 {
7579         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7580 }
7581
7582 /*
7583  * mono_arch_start_single_stepping:
7584  *
7585  *   Start single stepping.
7586  */
7587 void
7588 mono_arch_start_single_stepping (void)
7589 {
7590         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7591 }
7592
7593 /*
7594  * mono_arch_stop_single_stepping:
7595  *
7596  *   Stop single stepping.
7597  */
7598 void
7599 mono_arch_stop_single_stepping (void)
7600 {
7601         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7602 }
7603
7604 /*
7605  * mono_arch_is_single_step_event:
7606  *
7607  *   Return whenever the machine state in SIGCTX corresponds to a single
7608  * step event.
7609  */
7610 gboolean
7611 mono_arch_is_single_step_event (void *info, void *sigctx)
7612 {
7613 #ifdef HOST_WIN32
7614         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7615         return FALSE;
7616 #else
7617         siginfo_t* sinfo = (siginfo_t*) info;
7618         /* Sometimes the address is off by 4 */
7619         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7620                 return TRUE;
7621         else
7622                 return FALSE;
7623 #endif
7624 }
7625
7626 /*
7627  * mono_arch_get_ip_for_single_step:
7628  *
7629  *   Convert the ip in CTX to the address stored in seq_points.
7630  */
7631 guint8*
7632 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7633 {
7634         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7635
7636         ip += single_step_fault_size;
7637
7638         return ip;
7639 }
7640
7641 /*
7642  * mono_arch_skip_single_step:
7643  *
7644  *   Modify CTX so the ip is placed after the single step trigger instruction,
7645  * we resume, the instruction is not executed again.
7646  */
7647 void
7648 mono_arch_skip_single_step (MonoContext *ctx)
7649 {
7650         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7651 }
7652
7653 /*
7654  * mono_arch_create_seq_point_info:
7655  *
7656  *   Return a pointer to a data structure which is used by the sequence
7657  * point implementation in AOTed code.
7658  */
7659 gpointer
7660 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7661 {
7662         NOT_IMPLEMENTED;
7663         return NULL;
7664 }
7665
7666 #endif