2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
33 #include <mono/utils/mono-hwcap-x86.h>
37 #include "mini-amd64.h"
38 #include "cpu-amd64.h"
39 #include "debugger-agent.h"
42 static gint lmf_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
44 static gint appdomain_tls_offset = -1;
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
68 static CRITICAL_SECTION mini_arch_mutex;
71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 /* Structure used by the sequence points in AOTed code */
75 gpointer ss_trigger_page;
76 gpointer bp_trigger_page;
77 gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
81 * The code generated for sequence points reads from this location, which is
82 * made read-only when single stepping is enabled.
84 static gpointer ss_trigger_page;
86 /* Enabled breakpoints read from this trigger page */
87 static gpointer bp_trigger_page;
89 /* The size of the breakpoint sequence */
90 static int breakpoint_size;
92 /* The size of the breakpoint instruction causing the actual fault */
93 static int breakpoint_fault_size;
95 /* The size of the single step instruction causing the actual fault */
96 static int single_step_fault_size;
99 /* On Win64 always reserve first 32 bytes for first four arguments */
100 #define ARGS_OFFSET 48
102 #define ARGS_OFFSET 16
104 #define GP_SCRATCH_REG AMD64_R11
107 * AMD64 register usage:
108 * - callee saved registers are used for global register allocation
109 * - %r11 is used for materializing 64 bit constants in opcodes
110 * - the rest is used for local allocation
114 * Floating point comparison results:
124 mono_arch_regname (int reg)
127 case AMD64_RAX: return "%rax";
128 case AMD64_RBX: return "%rbx";
129 case AMD64_RCX: return "%rcx";
130 case AMD64_RDX: return "%rdx";
131 case AMD64_RSP: return "%rsp";
132 case AMD64_RBP: return "%rbp";
133 case AMD64_RDI: return "%rdi";
134 case AMD64_RSI: return "%rsi";
135 case AMD64_R8: return "%r8";
136 case AMD64_R9: return "%r9";
137 case AMD64_R10: return "%r10";
138 case AMD64_R11: return "%r11";
139 case AMD64_R12: return "%r12";
140 case AMD64_R13: return "%r13";
141 case AMD64_R14: return "%r14";
142 case AMD64_R15: return "%r15";
147 static const char * packed_xmmregs [] = {
148 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
149 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
152 static const char * single_xmmregs [] = {
153 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
154 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
158 mono_arch_fregname (int reg)
160 if (reg < AMD64_XMM_NREG)
161 return single_xmmregs [reg];
167 mono_arch_xregname (int reg)
169 if (reg < AMD64_XMM_NREG)
170 return packed_xmmregs [reg];
179 return mono_debug_count ();
185 static inline gboolean
186 amd64_is_near_call (guint8 *code)
189 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
192 return code [0] == 0xe8;
195 #ifdef __native_client_codegen__
197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
198 /* for any given instruction. For instance, amd64_call_reg resolves to */
199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
200 /* We only want to force bundle alignment for the top level instruction, */
201 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
202 static MonoNativeTlsKey nacl_instruction_depth;
204 static MonoNativeTlsKey nacl_rex_tag;
205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
208 amd64_nacl_clear_legacy_prefix_tag ()
210 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
214 amd64_nacl_tag_legacy_prefix (guint8* code)
216 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
217 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
221 amd64_nacl_tag_rex (guint8* code)
223 mono_native_tls_set_value (nacl_rex_tag, code);
227 amd64_nacl_get_legacy_prefix_tag ()
229 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
233 amd64_nacl_get_rex_tag ()
235 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
238 /* Increment the instruction "depth" described above */
240 amd64_nacl_instruction_pre ()
242 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
244 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
248 /* alignment if depth == 0 (top level instruction) */
249 /* IN: start, end pointers to instruction beginning and end */
250 /* OUT: start, end pointers to beginning and end after possible alignment */
251 /* GLOBALS: nacl_instruction_depth defined above */
253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
255 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
257 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
259 g_assert ( depth >= 0 );
261 uintptr_t space_in_block;
263 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
264 /* if legacy prefix is present, and if it was emitted before */
265 /* the start of the instruction sequence, adjust the start */
266 if (prefix != NULL && prefix < *start) {
267 g_assert (*start - prefix <= 3);/* only 3 are allowed */
270 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
271 instlen = (uintptr_t)(*end - *start);
272 /* Only check for instructions which are less than */
273 /* kNaClAlignment. The only instructions that should ever */
274 /* be that long are call sequences, which are already */
275 /* padded out to align the return to the next bundle. */
276 if (instlen > space_in_block && instlen < kNaClAlignment) {
277 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
278 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
279 const size_t length = (size_t)((*end)-(*start));
280 g_assert (length < MAX_NACL_INST_LENGTH);
282 memcpy (copy_of_instruction, *start, length);
283 *start = mono_arch_nacl_pad (*start, space_in_block);
284 memcpy (*start, copy_of_instruction, length);
285 *end = *start + length;
287 amd64_nacl_clear_legacy_prefix_tag ();
288 amd64_nacl_tag_rex (NULL);
292 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
293 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
294 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
295 /* make sure the upper 32-bits are cleared, and use that register in the */
296 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
298 /* pointer to current instruction stream (in the */
299 /* middle of an instruction, after opcode is emitted) */
300 /* basereg/offset/dreg */
301 /* operands of normal membase address */
303 /* pointer to the end of the membase/memindex emit */
304 /* GLOBALS: nacl_rex_tag */
305 /* position in instruction stream that rex prefix was emitted */
306 /* nacl_legacy_prefix_tag */
307 /* (possibly NULL) position in instruction of legacy x86 prefix */
309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
311 gint8 true_basereg = basereg;
313 /* Cache these values, they might change */
314 /* as new instructions are emitted below. */
315 guint8* rex_tag = amd64_nacl_get_rex_tag ();
316 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
318 /* 'basereg' is given masked to 0x7 at this point, so check */
319 /* the rex prefix to see if this is an extended register. */
320 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
324 #define X86_LEA_OPCODE (0x8D)
326 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
327 guint8* old_instruction_start;
329 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
330 /* 32-bits of the old base register (new index register) */
332 guint8* buf_ptr = buf;
335 g_assert (rex_tag != NULL);
337 if (IS_REX(*rex_tag)) {
338 /* The old rex.B should be the new rex.X */
339 if (*rex_tag & AMD64_REX_B) {
340 *rex_tag |= AMD64_REX_X;
342 /* Since our new base is %r15 set rex.B */
343 *rex_tag |= AMD64_REX_B;
345 /* Shift the instruction by one byte */
346 /* so we can insert a rex prefix */
347 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
349 /* New rex prefix only needs rex.B for %r15 base */
350 *rex_tag = AMD64_REX(AMD64_REX_B);
353 if (legacy_prefix_tag) {
354 old_instruction_start = legacy_prefix_tag;
356 old_instruction_start = rex_tag;
359 /* Clears the upper 32-bits of the previous base register */
360 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
361 insert_len = buf_ptr - buf;
363 /* Move the old instruction forward to make */
364 /* room for 'mov' stored in 'buf_ptr' */
365 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
367 memcpy (old_instruction_start, buf, insert_len);
369 /* Sandboxed replacement for the normal membase_emit */
370 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
373 /* Normal default behavior, emit membase memory location */
374 x86_membase_emit_body (*code, dreg, basereg, offset);
379 static inline unsigned char*
380 amd64_skip_nops (unsigned char* code)
385 if ( code[0] == 0x90) {
389 if ( code[0] == 0x66 && code[1] == 0x90) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x00) {
398 if (code[0] == 0x0f && code[1] == 0x1f
399 && code[2] == 0x40 && code[3] == 0x00) {
403 if (code[0] == 0x0f && code[1] == 0x1f
404 && code[2] == 0x44 && code[3] == 0x00
405 && code[4] == 0x00) {
409 if (code[0] == 0x66 && code[1] == 0x0f
410 && code[2] == 0x1f && code[3] == 0x44
411 && code[4] == 0x00 && code[5] == 0x00) {
415 if (code[0] == 0x0f && code[1] == 0x1f
416 && code[2] == 0x80 && code[3] == 0x00
417 && code[4] == 0x00 && code[5] == 0x00
418 && code[6] == 0x00) {
422 if (code[0] == 0x0f && code[1] == 0x1f
423 && code[2] == 0x84 && code[3] == 0x00
424 && code[4] == 0x00 && code[5] == 0x00
425 && code[6] == 0x00 && code[7] == 0x00) {
434 mono_arch_nacl_skip_nops (guint8* code)
436 return amd64_skip_nops(code);
439 #endif /*__native_client_codegen__*/
442 amd64_patch (unsigned char* code, gpointer target)
446 #ifdef __native_client_codegen__
447 code = amd64_skip_nops (code);
449 #if defined(__native_client_codegen__) && defined(__native_client__)
450 if (nacl_is_code_address (code)) {
451 /* For tail calls, code is patched after being installed */
452 /* but not through the normal "patch callsite" method. */
453 unsigned char buf[kNaClAlignment];
454 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
456 memcpy (buf, aligned_code, kNaClAlignment);
457 /* Patch a temp buffer of bundle size, */
458 /* then install to actual location. */
459 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
460 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
464 target = nacl_modify_patch_target (target);
468 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
473 if ((code [0] & 0xf8) == 0xb8) {
474 /* amd64_set_reg_template */
475 *(guint64*)(code + 1) = (guint64)target;
477 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
478 /* mov 0(%rip), %dreg */
479 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
481 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
482 /* call *<OFFSET>(%rip) */
483 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
485 else if (code [0] == 0xe8) {
487 gint64 disp = (guint8*)target - (guint8*)code;
488 g_assert (amd64_is_imm32 (disp));
489 x86_patch (code, (unsigned char*)target);
492 x86_patch (code, (unsigned char*)target);
496 mono_amd64_patch (unsigned char* code, gpointer target)
498 amd64_patch (code, target);
507 ArgValuetypeAddrInIReg,
508 ArgNone /* only in pair_storage */
516 /* Only if storage == ArgValuetypeInReg */
517 ArgStorage pair_storage [2];
527 gboolean need_stack_align;
528 gboolean vtype_retaddr;
529 /* The index of the vret arg in the argument list */
536 #define DEBUG(a) if (cfg->verbose_level > 1) a
541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
549 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
555 ainfo->offset = *stack_size;
557 if (*gr >= PARAM_REGS) {
558 ainfo->storage = ArgOnStack;
559 /* Since the same stack slot size is used for all arg */
560 /* types, it needs to be big enough to hold them all */
561 (*stack_size) += sizeof(mgreg_t);
564 ainfo->storage = ArgInIReg;
565 ainfo->reg = param_regs [*gr];
571 #define FLOAT_PARAM_REGS 4
573 #define FLOAT_PARAM_REGS 8
577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
579 ainfo->offset = *stack_size;
581 if (*gr >= FLOAT_PARAM_REGS) {
582 ainfo->storage = ArgOnStack;
583 /* Since the same stack slot size is used for both float */
584 /* types, it needs to be big enough to hold them both */
585 (*stack_size) += sizeof(mgreg_t);
588 /* A double register */
590 ainfo->storage = ArgInDoubleSSEReg;
592 ainfo->storage = ArgInFloatSSEReg;
598 typedef enum ArgumentClass {
606 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
608 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
611 ptype = mini_type_get_underlying_type (NULL, type);
612 switch (ptype->type) {
613 case MONO_TYPE_BOOLEAN:
623 case MONO_TYPE_STRING:
624 case MONO_TYPE_OBJECT:
625 case MONO_TYPE_CLASS:
626 case MONO_TYPE_SZARRAY:
628 case MONO_TYPE_FNPTR:
629 case MONO_TYPE_ARRAY:
632 class2 = ARG_CLASS_INTEGER;
637 class2 = ARG_CLASS_INTEGER;
639 class2 = ARG_CLASS_SSE;
643 case MONO_TYPE_TYPEDBYREF:
644 g_assert_not_reached ();
646 case MONO_TYPE_GENERICINST:
647 if (!mono_type_generic_inst_is_valuetype (ptype)) {
648 class2 = ARG_CLASS_INTEGER;
652 case MONO_TYPE_VALUETYPE: {
653 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
656 for (i = 0; i < info->num_fields; ++i) {
658 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
663 g_assert_not_reached ();
667 if (class1 == class2)
669 else if (class1 == ARG_CLASS_NO_CLASS)
671 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
672 class1 = ARG_CLASS_MEMORY;
673 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
674 class1 = ARG_CLASS_INTEGER;
676 class1 = ARG_CLASS_SSE;
680 #ifdef __native_client_codegen__
682 /* Default alignment for Native Client is 32-byte. */
683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
686 /* Check that alignment doesn't cross an alignment boundary. */
688 mono_arch_nacl_pad(guint8 *code, int pad)
690 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
692 if (pad == 0) return code;
693 /* assertion: alignment cannot cross a block boundary */
694 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
695 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
696 while (pad >= kMaxPadding) {
697 amd64_padding (code, kMaxPadding);
700 if (pad != 0) amd64_padding (code, pad);
706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
708 guint32 *gr, guint32 *fr, guint32 *stack_size)
710 guint32 size, quad, nquads, i;
711 /* Keep track of the size used in each quad so we can */
712 /* use the right size when copying args/return vars. */
713 guint32 quadsize [2] = {8, 8};
714 ArgumentClass args [2];
715 MonoMarshalType *info = NULL;
717 MonoGenericSharingContext tmp_gsctx;
718 gboolean pass_on_stack = FALSE;
721 * The gsctx currently contains no data, it is only used for checking whenever
722 * open types are allowed, some callers like mono_arch_get_argument_info ()
723 * don't pass it to us, so work around that.
728 klass = mono_class_from_mono_type (type);
729 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
731 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
732 /* We pass and return vtypes of size 8 in a register */
733 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
734 pass_on_stack = TRUE;
738 pass_on_stack = TRUE;
742 /* If this struct can't be split up naturally into 8-byte */
743 /* chunks (registers), pass it on the stack. */
744 if (sig->pinvoke && !pass_on_stack) {
748 info = mono_marshal_load_type_info (klass);
750 for (i = 0; i < info->num_fields; ++i) {
751 field_size = mono_marshal_type_size (info->fields [i].field->type,
752 info->fields [i].mspec,
753 &align, TRUE, klass->unicode);
754 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
755 pass_on_stack = TRUE;
762 /* Allways pass in memory */
763 ainfo->offset = *stack_size;
764 *stack_size += ALIGN_TO (size, 8);
765 ainfo->storage = ArgOnStack;
770 /* FIXME: Handle structs smaller than 8 bytes */
771 //if ((size % 8) != 0)
780 /* Always pass in 1 or 2 integer registers */
781 args [0] = ARG_CLASS_INTEGER;
782 args [1] = ARG_CLASS_INTEGER;
783 /* Only the simplest cases are supported */
784 if (is_return && nquads != 1) {
785 args [0] = ARG_CLASS_MEMORY;
786 args [1] = ARG_CLASS_MEMORY;
790 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
791 * The X87 and SSEUP stuff is left out since there are no such types in
794 info = mono_marshal_load_type_info (klass);
798 if (info->native_size > 16) {
799 ainfo->offset = *stack_size;
800 *stack_size += ALIGN_TO (info->native_size, 8);
801 ainfo->storage = ArgOnStack;
806 switch (info->native_size) {
807 case 1: case 2: case 4: case 8:
811 ainfo->storage = ArgOnStack;
812 ainfo->offset = *stack_size;
813 *stack_size += ALIGN_TO (info->native_size, 8);
816 ainfo->storage = ArgValuetypeAddrInIReg;
818 if (*gr < PARAM_REGS) {
819 ainfo->pair_storage [0] = ArgInIReg;
820 ainfo->pair_regs [0] = param_regs [*gr];
824 ainfo->pair_storage [0] = ArgOnStack;
825 ainfo->offset = *stack_size;
834 args [0] = ARG_CLASS_NO_CLASS;
835 args [1] = ARG_CLASS_NO_CLASS;
836 for (quad = 0; quad < nquads; ++quad) {
839 ArgumentClass class1;
841 if (info->num_fields == 0)
842 class1 = ARG_CLASS_MEMORY;
844 class1 = ARG_CLASS_NO_CLASS;
845 for (i = 0; i < info->num_fields; ++i) {
846 size = mono_marshal_type_size (info->fields [i].field->type,
847 info->fields [i].mspec,
848 &align, TRUE, klass->unicode);
849 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
850 /* Unaligned field */
854 /* Skip fields in other quad */
855 if ((quad == 0) && (info->fields [i].offset >= 8))
857 if ((quad == 1) && (info->fields [i].offset < 8))
860 /* How far into this quad this data extends.*/
861 /* (8 is size of quad) */
862 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
864 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
866 g_assert (class1 != ARG_CLASS_NO_CLASS);
867 args [quad] = class1;
871 /* Post merger cleanup */
872 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
873 args [0] = args [1] = ARG_CLASS_MEMORY;
875 /* Allocate registers */
880 ainfo->storage = ArgValuetypeInReg;
881 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
882 ainfo->nregs = nquads;
883 for (quad = 0; quad < nquads; ++quad) {
884 switch (args [quad]) {
885 case ARG_CLASS_INTEGER:
886 if (*gr >= PARAM_REGS)
887 args [quad] = ARG_CLASS_MEMORY;
889 ainfo->pair_storage [quad] = ArgInIReg;
891 ainfo->pair_regs [quad] = return_regs [*gr];
893 ainfo->pair_regs [quad] = param_regs [*gr];
898 if (*fr >= FLOAT_PARAM_REGS)
899 args [quad] = ARG_CLASS_MEMORY;
901 if (quadsize[quad] <= 4)
902 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
903 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
904 ainfo->pair_regs [quad] = *fr;
908 case ARG_CLASS_MEMORY:
911 g_assert_not_reached ();
915 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
916 /* Revert possible register assignments */
920 ainfo->offset = *stack_size;
922 *stack_size += ALIGN_TO (info->native_size, 8);
924 *stack_size += nquads * sizeof(mgreg_t);
925 ainfo->storage = ArgOnStack;
933 * Obtain information about a call according to the calling convention.
934 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
935 * Draft Version 0.23" document for more information.
938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
940 guint32 i, gr, fr, pstart;
942 int n = sig->hasthis + sig->param_count;
943 guint32 stack_size = 0;
945 gboolean is_pinvoke = sig->pinvoke;
948 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
950 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
959 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
960 switch (ret_type->type) {
961 case MONO_TYPE_BOOLEAN:
972 case MONO_TYPE_FNPTR:
973 case MONO_TYPE_CLASS:
974 case MONO_TYPE_OBJECT:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
977 case MONO_TYPE_STRING:
978 cinfo->ret.storage = ArgInIReg;
979 cinfo->ret.reg = AMD64_RAX;
983 cinfo->ret.storage = ArgInIReg;
984 cinfo->ret.reg = AMD64_RAX;
987 cinfo->ret.storage = ArgInFloatSSEReg;
988 cinfo->ret.reg = AMD64_XMM0;
991 cinfo->ret.storage = ArgInDoubleSSEReg;
992 cinfo->ret.reg = AMD64_XMM0;
994 case MONO_TYPE_GENERICINST:
995 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
996 cinfo->ret.storage = ArgInIReg;
997 cinfo->ret.reg = AMD64_RAX;
1001 #if defined( __native_client_codegen__ )
1002 case MONO_TYPE_TYPEDBYREF:
1004 case MONO_TYPE_VALUETYPE: {
1005 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1007 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008 if (cinfo->ret.storage == ArgOnStack) {
1009 cinfo->vtype_retaddr = TRUE;
1010 /* The caller passes the address where the value is stored */
1014 #if !defined( __native_client_codegen__ )
1015 case MONO_TYPE_TYPEDBYREF:
1016 /* Same as a valuetype with size 24 */
1017 cinfo->vtype_retaddr = TRUE;
1020 case MONO_TYPE_VOID:
1023 g_error ("Can't handle as return value 0x%x", ret_type->type);
1029 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030 * the first argument, allowing 'this' to be always passed in the first arg reg.
1031 * Also do this if the first argument is a reference type, since virtual calls
1032 * are sometimes made using calli without sig->hasthis set, like in the delegate
1035 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1037 add_general (&gr, &stack_size, cinfo->args + 0);
1039 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1042 add_general (&gr, &stack_size, &cinfo->ret);
1043 cinfo->vret_arg_index = 1;
1047 add_general (&gr, &stack_size, cinfo->args + 0);
1049 if (cinfo->vtype_retaddr)
1050 add_general (&gr, &stack_size, &cinfo->ret);
1053 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1055 fr = FLOAT_PARAM_REGS;
1057 /* Emit the signature cookie just before the implicit arguments */
1058 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1061 for (i = pstart; i < sig->param_count; ++i) {
1062 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1066 /* The float param registers and other param registers must be the same index on Windows x64.*/
1073 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074 /* We allways pass the sig cookie on the stack for simplicity */
1076 * Prevent implicit arguments + the sig cookie from being passed
1080 fr = FLOAT_PARAM_REGS;
1082 /* Emit the signature cookie just before the implicit arguments */
1083 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1086 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087 switch (ptype->type) {
1088 case MONO_TYPE_BOOLEAN:
1091 add_general (&gr, &stack_size, ainfo);
1095 case MONO_TYPE_CHAR:
1096 add_general (&gr, &stack_size, ainfo);
1100 add_general (&gr, &stack_size, ainfo);
1105 case MONO_TYPE_FNPTR:
1106 case MONO_TYPE_CLASS:
1107 case MONO_TYPE_OBJECT:
1108 case MONO_TYPE_STRING:
1109 case MONO_TYPE_SZARRAY:
1110 case MONO_TYPE_ARRAY:
1111 add_general (&gr, &stack_size, ainfo);
1113 case MONO_TYPE_GENERICINST:
1114 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115 add_general (&gr, &stack_size, ainfo);
1119 case MONO_TYPE_VALUETYPE:
1120 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1122 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1126 stack_size += sizeof (MonoTypedRef);
1127 ainfo->storage = ArgOnStack;
1132 add_general (&gr, &stack_size, ainfo);
1135 add_float (&fr, &stack_size, ainfo, FALSE);
1138 add_float (&fr, &stack_size, ainfo, TRUE);
1141 g_assert_not_reached ();
1145 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1147 fr = FLOAT_PARAM_REGS;
1149 /* Emit the signature cookie just before the implicit arguments */
1150 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1154 // There always is 32 bytes reserved on the stack when calling on Winx64
1158 #ifndef MONO_AMD64_NO_PUSHES
1159 if (stack_size & 0x8) {
1160 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161 cinfo->need_stack_align = TRUE;
1166 cinfo->stack_usage = stack_size;
1167 cinfo->reg_usage = gr;
1168 cinfo->freg_usage = fr;
1173 * mono_arch_get_argument_info:
1174 * @csig: a method signature
1175 * @param_count: the number of parameters to consider
1176 * @arg_info: an array to store the result infos
1178 * Gathers information on parameters such as size, alignment and
1179 * padding. arg_info should be large enought to hold param_count + 1 entries.
1181 * Returns the size of the argument area on the stack.
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1187 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188 guint32 args_size = cinfo->stack_usage;
1190 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191 if (csig->hasthis) {
1192 arg_info [0].offset = 0;
1195 for (k = 0; k < param_count; k++) {
1196 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1198 arg_info [k + 1].size = 0;
1207 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1211 MonoType *callee_ret;
1213 c1 = get_call_info (NULL, NULL, caller_sig);
1214 c2 = get_call_info (NULL, NULL, callee_sig);
1215 res = c1->stack_usage >= c2->stack_usage;
1216 callee_ret = callee_sig->ret;
1217 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1218 /* An address on the callee's stack is passed as the first argument */
1228 * Initialize the cpu to execute managed code.
1231 mono_arch_cpu_init (void)
1236 /* spec compliance requires running with double precision */
1237 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1238 fpcw &= ~X86_FPCW_PRECC_MASK;
1239 fpcw |= X86_FPCW_PREC_DOUBLE;
1240 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1241 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1243 /* TODO: This is crashing on Win64 right now.
1244 * _control87 (_PC_53, MCW_PC);
1250 * Initialize architecture specific code.
1253 mono_arch_init (void)
1257 InitializeCriticalSection (&mini_arch_mutex);
1258 #if defined(__native_client_codegen__)
1259 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1260 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1261 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1262 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1265 #ifdef MONO_ARCH_NOMAP32BIT
1266 flags = MONO_MMAP_READ;
1267 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1268 breakpoint_size = 13;
1269 breakpoint_fault_size = 3;
1271 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1272 /* amd64_mov_reg_mem () */
1273 breakpoint_size = 8;
1274 breakpoint_fault_size = 8;
1277 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1278 single_step_fault_size = 4;
1280 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1281 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1284 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1285 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1286 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1290 * Cleanup architecture specific code.
1293 mono_arch_cleanup (void)
1295 DeleteCriticalSection (&mini_arch_mutex);
1296 #if defined(__native_client_codegen__)
1297 mono_native_tls_free (nacl_instruction_depth);
1298 mono_native_tls_free (nacl_rex_tag);
1299 mono_native_tls_free (nacl_legacy_prefix_tag);
1304 * This function returns the optimizations supported on this cpu.
1307 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1313 if (mono_hwcap_x86_has_cmov) {
1314 opts |= MONO_OPT_CMOV;
1316 if (mono_hwcap_x86_has_fcmov)
1317 opts |= MONO_OPT_FCMOV;
1319 *exclude_mask |= MONO_OPT_FCMOV;
1321 *exclude_mask |= MONO_OPT_CMOV;
1328 * This function test for all SSE functions supported.
1330 * Returns a bitmask corresponding to all supported versions.
1334 mono_arch_cpu_enumerate_simd_versions (void)
1336 guint32 sse_opts = 0;
1338 if (mono_hwcap_x86_has_sse1)
1339 sse_opts |= SIMD_VERSION_SSE1;
1341 if (mono_hwcap_x86_has_sse2)
1342 sse_opts |= SIMD_VERSION_SSE2;
1344 if (mono_hwcap_x86_has_sse3)
1345 sse_opts |= SIMD_VERSION_SSE3;
1347 if (mono_hwcap_x86_has_ssse3)
1348 sse_opts |= SIMD_VERSION_SSSE3;
1350 if (mono_hwcap_x86_has_sse41)
1351 sse_opts |= SIMD_VERSION_SSE41;
1353 if (mono_hwcap_x86_has_sse42)
1354 sse_opts |= SIMD_VERSION_SSE42;
1356 if (mono_hwcap_x86_has_sse4a)
1357 sse_opts |= SIMD_VERSION_SSE4a;
1365 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1370 for (i = 0; i < cfg->num_varinfo; i++) {
1371 MonoInst *ins = cfg->varinfo [i];
1372 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1375 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1378 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1379 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1382 if (mono_is_regsize_var (ins->inst_vtype)) {
1383 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1384 g_assert (i == vmv->idx);
1385 vars = g_list_prepend (vars, vmv);
1389 vars = mono_varlist_sort (cfg, vars, 0);
1395 * mono_arch_compute_omit_fp:
1397 * Determine whenever the frame pointer can be eliminated.
1400 mono_arch_compute_omit_fp (MonoCompile *cfg)
1402 MonoMethodSignature *sig;
1403 MonoMethodHeader *header;
1407 if (cfg->arch.omit_fp_computed)
1410 header = cfg->header;
1412 sig = mono_method_signature (cfg->method);
1414 if (!cfg->arch.cinfo)
1415 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1416 cinfo = cfg->arch.cinfo;
1419 * FIXME: Remove some of the restrictions.
1421 cfg->arch.omit_fp = TRUE;
1422 cfg->arch.omit_fp_computed = TRUE;
1424 #ifdef __native_client_codegen__
1425 /* NaCl modules may not change the value of RBP, so it cannot be */
1426 /* used as a normal register, but it can be used as a frame pointer*/
1427 cfg->disable_omit_fp = TRUE;
1428 cfg->arch.omit_fp = FALSE;
1431 if (cfg->disable_omit_fp)
1432 cfg->arch.omit_fp = FALSE;
1434 if (!debug_omit_fp ())
1435 cfg->arch.omit_fp = FALSE;
1437 if (cfg->method->save_lmf)
1438 cfg->arch.omit_fp = FALSE;
1440 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1441 cfg->arch.omit_fp = FALSE;
1442 if (header->num_clauses)
1443 cfg->arch.omit_fp = FALSE;
1444 if (cfg->param_area)
1445 cfg->arch.omit_fp = FALSE;
1446 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1447 cfg->arch.omit_fp = FALSE;
1448 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1449 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1450 cfg->arch.omit_fp = FALSE;
1451 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1452 ArgInfo *ainfo = &cinfo->args [i];
1454 if (ainfo->storage == ArgOnStack) {
1456 * The stack offset can only be determined when the frame
1459 cfg->arch.omit_fp = FALSE;
1464 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1465 MonoInst *ins = cfg->varinfo [i];
1468 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1473 mono_arch_get_global_int_regs (MonoCompile *cfg)
1477 mono_arch_compute_omit_fp (cfg);
1479 if (cfg->globalra) {
1480 if (cfg->arch.omit_fp)
1481 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1483 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1484 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1485 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1486 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1487 #ifndef __native_client_codegen__
1488 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1491 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1492 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1493 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1494 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1495 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1496 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1497 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1498 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1500 if (cfg->arch.omit_fp)
1501 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1503 /* We use the callee saved registers for global allocation */
1504 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1505 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1506 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1507 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1508 #ifndef __native_client_codegen__
1509 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1512 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1513 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1521 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1526 /* All XMM registers */
1527 for (i = 0; i < 16; ++i)
1528 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1534 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1536 static GList *r = NULL;
1541 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1543 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1544 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1545 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1546 #ifndef __native_client_codegen__
1547 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1550 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1551 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1552 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1557 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1559 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1566 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1569 static GList *r = NULL;
1574 for (i = 0; i < AMD64_XMM_NREG; ++i)
1575 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1577 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1584 * mono_arch_regalloc_cost:
1586 * Return the cost, in number of memory references, of the action of
1587 * allocating the variable VMV into a register during global register
1591 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1593 MonoInst *ins = cfg->varinfo [vmv->idx];
1595 if (cfg->method->save_lmf)
1596 /* The register is already saved */
1597 /* substract 1 for the invisible store in the prolog */
1598 return (ins->opcode == OP_ARG) ? 0 : 1;
1601 return (ins->opcode == OP_ARG) ? 1 : 2;
1605 * mono_arch_fill_argument_info:
1607 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1611 mono_arch_fill_argument_info (MonoCompile *cfg)
1614 MonoMethodSignature *sig;
1615 MonoMethodHeader *header;
1620 header = cfg->header;
1622 sig = mono_method_signature (cfg->method);
1624 cinfo = cfg->arch.cinfo;
1627 * Contrary to mono_arch_allocate_vars (), the information should describe
1628 * where the arguments are at the beginning of the method, not where they can be
1629 * accessed during the execution of the method. The later makes no sense for the
1630 * global register allocator, since a variable can be in more than one location.
1632 if (sig_ret->type != MONO_TYPE_VOID) {
1633 switch (cinfo->ret.storage) {
1635 case ArgInFloatSSEReg:
1636 case ArgInDoubleSSEReg:
1637 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1638 cfg->vret_addr->opcode = OP_REGVAR;
1639 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1642 cfg->ret->opcode = OP_REGVAR;
1643 cfg->ret->inst_c0 = cinfo->ret.reg;
1646 case ArgValuetypeInReg:
1647 cfg->ret->opcode = OP_REGOFFSET;
1648 cfg->ret->inst_basereg = -1;
1649 cfg->ret->inst_offset = -1;
1652 g_assert_not_reached ();
1656 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1657 ArgInfo *ainfo = &cinfo->args [i];
1660 ins = cfg->args [i];
1662 if (sig->hasthis && (i == 0))
1663 arg_type = &mono_defaults.object_class->byval_arg;
1665 arg_type = sig->params [i - sig->hasthis];
1667 switch (ainfo->storage) {
1669 case ArgInFloatSSEReg:
1670 case ArgInDoubleSSEReg:
1671 ins->opcode = OP_REGVAR;
1672 ins->inst_c0 = ainfo->reg;
1675 ins->opcode = OP_REGOFFSET;
1676 ins->inst_basereg = -1;
1677 ins->inst_offset = -1;
1679 case ArgValuetypeInReg:
1681 ins->opcode = OP_NOP;
1684 g_assert_not_reached ();
1690 mono_arch_allocate_vars (MonoCompile *cfg)
1693 MonoMethodSignature *sig;
1694 MonoMethodHeader *header;
1697 guint32 locals_stack_size, locals_stack_align;
1701 header = cfg->header;
1703 sig = mono_method_signature (cfg->method);
1705 cinfo = cfg->arch.cinfo;
1708 mono_arch_compute_omit_fp (cfg);
1711 * We use the ABI calling conventions for managed code as well.
1712 * Exception: valuetypes are only sometimes passed or returned in registers.
1716 * The stack looks like this:
1717 * <incoming arguments passed on the stack>
1719 * <lmf/caller saved registers>
1722 * <localloc area> -> grows dynamically
1726 if (cfg->arch.omit_fp) {
1727 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1728 cfg->frame_reg = AMD64_RSP;
1731 /* Locals are allocated backwards from %fp */
1732 cfg->frame_reg = AMD64_RBP;
1736 if (cfg->method->save_lmf) {
1737 /* The LMF var is allocated normally */
1739 if (cfg->arch.omit_fp)
1740 cfg->arch.reg_save_area_offset = offset;
1741 /* Reserve space for callee saved registers */
1742 for (i = 0; i < AMD64_NREG; ++i)
1743 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1744 offset += sizeof(mgreg_t);
1748 if (sig_ret->type != MONO_TYPE_VOID) {
1749 switch (cinfo->ret.storage) {
1751 case ArgInFloatSSEReg:
1752 case ArgInDoubleSSEReg:
1753 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1754 if (cfg->globalra) {
1755 cfg->vret_addr->opcode = OP_REGVAR;
1756 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1758 /* The register is volatile */
1759 cfg->vret_addr->opcode = OP_REGOFFSET;
1760 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1761 if (cfg->arch.omit_fp) {
1762 cfg->vret_addr->inst_offset = offset;
1766 cfg->vret_addr->inst_offset = -offset;
1768 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1769 printf ("vret_addr =");
1770 mono_print_ins (cfg->vret_addr);
1775 cfg->ret->opcode = OP_REGVAR;
1776 cfg->ret->inst_c0 = cinfo->ret.reg;
1779 case ArgValuetypeInReg:
1780 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1781 cfg->ret->opcode = OP_REGOFFSET;
1782 cfg->ret->inst_basereg = cfg->frame_reg;
1783 if (cfg->arch.omit_fp) {
1784 cfg->ret->inst_offset = offset;
1785 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1787 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1788 cfg->ret->inst_offset = - offset;
1792 g_assert_not_reached ();
1795 cfg->ret->dreg = cfg->ret->inst_c0;
1798 /* Allocate locals */
1799 if (!cfg->globalra) {
1800 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1801 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1802 char *mname = mono_method_full_name (cfg->method, TRUE);
1803 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1804 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1809 if (locals_stack_align) {
1810 offset += (locals_stack_align - 1);
1811 offset &= ~(locals_stack_align - 1);
1813 if (cfg->arch.omit_fp) {
1814 cfg->locals_min_stack_offset = offset;
1815 cfg->locals_max_stack_offset = offset + locals_stack_size;
1817 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1818 cfg->locals_max_stack_offset = - offset;
1821 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1822 if (offsets [i] != -1) {
1823 MonoInst *ins = cfg->varinfo [i];
1824 ins->opcode = OP_REGOFFSET;
1825 ins->inst_basereg = cfg->frame_reg;
1826 if (cfg->arch.omit_fp)
1827 ins->inst_offset = (offset + offsets [i]);
1829 ins->inst_offset = - (offset + offsets [i]);
1830 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1833 offset += locals_stack_size;
1836 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1837 g_assert (!cfg->arch.omit_fp);
1838 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1839 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1842 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1843 ins = cfg->args [i];
1844 if (ins->opcode != OP_REGVAR) {
1845 ArgInfo *ainfo = &cinfo->args [i];
1846 gboolean inreg = TRUE;
1849 if (sig->hasthis && (i == 0))
1850 arg_type = &mono_defaults.object_class->byval_arg;
1852 arg_type = sig->params [i - sig->hasthis];
1854 if (cfg->globalra) {
1855 /* The new allocator needs info about the original locations of the arguments */
1856 switch (ainfo->storage) {
1858 case ArgInFloatSSEReg:
1859 case ArgInDoubleSSEReg:
1860 ins->opcode = OP_REGVAR;
1861 ins->inst_c0 = ainfo->reg;
1864 g_assert (!cfg->arch.omit_fp);
1865 ins->opcode = OP_REGOFFSET;
1866 ins->inst_basereg = cfg->frame_reg;
1867 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1869 case ArgValuetypeInReg:
1870 ins->opcode = OP_REGOFFSET;
1871 ins->inst_basereg = cfg->frame_reg;
1872 /* These arguments are saved to the stack in the prolog */
1873 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1874 if (cfg->arch.omit_fp) {
1875 ins->inst_offset = offset;
1876 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1878 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1879 ins->inst_offset = - offset;
1883 g_assert_not_reached ();
1889 /* FIXME: Allocate volatile arguments to registers */
1890 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1894 * Under AMD64, all registers used to pass arguments to functions
1895 * are volatile across calls.
1896 * FIXME: Optimize this.
1898 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1901 ins->opcode = OP_REGOFFSET;
1903 switch (ainfo->storage) {
1905 case ArgInFloatSSEReg:
1906 case ArgInDoubleSSEReg:
1908 ins->opcode = OP_REGVAR;
1909 ins->dreg = ainfo->reg;
1913 g_assert (!cfg->arch.omit_fp);
1914 ins->opcode = OP_REGOFFSET;
1915 ins->inst_basereg = cfg->frame_reg;
1916 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1918 case ArgValuetypeInReg:
1920 case ArgValuetypeAddrInIReg: {
1922 g_assert (!cfg->arch.omit_fp);
1924 MONO_INST_NEW (cfg, indir, 0);
1925 indir->opcode = OP_REGOFFSET;
1926 if (ainfo->pair_storage [0] == ArgInIReg) {
1927 indir->inst_basereg = cfg->frame_reg;
1928 offset = ALIGN_TO (offset, sizeof (gpointer));
1929 offset += (sizeof (gpointer));
1930 indir->inst_offset = - offset;
1933 indir->inst_basereg = cfg->frame_reg;
1934 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1937 ins->opcode = OP_VTARG_ADDR;
1938 ins->inst_left = indir;
1946 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1947 ins->opcode = OP_REGOFFSET;
1948 ins->inst_basereg = cfg->frame_reg;
1949 /* These arguments are saved to the stack in the prolog */
1950 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1951 if (cfg->arch.omit_fp) {
1952 ins->inst_offset = offset;
1953 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1954 // Arguments are yet supported by the stack map creation code
1955 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1957 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1958 ins->inst_offset = - offset;
1959 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1965 cfg->stack_offset = offset;
1969 mono_arch_create_vars (MonoCompile *cfg)
1971 MonoMethodSignature *sig;
1974 sig = mono_method_signature (cfg->method);
1976 if (!cfg->arch.cinfo)
1977 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1978 cinfo = cfg->arch.cinfo;
1980 if (cinfo->ret.storage == ArgValuetypeInReg)
1981 cfg->ret_var_is_local = TRUE;
1983 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1984 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1985 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1986 printf ("vret_addr = ");
1987 mono_print_ins (cfg->vret_addr);
1991 if (cfg->gen_seq_points) {
1994 if (cfg->compile_aot) {
1995 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1996 ins->flags |= MONO_INST_VOLATILE;
1997 cfg->arch.seq_point_info_var = ins;
2000 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2001 ins->flags |= MONO_INST_VOLATILE;
2002 cfg->arch.ss_trigger_page_var = ins;
2005 #ifdef MONO_AMD64_NO_PUSHES
2007 * When this is set, we pass arguments on the stack by moves, and by allocating
2008 * a bigger stack frame, instead of pushes.
2009 * Pushes complicate exception handling because the arguments on the stack have
2010 * to be popped each time a frame is unwound. They also make fp elimination
2012 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2013 * on a new frame which doesn't include a param area.
2015 cfg->arch.no_pushes = TRUE;
2018 if (cfg->method->save_lmf) {
2019 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2020 lmf_var->flags |= MONO_INST_VOLATILE;
2021 lmf_var->flags |= MONO_INST_LMF;
2022 cfg->arch.lmf_var = lmf_var;
2025 #ifndef MONO_AMD64_NO_PUSHES
2026 cfg->arch_eh_jit_info = 1;
2031 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2037 MONO_INST_NEW (cfg, ins, OP_MOVE);
2038 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2039 ins->sreg1 = tree->dreg;
2040 MONO_ADD_INS (cfg->cbb, ins);
2041 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2043 case ArgInFloatSSEReg:
2044 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2045 ins->dreg = mono_alloc_freg (cfg);
2046 ins->sreg1 = tree->dreg;
2047 MONO_ADD_INS (cfg->cbb, ins);
2049 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2051 case ArgInDoubleSSEReg:
2052 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2053 ins->dreg = mono_alloc_freg (cfg);
2054 ins->sreg1 = tree->dreg;
2055 MONO_ADD_INS (cfg->cbb, ins);
2057 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2061 g_assert_not_reached ();
2066 arg_storage_to_load_membase (ArgStorage storage)
2070 #if defined(__mono_ilp32__)
2071 return OP_LOADI8_MEMBASE;
2073 return OP_LOAD_MEMBASE;
2075 case ArgInDoubleSSEReg:
2076 return OP_LOADR8_MEMBASE;
2077 case ArgInFloatSSEReg:
2078 return OP_LOADR4_MEMBASE;
2080 g_assert_not_reached ();
2087 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2090 MonoMethodSignature *tmp_sig;
2093 if (call->tail_call)
2096 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2099 * mono_ArgIterator_Setup assumes the signature cookie is
2100 * passed first and all the arguments which were before it are
2101 * passed on the stack after the signature. So compensate by
2102 * passing a different signature.
2104 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2105 tmp_sig->param_count -= call->signature->sentinelpos;
2106 tmp_sig->sentinelpos = 0;
2107 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2109 sig_reg = mono_alloc_ireg (cfg);
2110 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2112 if (cfg->arch.no_pushes) {
2113 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2115 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2116 arg->sreg1 = sig_reg;
2117 MONO_ADD_INS (cfg->cbb, arg);
2121 static inline LLVMArgStorage
2122 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2126 return LLVMArgInIReg;
2130 g_assert_not_reached ();
2137 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2143 LLVMCallInfo *linfo;
2144 MonoType *t, *sig_ret;
2146 n = sig->param_count + sig->hasthis;
2148 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2150 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2153 * LLVM always uses the native ABI while we use our own ABI, the
2154 * only difference is the handling of vtypes:
2155 * - we only pass/receive them in registers in some cases, and only
2156 * in 1 or 2 integer registers.
2158 if (cinfo->ret.storage == ArgValuetypeInReg) {
2160 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2161 cfg->disable_llvm = TRUE;
2165 linfo->ret.storage = LLVMArgVtypeInReg;
2166 for (j = 0; j < 2; ++j)
2167 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2170 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2171 /* Vtype returned using a hidden argument */
2172 linfo->ret.storage = LLVMArgVtypeRetAddr;
2173 linfo->vret_arg_index = cinfo->vret_arg_index;
2176 for (i = 0; i < n; ++i) {
2177 ainfo = cinfo->args + i;
2179 if (i >= sig->hasthis)
2180 t = sig->params [i - sig->hasthis];
2182 t = &mono_defaults.int_class->byval_arg;
2184 linfo->args [i].storage = LLVMArgNone;
2186 switch (ainfo->storage) {
2188 linfo->args [i].storage = LLVMArgInIReg;
2190 case ArgInDoubleSSEReg:
2191 case ArgInFloatSSEReg:
2192 linfo->args [i].storage = LLVMArgInFPReg;
2195 if (MONO_TYPE_ISSTRUCT (t)) {
2196 linfo->args [i].storage = LLVMArgVtypeByVal;
2198 linfo->args [i].storage = LLVMArgInIReg;
2200 if (t->type == MONO_TYPE_R4)
2201 linfo->args [i].storage = LLVMArgInFPReg;
2202 else if (t->type == MONO_TYPE_R8)
2203 linfo->args [i].storage = LLVMArgInFPReg;
2207 case ArgValuetypeInReg:
2209 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2210 cfg->disable_llvm = TRUE;
2214 linfo->args [i].storage = LLVMArgVtypeInReg;
2215 for (j = 0; j < 2; ++j)
2216 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2219 cfg->exception_message = g_strdup ("ainfo->storage");
2220 cfg->disable_llvm = TRUE;
2230 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2233 MonoMethodSignature *sig;
2235 int i, n, stack_size;
2241 sig = call->signature;
2242 n = sig->param_count + sig->hasthis;
2244 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2248 if (COMPILE_LLVM (cfg)) {
2249 /* We shouldn't be called in the llvm case */
2250 cfg->disable_llvm = TRUE;
2254 if (cinfo->need_stack_align) {
2255 if (!cfg->arch.no_pushes)
2256 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2260 * Emit all arguments which are passed on the stack to prevent register
2261 * allocation problems.
2263 if (cfg->arch.no_pushes) {
2264 for (i = 0; i < n; ++i) {
2266 ainfo = cinfo->args + i;
2268 in = call->args [i];
2270 if (sig->hasthis && i == 0)
2271 t = &mono_defaults.object_class->byval_arg;
2273 t = sig->params [i - sig->hasthis];
2275 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2277 if (t->type == MONO_TYPE_R4)
2278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2279 else if (t->type == MONO_TYPE_R8)
2280 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2282 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2284 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2286 if (cfg->compute_gc_maps) {
2289 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2296 * Emit all parameters passed in registers in non-reverse order for better readability
2297 * and to help the optimization in emit_prolog ().
2299 for (i = 0; i < n; ++i) {
2300 ainfo = cinfo->args + i;
2302 in = call->args [i];
2304 if (ainfo->storage == ArgInIReg)
2305 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2308 for (i = n - 1; i >= 0; --i) {
2309 ainfo = cinfo->args + i;
2311 in = call->args [i];
2313 switch (ainfo->storage) {
2317 case ArgInFloatSSEReg:
2318 case ArgInDoubleSSEReg:
2319 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2322 case ArgValuetypeInReg:
2323 case ArgValuetypeAddrInIReg:
2324 if (ainfo->storage == ArgOnStack && call->tail_call) {
2325 MonoInst *call_inst = (MonoInst*)call;
2326 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2327 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2328 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2332 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2333 size = sizeof (MonoTypedRef);
2334 align = sizeof (gpointer);
2338 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2341 * Other backends use mono_type_stack_size (), but that
2342 * aligns the size to 8, which is larger than the size of
2343 * the source, leading to reads of invalid memory if the
2344 * source is at the end of address space.
2346 size = mono_class_value_size (in->klass, &align);
2349 g_assert (in->klass);
2351 if (ainfo->storage == ArgOnStack && size >= 10000) {
2352 /* Avoid asserts in emit_memcpy () */
2353 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2354 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2355 /* Continue normally */
2359 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2360 arg->sreg1 = in->dreg;
2361 arg->klass = in->klass;
2362 arg->backend.size = size;
2363 arg->inst_p0 = call;
2364 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2365 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2367 MONO_ADD_INS (cfg->cbb, arg);
2370 if (cfg->arch.no_pushes) {
2373 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2374 arg->sreg1 = in->dreg;
2375 if (!sig->params [i - sig->hasthis]->byref) {
2376 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2377 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2378 arg->opcode = OP_STORER4_MEMBASE_REG;
2379 arg->inst_destbasereg = X86_ESP;
2380 arg->inst_offset = 0;
2381 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2382 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2383 arg->opcode = OP_STORER8_MEMBASE_REG;
2384 arg->inst_destbasereg = X86_ESP;
2385 arg->inst_offset = 0;
2388 MONO_ADD_INS (cfg->cbb, arg);
2393 g_assert_not_reached ();
2396 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2397 /* Emit the signature cookie just before the implicit arguments */
2398 emit_sig_cookie (cfg, call, cinfo);
2401 /* Handle the case where there are no implicit arguments */
2402 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2403 emit_sig_cookie (cfg, call, cinfo);
2405 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2408 if (cinfo->ret.storage == ArgValuetypeInReg) {
2409 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2411 * Tell the JIT to use a more efficient calling convention: call using
2412 * OP_CALL, compute the result location after the call, and save the
2415 call->vret_in_reg = TRUE;
2417 * Nullify the instruction computing the vret addr to enable
2418 * future optimizations.
2421 NULLIFY_INS (call->vret_var);
2423 if (call->tail_call)
2426 * The valuetype is in RAX:RDX after the call, need to be copied to
2427 * the stack. Push the address here, so the call instruction can
2430 if (!cfg->arch.vret_addr_loc) {
2431 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2432 /* Prevent it from being register allocated or optimized away */
2433 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2436 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2440 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2441 vtarg->sreg1 = call->vret_var->dreg;
2442 vtarg->dreg = mono_alloc_preg (cfg);
2443 MONO_ADD_INS (cfg->cbb, vtarg);
2445 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2450 if (call->inst.opcode != OP_TAILCALL) {
2451 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2455 if (cfg->method->save_lmf) {
2456 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2457 MONO_ADD_INS (cfg->cbb, arg);
2460 call->stack_usage = cinfo->stack_usage;
2464 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2467 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2468 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2469 int size = ins->backend.size;
2471 if (ainfo->storage == ArgValuetypeInReg) {
2475 for (part = 0; part < 2; ++part) {
2476 if (ainfo->pair_storage [part] == ArgNone)
2479 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2480 load->inst_basereg = src->dreg;
2481 load->inst_offset = part * sizeof(mgreg_t);
2483 switch (ainfo->pair_storage [part]) {
2485 load->dreg = mono_alloc_ireg (cfg);
2487 case ArgInDoubleSSEReg:
2488 case ArgInFloatSSEReg:
2489 load->dreg = mono_alloc_freg (cfg);
2492 g_assert_not_reached ();
2494 MONO_ADD_INS (cfg->cbb, load);
2496 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2498 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2499 MonoInst *vtaddr, *load;
2500 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2502 g_assert (!cfg->arch.no_pushes);
2504 MONO_INST_NEW (cfg, load, OP_LDADDR);
2505 cfg->has_indirection = TRUE;
2506 load->inst_p0 = vtaddr;
2507 vtaddr->flags |= MONO_INST_INDIRECT;
2508 load->type = STACK_MP;
2509 load->klass = vtaddr->klass;
2510 load->dreg = mono_alloc_ireg (cfg);
2511 MONO_ADD_INS (cfg->cbb, load);
2512 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2514 if (ainfo->pair_storage [0] == ArgInIReg) {
2515 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2516 arg->dreg = mono_alloc_ireg (cfg);
2517 arg->sreg1 = load->dreg;
2519 MONO_ADD_INS (cfg->cbb, arg);
2520 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2522 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2523 arg->sreg1 = load->dreg;
2524 MONO_ADD_INS (cfg->cbb, arg);
2528 if (cfg->arch.no_pushes) {
2529 int dreg = mono_alloc_ireg (cfg);
2531 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2532 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2534 /* Can't use this for < 8 since it does an 8 byte memory load */
2535 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2536 arg->inst_basereg = src->dreg;
2537 arg->inst_offset = 0;
2538 MONO_ADD_INS (cfg->cbb, arg);
2540 } else if (size <= 40) {
2541 if (cfg->arch.no_pushes) {
2542 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2544 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2545 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2548 if (cfg->arch.no_pushes) {
2549 // FIXME: Code growth
2550 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2552 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2553 arg->inst_basereg = src->dreg;
2554 arg->inst_offset = 0;
2555 arg->inst_imm = size;
2556 MONO_ADD_INS (cfg->cbb, arg);
2560 if (cfg->compute_gc_maps) {
2562 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2568 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2570 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2572 if (ret->type == MONO_TYPE_R4) {
2573 if (COMPILE_LLVM (cfg))
2574 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2576 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2578 } else if (ret->type == MONO_TYPE_R8) {
2579 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2583 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2586 #endif /* DISABLE_JIT */
2588 #define EMIT_COND_BRANCH(ins,cond,sign) \
2589 if (ins->inst_true_bb->native_offset) { \
2590 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2592 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2593 if ((cfg->opt & MONO_OPT_BRANCH) && \
2594 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2595 x86_branch8 (code, cond, 0, sign); \
2597 x86_branch32 (code, cond, 0, sign); \
2601 MonoMethodSignature *sig;
2606 mgreg_t regs [PARAM_REGS];
2612 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2620 switch (cinfo->ret.storage) {
2624 case ArgValuetypeInReg: {
2625 ArgInfo *ainfo = &cinfo->ret;
2627 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2629 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2637 for (i = 0; i < cinfo->nargs; ++i) {
2638 ArgInfo *ainfo = &cinfo->args [i];
2639 switch (ainfo->storage) {
2642 case ArgValuetypeInReg:
2643 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2645 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2657 * mono_arch_dyn_call_prepare:
2659 * Return a pointer to an arch-specific structure which contains information
2660 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2661 * supported for SIG.
2662 * This function is equivalent to ffi_prep_cif in libffi.
2665 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2667 ArchDynCallInfo *info;
2670 cinfo = get_call_info (NULL, NULL, sig);
2672 if (!dyn_call_supported (sig, cinfo)) {
2677 info = g_new0 (ArchDynCallInfo, 1);
2678 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2680 info->cinfo = cinfo;
2682 return (MonoDynCallInfo*)info;
2686 * mono_arch_dyn_call_free:
2688 * Free a MonoDynCallInfo structure.
2691 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2693 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2695 g_free (ainfo->cinfo);
2699 #if !defined(__native_client__)
2700 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2701 #define GREG_TO_PTR(greg) (gpointer)(greg)
2703 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2704 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2705 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2709 * mono_arch_get_start_dyn_call:
2711 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2712 * store the result into BUF.
2713 * ARGS should be an array of pointers pointing to the arguments.
2714 * RET should point to a memory buffer large enought to hold the result of the
2716 * This function should be as fast as possible, any work which does not depend
2717 * on the actual values of the arguments should be done in
2718 * mono_arch_dyn_call_prepare ().
2719 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2723 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2725 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2726 DynCallArgs *p = (DynCallArgs*)buf;
2727 int arg_index, greg, i, pindex;
2728 MonoMethodSignature *sig = dinfo->sig;
2730 g_assert (buf_len >= sizeof (DynCallArgs));
2739 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2740 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2745 if (dinfo->cinfo->vtype_retaddr)
2746 p->regs [greg ++] = PTR_TO_GREG(ret);
2748 for (i = pindex; i < sig->param_count; i++) {
2749 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2750 gpointer *arg = args [arg_index ++];
2753 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2758 case MONO_TYPE_STRING:
2759 case MONO_TYPE_CLASS:
2760 case MONO_TYPE_ARRAY:
2761 case MONO_TYPE_SZARRAY:
2762 case MONO_TYPE_OBJECT:
2766 #if !defined(__mono_ilp32__)
2770 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2771 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2773 #if defined(__mono_ilp32__)
2776 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2777 p->regs [greg ++] = *(guint64*)(arg);
2780 case MONO_TYPE_BOOLEAN:
2782 p->regs [greg ++] = *(guint8*)(arg);
2785 p->regs [greg ++] = *(gint8*)(arg);
2788 p->regs [greg ++] = *(gint16*)(arg);
2791 case MONO_TYPE_CHAR:
2792 p->regs [greg ++] = *(guint16*)(arg);
2795 p->regs [greg ++] = *(gint32*)(arg);
2798 p->regs [greg ++] = *(guint32*)(arg);
2800 case MONO_TYPE_GENERICINST:
2801 if (MONO_TYPE_IS_REFERENCE (t)) {
2802 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2807 case MONO_TYPE_VALUETYPE: {
2808 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2810 g_assert (ainfo->storage == ArgValuetypeInReg);
2811 if (ainfo->pair_storage [0] != ArgNone) {
2812 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2813 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2815 if (ainfo->pair_storage [1] != ArgNone) {
2816 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2817 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2822 g_assert_not_reached ();
2826 g_assert (greg <= PARAM_REGS);
2830 * mono_arch_finish_dyn_call:
2832 * Store the result of a dyn call into the return value buffer passed to
2833 * start_dyn_call ().
2834 * This function should be as fast as possible, any work which does not depend
2835 * on the actual values of the arguments should be done in
2836 * mono_arch_dyn_call_prepare ().
2839 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2841 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2842 MonoMethodSignature *sig = dinfo->sig;
2843 guint8 *ret = ((DynCallArgs*)buf)->ret;
2844 mgreg_t res = ((DynCallArgs*)buf)->res;
2845 MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2847 switch (sig_ret->type) {
2848 case MONO_TYPE_VOID:
2849 *(gpointer*)ret = NULL;
2851 case MONO_TYPE_STRING:
2852 case MONO_TYPE_CLASS:
2853 case MONO_TYPE_ARRAY:
2854 case MONO_TYPE_SZARRAY:
2855 case MONO_TYPE_OBJECT:
2859 *(gpointer*)ret = GREG_TO_PTR(res);
2865 case MONO_TYPE_BOOLEAN:
2866 *(guint8*)ret = res;
2869 *(gint16*)ret = res;
2872 case MONO_TYPE_CHAR:
2873 *(guint16*)ret = res;
2876 *(gint32*)ret = res;
2879 *(guint32*)ret = res;
2882 *(gint64*)ret = res;
2885 *(guint64*)ret = res;
2887 case MONO_TYPE_GENERICINST:
2888 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2889 *(gpointer*)ret = GREG_TO_PTR(res);
2894 case MONO_TYPE_VALUETYPE:
2895 if (dinfo->cinfo->vtype_retaddr) {
2898 ArgInfo *ainfo = &dinfo->cinfo->ret;
2900 g_assert (ainfo->storage == ArgValuetypeInReg);
2902 if (ainfo->pair_storage [0] != ArgNone) {
2903 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2904 ((mgreg_t*)ret)[0] = res;
2907 g_assert (ainfo->pair_storage [1] == ArgNone);
2911 g_assert_not_reached ();
2915 /* emit an exception if condition is fail */
2916 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2918 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2919 if (tins == NULL) { \
2920 mono_add_patch_info (cfg, code - cfg->native_code, \
2921 MONO_PATCH_INFO_EXC, exc_name); \
2922 x86_branch32 (code, cond, 0, signed); \
2924 EMIT_COND_BRANCH (tins, cond, signed); \
2928 #define EMIT_FPCOMPARE(code) do { \
2929 amd64_fcompp (code); \
2930 amd64_fnstsw (code); \
2933 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2934 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2935 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2936 amd64_ ##op (code); \
2937 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2938 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2942 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2944 gboolean no_patch = FALSE;
2947 * FIXME: Add support for thunks
2950 gboolean near_call = FALSE;
2953 * Indirect calls are expensive so try to make a near call if possible.
2954 * The caller memory is allocated by the code manager so it is
2955 * guaranteed to be at a 32 bit offset.
2958 if (patch_type != MONO_PATCH_INFO_ABS) {
2959 /* The target is in memory allocated using the code manager */
2962 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2963 if (((MonoMethod*)data)->klass->image->aot_module)
2964 /* The callee might be an AOT method */
2966 if (((MonoMethod*)data)->dynamic)
2967 /* The target is in malloc-ed memory */
2971 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2973 * The call might go directly to a native function without
2976 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2978 gconstpointer target = mono_icall_get_wrapper (mi);
2979 if ((((guint64)target) >> 32) != 0)
2985 MonoJumpInfo *jinfo = NULL;
2987 if (cfg->abs_patches)
2988 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2990 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2991 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2992 if (mi && (((guint64)mi->func) >> 32) == 0)
2997 * This is not really an optimization, but required because the
2998 * generic class init trampolines use R11 to pass the vtable.
3003 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3005 if (info->func == info->wrapper) {
3007 if ((((guint64)info->func) >> 32) == 0)
3011 /* See the comment in mono_codegen () */
3012 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3016 else if ((((guint64)data) >> 32) == 0) {
3023 if (cfg->method->dynamic)
3024 /* These methods are allocated using malloc */
3027 #ifdef MONO_ARCH_NOMAP32BIT
3030 #if defined(__native_client__)
3031 /* Always use near_call == TRUE for Native Client */
3034 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3035 if (optimize_for_xen)
3038 if (cfg->compile_aot) {
3045 * Align the call displacement to an address divisible by 4 so it does
3046 * not span cache lines. This is required for code patching to work on SMP
3049 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3050 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3051 amd64_padding (code, pad_size);
3053 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3054 amd64_call_code (code, 0);
3057 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3058 amd64_set_reg_template (code, GP_SCRATCH_REG);
3059 amd64_call_reg (code, GP_SCRATCH_REG);
3066 static inline guint8*
3067 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3070 if (win64_adjust_stack)
3071 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3073 code = emit_call_body (cfg, code, patch_type, data);
3075 if (win64_adjust_stack)
3076 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3083 store_membase_imm_to_store_membase_reg (int opcode)
3086 case OP_STORE_MEMBASE_IMM:
3087 return OP_STORE_MEMBASE_REG;
3088 case OP_STOREI4_MEMBASE_IMM:
3089 return OP_STOREI4_MEMBASE_REG;
3090 case OP_STOREI8_MEMBASE_IMM:
3091 return OP_STOREI8_MEMBASE_REG;
3099 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3102 * mono_arch_peephole_pass_1:
3104 * Perform peephole opts which should/can be performed before local regalloc
3107 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3111 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3112 MonoInst *last_ins = ins->prev;
3114 switch (ins->opcode) {
3118 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3120 * X86_LEA is like ADD, but doesn't have the
3121 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3122 * its operand to 64 bit.
3124 ins->opcode = OP_X86_LEA_MEMBASE;
3125 ins->inst_basereg = ins->sreg1;
3130 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3134 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3135 * the latter has length 2-3 instead of 6 (reverse constant
3136 * propagation). These instruction sequences are very common
3137 * in the initlocals bblock.
3139 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3140 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3141 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3142 ins2->sreg1 = ins->dreg;
3143 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3145 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3154 case OP_COMPARE_IMM:
3155 case OP_LCOMPARE_IMM:
3156 /* OP_COMPARE_IMM (reg, 0)
3158 * OP_AMD64_TEST_NULL (reg)
3161 ins->opcode = OP_AMD64_TEST_NULL;
3163 case OP_ICOMPARE_IMM:
3165 ins->opcode = OP_X86_TEST_NULL;
3167 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3169 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3170 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3172 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3173 * OP_COMPARE_IMM reg, imm
3175 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3177 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3178 ins->inst_basereg == last_ins->inst_destbasereg &&
3179 ins->inst_offset == last_ins->inst_offset) {
3180 ins->opcode = OP_ICOMPARE_IMM;
3181 ins->sreg1 = last_ins->sreg1;
3183 /* check if we can remove cmp reg,0 with test null */
3185 ins->opcode = OP_X86_TEST_NULL;
3191 mono_peephole_ins (bb, ins);
3196 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3200 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3201 switch (ins->opcode) {
3204 /* reg = 0 -> XOR (reg, reg) */
3205 /* XOR sets cflags on x86, so we cant do it always */
3206 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3207 ins->opcode = OP_LXOR;
3208 ins->sreg1 = ins->dreg;
3209 ins->sreg2 = ins->dreg;
3217 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3218 * 0 result into 64 bits.
3220 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3221 ins->opcode = OP_IXOR;
3225 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3229 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3230 * the latter has length 2-3 instead of 6 (reverse constant
3231 * propagation). These instruction sequences are very common
3232 * in the initlocals bblock.
3234 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3235 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3236 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3237 ins2->sreg1 = ins->dreg;
3238 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3240 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3250 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3251 ins->opcode = OP_X86_INC_REG;
3254 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3255 ins->opcode = OP_X86_DEC_REG;
3259 mono_peephole_ins (bb, ins);
3263 #define NEW_INS(cfg,ins,dest,op) do { \
3264 MONO_INST_NEW ((cfg), (dest), (op)); \
3265 (dest)->cil_code = (ins)->cil_code; \
3266 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3270 * mono_arch_lowering_pass:
3272 * Converts complex opcodes into simpler ones so that each IR instruction
3273 * corresponds to one machine instruction.
3276 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3278 MonoInst *ins, *n, *temp;
3281 * FIXME: Need to add more instructions, but the current machine
3282 * description can't model some parts of the composite instructions like
3285 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3286 switch (ins->opcode) {
3290 case OP_IDIV_UN_IMM:
3291 case OP_IREM_UN_IMM:
3292 mono_decompose_op_imm (cfg, bb, ins);
3295 /* Keep the opcode if we can implement it efficiently */
3296 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3297 mono_decompose_op_imm (cfg, bb, ins);
3299 case OP_COMPARE_IMM:
3300 case OP_LCOMPARE_IMM:
3301 if (!amd64_is_imm32 (ins->inst_imm)) {
3302 NEW_INS (cfg, ins, temp, OP_I8CONST);
3303 temp->inst_c0 = ins->inst_imm;
3304 temp->dreg = mono_alloc_ireg (cfg);
3305 ins->opcode = OP_COMPARE;
3306 ins->sreg2 = temp->dreg;
3309 #ifndef __mono_ilp32__
3310 case OP_LOAD_MEMBASE:
3312 case OP_LOADI8_MEMBASE:
3313 #ifndef __native_client_codegen__
3314 /* Don't generate memindex opcodes (to simplify */
3315 /* read sandboxing) */
3316 if (!amd64_is_imm32 (ins->inst_offset)) {
3317 NEW_INS (cfg, ins, temp, OP_I8CONST);
3318 temp->inst_c0 = ins->inst_offset;
3319 temp->dreg = mono_alloc_ireg (cfg);
3320 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3321 ins->inst_indexreg = temp->dreg;
3325 #ifndef __mono_ilp32__
3326 case OP_STORE_MEMBASE_IMM:
3328 case OP_STOREI8_MEMBASE_IMM:
3329 if (!amd64_is_imm32 (ins->inst_imm)) {
3330 NEW_INS (cfg, ins, temp, OP_I8CONST);
3331 temp->inst_c0 = ins->inst_imm;
3332 temp->dreg = mono_alloc_ireg (cfg);
3333 ins->opcode = OP_STOREI8_MEMBASE_REG;
3334 ins->sreg1 = temp->dreg;
3337 #ifdef MONO_ARCH_SIMD_INTRINSICS
3338 case OP_EXPAND_I1: {
3339 int temp_reg1 = mono_alloc_ireg (cfg);
3340 int temp_reg2 = mono_alloc_ireg (cfg);
3341 int original_reg = ins->sreg1;
3343 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3344 temp->sreg1 = original_reg;
3345 temp->dreg = temp_reg1;
3347 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3348 temp->sreg1 = temp_reg1;
3349 temp->dreg = temp_reg2;
3352 NEW_INS (cfg, ins, temp, OP_LOR);
3353 temp->sreg1 = temp->dreg = temp_reg2;
3354 temp->sreg2 = temp_reg1;
3356 ins->opcode = OP_EXPAND_I2;
3357 ins->sreg1 = temp_reg2;
3366 bb->max_vreg = cfg->next_vreg;
3370 branch_cc_table [] = {
3371 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3372 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3373 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3376 /* Maps CMP_... constants to X86_CC_... constants */
3379 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3380 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3384 cc_signed_table [] = {
3385 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3386 FALSE, FALSE, FALSE, FALSE
3389 /*#include "cprop.c"*/
3391 static unsigned char*
3392 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3394 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3397 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3399 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3403 static unsigned char*
3404 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3406 int sreg = tree->sreg1;
3407 int need_touch = FALSE;
3409 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3410 if (!tree->flags & MONO_INST_INIT)
3419 * If requested stack size is larger than one page,
3420 * perform stack-touch operation
3423 * Generate stack probe code.
3424 * Under Windows, it is necessary to allocate one page at a time,
3425 * "touching" stack after each successful sub-allocation. This is
3426 * because of the way stack growth is implemented - there is a
3427 * guard page before the lowest stack page that is currently commited.
3428 * Stack normally grows sequentially so OS traps access to the
3429 * guard page and commits more pages when needed.
3431 amd64_test_reg_imm (code, sreg, ~0xFFF);
3432 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3434 br[2] = code; /* loop */
3435 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3436 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3437 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3438 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3439 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3440 amd64_patch (br[3], br[2]);
3441 amd64_test_reg_reg (code, sreg, sreg);
3442 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3443 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3445 br[1] = code; x86_jump8 (code, 0);
3447 amd64_patch (br[0], code);
3448 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3449 amd64_patch (br[1], code);
3450 amd64_patch (br[4], code);
3453 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3455 if (tree->flags & MONO_INST_INIT) {
3457 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3458 amd64_push_reg (code, AMD64_RAX);
3461 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3462 amd64_push_reg (code, AMD64_RCX);
3465 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3466 amd64_push_reg (code, AMD64_RDI);
3470 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3471 if (sreg != AMD64_RCX)
3472 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3473 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3475 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3476 if (cfg->param_area && cfg->arch.no_pushes)
3477 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3479 #if defined(__default_codegen__)
3480 amd64_prefix (code, X86_REP_PREFIX);
3482 #elif defined(__native_client_codegen__)
3483 /* NaCl stos pseudo-instruction */
3484 amd64_codegen_pre(code);
3485 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3486 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3487 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3488 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3489 amd64_prefix (code, X86_REP_PREFIX);
3491 amd64_codegen_post(code);
3492 #endif /* __native_client_codegen__ */
3494 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3495 amd64_pop_reg (code, AMD64_RDI);
3496 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3497 amd64_pop_reg (code, AMD64_RCX);
3498 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3499 amd64_pop_reg (code, AMD64_RAX);
3505 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3510 /* Move return value to the target register */
3511 /* FIXME: do this in the local reg allocator */
3512 switch (ins->opcode) {
3515 case OP_CALL_MEMBASE:
3518 case OP_LCALL_MEMBASE:
3519 g_assert (ins->dreg == AMD64_RAX);
3523 case OP_FCALL_MEMBASE:
3524 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3525 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3528 if (ins->dreg != AMD64_XMM0)
3529 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3534 case OP_VCALL_MEMBASE:
3537 case OP_VCALL2_MEMBASE:
3538 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3539 if (cinfo->ret.storage == ArgValuetypeInReg) {
3540 MonoInst *loc = cfg->arch.vret_addr_loc;
3542 /* Load the destination address */
3543 g_assert (loc->opcode == OP_REGOFFSET);
3544 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3546 for (quad = 0; quad < 2; quad ++) {
3547 switch (cinfo->ret.pair_storage [quad]) {
3549 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3551 case ArgInFloatSSEReg:
3552 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3554 case ArgInDoubleSSEReg:
3555 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3570 #endif /* DISABLE_JIT */
3573 static int tls_gs_offset;
3577 mono_amd64_have_tls_get (void)
3580 static gboolean have_tls_get = FALSE;
3581 static gboolean inited = FALSE;
3585 return have_tls_get;
3587 ins = (guint8*)pthread_getspecific;
3590 * We're looking for these two instructions:
3592 * mov %gs:[offset](,%rdi,8),%rax
3595 have_tls_get = ins [0] == 0x65 &&
3607 tls_gs_offset = ins[5];
3609 return have_tls_get;
3616 mono_amd64_get_tls_gs_offset (void)
3619 return tls_gs_offset;
3621 g_assert_not_reached ();
3627 * mono_amd64_emit_tls_get:
3628 * @code: buffer to store code to
3629 * @dreg: hard register where to place the result
3630 * @tls_offset: offset info
3632 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3633 * the dreg register the item in the thread local storage identified
3636 * Returns: a pointer to the end of the stored code
3639 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3642 g_assert (tls_offset < 64);
3643 x86_prefix (code, X86_GS_PREFIX);
3644 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3645 #elif defined(__APPLE__)
3646 x86_prefix (code, X86_GS_PREFIX);
3647 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3649 if (optimize_for_xen) {
3650 x86_prefix (code, X86_FS_PREFIX);
3651 amd64_mov_reg_mem (code, dreg, 0, 8);
3652 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3654 x86_prefix (code, X86_FS_PREFIX);
3655 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3662 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3665 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
3666 if (dreg != offset_reg)
3667 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (gpointer));
3668 amd64_shift_reg_imm (code, X86_SHL, dreg, 3);
3670 amd64_alu_reg_imm (code, X86_ADD, dreg, tls_gs_offset);
3671 x86_prefix (code, X86_GS_PREFIX);
3672 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (gpointer));
3673 #elif defined(__linux__)
3676 if (dreg == offset_reg) {
3677 /* Use a temporary reg by saving it to the redzone */
3678 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3679 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3680 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3681 offset_reg = tmpreg;
3683 x86_prefix (code, X86_FS_PREFIX);
3684 amd64_mov_reg_mem (code, dreg, 0, 8);
3685 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3687 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3689 g_assert_not_reached ();
3697 * Emit code to initialize an LMF structure at LMF_OFFSET.
3700 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3705 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3708 * sp is saved right before calls but we need to save it here too so
3709 * async stack walks would work.
3711 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3712 /* Skip method (only needed for trampoline LMF frames) */
3713 /* Save callee saved regs */
3714 for (i = 0; i < MONO_MAX_IREGS; ++i) {
3718 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3719 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3720 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3721 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3722 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3723 #ifndef __native_client_codegen__
3724 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3727 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3728 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3736 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3737 if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3738 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3742 /* These can't contain refs */
3743 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3744 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3745 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3746 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3748 /* These are handled automatically by the stack marking code */
3749 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3750 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3751 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3752 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3753 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3754 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3756 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3757 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3766 * Emit code to push an LMF structure on the LMF stack.
3769 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3771 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3773 * Optimized version which uses the mono_lmf TLS variable instead of
3774 * indirection through the mono_lmf_addr TLS variable.
3776 /* %rax = previous_lmf */
3777 x86_prefix (code, X86_FS_PREFIX);
3778 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
3780 /* Save previous_lmf */
3781 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3783 if (lmf_offset == 0) {
3784 x86_prefix (code, X86_FS_PREFIX);
3785 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
3787 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3788 x86_prefix (code, X86_FS_PREFIX);
3789 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3792 if (lmf_addr_tls_offset != -1) {
3793 /* Load lmf quicky using the FS register */
3794 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
3796 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3797 /* FIXME: Add a separate key for LMF to avoid this */
3798 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3803 * The call might clobber argument registers, but they are already
3804 * saved to the stack/global regs.
3807 *args_clobbered = TRUE;
3808 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3809 (gpointer)"mono_get_lmf_addr", TRUE);
3813 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3814 /* Save previous_lmf */
3815 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3816 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3818 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3819 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3828 * Emit code to pop an LMF structure from the LMF stack.
3831 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3833 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3835 * Optimized version which uses the mono_lmf TLS variable instead of indirection
3836 * through the mono_lmf_addr TLS variable.
3838 /* reg = previous_lmf */
3839 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3840 x86_prefix (code, X86_FS_PREFIX);
3841 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3843 /* Restore previous lmf */
3844 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3845 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3846 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3852 #define REAL_PRINT_REG(text,reg) \
3853 mono_assert (reg >= 0); \
3854 amd64_push_reg (code, AMD64_RAX); \
3855 amd64_push_reg (code, AMD64_RDX); \
3856 amd64_push_reg (code, AMD64_RCX); \
3857 amd64_push_reg (code, reg); \
3858 amd64_push_imm (code, reg); \
3859 amd64_push_imm (code, text " %d %p\n"); \
3860 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3861 amd64_call_reg (code, AMD64_RAX); \
3862 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3863 amd64_pop_reg (code, AMD64_RCX); \
3864 amd64_pop_reg (code, AMD64_RDX); \
3865 amd64_pop_reg (code, AMD64_RAX);
3867 /* benchmark and set based on cpu */
3868 #define LOOP_ALIGNMENT 8
3869 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3873 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3878 guint8 *code = cfg->native_code + cfg->code_len;
3879 MonoInst *last_ins = NULL;
3880 guint last_offset = 0;
3883 /* Fix max_offset estimate for each successor bb */
3884 if (cfg->opt & MONO_OPT_BRANCH) {
3885 int current_offset = cfg->code_len;
3886 MonoBasicBlock *current_bb;
3887 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3888 current_bb->max_offset = current_offset;
3889 current_offset += current_bb->max_length;
3893 if (cfg->opt & MONO_OPT_LOOP) {
3894 int pad, align = LOOP_ALIGNMENT;
3895 /* set alignment depending on cpu */
3896 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3898 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3899 amd64_padding (code, pad);
3900 cfg->code_len += pad;
3901 bb->native_offset = cfg->code_len;
3905 #if defined(__native_client_codegen__)
3906 /* For Native Client, all indirect call/jump targets must be */
3907 /* 32-byte aligned. Exception handler blocks are jumped to */
3908 /* indirectly as well. */
3909 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3910 (bb->flags & BB_EXCEPTION_HANDLER);
3912 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3913 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3914 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3915 cfg->code_len += pad;
3916 bb->native_offset = cfg->code_len;
3918 #endif /*__native_client_codegen__*/
3920 if (cfg->verbose_level > 2)
3921 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3923 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3924 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3925 g_assert (!cfg->compile_aot);
3927 cov->data [bb->dfn].cil_code = bb->cil_code;
3928 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3929 /* this is not thread save, but good enough */
3930 amd64_inc_membase (code, AMD64_R11, 0);
3933 offset = code - cfg->native_code;
3935 mono_debug_open_block (cfg, bb, offset);
3937 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3938 x86_breakpoint (code);
3940 MONO_BB_FOR_EACH_INS (bb, ins) {
3941 offset = code - cfg->native_code;
3943 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3945 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3947 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3948 cfg->code_size *= 2;
3949 cfg->native_code = mono_realloc_native_code(cfg);
3950 code = cfg->native_code + offset;
3951 cfg->stat_code_reallocs++;
3954 if (cfg->debug_info)
3955 mono_debug_record_line_number (cfg, ins, offset);
3957 switch (ins->opcode) {
3959 amd64_mul_reg (code, ins->sreg2, TRUE);
3962 amd64_mul_reg (code, ins->sreg2, FALSE);
3964 case OP_X86_SETEQ_MEMBASE:
3965 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3967 case OP_STOREI1_MEMBASE_IMM:
3968 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3970 case OP_STOREI2_MEMBASE_IMM:
3971 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3973 case OP_STOREI4_MEMBASE_IMM:
3974 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3976 case OP_STOREI1_MEMBASE_REG:
3977 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3979 case OP_STOREI2_MEMBASE_REG:
3980 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3982 /* In AMD64 NaCl, pointers are 4 bytes, */
3983 /* so STORE_* != STOREI8_*. Likewise below. */
3984 case OP_STORE_MEMBASE_REG:
3985 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3987 case OP_STOREI8_MEMBASE_REG:
3988 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3990 case OP_STOREI4_MEMBASE_REG:
3991 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3993 case OP_STORE_MEMBASE_IMM:
3994 #ifndef __native_client_codegen__
3995 /* In NaCl, this could be a PCONST type, which could */
3996 /* mean a pointer type was copied directly into the */
3997 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3998 /* the value would be 0x00000000FFFFFFFF which is */
3999 /* not proper for an imm32 unless you cast it. */
4000 g_assert (amd64_is_imm32 (ins->inst_imm));
4002 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4004 case OP_STOREI8_MEMBASE_IMM:
4005 g_assert (amd64_is_imm32 (ins->inst_imm));
4006 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4009 #ifdef __mono_ilp32__
4010 /* In ILP32, pointers are 4 bytes, so separate these */
4011 /* cases, use literal 8 below where we really want 8 */
4012 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4013 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4017 // FIXME: Decompose this earlier
4018 if (amd64_is_imm32 (ins->inst_imm))
4019 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4021 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4022 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4026 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4027 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4030 // FIXME: Decompose this earlier
4031 if (amd64_is_imm32 (ins->inst_imm))
4032 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4034 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4035 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4039 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4040 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4043 /* For NaCl, pointers are 4 bytes, so separate these */
4044 /* cases, use literal 8 below where we really want 8 */
4045 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4046 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4048 case OP_LOAD_MEMBASE:
4049 g_assert (amd64_is_imm32 (ins->inst_offset));
4050 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4052 case OP_LOADI8_MEMBASE:
4053 /* Use literal 8 instead of sizeof pointer or */
4054 /* register, we really want 8 for this opcode */
4055 g_assert (amd64_is_imm32 (ins->inst_offset));
4056 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4058 case OP_LOADI4_MEMBASE:
4059 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4061 case OP_LOADU4_MEMBASE:
4062 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4064 case OP_LOADU1_MEMBASE:
4065 /* The cpu zero extends the result into 64 bits */
4066 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4068 case OP_LOADI1_MEMBASE:
4069 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4071 case OP_LOADU2_MEMBASE:
4072 /* The cpu zero extends the result into 64 bits */
4073 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4075 case OP_LOADI2_MEMBASE:
4076 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4078 case OP_AMD64_LOADI8_MEMINDEX:
4079 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4081 case OP_LCONV_TO_I1:
4082 case OP_ICONV_TO_I1:
4084 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4086 case OP_LCONV_TO_I2:
4087 case OP_ICONV_TO_I2:
4089 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4091 case OP_LCONV_TO_U1:
4092 case OP_ICONV_TO_U1:
4093 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4095 case OP_LCONV_TO_U2:
4096 case OP_ICONV_TO_U2:
4097 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4100 /* Clean out the upper word */
4101 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4104 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4108 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4110 case OP_COMPARE_IMM:
4111 #if defined(__mono_ilp32__)
4112 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4113 g_assert (amd64_is_imm32 (ins->inst_imm));
4114 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4117 case OP_LCOMPARE_IMM:
4118 g_assert (amd64_is_imm32 (ins->inst_imm));
4119 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4121 case OP_X86_COMPARE_REG_MEMBASE:
4122 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4124 case OP_X86_TEST_NULL:
4125 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4127 case OP_AMD64_TEST_NULL:
4128 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4131 case OP_X86_ADD_REG_MEMBASE:
4132 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4134 case OP_X86_SUB_REG_MEMBASE:
4135 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4137 case OP_X86_AND_REG_MEMBASE:
4138 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4140 case OP_X86_OR_REG_MEMBASE:
4141 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4143 case OP_X86_XOR_REG_MEMBASE:
4144 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4147 case OP_X86_ADD_MEMBASE_IMM:
4148 /* FIXME: Make a 64 version too */
4149 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4151 case OP_X86_SUB_MEMBASE_IMM:
4152 g_assert (amd64_is_imm32 (ins->inst_imm));
4153 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4155 case OP_X86_AND_MEMBASE_IMM:
4156 g_assert (amd64_is_imm32 (ins->inst_imm));
4157 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4159 case OP_X86_OR_MEMBASE_IMM:
4160 g_assert (amd64_is_imm32 (ins->inst_imm));
4161 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4163 case OP_X86_XOR_MEMBASE_IMM:
4164 g_assert (amd64_is_imm32 (ins->inst_imm));
4165 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4167 case OP_X86_ADD_MEMBASE_REG:
4168 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4170 case OP_X86_SUB_MEMBASE_REG:
4171 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4173 case OP_X86_AND_MEMBASE_REG:
4174 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4176 case OP_X86_OR_MEMBASE_REG:
4177 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4179 case OP_X86_XOR_MEMBASE_REG:
4180 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4182 case OP_X86_INC_MEMBASE:
4183 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4185 case OP_X86_INC_REG:
4186 amd64_inc_reg_size (code, ins->dreg, 4);
4188 case OP_X86_DEC_MEMBASE:
4189 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4191 case OP_X86_DEC_REG:
4192 amd64_dec_reg_size (code, ins->dreg, 4);
4194 case OP_X86_MUL_REG_MEMBASE:
4195 case OP_X86_MUL_MEMBASE_REG:
4196 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4198 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4199 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4201 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4202 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4204 case OP_AMD64_COMPARE_MEMBASE_REG:
4205 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4207 case OP_AMD64_COMPARE_MEMBASE_IMM:
4208 g_assert (amd64_is_imm32 (ins->inst_imm));
4209 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4211 case OP_X86_COMPARE_MEMBASE8_IMM:
4212 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4214 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4215 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4217 case OP_AMD64_COMPARE_REG_MEMBASE:
4218 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4221 case OP_AMD64_ADD_REG_MEMBASE:
4222 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4224 case OP_AMD64_SUB_REG_MEMBASE:
4225 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4227 case OP_AMD64_AND_REG_MEMBASE:
4228 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4230 case OP_AMD64_OR_REG_MEMBASE:
4231 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4233 case OP_AMD64_XOR_REG_MEMBASE:
4234 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4237 case OP_AMD64_ADD_MEMBASE_REG:
4238 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4240 case OP_AMD64_SUB_MEMBASE_REG:
4241 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4243 case OP_AMD64_AND_MEMBASE_REG:
4244 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4246 case OP_AMD64_OR_MEMBASE_REG:
4247 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4249 case OP_AMD64_XOR_MEMBASE_REG:
4250 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4253 case OP_AMD64_ADD_MEMBASE_IMM:
4254 g_assert (amd64_is_imm32 (ins->inst_imm));
4255 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4257 case OP_AMD64_SUB_MEMBASE_IMM:
4258 g_assert (amd64_is_imm32 (ins->inst_imm));
4259 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4261 case OP_AMD64_AND_MEMBASE_IMM:
4262 g_assert (amd64_is_imm32 (ins->inst_imm));
4263 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4265 case OP_AMD64_OR_MEMBASE_IMM:
4266 g_assert (amd64_is_imm32 (ins->inst_imm));
4267 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4269 case OP_AMD64_XOR_MEMBASE_IMM:
4270 g_assert (amd64_is_imm32 (ins->inst_imm));
4271 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4275 amd64_breakpoint (code);
4277 case OP_RELAXED_NOP:
4278 x86_prefix (code, X86_REP_PREFIX);
4286 case OP_DUMMY_STORE:
4287 case OP_NOT_REACHED:
4290 case OP_SEQ_POINT: {
4294 * Read from the single stepping trigger page. This will cause a
4295 * SIGSEGV when single stepping is enabled.
4296 * We do this _before_ the breakpoint, so single stepping after
4297 * a breakpoint is hit will step to the next IL offset.
4299 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4300 MonoInst *var = cfg->arch.ss_trigger_page_var;
4302 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4303 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4307 * This is the address which is saved in seq points,
4309 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4311 if (cfg->compile_aot) {
4312 guint32 offset = code - cfg->native_code;
4314 MonoInst *info_var = cfg->arch.seq_point_info_var;
4317 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4318 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4319 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4320 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4321 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4324 * A placeholder for a possible breakpoint inserted by
4325 * mono_arch_set_breakpoint ().
4327 for (i = 0; i < breakpoint_size; ++i)
4331 * Add an additional nop so skipping the bp doesn't cause the ip to point
4332 * to another IL offset.
4340 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4343 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4347 g_assert (amd64_is_imm32 (ins->inst_imm));
4348 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4351 g_assert (amd64_is_imm32 (ins->inst_imm));
4352 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4357 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4360 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4364 g_assert (amd64_is_imm32 (ins->inst_imm));
4365 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4368 g_assert (amd64_is_imm32 (ins->inst_imm));
4369 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4372 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4376 g_assert (amd64_is_imm32 (ins->inst_imm));
4377 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4380 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4385 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4387 switch (ins->inst_imm) {
4391 if (ins->dreg != ins->sreg1)
4392 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4393 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4396 /* LEA r1, [r2 + r2*2] */
4397 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4400 /* LEA r1, [r2 + r2*4] */
4401 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4404 /* LEA r1, [r2 + r2*2] */
4406 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4407 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4410 /* LEA r1, [r2 + r2*8] */
4411 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4414 /* LEA r1, [r2 + r2*4] */
4416 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4417 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4420 /* LEA r1, [r2 + r2*2] */
4422 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4423 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4426 /* LEA r1, [r2 + r2*4] */
4427 /* LEA r1, [r1 + r1*4] */
4428 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4429 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4432 /* LEA r1, [r2 + r2*4] */
4434 /* LEA r1, [r1 + r1*4] */
4435 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4436 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4437 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4440 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4447 #if defined( __native_client_codegen__ )
4448 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4449 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4451 /* Regalloc magic makes the div/rem cases the same */
4452 if (ins->sreg2 == AMD64_RDX) {
4453 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4455 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4458 amd64_div_reg (code, ins->sreg2, TRUE);
4463 #if defined( __native_client_codegen__ )
4464 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4465 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4467 if (ins->sreg2 == AMD64_RDX) {
4468 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4469 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4470 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4472 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4473 amd64_div_reg (code, ins->sreg2, FALSE);
4478 #if defined( __native_client_codegen__ )
4479 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4480 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4482 if (ins->sreg2 == AMD64_RDX) {
4483 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4484 amd64_cdq_size (code, 4);
4485 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4487 amd64_cdq_size (code, 4);
4488 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4493 #if defined( __native_client_codegen__ )
4494 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4495 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4497 if (ins->sreg2 == AMD64_RDX) {
4498 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4499 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4500 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4502 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4503 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4507 int power = mono_is_power_of_two (ins->inst_imm);
4509 g_assert (ins->sreg1 == X86_EAX);
4510 g_assert (ins->dreg == X86_EAX);
4511 g_assert (power >= 0);
4514 amd64_mov_reg_imm (code, ins->dreg, 0);
4518 /* Based on gcc code */
4520 /* Add compensation for negative dividents */
4521 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4523 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4524 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4525 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4526 /* Compute remainder */
4527 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4528 /* Remove compensation */
4529 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4533 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4534 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4537 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4541 g_assert (amd64_is_imm32 (ins->inst_imm));
4542 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4545 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4549 g_assert (amd64_is_imm32 (ins->inst_imm));
4550 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4553 g_assert (ins->sreg2 == AMD64_RCX);
4554 amd64_shift_reg (code, X86_SHL, ins->dreg);
4557 g_assert (ins->sreg2 == AMD64_RCX);
4558 amd64_shift_reg (code, X86_SAR, ins->dreg);
4561 g_assert (amd64_is_imm32 (ins->inst_imm));
4562 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4565 g_assert (amd64_is_imm32 (ins->inst_imm));
4566 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4569 g_assert (amd64_is_imm32 (ins->inst_imm));
4570 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4572 case OP_LSHR_UN_IMM:
4573 g_assert (amd64_is_imm32 (ins->inst_imm));
4574 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4577 g_assert (ins->sreg2 == AMD64_RCX);
4578 amd64_shift_reg (code, X86_SHR, ins->dreg);
4581 g_assert (amd64_is_imm32 (ins->inst_imm));
4582 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4585 g_assert (amd64_is_imm32 (ins->inst_imm));
4586 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4591 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4594 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4597 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4600 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4604 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4607 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4610 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4613 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4616 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4619 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4622 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4625 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4628 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4631 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4634 amd64_neg_reg_size (code, ins->sreg1, 4);
4637 amd64_not_reg_size (code, ins->sreg1, 4);
4640 g_assert (ins->sreg2 == AMD64_RCX);
4641 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4644 g_assert (ins->sreg2 == AMD64_RCX);
4645 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4648 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4650 case OP_ISHR_UN_IMM:
4651 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4654 g_assert (ins->sreg2 == AMD64_RCX);
4655 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4658 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4661 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4664 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4665 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4667 case OP_IMUL_OVF_UN:
4668 case OP_LMUL_OVF_UN: {
4669 /* the mul operation and the exception check should most likely be split */
4670 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4671 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4672 /*g_assert (ins->sreg2 == X86_EAX);
4673 g_assert (ins->dreg == X86_EAX);*/
4674 if (ins->sreg2 == X86_EAX) {
4675 non_eax_reg = ins->sreg1;
4676 } else if (ins->sreg1 == X86_EAX) {
4677 non_eax_reg = ins->sreg2;
4679 /* no need to save since we're going to store to it anyway */
4680 if (ins->dreg != X86_EAX) {
4682 amd64_push_reg (code, X86_EAX);
4684 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4685 non_eax_reg = ins->sreg2;
4687 if (ins->dreg == X86_EDX) {
4690 amd64_push_reg (code, X86_EAX);
4694 amd64_push_reg (code, X86_EDX);
4696 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4697 /* save before the check since pop and mov don't change the flags */
4698 if (ins->dreg != X86_EAX)
4699 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4701 amd64_pop_reg (code, X86_EDX);
4703 amd64_pop_reg (code, X86_EAX);
4704 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4708 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4710 case OP_ICOMPARE_IMM:
4711 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4733 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4741 case OP_CMOV_INE_UN:
4742 case OP_CMOV_IGE_UN:
4743 case OP_CMOV_IGT_UN:
4744 case OP_CMOV_ILE_UN:
4745 case OP_CMOV_ILT_UN:
4751 case OP_CMOV_LNE_UN:
4752 case OP_CMOV_LGE_UN:
4753 case OP_CMOV_LGT_UN:
4754 case OP_CMOV_LLE_UN:
4755 case OP_CMOV_LLT_UN:
4756 g_assert (ins->dreg == ins->sreg1);
4757 /* This needs to operate on 64 bit values */
4758 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4762 amd64_not_reg (code, ins->sreg1);
4765 amd64_neg_reg (code, ins->sreg1);
4770 if ((((guint64)ins->inst_c0) >> 32) == 0)
4771 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4773 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4776 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4777 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4780 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4781 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4784 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4786 case OP_AMD64_SET_XMMREG_R4: {
4787 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4790 case OP_AMD64_SET_XMMREG_R8: {
4791 if (ins->dreg != ins->sreg1)
4792 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4796 MonoCallInst *call = (MonoCallInst*)ins;
4799 /* FIXME: no tracing support... */
4800 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4801 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4803 g_assert (!cfg->method->save_lmf);
4805 if (cfg->arch.omit_fp) {
4806 guint32 save_offset = 0;
4807 /* Pop callee-saved registers */
4808 for (i = 0; i < AMD64_NREG; ++i)
4809 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4810 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4813 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4816 if (call->stack_usage)
4820 for (i = 0; i < AMD64_NREG; ++i)
4821 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4822 pos -= sizeof(mgreg_t);
4824 /* Restore callee-saved registers */
4825 for (i = AMD64_NREG - 1; i > 0; --i) {
4826 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4827 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4828 pos += sizeof(mgreg_t);
4832 /* Copy arguments on the stack to our argument area */
4833 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4834 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4835 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4839 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4844 offset = code - cfg->native_code;
4845 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4846 if (cfg->compile_aot)
4847 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4849 amd64_set_reg_template (code, AMD64_R11);
4850 amd64_jump_reg (code, AMD64_R11);
4851 ins->flags |= MONO_INST_GC_CALLSITE;
4852 ins->backend.pc_offset = code - cfg->native_code;
4856 /* ensure ins->sreg1 is not NULL */
4857 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4860 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4861 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4870 call = (MonoCallInst*)ins;
4872 * The AMD64 ABI forces callers to know about varargs.
4874 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4875 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4876 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4878 * Since the unmanaged calling convention doesn't contain a
4879 * 'vararg' entry, we have to treat every pinvoke call as a
4880 * potential vararg call.
4884 for (i = 0; i < AMD64_XMM_NREG; ++i)
4885 if (call->used_fregs & (1 << i))
4888 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4890 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4893 if (ins->flags & MONO_INST_HAS_METHOD)
4894 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4896 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4897 ins->flags |= MONO_INST_GC_CALLSITE;
4898 ins->backend.pc_offset = code - cfg->native_code;
4899 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4900 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4901 code = emit_move_return_value (cfg, ins, code);
4907 case OP_VOIDCALL_REG:
4909 call = (MonoCallInst*)ins;
4911 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4912 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4913 ins->sreg1 = AMD64_R11;
4917 * The AMD64 ABI forces callers to know about varargs.
4919 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4920 if (ins->sreg1 == AMD64_RAX) {
4921 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4922 ins->sreg1 = AMD64_R11;
4924 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4925 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4927 * Since the unmanaged calling convention doesn't contain a
4928 * 'vararg' entry, we have to treat every pinvoke call as a
4929 * potential vararg call.
4933 for (i = 0; i < AMD64_XMM_NREG; ++i)
4934 if (call->used_fregs & (1 << i))
4936 if (ins->sreg1 == AMD64_RAX) {
4937 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4938 ins->sreg1 = AMD64_R11;
4941 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4943 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4946 amd64_call_reg (code, ins->sreg1);
4947 ins->flags |= MONO_INST_GC_CALLSITE;
4948 ins->backend.pc_offset = code - cfg->native_code;
4949 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4950 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4951 code = emit_move_return_value (cfg, ins, code);
4953 case OP_FCALL_MEMBASE:
4954 case OP_LCALL_MEMBASE:
4955 case OP_VCALL_MEMBASE:
4956 case OP_VCALL2_MEMBASE:
4957 case OP_VOIDCALL_MEMBASE:
4958 case OP_CALL_MEMBASE:
4959 call = (MonoCallInst*)ins;
4961 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4962 ins->flags |= MONO_INST_GC_CALLSITE;
4963 ins->backend.pc_offset = code - cfg->native_code;
4964 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4965 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4966 code = emit_move_return_value (cfg, ins, code);
4970 MonoInst *var = cfg->dyn_call_var;
4972 g_assert (var->opcode == OP_REGOFFSET);
4974 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4975 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4977 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4979 /* Save args buffer */
4980 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4982 /* Set argument registers */
4983 for (i = 0; i < PARAM_REGS; ++i)
4984 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4987 amd64_call_reg (code, AMD64_R10);
4989 ins->flags |= MONO_INST_GC_CALLSITE;
4990 ins->backend.pc_offset = code - cfg->native_code;
4993 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4994 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4997 case OP_AMD64_SAVE_SP_TO_LMF: {
4998 MonoInst *lmf_var = cfg->arch.lmf_var;
4999 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5003 g_assert (!cfg->arch.no_pushes);
5004 amd64_push_reg (code, ins->sreg1);
5006 case OP_X86_PUSH_IMM:
5007 g_assert (!cfg->arch.no_pushes);
5008 g_assert (amd64_is_imm32 (ins->inst_imm));
5009 amd64_push_imm (code, ins->inst_imm);
5011 case OP_X86_PUSH_MEMBASE:
5012 g_assert (!cfg->arch.no_pushes);
5013 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5015 case OP_X86_PUSH_OBJ: {
5016 int size = ALIGN_TO (ins->inst_imm, 8);
5018 g_assert (!cfg->arch.no_pushes);
5020 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5021 amd64_push_reg (code, AMD64_RDI);
5022 amd64_push_reg (code, AMD64_RSI);
5023 amd64_push_reg (code, AMD64_RCX);
5024 if (ins->inst_offset)
5025 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5027 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5028 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5029 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5031 amd64_prefix (code, X86_REP_PREFIX);
5033 amd64_pop_reg (code, AMD64_RCX);
5034 amd64_pop_reg (code, AMD64_RSI);
5035 amd64_pop_reg (code, AMD64_RDI);
5039 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5041 case OP_X86_LEA_MEMBASE:
5042 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5045 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5048 /* keep alignment */
5049 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5050 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5051 code = mono_emit_stack_alloc (cfg, code, ins);
5052 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5053 if (cfg->param_area && cfg->arch.no_pushes)
5054 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5056 case OP_LOCALLOC_IMM: {
5057 guint32 size = ins->inst_imm;
5058 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5060 if (ins->flags & MONO_INST_INIT) {
5064 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5065 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5067 for (i = 0; i < size; i += 8)
5068 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5069 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5071 amd64_mov_reg_imm (code, ins->dreg, size);
5072 ins->sreg1 = ins->dreg;
5074 code = mono_emit_stack_alloc (cfg, code, ins);
5075 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5078 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5079 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5081 if (cfg->param_area && cfg->arch.no_pushes)
5082 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5086 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5087 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5088 (gpointer)"mono_arch_throw_exception", FALSE);
5089 ins->flags |= MONO_INST_GC_CALLSITE;
5090 ins->backend.pc_offset = code - cfg->native_code;
5094 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5095 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5096 (gpointer)"mono_arch_rethrow_exception", FALSE);
5097 ins->flags |= MONO_INST_GC_CALLSITE;
5098 ins->backend.pc_offset = code - cfg->native_code;
5101 case OP_CALL_HANDLER:
5103 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5104 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5105 amd64_call_imm (code, 0);
5106 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5107 /* Restore stack alignment */
5108 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5110 case OP_START_HANDLER: {
5111 /* Even though we're saving RSP, use sizeof */
5112 /* gpointer because spvar is of type IntPtr */
5113 /* see: mono_create_spvar_for_region */
5114 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5115 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5117 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5118 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5119 cfg->param_area && cfg->arch.no_pushes) {
5120 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5124 case OP_ENDFINALLY: {
5125 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5126 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5130 case OP_ENDFILTER: {
5131 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5132 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5133 /* The local allocator will put the result into RAX */
5139 ins->inst_c0 = code - cfg->native_code;
5142 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5143 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5145 if (ins->inst_target_bb->native_offset) {
5146 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5148 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5149 if ((cfg->opt & MONO_OPT_BRANCH) &&
5150 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5151 x86_jump8 (code, 0);
5153 x86_jump32 (code, 0);
5157 amd64_jump_reg (code, ins->sreg1);
5180 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5181 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5183 case OP_COND_EXC_EQ:
5184 case OP_COND_EXC_NE_UN:
5185 case OP_COND_EXC_LT:
5186 case OP_COND_EXC_LT_UN:
5187 case OP_COND_EXC_GT:
5188 case OP_COND_EXC_GT_UN:
5189 case OP_COND_EXC_GE:
5190 case OP_COND_EXC_GE_UN:
5191 case OP_COND_EXC_LE:
5192 case OP_COND_EXC_LE_UN:
5193 case OP_COND_EXC_IEQ:
5194 case OP_COND_EXC_INE_UN:
5195 case OP_COND_EXC_ILT:
5196 case OP_COND_EXC_ILT_UN:
5197 case OP_COND_EXC_IGT:
5198 case OP_COND_EXC_IGT_UN:
5199 case OP_COND_EXC_IGE:
5200 case OP_COND_EXC_IGE_UN:
5201 case OP_COND_EXC_ILE:
5202 case OP_COND_EXC_ILE_UN:
5203 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5205 case OP_COND_EXC_OV:
5206 case OP_COND_EXC_NO:
5208 case OP_COND_EXC_NC:
5209 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5210 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5212 case OP_COND_EXC_IOV:
5213 case OP_COND_EXC_INO:
5214 case OP_COND_EXC_IC:
5215 case OP_COND_EXC_INC:
5216 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5217 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5220 /* floating point opcodes */
5222 double d = *(double *)ins->inst_p0;
5224 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5225 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5228 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5229 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5234 float f = *(float *)ins->inst_p0;
5236 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5237 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5240 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5241 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5242 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5246 case OP_STORER8_MEMBASE_REG:
5247 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5249 case OP_LOADR8_MEMBASE:
5250 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5252 case OP_STORER4_MEMBASE_REG:
5253 /* This requires a double->single conversion */
5254 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5255 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5257 case OP_LOADR4_MEMBASE:
5258 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5259 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5261 case OP_ICONV_TO_R4: /* FIXME: change precision */
5262 case OP_ICONV_TO_R8:
5263 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5265 case OP_LCONV_TO_R4: /* FIXME: change precision */
5266 case OP_LCONV_TO_R8:
5267 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5269 case OP_FCONV_TO_R4:
5270 /* FIXME: nothing to do ?? */
5272 case OP_FCONV_TO_I1:
5273 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5275 case OP_FCONV_TO_U1:
5276 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5278 case OP_FCONV_TO_I2:
5279 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5281 case OP_FCONV_TO_U2:
5282 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5284 case OP_FCONV_TO_U4:
5285 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5287 case OP_FCONV_TO_I4:
5289 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5291 case OP_FCONV_TO_I8:
5292 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5294 case OP_LCONV_TO_R_UN: {
5297 /* Based on gcc code */
5298 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5299 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5302 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5303 br [1] = code; x86_jump8 (code, 0);
5304 amd64_patch (br [0], code);
5307 /* Save to the red zone */
5308 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5309 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5310 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5311 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5312 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5313 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5314 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5315 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5316 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5318 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5319 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5320 amd64_patch (br [1], code);
5323 case OP_LCONV_TO_OVF_U4:
5324 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5325 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5326 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5328 case OP_LCONV_TO_OVF_I4_UN:
5329 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5330 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5331 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5334 if (ins->dreg != ins->sreg1)
5335 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5338 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5341 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5344 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5347 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5350 static double r8_0 = -0.0;
5352 g_assert (ins->sreg1 == ins->dreg);
5354 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5355 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5359 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5362 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5365 static guint64 d = 0x7fffffffffffffffUL;
5367 g_assert (ins->sreg1 == ins->dreg);
5369 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5370 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5374 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5377 g_assert (cfg->opt & MONO_OPT_CMOV);
5378 g_assert (ins->dreg == ins->sreg1);
5379 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5380 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5383 g_assert (cfg->opt & MONO_OPT_CMOV);
5384 g_assert (ins->dreg == ins->sreg1);
5385 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5386 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5389 g_assert (cfg->opt & MONO_OPT_CMOV);
5390 g_assert (ins->dreg == ins->sreg1);
5391 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5392 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5395 g_assert (cfg->opt & MONO_OPT_CMOV);
5396 g_assert (ins->dreg == ins->sreg1);
5397 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5398 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5401 g_assert (cfg->opt & MONO_OPT_CMOV);
5402 g_assert (ins->dreg == ins->sreg1);
5403 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5404 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5407 g_assert (cfg->opt & MONO_OPT_CMOV);
5408 g_assert (ins->dreg == ins->sreg1);
5409 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5410 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5413 g_assert (cfg->opt & MONO_OPT_CMOV);
5414 g_assert (ins->dreg == ins->sreg1);
5415 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5416 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5419 g_assert (cfg->opt & MONO_OPT_CMOV);
5420 g_assert (ins->dreg == ins->sreg1);
5421 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5422 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5428 * The two arguments are swapped because the fbranch instructions
5429 * depend on this for the non-sse case to work.
5431 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5435 /* zeroing the register at the start results in
5436 * shorter and faster code (we can also remove the widening op)
5438 guchar *unordered_check;
5439 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5440 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5441 unordered_check = code;
5442 x86_branch8 (code, X86_CC_P, 0, FALSE);
5444 if (ins->opcode == OP_FCEQ) {
5445 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5446 amd64_patch (unordered_check, code);
5448 guchar *jump_to_end;
5449 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5451 x86_jump8 (code, 0);
5452 amd64_patch (unordered_check, code);
5453 amd64_inc_reg (code, ins->dreg);
5454 amd64_patch (jump_to_end, code);
5460 /* zeroing the register at the start results in
5461 * shorter and faster code (we can also remove the widening op)
5463 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5464 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5465 if (ins->opcode == OP_FCLT_UN) {
5466 guchar *unordered_check = code;
5467 guchar *jump_to_end;
5468 x86_branch8 (code, X86_CC_P, 0, FALSE);
5469 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5471 x86_jump8 (code, 0);
5472 amd64_patch (unordered_check, code);
5473 amd64_inc_reg (code, ins->dreg);
5474 amd64_patch (jump_to_end, code);
5476 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5480 guchar *unordered_check;
5481 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5482 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5483 unordered_check = code;
5484 x86_branch8 (code, X86_CC_P, 0, FALSE);
5485 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5486 amd64_patch (unordered_check, code);
5491 /* zeroing the register at the start results in
5492 * shorter and faster code (we can also remove the widening op)
5494 guchar *unordered_check;
5495 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5496 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5497 if (ins->opcode == OP_FCGT) {
5498 unordered_check = code;
5499 x86_branch8 (code, X86_CC_P, 0, FALSE);
5500 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5501 amd64_patch (unordered_check, code);
5503 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5508 guchar *unordered_check;
5509 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5510 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5511 unordered_check = code;
5512 x86_branch8 (code, X86_CC_P, 0, FALSE);
5513 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5514 amd64_patch (unordered_check, code);
5518 case OP_FCLT_MEMBASE:
5519 case OP_FCGT_MEMBASE:
5520 case OP_FCLT_UN_MEMBASE:
5521 case OP_FCGT_UN_MEMBASE:
5522 case OP_FCEQ_MEMBASE: {
5523 guchar *unordered_check, *jump_to_end;
5526 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5527 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5529 switch (ins->opcode) {
5530 case OP_FCEQ_MEMBASE:
5531 x86_cond = X86_CC_EQ;
5533 case OP_FCLT_MEMBASE:
5534 case OP_FCLT_UN_MEMBASE:
5535 x86_cond = X86_CC_LT;
5537 case OP_FCGT_MEMBASE:
5538 case OP_FCGT_UN_MEMBASE:
5539 x86_cond = X86_CC_GT;
5542 g_assert_not_reached ();
5545 unordered_check = code;
5546 x86_branch8 (code, X86_CC_P, 0, FALSE);
5547 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5549 switch (ins->opcode) {
5550 case OP_FCEQ_MEMBASE:
5551 case OP_FCLT_MEMBASE:
5552 case OP_FCGT_MEMBASE:
5553 amd64_patch (unordered_check, code);
5555 case OP_FCLT_UN_MEMBASE:
5556 case OP_FCGT_UN_MEMBASE:
5558 x86_jump8 (code, 0);
5559 amd64_patch (unordered_check, code);
5560 amd64_inc_reg (code, ins->dreg);
5561 amd64_patch (jump_to_end, code);
5569 guchar *jump = code;
5570 x86_branch8 (code, X86_CC_P, 0, TRUE);
5571 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5572 amd64_patch (jump, code);
5576 /* Branch if C013 != 100 */
5577 /* branch if !ZF or (PF|CF) */
5578 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5579 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5580 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5583 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5586 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5587 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5591 if (ins->opcode == OP_FBGT) {
5594 /* skip branch if C1=1 */
5596 x86_branch8 (code, X86_CC_P, 0, FALSE);
5597 /* branch if (C0 | C3) = 1 */
5598 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5599 amd64_patch (br1, code);
5602 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5606 /* Branch if C013 == 100 or 001 */
5609 /* skip branch if C1=1 */
5611 x86_branch8 (code, X86_CC_P, 0, FALSE);
5612 /* branch if (C0 | C3) = 1 */
5613 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5614 amd64_patch (br1, code);
5618 /* Branch if C013 == 000 */
5619 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5622 /* Branch if C013=000 or 100 */
5625 /* skip branch if C1=1 */
5627 x86_branch8 (code, X86_CC_P, 0, FALSE);
5628 /* branch if C0=0 */
5629 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5630 amd64_patch (br1, code);
5634 /* Branch if C013 != 001 */
5635 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5636 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5639 /* Transfer value to the fp stack */
5640 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5641 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5642 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5644 amd64_push_reg (code, AMD64_RAX);
5646 amd64_fnstsw (code);
5647 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5648 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5649 amd64_pop_reg (code, AMD64_RAX);
5650 amd64_fstp (code, 0);
5651 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5652 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5655 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5658 case OP_TLS_GET_REG:
5659 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5662 case OP_MEMORY_BARRIER: {
5663 switch (ins->backend.memory_barrier_kind) {
5664 case StoreLoadBarrier:
5666 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5667 x86_prefix (code, X86_LOCK_PREFIX);
5668 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5673 case OP_ATOMIC_ADD_I4:
5674 case OP_ATOMIC_ADD_I8: {
5675 int dreg = ins->dreg;
5676 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5678 if (dreg == ins->inst_basereg)
5681 if (dreg != ins->sreg2)
5682 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5684 x86_prefix (code, X86_LOCK_PREFIX);
5685 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5687 if (dreg != ins->dreg)
5688 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5692 case OP_ATOMIC_ADD_NEW_I4:
5693 case OP_ATOMIC_ADD_NEW_I8: {
5694 int dreg = ins->dreg;
5695 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5697 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5700 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5701 amd64_prefix (code, X86_LOCK_PREFIX);
5702 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5703 /* dreg contains the old value, add with sreg2 value */
5704 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5706 if (ins->dreg != dreg)
5707 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5711 case OP_ATOMIC_EXCHANGE_I4:
5712 case OP_ATOMIC_EXCHANGE_I8: {
5714 int sreg2 = ins->sreg2;
5715 int breg = ins->inst_basereg;
5717 gboolean need_push = FALSE, rdx_pushed = FALSE;
5719 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5725 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5726 * an explanation of how this works.
5729 /* cmpxchg uses eax as comperand, need to make sure we can use it
5730 * hack to overcome limits in x86 reg allocator
5731 * (req: dreg == eax and sreg2 != eax and breg != eax)
5733 g_assert (ins->dreg == AMD64_RAX);
5735 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5736 /* Highly unlikely, but possible */
5739 /* The pushes invalidate rsp */
5740 if ((breg == AMD64_RAX) || need_push) {
5741 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5745 /* We need the EAX reg for the comparand */
5746 if (ins->sreg2 == AMD64_RAX) {
5747 if (breg != AMD64_R11) {
5748 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5751 g_assert (need_push);
5752 amd64_push_reg (code, AMD64_RDX);
5753 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5759 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5761 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5762 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5763 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5764 amd64_patch (br [1], br [0]);
5767 amd64_pop_reg (code, AMD64_RDX);
5771 case OP_ATOMIC_CAS_I4:
5772 case OP_ATOMIC_CAS_I8: {
5775 if (ins->opcode == OP_ATOMIC_CAS_I8)
5781 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5782 * an explanation of how this works.
5784 g_assert (ins->sreg3 == AMD64_RAX);
5785 g_assert (ins->sreg1 != AMD64_RAX);
5786 g_assert (ins->sreg1 != ins->sreg2);
5788 amd64_prefix (code, X86_LOCK_PREFIX);
5789 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5791 if (ins->dreg != AMD64_RAX)
5792 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5795 case OP_CARD_TABLE_WBARRIER: {
5796 int ptr = ins->sreg1;
5797 int value = ins->sreg2;
5799 int nursery_shift, card_table_shift;
5800 gpointer card_table_mask;
5801 size_t nursery_size;
5803 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5804 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5805 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5807 /*If either point to the stack we can simply avoid the WB. This happens due to
5808 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5810 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5814 * We need one register we can clobber, we choose EDX and make sreg1
5815 * fixed EAX to work around limitations in the local register allocator.
5816 * sreg2 might get allocated to EDX, but that is not a problem since
5817 * we use it before clobbering EDX.
5819 g_assert (ins->sreg1 == AMD64_RAX);
5822 * This is the code we produce:
5825 * edx >>= nursery_shift
5826 * cmp edx, (nursery_start >> nursery_shift)
5829 * edx >>= card_table_shift
5835 if (mono_gc_card_table_nursery_check ()) {
5836 if (value != AMD64_RDX)
5837 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5838 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5839 if (shifted_nursery_start >> 31) {
5841 * The value we need to compare against is 64 bits, so we need
5842 * another spare register. We use RBX, which we save and
5845 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5846 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5847 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5848 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5850 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5852 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5854 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5855 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5856 if (card_table_mask)
5857 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5859 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5860 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5862 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5864 if (mono_gc_card_table_nursery_check ())
5865 x86_patch (br, code);
5868 #ifdef MONO_ARCH_SIMD_INTRINSICS
5869 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5871 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5874 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5877 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5880 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5883 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5886 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5889 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5890 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5893 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5896 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5899 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5902 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5905 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5908 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5911 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5914 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5923 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5926 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5929 case OP_PSHUFLEW_HIGH:
5930 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5931 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5933 case OP_PSHUFLEW_LOW:
5934 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5935 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5938 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5939 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5942 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5943 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5946 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5947 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5951 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5954 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5969 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5970 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5973 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5979 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5982 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5985 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5988 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6000 case OP_EXTRACT_MASK:
6001 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6005 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6008 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6011 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6021 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6024 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6028 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6031 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6034 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6037 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6044 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6047 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6051 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6054 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6057 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6064 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6071 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6074 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6078 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6081 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6084 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6088 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6097 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6101 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6104 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6107 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6110 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6113 case OP_PSUM_ABS_DIFF:
6114 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6117 case OP_UNPACK_LOWB:
6118 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6120 case OP_UNPACK_LOWW:
6121 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6123 case OP_UNPACK_LOWD:
6124 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6126 case OP_UNPACK_LOWQ:
6127 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6129 case OP_UNPACK_LOWPS:
6130 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6132 case OP_UNPACK_LOWPD:
6133 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6136 case OP_UNPACK_HIGHB:
6137 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6139 case OP_UNPACK_HIGHW:
6140 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6142 case OP_UNPACK_HIGHD:
6143 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6145 case OP_UNPACK_HIGHQ:
6146 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6148 case OP_UNPACK_HIGHPS:
6149 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6151 case OP_UNPACK_HIGHPD:
6152 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6156 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6159 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6162 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6165 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6168 case OP_PADDB_SAT_UN:
6169 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6171 case OP_PSUBB_SAT_UN:
6172 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6174 case OP_PADDW_SAT_UN:
6175 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6177 case OP_PSUBW_SAT_UN:
6178 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6182 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6185 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6188 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6191 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6195 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6198 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6201 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6203 case OP_PMULW_HIGH_UN:
6204 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6207 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6211 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6214 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6218 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6221 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6225 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6228 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6232 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6235 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6239 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6242 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6246 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6249 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6253 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6256 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6259 /*TODO: This is appart of the sse spec but not added
6261 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6264 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6269 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6272 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6275 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6278 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6281 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6284 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6287 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6290 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6293 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6296 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6300 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6303 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6307 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6308 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6310 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6315 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6317 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6318 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6322 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6324 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6325 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6326 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6330 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6332 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6335 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6337 case OP_EXTRACTX_U2:
6338 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6340 case OP_INSERTX_U1_SLOW:
6341 /*sreg1 is the extracted ireg (scratch)
6342 /sreg2 is the to be inserted ireg (scratch)
6343 /dreg is the xreg to receive the value*/
6345 /*clear the bits from the extracted word*/
6346 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6347 /*shift the value to insert if needed*/
6348 if (ins->inst_c0 & 1)
6349 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6350 /*join them together*/
6351 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6352 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6354 case OP_INSERTX_I4_SLOW:
6355 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6356 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6357 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6359 case OP_INSERTX_I8_SLOW:
6360 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6362 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6364 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6367 case OP_INSERTX_R4_SLOW:
6368 switch (ins->inst_c0) {
6370 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6373 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6374 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6375 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6378 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6379 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6380 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6383 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6384 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6385 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6389 case OP_INSERTX_R8_SLOW:
6391 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6393 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6395 case OP_STOREX_MEMBASE_REG:
6396 case OP_STOREX_MEMBASE:
6397 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6399 case OP_LOADX_MEMBASE:
6400 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6402 case OP_LOADX_ALIGNED_MEMBASE:
6403 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6405 case OP_STOREX_ALIGNED_MEMBASE_REG:
6406 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6408 case OP_STOREX_NTA_MEMBASE_REG:
6409 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6411 case OP_PREFETCH_MEMBASE:
6412 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6416 /*FIXME the peephole pass should have killed this*/
6417 if (ins->dreg != ins->sreg1)
6418 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6421 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6423 case OP_ICONV_TO_R8_RAW:
6424 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6425 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6428 case OP_FCONV_TO_R8_X:
6429 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6432 case OP_XCONV_R8_TO_I4:
6433 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6434 switch (ins->backend.source_opcode) {
6435 case OP_FCONV_TO_I1:
6436 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6438 case OP_FCONV_TO_U1:
6439 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6441 case OP_FCONV_TO_I2:
6442 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6444 case OP_FCONV_TO_U2:
6445 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6451 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6452 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6453 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6456 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6457 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6460 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6461 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6464 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6465 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6466 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6469 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6470 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6473 case OP_LIVERANGE_START: {
6474 if (cfg->verbose_level > 1)
6475 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6476 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6479 case OP_LIVERANGE_END: {
6480 if (cfg->verbose_level > 1)
6481 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6482 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6485 case OP_NACL_GC_SAFE_POINT: {
6486 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6487 if (cfg->compile_aot)
6488 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6492 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6493 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6494 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6495 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6496 amd64_patch (br[0], code);
6501 case OP_GC_LIVENESS_DEF:
6502 case OP_GC_LIVENESS_USE:
6503 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6504 ins->backend.pc_offset = code - cfg->native_code;
6506 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6507 ins->backend.pc_offset = code - cfg->native_code;
6508 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6511 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6512 g_assert_not_reached ();
6515 if ((code - cfg->native_code - offset) > max_len) {
6516 #if !defined(__native_client_codegen__)
6517 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6518 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6519 g_assert_not_reached ();
6524 last_offset = offset;
6527 cfg->code_len = code - cfg->native_code;
6530 #endif /* DISABLE_JIT */
6533 mono_arch_register_lowlevel_calls (void)
6535 /* The signature doesn't matter */
6536 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6540 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6542 MonoJumpInfo *patch_info;
6543 gboolean compile_aot = !run_cctors;
6545 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6546 unsigned char *ip = patch_info->ip.i + code;
6547 unsigned char *target;
6550 switch (patch_info->type) {
6551 case MONO_PATCH_INFO_BB:
6552 case MONO_PATCH_INFO_LABEL:
6555 /* No need to patch these */
6560 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6562 switch (patch_info->type) {
6563 case MONO_PATCH_INFO_NONE:
6565 case MONO_PATCH_INFO_METHOD_REL:
6566 case MONO_PATCH_INFO_R8:
6567 case MONO_PATCH_INFO_R4:
6568 g_assert_not_reached ();
6570 case MONO_PATCH_INFO_BB:
6577 * Debug code to help track down problems where the target of a near call is
6580 if (amd64_is_near_call (ip)) {
6581 gint64 disp = (guint8*)target - (guint8*)ip;
6583 if (!amd64_is_imm32 (disp)) {
6584 printf ("TYPE: %d\n", patch_info->type);
6585 switch (patch_info->type) {
6586 case MONO_PATCH_INFO_INTERNAL_METHOD:
6587 printf ("V: %s\n", patch_info->data.name);
6589 case MONO_PATCH_INFO_METHOD_JUMP:
6590 case MONO_PATCH_INFO_METHOD:
6591 printf ("V: %s\n", patch_info->data.method->name);
6599 amd64_patch (ip, (gpointer)target);
6606 get_max_epilog_size (MonoCompile *cfg)
6608 int max_epilog_size = 16;
6610 if (cfg->method->save_lmf)
6611 max_epilog_size += 256;
6613 if (mono_jit_trace_calls != NULL)
6614 max_epilog_size += 50;
6616 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6617 max_epilog_size += 50;
6619 max_epilog_size += (AMD64_NREG * 2);
6621 return max_epilog_size;
6625 * This macro is used for testing whenever the unwinder works correctly at every point
6626 * where an async exception can happen.
6628 /* This will generate a SIGSEGV at the given point in the code */
6629 #define async_exc_point(code) do { \
6630 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6631 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6632 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6633 cfg->arch.async_point_count ++; \
6638 mono_arch_emit_prolog (MonoCompile *cfg)
6640 MonoMethod *method = cfg->method;
6642 MonoMethodSignature *sig;
6644 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6647 MonoInst *lmf_var = cfg->arch.lmf_var;
6648 gboolean args_clobbered = FALSE;
6649 gboolean trace = FALSE;
6650 #ifdef __native_client_codegen__
6651 guint alignment_check;
6654 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6656 #if defined(__default_codegen__)
6657 code = cfg->native_code = g_malloc (cfg->code_size);
6658 #elif defined(__native_client_codegen__)
6659 /* native_code_alloc is not 32-byte aligned, native_code is. */
6660 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6662 /* Align native_code to next nearest kNaclAlignment byte. */
6663 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6664 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6666 code = cfg->native_code;
6668 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6669 g_assert (alignment_check == 0);
6672 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6675 /* Amount of stack space allocated by register saving code */
6678 /* Offset between RSP and the CFA */
6682 * The prolog consists of the following parts:
6684 * - push rbp, mov rbp, rsp
6685 * - save callee saved regs using pushes
6687 * - save rgctx if needed
6688 * - save lmf if needed
6691 * - save rgctx if needed
6692 * - save lmf if needed
6693 * - save callee saved regs using moves
6698 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6699 // IP saved at CFA - 8
6700 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6701 async_exc_point (code);
6702 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6704 if (!cfg->arch.omit_fp) {
6705 amd64_push_reg (code, AMD64_RBP);
6707 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6708 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6709 async_exc_point (code);
6711 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6713 /* These are handled automatically by the stack marking code */
6714 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6716 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6717 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6718 async_exc_point (code);
6720 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6724 /* Save callee saved registers */
6725 if (!cfg->arch.omit_fp && !method->save_lmf) {
6726 int offset = cfa_offset;
6728 for (i = 0; i < AMD64_NREG; ++i)
6729 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6730 amd64_push_reg (code, i);
6731 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6733 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6734 async_exc_point (code);
6736 /* These are handled automatically by the stack marking code */
6737 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
6741 /* The param area is always at offset 0 from sp */
6742 /* This needs to be allocated here, since it has to come after the spill area */
6743 if (cfg->arch.no_pushes && cfg->param_area) {
6744 if (cfg->arch.omit_fp)
6746 g_assert_not_reached ();
6747 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6750 if (cfg->arch.omit_fp) {
6752 * On enter, the stack is misaligned by the pushing of the return
6753 * address. It is either made aligned by the pushing of %rbp, or by
6756 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6757 if ((alloc_size % 16) == 0) {
6759 /* Mark the padding slot as NOREF */
6760 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6763 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6764 if (cfg->stack_offset != alloc_size) {
6765 /* Mark the padding slot as NOREF */
6766 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6768 cfg->arch.sp_fp_offset = alloc_size;
6772 cfg->arch.stack_alloc_size = alloc_size;
6774 /* Allocate stack frame */
6776 /* See mono_emit_stack_alloc */
6777 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6778 guint32 remaining_size = alloc_size;
6779 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6780 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6781 guint32 offset = code - cfg->native_code;
6782 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6783 while (required_code_size >= (cfg->code_size - offset))
6784 cfg->code_size *= 2;
6785 cfg->native_code = mono_realloc_native_code (cfg);
6786 code = cfg->native_code + offset;
6787 cfg->stat_code_reallocs++;
6790 while (remaining_size >= 0x1000) {
6791 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6792 if (cfg->arch.omit_fp) {
6793 cfa_offset += 0x1000;
6794 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6796 async_exc_point (code);
6798 if (cfg->arch.omit_fp)
6799 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6802 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6803 remaining_size -= 0x1000;
6805 if (remaining_size) {
6806 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6807 if (cfg->arch.omit_fp) {
6808 cfa_offset += remaining_size;
6809 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6810 async_exc_point (code);
6813 if (cfg->arch.omit_fp)
6814 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6818 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6819 if (cfg->arch.omit_fp) {
6820 cfa_offset += alloc_size;
6821 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6822 async_exc_point (code);
6827 /* Stack alignment check */
6830 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6831 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6832 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6833 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6834 amd64_breakpoint (code);
6838 #ifndef TARGET_WIN32
6839 if (mini_get_debug_options ()->init_stacks) {
6840 /* Fill the stack frame with a dummy value to force deterministic behavior */
6842 /* Save registers to the red zone */
6843 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6844 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6846 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6847 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6848 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6851 #if defined(__default_codegen__)
6852 amd64_prefix (code, X86_REP_PREFIX);
6854 #elif defined(__native_client_codegen__)
6855 /* NaCl stos pseudo-instruction */
6856 amd64_codegen_pre (code);
6857 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6858 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6859 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6860 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6861 amd64_prefix (code, X86_REP_PREFIX);
6863 amd64_codegen_post (code);
6864 #endif /* __native_client_codegen__ */
6866 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6867 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6872 if (method->save_lmf) {
6873 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6876 /* Save callee saved registers */
6877 if (cfg->arch.omit_fp && !method->save_lmf) {
6878 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6880 /* Save caller saved registers after sp is adjusted */
6881 /* The registers are saved at the bottom of the frame */
6882 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6883 for (i = 0; i < AMD64_NREG; ++i)
6884 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6885 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6886 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6888 /* These are handled automatically by the stack marking code */
6889 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6891 save_area_offset += 8;
6892 async_exc_point (code);
6896 /* store runtime generic context */
6897 if (cfg->rgctx_var) {
6898 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6899 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6901 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6903 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6904 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6907 /* compute max_length in order to use short forward jumps */
6908 max_epilog_size = get_max_epilog_size (cfg);
6909 if (cfg->opt & MONO_OPT_BRANCH) {
6910 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6914 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6916 /* max alignment for loops */
6917 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6918 max_length += LOOP_ALIGNMENT;
6919 #ifdef __native_client_codegen__
6920 /* max alignment for native client */
6921 max_length += kNaClAlignment;
6924 MONO_BB_FOR_EACH_INS (bb, ins) {
6925 #ifdef __native_client_codegen__
6927 int space_in_block = kNaClAlignment -
6928 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6929 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6930 if (space_in_block < max_len && max_len < kNaClAlignment) {
6931 max_length += space_in_block;
6934 #endif /*__native_client_codegen__*/
6935 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6938 /* Take prolog and epilog instrumentation into account */
6939 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6940 max_length += max_epilog_size;
6942 bb->max_length = max_length;
6946 sig = mono_method_signature (method);
6949 cinfo = cfg->arch.cinfo;
6951 if (sig->ret->type != MONO_TYPE_VOID) {
6952 /* Save volatile arguments to the stack */
6953 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6954 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6957 /* Keep this in sync with emit_load_volatile_arguments */
6958 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6959 ArgInfo *ainfo = cinfo->args + i;
6960 gint32 stack_offset;
6963 ins = cfg->args [i];
6965 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6966 /* Unused arguments */
6969 if (sig->hasthis && (i == 0))
6970 arg_type = &mono_defaults.object_class->byval_arg;
6972 arg_type = sig->params [i - sig->hasthis];
6974 stack_offset = ainfo->offset + ARGS_OFFSET;
6976 if (cfg->globalra) {
6977 /* All the other moves are done by the register allocator */
6978 switch (ainfo->storage) {
6979 case ArgInFloatSSEReg:
6980 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6982 case ArgValuetypeInReg:
6983 for (quad = 0; quad < 2; quad ++) {
6984 switch (ainfo->pair_storage [quad]) {
6986 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6988 case ArgInFloatSSEReg:
6989 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6991 case ArgInDoubleSSEReg:
6992 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6997 g_assert_not_reached ();
7008 /* Save volatile arguments to the stack */
7009 if (ins->opcode != OP_REGVAR) {
7010 switch (ainfo->storage) {
7016 if (stack_offset & 0x1)
7018 else if (stack_offset & 0x2)
7020 else if (stack_offset & 0x4)
7025 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7028 * Save the original location of 'this',
7029 * get_generic_info_from_stack_frame () needs this to properly look up
7030 * the argument value during the handling of async exceptions.
7032 if (ins == cfg->args [0]) {
7033 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7034 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7038 case ArgInFloatSSEReg:
7039 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7041 case ArgInDoubleSSEReg:
7042 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7044 case ArgValuetypeInReg:
7045 for (quad = 0; quad < 2; quad ++) {
7046 switch (ainfo->pair_storage [quad]) {
7048 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7050 case ArgInFloatSSEReg:
7051 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7053 case ArgInDoubleSSEReg:
7054 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7059 g_assert_not_reached ();
7063 case ArgValuetypeAddrInIReg:
7064 if (ainfo->pair_storage [0] == ArgInIReg)
7065 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7071 /* Argument allocated to (non-volatile) register */
7072 switch (ainfo->storage) {
7074 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7077 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7080 g_assert_not_reached ();
7083 if (ins == cfg->args [0]) {
7084 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7085 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7090 if (method->save_lmf) {
7091 code = emit_save_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7095 args_clobbered = TRUE;
7096 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7099 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7100 args_clobbered = TRUE;
7103 * Optimize the common case of the first bblock making a call with the same
7104 * arguments as the method. This works because the arguments are still in their
7105 * original argument registers.
7106 * FIXME: Generalize this
7108 if (!args_clobbered) {
7109 MonoBasicBlock *first_bb = cfg->bb_entry;
7112 next = mono_bb_first_ins (first_bb);
7113 if (!next && first_bb->next_bb) {
7114 first_bb = first_bb->next_bb;
7115 next = mono_bb_first_ins (first_bb);
7118 if (first_bb->in_count > 1)
7121 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7122 ArgInfo *ainfo = cinfo->args + i;
7123 gboolean match = FALSE;
7125 ins = cfg->args [i];
7126 if (ins->opcode != OP_REGVAR) {
7127 switch (ainfo->storage) {
7129 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7130 if (next->dreg == ainfo->reg) {
7134 next->opcode = OP_MOVE;
7135 next->sreg1 = ainfo->reg;
7136 /* Only continue if the instruction doesn't change argument regs */
7137 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7147 /* Argument allocated to (non-volatile) register */
7148 switch (ainfo->storage) {
7150 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7162 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7169 if (cfg->gen_seq_points) {
7170 MonoInst *info_var = cfg->arch.seq_point_info_var;
7172 /* Initialize seq_point_info_var */
7173 if (cfg->compile_aot) {
7174 /* Initialize the variable from a GOT slot */
7175 /* Same as OP_AOTCONST */
7176 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7177 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7178 g_assert (info_var->opcode == OP_REGOFFSET);
7179 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7182 /* Initialize ss_trigger_page_var */
7183 ins = cfg->arch.ss_trigger_page_var;
7185 g_assert (ins->opcode == OP_REGOFFSET);
7187 if (cfg->compile_aot) {
7188 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7189 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7191 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7193 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7196 cfg->code_len = code - cfg->native_code;
7198 g_assert (cfg->code_len < cfg->code_size);
7204 mono_arch_emit_epilog (MonoCompile *cfg)
7206 MonoMethod *method = cfg->method;
7209 int max_epilog_size;
7211 gint32 lmf_offset = cfg->arch.lmf_var ? ((MonoInst*)cfg->arch.lmf_var)->inst_offset : -1;
7213 max_epilog_size = get_max_epilog_size (cfg);
7215 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7216 cfg->code_size *= 2;
7217 cfg->native_code = mono_realloc_native_code (cfg);
7218 cfg->stat_code_reallocs++;
7221 code = cfg->native_code + cfg->code_len;
7223 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7224 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7226 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7229 if (method->save_lmf) {
7230 /* check if we need to restore protection of the stack after a stack overflow */
7231 if (mono_get_jit_tls_offset () != -1) {
7233 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7234 /* we load the value in a separate instruction: this mechanism may be
7235 * used later as a safer way to do thread interruption
7237 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7238 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7240 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7241 /* note that the call trampoline will preserve eax/edx */
7242 x86_call_reg (code, X86_ECX);
7243 x86_patch (patch, code);
7245 /* FIXME: maybe save the jit tls in the prolog */
7248 code = emit_restore_lmf (cfg, code, lmf_offset);
7250 /* Restore caller saved regs */
7251 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7252 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7254 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7255 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7257 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7258 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7260 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7261 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7263 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7264 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7266 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7267 #if defined(__default_codegen__)
7268 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7269 #elif defined(__native_client_codegen__)
7270 g_assert_not_reached();
7274 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7275 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7277 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7278 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7283 if (cfg->arch.omit_fp) {
7284 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7286 for (i = 0; i < AMD64_NREG; ++i)
7287 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7288 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
7289 save_area_offset += 8;
7293 for (i = 0; i < AMD64_NREG; ++i)
7294 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
7295 pos -= sizeof(mgreg_t);
7298 if (pos == - sizeof(mgreg_t)) {
7299 /* Only one register, so avoid lea */
7300 for (i = AMD64_NREG - 1; i > 0; --i)
7301 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7302 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7306 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7308 /* Pop registers in reverse order */
7309 for (i = AMD64_NREG - 1; i > 0; --i)
7310 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7311 amd64_pop_reg (code, i);
7318 /* Load returned vtypes into registers if needed */
7319 cinfo = cfg->arch.cinfo;
7320 if (cinfo->ret.storage == ArgValuetypeInReg) {
7321 ArgInfo *ainfo = &cinfo->ret;
7322 MonoInst *inst = cfg->ret;
7324 for (quad = 0; quad < 2; quad ++) {
7325 switch (ainfo->pair_storage [quad]) {
7327 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7329 case ArgInFloatSSEReg:
7330 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7332 case ArgInDoubleSSEReg:
7333 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7338 g_assert_not_reached ();
7343 if (cfg->arch.omit_fp) {
7344 if (cfg->arch.stack_alloc_size)
7345 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7349 async_exc_point (code);
7352 cfg->code_len = code - cfg->native_code;
7354 g_assert (cfg->code_len < cfg->code_size);
7358 mono_arch_emit_exceptions (MonoCompile *cfg)
7360 MonoJumpInfo *patch_info;
7363 MonoClass *exc_classes [16];
7364 guint8 *exc_throw_start [16], *exc_throw_end [16];
7365 guint32 code_size = 0;
7367 /* Compute needed space */
7368 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7369 if (patch_info->type == MONO_PATCH_INFO_EXC)
7371 if (patch_info->type == MONO_PATCH_INFO_R8)
7372 code_size += 8 + 15; /* sizeof (double) + alignment */
7373 if (patch_info->type == MONO_PATCH_INFO_R4)
7374 code_size += 4 + 15; /* sizeof (float) + alignment */
7375 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7376 code_size += 8 + 7; /*sizeof (void*) + alignment */
7379 #ifdef __native_client_codegen__
7380 /* Give us extra room on Native Client. This could be */
7381 /* more carefully calculated, but bundle alignment makes */
7382 /* it much trickier, so *2 like other places is good. */
7386 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7387 cfg->code_size *= 2;
7388 cfg->native_code = mono_realloc_native_code (cfg);
7389 cfg->stat_code_reallocs++;
7392 code = cfg->native_code + cfg->code_len;
7394 /* add code to raise exceptions */
7396 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7397 switch (patch_info->type) {
7398 case MONO_PATCH_INFO_EXC: {
7399 MonoClass *exc_class;
7403 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7405 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7406 g_assert (exc_class);
7407 throw_ip = patch_info->ip.i;
7409 //x86_breakpoint (code);
7410 /* Find a throw sequence for the same exception class */
7411 for (i = 0; i < nthrows; ++i)
7412 if (exc_classes [i] == exc_class)
7415 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7416 x86_jump_code (code, exc_throw_start [i]);
7417 patch_info->type = MONO_PATCH_INFO_NONE;
7421 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7425 exc_classes [nthrows] = exc_class;
7426 exc_throw_start [nthrows] = code;
7428 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7430 patch_info->type = MONO_PATCH_INFO_NONE;
7432 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7434 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7439 exc_throw_end [nthrows] = code;
7449 g_assert(code < cfg->native_code + cfg->code_size);
7452 /* Handle relocations with RIP relative addressing */
7453 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7454 gboolean remove = FALSE;
7455 guint8 *orig_code = code;
7457 switch (patch_info->type) {
7458 case MONO_PATCH_INFO_R8:
7459 case MONO_PATCH_INFO_R4: {
7460 guint8 *pos, *patch_pos;
7463 /* The SSE opcodes require a 16 byte alignment */
7464 #if defined(__default_codegen__)
7465 code = (guint8*)ALIGN_TO (code, 16);
7466 #elif defined(__native_client_codegen__)
7468 /* Pad this out with HLT instructions */
7469 /* or we can get garbage bytes emitted */
7470 /* which will fail validation */
7471 guint8 *aligned_code;
7472 /* extra align to make room for */
7473 /* mov/push below */
7474 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7475 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7476 /* The technique of hiding data in an */
7477 /* instruction has a problem here: we */
7478 /* need the data aligned to a 16-byte */
7479 /* boundary but the instruction cannot */
7480 /* cross the bundle boundary. so only */
7481 /* odd multiples of 16 can be used */
7482 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7485 while (code < aligned_code) {
7486 *(code++) = 0xf4; /* hlt */
7491 pos = cfg->native_code + patch_info->ip.i;
7492 if (IS_REX (pos [1])) {
7493 patch_pos = pos + 5;
7494 target_pos = code - pos - 9;
7497 patch_pos = pos + 4;
7498 target_pos = code - pos - 8;
7501 if (patch_info->type == MONO_PATCH_INFO_R8) {
7502 #ifdef __native_client_codegen__
7503 /* Hide 64-bit data in a */
7504 /* "mov imm64, r11" instruction. */
7505 /* write it before the start of */
7507 *(code-2) = 0x49; /* prefix */
7508 *(code-1) = 0xbb; /* mov X, %r11 */
7510 *(double*)code = *(double*)patch_info->data.target;
7511 code += sizeof (double);
7513 #ifdef __native_client_codegen__
7514 /* Hide 32-bit data in a */
7515 /* "push imm32" instruction. */
7516 *(code-1) = 0x68; /* push */
7518 *(float*)code = *(float*)patch_info->data.target;
7519 code += sizeof (float);
7522 *(guint32*)(patch_pos) = target_pos;
7527 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7530 if (cfg->compile_aot)
7533 /*loading is faster against aligned addresses.*/
7534 code = (guint8*)ALIGN_TO (code, 8);
7535 memset (orig_code, 0, code - orig_code);
7537 pos = cfg->native_code + patch_info->ip.i;
7539 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7540 if (IS_REX (pos [1]))
7541 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7543 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7545 *(gpointer*)code = (gpointer)patch_info->data.target;
7546 code += sizeof (gpointer);
7556 if (patch_info == cfg->patch_info)
7557 cfg->patch_info = patch_info->next;
7561 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7563 tmp->next = patch_info->next;
7566 g_assert (code < cfg->native_code + cfg->code_size);
7569 cfg->code_len = code - cfg->native_code;
7571 g_assert (cfg->code_len < cfg->code_size);
7575 #endif /* DISABLE_JIT */
7578 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7581 CallInfo *cinfo = NULL;
7582 MonoMethodSignature *sig;
7584 int i, n, stack_area = 0;
7586 /* Keep this in sync with mono_arch_get_argument_info */
7588 if (enable_arguments) {
7589 /* Allocate a new area on the stack and save arguments there */
7590 sig = mono_method_signature (cfg->method);
7592 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7594 n = sig->param_count + sig->hasthis;
7596 stack_area = ALIGN_TO (n * 8, 16);
7598 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7600 for (i = 0; i < n; ++i) {
7601 inst = cfg->args [i];
7603 if (inst->opcode == OP_REGVAR)
7604 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7606 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7607 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7612 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7613 amd64_set_reg_template (code, AMD64_ARG_REG1);
7614 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7615 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7617 if (enable_arguments)
7618 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7632 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7635 int save_mode = SAVE_NONE;
7636 MonoMethod *method = cfg->method;
7637 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7640 switch (ret_type->type) {
7641 case MONO_TYPE_VOID:
7642 /* special case string .ctor icall */
7643 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7644 save_mode = SAVE_EAX;
7646 save_mode = SAVE_NONE;
7650 save_mode = SAVE_EAX;
7654 save_mode = SAVE_XMM;
7656 case MONO_TYPE_GENERICINST:
7657 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7658 save_mode = SAVE_EAX;
7662 case MONO_TYPE_VALUETYPE:
7663 save_mode = SAVE_STRUCT;
7666 save_mode = SAVE_EAX;
7670 /* Save the result and copy it into the proper argument register */
7671 switch (save_mode) {
7673 amd64_push_reg (code, AMD64_RAX);
7675 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7676 if (enable_arguments)
7677 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7681 if (enable_arguments)
7682 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7685 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7686 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7688 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7690 * The result is already in the proper argument register so no copying
7697 g_assert_not_reached ();
7700 /* Set %al since this is a varargs call */
7701 if (save_mode == SAVE_XMM)
7702 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7704 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7706 if (preserve_argument_registers) {
7707 for (i = 0; i < PARAM_REGS; ++i)
7708 amd64_push_reg (code, param_regs [i]);
7711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7712 amd64_set_reg_template (code, AMD64_ARG_REG1);
7713 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7715 if (preserve_argument_registers) {
7716 for (i = PARAM_REGS - 1; i >= 0; --i)
7717 amd64_pop_reg (code, param_regs [i]);
7720 /* Restore result */
7721 switch (save_mode) {
7723 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7724 amd64_pop_reg (code, AMD64_RAX);
7730 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7731 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7732 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7737 g_assert_not_reached ();
7744 mono_arch_flush_icache (guint8 *code, gint size)
7750 mono_arch_flush_register_windows (void)
7755 mono_arch_is_inst_imm (gint64 imm)
7757 return amd64_is_imm32 (imm);
7761 * Determine whenever the trap whose info is in SIGINFO is caused by
7765 mono_arch_is_int_overflow (void *sigctx, void *info)
7772 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7774 rip = (guint8*)ctx.rip;
7776 if (IS_REX (rip [0])) {
7777 reg = amd64_rex_b (rip [0]);
7783 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7785 reg += x86_modrm_rm (rip [1]);
7825 g_assert_not_reached ();
7837 mono_arch_get_patch_offset (guint8 *code)
7843 * mono_breakpoint_clean_code:
7845 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7846 * breakpoints in the original code, they are removed in the copy.
7848 * Returns TRUE if no sw breakpoint was present.
7851 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7854 gboolean can_write = TRUE;
7856 * If method_start is non-NULL we need to perform bound checks, since we access memory
7857 * at code - offset we could go before the start of the method and end up in a different
7858 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7861 if (!method_start || code - offset >= method_start) {
7862 memcpy (buf, code - offset, size);
7864 int diff = code - method_start;
7865 memset (buf, 0, size);
7866 memcpy (buf + offset - diff, method_start, diff + size - offset);
7869 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7870 int idx = mono_breakpoint_info_index [i];
7874 ptr = mono_breakpoint_info [idx].address;
7875 if (ptr >= code && ptr < code + size) {
7876 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7878 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7879 buf [ptr - code] = saved_byte;
7885 #if defined(__native_client_codegen__)
7886 /* For membase calls, we want the base register. for Native Client, */
7887 /* all indirect calls have the following sequence with the given sizes: */
7888 /* mov %eXX,%eXX [2-3] */
7889 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7890 /* and $0xffffffffffffffe0,%r11d [4] */
7891 /* add %r15,%r11 [3] */
7892 /* callq *%r11 [3] */
7895 /* Determine if code points to a NaCl call-through-register sequence, */
7896 /* (i.e., the last 3 instructions listed above) */
7898 is_nacl_call_reg_sequence(guint8* code)
7900 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7901 "\x4d\x03\xdf" /* add */
7902 "\x41\xff\xd3"; /* call */
7903 return memcmp(code, sequence, 10) == 0;
7906 /* Determine if code points to the first opcode of the mov membase component */
7907 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7908 /* (there could be a REX prefix before the opcode but it is ignored) */
7910 is_nacl_indirect_call_membase_sequence(guint8* code)
7912 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7913 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7914 /* and that src reg = dest reg */
7915 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7916 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7918 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7919 /* and has dst of r11 and base of r15 */
7920 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7921 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7923 #endif /* __native_client_codegen__ */
7926 mono_arch_get_this_arg_reg (guint8 *code)
7928 return AMD64_ARG_REG1;
7932 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7934 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7937 #define MAX_ARCH_DELEGATE_PARAMS 10
7940 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7942 guint8 *code, *start;
7946 start = code = mono_global_codeman_reserve (64);
7948 /* Replace the this argument with the target */
7949 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7950 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7951 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7953 g_assert ((code - start) < 64);
7955 start = code = mono_global_codeman_reserve (64);
7957 if (param_count == 0) {
7958 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7960 /* We have to shift the arguments left */
7961 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7962 for (i = 0; i < param_count; ++i) {
7965 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7967 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7969 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7973 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7975 g_assert ((code - start) < 64);
7978 nacl_global_codeman_validate(&start, 64, &code);
7980 mono_debug_add_delegate_trampoline (start, code - start);
7983 *code_len = code - start;
7986 if (mono_jit_map_is_enabled ()) {
7989 buff = (char*)"delegate_invoke_has_target";
7991 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7992 mono_emit_jit_tramp (start, code - start, buff);
8001 * mono_arch_get_delegate_invoke_impls:
8003 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8007 mono_arch_get_delegate_invoke_impls (void)
8015 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8016 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8018 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8019 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8020 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8021 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8022 g_free (tramp_name);
8029 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8031 guint8 *code, *start;
8034 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8037 /* FIXME: Support more cases */
8038 if (MONO_TYPE_ISSTRUCT (sig->ret))
8042 static guint8* cached = NULL;
8048 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8050 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8052 mono_memory_barrier ();
8056 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8057 for (i = 0; i < sig->param_count; ++i)
8058 if (!mono_is_regsize_var (sig->params [i]))
8060 if (sig->param_count > 4)
8063 code = cache [sig->param_count];
8067 if (mono_aot_only) {
8068 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8069 start = mono_aot_get_trampoline (name);
8072 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8075 mono_memory_barrier ();
8077 cache [sig->param_count] = start;
8083 mono_arch_finish_init (void)
8087 * We need to init this multiple times, since when we are first called, the key might not
8088 * be initialized yet.
8090 appdomain_tls_offset = mono_domain_get_tls_key ();
8091 lmf_tls_offset = mono_get_jit_tls_key ();
8092 lmf_addr_tls_offset = mono_get_jit_tls_key ();
8094 /* Only 64 tls entries can be accessed using inline code */
8095 if (appdomain_tls_offset >= 64)
8096 appdomain_tls_offset = -1;
8097 if (lmf_tls_offset >= 64)
8098 lmf_tls_offset = -1;
8099 if (lmf_addr_tls_offset >= 64)
8100 lmf_addr_tls_offset = -1;
8103 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8105 appdomain_tls_offset = mono_domain_get_tls_offset ();
8106 lmf_tls_offset = mono_get_lmf_tls_offset ();
8107 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
8112 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8116 #ifdef MONO_ARCH_HAVE_IMT
8118 #if defined(__default_codegen__)
8119 #define CMP_SIZE (6 + 1)
8120 #define CMP_REG_REG_SIZE (4 + 1)
8121 #define BR_SMALL_SIZE 2
8122 #define BR_LARGE_SIZE 6
8123 #define MOV_REG_IMM_SIZE 10
8124 #define MOV_REG_IMM_32BIT_SIZE 6
8125 #define JUMP_REG_SIZE (2 + 1)
8126 #elif defined(__native_client_codegen__)
8127 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8128 #define CMP_SIZE ((6 + 1) * 2 - 1)
8129 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8130 #define BR_SMALL_SIZE (2 * 2 - 1)
8131 #define BR_LARGE_SIZE (6 * 2 - 1)
8132 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8133 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8134 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8135 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8136 /* Jump membase's size is large and unpredictable */
8137 /* in native client, just pad it out a whole bundle. */
8138 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8142 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8144 int i, distance = 0;
8145 for (i = start; i < target; ++i)
8146 distance += imt_entries [i]->chunk_size;
8151 * LOCKING: called with the domain lock held
8154 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8155 gpointer fail_tramp)
8159 guint8 *code, *start;
8160 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8162 for (i = 0; i < count; ++i) {
8163 MonoIMTCheckItem *item = imt_entries [i];
8164 if (item->is_equals) {
8165 if (item->check_target_idx) {
8166 if (!item->compare_done) {
8167 if (amd64_is_imm32 (item->key))
8168 item->chunk_size += CMP_SIZE;
8170 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8172 if (item->has_target_code) {
8173 item->chunk_size += MOV_REG_IMM_SIZE;
8175 if (vtable_is_32bit)
8176 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8178 item->chunk_size += MOV_REG_IMM_SIZE;
8179 #ifdef __native_client_codegen__
8180 item->chunk_size += JUMP_MEMBASE_SIZE;
8183 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8186 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8187 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8189 if (vtable_is_32bit)
8190 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8192 item->chunk_size += MOV_REG_IMM_SIZE;
8193 item->chunk_size += JUMP_REG_SIZE;
8194 /* with assert below:
8195 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8197 #ifdef __native_client_codegen__
8198 item->chunk_size += JUMP_MEMBASE_SIZE;
8203 if (amd64_is_imm32 (item->key))
8204 item->chunk_size += CMP_SIZE;
8206 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8207 item->chunk_size += BR_LARGE_SIZE;
8208 imt_entries [item->check_target_idx]->compare_done = TRUE;
8210 size += item->chunk_size;
8212 #if defined(__native_client__) && defined(__native_client_codegen__)
8213 /* In Native Client, we don't re-use thunks, allocate from the */
8214 /* normal code manager paths. */
8215 code = mono_domain_code_reserve (domain, size);
8218 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8220 code = mono_domain_code_reserve (domain, size);
8223 for (i = 0; i < count; ++i) {
8224 MonoIMTCheckItem *item = imt_entries [i];
8225 item->code_target = code;
8226 if (item->is_equals) {
8227 gboolean fail_case = !item->check_target_idx && fail_tramp;
8229 if (item->check_target_idx || fail_case) {
8230 if (!item->compare_done || fail_case) {
8231 if (amd64_is_imm32 (item->key))
8232 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8234 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8235 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8238 item->jmp_code = code;
8239 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8240 if (item->has_target_code) {
8241 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8242 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8244 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8245 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8249 amd64_patch (item->jmp_code, code);
8250 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8251 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8252 item->jmp_code = NULL;
8255 /* enable the commented code to assert on wrong method */
8257 if (amd64_is_imm32 (item->key))
8258 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8260 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8261 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8263 item->jmp_code = code;
8264 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8265 /* See the comment below about R10 */
8266 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8267 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8268 amd64_patch (item->jmp_code, code);
8269 amd64_breakpoint (code);
8270 item->jmp_code = NULL;
8272 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8273 needs to be preserved. R10 needs
8274 to be preserved for calls which
8275 require a runtime generic context,
8276 but interface calls don't. */
8277 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8278 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8282 if (amd64_is_imm32 (item->key))
8283 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8285 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8286 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8288 item->jmp_code = code;
8289 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8290 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8292 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8294 g_assert (code - item->code_target <= item->chunk_size);
8296 /* patch the branches to get to the target items */
8297 for (i = 0; i < count; ++i) {
8298 MonoIMTCheckItem *item = imt_entries [i];
8299 if (item->jmp_code) {
8300 if (item->check_target_idx) {
8301 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8307 mono_stats.imt_thunks_size += code - start;
8308 g_assert (code - start <= size);
8310 nacl_domain_code_validate(domain, &start, size, &code);
8316 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8318 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8323 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8325 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8329 mono_arch_get_cie_program (void)
8333 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8334 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8340 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8342 MonoInst *ins = NULL;
8345 if (cmethod->klass == mono_defaults.math_class) {
8346 if (strcmp (cmethod->name, "Sin") == 0) {
8348 } else if (strcmp (cmethod->name, "Cos") == 0) {
8350 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8352 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8357 MONO_INST_NEW (cfg, ins, opcode);
8358 ins->type = STACK_R8;
8359 ins->dreg = mono_alloc_freg (cfg);
8360 ins->sreg1 = args [0]->dreg;
8361 MONO_ADD_INS (cfg->cbb, ins);
8365 if (cfg->opt & MONO_OPT_CMOV) {
8366 if (strcmp (cmethod->name, "Min") == 0) {
8367 if (fsig->params [0]->type == MONO_TYPE_I4)
8369 if (fsig->params [0]->type == MONO_TYPE_U4)
8370 opcode = OP_IMIN_UN;
8371 else if (fsig->params [0]->type == MONO_TYPE_I8)
8373 else if (fsig->params [0]->type == MONO_TYPE_U8)
8374 opcode = OP_LMIN_UN;
8375 } else if (strcmp (cmethod->name, "Max") == 0) {
8376 if (fsig->params [0]->type == MONO_TYPE_I4)
8378 if (fsig->params [0]->type == MONO_TYPE_U4)
8379 opcode = OP_IMAX_UN;
8380 else if (fsig->params [0]->type == MONO_TYPE_I8)
8382 else if (fsig->params [0]->type == MONO_TYPE_U8)
8383 opcode = OP_LMAX_UN;
8388 MONO_INST_NEW (cfg, ins, opcode);
8389 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8390 ins->dreg = mono_alloc_ireg (cfg);
8391 ins->sreg1 = args [0]->dreg;
8392 ins->sreg2 = args [1]->dreg;
8393 MONO_ADD_INS (cfg->cbb, ins);
8397 /* OP_FREM is not IEEE compatible */
8398 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8399 MONO_INST_NEW (cfg, ins, OP_FREM);
8400 ins->inst_i0 = args [0];
8401 ins->inst_i1 = args [1];
8407 * Can't implement CompareExchange methods this way since they have
8415 mono_arch_print_tree (MonoInst *tree, int arity)
8420 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8424 if (appdomain_tls_offset == -1)
8427 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8428 ins->inst_offset = appdomain_tls_offset;
8432 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8435 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8438 case AMD64_RCX: return ctx->rcx;
8439 case AMD64_RDX: return ctx->rdx;
8440 case AMD64_RBX: return ctx->rbx;
8441 case AMD64_RBP: return ctx->rbp;
8442 case AMD64_RSP: return ctx->rsp;
8444 return _CTX_REG (ctx, rax, reg);
8449 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8468 _CTX_REG (ctx, rax, reg) = val;
8472 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8474 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8477 gpointer *sp, old_value;
8479 const unsigned char *handler;
8481 /*Decode the first instruction to figure out where did we store the spvar*/
8482 /*Our jit MUST generate the following:
8485 Which is encoded as: REX.W 0x89 mod_rm
8486 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8487 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8488 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8490 FIXME can we generate frameless methods on this case?
8493 handler = clause->handler_start;
8496 if (*handler != 0x48)
8501 if (*handler != 0x89)
8505 if (*handler == 0x65)
8506 offset = *(signed char*)(handler + 1);
8507 else if (*handler == 0xA5)
8508 offset = *(int*)(handler + 1);
8513 bp = MONO_CONTEXT_GET_BP (ctx);
8514 sp = *(gpointer*)(bp + offset);
8517 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8526 * mono_arch_emit_load_aotconst:
8528 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8529 * TARGET from the mscorlib GOT in full-aot code.
8530 * On AMD64, the result is placed into R11.
8533 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8535 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8536 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8542 * mono_arch_get_trampolines:
8544 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8548 mono_arch_get_trampolines (gboolean aot)
8550 return mono_amd64_get_exception_trampolines (aot);
8553 /* Soft Debug support */
8554 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8557 * mono_arch_set_breakpoint:
8559 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8560 * The location should contain code emitted by OP_SEQ_POINT.
8563 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8566 guint8 *orig_code = code;
8569 guint32 native_offset = ip - (guint8*)ji->code_start;
8570 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8572 g_assert (info->bp_addrs [native_offset] == 0);
8573 info->bp_addrs [native_offset] = bp_trigger_page;
8576 * In production, we will use int3 (has to fix the size in the md
8577 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8580 g_assert (code [0] == 0x90);
8581 if (breakpoint_size == 8) {
8582 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8584 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8585 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8588 g_assert (code - orig_code == breakpoint_size);
8593 * mono_arch_clear_breakpoint:
8595 * Clear the breakpoint at IP.
8598 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8604 guint32 native_offset = ip - (guint8*)ji->code_start;
8605 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8607 g_assert (info->bp_addrs [native_offset] == 0);
8608 info->bp_addrs [native_offset] = info;
8610 for (i = 0; i < breakpoint_size; ++i)
8616 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8619 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8622 siginfo_t* sinfo = (siginfo_t*) info;
8623 /* Sometimes the address is off by 4 */
8624 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8632 * mono_arch_skip_breakpoint:
8634 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8635 * we resume, the instruction is not executed again.
8638 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8641 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8642 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8644 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8649 * mono_arch_start_single_stepping:
8651 * Start single stepping.
8654 mono_arch_start_single_stepping (void)
8656 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8660 * mono_arch_stop_single_stepping:
8662 * Stop single stepping.
8665 mono_arch_stop_single_stepping (void)
8667 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8671 * mono_arch_is_single_step_event:
8673 * Return whenever the machine state in SIGCTX corresponds to a single
8677 mono_arch_is_single_step_event (void *info, void *sigctx)
8680 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8683 siginfo_t* sinfo = (siginfo_t*) info;
8684 /* Sometimes the address is off by 4 */
8685 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8693 * mono_arch_skip_single_step:
8695 * Modify CTX so the ip is placed after the single step trigger instruction,
8696 * we resume, the instruction is not executed again.
8699 mono_arch_skip_single_step (MonoContext *ctx)
8701 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8705 * mono_arch_create_seq_point_info:
8707 * Return a pointer to a data structure which is used by the sequence
8708 * point implementation in AOTed code.
8711 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8717 // FIXME: Add a free function
8719 mono_domain_lock (domain);
8720 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8722 mono_domain_unlock (domain);
8725 ji = mono_jit_info_table_find (domain, (char*)code);
8728 // FIXME: Optimize the size
8729 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8731 info->ss_trigger_page = ss_trigger_page;
8732 info->bp_trigger_page = bp_trigger_page;
8733 /* Initialize to a valid address */
8734 for (i = 0; i < ji->code_size; ++i)
8735 info->bp_addrs [i] = info;
8737 mono_domain_lock (domain);
8738 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8740 mono_domain_unlock (domain);
8747 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8749 ext->lmf.previous_lmf = prev_lmf;
8750 /* Mark that this is a MonoLMFExt */
8751 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8752 ext->lmf.rsp = (gssize)ext;