mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16
  17 #include <mono/metadata/appdomain.h>
  18 #include <mono/metadata/debug-helpers.h>
  19 #include <mono/metadata/threads.h>
  20 #include <mono/metadata/profiler-private.h>
  21 #include <mono/metadata/mono-debug.h>
  22 #include <mono/utils/mono-math.h>
  23
  24 #include "trace.h"
  25 #include "mini-amd64.h"
  26 #include "inssel.h"
  27 #include "cpu-amd64.h"
  28
  29 static gint lmf_tls_offset = -1;
  30 static gint appdomain_tls_offset = -1;
  31 static gint thread_tls_offset = -1;
  32
  33 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  34
  35 const char * const amd64_desc [OP_LAST];
  36 static const char*const * ins_spec = amd64_desc;
  37
  38 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  39
  40 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  41
  42 #ifdef PLATFORM_WIN32
  43 /* Under windows, the default pinvoke calling convention is stdcall */
  44 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  45 #else
  46 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  47 #endif
  48
  49 #define ARGS_OFFSET 16
  50 #define GP_SCRATCH_REG AMD64_R11
  51
  52 /*
  53  * AMD64 register usage:
  54  * - callee saved registers are used for global register allocation
  55  * - %r11 is used for materializing 64 bit constants in opcodes
  56  * - the rest is used for local allocation
  57  */
  58
  59 /*
  60  * Floating point comparison results:
  61  *                  ZF PF CF
  62  * A > B            0  0  0
  63  * A < B            0  0  1
  64  * A = B            1  0  0
  65  * A > B            0  0  0
  66  * UNORDERED        1  1  1
  67  */
  68
  69 #define NOT_IMPLEMENTED g_assert_not_reached ()
  70
  71 const char*
  72 mono_arch_regname (int reg) {
  73         switch (reg) {
  74         case AMD64_RAX: return "%rax";
  75         case AMD64_RBX: return "%rbx";
  76         case AMD64_RCX: return "%rcx";
  77         case AMD64_RDX: return "%rdx";
  78         case AMD64_RSP: return "%rsp";
  79         case AMD64_RBP: return "%rbp";
  80         case AMD64_RDI: return "%rdi";
  81         case AMD64_RSI: return "%rsi";
  82         case AMD64_R8: return "%r8";
  83         case AMD64_R9: return "%r9";
  84         case AMD64_R10: return "%r10";
  85         case AMD64_R11: return "%r11";
  86         case AMD64_R12: return "%r12";
  87         case AMD64_R13: return "%r13";
  88         case AMD64_R14: return "%r14";
  89         case AMD64_R15: return "%r15";
  90         }
  91         return "unknown";
  92 }
  93
  94 static const char * xmmregs [] = {
  95         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
  96         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
  97 };
  98
  99 const char*
 100 mono_arch_fregname (int reg)
 101 {
 102         if (reg < AMD64_XMM_NREG)
 103                 return xmmregs [reg];
 104         else
 105                 return "unknown";
 106 }
 107
 108 G_GNUC_UNUSED static void
 109 break_count (void)
 110 {
 111 }
 112
 113 G_GNUC_UNUSED static gboolean
 114 debug_count (void)
 115 {
 116         static int count = 0;
 117         count ++;
 118
 119         if (!getenv ("COUNT"))
 120                 return TRUE;
 121
 122         if (count == atoi (getenv ("COUNT"))) {
 123                 break_count ();
 124         }
 125
 126         if (count > atoi (getenv ("COUNT"))) {
 127                 return FALSE;
 128         }
 129
 130         return TRUE;
 131 }
 132
 133 static gboolean
 134 debug_omit_fp (void)
 135 {
 136 #if 0
 137         return debug_count ();
 138 #else
 139         return TRUE;
 140 #endif
 141 }
 142
 143 static inline void
 144 amd64_patch (unsigned char* code, gpointer target)
 145 {
 146         /* Skip REX */
 147         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 148                 code += 1;
 149
 150         if ((code [0] & 0xf8) == 0xb8) {
 151                 /* amd64_set_reg_template */
 152                 *(guint64*)(code + 1) = (guint64)target;
 153         }
 154         else if (code [0] == 0x8b) {
 155                 /* mov 0(%rip), %dreg */
 156                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 157         }
 158         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 159                 /* call *<OFFSET>(%rip) */
 160                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 161         }
 162         else if ((code [0] == 0xe8)) {
 163                 /* call <DISP> */
 164                 gint64 disp = (guint8*)target - (guint8*)code;
 165                 g_assert (amd64_is_imm32 (disp));
 166                 x86_patch (code, (unsigned char*)target);
 167         }
 168         else
 169                 x86_patch (code, (unsigned char*)target);
 170 }
 171
 172 typedef enum {
 173         ArgInIReg,
 174         ArgInFloatSSEReg,
 175         ArgInDoubleSSEReg,
 176         ArgOnStack,
 177         ArgValuetypeInReg,
 178         ArgNone /* only in pair_storage */
 179 } ArgStorage;
 180
 181 typedef struct {
 182         gint16 offset;
 183         gint8  reg;
 184         ArgStorage storage;
 185
 186         /* Only if storage == ArgValuetypeInReg */
 187         ArgStorage pair_storage [2];
 188         gint8 pair_regs [2];
 189 } ArgInfo;
 190
 191 typedef struct {
 192         int nargs;
 193         guint32 stack_usage;
 194         guint32 reg_usage;
 195         guint32 freg_usage;
 196         gboolean need_stack_align;
 197         ArgInfo ret;
 198         ArgInfo sig_cookie;
 199         ArgInfo args [1];
 200 } CallInfo;
 201
 202 #define DEBUG(a) if (cfg->verbose_level > 1) a
 203
 204 #define NEW_ICONST(cfg,dest,val) do {   \
 205                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 206                 (dest)->opcode = OP_ICONST;     \
 207                 (dest)->inst_c0 = (val);        \
 208                 (dest)->type = STACK_I4;        \
 209         } while (0)
 210
 211 #define PARAM_REGS 6
 212
 213 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 214
 215 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 216
 217 static void inline
 218 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 219 {
 220     ainfo->offset = *stack_size;
 221
 222     if (*gr >= PARAM_REGS) {
 223                 ainfo->storage = ArgOnStack;
 224                 (*stack_size) += sizeof (gpointer);
 225     }
 226     else {
 227                 ainfo->storage = ArgInIReg;
 228                 ainfo->reg = param_regs [*gr];
 229                 (*gr) ++;
 230     }
 231 }
 232
 233 #define FLOAT_PARAM_REGS 8
 234
 235 static void inline
 236 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 237 {
 238     ainfo->offset = *stack_size;
 239
 240     if (*gr >= FLOAT_PARAM_REGS) {
 241                 ainfo->storage = ArgOnStack;
 242                 (*stack_size) += sizeof (gpointer);
 243     }
 244     else {
 245                 /* A double register */
 246                 if (is_double)
 247                         ainfo->storage = ArgInDoubleSSEReg;
 248                 else
 249                         ainfo->storage = ArgInFloatSSEReg;
 250                 ainfo->reg = *gr;
 251                 (*gr) += 1;
 252     }
 253 }
 254
 255 typedef enum ArgumentClass {
 256         ARG_CLASS_NO_CLASS,
 257         ARG_CLASS_MEMORY,
 258         ARG_CLASS_INTEGER,
 259         ARG_CLASS_SSE
 260 } ArgumentClass;
 261
 262 static ArgumentClass
 263 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 264 {
 265         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 266         MonoType *ptype;
 267
 268         ptype = mono_type_get_underlying_type (type);
 269         switch (ptype->type) {
 270         case MONO_TYPE_BOOLEAN:
 271         case MONO_TYPE_CHAR:
 272         case MONO_TYPE_I1:
 273         case MONO_TYPE_U1:
 274         case MONO_TYPE_I2:
 275         case MONO_TYPE_U2:
 276         case MONO_TYPE_I4:
 277         case MONO_TYPE_U4:
 278         case MONO_TYPE_I:
 279         case MONO_TYPE_U:
 280         case MONO_TYPE_STRING:
 281         case MONO_TYPE_OBJECT:
 282         case MONO_TYPE_CLASS:
 283         case MONO_TYPE_SZARRAY:
 284         case MONO_TYPE_PTR:
 285         case MONO_TYPE_FNPTR:
 286         case MONO_TYPE_ARRAY:
 287         case MONO_TYPE_I8:
 288         case MONO_TYPE_U8:
 289                 class2 = ARG_CLASS_INTEGER;
 290                 break;
 291         case MONO_TYPE_R4:
 292         case MONO_TYPE_R8:
 293                 class2 = ARG_CLASS_SSE;
 294                 break;
 295
 296         case MONO_TYPE_TYPEDBYREF:
 297                 g_assert_not_reached ();
 298
 299         case MONO_TYPE_VALUETYPE: {
 300                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 301                 int i;
 302
 303                 for (i = 0; i < info->num_fields; ++i) {
 304                         class2 = class1;
 305                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 306                 }
 307                 break;
 308         }
 309         default:
 310                 g_assert_not_reached ();
 311         }
 312
 313         /* Merge */
 314         if (class1 == class2)
 315                 ;
 316         else if (class1 == ARG_CLASS_NO_CLASS)
 317                 class1 = class2;
 318         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 319                 class1 = ARG_CLASS_MEMORY;
 320         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 321                 class1 = ARG_CLASS_INTEGER;
 322         else
 323                 class1 = ARG_CLASS_SSE;
 324
 325         return class1;
 326 }
 327
 328 static void
 329 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 330                gboolean is_return,
 331                guint32 *gr, guint32 *fr, guint32 *stack_size)
 332 {
 333         guint32 size, quad, nquads, i;
 334         ArgumentClass args [2];
 335         MonoMarshalType *info;
 336         MonoClass *klass;
 337
 338         klass = mono_class_from_mono_type (type);
 339         if (sig->pinvoke)
 340                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 341         else
 342                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 343
 344         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 345                 /* Allways pass in memory */
 346                 ainfo->offset = *stack_size;
 347                 *stack_size += ALIGN_TO (size, 8);
 348                 ainfo->storage = ArgOnStack;
 349
 350                 return;
 351         }
 352
 353         /* FIXME: Handle structs smaller than 8 bytes */
 354         //if ((size % 8) != 0)
 355         //      NOT_IMPLEMENTED;
 356
 357         if (size > 8)
 358                 nquads = 2;
 359         else
 360                 nquads = 1;
 361
 362         /*
 363          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 364          * The X87 and SSEUP stuff is left out since there are no such types in
 365          * the CLR.
 366          */
 367         info = mono_marshal_load_type_info (klass);
 368         g_assert (info);
 369         if (info->native_size > 16) {
 370                 ainfo->offset = *stack_size;
 371                 *stack_size += ALIGN_TO (info->native_size, 8);
 372                 ainfo->storage = ArgOnStack;
 373
 374                 return;
 375         }
 376
 377         for (quad = 0; quad < nquads; ++quad) {
 378                 int size, align;
 379                 ArgumentClass class1;
 380
 381                 class1 = ARG_CLASS_NO_CLASS;
 382                 for (i = 0; i < info->num_fields; ++i) {
 383                         size = mono_marshal_type_size (info->fields [i].field->type,
 384                                                                                    info->fields [i].mspec,
 385                                                                                    &align, TRUE, klass->unicode);
 386                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 387                                 /* Unaligned field */
 388                                 NOT_IMPLEMENTED;
 389                         }
 390
 391                         /* Skip fields in other quad */
 392                         if ((quad == 0) && (info->fields [i].offset >= 8))
 393                                 continue;
 394                         if ((quad == 1) && (info->fields [i].offset < 8))
 395                                 continue;
 396
 397                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 398                 }
 399                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 400                 args [quad] = class1;
 401         }
 402
 403         /* Post merger cleanup */
 404         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 405                 args [0] = args [1] = ARG_CLASS_MEMORY;
 406
 407         /* Allocate registers */
 408         {
 409                 int orig_gr = *gr;
 410                 int orig_fr = *fr;
 411
 412                 ainfo->storage = ArgValuetypeInReg;
 413                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 414                 for (quad = 0; quad < nquads; ++quad) {
 415                         switch (args [quad]) {
 416                         case ARG_CLASS_INTEGER:
 417                                 if (*gr >= PARAM_REGS)
 418                                         args [quad] = ARG_CLASS_MEMORY;
 419                                 else {
 420                                         ainfo->pair_storage [quad] = ArgInIReg;
 421                                         if (is_return)
 422                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 423                                         else
 424                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 425                                         (*gr) ++;
 426                                 }
 427                                 break;
 428                         case ARG_CLASS_SSE:
 429                                 if (*fr >= FLOAT_PARAM_REGS)
 430                                         args [quad] = ARG_CLASS_MEMORY;
 431                                 else {
 432                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 433                                         ainfo->pair_regs [quad] = *fr;
 434                                         (*fr) ++;
 435                                 }
 436                                 break;
 437                         case ARG_CLASS_MEMORY:
 438                                 break;
 439                         default:
 440                                 g_assert_not_reached ();
 441                         }
 442                 }
 443
 444                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 445                         /* Revert possible register assignments */
 446                         *gr = orig_gr;
 447                         *fr = orig_fr;
 448
 449                         ainfo->offset = *stack_size;
 450                         *stack_size += ALIGN_TO (info->native_size, 8);
 451                         ainfo->storage = ArgOnStack;
 452                 }
 453         }
 454 }
 455
 456 /*
 457  * get_call_info:
 458  *
 459  *  Obtain information about a call according to the calling convention.
 460  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 461  * Draft Version 0.23" document for more information.
 462  */
 463 static CallInfo*
 464 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 465 {
 466         guint32 i, gr, fr;
 467         MonoType *ret_type;
 468         int n = sig->hasthis + sig->param_count;
 469         guint32 stack_size = 0;
 470         CallInfo *cinfo;
 471
 472         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 473
 474         gr = 0;
 475         fr = 0;
 476
 477         /* return value */
 478         {
 479                 ret_type = mono_type_get_underlying_type (sig->ret);
 480                 switch (ret_type->type) {
 481                 case MONO_TYPE_BOOLEAN:
 482                 case MONO_TYPE_I1:
 483                 case MONO_TYPE_U1:
 484                 case MONO_TYPE_I2:
 485                 case MONO_TYPE_U2:
 486                 case MONO_TYPE_CHAR:
 487                 case MONO_TYPE_I4:
 488                 case MONO_TYPE_U4:
 489                 case MONO_TYPE_I:
 490                 case MONO_TYPE_U:
 491                 case MONO_TYPE_PTR:
 492                 case MONO_TYPE_FNPTR:
 493                 case MONO_TYPE_CLASS:
 494                 case MONO_TYPE_OBJECT:
 495                 case MONO_TYPE_SZARRAY:
 496                 case MONO_TYPE_ARRAY:
 497                 case MONO_TYPE_STRING:
 498                         cinfo->ret.storage = ArgInIReg;
 499                         cinfo->ret.reg = AMD64_RAX;
 500                         break;
 501                 case MONO_TYPE_U8:
 502                 case MONO_TYPE_I8:
 503                         cinfo->ret.storage = ArgInIReg;
 504                         cinfo->ret.reg = AMD64_RAX;
 505                         break;
 506                 case MONO_TYPE_R4:
 507                         cinfo->ret.storage = ArgInFloatSSEReg;
 508                         cinfo->ret.reg = AMD64_XMM0;
 509                         break;
 510                 case MONO_TYPE_R8:
 511                         cinfo->ret.storage = ArgInDoubleSSEReg;
 512                         cinfo->ret.reg = AMD64_XMM0;
 513                         break;
 514                 case MONO_TYPE_VALUETYPE: {
 515                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 516
 517                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 518                         if (cinfo->ret.storage == ArgOnStack)
 519                                 /* The caller passes the address where the value is stored */
 520                                 add_general (&gr, &stack_size, &cinfo->ret);
 521                         break;
 522                 }
 523                 case MONO_TYPE_TYPEDBYREF:
 524                         /* Same as a valuetype with size 24 */
 525                         add_general (&gr, &stack_size, &cinfo->ret);
 526                         ;
 527                         break;
 528                 case MONO_TYPE_VOID:
 529                         break;
 530                 default:
 531                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 532                 }
 533         }
 534
 535         /* this */
 536         if (sig->hasthis)
 537                 add_general (&gr, &stack_size, cinfo->args + 0);
 538
 539         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 540                 gr = PARAM_REGS;
 541                 fr = FLOAT_PARAM_REGS;
 542
 543                 /* Emit the signature cookie just before the implicit arguments */
 544                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 545         }
 546
 547         for (i = 0; i < sig->param_count; ++i) {
 548                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 549                 MonoType *ptype;
 550
 551                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 552                         /* We allways pass the sig cookie on the stack for simplicity */
 553                         /*
 554                          * Prevent implicit arguments + the sig cookie from being passed
 555                          * in registers.
 556                          */
 557                         gr = PARAM_REGS;
 558                         fr = FLOAT_PARAM_REGS;
 559
 560                         /* Emit the signature cookie just before the implicit arguments */
 561                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 562                 }
 563
 564                 if (sig->params [i]->byref) {
 565                         add_general (&gr, &stack_size, ainfo);
 566                         continue;
 567                 }
 568                 ptype = mono_type_get_underlying_type (sig->params [i]);
 569                 switch (ptype->type) {
 570                 case MONO_TYPE_BOOLEAN:
 571                 case MONO_TYPE_I1:
 572                 case MONO_TYPE_U1:
 573                         add_general (&gr, &stack_size, ainfo);
 574                         break;
 575                 case MONO_TYPE_I2:
 576                 case MONO_TYPE_U2:
 577                 case MONO_TYPE_CHAR:
 578                         add_general (&gr, &stack_size, ainfo);
 579                         break;
 580                 case MONO_TYPE_I4:
 581                 case MONO_TYPE_U4:
 582                         add_general (&gr, &stack_size, ainfo);
 583                         break;
 584                 case MONO_TYPE_I:
 585                 case MONO_TYPE_U:
 586                 case MONO_TYPE_PTR:
 587                 case MONO_TYPE_FNPTR:
 588                 case MONO_TYPE_CLASS:
 589                 case MONO_TYPE_OBJECT:
 590                 case MONO_TYPE_STRING:
 591                 case MONO_TYPE_SZARRAY:
 592                 case MONO_TYPE_ARRAY:
 593                         add_general (&gr, &stack_size, ainfo);
 594                         break;
 595                 case MONO_TYPE_VALUETYPE:
 596                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 597                         break;
 598                 case MONO_TYPE_TYPEDBYREF:
 599                         stack_size += sizeof (MonoTypedRef);
 600                         ainfo->storage = ArgOnStack;
 601                         break;
 602                 case MONO_TYPE_U8:
 603                 case MONO_TYPE_I8:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_R4:
 607                         add_float (&fr, &stack_size, ainfo, FALSE);
 608                         break;
 609                 case MONO_TYPE_R8:
 610                         add_float (&fr, &stack_size, ainfo, TRUE);
 611                         break;
 612                 default:
 613                         g_assert_not_reached ();
 614                 }
 615         }
 616
 617         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 618                 gr = PARAM_REGS;
 619                 fr = FLOAT_PARAM_REGS;
 620
 621                 /* Emit the signature cookie just before the implicit arguments */
 622                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 623         }
 624
 625         if (stack_size & 0x8) {
 626                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 627                 cinfo->need_stack_align = TRUE;
 628                 stack_size += 8;
 629         }
 630
 631         cinfo->stack_usage = stack_size;
 632         cinfo->reg_usage = gr;
 633         cinfo->freg_usage = fr;
 634         return cinfo;
 635 }
 636
 637 /*
 638  * mono_arch_get_argument_info:
 639  * @csig:  a method signature
 640  * @param_count: the number of parameters to consider
 641  * @arg_info: an array to store the result infos
 642  *
 643  * Gathers information on parameters such as size, alignment and
 644  * padding. arg_info should be large enought to hold param_count + 1 entries.
 645  *
 646  * Returns the size of the argument area on the stack.
 647  */
 648 int
 649 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 650 {
 651         int k;
 652         CallInfo *cinfo = get_call_info (csig, FALSE);
 653         guint32 args_size = cinfo->stack_usage;
 654
 655         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 656         if (csig->hasthis) {
 657                 arg_info [0].offset = 0;
 658         }
 659
 660         for (k = 0; k < param_count; k++) {
 661                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 662                 /* FIXME: */
 663                 arg_info [k + 1].size = 0;
 664         }
 665
 666         g_free (cinfo);
 667
 668         return args_size;
 669 }
 670
 671 static int
 672 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 673 {
 674         return 0;
 675 }
 676
 677 /*
 678  * Initialize the cpu to execute managed code.
 679  */
 680 void
 681 mono_arch_cpu_init (void)
 682 {
 683         guint16 fpcw;
 684
 685         /* spec compliance requires running with double precision */
 686         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 687         fpcw &= ~X86_FPCW_PRECC_MASK;
 688         fpcw |= X86_FPCW_PREC_DOUBLE;
 689         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 690         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 691 }
 692
 693 /*
 694  * This function returns the optimizations supported on this cpu.
 695  */
 696 guint32
 697 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 698 {
 699         int eax, ebx, ecx, edx;
 700         guint32 opts = 0;
 701
 702         /* FIXME: AMD64 */
 703
 704         *exclude_mask = 0;
 705         /* Feature Flags function, flags returned in EDX. */
 706         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 707                 if (edx & (1 << 15)) {
 708                         opts |= MONO_OPT_CMOV;
 709                         if (edx & 1)
 710                                 opts |= MONO_OPT_FCMOV;
 711                         else
 712                                 *exclude_mask |= MONO_OPT_FCMOV;
 713                 } else
 714                         *exclude_mask |= MONO_OPT_CMOV;
 715         }
 716         return opts;
 717 }
 718
 719 gboolean
 720 mono_amd64_is_sse2 (void)
 721 {
 722         return use_sse2;
 723 }
 724
 725 static gboolean
 726 is_regsize_var (MonoType *t) {
 727         if (t->byref)
 728                 return TRUE;
 729         t = mono_type_get_underlying_type (t);
 730         switch (t->type) {
 731         case MONO_TYPE_I4:
 732         case MONO_TYPE_U4:
 733         case MONO_TYPE_I:
 734         case MONO_TYPE_U:
 735         case MONO_TYPE_PTR:
 736         case MONO_TYPE_FNPTR:
 737                 return TRUE;
 738         case MONO_TYPE_OBJECT:
 739         case MONO_TYPE_STRING:
 740         case MONO_TYPE_CLASS:
 741         case MONO_TYPE_SZARRAY:
 742         case MONO_TYPE_ARRAY:
 743                 return TRUE;
 744         case MONO_TYPE_VALUETYPE:
 745                 return FALSE;
 746         }
 747         return FALSE;
 748 }
 749
 750 GList *
 751 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 752 {
 753         GList *vars = NULL;
 754         int i;
 755
 756         for (i = 0; i < cfg->num_varinfo; i++) {
 757                 MonoInst *ins = cfg->varinfo [i];
 758                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 759
 760                 /* unused vars */
 761                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 762                         continue;
 763
 764                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 765                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 766                         continue;
 767
 768                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 769                  * 8bit quantities in caller saved registers on x86 */
 770                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 771                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 772                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 773                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 774                         g_assert (i == vmv->idx);
 775                         vars = g_list_prepend (vars, vmv);
 776                 }
 777         }
 778
 779         vars = mono_varlist_sort (cfg, vars, 0);
 780
 781         return vars;
 782 }
 783
 784 /**
 785  * mono_arch_compute_omit_fp:
 786  *
 787  *   Determine whenever the frame pointer can be eliminated.
 788  */
 789 static void
 790 mono_arch_compute_omit_fp (MonoCompile *cfg)
 791 {
 792         MonoMethodSignature *sig;
 793         MonoMethodHeader *header;
 794         int i;
 795         CallInfo *cinfo;
 796
 797         if (cfg->arch.omit_fp_computed)
 798                 return;
 799
 800         header = mono_method_get_header (cfg->method);
 801
 802         sig = mono_method_signature (cfg->method);
 803
 804         cinfo = get_call_info (sig, FALSE);
 805
 806         /*
 807          * FIXME: Remove some of the restrictions.
 808          */
 809         cfg->arch.omit_fp = TRUE;
 810         cfg->arch.omit_fp_computed = TRUE;
 811
 812         /* Temporarily disable this when running in the debugger until we have support
 813          * for this in the debugger. */
 814         if (mono_debug_using_mono_debugger ())
 815                 cfg->arch.omit_fp = FALSE;
 816
 817         if (!debug_omit_fp ())
 818                 cfg->arch.omit_fp = FALSE;
 819         /*
 820         if (cfg->method->save_lmf)
 821                 cfg->arch.omit_fp = FALSE;
 822         */
 823         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 824                 cfg->arch.omit_fp = FALSE;
 825         if (header->num_clauses)
 826                 cfg->arch.omit_fp = FALSE;
 827         if (cfg->param_area)
 828                 cfg->arch.omit_fp = FALSE;
 829         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 830                 cfg->arch.omit_fp = FALSE;
 831         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 832                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 833                 cfg->arch.omit_fp = FALSE;
 834         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 835                 ArgInfo *ainfo = &cinfo->args [i];
 836
 837                 if (ainfo->storage == ArgOnStack) {
 838                         /*
 839                          * The stack offset can only be determined when the frame
 840                          * size is known.
 841                          */
 842                         cfg->arch.omit_fp = FALSE;
 843                 }
 844         }
 845
 846         if (cfg->num_varinfo > 10000) {
 847                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 848                 cfg->arch.omit_fp = FALSE;
 849         }
 850
 851         g_free (cinfo);
 852 }
 853
 854 GList *
 855 mono_arch_get_global_int_regs (MonoCompile *cfg)
 856 {
 857         GList *regs = NULL;
 858
 859         mono_arch_compute_omit_fp (cfg);
 860
 861         if (cfg->arch.omit_fp)
 862                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 863
 864         /* We use the callee saved registers for global allocation */
 865         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 866         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 867         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 868         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 869         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 870
 871         return regs;
 872 }
 873
 874 /*
 875  * mono_arch_regalloc_cost:
 876  *
 877  *  Return the cost, in number of memory references, of the action of
 878  * allocating the variable VMV into a register during global register
 879  * allocation.
 880  */
 881 guint32
 882 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 883 {
 884         MonoInst *ins = cfg->varinfo [vmv->idx];
 885
 886         if (cfg->method->save_lmf)
 887                 /* The register is already saved */
 888                 /* substract 1 for the invisible store in the prolog */
 889                 return (ins->opcode == OP_ARG) ? 0 : 1;
 890         else
 891                 /* push+pop */
 892                 return (ins->opcode == OP_ARG) ? 1 : 2;
 893 }
 894
 895 void
 896 mono_arch_allocate_vars (MonoCompile *cfg)
 897 {
 898         MonoMethodSignature *sig;
 899         MonoMethodHeader *header;
 900         MonoInst *inst;
 901         int i, offset;
 902         guint32 locals_stack_size, locals_stack_align;
 903         gint32 *offsets;
 904         CallInfo *cinfo;
 905
 906         header = mono_method_get_header (cfg->method);
 907
 908         sig = mono_method_signature (cfg->method);
 909
 910         cinfo = get_call_info (sig, FALSE);
 911
 912         mono_arch_compute_omit_fp (cfg);
 913
 914         /*
 915          * We use the ABI calling conventions for managed code as well.
 916          * Exception: valuetypes are never passed or returned in registers.
 917          */
 918
 919         if (cfg->arch.omit_fp) {
 920                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 921                 cfg->frame_reg = AMD64_RSP;
 922                 offset = 0;
 923         } else {
 924                 /* Locals are allocated backwards from %fp */
 925                 cfg->frame_reg = AMD64_RBP;
 926                 offset = 0;
 927         }
 928
 929         cfg->arch.reg_save_area_offset = offset;
 930
 931         /* Reserve space for caller saved registers */
 932         for (i = 0; i < AMD64_NREG; ++i)
 933                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 934                         offset += sizeof (gpointer);
 935                 }
 936
 937         if (cfg->method->save_lmf) {
 938                 /* Reserve stack space for saving LMF + argument regs */
 939                 guint32 size = sizeof (MonoLMF);
 940
 941                 if (lmf_tls_offset == -1)
 942                         /* Need to save argument regs too */
 943                         size += (AMD64_NREG * 8) + (8 * 8);
 944
 945                 if (cfg->arch.omit_fp) {
 946                         cfg->arch.lmf_offset = offset;
 947                         offset += size;
 948                 }
 949                 else {
 950                         offset += size;
 951                         cfg->arch.lmf_offset = -offset;
 952                 }
 953         }
 954
 955         if (sig->ret->type != MONO_TYPE_VOID) {
 956                 switch (cinfo->ret.storage) {
 957                 case ArgInIReg:
 958                 case ArgInFloatSSEReg:
 959                 case ArgInDoubleSSEReg:
 960                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 961                                 /* The register is volatile */
 962                                 cfg->ret->opcode = OP_REGOFFSET;
 963                                 cfg->ret->inst_basereg = cfg->frame_reg;
 964                                 if (cfg->arch.omit_fp) {
 965                                         cfg->ret->inst_offset = offset;
 966                                         offset += 8;
 967                                 } else {
 968                                         offset += 8;
 969                                         cfg->ret->inst_offset = -offset;
 970                                 }
 971                         }
 972                         else {
 973                                 cfg->ret->opcode = OP_REGVAR;
 974                                 cfg->ret->inst_c0 = cinfo->ret.reg;
 975                         }
 976                         break;
 977                 case ArgValuetypeInReg:
 978                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 979                         g_assert (!cfg->arch.omit_fp);
 980                         offset += 16;
 981                         cfg->ret->opcode = OP_REGOFFSET;
 982                         cfg->ret->inst_basereg = cfg->frame_reg;
 983                         cfg->ret->inst_offset = - offset;
 984                         break;
 985                 default:
 986                         g_assert_not_reached ();
 987                 }
 988                 cfg->ret->dreg = cfg->ret->inst_c0;
 989         }
 990
 991         /* Allocate locals */
 992         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
 993         if (locals_stack_align) {
 994                 offset += (locals_stack_align - 1);
 995                 offset &= ~(locals_stack_align - 1);
 996         }
 997         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 998                 if (offsets [i] != -1) {
 999                         MonoInst *inst = cfg->varinfo [i];
1000                         inst->opcode = OP_REGOFFSET;
1001                         inst->inst_basereg = cfg->frame_reg;
1002                         if (cfg->arch.omit_fp)
1003                                 inst->inst_offset = (offset + offsets [i]);
1004                         else
1005                                 inst->inst_offset = - (offset + offsets [i]);
1006                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1007                 }
1008         }
1009         g_free (offsets);
1010         offset += locals_stack_size;
1011
1012         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1013                 g_assert (!cfg->arch.omit_fp);
1014                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1015                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1016         }
1017
1018         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1019                 inst = cfg->varinfo [i];
1020                 if (inst->opcode != OP_REGVAR) {
1021                         ArgInfo *ainfo = &cinfo->args [i];
1022                         gboolean inreg = TRUE;
1023                         MonoType *arg_type;
1024
1025                         if (sig->hasthis && (i == 0))
1026                                 arg_type = &mono_defaults.object_class->byval_arg;
1027                         else
1028                                 arg_type = sig->params [i - sig->hasthis];
1029
1030                         /* FIXME: Allocate volatile arguments to registers */
1031                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1032                                 inreg = FALSE;
1033
1034                         /*
1035                          * Under AMD64, all registers used to pass arguments to functions
1036                          * are volatile across calls.
1037                          * FIXME: Optimize this.
1038                          */
1039                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1040                                 inreg = FALSE;
1041
1042                         inst->opcode = OP_REGOFFSET;
1043
1044                         switch (ainfo->storage) {
1045                         case ArgInIReg:
1046                         case ArgInFloatSSEReg:
1047                         case ArgInDoubleSSEReg:
1048                                 inst->opcode = OP_REGVAR;
1049                                 inst->dreg = ainfo->reg;
1050                                 break;
1051                         case ArgOnStack:
1052                                 g_assert (!cfg->arch.omit_fp);
1053                                 inst->opcode = OP_REGOFFSET;
1054                                 inst->inst_basereg = cfg->frame_reg;
1055                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1056                                 break;
1057                         case ArgValuetypeInReg:
1058                                 break;
1059                         default:
1060                                 NOT_IMPLEMENTED;
1061                         }
1062
1063                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1064                                 inst->opcode = OP_REGOFFSET;
1065                                 inst->inst_basereg = cfg->frame_reg;
1066                                 /* These arguments are saved to the stack in the prolog */
1067                                 if (cfg->arch.omit_fp) {
1068                                         inst->inst_offset = offset;
1069                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1070                                 } else {
1071                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1072                                         inst->inst_offset = - offset;
1073                                 }
1074                         }
1075                 }
1076         }
1077
1078         cfg->stack_offset = offset;
1079
1080         g_free (cinfo);
1081 }
1082
1083 void
1084 mono_arch_create_vars (MonoCompile *cfg)
1085 {
1086         MonoMethodSignature *sig;
1087         CallInfo *cinfo;
1088
1089         sig = mono_method_signature (cfg->method);
1090
1091         cinfo = get_call_info (sig, FALSE);
1092
1093         if (cinfo->ret.storage == ArgValuetypeInReg)
1094                 cfg->ret_var_is_local = TRUE;
1095
1096         g_free (cinfo);
1097 }
1098
1099 static void
1100 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1101 {
1102         switch (storage) {
1103         case ArgInIReg:
1104                 arg->opcode = OP_OUTARG_REG;
1105                 arg->inst_left = tree;
1106                 arg->inst_right = (MonoInst*)call;
1107                 arg->unused = reg;
1108                 call->used_iregs |= 1 << reg;
1109                 break;
1110         case ArgInFloatSSEReg:
1111                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1112                 arg->inst_left = tree;
1113                 arg->inst_right = (MonoInst*)call;
1114                 arg->unused = reg;
1115                 call->used_fregs |= 1 << reg;
1116                 break;
1117         case ArgInDoubleSSEReg:
1118                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1119                 arg->inst_left = tree;
1120                 arg->inst_right = (MonoInst*)call;
1121                 arg->unused = reg;
1122                 call->used_fregs |= 1 << reg;
1123                 break;
1124         default:
1125                 g_assert_not_reached ();
1126         }
1127 }
1128
1129 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1130  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1131  */
1132
1133 static int
1134 arg_storage_to_ldind (ArgStorage storage)
1135 {
1136         switch (storage) {
1137         case ArgInIReg:
1138                 return CEE_LDIND_I;
1139         case ArgInDoubleSSEReg:
1140                 return CEE_LDIND_R8;
1141         case ArgInFloatSSEReg:
1142                 return CEE_LDIND_R4;
1143         default:
1144                 g_assert_not_reached ();
1145         }
1146
1147         return -1;
1148 }
1149
1150 /*
1151  * take the arguments and generate the arch-specific
1152  * instructions to properly call the function in call.
1153  * This includes pushing, moving arguments to the right register
1154  * etc.
1155  * Issue: who does the spilling if needed, and when?
1156  */
1157 MonoCallInst*
1158 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1159         MonoInst *arg, *in;
1160         MonoMethodSignature *sig;
1161         int i, n, stack_size;
1162         CallInfo *cinfo;
1163         ArgInfo *ainfo;
1164
1165         stack_size = 0;
1166
1167         sig = call->signature;
1168         n = sig->param_count + sig->hasthis;
1169
1170         cinfo = get_call_info (sig, sig->pinvoke);
1171
1172         for (i = 0; i < n; ++i) {
1173                 ainfo = cinfo->args + i;
1174
1175                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1176                         MonoMethodSignature *tmp_sig;
1177
1178                         /* Emit the signature cookie just before the implicit arguments */
1179                         MonoInst *sig_arg;
1180                         /* FIXME: Add support for signature tokens to AOT */
1181                         cfg->disable_aot = TRUE;
1182
1183                         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1184
1185                         /*
1186                          * mono_ArgIterator_Setup assumes the signature cookie is
1187                          * passed first and all the arguments which were before it are
1188                          * passed on the stack after the signature. So compensate by
1189                          * passing a different signature.
1190                          */
1191                         tmp_sig = mono_metadata_signature_dup (call->signature);
1192                         tmp_sig->param_count -= call->signature->sentinelpos;
1193                         tmp_sig->sentinelpos = 0;
1194                         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1195
1196                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1197                         sig_arg->inst_p0 = tmp_sig;
1198
1199                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1200                         arg->inst_left = sig_arg;
1201                         arg->type = STACK_PTR;
1202
1203                         /* prepend, so they get reversed */
1204                         arg->next = call->out_args;
1205                         call->out_args = arg;
1206                 }
1207
1208                 if (is_virtual && i == 0) {
1209                         /* the argument will be attached to the call instruction */
1210                         in = call->args [i];
1211                 } else {
1212                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1213                         in = call->args [i];
1214                         arg->cil_code = in->cil_code;
1215                         arg->inst_left = in;
1216                         arg->type = in->type;
1217                         /* prepend, so they get reversed */
1218                         arg->next = call->out_args;
1219                         call->out_args = arg;
1220
1221                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1222                                 gint align;
1223                                 guint32 size;
1224
1225                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1226                                         size = sizeof (MonoTypedRef);
1227                                         align = sizeof (gpointer);
1228                                 }
1229                                 else
1230                                 if (sig->pinvoke)
1231                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1232                                 else {
1233                                         /*
1234                                          * Other backends use mono_type_stack_size (), but that
1235                                          * aligns the size to 8, which is larger than the size of
1236                                          * the source, leading to reads of invalid memory if the
1237                                          * source is at the end of address space.
1238                                          */
1239                                         size = mono_class_value_size (in->klass, &align);
1240                                 }
1241                                 if (ainfo->storage == ArgValuetypeInReg) {
1242                                         if (ainfo->pair_storage [1] == ArgNone) {
1243                                                 MonoInst *load;
1244
1245                                                 /* Simpler case */
1246
1247                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1248                                                 load->inst_left = in;
1249
1250                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1251                                         }
1252                                         else {
1253                                                 /* Trees can't be shared so make a copy */
1254                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1255                                                 MonoInst *load, *load2, *offset_ins;
1256
1257                                                 /* Reg1 */
1258                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1259                                                 load->ssa_op = MONO_SSA_LOAD;
1260                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1261
1262                                                 NEW_ICONST (cfg, offset_ins, 0);
1263                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1264                                                 load2->inst_left = load;
1265                                                 load2->inst_right = offset_ins;
1266
1267                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1268                                                 load->inst_left = load2;
1269
1270                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1271
1272                                                 /* Reg2 */
1273                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1274                                                 load->ssa_op = MONO_SSA_LOAD;
1275                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1276
1277                                                 NEW_ICONST (cfg, offset_ins, 8);
1278                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1279                                                 load2->inst_left = load;
1280                                                 load2->inst_right = offset_ins;
1281
1282                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1283                                                 load->inst_left = load2;
1284
1285                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1286                                                 arg->cil_code = in->cil_code;
1287                                                 arg->type = in->type;
1288                                                 /* prepend, so they get reversed */
1289                                                 arg->next = call->out_args;
1290                                                 call->out_args = arg;
1291
1292                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1293
1294                                                 /* Prepend a copy inst */
1295                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1296                                                 arg->cil_code = in->cil_code;
1297                                                 arg->ssa_op = MONO_SSA_STORE;
1298                                                 arg->inst_left = vtaddr;
1299                                                 arg->inst_right = in;
1300                                                 arg->type = in->type;
1301
1302                                                 /* prepend, so they get reversed */
1303                                                 arg->next = call->out_args;
1304                                                 call->out_args = arg;
1305                                         }
1306                                 }
1307                                 else {
1308                                         arg->opcode = OP_OUTARG_VT;
1309                                         arg->klass = in->klass;
1310                                         arg->unused = sig->pinvoke;
1311                                         arg->inst_imm = size;
1312                                 }
1313                         }
1314                         else {
1315                                 switch (ainfo->storage) {
1316                                 case ArgInIReg:
1317                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1318                                         break;
1319                                 case ArgInFloatSSEReg:
1320                                 case ArgInDoubleSSEReg:
1321                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1322                                         break;
1323                                 case ArgOnStack:
1324                                         arg->opcode = OP_OUTARG;
1325                                         if (!sig->params [i - sig->hasthis]->byref) {
1326                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1327                                                         arg->opcode = OP_OUTARG_R4;
1328                                                 else
1329                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1330                                                                 arg->opcode = OP_OUTARG_R8;
1331                                         }
1332                                         break;
1333                                 default:
1334                                         g_assert_not_reached ();
1335                                 }
1336                         }
1337                 }
1338         }
1339
1340         if (cinfo->need_stack_align) {
1341                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1342                 /* prepend, so they get reversed */
1343                 arg->next = call->out_args;
1344                 call->out_args = arg;
1345         }
1346
1347         call->stack_usage = cinfo->stack_usage;
1348         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1349         cfg->flags |= MONO_CFG_HAS_CALLS;
1350
1351         g_free (cinfo);
1352
1353         return call;
1354 }
1355
1356 #define EMIT_COND_BRANCH(ins,cond,sign) \
1357 if (ins->flags & MONO_INST_BRLABEL) { \
1358         if (ins->inst_i0->inst_c0) { \
1359                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1360         } else { \
1361                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1362                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1363                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1364                         x86_branch8 (code, cond, 0, sign); \
1365                 else \
1366                         x86_branch32 (code, cond, 0, sign); \
1367         } \
1368 } else { \
1369         if (ins->inst_true_bb->native_offset) { \
1370                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1371         } else { \
1372                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1373                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1374                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1375                         x86_branch8 (code, cond, 0, sign); \
1376                 else \
1377                         x86_branch32 (code, cond, 0, sign); \
1378         } \
1379 }
1380
1381 /* emit an exception if condition is fail */
1382 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1383         do {                                                        \
1384                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1385                 if (tins == NULL) {                                                                             \
1386                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1387                                         MONO_PATCH_INFO_EXC, exc_name);  \
1388                         x86_branch32 (code, cond, 0, signed);               \
1389                 } else {        \
1390                         EMIT_COND_BRANCH (tins, cond, signed);  \
1391                 }                       \
1392         } while (0);
1393
1394 #define EMIT_FPCOMPARE(code) do { \
1395         amd64_fcompp (code); \
1396         amd64_fnstsw (code); \
1397 } while (0);
1398
1399 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1400     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1401         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1402         amd64_ ##op (code); \
1403         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1404         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1405 } while (0);
1406
1407 static guint8*
1408 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1409 {
1410         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1411
1412         if (cfg->compile_aot) {
1413                 amd64_call_membase (code, AMD64_RIP, 0);
1414         }
1415         else {
1416                 gboolean near_call = FALSE;
1417
1418                 /*
1419                  * Indirect calls are expensive so try to make a near call if possible.
1420                  * The caller memory is allocated by the code manager so it is
1421                  * guaranteed to be at a 32 bit offset.
1422                  */
1423
1424                 if (patch_type != MONO_PATCH_INFO_ABS) {
1425                         /* The target is in memory allocated using the code manager */
1426                         near_call = TRUE;
1427
1428                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1429                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1430                                         /* The callee might be an AOT method */
1431                                         near_call = FALSE;
1432                         }
1433
1434                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1435                                 /*
1436                                  * The call might go directly to a native function without
1437                                  * the wrapper.
1438                                  */
1439                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1440                                 if (mi) {
1441                                         gconstpointer target = mono_icall_get_wrapper (mi);
1442                                         if ((((guint64)target) >> 32) != 0)
1443                                                 near_call = FALSE;
1444                                 }
1445                         }
1446                 }
1447                 else {
1448                         if (mono_find_class_init_trampoline_by_addr (data))
1449                                 near_call = TRUE;
1450                         else {
1451                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1452                                 if (info) {
1453                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1454                                                 strstr (cfg->method->name, info->name)) {
1455                                                 /* A call to the wrapped function */
1456                                                 if ((((guint64)data) >> 32) == 0)
1457                                                         near_call = TRUE;
1458                                         }
1459                                         else if (info->func == info->wrapper) {
1460                                                 /* No wrapper */
1461                                                 if ((((guint64)info->func) >> 32) == 0)
1462                                                         near_call = TRUE;
1463                                         }
1464                                         else
1465                                                 near_call = TRUE;
1466                                 }
1467                                 else if ((((guint64)data) >> 32) == 0)
1468                                         near_call = TRUE;
1469                         }
1470                 }
1471
1472                 if (cfg->method->dynamic)
1473                         /* These methods are allocated using malloc */
1474                         near_call = FALSE;
1475
1476                 if (near_call) {
1477                         amd64_call_code (code, 0);
1478                 }
1479                 else {
1480                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1481                         amd64_call_reg (code, GP_SCRATCH_REG);
1482                 }
1483         }
1484
1485         return code;
1486 }
1487
1488 /* FIXME: Add more instructions */
1489 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1490
1491 static void
1492 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1493 {
1494         MonoInst *ins, *last_ins = NULL;
1495         ins = bb->code;
1496
1497         while (ins) {
1498
1499                 switch (ins->opcode) {
1500                 case OP_ICONST:
1501                 case OP_I8CONST:
1502                         /* reg = 0 -> XOR (reg, reg) */
1503                         /* XOR sets cflags on x86, so we cant do it always */
1504                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1505                                 ins->opcode = CEE_XOR;
1506                                 ins->sreg1 = ins->dreg;
1507                                 ins->sreg2 = ins->dreg;
1508                         }
1509                         break;
1510                 case OP_MUL_IMM:
1511                         /* remove unnecessary multiplication with 1 */
1512                         if (ins->inst_imm == 1) {
1513                                 if (ins->dreg != ins->sreg1) {
1514                                         ins->opcode = OP_MOVE;
1515                                 } else {
1516                                         last_ins->next = ins->next;
1517                                         ins = ins->next;
1518                                         continue;
1519                                 }
1520                         }
1521                         break;
1522                 case OP_COMPARE_IMM:
1523                         /* OP_COMPARE_IMM (reg, 0)
1524                          * -->
1525                          * OP_AMD64_TEST_NULL (reg)
1526                          */
1527                         if (!ins->inst_imm)
1528                                 ins->opcode = OP_AMD64_TEST_NULL;
1529                         break;
1530                 case OP_ICOMPARE_IMM:
1531                         if (!ins->inst_imm)
1532                                 ins->opcode = OP_X86_TEST_NULL;
1533                         break;
1534                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1535                         /*
1536                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1537                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1538                          * -->
1539                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1540                          * OP_COMPARE_IMM reg, imm
1541                          *
1542                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1543                          */
1544                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1545                             ins->inst_basereg == last_ins->inst_destbasereg &&
1546                             ins->inst_offset == last_ins->inst_offset) {
1547                                         ins->opcode = OP_ICOMPARE_IMM;
1548                                         ins->sreg1 = last_ins->sreg1;
1549
1550                                         /* check if we can remove cmp reg,0 with test null */
1551                                         if (!ins->inst_imm)
1552                                                 ins->opcode = OP_X86_TEST_NULL;
1553                                 }
1554
1555                         break;
1556                 case OP_LOAD_MEMBASE:
1557                 case OP_LOADI4_MEMBASE:
1558                         /*
1559                          * Note: if reg1 = reg2 the load op is removed
1560                          *
1561                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1562                          * OP_LOAD_MEMBASE offset(basereg), reg2
1563                          * -->
1564                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1565                          * OP_MOVE reg1, reg2
1566                          */
1567                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1568                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1569                             ins->inst_basereg == last_ins->inst_destbasereg &&
1570                             ins->inst_offset == last_ins->inst_offset) {
1571                                 if (ins->dreg == last_ins->sreg1) {
1572                                         last_ins->next = ins->next;
1573                                         ins = ins->next;
1574                                         continue;
1575                                 } else {
1576                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1577                                         ins->opcode = OP_MOVE;
1578                                         ins->sreg1 = last_ins->sreg1;
1579                                 }
1580
1581                         /*
1582                          * Note: reg1 must be different from the basereg in the second load
1583                          * Note: if reg1 = reg2 is equal then second load is removed
1584                          *
1585                          * OP_LOAD_MEMBASE offset(basereg), reg1
1586                          * OP_LOAD_MEMBASE offset(basereg), reg2
1587                          * -->
1588                          * OP_LOAD_MEMBASE offset(basereg), reg1
1589                          * OP_MOVE reg1, reg2
1590                          */
1591                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1592                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1593                               ins->inst_basereg != last_ins->dreg &&
1594                               ins->inst_basereg == last_ins->inst_basereg &&
1595                               ins->inst_offset == last_ins->inst_offset) {
1596
1597                                 if (ins->dreg == last_ins->dreg) {
1598                                         last_ins->next = ins->next;
1599                                         ins = ins->next;
1600                                         continue;
1601                                 } else {
1602                                         ins->opcode = OP_MOVE;
1603                                         ins->sreg1 = last_ins->dreg;
1604                                 }
1605
1606                                 //g_assert_not_reached ();
1607
1608 #if 0
1609                         /*
1610                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1611                          * OP_LOAD_MEMBASE offset(basereg), reg
1612                          * -->
1613                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1614                          * OP_ICONST reg, imm
1615                          */
1616                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1617                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1618                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1619                                    ins->inst_offset == last_ins->inst_offset) {
1620                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1621                                 ins->opcode = OP_ICONST;
1622                                 ins->inst_c0 = last_ins->inst_imm;
1623                                 g_assert_not_reached (); // check this rule
1624 #endif
1625                         }
1626                         break;
1627                 case OP_LOADU1_MEMBASE:
1628                 case OP_LOADI1_MEMBASE:
1629                         /*
1630                          * Note: if reg1 = reg2 the load op is removed
1631                          *
1632                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1633                          * OP_LOAD_MEMBASE offset(basereg), reg2
1634                          * -->
1635                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1636                          * OP_MOVE reg1, reg2
1637                          */
1638                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1639                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1640                                         ins->inst_offset == last_ins->inst_offset) {
1641                                 if (ins->dreg == last_ins->sreg1) {
1642                                         last_ins->next = ins->next;
1643                                         ins = ins->next;
1644                                         continue;
1645                                 } else {
1646                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1647                                         ins->opcode = OP_MOVE;
1648                                         ins->sreg1 = last_ins->sreg1;
1649                                 }
1650                         }
1651                         break;
1652                 case OP_LOADU2_MEMBASE:
1653                 case OP_LOADI2_MEMBASE:
1654                         /*
1655                          * Note: if reg1 = reg2 the load op is removed
1656                          *
1657                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1658                          * OP_LOAD_MEMBASE offset(basereg), reg2
1659                          * -->
1660                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1661                          * OP_MOVE reg1, reg2
1662                          */
1663                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1664                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1665                                         ins->inst_offset == last_ins->inst_offset) {
1666                                 if (ins->dreg == last_ins->sreg1) {
1667                                         last_ins->next = ins->next;
1668                                         ins = ins->next;
1669                                         continue;
1670                                 } else {
1671                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1672                                         ins->opcode = OP_MOVE;
1673                                         ins->sreg1 = last_ins->sreg1;
1674                                 }
1675                         }
1676                         break;
1677                 case CEE_CONV_I4:
1678                 case CEE_CONV_U4:
1679                 case OP_MOVE:
1680                         /*
1681                          * Removes:
1682                          *
1683                          * OP_MOVE reg, reg
1684                          */
1685                         if (ins->dreg == ins->sreg1) {
1686                                 if (last_ins)
1687                                         last_ins->next = ins->next;
1688                                 ins = ins->next;
1689                                 continue;
1690                         }
1691                         /*
1692                          * Removes:
1693                          *
1694                          * OP_MOVE sreg, dreg
1695                          * OP_MOVE dreg, sreg
1696                          */
1697                         if (last_ins && last_ins->opcode == OP_MOVE &&
1698                             ins->sreg1 == last_ins->dreg &&
1699                             ins->dreg == last_ins->sreg1) {
1700                                 last_ins->next = ins->next;
1701                                 ins = ins->next;
1702                                 continue;
1703                         }
1704                         break;
1705                 }
1706                 last_ins = ins;
1707                 ins = ins->next;
1708         }
1709         bb->last_ins = last_ins;
1710 }
1711
1712 static void
1713 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1714 {
1715         if (ins == NULL) {
1716                 ins = bb->code;
1717                 bb->code = to_insert;
1718                 to_insert->next = ins;
1719         }
1720         else {
1721                 to_insert->next = ins->next;
1722                 ins->next = to_insert;
1723         }
1724 }
1725
1726 #define NEW_INS(cfg,dest,op) do {       \
1727                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1728                 (dest)->opcode = (op);  \
1729         insert_after_ins (bb, last_ins, (dest)); \
1730         } while (0)
1731
1732 /*
1733  * mono_arch_lowering_pass:
1734  *
1735  *  Converts complex opcodes into simpler ones so that each IR instruction
1736  * corresponds to one machine instruction.
1737  */
1738 static void
1739 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1740 {
1741         MonoInst *ins, *temp, *last_ins = NULL;
1742         ins = bb->code;
1743
1744         if (bb->max_ireg > cfg->rs->next_vireg)
1745                 cfg->rs->next_vireg = bb->max_ireg;
1746         if (bb->max_freg > cfg->rs->next_vfreg)
1747                 cfg->rs->next_vfreg = bb->max_freg;
1748
1749         /*
1750          * FIXME: Need to add more instructions, but the current machine
1751          * description can't model some parts of the composite instructions like
1752          * cdq.
1753          */
1754         while (ins) {
1755                 switch (ins->opcode) {
1756                 case OP_DIV_IMM:
1757                 case OP_REM_IMM:
1758                 case OP_IDIV_IMM:
1759                 case OP_IREM_IMM:
1760                         NEW_INS (cfg, temp, OP_ICONST);
1761                         temp->inst_c0 = ins->inst_imm;
1762                         temp->dreg = mono_regstate_next_int (cfg->rs);
1763                         switch (ins->opcode) {
1764                         case OP_DIV_IMM:
1765                                 ins->opcode = OP_LDIV;
1766                                 break;
1767                         case OP_REM_IMM:
1768                                 ins->opcode = OP_LREM;
1769                                 break;
1770                         case OP_IDIV_IMM:
1771                                 ins->opcode = OP_IDIV;
1772                                 break;
1773                         case OP_IREM_IMM:
1774                                 ins->opcode = OP_IREM;
1775                                 break;
1776                         }
1777                         ins->sreg2 = temp->dreg;
1778                         break;
1779                 case OP_COMPARE_IMM:
1780                         if (!amd64_is_imm32 (ins->inst_imm)) {
1781                                 NEW_INS (cfg, temp, OP_I8CONST);
1782                                 temp->inst_c0 = ins->inst_imm;
1783                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1784                                 ins->opcode = OP_COMPARE;
1785                                 ins->sreg2 = temp->dreg;
1786                         }
1787                         break;
1788                 case OP_LOAD_MEMBASE:
1789                 case OP_LOADI8_MEMBASE:
1790                         if (!amd64_is_imm32 (ins->inst_offset)) {
1791                                 NEW_INS (cfg, temp, OP_I8CONST);
1792                                 temp->inst_c0 = ins->inst_offset;
1793                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1794                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1795                                 ins->inst_indexreg = temp->dreg;
1796                         }
1797                         break;
1798                 case OP_STORE_MEMBASE_IMM:
1799                 case OP_STOREI8_MEMBASE_IMM:
1800                         if (!amd64_is_imm32 (ins->inst_imm)) {
1801                                 NEW_INS (cfg, temp, OP_I8CONST);
1802                                 temp->inst_c0 = ins->inst_imm;
1803                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1804                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1805                                 ins->sreg1 = temp->dreg;
1806                         }
1807                         break;
1808                 default:
1809                         break;
1810                 }
1811                 last_ins = ins;
1812                 ins = ins->next;
1813         }
1814         bb->last_ins = last_ins;
1815
1816         bb->max_ireg = cfg->rs->next_vireg;
1817         bb->max_freg = cfg->rs->next_vfreg;
1818 }
1819
1820 static const int
1821 branch_cc_table [] = {
1822         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1823         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1824         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1825 };
1826
1827 static int
1828 opcode_to_x86_cond (int opcode)
1829 {
1830         switch (opcode) {
1831         case OP_IBEQ:
1832                 return X86_CC_EQ;
1833         case OP_IBNE_UN:
1834                 return X86_CC_NE;
1835         case OP_IBLT:
1836                 return X86_CC_LT;
1837         case OP_IBLT_UN:
1838                 return X86_CC_LT;
1839         case OP_IBGT:
1840                 return X86_CC_GT;
1841         case OP_IBGT_UN:
1842                 return X86_CC_GT;
1843         case OP_IBGE:
1844                 return X86_CC_GE;
1845         case OP_IBGE_UN:
1846                 return X86_CC_GE;
1847         case OP_IBLE:
1848                 return X86_CC_LE;
1849         case OP_IBLE_UN:
1850                 return X86_CC_LE;
1851         case OP_COND_EXC_IOV:
1852                 return X86_CC_O;
1853         case OP_COND_EXC_IC:
1854                 return X86_CC_C;
1855         default:
1856                 g_assert_not_reached ();
1857         }
1858
1859         return -1;
1860 }
1861
1862 /*#include "cprop.c"*/
1863
1864 /*
1865  * Local register allocation.
1866  * We first scan the list of instructions and we save the liveness info of
1867  * each register (when the register is first used, when it's value is set etc.).
1868  * We also reverse the list of instructions (in the InstList list) because assigning
1869  * registers backwards allows for more tricks to be used.
1870  */
1871 void
1872 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1873 {
1874         if (!bb->code)
1875                 return;
1876
1877         mono_arch_lowering_pass (cfg, bb);
1878
1879         mono_local_regalloc (cfg, bb);
1880 }
1881
1882 static unsigned char*
1883 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1884 {
1885         if (use_sse2) {
1886                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1887         }
1888         else {
1889                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1890                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1891                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1892                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1893                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1894                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1895                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1896                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1897                 amd64_pop_reg (code, dreg);
1898                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1899                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1900         }
1901
1902         if (size == 1)
1903                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1904         else if (size == 2)
1905                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1906         return code;
1907 }
1908
1909 static unsigned char*
1910 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1911 {
1912         int sreg = tree->sreg1;
1913         int need_touch = FALSE;
1914
1915 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1916         if (!tree->flags & MONO_INST_INIT)
1917                 need_touch = TRUE;
1918 #endif
1919
1920         if (need_touch) {
1921                 guint8* br[5];
1922
1923                 /*
1924                  * Under Windows:
1925                  * If requested stack size is larger than one page,
1926                  * perform stack-touch operation
1927                  */
1928                 /*
1929                  * Generate stack probe code.
1930                  * Under Windows, it is necessary to allocate one page at a time,
1931                  * "touching" stack after each successful sub-allocation. This is
1932                  * because of the way stack growth is implemented - there is a
1933                  * guard page before the lowest stack page that is currently commited.
1934                  * Stack normally grows sequentially so OS traps access to the
1935                  * guard page and commits more pages when needed.
1936                  */
1937                 amd64_test_reg_imm (code, sreg, ~0xFFF);
1938                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1939
1940                 br[2] = code; /* loop */
1941                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
1942                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
1943                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1944                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1945                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1946                 amd64_patch (br[3], br[2]);
1947                 amd64_test_reg_reg (code, sreg, sreg);
1948                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1949                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1950
1951                 br[1] = code; x86_jump8 (code, 0);
1952
1953                 amd64_patch (br[0], code);
1954                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1955                 amd64_patch (br[1], code);
1956                 amd64_patch (br[4], code);
1957         }
1958         else
1959                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
1960
1961         if (tree->flags & MONO_INST_INIT) {
1962                 int offset = 0;
1963                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
1964                         amd64_push_reg (code, AMD64_RAX);
1965                         offset += 8;
1966                 }
1967                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
1968                         amd64_push_reg (code, AMD64_RCX);
1969                         offset += 8;
1970                 }
1971                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
1972                         amd64_push_reg (code, AMD64_RDI);
1973                         offset += 8;
1974                 }
1975
1976                 amd64_shift_reg_imm (code, X86_SHR, sreg, 4);
1977                 if (sreg != AMD64_RCX)
1978                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
1979                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
1980
1981                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
1982                 amd64_cld (code);
1983                 amd64_prefix (code, X86_REP_PREFIX);
1984                 amd64_stosl (code);
1985
1986                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
1987                         amd64_pop_reg (code, AMD64_RDI);
1988                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
1989                         amd64_pop_reg (code, AMD64_RCX);
1990                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
1991                         amd64_pop_reg (code, AMD64_RAX);
1992         }
1993         return code;
1994 }
1995
1996 static guint8*
1997 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1998 {
1999         CallInfo *cinfo;
2000         guint32 quad;
2001
2002         /* Move return value to the target register */
2003         /* FIXME: do this in the local reg allocator */
2004         switch (ins->opcode) {
2005         case CEE_CALL:
2006         case OP_CALL_REG:
2007         case OP_CALL_MEMBASE:
2008         case OP_LCALL:
2009         case OP_LCALL_REG:
2010         case OP_LCALL_MEMBASE:
2011                 g_assert (ins->dreg == AMD64_RAX);
2012                 break;
2013         case OP_FCALL:
2014         case OP_FCALL_REG:
2015         case OP_FCALL_MEMBASE:
2016                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2017                         if (use_sse2)
2018                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2019                         else {
2020                                 /* FIXME: optimize this */
2021                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2022                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2023                         }
2024                 }
2025                 else {
2026                         if (use_sse2) {
2027                                 if (ins->dreg != AMD64_XMM0)
2028                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2029                         }
2030                         else {
2031                                 /* FIXME: optimize this */
2032                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2033                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2034                         }
2035                 }
2036                 break;
2037         case OP_VCALL:
2038         case OP_VCALL_REG:
2039         case OP_VCALL_MEMBASE:
2040                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2041                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2042                         /* Pop the destination address from the stack */
2043                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2044                         amd64_pop_reg (code, AMD64_RCX);
2045
2046                         for (quad = 0; quad < 2; quad ++) {
2047                                 switch (cinfo->ret.pair_storage [quad]) {
2048                                 case ArgInIReg:
2049                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2050                                         break;
2051                                 case ArgInFloatSSEReg:
2052                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2053                                         break;
2054                                 case ArgInDoubleSSEReg:
2055                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2056                                         break;
2057                                 case ArgNone:
2058                                         break;
2059                                 default:
2060                                         NOT_IMPLEMENTED;
2061                                 }
2062                         }
2063                 }
2064                 g_free (cinfo);
2065                 break;
2066         }
2067
2068         return code;
2069 }
2070
2071 /*
2072  * emit_load_volatile_arguments:
2073  *
2074  *  Load volatile arguments from the stack to the original input registers.
2075  * Required before a tail call.
2076  */
2077 static guint8*
2078 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2079 {
2080         MonoMethod *method = cfg->method;
2081         MonoMethodSignature *sig;
2082         MonoInst *inst;
2083         CallInfo *cinfo;
2084         guint32 i;
2085
2086         /* FIXME: Generate intermediate code instead */
2087
2088         sig = mono_method_signature (method);
2089
2090         cinfo = get_call_info (sig, FALSE);
2091
2092         /* This is the opposite of the code in emit_prolog */
2093
2094         if (sig->ret->type != MONO_TYPE_VOID) {
2095                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2096                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2097                 }
2098         }
2099
2100         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2101                 ArgInfo *ainfo = cinfo->args + i;
2102                 MonoType *arg_type;
2103                 inst = cfg->varinfo [i];
2104
2105                 if (sig->hasthis && (i == 0))
2106                         arg_type = &mono_defaults.object_class->byval_arg;
2107                 else
2108                         arg_type = sig->params [i - sig->hasthis];
2109
2110                 if (inst->opcode != OP_REGVAR) {
2111                         switch (ainfo->storage) {
2112                         case ArgInIReg: {
2113                                 guint32 size = 8;
2114
2115                                 /* FIXME: I1 etc */
2116                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2117                                 break;
2118                         }
2119                         case ArgInFloatSSEReg:
2120                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2121                                 break;
2122                         case ArgInDoubleSSEReg:
2123                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2124                                 break;
2125                         default:
2126                                 break;
2127                         }
2128                 }
2129                 else {
2130                         g_assert (ainfo->storage == ArgInIReg);
2131
2132                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2133                 }
2134         }
2135
2136         g_free (cinfo);
2137
2138         return code;
2139 }
2140
2141 #define REAL_PRINT_REG(text,reg) \
2142 mono_assert (reg >= 0); \
2143 amd64_push_reg (code, AMD64_RAX); \
2144 amd64_push_reg (code, AMD64_RDX); \
2145 amd64_push_reg (code, AMD64_RCX); \
2146 amd64_push_reg (code, reg); \
2147 amd64_push_imm (code, reg); \
2148 amd64_push_imm (code, text " %d %p\n"); \
2149 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2150 amd64_call_reg (code, AMD64_RAX); \
2151 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2152 amd64_pop_reg (code, AMD64_RCX); \
2153 amd64_pop_reg (code, AMD64_RDX); \
2154 amd64_pop_reg (code, AMD64_RAX);
2155
2156 /* benchmark and set based on cpu */
2157 #define LOOP_ALIGNMENT 8
2158 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2159
2160 void
2161 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2162 {
2163         MonoInst *ins;
2164         MonoCallInst *call;
2165         guint offset;
2166         guint8 *code = cfg->native_code + cfg->code_len;
2167         MonoInst *last_ins = NULL;
2168         guint last_offset = 0;
2169         int max_len, cpos;
2170
2171         if (cfg->opt & MONO_OPT_PEEPHOLE)
2172                 peephole_pass (cfg, bb);
2173
2174         if (cfg->opt & MONO_OPT_LOOP) {
2175                 int pad, align = LOOP_ALIGNMENT;
2176                 /* set alignment depending on cpu */
2177                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2178                         pad = align - pad;
2179                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2180                         amd64_padding (code, pad);
2181                         cfg->code_len += pad;
2182                         bb->native_offset = cfg->code_len;
2183                 }
2184         }
2185
2186         if (cfg->verbose_level > 2)
2187                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2188
2189         cpos = bb->max_offset;
2190
2191         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2192                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2193                 g_assert (!cfg->compile_aot);
2194                 cpos += 6;
2195
2196                 cov->data [bb->dfn].cil_code = bb->cil_code;
2197                 /* this is not thread save, but good enough */
2198                 amd64_inc_mem (code, (guint64)&cov->data [bb->dfn].count);
2199         }
2200
2201         offset = code - cfg->native_code;
2202
2203         ins = bb->code;
2204         while (ins) {
2205                 offset = code - cfg->native_code;
2206
2207                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2208
2209                 if (offset > (cfg->code_size - max_len - 16)) {
2210                         cfg->code_size *= 2;
2211                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2212                         code = cfg->native_code + offset;
2213                         mono_jit_stats.code_reallocs++;
2214                 }
2215
2216                 mono_debug_record_line_number (cfg, ins, offset);
2217
2218                 switch (ins->opcode) {
2219                 case OP_BIGMUL:
2220                         amd64_mul_reg (code, ins->sreg2, TRUE);
2221                         break;
2222                 case OP_BIGMUL_UN:
2223                         amd64_mul_reg (code, ins->sreg2, FALSE);
2224                         break;
2225                 case OP_X86_SETEQ_MEMBASE:
2226                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2227                         break;
2228                 case OP_STOREI1_MEMBASE_IMM:
2229                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2230                         break;
2231                 case OP_STOREI2_MEMBASE_IMM:
2232                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2233                         break;
2234                 case OP_STOREI4_MEMBASE_IMM:
2235                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2236                         break;
2237                 case OP_STOREI1_MEMBASE_REG:
2238                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2239                         break;
2240                 case OP_STOREI2_MEMBASE_REG:
2241                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2242                         break;
2243                 case OP_STORE_MEMBASE_REG:
2244                 case OP_STOREI8_MEMBASE_REG:
2245                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2246                         break;
2247                 case OP_STOREI4_MEMBASE_REG:
2248                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2249                         break;
2250                 case OP_STORE_MEMBASE_IMM:
2251                 case OP_STOREI8_MEMBASE_IMM:
2252                         g_assert (amd64_is_imm32 (ins->inst_imm));
2253                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2254                         break;
2255                 case CEE_LDIND_I:
2256                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2257                         break;
2258                 case CEE_LDIND_I4:
2259                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2260                         break;
2261                 case CEE_LDIND_U4:
2262                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2263                         break;
2264                 case OP_LOADU4_MEM:
2265                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2266                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2267                         break;
2268                 case OP_LOAD_MEMBASE:
2269                 case OP_LOADI8_MEMBASE:
2270                         g_assert (amd64_is_imm32 (ins->inst_offset));
2271                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2272                         break;
2273                 case OP_LOADI4_MEMBASE:
2274                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2275                         break;
2276                 case OP_LOADU4_MEMBASE:
2277                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2278                         break;
2279                 case OP_LOADU1_MEMBASE:
2280                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2281                         break;
2282                 case OP_LOADI1_MEMBASE:
2283                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2284                         break;
2285                 case OP_LOADU2_MEMBASE:
2286                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2287                         break;
2288                 case OP_LOADI2_MEMBASE:
2289                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2290                         break;
2291                 case OP_AMD64_LOADI8_MEMINDEX:
2292                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2293                         break;
2294                 case CEE_CONV_I1:
2295                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2296                         break;
2297                 case CEE_CONV_I2:
2298                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2299                         break;
2300                 case CEE_CONV_U1:
2301                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2302                         break;
2303                 case CEE_CONV_U2:
2304                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2305                         break;
2306                 case CEE_CONV_U8:
2307                 case CEE_CONV_U:
2308                         /* Clean out the upper word */
2309                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2310                         break;
2311                 case CEE_CONV_I8:
2312                 case CEE_CONV_I:
2313                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2314                         break;
2315                 case OP_COMPARE:
2316                 case OP_LCOMPARE:
2317                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2318                         break;
2319                 case OP_COMPARE_IMM:
2320                         g_assert (amd64_is_imm32 (ins->inst_imm));
2321                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2322                         break;
2323                 case OP_X86_COMPARE_REG_MEMBASE:
2324                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2325                         break;
2326                 case OP_X86_TEST_NULL:
2327                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2328                         break;
2329                 case OP_AMD64_TEST_NULL:
2330                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2331                         break;
2332                 case OP_X86_ADD_MEMBASE_IMM:
2333                         /* FIXME: Make a 64 version too */
2334                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2335                         break;
2336                 case OP_X86_ADD_MEMBASE:
2337                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2338                         break;
2339                 case OP_X86_SUB_MEMBASE_IMM:
2340                         g_assert (amd64_is_imm32 (ins->inst_imm));
2341                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2342                         break;
2343                 case OP_X86_SUB_MEMBASE:
2344                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2345                         break;
2346                 case OP_X86_INC_MEMBASE:
2347                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2348                         break;
2349                 case OP_X86_INC_REG:
2350                         amd64_inc_reg_size (code, ins->dreg, 4);
2351                         break;
2352                 case OP_X86_DEC_MEMBASE:
2353                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2354                         break;
2355                 case OP_X86_DEC_REG:
2356                         amd64_dec_reg_size (code, ins->dreg, 4);
2357                         break;
2358                 case OP_X86_MUL_MEMBASE:
2359                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2360                         break;
2361                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2362                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2363                         break;
2364                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2365                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2366                         break;
2367                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2368                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2369                         break;
2370                 case CEE_BREAK:
2371                         amd64_breakpoint (code);
2372                         break;
2373                 case OP_ADDCC:
2374                 case CEE_ADD:
2375                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2376                         break;
2377                 case OP_ADC:
2378                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2379                         break;
2380                 case OP_ADD_IMM:
2381                         g_assert (amd64_is_imm32 (ins->inst_imm));
2382                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2383                         break;
2384                 case OP_ADC_IMM:
2385                         g_assert (amd64_is_imm32 (ins->inst_imm));
2386                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2387                         break;
2388                 case OP_SUBCC:
2389                 case CEE_SUB:
2390                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2391                         break;
2392                 case OP_SBB:
2393                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2394                         break;
2395                 case OP_SUB_IMM:
2396                         g_assert (amd64_is_imm32 (ins->inst_imm));
2397                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2398                         break;
2399                 case OP_SBB_IMM:
2400                         g_assert (amd64_is_imm32 (ins->inst_imm));
2401                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2402                         break;
2403                 case CEE_AND:
2404                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2405                         break;
2406                 case OP_AND_IMM:
2407                         g_assert (amd64_is_imm32 (ins->inst_imm));
2408                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2409                         break;
2410                 case CEE_MUL:
2411                 case OP_LMUL:
2412                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2413                         break;
2414                 case OP_MUL_IMM:
2415                 case OP_LMUL_IMM:
2416                 case OP_IMUL_IMM: {
2417                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2418
2419                         switch (ins->inst_imm) {
2420                         case 2:
2421                                 /* MOV r1, r2 */
2422                                 /* ADD r1, r1 */
2423                                 if (ins->dreg != ins->sreg1)
2424                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2425                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2426                                 break;
2427                         case 3:
2428                                 /* LEA r1, [r2 + r2*2] */
2429                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2430                                 break;
2431                         case 5:
2432                                 /* LEA r1, [r2 + r2*4] */
2433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2434                                 break;
2435                         case 6:
2436                                 /* LEA r1, [r2 + r2*2] */
2437                                 /* ADD r1, r1          */
2438                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2439                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2440                                 break;
2441                         case 9:
2442                                 /* LEA r1, [r2 + r2*8] */
2443                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2444                                 break;
2445                         case 10:
2446                                 /* LEA r1, [r2 + r2*4] */
2447                                 /* ADD r1, r1          */
2448                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2449                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2450                                 break;
2451                         case 12:
2452                                 /* LEA r1, [r2 + r2*2] */
2453                                 /* SHL r1, 2           */
2454                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2455                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2456                                 break;
2457                         case 25:
2458                                 /* LEA r1, [r2 + r2*4] */
2459                                 /* LEA r1, [r1 + r1*4] */
2460                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2461                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2462                                 break;
2463                         case 100:
2464                                 /* LEA r1, [r2 + r2*4] */
2465                                 /* SHL r1, 2           */
2466                                 /* LEA r1, [r1 + r1*4] */
2467                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2468                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2469                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2470                                 break;
2471                         default:
2472                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2473                                 break;
2474                         }
2475                         break;
2476                 }
2477                 case CEE_DIV:
2478                 case OP_LDIV:
2479                         amd64_cdq (code);
2480                         amd64_div_reg (code, ins->sreg2, TRUE);
2481                         break;
2482                 case CEE_DIV_UN:
2483                 case OP_LDIV_UN:
2484                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2485                         amd64_div_reg (code, ins->sreg2, FALSE);
2486                         break;
2487                 case CEE_REM:
2488                 case OP_LREM:
2489                         amd64_cdq (code);
2490                         amd64_div_reg (code, ins->sreg2, TRUE);
2491                         break;
2492                 case CEE_REM_UN:
2493                 case OP_LREM_UN:
2494                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2495                         amd64_div_reg (code, ins->sreg2, FALSE);
2496                         break;
2497                 case OP_LMUL_OVF:
2498                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2499                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2500                         break;
2501                 case CEE_OR:
2502                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2503                         break;
2504                 case OP_OR_IMM
2505 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2506                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2507                         break;
2508                 case CEE_XOR:
2509                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2510                         break;
2511                 case OP_XOR_IMM:
2512                         g_assert (amd64_is_imm32 (ins->inst_imm));
2513                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2514                         break;
2515                 case CEE_SHL:
2516                 case OP_LSHL:
2517                         g_assert (ins->sreg2 == AMD64_RCX);
2518                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2519                         break;
2520                 case CEE_SHR:
2521                 case OP_LSHR:
2522                         g_assert (ins->sreg2 == AMD64_RCX);
2523                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2524                         break;
2525                 case OP_SHR_IMM:
2526                         g_assert (amd64_is_imm32 (ins->inst_imm));
2527                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2528                         break;
2529                 case OP_LSHR_IMM:
2530                         g_assert (amd64_is_imm32 (ins->inst_imm));
2531                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2532                         break;
2533                 case OP_SHR_UN_IMM:
2534                         g_assert (amd64_is_imm32 (ins->inst_imm));
2535                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2536                         break;
2537                 case OP_LSHR_UN_IMM:
2538                         g_assert (amd64_is_imm32 (ins->inst_imm));
2539                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2540                         break;
2541                 case CEE_SHR_UN:
2542                         g_assert (ins->sreg2 == AMD64_RCX);
2543                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2544                         break;
2545                 case OP_LSHR_UN:
2546                         g_assert (ins->sreg2 == AMD64_RCX);
2547                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2548                         break;
2549                 case OP_SHL_IMM:
2550                         g_assert (amd64_is_imm32 (ins->inst_imm));
2551                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2552                         break;
2553                 case OP_LSHL_IMM:
2554                         g_assert (amd64_is_imm32 (ins->inst_imm));
2555                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2556                         break;
2557
2558                 case OP_IADDCC:
2559                 case OP_IADD:
2560                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2561                         break;
2562                 case OP_IADC:
2563                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2564                         break;
2565                 case OP_IADD_IMM:
2566                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2567                         break;
2568                 case OP_IADC_IMM:
2569                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2570                         break;
2571                 case OP_ISUBCC:
2572                 case OP_ISUB:
2573                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2574                         break;
2575                 case OP_ISBB:
2576                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2577                         break;
2578                 case OP_ISUB_IMM:
2579                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2580                         break;
2581                 case OP_ISBB_IMM:
2582                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2583                         break;
2584                 case OP_IAND:
2585                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2586                         break;
2587                 case OP_IAND_IMM:
2588                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2589                         break;
2590                 case OP_IOR:
2591                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2592                         break;
2593                 case OP_IOR_IMM:
2594                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2595                         break;
2596                 case OP_IXOR:
2597                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2598                         break;
2599                 case OP_IXOR_IMM:
2600                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2601                         break;
2602                 case OP_INEG:
2603                         amd64_neg_reg_size (code, ins->sreg1, 4);
2604                         break;
2605                 case OP_INOT:
2606                         amd64_not_reg_size (code, ins->sreg1, 4);
2607                         break;
2608                 case OP_ISHL:
2609                         g_assert (ins->sreg2 == AMD64_RCX);
2610                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2611                         break;
2612                 case OP_ISHR:
2613                         g_assert (ins->sreg2 == AMD64_RCX);
2614                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2615                         break;
2616                 case OP_ISHR_IMM:
2617                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2618                         break;
2619                 case OP_ISHR_UN_IMM:
2620                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2621                         break;
2622                 case OP_ISHR_UN:
2623                         g_assert (ins->sreg2 == AMD64_RCX);
2624                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2625                         break;
2626                 case OP_ISHL_IMM:
2627                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2628                         break;
2629                 case OP_IMUL:
2630                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2631                         break;
2632                 case OP_IMUL_OVF:
2633                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2634                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2635                         break;
2636                 case OP_IMUL_OVF_UN:
2637                 case OP_LMUL_OVF_UN: {
2638                         /* the mul operation and the exception check should most likely be split */
2639                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2640                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2641                         /*g_assert (ins->sreg2 == X86_EAX);
2642                         g_assert (ins->dreg == X86_EAX);*/
2643                         if (ins->sreg2 == X86_EAX) {
2644                                 non_eax_reg = ins->sreg1;
2645                         } else if (ins->sreg1 == X86_EAX) {
2646                                 non_eax_reg = ins->sreg2;
2647                         } else {
2648                                 /* no need to save since we're going to store to it anyway */
2649                                 if (ins->dreg != X86_EAX) {
2650                                         saved_eax = TRUE;
2651                                         amd64_push_reg (code, X86_EAX);
2652                                 }
2653                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2654                                 non_eax_reg = ins->sreg2;
2655                         }
2656                         if (ins->dreg == X86_EDX) {
2657                                 if (!saved_eax) {
2658                                         saved_eax = TRUE;
2659                                         amd64_push_reg (code, X86_EAX);
2660                                 }
2661                         } else {
2662                                 saved_edx = TRUE;
2663                                 amd64_push_reg (code, X86_EDX);
2664                         }
2665                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2666                         /* save before the check since pop and mov don't change the flags */
2667                         if (ins->dreg != X86_EAX)
2668                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2669                         if (saved_edx)
2670                                 amd64_pop_reg (code, X86_EDX);
2671                         if (saved_eax)
2672                                 amd64_pop_reg (code, X86_EAX);
2673                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2674                         break;
2675                 }
2676                 case OP_IDIV:
2677                         amd64_cdq_size (code, 4);
2678                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2679                         break;
2680                 case OP_IDIV_UN:
2681                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2682                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2683                         break;
2684                 case OP_IREM:
2685                         amd64_cdq_size (code, 4);
2686                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2687                         break;
2688                 case OP_IREM_UN:
2689                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2690                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2691                         break;
2692                 case OP_ICOMPARE:
2693                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2694                         break;
2695                 case OP_ICOMPARE_IMM:
2696                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2697                         break;
2698                 case OP_IBEQ:
2699                 case OP_IBLT:
2700                 case OP_IBGT:
2701                 case OP_IBGE:
2702                 case OP_IBLE:
2703                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2704                         break;
2705                 case OP_IBNE_UN:
2706                 case OP_IBLT_UN:
2707                 case OP_IBGT_UN:
2708                 case OP_IBGE_UN:
2709                 case OP_IBLE_UN:
2710                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2711                         break;
2712                 case OP_COND_EXC_IOV:
2713                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2714                                                                                 TRUE, ins->inst_p1);
2715                         break;
2716                 case OP_COND_EXC_IC:
2717                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2718                                                                                 FALSE, ins->inst_p1);
2719                         break;
2720                 case CEE_NOT:
2721                         amd64_not_reg (code, ins->sreg1);
2722                         break;
2723                 case CEE_NEG:
2724                         amd64_neg_reg (code, ins->sreg1);
2725                         break;
2726                 case OP_SEXT_I1:
2727                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2728                         break;
2729                 case OP_SEXT_I2:
2730                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2731                         break;
2732                 case OP_SEXT_I4:
2733                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2734                         break;
2735                 case OP_ICONST:
2736                 case OP_I8CONST:
2737                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2738                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2739                         else
2740                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2741                         break;
2742                 case OP_AOTCONST:
2743                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2744                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2745                         break;
2746                 case CEE_CONV_I4:
2747                 case CEE_CONV_U4:
2748                 case OP_MOVE:
2749                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2750                         break;
2751                 case OP_AMD64_SET_XMMREG_R4: {
2752                         if (use_sse2) {
2753                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2754                         }
2755                         else {
2756                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2757                                 /* ins->dreg is set to -1 by the reg allocator */
2758                                 amd64_movss_reg_membase (code, ins->unused, AMD64_RSP, -8);
2759                         }
2760                         break;
2761                 }
2762                 case OP_AMD64_SET_XMMREG_R8: {
2763                         if (use_sse2) {
2764                                 if (ins->dreg != ins->sreg1)
2765                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2766                         }
2767                         else {
2768                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2769                                 /* ins->dreg is set to -1 by the reg allocator */
2770                                 amd64_movsd_reg_membase (code, ins->unused, AMD64_RSP, -8);
2771                         }
2772                         break;
2773                 }
2774                 case CEE_JMP: {
2775                         /*
2776                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2777                          * Keep in sync with the code in emit_epilog.
2778                          */
2779                         int pos = 0, i;
2780
2781                         /* FIXME: no tracing support... */
2782                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2783                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2784
2785                         g_assert (!cfg->method->save_lmf);
2786
2787                         code = emit_load_volatile_arguments (cfg, code);
2788
2789                         if (cfg->arch.omit_fp) {
2790                                 guint32 save_offset = 0;
2791                                 /* Pop callee-saved registers */
2792                                 for (i = 0; i < AMD64_NREG; ++i)
2793                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2794                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2795                                                 save_offset += 8;
2796                                         }
2797                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2798                         }
2799                         else {
2800                                 for (i = 0; i < AMD64_NREG; ++i)
2801                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2802                                                 pos -= sizeof (gpointer);
2803
2804                                 if (pos)
2805                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2806
2807                                 /* Pop registers in reverse order */
2808                                 for (i = AMD64_NREG - 1; i > 0; --i)
2809                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2810                                                 amd64_pop_reg (code, i);
2811                                         }
2812
2813                                 amd64_leave (code);
2814                         }
2815
2816                         offset = code - cfg->native_code;
2817                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2818                         if (cfg->compile_aot)
2819                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2820                         else
2821                                 amd64_set_reg_template (code, AMD64_R11);
2822                         amd64_jump_reg (code, AMD64_R11);
2823                         break;
2824                 }
2825                 case OP_CHECK_THIS:
2826                         /* ensure ins->sreg1 is not NULL */
2827                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2828                         break;
2829                 case OP_ARGLIST: {
2830                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2831                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2832                         break;
2833                 }
2834                 case OP_FCALL:
2835                 case OP_LCALL:
2836                 case OP_VCALL:
2837                 case OP_VOIDCALL:
2838                 case CEE_CALL:
2839                         call = (MonoCallInst*)ins;
2840                         /*
2841                          * The AMD64 ABI forces callers to know about varargs.
2842                          */
2843                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2844                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2845                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2846                                 /*
2847                                  * Since the unmanaged calling convention doesn't contain a
2848                                  * 'vararg' entry, we have to treat every pinvoke call as a
2849                                  * potential vararg call.
2850                                  */
2851                                 guint32 nregs, i;
2852                                 nregs = 0;
2853                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2854                                         if (call->used_fregs & (1 << i))
2855                                                 nregs ++;
2856                                 if (!nregs)
2857                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2858                                 else
2859                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2860                         }
2861
2862                         if (ins->flags & MONO_INST_HAS_METHOD)
2863                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2864                         else
2865                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2866                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2867                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2868                         code = emit_move_return_value (cfg, ins, code);
2869                         break;
2870                 case OP_FCALL_REG:
2871                 case OP_LCALL_REG:
2872                 case OP_VCALL_REG:
2873                 case OP_VOIDCALL_REG:
2874                 case OP_CALL_REG:
2875                         call = (MonoCallInst*)ins;
2876
2877                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2878                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2879                                 ins->sreg1 = AMD64_R11;
2880                         }
2881
2882                         /*
2883                          * The AMD64 ABI forces callers to know about varargs.
2884                          */
2885                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2886                                 if (ins->sreg1 == AMD64_RAX) {
2887                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2888                                         ins->sreg1 = AMD64_R11;
2889                                 }
2890                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2891                         }
2892                         amd64_call_reg (code, ins->sreg1);
2893                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2894                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2895                         code = emit_move_return_value (cfg, ins, code);
2896                         break;
2897                 case OP_FCALL_MEMBASE:
2898                 case OP_LCALL_MEMBASE:
2899                 case OP_VCALL_MEMBASE:
2900                 case OP_VOIDCALL_MEMBASE:
2901                 case OP_CALL_MEMBASE:
2902                         call = (MonoCallInst*)ins;
2903
2904                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2905                                 /*
2906                                  * Can't use R11 because it is clobbered by the trampoline
2907                                  * code, and the reg value is needed by get_vcall_slot_addr.
2908                                  */
2909                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
2910                                 ins->sreg1 = AMD64_RAX;
2911                         }
2912
2913                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
2914                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2915                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2916                         code = emit_move_return_value (cfg, ins, code);
2917                         break;
2918                 case OP_OUTARG:
2919                 case OP_X86_PUSH:
2920                         amd64_push_reg (code, ins->sreg1);
2921                         break;
2922                 case OP_X86_PUSH_IMM:
2923                         g_assert (amd64_is_imm32 (ins->inst_imm));
2924                         amd64_push_imm (code, ins->inst_imm);
2925                         break;
2926                 case OP_X86_PUSH_MEMBASE:
2927                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
2928                         break;
2929                 case OP_X86_PUSH_OBJ:
2930                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
2931                         amd64_push_reg (code, AMD64_RDI);
2932                         amd64_push_reg (code, AMD64_RSI);
2933                         amd64_push_reg (code, AMD64_RCX);
2934                         if (ins->inst_offset)
2935                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
2936                         else
2937                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
2938                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
2939                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
2940                         amd64_cld (code);
2941                         amd64_prefix (code, X86_REP_PREFIX);
2942                         amd64_movsd (code);
2943                         amd64_pop_reg (code, AMD64_RCX);
2944                         amd64_pop_reg (code, AMD64_RSI);
2945                         amd64_pop_reg (code, AMD64_RDI);
2946                         break;
2947                 case OP_X86_LEA:
2948                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2949                         break;
2950                 case OP_X86_LEA_MEMBASE:
2951                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2952                         break;
2953                 case OP_X86_XCHG:
2954                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2955                         break;
2956                 case OP_LOCALLOC:
2957                         /* keep alignment */
2958                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2959                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2960                         code = mono_emit_stack_alloc (code, ins);
2961                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
2962                         break;
2963                 case CEE_RET:
2964                         amd64_ret (code);
2965                         break;
2966                 case CEE_THROW: {
2967                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
2968                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2969                                              (gpointer)"mono_arch_throw_exception");
2970                         break;
2971                 }
2972                 case OP_RETHROW: {
2973                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
2974                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2975                                              (gpointer)"mono_arch_rethrow_exception");
2976                         break;
2977                 }
2978                 case OP_CALL_HANDLER:
2979                         /* Align stack */
2980                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
2981                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2982                         amd64_call_imm (code, 0);
2983                         /* Restore stack alignment */
2984                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2985                         break;
2986                 case OP_LABEL:
2987                         ins->inst_c0 = code - cfg->native_code;
2988                         break;
2989                 case CEE_BR:
2990                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2991                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2992                         //break;
2993                         if (ins->flags & MONO_INST_BRLABEL) {
2994                                 if (ins->inst_i0->inst_c0) {
2995                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2996                                 } else {
2997                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2998                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
2999                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3000                                                 x86_jump8 (code, 0);
3001                                         else
3002                                                 x86_jump32 (code, 0);
3003                                 }
3004                         } else {
3005                                 if (ins->inst_target_bb->native_offset) {
3006                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3007                                 } else {
3008                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3009                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3010                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3011                                                 x86_jump8 (code, 0);
3012                                         else
3013                                                 x86_jump32 (code, 0);
3014                                 }
3015                         }
3016                         break;
3017                 case OP_BR_REG:
3018                         amd64_jump_reg (code, ins->sreg1);
3019                         break;
3020                 case OP_CEQ:
3021                 case OP_ICEQ:
3022                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3023                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3024                         break;
3025                 case OP_CLT:
3026                 case OP_ICLT:
3027                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3028                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3029                         break;
3030                 case OP_CLT_UN:
3031                 case OP_ICLT_UN:
3032                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3033                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3034                         break;
3035                 case OP_CGT:
3036                 case OP_ICGT:
3037                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3038                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3039                         break;
3040                 case OP_CGT_UN:
3041                 case OP_ICGT_UN:
3042                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3043                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3044                         break;
3045                 case OP_COND_EXC_EQ:
3046                 case OP_COND_EXC_NE_UN:
3047                 case OP_COND_EXC_LT:
3048                 case OP_COND_EXC_LT_UN:
3049                 case OP_COND_EXC_GT:
3050                 case OP_COND_EXC_GT_UN:
3051                 case OP_COND_EXC_GE:
3052                 case OP_COND_EXC_GE_UN:
3053                 case OP_COND_EXC_LE:
3054                 case OP_COND_EXC_LE_UN:
3055                 case OP_COND_EXC_OV:
3056                 case OP_COND_EXC_NO:
3057                 case OP_COND_EXC_C:
3058                 case OP_COND_EXC_NC:
3059                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3060                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3061                         break;
3062                 case CEE_BEQ:
3063                 case CEE_BNE_UN:
3064                 case CEE_BLT:
3065                 case CEE_BLT_UN:
3066                 case CEE_BGT:
3067                 case CEE_BGT_UN:
3068                 case CEE_BGE:
3069                 case CEE_BGE_UN:
3070                 case CEE_BLE:
3071                 case CEE_BLE_UN:
3072                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3073                         break;
3074
3075                 /* floating point opcodes */
3076                 case OP_R8CONST: {
3077                         double d = *(double *)ins->inst_p0;
3078
3079                         if (use_sse2) {
3080                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3081                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3082                                 }
3083                                 else {
3084                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3085                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3086                                 }
3087                         }
3088                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3089                                 amd64_fldz (code);
3090                         } else if (d == 1.0) {
3091                                 x86_fld1 (code);
3092                         } else {
3093                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3094                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3095                         }
3096                         break;
3097                 }
3098                 case OP_R4CONST: {
3099                         float f = *(float *)ins->inst_p0;
3100
3101                         if (use_sse2) {
3102                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3103                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3104                                 }
3105                                 else {
3106                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3107                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3108                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3109                                 }
3110                         }
3111                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3112                                 amd64_fldz (code);
3113                         } else if (f == 1.0) {
3114                                 x86_fld1 (code);
3115                         } else {
3116                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3117                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3118                         }
3119                         break;
3120                 }
3121                 case OP_STORER8_MEMBASE_REG:
3122                         if (use_sse2)
3123                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3124                         else
3125                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3126                         break;
3127                 case OP_LOADR8_SPILL_MEMBASE:
3128                         if (use_sse2)
3129                                 g_assert_not_reached ();
3130                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3131                         amd64_fxch (code, 1);
3132                         break;
3133                 case OP_LOADR8_MEMBASE:
3134                         if (use_sse2)
3135                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3136                         else
3137                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3138                         break;
3139                 case OP_STORER4_MEMBASE_REG:
3140                         if (use_sse2) {
3141                                 /* This requires a double->single conversion */
3142                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3143                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3144                         }
3145                         else
3146                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3147                         break;
3148                 case OP_LOADR4_MEMBASE:
3149                         if (use_sse2) {
3150                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3151                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3152                         }
3153                         else
3154                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3155                         break;
3156                 case CEE_CONV_R4: /* FIXME: change precision */
3157                 case CEE_CONV_R8:
3158                         if (use_sse2)
3159                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3160                         else {
3161                                 amd64_push_reg (code, ins->sreg1);
3162                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3163                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3164                         }
3165                         break;
3166                 case CEE_CONV_R_UN:
3167                         /* Emulated */
3168                         g_assert_not_reached ();
3169                         break;
3170                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3171                 case OP_LCONV_TO_R8:
3172                         if (use_sse2)
3173                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3174                         else {
3175                                 amd64_push_reg (code, ins->sreg1);
3176                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3177                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3178                         }
3179                         break;
3180                 case OP_X86_FP_LOAD_I8:
3181                         if (use_sse2)
3182                                 g_assert_not_reached ();
3183                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3184                         break;
3185                 case OP_X86_FP_LOAD_I4:
3186                         if (use_sse2)
3187                                 g_assert_not_reached ();
3188                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3189                         break;
3190                 case OP_FCONV_TO_I1:
3191                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3192                         break;
3193                 case OP_FCONV_TO_U1:
3194                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3195                         break;
3196                 case OP_FCONV_TO_I2:
3197                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3198                         break;
3199                 case OP_FCONV_TO_U2:
3200                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3201                         break;
3202                 case OP_FCONV_TO_I4:
3203                 case OP_FCONV_TO_I:
3204                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3205                         break;
3206                 case OP_FCONV_TO_I8:
3207                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3208                         break;
3209                 case OP_LCONV_TO_R_UN: {
3210                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3211                         guint8 *br;
3212
3213                         if (use_sse2)
3214                                 g_assert_not_reached ();
3215
3216                         /* load 64bit integer to FP stack */
3217                         amd64_push_imm (code, 0);
3218                         amd64_push_reg (code, ins->sreg2);
3219                         amd64_push_reg (code, ins->sreg1);
3220                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3221                         /* store as 80bit FP value */
3222                         x86_fst80_membase (code, AMD64_RSP, 0);
3223
3224                         /* test if lreg is negative */
3225                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3226                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3227
3228                         /* add correction constant mn */
3229                         x86_fld80_mem (code, mn);
3230                         x86_fld80_membase (code, AMD64_RSP, 0);
3231                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3232                         x86_fst80_membase (code, AMD64_RSP, 0);
3233
3234                         amd64_patch (br, code);
3235
3236                         x86_fld80_membase (code, AMD64_RSP, 0);
3237                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3238
3239                         break;
3240                 }
3241                 case CEE_CONV_OVF_U4:
3242                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3243                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3244                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3245                         break;
3246                 case CEE_CONV_OVF_I4_UN:
3247                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3248                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3249                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3250                         break;
3251                 case OP_FMOVE:
3252                         if (use_sse2 && (ins->dreg != ins->sreg1))
3253                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3254                         break;
3255                 case OP_FADD:
3256                         if (use_sse2)
3257                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3258                         else
3259                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3260                         break;
3261                 case OP_FSUB:
3262                         if (use_sse2)
3263                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3264                         else
3265                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3266                         break;
3267                 case OP_FMUL:
3268                         if (use_sse2)
3269                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3270                         else
3271                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3272                         break;
3273                 case OP_FDIV:
3274                         if (use_sse2)
3275                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3276                         else
3277                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3278                         break;
3279                 case OP_FNEG:
3280                         if (use_sse2) {
3281                                 amd64_mov_reg_imm_size (code, AMD64_R11, 0x8000000000000000, 8);
3282                                 amd64_push_reg (code, AMD64_R11);
3283                                 amd64_push_reg (code, AMD64_R11);
3284                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RSP, 0);
3285                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3286                         }
3287                         else
3288                                 amd64_fchs (code);
3289                         break;
3290                 case OP_SIN:
3291                         if (use_sse2) {
3292                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3293                         }
3294                         else {
3295                                 amd64_fsin (code);
3296                                 amd64_fldz (code);
3297                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3298                         }
3299                         break;
3300                 case OP_COS:
3301                         if (use_sse2) {
3302                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3303                         }
3304                         else {
3305                                 amd64_fcos (code);
3306                                 amd64_fldz (code);
3307                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3308                         }
3309                         break;
3310                 case OP_ABS:
3311                         if (use_sse2) {
3312                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3313                         }
3314                         else
3315                                 amd64_fabs (code);
3316                         break;
3317                 case OP_TAN: {
3318                         /*
3319                          * it really doesn't make sense to inline all this code,
3320                          * it's here just to show that things may not be as simple
3321                          * as they appear.
3322                          */
3323                         guchar *check_pos, *end_tan, *pop_jump;
3324                         if (use_sse2)
3325                                 g_assert_not_reached ();
3326                         amd64_push_reg (code, AMD64_RAX);
3327                         amd64_fptan (code);
3328                         amd64_fnstsw (code);
3329                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3330                         check_pos = code;
3331                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3332                         amd64_fstp (code, 0); /* pop the 1.0 */
3333                         end_tan = code;
3334                         x86_jump8 (code, 0);
3335                         amd64_fldpi (code);
3336                         amd64_fp_op (code, X86_FADD, 0);
3337                         amd64_fxch (code, 1);
3338                         x86_fprem1 (code);
3339                         amd64_fstsw (code);
3340                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3341                         pop_jump = code;
3342                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3343                         amd64_fstp (code, 1);
3344                         amd64_fptan (code);
3345                         amd64_patch (pop_jump, code);
3346                         amd64_fstp (code, 0); /* pop the 1.0 */
3347                         amd64_patch (check_pos, code);
3348                         amd64_patch (end_tan, code);
3349                         amd64_fldz (code);
3350                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3351                         amd64_pop_reg (code, AMD64_RAX);
3352                         break;
3353                 }
3354                 case OP_ATAN:
3355                         if (use_sse2)
3356                                 g_assert_not_reached ();
3357                         x86_fld1 (code);
3358                         amd64_fpatan (code);
3359                         amd64_fldz (code);
3360                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3361                         break;
3362                 case OP_SQRT:
3363                         if (use_sse2) {
3364                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3365                         }
3366                         else
3367                                 amd64_fsqrt (code);
3368                         break;
3369                 case OP_X86_FPOP:
3370                         if (!use_sse2)
3371                                 amd64_fstp (code, 0);
3372                         break;
3373                 case OP_FREM: {
3374                         guint8 *l1, *l2;
3375
3376                         if (use_sse2)
3377                                 g_assert_not_reached ();
3378                         amd64_push_reg (code, AMD64_RAX);
3379                         /* we need to exchange ST(0) with ST(1) */
3380                         amd64_fxch (code, 1);
3381
3382                         /* this requires a loop, because fprem somtimes
3383                          * returns a partial remainder */
3384                         l1 = code;
3385                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3386                         /* x86_fprem1 (code); */
3387                         amd64_fprem (code);
3388                         amd64_fnstsw (code);
3389                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3390                         l2 = code + 2;
3391                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3392
3393                         /* pop result */
3394                         amd64_fstp (code, 1);
3395
3396                         amd64_pop_reg (code, AMD64_RAX);
3397                         break;
3398                 }
3399                 case OP_FCOMPARE:
3400                         if (use_sse2) {
3401                                 /*
3402                                  * The two arguments are swapped because the fbranch instructions
3403                                  * depend on this for the non-sse case to work.
3404                                  */
3405                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3406                                 break;
3407                         }
3408                         if (cfg->opt & MONO_OPT_FCMOV) {
3409                                 amd64_fcomip (code, 1);
3410                                 amd64_fstp (code, 0);
3411                                 break;
3412                         }
3413                         /* this overwrites EAX */
3414                         EMIT_FPCOMPARE(code);
3415                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3416                         break;
3417                 case OP_FCEQ:
3418                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3419                                 /* zeroing the register at the start results in
3420                                  * shorter and faster code (we can also remove the widening op)
3421                                  */
3422                                 guchar *unordered_check;
3423                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3424
3425                                 if (use_sse2)
3426                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3427                                 else {
3428                                         amd64_fcomip (code, 1);
3429                                         amd64_fstp (code, 0);
3430                                 }
3431                                 unordered_check = code;
3432                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3433                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3434                                 amd64_patch (unordered_check, code);
3435                                 break;
3436                         }
3437                         if (ins->dreg != AMD64_RAX)
3438                                 amd64_push_reg (code, AMD64_RAX);
3439
3440                         EMIT_FPCOMPARE(code);
3441                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3442                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3443                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3444                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3445
3446                         if (ins->dreg != AMD64_RAX)
3447                                 amd64_pop_reg (code, AMD64_RAX);
3448                         break;
3449                 case OP_FCLT:
3450                 case OP_FCLT_UN:
3451                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3452                                 /* zeroing the register at the start results in
3453                                  * shorter and faster code (we can also remove the widening op)
3454                                  */
3455                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3456                                 if (use_sse2)
3457                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3458                                 else {
3459                                         amd64_fcomip (code, 1);
3460                                         amd64_fstp (code, 0);
3461                                 }
3462                                 if (ins->opcode == OP_FCLT_UN) {
3463                                         guchar *unordered_check = code;
3464                                         guchar *jump_to_end;
3465                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3466                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3467                                         jump_to_end = code;
3468                                         x86_jump8 (code, 0);
3469                                         amd64_patch (unordered_check, code);
3470                                         amd64_inc_reg (code, ins->dreg);
3471                                         amd64_patch (jump_to_end, code);
3472                                 } else {
3473                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3474                                 }
3475                                 break;
3476                         }
3477                         if (ins->dreg != AMD64_RAX)
3478                                 amd64_push_reg (code, AMD64_RAX);
3479
3480                         EMIT_FPCOMPARE(code);
3481                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3482                         if (ins->opcode == OP_FCLT_UN) {
3483                                 guchar *is_not_zero_check, *end_jump;
3484                                 is_not_zero_check = code;
3485                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3486                                 end_jump = code;
3487                                 x86_jump8 (code, 0);
3488                                 amd64_patch (is_not_zero_check, code);
3489                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3490
3491                                 amd64_patch (end_jump, code);
3492                         }
3493                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3494                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3495
3496                         if (ins->dreg != AMD64_RAX)
3497                                 amd64_pop_reg (code, AMD64_RAX);
3498                         break;
3499                 case OP_FCGT:
3500                 case OP_FCGT_UN:
3501                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3502                                 /* zeroing the register at the start results in
3503                                  * shorter and faster code (we can also remove the widening op)
3504                                  */
3505                                 guchar *unordered_check;
3506                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3507                                 if (use_sse2)
3508                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3509                                 else {
3510                                         amd64_fcomip (code, 1);
3511                                         amd64_fstp (code, 0);
3512                                 }
3513                                 if (ins->opcode == OP_FCGT) {
3514                                         unordered_check = code;
3515                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3516                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3517                                         amd64_patch (unordered_check, code);
3518                                 } else {
3519                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3520                                 }
3521                                 break;
3522                         }
3523                         if (ins->dreg != AMD64_RAX)
3524                                 amd64_push_reg (code, AMD64_RAX);
3525
3526                         EMIT_FPCOMPARE(code);
3527                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3528                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3529                         if (ins->opcode == OP_FCGT_UN) {
3530                                 guchar *is_not_zero_check, *end_jump;
3531                                 is_not_zero_check = code;
3532                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3533                                 end_jump = code;
3534                                 x86_jump8 (code, 0);
3535                                 amd64_patch (is_not_zero_check, code);
3536                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3537
3538                                 amd64_patch (end_jump, code);
3539                         }
3540                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3541                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3542
3543                         if (ins->dreg != AMD64_RAX)
3544                                 amd64_pop_reg (code, AMD64_RAX);
3545                         break;
3546                 case OP_FCLT_MEMBASE:
3547                 case OP_FCGT_MEMBASE:
3548                 case OP_FCLT_UN_MEMBASE:
3549                 case OP_FCGT_UN_MEMBASE:
3550                 case OP_FCEQ_MEMBASE: {
3551                         guchar *unordered_check, *jump_to_end;
3552                         int x86_cond;
3553                         g_assert (use_sse2);
3554
3555                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3556                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3557
3558                         switch (ins->opcode) {
3559                         case OP_FCEQ_MEMBASE:
3560                                 x86_cond = X86_CC_EQ;
3561                                 break;
3562                         case OP_FCLT_MEMBASE:
3563                         case OP_FCLT_UN_MEMBASE:
3564                                 x86_cond = X86_CC_LT;
3565                                 break;
3566                         case OP_FCGT_MEMBASE:
3567                         case OP_FCGT_UN_MEMBASE:
3568                                 x86_cond = X86_CC_GT;
3569                                 break;
3570                         default:
3571                                 g_assert_not_reached ();
3572                         }
3573
3574                         unordered_check = code;
3575                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3576                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3577
3578                         switch (ins->opcode) {
3579                         case OP_FCEQ_MEMBASE:
3580                         case OP_FCLT_MEMBASE:
3581                         case OP_FCGT_MEMBASE:
3582                                 amd64_patch (unordered_check, code);
3583                                 break;
3584                         case OP_FCLT_UN_MEMBASE:
3585                         case OP_FCGT_UN_MEMBASE:
3586                                 jump_to_end = code;
3587                                 x86_jump8 (code, 0);
3588                                 amd64_patch (unordered_check, code);
3589                                 amd64_inc_reg (code, ins->dreg);
3590                                 amd64_patch (jump_to_end, code);
3591                                 break;
3592                         default:
3593                                 break;
3594                         }
3595                         break;
3596                 }
3597                 case OP_FBEQ:
3598                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3599                                 guchar *jump = code;
3600                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3601                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3602                                 amd64_patch (jump, code);
3603                                 break;
3604                         }
3605                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3606                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3607                         break;
3608                 case OP_FBNE_UN:
3609                         /* Branch if C013 != 100 */
3610                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3611                                 /* branch if !ZF or (PF|CF) */
3612                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3613                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3614                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3615                                 break;
3616                         }
3617                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3618                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3619                         break;
3620                 case OP_FBLT:
3621                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3622                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3623                                 break;
3624                         }
3625                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3626                         break;
3627                 case OP_FBLT_UN:
3628                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3629                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3630                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3631                                 break;
3632                         }
3633                         if (ins->opcode == OP_FBLT_UN) {
3634                                 guchar *is_not_zero_check, *end_jump;
3635                                 is_not_zero_check = code;
3636                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3637                                 end_jump = code;
3638                                 x86_jump8 (code, 0);
3639                                 amd64_patch (is_not_zero_check, code);
3640                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3641
3642                                 amd64_patch (end_jump, code);
3643                         }
3644                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3645                         break;
3646                 case OP_FBGT:
3647                 case OP_FBGT_UN:
3648                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3649                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3650                                 break;
3651                         }
3652                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3653                         if (ins->opcode == OP_FBGT_UN) {
3654                                 guchar *is_not_zero_check, *end_jump;
3655                                 is_not_zero_check = code;
3656                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3657                                 end_jump = code;
3658                                 x86_jump8 (code, 0);
3659                                 amd64_patch (is_not_zero_check, code);
3660                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3661
3662                                 amd64_patch (end_jump, code);
3663                         }
3664                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3665                         break;
3666                 case OP_FBGE:
3667                         /* Branch if C013 == 100 or 001 */
3668                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3669                                 guchar *br1;
3670
3671                                 /* skip branch if C1=1 */
3672                                 br1 = code;
3673                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3674                                 /* branch if (C0 | C3) = 1 */
3675                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3676                                 amd64_patch (br1, code);
3677                                 break;
3678                         }
3679                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3680                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3681                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3682                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3683                         break;
3684                 case OP_FBGE_UN:
3685                         /* Branch if C013 == 000 */
3686                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3687                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3688                                 break;
3689                         }
3690                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3691                         break;
3692                 case OP_FBLE:
3693                         /* Branch if C013=000 or 100 */
3694                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3695                                 guchar *br1;
3696
3697                                 /* skip branch if C1=1 */
3698                                 br1 = code;
3699                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3700                                 /* branch if C0=0 */
3701                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3702                                 amd64_patch (br1, code);
3703                                 break;
3704                         }
3705                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3706                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3707                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3708                         break;
3709                 case OP_FBLE_UN:
3710                         /* Branch if C013 != 001 */
3711                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3712                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3713                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3714                                 break;
3715                         }
3716                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3717                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3718                         break;
3719                 case CEE_CKFINITE: {
3720                         if (use_sse2) {
3721                                 /* Transfer value to the fp stack */
3722                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3723                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3724                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3725                         }
3726                         amd64_push_reg (code, AMD64_RAX);
3727                         amd64_fxam (code);
3728                         amd64_fnstsw (code);
3729                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3730                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3731                         amd64_pop_reg (code, AMD64_RAX);
3732                         if (use_sse2) {
3733                                 amd64_fstp (code, 0);
3734                         }
3735                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3736                         if (use_sse2)
3737                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3738                         break;
3739                 }
3740                 case OP_TLS_GET: {
3741                         x86_prefix (code, X86_FS_PREFIX);
3742                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_offset, 8);
3743                         break;
3744                 }
3745                 case OP_MEMORY_BARRIER: {
3746                         /* Not needed on amd64 */
3747                         break;
3748                 }
3749                 case OP_ATOMIC_ADD_I4:
3750                 case OP_ATOMIC_ADD_I8: {
3751                         int dreg = ins->dreg;
3752                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3753
3754                         if (dreg == ins->inst_basereg)
3755                                 dreg = AMD64_R11;
3756
3757                         if (dreg != ins->sreg2)
3758                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3759
3760                         x86_prefix (code, X86_LOCK_PREFIX);
3761                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3762
3763                         if (dreg != ins->dreg)
3764                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3765
3766                         break;
3767                 }
3768                 case OP_ATOMIC_ADD_NEW_I4:
3769                 case OP_ATOMIC_ADD_NEW_I8: {
3770                         int dreg = ins->dreg;
3771                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3772
3773                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3774                                 dreg = AMD64_R11;
3775
3776                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3777                         amd64_prefix (code, X86_LOCK_PREFIX);
3778                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3779                         /* dreg contains the old value, add with sreg2 value */
3780                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3781
3782                         if (ins->dreg != dreg)
3783                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3784
3785                         break;
3786                 }
3787                 case OP_ATOMIC_EXCHANGE_I4:
3788                 case OP_ATOMIC_EXCHANGE_I8: {
3789                         guchar *br[2];
3790                         int sreg2 = ins->sreg2;
3791                         int breg = ins->inst_basereg;
3792                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3793
3794                         /*
3795                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3796                          * an explanation of how this works.
3797                          */
3798
3799                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3800                          * hack to overcome limits in x86 reg allocator
3801                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3802                          */
3803                         if (ins->dreg != AMD64_RAX)
3804                                 amd64_push_reg (code, AMD64_RAX);
3805
3806                         /* We need the EAX reg for the cmpxchg */
3807                         if (ins->sreg2 == AMD64_RAX) {
3808                                 amd64_push_reg (code, AMD64_RDX);
3809                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3810                                 sreg2 = AMD64_RDX;
3811                         }
3812
3813                         if (breg == AMD64_RAX) {
3814                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, size);
3815                                 breg = AMD64_R11;
3816                         }
3817
3818                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3819
3820                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3821                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3822                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3823                         amd64_patch (br [1], br [0]);
3824
3825                         if (ins->dreg != AMD64_RAX) {
3826                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3827                                 amd64_pop_reg (code, AMD64_RAX);
3828                         }
3829
3830                         if (ins->sreg2 != sreg2)
3831                                 amd64_pop_reg (code, AMD64_RDX);
3832
3833                         break;
3834                 }
3835                 default:
3836                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3837                         g_assert_not_reached ();
3838                 }
3839
3840                 if ((code - cfg->native_code - offset) > max_len) {
3841                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3842                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3843                         g_assert_not_reached ();
3844                 }
3845
3846                 cpos += max_len;
3847
3848                 last_ins = ins;
3849                 last_offset = offset;
3850
3851                 ins = ins->next;
3852         }
3853
3854         cfg->code_len = code - cfg->native_code;
3855 }
3856
3857 void
3858 mono_arch_register_lowlevel_calls (void)
3859 {
3860 }
3861
3862 void
3863 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3864 {
3865         MonoJumpInfo *patch_info;
3866         gboolean compile_aot = !run_cctors;
3867
3868         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3869                 unsigned char *ip = patch_info->ip.i + code;
3870                 const unsigned char *target;
3871
3872                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3873
3874                 if (compile_aot) {
3875                         switch (patch_info->type) {
3876                         case MONO_PATCH_INFO_BB:
3877                         case MONO_PATCH_INFO_LABEL:
3878                                 break;
3879                         default:
3880                                 /* No need to patch these */
3881                                 continue;
3882                         }
3883                 }
3884
3885                 switch (patch_info->type) {
3886                 case MONO_PATCH_INFO_NONE:
3887                         continue;
3888                 case MONO_PATCH_INFO_CLASS_INIT: {
3889                         /* Might already been changed to a nop */
3890                         guint8* ip2 = ip;
3891                         amd64_call_code (ip2, 0);
3892                         break;
3893                 }
3894                 case MONO_PATCH_INFO_METHOD_REL:
3895                 case MONO_PATCH_INFO_R8:
3896                 case MONO_PATCH_INFO_R4:
3897                         g_assert_not_reached ();
3898                         continue;
3899                 case MONO_PATCH_INFO_BB:
3900                         break;
3901                 default:
3902                         break;
3903                 }
3904                 amd64_patch (ip, (gpointer)target);
3905         }
3906 }
3907
3908 guint8 *
3909 mono_arch_emit_prolog (MonoCompile *cfg)
3910 {
3911         MonoMethod *method = cfg->method;
3912         MonoBasicBlock *bb;
3913         MonoMethodSignature *sig;
3914         MonoInst *inst;
3915         int alloc_size, pos, max_offset, i, quad;
3916         guint8 *code;
3917         CallInfo *cinfo;
3918         gint32 lmf_offset = cfg->arch.lmf_offset;
3919
3920         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
3921         code = cfg->native_code = g_malloc (cfg->code_size);
3922
3923         /* Amount of stack space allocated by register saving code */
3924         pos = 0;
3925
3926         /*
3927          * The prolog consists of the following parts:
3928          * FP present:
3929          * - push rbp, mov rbp, rsp
3930          * - save callee saved regs using pushes
3931          * - allocate frame
3932          * - save lmf if needed
3933          * FP not present:
3934          * - allocate frame
3935          * - save lmf if needed
3936          * - save callee saved regs using moves
3937          */
3938
3939         if (!cfg->arch.omit_fp) {
3940                 amd64_push_reg (code, AMD64_RBP);
3941                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
3942         }
3943
3944         /* Save callee saved registers */
3945         if (!cfg->arch.omit_fp && !method->save_lmf) {
3946                 for (i = 0; i < AMD64_NREG; ++i)
3947                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3948                                 amd64_push_reg (code, i);
3949                                 pos += sizeof (gpointer);
3950                         }
3951         }
3952
3953         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3954
3955         alloc_size -= pos;
3956
3957         if (cfg->arch.omit_fp)
3958                 /*
3959                  * On enter, the stack is misaligned by the the pushing of the return
3960                  * address. It is either made aligned by the pushing of %rbp, or by
3961                  * this.
3962                  */
3963                 alloc_size += 8;
3964
3965         cfg->arch.stack_alloc_size = alloc_size;
3966
3967         /* Allocate stack frame */
3968         if (alloc_size) {
3969                 /* See mono_emit_stack_alloc */
3970 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3971                 guint32 remaining_size = alloc_size;
3972                 while (remaining_size >= 0x1000) {
3973                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3974                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3975                         remaining_size -= 0x1000;
3976                 }
3977                 if (remaining_size)
3978                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
3979 #else
3980                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
3981 #endif
3982         }
3983
3984         /* Stack alignment check */
3985 #if 0
3986         {
3987                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
3988                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
3989                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3990                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
3991                 amd64_breakpoint (code);
3992         }
3993 #endif
3994
3995         /* Save LMF */
3996         if (method->save_lmf) {
3997                 /* Save ip */
3998                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
3999                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4000                 /* Save fp */
4001                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4002                 /* Save sp */
4003                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4004                 /* Save method */
4005                 /* FIXME: add a relocation for this */
4006                 if (IS_IMM32 (cfg->method))
4007                         amd64_mov_membase_imm (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), (guint64)cfg->method, 8);
4008                 else {
4009                         amd64_mov_reg_imm (code, AMD64_R11, cfg->method);
4010                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), AMD64_R11, 8);
4011                 }
4012                 /* Save callee saved regs */
4013                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4014                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4015                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4016                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4017                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4018         }
4019
4020         /* Save callee saved registers */
4021         if (cfg->arch.omit_fp && !method->save_lmf) {
4022                 gint32 save_area_offset = 0;
4023
4024                 /* Save caller saved registers after sp is adjusted */
4025                 /* The registers are saved at the bottom of the frame */
4026                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4027                 for (i = 0; i < AMD64_NREG; ++i)
4028                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4029                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4030                                 save_area_offset += 8;
4031                         }
4032         }
4033
4034         /* compute max_offset in order to use short forward jumps */
4035         max_offset = 0;
4036         if (cfg->opt & MONO_OPT_BRANCH) {
4037                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4038                         MonoInst *ins = bb->code;
4039                         bb->max_offset = max_offset;
4040
4041                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4042                                 max_offset += 6;
4043                         /* max alignment for loops */
4044                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4045                                 max_offset += LOOP_ALIGNMENT;
4046
4047                         while (ins) {
4048                                 if (ins->opcode == OP_LABEL)
4049                                         ins->inst_c1 = max_offset;
4050
4051                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
4052                                 ins = ins->next;
4053                         }
4054                 }
4055         }
4056
4057         sig = mono_method_signature (method);
4058         pos = 0;
4059
4060         cinfo = get_call_info (sig, FALSE);
4061
4062         if (sig->ret->type != MONO_TYPE_VOID) {
4063                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4064                         /* Save volatile arguments to the stack */
4065                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4066                 }
4067         }
4068
4069         /* Keep this in sync with emit_load_volatile_arguments */
4070         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4071                 ArgInfo *ainfo = cinfo->args + i;
4072                 gint32 stack_offset;
4073                 MonoType *arg_type;
4074                 inst = cfg->varinfo [i];
4075
4076                 if (sig->hasthis && (i == 0))
4077                         arg_type = &mono_defaults.object_class->byval_arg;
4078                 else
4079                         arg_type = sig->params [i - sig->hasthis];
4080
4081                 stack_offset = ainfo->offset + ARGS_OFFSET;
4082
4083                 /* Save volatile arguments to the stack */
4084                 if (inst->opcode != OP_REGVAR) {
4085                         switch (ainfo->storage) {
4086                         case ArgInIReg: {
4087                                 guint32 size = 8;
4088
4089                                 /* FIXME: I1 etc */
4090                                 /*
4091                                 if (stack_offset & 0x1)
4092                                         size = 1;
4093                                 else if (stack_offset & 0x2)
4094                                         size = 2;
4095                                 else if (stack_offset & 0x4)
4096                                         size = 4;
4097                                 else
4098                                         size = 8;
4099                                 */
4100                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4101                                 break;
4102                         }
4103                         case ArgInFloatSSEReg:
4104                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4105                                 break;
4106                         case ArgInDoubleSSEReg:
4107                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4108                                 break;
4109                         case ArgValuetypeInReg:
4110                                 for (quad = 0; quad < 2; quad ++) {
4111                                         switch (ainfo->pair_storage [quad]) {
4112                                         case ArgInIReg:
4113                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4114                                                 break;
4115                                         case ArgInFloatSSEReg:
4116                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4117                                                 break;
4118                                         case ArgInDoubleSSEReg:
4119                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4120                                                 break;
4121                                         case ArgNone:
4122                                                 break;
4123                                         default:
4124                                                 g_assert_not_reached ();
4125                                         }
4126                                 }
4127                                 break;
4128                         default:
4129                                 break;
4130                         }
4131                 }
4132
4133                 if (inst->opcode == OP_REGVAR) {
4134                         /* Argument allocated to (non-volatile) register */
4135                         switch (ainfo->storage) {
4136                         case ArgInIReg:
4137                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4138                                 break;
4139                         case ArgOnStack:
4140                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4141                                 break;
4142                         default:
4143                                 g_assert_not_reached ();
4144                         }
4145                 }
4146         }
4147
4148         if (method->save_lmf) {
4149                 if (lmf_tls_offset != -1) {
4150                         /* Load lmf quicky using the FS register */
4151                         x86_prefix (code, X86_FS_PREFIX);
4152                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4153                 }
4154                 else {
4155                         /*
4156                          * The call might clobber argument registers, but they are already
4157                          * saved to the stack/global regs.
4158                          */
4159
4160                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4161                                                                  (gpointer)"mono_get_lmf_addr");
4162                 }
4163
4164                 /* Save lmf_addr */
4165                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4166                 /* Save previous_lmf */
4167                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4168                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4169                 /* Set new lmf */
4170                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4171                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4172         }
4173
4174
4175         g_free (cinfo);
4176
4177         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4178                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4179
4180         cfg->code_len = code - cfg->native_code;
4181
4182         g_assert (cfg->code_len < cfg->code_size);
4183
4184         return code;
4185 }
4186
4187 void
4188 mono_arch_emit_epilog (MonoCompile *cfg)
4189 {
4190         MonoMethod *method = cfg->method;
4191         int quad, pos, i;
4192         guint8 *code;
4193         int max_epilog_size = 16;
4194         CallInfo *cinfo;
4195         gint32 lmf_offset = cfg->arch.lmf_offset;
4196
4197         if (cfg->method->save_lmf)
4198                 max_epilog_size += 256;
4199
4200         if (mono_jit_trace_calls != NULL)
4201                 max_epilog_size += 50;
4202
4203         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4204                 max_epilog_size += 50;
4205
4206         max_epilog_size += (AMD64_NREG * 2);
4207
4208         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4209                 cfg->code_size *= 2;
4210                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4211                 mono_jit_stats.code_reallocs++;
4212         }
4213
4214         code = cfg->native_code + cfg->code_len;
4215
4216         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4217                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4218
4219         /* the code restoring the registers must be kept in sync with CEE_JMP */
4220         pos = 0;
4221
4222         if (method->save_lmf) {
4223                 /* Restore previous lmf */
4224                 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4225                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4226                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4227
4228                 /* Restore caller saved regs */
4229                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4230                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4231                 }
4232                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4233                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4234                 }
4235                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4236                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4237                 }
4238                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4239                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4240                 }
4241                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4242                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4243                 }
4244                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4245                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4246                 }
4247         } else {
4248
4249                 if (cfg->arch.omit_fp) {
4250                         gint32 save_area_offset = 0;
4251
4252                         for (i = 0; i < AMD64_NREG; ++i)
4253                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4254                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4255                                         save_area_offset += 8;
4256                                 }
4257                 }
4258                 else {
4259                         for (i = 0; i < AMD64_NREG; ++i)
4260                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4261                                         pos -= sizeof (gpointer);
4262
4263                         if (pos) {
4264                                 if (pos == - sizeof (gpointer)) {
4265                                         /* Only one register, so avoid lea */
4266                                         for (i = AMD64_NREG - 1; i > 0; --i)
4267                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4268                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4269                                                 }
4270                                 }
4271                                 else {
4272                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4273
4274                                         /* Pop registers in reverse order */
4275                                         for (i = AMD64_NREG - 1; i > 0; --i)
4276                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4277                                                         amd64_pop_reg (code, i);
4278                                                 }
4279                                 }
4280                         }
4281                 }
4282         }
4283
4284         /* Load returned vtypes into registers if needed */
4285         cinfo = get_call_info (mono_method_signature (method), FALSE);
4286         if (cinfo->ret.storage == ArgValuetypeInReg) {
4287                 ArgInfo *ainfo = &cinfo->ret;
4288                 MonoInst *inst = cfg->ret;
4289
4290                 for (quad = 0; quad < 2; quad ++) {
4291                         switch (ainfo->pair_storage [quad]) {
4292                         case ArgInIReg:
4293                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4294                                 break;
4295                         case ArgInFloatSSEReg:
4296                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4297                                 break;
4298                         case ArgInDoubleSSEReg:
4299                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4300                                 break;
4301                         case ArgNone:
4302                                 break;
4303                         default:
4304                                 g_assert_not_reached ();
4305                         }
4306                 }
4307         }
4308         g_free (cinfo);
4309
4310         if (cfg->arch.omit_fp) {
4311                 if (cfg->arch.stack_alloc_size)
4312                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4313         } else {
4314                 amd64_leave (code);
4315         }
4316         amd64_ret (code);
4317
4318         cfg->code_len = code - cfg->native_code;
4319
4320         g_assert (cfg->code_len < cfg->code_size);
4321
4322         if (cfg->arch.omit_fp) {
4323                 /*
4324                  * Encode the stack size into used_int_regs so the exception handler
4325                  * can access it.
4326                  */
4327                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4328                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4329         }
4330 }
4331
4332 void
4333 mono_arch_emit_exceptions (MonoCompile *cfg)
4334 {
4335         MonoJumpInfo *patch_info;
4336         int nthrows, i;
4337         guint8 *code;
4338         MonoClass *exc_classes [16];
4339         guint8 *exc_throw_start [16], *exc_throw_end [16];
4340         guint32 code_size = 0;
4341
4342         /* Compute needed space */
4343         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4344                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4345                         code_size += 40;
4346                 if (patch_info->type == MONO_PATCH_INFO_R8)
4347                         code_size += 8 + 7; /* sizeof (double) + alignment */
4348                 if (patch_info->type == MONO_PATCH_INFO_R4)
4349                         code_size += 4 + 7; /* sizeof (float) + alignment */
4350         }
4351
4352         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4353                 cfg->code_size *= 2;
4354                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4355                 mono_jit_stats.code_reallocs++;
4356         }
4357
4358         code = cfg->native_code + cfg->code_len;
4359
4360         /* add code to raise exceptions */
4361         nthrows = 0;
4362         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4363                 switch (patch_info->type) {
4364                 case MONO_PATCH_INFO_EXC: {
4365                         MonoClass *exc_class;
4366                         guint8 *buf, *buf2;
4367                         guint32 throw_ip;
4368
4369                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4370
4371                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4372                         g_assert (exc_class);
4373                         throw_ip = patch_info->ip.i;
4374
4375                         //x86_breakpoint (code);
4376                         /* Find a throw sequence for the same exception class */
4377                         for (i = 0; i < nthrows; ++i)
4378                                 if (exc_classes [i] == exc_class)
4379                                         break;
4380                         if (i < nthrows) {
4381                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4382                                 x86_jump_code (code, exc_throw_start [i]);
4383                                 patch_info->type = MONO_PATCH_INFO_NONE;
4384                         }
4385                         else {
4386                                 buf = code;
4387                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4388                                 buf2 = code;
4389
4390                                 if (nthrows < 16) {
4391                                         exc_classes [nthrows] = exc_class;
4392                                         exc_throw_start [nthrows] = code;
4393                                 }
4394
4395                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4396                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4397                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4398                                 patch_info->ip.i = code - cfg->native_code;
4399
4400                                 if (cfg->compile_aot) {
4401                                         amd64_mov_reg_membase (code, GP_SCRATCH_REG, AMD64_RIP, 0, 8);
4402                                         amd64_call_reg (code, GP_SCRATCH_REG);
4403                                 } else {
4404                                         /* The callee is in memory allocated using the code manager */
4405                                         amd64_call_code (code, 0);
4406                                 }
4407
4408                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4409                                 while (buf < buf2)
4410                                         x86_nop (buf);
4411
4412                                 if (nthrows < 16) {
4413                                         exc_throw_end [nthrows] = code;
4414                                         nthrows ++;
4415                                 }
4416                         }
4417                         break;
4418                 }
4419                 default:
4420                         /* do nothing */
4421                         break;
4422                 }
4423         }
4424
4425         /* Handle relocations with RIP relative addressing */
4426         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4427                 gboolean remove = FALSE;
4428
4429                 switch (patch_info->type) {
4430                 case MONO_PATCH_INFO_R8: {
4431                         guint8 *pos;
4432
4433                         code = (guint8*)ALIGN_TO (code, 8);
4434
4435                         pos = cfg->native_code + patch_info->ip.i;
4436
4437                         *(double*)code = *(double*)patch_info->data.target;
4438
4439                         if (use_sse2)
4440                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4441                         else
4442                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4443                         code += 8;
4444
4445                         remove = TRUE;
4446                         break;
4447                 }
4448                 case MONO_PATCH_INFO_R4: {
4449                         guint8 *pos;
4450
4451                         code = (guint8*)ALIGN_TO (code, 8);
4452
4453                         pos = cfg->native_code + patch_info->ip.i;
4454
4455                         *(float*)code = *(float*)patch_info->data.target;
4456
4457                         if (use_sse2)
4458                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4459                         else
4460                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4461                         code += 4;
4462
4463                         remove = TRUE;
4464                         break;
4465                 }
4466                 default:
4467                         break;
4468                 }
4469
4470                 if (remove) {
4471                         if (patch_info == cfg->patch_info)
4472                                 cfg->patch_info = patch_info->next;
4473                         else {
4474                                 MonoJumpInfo *tmp;
4475
4476                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4477                                         ;
4478                                 tmp->next = patch_info->next;
4479                         }
4480                 }
4481         }
4482
4483         cfg->code_len = code - cfg->native_code;
4484
4485         g_assert (cfg->code_len < cfg->code_size);
4486
4487 }
4488
4489 void*
4490 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4491 {
4492         guchar *code = p;
4493         CallInfo *cinfo = NULL;
4494         MonoMethodSignature *sig;
4495         MonoInst *inst;
4496         int i, n, stack_area = 0;
4497
4498         /* Keep this in sync with mono_arch_get_argument_info */
4499
4500         if (enable_arguments) {
4501                 /* Allocate a new area on the stack and save arguments there */
4502                 sig = mono_method_signature (cfg->method);
4503
4504                 cinfo = get_call_info (sig, FALSE);
4505
4506                 n = sig->param_count + sig->hasthis;
4507
4508                 stack_area = ALIGN_TO (n * 8, 16);
4509
4510                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4511
4512                 for (i = 0; i < n; ++i) {
4513                         inst = cfg->varinfo [i];
4514
4515                         if (inst->opcode == OP_REGVAR)
4516                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4517                         else {
4518                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4519                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4520                         }
4521                 }
4522         }
4523
4524         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4525         amd64_set_reg_template (code, AMD64_RDI);
4526         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4527         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4528
4529         if (enable_arguments) {
4530                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4531
4532                 g_free (cinfo);
4533         }
4534
4535         return code;
4536 }
4537
4538 enum {
4539         SAVE_NONE,
4540         SAVE_STRUCT,
4541         SAVE_EAX,
4542         SAVE_EAX_EDX,
4543         SAVE_XMM
4544 };
4545
4546 void*
4547 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4548 {
4549         guchar *code = p;
4550         int save_mode = SAVE_NONE;
4551         MonoMethod *method = cfg->method;
4552         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4553
4554         switch (rtype) {
4555         case MONO_TYPE_VOID:
4556                 /* special case string .ctor icall */
4557                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4558                         save_mode = SAVE_EAX;
4559                 else
4560                         save_mode = SAVE_NONE;
4561                 break;
4562         case MONO_TYPE_I8:
4563         case MONO_TYPE_U8:
4564                 save_mode = SAVE_EAX;
4565                 break;
4566         case MONO_TYPE_R4:
4567         case MONO_TYPE_R8:
4568                 save_mode = SAVE_XMM;
4569                 break;
4570         case MONO_TYPE_VALUETYPE:
4571                 save_mode = SAVE_STRUCT;
4572                 break;
4573         default:
4574                 save_mode = SAVE_EAX;
4575                 break;
4576         }
4577
4578         /* Save the result and copy it into the proper argument register */
4579         switch (save_mode) {
4580         case SAVE_EAX:
4581                 amd64_push_reg (code, AMD64_RAX);
4582                 /* Align stack */
4583                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4584                 if (enable_arguments)
4585                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4586                 break;
4587         case SAVE_STRUCT:
4588                 /* FIXME: */
4589                 if (enable_arguments)
4590                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4591                 break;
4592         case SAVE_XMM:
4593                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4594                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4595                 /* Align stack */
4596                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4597                 /*
4598                  * The result is already in the proper argument register so no copying
4599                  * needed.
4600                  */
4601                 break;
4602         case SAVE_NONE:
4603                 break;
4604         default:
4605                 g_assert_not_reached ();
4606         }
4607
4608         /* Set %al since this is a varargs call */
4609         if (save_mode == SAVE_XMM)
4610                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4611         else
4612                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4613
4614         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4615         amd64_set_reg_template (code, AMD64_RDI);
4616         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4617
4618         /* Restore result */
4619         switch (save_mode) {
4620         case SAVE_EAX:
4621                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4622                 amd64_pop_reg (code, AMD64_RAX);
4623                 break;
4624         case SAVE_STRUCT:
4625                 /* FIXME: */
4626                 break;
4627         case SAVE_XMM:
4628                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4629                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4630                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4631                 break;
4632         case SAVE_NONE:
4633                 break;
4634         default:
4635                 g_assert_not_reached ();
4636         }
4637
4638         return code;
4639 }
4640
4641 void
4642 mono_arch_flush_icache (guint8 *code, gint size)
4643 {
4644         /* Not needed */
4645 }
4646
4647 void
4648 mono_arch_flush_register_windows (void)
4649 {
4650 }
4651
4652 gboolean
4653 mono_arch_is_inst_imm (gint64 imm)
4654 {
4655         return amd64_is_imm32 (imm);
4656 }
4657
4658 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4659
4660 static int reg_to_ucontext_reg [] = {
4661         REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
4662         REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
4663         REG_RIP
4664 };
4665
4666 /*
4667  * Determine whenever the trap whose info is in SIGINFO is caused by
4668  * integer overflow.
4669  */
4670 gboolean
4671 mono_arch_is_int_overflow (void *sigctx, void *info)
4672 {
4673         ucontext_t *ctx = (ucontext_t*)sigctx;
4674         guint8* rip;
4675         int reg;
4676
4677         rip = (guint8*)ctx->uc_mcontext.gregs [REG_RIP];
4678
4679         if (IS_REX (rip [0])) {
4680                 reg = amd64_rex_b (rip [0]);
4681                 rip ++;
4682         }
4683         else
4684                 reg = 0;
4685
4686         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4687                 /* idiv REG */
4688                 reg += x86_modrm_rm (rip [1]);
4689
4690                 if (ctx->uc_mcontext.gregs [reg_to_ucontext_reg [reg]] == -1)
4691                         return TRUE;
4692         }
4693
4694         return FALSE;
4695 }
4696
4697 guint32
4698 mono_arch_get_patch_offset (guint8 *code)
4699 {
4700         return 3;
4701 }
4702
4703 gpointer*
4704 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4705 {
4706         guint32 reg;
4707         guint32 disp;
4708         guint8 rex = 0;
4709
4710         /* go to the start of the call instruction
4711          *
4712          * address_byte = (m << 6) | (o << 3) | reg
4713          * call opcode: 0xff address_byte displacement
4714          * 0xff m=1,o=2 imm8
4715          * 0xff m=2,o=2 imm32
4716          */
4717         code -= 7;
4718
4719         /*
4720          * A given byte sequence can match more than case here, so we have to be
4721          * really careful about the ordering of the cases. Longer sequences
4722          * come first.
4723          */
4724         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4725                 /* call OFFSET(%rip) */
4726                 disp = *(guint32*)(code + 3);
4727                 return (gpointer*)(code + disp + 7);
4728         }
4729         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4730                 /* call *[reg+disp32] */
4731                 if (IS_REX (code [0]))
4732                         rex = code [0];
4733                 reg = amd64_modrm_rm (code [2]);
4734                 disp = *(guint32*)(code + 3);
4735                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4736         }
4737         else if (code [2] == 0xe8) {
4738                 /* call <ADDR> */
4739                 return NULL;
4740         }
4741         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4742                 /* call *%reg */
4743                 return NULL;
4744         }
4745         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4746                 /* call *[reg+disp8] */
4747                 if (IS_REX (code [3]))
4748                         rex = code [3];
4749                 reg = amd64_modrm_rm (code [5]);
4750                 disp = *(guint8*)(code + 6);
4751                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4752         }
4753         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4754                         /*
4755                          * This is a interface call: should check the above code can't catch it earlier
4756                          * 8b 40 30   mov    0x30(%eax),%eax
4757                          * ff 10      call   *(%eax)
4758                          */
4759                 if (IS_REX (code [4]))
4760                         rex = code [4];
4761                 reg = amd64_modrm_rm (code [6]);
4762                 disp = 0;
4763         }
4764         else
4765                 g_assert_not_reached ();
4766
4767         reg += amd64_rex_b (rex);
4768
4769         /* R11 is clobbered by the trampoline code */
4770         g_assert (reg != AMD64_R11);
4771
4772         return (gpointer)(((guint64)(regs [reg])) + disp);
4773 }
4774
4775 gpointer*
4776 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4777 {
4778         guint32 reg;
4779         guint32 disp;
4780
4781         code -= 10;
4782
4783         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
4784                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
4785                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
4786                 disp = code [6];
4787
4788                 if (reg == AMD64_RAX)
4789                         return NULL;
4790                 else
4791                         return (gpointer*)(((guint64)(regs [reg])) + disp);
4792         }
4793
4794         return NULL;
4795 }
4796
4797 /*
4798  * Support for fast access to the thread-local lmf structure using the GS
4799  * segment register on NPTL + kernel 2.6.x.
4800  */
4801
4802 static gboolean tls_offset_inited = FALSE;
4803
4804 void
4805 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4806 {
4807         if (!tls_offset_inited) {
4808                 tls_offset_inited = TRUE;
4809
4810                 appdomain_tls_offset = mono_domain_get_tls_offset ();
4811                 lmf_tls_offset = mono_get_lmf_tls_offset ();
4812                 thread_tls_offset = mono_thread_get_tls_offset ();
4813         }
4814 }
4815
4816 void
4817 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4818 {
4819 }
4820
4821 void
4822 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
4823 {
4824         MonoCallInst *call = (MonoCallInst*)inst;
4825         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
4826
4827         if (vt_reg != -1) {
4828                 MonoInst *vtarg;
4829
4830                 if (cinfo->ret.storage == ArgValuetypeInReg) {
4831                         /*
4832                          * The valuetype is in RAX:RDX after the call, need to be copied to
4833                          * the stack. Push the address here, so the call instruction can
4834                          * access it.
4835                          */
4836                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
4837                         vtarg->sreg1 = vt_reg;
4838                         mono_bblock_add_inst (cfg->cbb, vtarg);
4839
4840                         /* Align stack */
4841                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
4842                 }
4843                 else {
4844                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
4845                         vtarg->sreg1 = vt_reg;
4846                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
4847                         mono_bblock_add_inst (cfg->cbb, vtarg);
4848
4849                         mono_call_inst_add_outarg_reg (call, vtarg->dreg, cinfo->ret.reg, FALSE);
4850                 }
4851         }
4852
4853         /* add the this argument */
4854         if (this_reg != -1) {
4855                 MonoInst *this;
4856                 MONO_INST_NEW (cfg, this, OP_MOVE);
4857                 this->type = this_type;
4858                 this->sreg1 = this_reg;
4859                 this->dreg = mono_regstate_next_int (cfg->rs);
4860                 mono_bblock_add_inst (cfg->cbb, this);
4861
4862                 mono_call_inst_add_outarg_reg (call, this->dreg, cinfo->args [0].reg, FALSE);
4863         }
4864
4865         g_free (cinfo);
4866 }
4867
4868 MonoInst*
4869 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4870 {
4871         MonoInst *ins = NULL;
4872
4873         if (cmethod->klass == mono_defaults.math_class) {
4874                 if (strcmp (cmethod->name, "Sin") == 0) {
4875                         MONO_INST_NEW (cfg, ins, OP_SIN);
4876                         ins->inst_i0 = args [0];
4877                 } else if (strcmp (cmethod->name, "Cos") == 0) {
4878                         MONO_INST_NEW (cfg, ins, OP_COS);
4879                         ins->inst_i0 = args [0];
4880                 } else if (strcmp (cmethod->name, "Tan") == 0) {
4881                         if (use_sse2)
4882                                 return ins;
4883                         MONO_INST_NEW (cfg, ins, OP_TAN);
4884                         ins->inst_i0 = args [0];
4885                 } else if (strcmp (cmethod->name, "Atan") == 0) {
4886                         if (use_sse2)
4887                                 return ins;
4888                         MONO_INST_NEW (cfg, ins, OP_ATAN);
4889                         ins->inst_i0 = args [0];
4890                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
4891                         MONO_INST_NEW (cfg, ins, OP_SQRT);
4892                         ins->inst_i0 = args [0];
4893                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
4894                         MONO_INST_NEW (cfg, ins, OP_ABS);
4895                         ins->inst_i0 = args [0];
4896                 }
4897 #if 0
4898                 /* OP_FREM is not IEEE compatible */
4899                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
4900                         MONO_INST_NEW (cfg, ins, OP_FREM);
4901                         ins->inst_i0 = args [0];
4902                         ins->inst_i1 = args [1];
4903                 }
4904 #endif
4905         } else if (cmethod->klass == mono_defaults.thread_class &&
4906                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
4907                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
4908         } else if(cmethod->klass->image == mono_defaults.corlib &&
4909                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4910                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4911
4912                 if (strcmp (cmethod->name, "Increment") == 0) {
4913                         MonoInst *ins_iconst;
4914                         guint32 opcode;
4915
4916                         if (fsig->params [0]->type == MONO_TYPE_I4)
4917                                 opcode = OP_ATOMIC_ADD_NEW_I4;
4918                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4919                                 opcode = OP_ATOMIC_ADD_NEW_I8;
4920                         else
4921                                 g_assert_not_reached ();
4922                         MONO_INST_NEW (cfg, ins, opcode);
4923                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
4924                         ins_iconst->inst_c0 = 1;
4925
4926                         ins->inst_i0 = args [0];
4927                         ins->inst_i1 = ins_iconst;
4928                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4929                         MonoInst *ins_iconst;
4930                         guint32 opcode;
4931
4932                         if (fsig->params [0]->type == MONO_TYPE_I4)
4933                                 opcode = OP_ATOMIC_ADD_NEW_I4;
4934                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4935                                 opcode = OP_ATOMIC_ADD_NEW_I8;
4936                         else
4937                                 g_assert_not_reached ();
4938                         MONO_INST_NEW (cfg, ins, opcode);
4939                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
4940                         ins_iconst->inst_c0 = -1;
4941
4942                         ins->inst_i0 = args [0];
4943                         ins->inst_i1 = ins_iconst;
4944                 } else if (strcmp (cmethod->name, "Add") == 0) {
4945                         guint32 opcode;
4946
4947                         if (fsig->params [0]->type == MONO_TYPE_I4)
4948                                 opcode = OP_ATOMIC_ADD_I4;
4949                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4950                                 opcode = OP_ATOMIC_ADD_I8;
4951                         else
4952                                 g_assert_not_reached ();
4953
4954                         MONO_INST_NEW (cfg, ins, opcode);
4955
4956                         ins->inst_i0 = args [0];
4957                         ins->inst_i1 = args [1];
4958                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
4959                         guint32 opcode;
4960
4961                         if (fsig->params [0]->type == MONO_TYPE_I4)
4962                                 opcode = OP_ATOMIC_EXCHANGE_I4;
4963                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
4964                                          (fsig->params [0]->type == MONO_TYPE_I) ||
4965                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
4966                                 opcode = OP_ATOMIC_EXCHANGE_I8;
4967                         else
4968                                 return NULL;
4969
4970                         MONO_INST_NEW (cfg, ins, opcode);
4971
4972                         ins->inst_i0 = args [0];
4973                         ins->inst_i1 = args [1];
4974                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
4975                         /* 64 bit reads are already atomic */
4976                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
4977                         ins->inst_i0 = args [0];
4978                 }
4979
4980                 /*
4981                  * Can't implement CompareExchange methods this way since they have
4982                  * three arguments.
4983                  */
4984         }
4985
4986         return ins;
4987 }
4988
4989 gboolean
4990 mono_arch_print_tree (MonoInst *tree, int arity)
4991 {
4992         return 0;
4993 }
4994
4995 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4996 {
4997         MonoInst* ins;
4998
4999         if (appdomain_tls_offset == -1)
5000                 return NULL;
5001
5002         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5003         ins->inst_offset = appdomain_tls_offset;
5004         return ins;
5005 }
5006
5007 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5008 {
5009         MonoInst* ins;
5010
5011         if (thread_tls_offset == -1)
5012                 return NULL;
5013
5014         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5015         ins->inst_offset = thread_tls_offset;
5016         return ins;
5017 }