mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef HOST_WIN32
  44 static gint jit_tls_offset = -1;
  45 #endif
  46
  47 #ifdef MONO_XEN_OPT
  48 static gboolean optimize_for_xen = TRUE;
  49 #else
  50 #define optimize_for_xen 0
  51 #endif
  52
  53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  54
  55 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  56
  57 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  58
  59 #ifdef HOST_WIN32
  60 /* Under windows, the calling convention is never stdcall */
  61 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  62 #else
  63 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  64 #endif
  65
  66 /* This mutex protects architecture specific caches */
  67 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  68 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  69 static CRITICAL_SECTION mini_arch_mutex;
  70
  71 MonoBreakpointInfo
  72 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  73
  74 /* Structure used by the sequence points in AOTed code */
  75 typedef struct {
  76         gpointer ss_trigger_page;
  77         gpointer bp_trigger_page;
  78         gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
  79 } SeqPointInfo;
  80
  81 /*
  82  * The code generated for sequence points reads from this location, which is
  83  * made read-only when single stepping is enabled.
  84  */
  85 static gpointer ss_trigger_page;
  86
  87 /* Enabled breakpoints read from this trigger page */
  88 static gpointer bp_trigger_page;
  89
  90 /* The size of the breakpoint sequence */
  91 static int breakpoint_size;
  92
  93 /* The size of the breakpoint instruction causing the actual fault */
  94 static int breakpoint_fault_size;
  95
  96 /* The size of the single step instruction causing the actual fault */
  97 static int single_step_fault_size;
  98
  99 #ifdef HOST_WIN32
 100 /* On Win64 always reserve first 32 bytes for first four arguments */
 101 #define ARGS_OFFSET 48
 102 #else
 103 #define ARGS_OFFSET 16
 104 #endif
 105 #define GP_SCRATCH_REG AMD64_R11
 106
 107 /*
 108  * AMD64 register usage:
 109  * - callee saved registers are used for global register allocation
 110  * - %r11 is used for materializing 64 bit constants in opcodes
 111  * - the rest is used for local allocation
 112  */
 113
 114 /*
 115  * Floating point comparison results:
 116  *                  ZF PF CF
 117  * A > B            0  0  0
 118  * A < B            0  0  1
 119  * A = B            1  0  0
 120  * A > B            0  0  0
 121  * UNORDERED        1  1  1
 122  */
 123
 124 const char*
 125 mono_arch_regname (int reg)
 126 {
 127         switch (reg) {
 128         case AMD64_RAX: return "%rax";
 129         case AMD64_RBX: return "%rbx";
 130         case AMD64_RCX: return "%rcx";
 131         case AMD64_RDX: return "%rdx";
 132         case AMD64_RSP: return "%rsp";
 133         case AMD64_RBP: return "%rbp";
 134         case AMD64_RDI: return "%rdi";
 135         case AMD64_RSI: return "%rsi";
 136         case AMD64_R8: return "%r8";
 137         case AMD64_R9: return "%r9";
 138         case AMD64_R10: return "%r10";
 139         case AMD64_R11: return "%r11";
 140         case AMD64_R12: return "%r12";
 141         case AMD64_R13: return "%r13";
 142         case AMD64_R14: return "%r14";
 143         case AMD64_R15: return "%r15";
 144         }
 145         return "unknown";
 146 }
 147
 148 static const char * packed_xmmregs [] = {
 149         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 150         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 151 };
 152
 153 static const char * single_xmmregs [] = {
 154         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 155         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 156 };
 157
 158 const char*
 159 mono_arch_fregname (int reg)
 160 {
 161         if (reg < AMD64_XMM_NREG)
 162                 return single_xmmregs [reg];
 163         else
 164                 return "unknown";
 165 }
 166
 167 const char *
 168 mono_arch_xregname (int reg)
 169 {
 170         if (reg < AMD64_XMM_NREG)
 171                 return packed_xmmregs [reg];
 172         else
 173                 return "unknown";
 174 }
 175
 176 static gboolean
 177 debug_omit_fp (void)
 178 {
 179 #if 0
 180         return mono_debug_count ();
 181 #else
 182         return TRUE;
 183 #endif
 184 }
 185
 186 static inline gboolean
 187 amd64_is_near_call (guint8 *code)
 188 {
 189         /* Skip REX */
 190         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 191                 code += 1;
 192
 193         return code [0] == 0xe8;
 194 }
 195
 196 #ifdef __native_client_codegen__
 197
 198 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 199 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 200 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 201 /* We only want to force bundle alignment for the top level instruction,    */
 202 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 203 static MonoNativeTlsKey nacl_instruction_depth;
 204
 205 static MonoNativeTlsKey nacl_rex_tag;
 206 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 207
 208 void
 209 amd64_nacl_clear_legacy_prefix_tag ()
 210 {
 211         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 212 }
 213
 214 void
 215 amd64_nacl_tag_legacy_prefix (guint8* code)
 216 {
 217         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 218                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 219 }
 220
 221 void
 222 amd64_nacl_tag_rex (guint8* code)
 223 {
 224         mono_native_tls_set_value (nacl_rex_tag, code);
 225 }
 226
 227 guint8*
 228 amd64_nacl_get_legacy_prefix_tag ()
 229 {
 230         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 231 }
 232
 233 guint8*
 234 amd64_nacl_get_rex_tag ()
 235 {
 236         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 237 }
 238
 239 /* Increment the instruction "depth" described above */
 240 void
 241 amd64_nacl_instruction_pre ()
 242 {
 243         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 244         depth++;
 245         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 246 }
 247
 248 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 249 /* alignment if depth == 0 (top level instruction)                          */
 250 /* IN: start, end    pointers to instruction beginning and end              */
 251 /* OUT: start, end   pointers to beginning and end after possible alignment */
 252 /* GLOBALS: nacl_instruction_depth     defined above                        */
 253 void
 254 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 255 {
 256         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 257         depth--;
 258         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 259
 260         g_assert ( depth >= 0 );
 261         if (depth == 0) {
 262                 uintptr_t space_in_block;
 263                 uintptr_t instlen;
 264                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 265                 /* if legacy prefix is present, and if it was emitted before */
 266                 /* the start of the instruction sequence, adjust the start   */
 267                 if (prefix != NULL && prefix < *start) {
 268                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 269                         *start = prefix;
 270                 }
 271                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 272                 instlen = (uintptr_t)(*end - *start);
 273                 /* Only check for instructions which are less than        */
 274                 /* kNaClAlignment. The only instructions that should ever */
 275                 /* be that long are call sequences, which are already     */
 276                 /* padded out to align the return to the next bundle.     */
 277                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 278                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 279                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 280                         const size_t length = (size_t)((*end)-(*start));
 281                         g_assert (length < MAX_NACL_INST_LENGTH);
 282
 283                         memcpy (copy_of_instruction, *start, length);
 284                         *start = mono_arch_nacl_pad (*start, space_in_block);
 285                         memcpy (*start, copy_of_instruction, length);
 286                         *end = *start + length;
 287                 }
 288                 amd64_nacl_clear_legacy_prefix_tag ();
 289                 amd64_nacl_tag_rex (NULL);
 290         }
 291 }
 292
 293 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 294 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 295 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 296 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 297 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 298 /* IN:      code                                                            */
 299 /*             pointer to current instruction stream (in the                */
 300 /*             middle of an instruction, after opcode is emitted)           */
 301 /*          basereg/offset/dreg                                             */
 302 /*             operands of normal membase address                           */
 303 /* OUT:     code                                                            */
 304 /*             pointer to the end of the membase/memindex emit              */
 305 /* GLOBALS: nacl_rex_tag                                                    */
 306 /*             position in instruction stream that rex prefix was emitted   */
 307 /*          nacl_legacy_prefix_tag                                          */
 308 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 309 void
 310 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 311 {
 312         gint8 true_basereg = basereg;
 313
 314         /* Cache these values, they might change  */
 315         /* as new instructions are emitted below. */
 316         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 317         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 318
 319         /* 'basereg' is given masked to 0x7 at this point, so check */
 320         /* the rex prefix to see if this is an extended register.   */
 321         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 322                 true_basereg |= 0x8;
 323         }
 324
 325 #define X86_LEA_OPCODE (0x8D)
 326
 327         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 328                 guint8* old_instruction_start;
 329
 330                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 331                 /* 32-bits of the old base register (new index register)     */
 332                 guint8 buf[32];
 333                 guint8* buf_ptr = buf;
 334                 size_t insert_len;
 335
 336                 g_assert (rex_tag != NULL);
 337
 338                 if (IS_REX(*rex_tag)) {
 339                         /* The old rex.B should be the new rex.X */
 340                         if (*rex_tag & AMD64_REX_B) {
 341                                 *rex_tag |= AMD64_REX_X;
 342                         }
 343                         /* Since our new base is %r15 set rex.B */
 344                         *rex_tag |= AMD64_REX_B;
 345                 } else {
 346                         /* Shift the instruction by one byte  */
 347                         /* so we can insert a rex prefix      */
 348                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 349                         *code += 1;
 350                         /* New rex prefix only needs rex.B for %r15 base */
 351                         *rex_tag = AMD64_REX(AMD64_REX_B);
 352                 }
 353
 354                 if (legacy_prefix_tag) {
 355                         old_instruction_start = legacy_prefix_tag;
 356                 } else {
 357                         old_instruction_start = rex_tag;
 358                 }
 359
 360                 /* Clears the upper 32-bits of the previous base register */
 361                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 362                 insert_len = buf_ptr - buf;
 363
 364                 /* Move the old instruction forward to make */
 365                 /* room for 'mov' stored in 'buf_ptr'       */
 366                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 367                 *code += insert_len;
 368                 memcpy (old_instruction_start, buf, insert_len);
 369
 370                 /* Sandboxed replacement for the normal membase_emit */
 371                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 372
 373         } else {
 374                 /* Normal default behavior, emit membase memory location */
 375                 x86_membase_emit_body (*code, dreg, basereg, offset);
 376         }
 377 }
 378
 379
 380 static inline unsigned char*
 381 amd64_skip_nops (unsigned char* code)
 382 {
 383         guint8 in_nop;
 384         do {
 385                 in_nop = 0;
 386                 if (   code[0] == 0x90) {
 387                         in_nop = 1;
 388                         code += 1;
 389                 }
 390                 if (   code[0] == 0x66 && code[1] == 0x90) {
 391                         in_nop = 1;
 392                         code += 2;
 393                 }
 394                 if (code[0] == 0x0f && code[1] == 0x1f
 395                  && code[2] == 0x00) {
 396                         in_nop = 1;
 397                         code += 3;
 398                 }
 399                 if (code[0] == 0x0f && code[1] == 0x1f
 400                  && code[2] == 0x40 && code[3] == 0x00) {
 401                         in_nop = 1;
 402                         code += 4;
 403                 }
 404                 if (code[0] == 0x0f && code[1] == 0x1f
 405                  && code[2] == 0x44 && code[3] == 0x00
 406                  && code[4] == 0x00) {
 407                         in_nop = 1;
 408                         code += 5;
 409                 }
 410                 if (code[0] == 0x66 && code[1] == 0x0f
 411                  && code[2] == 0x1f && code[3] == 0x44
 412                  && code[4] == 0x00 && code[5] == 0x00) {
 413                         in_nop = 1;
 414                         code += 6;
 415                 }
 416                 if (code[0] == 0x0f && code[1] == 0x1f
 417                  && code[2] == 0x80 && code[3] == 0x00
 418                  && code[4] == 0x00 && code[5] == 0x00
 419                  && code[6] == 0x00) {
 420                         in_nop = 1;
 421                         code += 7;
 422                 }
 423                 if (code[0] == 0x0f && code[1] == 0x1f
 424                  && code[2] == 0x84 && code[3] == 0x00
 425                  && code[4] == 0x00 && code[5] == 0x00
 426                  && code[6] == 0x00 && code[7] == 0x00) {
 427                         in_nop = 1;
 428                         code += 8;
 429                 }
 430         } while ( in_nop );
 431         return code;
 432 }
 433
 434 guint8*
 435 mono_arch_nacl_skip_nops (guint8* code)
 436 {
 437   return amd64_skip_nops(code);
 438 }
 439
 440 #endif /*__native_client_codegen__*/
 441
 442 static inline void
 443 amd64_patch (unsigned char* code, gpointer target)
 444 {
 445         guint8 rex = 0;
 446
 447 #ifdef __native_client_codegen__
 448         code = amd64_skip_nops (code);
 449 #endif
 450 #if defined(__native_client_codegen__) && defined(__native_client__)
 451         if (nacl_is_code_address (code)) {
 452                 /* For tail calls, code is patched after being installed */
 453                 /* but not through the normal "patch callsite" method.   */
 454                 unsigned char buf[kNaClAlignment];
 455                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 456                 int ret;
 457                 memcpy (buf, aligned_code, kNaClAlignment);
 458                 /* Patch a temp buffer of bundle size, */
 459                 /* then install to actual location.    */
 460                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 461                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 462                 g_assert (ret == 0);
 463                 return;
 464         }
 465         target = nacl_modify_patch_target (target);
 466 #endif
 467
 468         /* Skip REX */
 469         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 470                 rex = code [0];
 471                 code += 1;
 472         }
 473
 474         if ((code [0] & 0xf8) == 0xb8) {
 475                 /* amd64_set_reg_template */
 476                 *(guint64*)(code + 1) = (guint64)target;
 477         }
 478         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 479                 /* mov 0(%rip), %dreg */
 480                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 481         }
 482         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 483                 /* call *<OFFSET>(%rip) */
 484                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 485         }
 486         else if (code [0] == 0xe8) {
 487                 /* call <DISP> */
 488                 gint64 disp = (guint8*)target - (guint8*)code;
 489                 g_assert (amd64_is_imm32 (disp));
 490                 x86_patch (code, (unsigned char*)target);
 491         }
 492         else
 493                 x86_patch (code, (unsigned char*)target);
 494 }
 495
 496 void
 497 mono_amd64_patch (unsigned char* code, gpointer target)
 498 {
 499         amd64_patch (code, target);
 500 }
 501
 502 typedef enum {
 503         ArgInIReg,
 504         ArgInFloatSSEReg,
 505         ArgInDoubleSSEReg,
 506         ArgOnStack,
 507         ArgValuetypeInReg,
 508         ArgValuetypeAddrInIReg,
 509         ArgNone /* only in pair_storage */
 510 } ArgStorage;
 511
 512 typedef struct {
 513         gint16 offset;
 514         gint8  reg;
 515         ArgStorage storage;
 516
 517         /* Only if storage == ArgValuetypeInReg */
 518         ArgStorage pair_storage [2];
 519         gint8 pair_regs [2];
 520         int nregs;
 521 } ArgInfo;
 522
 523 typedef struct {
 524         int nargs;
 525         guint32 stack_usage;
 526         guint32 reg_usage;
 527         guint32 freg_usage;
 528         gboolean need_stack_align;
 529         gboolean vtype_retaddr;
 530         /* The index of the vret arg in the argument list */
 531         int vret_arg_index;
 532         ArgInfo ret;
 533         ArgInfo sig_cookie;
 534         ArgInfo args [1];
 535 } CallInfo;
 536
 537 #define DEBUG(a) if (cfg->verbose_level > 1) a
 538
 539 #ifdef HOST_WIN32
 540 #define PARAM_REGS 4
 541
 542 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 543
 544 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 545 #else
 546 #define PARAM_REGS 6
 547
 548 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 549
 550  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 551 #endif
 552
 553 static void inline
 554 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 555 {
 556     ainfo->offset = *stack_size;
 557
 558     if (*gr >= PARAM_REGS) {
 559                 ainfo->storage = ArgOnStack;
 560                 /* Since the same stack slot size is used for all arg */
 561                 /*  types, it needs to be big enough to hold them all */
 562                 (*stack_size) += sizeof(mgreg_t);
 563     }
 564     else {
 565                 ainfo->storage = ArgInIReg;
 566                 ainfo->reg = param_regs [*gr];
 567                 (*gr) ++;
 568     }
 569 }
 570
 571 #ifdef HOST_WIN32
 572 #define FLOAT_PARAM_REGS 4
 573 #else
 574 #define FLOAT_PARAM_REGS 8
 575 #endif
 576
 577 static void inline
 578 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 579 {
 580     ainfo->offset = *stack_size;
 581
 582     if (*gr >= FLOAT_PARAM_REGS) {
 583                 ainfo->storage = ArgOnStack;
 584                 /* Since the same stack slot size is used for both float */
 585                 /*  types, it needs to be big enough to hold them both */
 586                 (*stack_size) += sizeof(mgreg_t);
 587     }
 588     else {
 589                 /* A double register */
 590                 if (is_double)
 591                         ainfo->storage = ArgInDoubleSSEReg;
 592                 else
 593                         ainfo->storage = ArgInFloatSSEReg;
 594                 ainfo->reg = *gr;
 595                 (*gr) += 1;
 596     }
 597 }
 598
 599 typedef enum ArgumentClass {
 600         ARG_CLASS_NO_CLASS,
 601         ARG_CLASS_MEMORY,
 602         ARG_CLASS_INTEGER,
 603         ARG_CLASS_SSE
 604 } ArgumentClass;
 605
 606 static ArgumentClass
 607 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 608 {
 609         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 610         MonoType *ptype;
 611
 612         ptype = mini_type_get_underlying_type (gsctx, type);
 613         switch (ptype->type) {
 614         case MONO_TYPE_BOOLEAN:
 615         case MONO_TYPE_CHAR:
 616         case MONO_TYPE_I1:
 617         case MONO_TYPE_U1:
 618         case MONO_TYPE_I2:
 619         case MONO_TYPE_U2:
 620         case MONO_TYPE_I4:
 621         case MONO_TYPE_U4:
 622         case MONO_TYPE_I:
 623         case MONO_TYPE_U:
 624         case MONO_TYPE_STRING:
 625         case MONO_TYPE_OBJECT:
 626         case MONO_TYPE_CLASS:
 627         case MONO_TYPE_SZARRAY:
 628         case MONO_TYPE_PTR:
 629         case MONO_TYPE_FNPTR:
 630         case MONO_TYPE_ARRAY:
 631         case MONO_TYPE_I8:
 632         case MONO_TYPE_U8:
 633                 class2 = ARG_CLASS_INTEGER;
 634                 break;
 635         case MONO_TYPE_R4:
 636         case MONO_TYPE_R8:
 637 #ifdef HOST_WIN32
 638                 class2 = ARG_CLASS_INTEGER;
 639 #else
 640                 class2 = ARG_CLASS_SSE;
 641 #endif
 642                 break;
 643
 644         case MONO_TYPE_TYPEDBYREF:
 645                 g_assert_not_reached ();
 646
 647         case MONO_TYPE_GENERICINST:
 648                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 649                         class2 = ARG_CLASS_INTEGER;
 650                         break;
 651                 }
 652                 /* fall through */
 653         case MONO_TYPE_VALUETYPE: {
 654                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 655                 int i;
 656
 657                 for (i = 0; i < info->num_fields; ++i) {
 658                         class2 = class1;
 659                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 660                 }
 661                 break;
 662         }
 663         default:
 664                 g_assert_not_reached ();
 665         }
 666
 667         /* Merge */
 668         if (class1 == class2)
 669                 ;
 670         else if (class1 == ARG_CLASS_NO_CLASS)
 671                 class1 = class2;
 672         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 673                 class1 = ARG_CLASS_MEMORY;
 674         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 675                 class1 = ARG_CLASS_INTEGER;
 676         else
 677                 class1 = ARG_CLASS_SSE;
 678
 679         return class1;
 680 }
 681 #ifdef __native_client_codegen__
 682
 683 /* Default alignment for Native Client is 32-byte. */
 684 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 685
 686 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 687 /* Check that alignment doesn't cross an alignment boundary.             */
 688 guint8*
 689 mono_arch_nacl_pad(guint8 *code, int pad)
 690 {
 691         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 692
 693         if (pad == 0) return code;
 694         /* assertion: alignment cannot cross a block boundary */
 695         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 696                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 697         while (pad >= kMaxPadding) {
 698                 amd64_padding (code, kMaxPadding);
 699                 pad -= kMaxPadding;
 700         }
 701         if (pad != 0) amd64_padding (code, pad);
 702         return code;
 703 }
 704 #endif
 705
 706 static void
 707 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 708                            gboolean is_return,
 709                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 710 {
 711         guint32 size, quad, nquads, i;
 712         /* Keep track of the size used in each quad so we can */
 713         /* use the right size when copying args/return vars.  */
 714         guint32 quadsize [2] = {8, 8};
 715         ArgumentClass args [2];
 716         MonoMarshalType *info = NULL;
 717         MonoClass *klass;
 718         MonoGenericSharingContext tmp_gsctx;
 719         gboolean pass_on_stack = FALSE;
 720
 721         /*
 722          * The gsctx currently contains no data, it is only used for checking whenever
 723          * open types are allowed, some callers like mono_arch_get_argument_info ()
 724          * don't pass it to us, so work around that.
 725          */
 726         if (!gsctx)
 727                 gsctx = &tmp_gsctx;
 728
 729         klass = mono_class_from_mono_type (type);
 730         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 731 #ifndef HOST_WIN32
 732         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 733                 /* We pass and return vtypes of size 8 in a register */
 734         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 735                 pass_on_stack = TRUE;
 736         }
 737 #else
 738         if (!sig->pinvoke) {
 739                 pass_on_stack = TRUE;
 740         }
 741 #endif
 742
 743         /* If this struct can't be split up naturally into 8-byte */
 744         /* chunks (registers), pass it on the stack.              */
 745         if (sig->pinvoke && !pass_on_stack) {
 746                 guint32 align;
 747                 guint32 field_size;
 748
 749                 info = mono_marshal_load_type_info (klass);
 750                 g_assert(info);
 751                 for (i = 0; i < info->num_fields; ++i) {
 752                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 753                                                            info->fields [i].mspec,
 754                                                            &align, TRUE, klass->unicode);
 755                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 756                                 pass_on_stack = TRUE;
 757                                 break;
 758                         }
 759                 }
 760         }
 761
 762         if (pass_on_stack) {
 763                 /* Allways pass in memory */
 764                 ainfo->offset = *stack_size;
 765                 *stack_size += ALIGN_TO (size, 8);
 766                 ainfo->storage = ArgOnStack;
 767
 768                 return;
 769         }
 770
 771         /* FIXME: Handle structs smaller than 8 bytes */
 772         //if ((size % 8) != 0)
 773         //      NOT_IMPLEMENTED;
 774
 775         if (size > 8)
 776                 nquads = 2;
 777         else
 778                 nquads = 1;
 779
 780         if (!sig->pinvoke) {
 781                 /* Always pass in 1 or 2 integer registers */
 782                 args [0] = ARG_CLASS_INTEGER;
 783                 args [1] = ARG_CLASS_INTEGER;
 784                 /* Only the simplest cases are supported */
 785                 if (is_return && nquads != 1) {
 786                         args [0] = ARG_CLASS_MEMORY;
 787                         args [1] = ARG_CLASS_MEMORY;
 788                 }
 789         } else {
 790                 /*
 791                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 792                  * The X87 and SSEUP stuff is left out since there are no such types in
 793                  * the CLR.
 794                  */
 795                 info = mono_marshal_load_type_info (klass);
 796                 g_assert (info);
 797
 798 #ifndef HOST_WIN32
 799                 if (info->native_size > 16) {
 800                         ainfo->offset = *stack_size;
 801                         *stack_size += ALIGN_TO (info->native_size, 8);
 802                         ainfo->storage = ArgOnStack;
 803
 804                         return;
 805                 }
 806 #else
 807                 switch (info->native_size) {
 808                 case 1: case 2: case 4: case 8:
 809                         break;
 810                 default:
 811                         if (is_return) {
 812                                 ainfo->storage = ArgOnStack;
 813                                 ainfo->offset = *stack_size;
 814                                 *stack_size += ALIGN_TO (info->native_size, 8);
 815                         }
 816                         else {
 817                                 ainfo->storage = ArgValuetypeAddrInIReg;
 818
 819                                 if (*gr < PARAM_REGS) {
 820                                         ainfo->pair_storage [0] = ArgInIReg;
 821                                         ainfo->pair_regs [0] = param_regs [*gr];
 822                                         (*gr) ++;
 823                                 }
 824                                 else {
 825                                         ainfo->pair_storage [0] = ArgOnStack;
 826                                         ainfo->offset = *stack_size;
 827                                         *stack_size += 8;
 828                                 }
 829                         }
 830
 831                         return;
 832                 }
 833 #endif
 834
 835                 args [0] = ARG_CLASS_NO_CLASS;
 836                 args [1] = ARG_CLASS_NO_CLASS;
 837                 for (quad = 0; quad < nquads; ++quad) {
 838                         int size;
 839                         guint32 align;
 840                         ArgumentClass class1;
 841
 842                         if (info->num_fields == 0)
 843                                 class1 = ARG_CLASS_MEMORY;
 844                         else
 845                                 class1 = ARG_CLASS_NO_CLASS;
 846                         for (i = 0; i < info->num_fields; ++i) {
 847                                 size = mono_marshal_type_size (info->fields [i].field->type,
 848                                                                                            info->fields [i].mspec,
 849                                                                                            &align, TRUE, klass->unicode);
 850                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 851                                         /* Unaligned field */
 852                                         NOT_IMPLEMENTED;
 853                                 }
 854
 855                                 /* Skip fields in other quad */
 856                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 857                                         continue;
 858                                 if ((quad == 1) && (info->fields [i].offset < 8))
 859                                         continue;
 860
 861                                 /* How far into this quad this data extends.*/
 862                                 /* (8 is size of quad) */
 863                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 864
 865                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 866                         }
 867                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 868                         args [quad] = class1;
 869                 }
 870         }
 871
 872         /* Post merger cleanup */
 873         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 874                 args [0] = args [1] = ARG_CLASS_MEMORY;
 875
 876         /* Allocate registers */
 877         {
 878                 int orig_gr = *gr;
 879                 int orig_fr = *fr;
 880
 881                 ainfo->storage = ArgValuetypeInReg;
 882                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 883                 ainfo->nregs = nquads;
 884                 for (quad = 0; quad < nquads; ++quad) {
 885                         switch (args [quad]) {
 886                         case ARG_CLASS_INTEGER:
 887                                 if (*gr >= PARAM_REGS)
 888                                         args [quad] = ARG_CLASS_MEMORY;
 889                                 else {
 890                                         ainfo->pair_storage [quad] = ArgInIReg;
 891                                         if (is_return)
 892                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 893                                         else
 894                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 895                                         (*gr) ++;
 896                                 }
 897                                 break;
 898                         case ARG_CLASS_SSE:
 899                                 if (*fr >= FLOAT_PARAM_REGS)
 900                                         args [quad] = ARG_CLASS_MEMORY;
 901                                 else {
 902                                         if (quadsize[quad] <= 4)
 903                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 904                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 905                                         ainfo->pair_regs [quad] = *fr;
 906                                         (*fr) ++;
 907                                 }
 908                                 break;
 909                         case ARG_CLASS_MEMORY:
 910                                 break;
 911                         default:
 912                                 g_assert_not_reached ();
 913                         }
 914                 }
 915
 916                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 917                         /* Revert possible register assignments */
 918                         *gr = orig_gr;
 919                         *fr = orig_fr;
 920
 921                         ainfo->offset = *stack_size;
 922                         if (sig->pinvoke)
 923                                 *stack_size += ALIGN_TO (info->native_size, 8);
 924                         else
 925                                 *stack_size += nquads * sizeof(mgreg_t);
 926                         ainfo->storage = ArgOnStack;
 927                 }
 928         }
 929 }
 930
 931 /*
 932  * get_call_info:
 933  *
 934  *  Obtain information about a call according to the calling convention.
 935  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 936  * Draft Version 0.23" document for more information.
 937  */
 938 static CallInfo*
 939 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 940 {
 941         guint32 i, gr, fr, pstart;
 942         MonoType *ret_type;
 943         int n = sig->hasthis + sig->param_count;
 944         guint32 stack_size = 0;
 945         CallInfo *cinfo;
 946         gboolean is_pinvoke = sig->pinvoke;
 947
 948         if (mp)
 949                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 950         else
 951                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 952
 953         cinfo->nargs = n;
 954
 955         gr = 0;
 956         fr = 0;
 957
 958         /* return value */
 959         {
 960                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 961                 switch (ret_type->type) {
 962                 case MONO_TYPE_BOOLEAN:
 963                 case MONO_TYPE_I1:
 964                 case MONO_TYPE_U1:
 965                 case MONO_TYPE_I2:
 966                 case MONO_TYPE_U2:
 967                 case MONO_TYPE_CHAR:
 968                 case MONO_TYPE_I4:
 969                 case MONO_TYPE_U4:
 970                 case MONO_TYPE_I:
 971                 case MONO_TYPE_U:
 972                 case MONO_TYPE_PTR:
 973                 case MONO_TYPE_FNPTR:
 974                 case MONO_TYPE_CLASS:
 975                 case MONO_TYPE_OBJECT:
 976                 case MONO_TYPE_SZARRAY:
 977                 case MONO_TYPE_ARRAY:
 978                 case MONO_TYPE_STRING:
 979                         cinfo->ret.storage = ArgInIReg;
 980                         cinfo->ret.reg = AMD64_RAX;
 981                         break;
 982                 case MONO_TYPE_U8:
 983                 case MONO_TYPE_I8:
 984                         cinfo->ret.storage = ArgInIReg;
 985                         cinfo->ret.reg = AMD64_RAX;
 986                         break;
 987                 case MONO_TYPE_R4:
 988                         cinfo->ret.storage = ArgInFloatSSEReg;
 989                         cinfo->ret.reg = AMD64_XMM0;
 990                         break;
 991                 case MONO_TYPE_R8:
 992                         cinfo->ret.storage = ArgInDoubleSSEReg;
 993                         cinfo->ret.reg = AMD64_XMM0;
 994                         break;
 995                 case MONO_TYPE_GENERICINST:
 996                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 997                                 cinfo->ret.storage = ArgInIReg;
 998                                 cinfo->ret.reg = AMD64_RAX;
 999                                 break;
1000                         }
1001                         /* fall through */
1002 #if defined( __native_client_codegen__ )
1003                 case MONO_TYPE_TYPEDBYREF:
1004 #endif
1005                 case MONO_TYPE_VALUETYPE: {
1006                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1007
1008                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1009                         if (cinfo->ret.storage == ArgOnStack) {
1010                                 cinfo->vtype_retaddr = TRUE;
1011                                 /* The caller passes the address where the value is stored */
1012                         }
1013                         break;
1014                 }
1015 #if !defined( __native_client_codegen__ )
1016                 case MONO_TYPE_TYPEDBYREF:
1017                         /* Same as a valuetype with size 24 */
1018                         cinfo->vtype_retaddr = TRUE;
1019                         break;
1020 #endif
1021                 case MONO_TYPE_VOID:
1022                         break;
1023                 default:
1024                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1025                 }
1026         }
1027
1028         pstart = 0;
1029         /*
1030          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1031          * the first argument, allowing 'this' to be always passed in the first arg reg.
1032          * Also do this if the first argument is a reference type, since virtual calls
1033          * are sometimes made using calli without sig->hasthis set, like in the delegate
1034          * invoke wrappers.
1035          */
1036         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1037                 if (sig->hasthis) {
1038                         add_general (&gr, &stack_size, cinfo->args + 0);
1039                 } else {
1040                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1041                         pstart = 1;
1042                 }
1043                 add_general (&gr, &stack_size, &cinfo->ret);
1044                 cinfo->vret_arg_index = 1;
1045         } else {
1046                 /* this */
1047                 if (sig->hasthis)
1048                         add_general (&gr, &stack_size, cinfo->args + 0);
1049
1050                 if (cinfo->vtype_retaddr)
1051                         add_general (&gr, &stack_size, &cinfo->ret);
1052         }
1053
1054         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1055                 gr = PARAM_REGS;
1056                 fr = FLOAT_PARAM_REGS;
1057
1058                 /* Emit the signature cookie just before the implicit arguments */
1059                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1060         }
1061
1062         for (i = pstart; i < sig->param_count; ++i) {
1063                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1064                 MonoType *ptype;
1065
1066 #ifdef HOST_WIN32
1067                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1068                 if (gr > fr)
1069                         fr = gr;
1070                 else if (fr > gr)
1071                         gr = fr;
1072 #endif
1073
1074                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1075                         /* We allways pass the sig cookie on the stack for simplicity */
1076                         /*
1077                          * Prevent implicit arguments + the sig cookie from being passed
1078                          * in registers.
1079                          */
1080                         gr = PARAM_REGS;
1081                         fr = FLOAT_PARAM_REGS;
1082
1083                         /* Emit the signature cookie just before the implicit arguments */
1084                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1085                 }
1086
1087                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1088                 switch (ptype->type) {
1089                 case MONO_TYPE_BOOLEAN:
1090                 case MONO_TYPE_I1:
1091                 case MONO_TYPE_U1:
1092                         add_general (&gr, &stack_size, ainfo);
1093                         break;
1094                 case MONO_TYPE_I2:
1095                 case MONO_TYPE_U2:
1096                 case MONO_TYPE_CHAR:
1097                         add_general (&gr, &stack_size, ainfo);
1098                         break;
1099                 case MONO_TYPE_I4:
1100                 case MONO_TYPE_U4:
1101                         add_general (&gr, &stack_size, ainfo);
1102                         break;
1103                 case MONO_TYPE_I:
1104                 case MONO_TYPE_U:
1105                 case MONO_TYPE_PTR:
1106                 case MONO_TYPE_FNPTR:
1107                 case MONO_TYPE_CLASS:
1108                 case MONO_TYPE_OBJECT:
1109                 case MONO_TYPE_STRING:
1110                 case MONO_TYPE_SZARRAY:
1111                 case MONO_TYPE_ARRAY:
1112                         add_general (&gr, &stack_size, ainfo);
1113                         break;
1114                 case MONO_TYPE_GENERICINST:
1115                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1116                                 add_general (&gr, &stack_size, ainfo);
1117                                 break;
1118                         }
1119                         /* fall through */
1120                 case MONO_TYPE_VALUETYPE:
1121                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1122                         break;
1123                 case MONO_TYPE_TYPEDBYREF:
1124 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1125                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1126 #else
1127                         stack_size += sizeof (MonoTypedRef);
1128                         ainfo->storage = ArgOnStack;
1129 #endif
1130                         break;
1131                 case MONO_TYPE_U8:
1132                 case MONO_TYPE_I8:
1133                         add_general (&gr, &stack_size, ainfo);
1134                         break;
1135                 case MONO_TYPE_R4:
1136                         add_float (&fr, &stack_size, ainfo, FALSE);
1137                         break;
1138                 case MONO_TYPE_R8:
1139                         add_float (&fr, &stack_size, ainfo, TRUE);
1140                         break;
1141                 default:
1142                         g_assert_not_reached ();
1143                 }
1144         }
1145
1146         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1147                 gr = PARAM_REGS;
1148                 fr = FLOAT_PARAM_REGS;
1149
1150                 /* Emit the signature cookie just before the implicit arguments */
1151                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1152         }
1153
1154 #ifdef HOST_WIN32
1155         // There always is 32 bytes reserved on the stack when calling on Winx64
1156         stack_size += 0x20;
1157 #endif
1158
1159 #ifndef MONO_AMD64_NO_PUSHES
1160         if (stack_size & 0x8) {
1161                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1162                 cinfo->need_stack_align = TRUE;
1163                 stack_size += 8;
1164         }
1165 #endif
1166
1167         cinfo->stack_usage = stack_size;
1168         cinfo->reg_usage = gr;
1169         cinfo->freg_usage = fr;
1170         return cinfo;
1171 }
1172
1173 /*
1174  * mono_arch_get_argument_info:
1175  * @csig:  a method signature
1176  * @param_count: the number of parameters to consider
1177  * @arg_info: an array to store the result infos
1178  *
1179  * Gathers information on parameters such as size, alignment and
1180  * padding. arg_info should be large enought to hold param_count + 1 entries.
1181  *
1182  * Returns the size of the argument area on the stack.
1183  */
1184 int
1185 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1186 {
1187         int k;
1188         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1189         guint32 args_size = cinfo->stack_usage;
1190
1191         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1192         if (csig->hasthis) {
1193                 arg_info [0].offset = 0;
1194         }
1195
1196         for (k = 0; k < param_count; k++) {
1197                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1198                 /* FIXME: */
1199                 arg_info [k + 1].size = 0;
1200         }
1201
1202         g_free (cinfo);
1203
1204         return args_size;
1205 }
1206
1207 gboolean
1208 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1209 {
1210         CallInfo *c1, *c2;
1211         gboolean res;
1212         MonoType *callee_ret;
1213
1214         c1 = get_call_info (NULL, NULL, caller_sig);
1215         c2 = get_call_info (NULL, NULL, callee_sig);
1216         res = c1->stack_usage >= c2->stack_usage;
1217         callee_ret = mini_replace_type (callee_sig->ret);
1218         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1219                 /* An address on the callee's stack is passed as the first argument */
1220                 res = FALSE;
1221
1222         g_free (c1);
1223         g_free (c2);
1224
1225         return res;
1226 }
1227
1228 /*
1229  * Initialize the cpu to execute managed code.
1230  */
1231 void
1232 mono_arch_cpu_init (void)
1233 {
1234 #ifndef _MSC_VER
1235         guint16 fpcw;
1236
1237         /* spec compliance requires running with double precision */
1238         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1239         fpcw &= ~X86_FPCW_PRECC_MASK;
1240         fpcw |= X86_FPCW_PREC_DOUBLE;
1241         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1242         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1243 #else
1244         /* TODO: This is crashing on Win64 right now.
1245         * _control87 (_PC_53, MCW_PC);
1246         */
1247 #endif
1248 }
1249
1250 /*
1251  * Initialize architecture specific code.
1252  */
1253 void
1254 mono_arch_init (void)
1255 {
1256         int flags;
1257
1258         InitializeCriticalSection (&mini_arch_mutex);
1259 #if defined(__native_client_codegen__)
1260         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1261         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1262         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1263         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1264 #endif
1265
1266 #ifdef MONO_ARCH_NOMAP32BIT
1267         flags = MONO_MMAP_READ;
1268         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1269         breakpoint_size = 13;
1270         breakpoint_fault_size = 3;
1271 #else
1272         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1273         /* amd64_mov_reg_mem () */
1274         breakpoint_size = 8;
1275         breakpoint_fault_size = 8;
1276 #endif
1277
1278         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1279         single_step_fault_size = 4;
1280
1281         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1283         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1284
1285         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1286         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1287         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1288 }
1289
1290 /*
1291  * Cleanup architecture specific code.
1292  */
1293 void
1294 mono_arch_cleanup (void)
1295 {
1296         DeleteCriticalSection (&mini_arch_mutex);
1297 #if defined(__native_client_codegen__)
1298         mono_native_tls_free (nacl_instruction_depth);
1299         mono_native_tls_free (nacl_rex_tag);
1300         mono_native_tls_free (nacl_legacy_prefix_tag);
1301 #endif
1302 }
1303
1304 /*
1305  * This function returns the optimizations supported on this cpu.
1306  */
1307 guint32
1308 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1309 {
1310         guint32 opts = 0;
1311
1312         *exclude_mask = 0;
1313
1314         if (mono_hwcap_x86_has_cmov) {
1315                 opts |= MONO_OPT_CMOV;
1316
1317                 if (mono_hwcap_x86_has_fcmov)
1318                         opts |= MONO_OPT_FCMOV;
1319                 else
1320                         *exclude_mask |= MONO_OPT_FCMOV;
1321         } else {
1322                 *exclude_mask |= MONO_OPT_CMOV;
1323         }
1324
1325         return opts;
1326 }
1327
1328 /*
1329  * This function test for all SSE functions supported.
1330  *
1331  * Returns a bitmask corresponding to all supported versions.
1332  *
1333  */
1334 guint32
1335 mono_arch_cpu_enumerate_simd_versions (void)
1336 {
1337         guint32 sse_opts = 0;
1338
1339         if (mono_hwcap_x86_has_sse1)
1340                 sse_opts |= SIMD_VERSION_SSE1;
1341
1342         if (mono_hwcap_x86_has_sse2)
1343                 sse_opts |= SIMD_VERSION_SSE2;
1344
1345         if (mono_hwcap_x86_has_sse3)
1346                 sse_opts |= SIMD_VERSION_SSE3;
1347
1348         if (mono_hwcap_x86_has_ssse3)
1349                 sse_opts |= SIMD_VERSION_SSSE3;
1350
1351         if (mono_hwcap_x86_has_sse41)
1352                 sse_opts |= SIMD_VERSION_SSE41;
1353
1354         if (mono_hwcap_x86_has_sse42)
1355                 sse_opts |= SIMD_VERSION_SSE42;
1356
1357         if (mono_hwcap_x86_has_sse4a)
1358                 sse_opts |= SIMD_VERSION_SSE4a;
1359
1360         return sse_opts;
1361 }
1362
1363 #ifndef DISABLE_JIT
1364
1365 GList *
1366 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1367 {
1368         GList *vars = NULL;
1369         int i;
1370
1371         for (i = 0; i < cfg->num_varinfo; i++) {
1372                 MonoInst *ins = cfg->varinfo [i];
1373                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1374
1375                 /* unused vars */
1376                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1377                         continue;
1378
1379                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1380                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1381                         continue;
1382
1383                 if (mono_is_regsize_var (ins->inst_vtype)) {
1384                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1385                         g_assert (i == vmv->idx);
1386                         vars = g_list_prepend (vars, vmv);
1387                 }
1388         }
1389
1390         vars = mono_varlist_sort (cfg, vars, 0);
1391
1392         return vars;
1393 }
1394
1395 /**
1396  * mono_arch_compute_omit_fp:
1397  *
1398  *   Determine whenever the frame pointer can be eliminated.
1399  */
1400 static void
1401 mono_arch_compute_omit_fp (MonoCompile *cfg)
1402 {
1403         MonoMethodSignature *sig;
1404         MonoMethodHeader *header;
1405         int i, locals_size;
1406         CallInfo *cinfo;
1407
1408         if (cfg->arch.omit_fp_computed)
1409                 return;
1410
1411         header = cfg->header;
1412
1413         sig = mono_method_signature (cfg->method);
1414
1415         if (!cfg->arch.cinfo)
1416                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1417         cinfo = cfg->arch.cinfo;
1418
1419         /*
1420          * FIXME: Remove some of the restrictions.
1421          */
1422         cfg->arch.omit_fp = TRUE;
1423         cfg->arch.omit_fp_computed = TRUE;
1424
1425 #ifdef __native_client_codegen__
1426         /* NaCl modules may not change the value of RBP, so it cannot be */
1427         /* used as a normal register, but it can be used as a frame pointer*/
1428         cfg->disable_omit_fp = TRUE;
1429         cfg->arch.omit_fp = FALSE;
1430 #endif
1431
1432 #ifdef HOST_WIN32
1433         cfg->arch.omit_fp = FALSE;
1434 #endif
1435
1436         if (cfg->disable_omit_fp)
1437                 cfg->arch.omit_fp = FALSE;
1438
1439         if (!debug_omit_fp ())
1440                 cfg->arch.omit_fp = FALSE;
1441         /*
1442         if (cfg->method->save_lmf)
1443                 cfg->arch.omit_fp = FALSE;
1444         */
1445         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1446                 cfg->arch.omit_fp = FALSE;
1447         if (header->num_clauses)
1448                 cfg->arch.omit_fp = FALSE;
1449         if (cfg->param_area)
1450                 cfg->arch.omit_fp = FALSE;
1451         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1452                 cfg->arch.omit_fp = FALSE;
1453         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1454                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1455                 cfg->arch.omit_fp = FALSE;
1456         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1457                 ArgInfo *ainfo = &cinfo->args [i];
1458
1459                 if (ainfo->storage == ArgOnStack) {
1460                         /*
1461                          * The stack offset can only be determined when the frame
1462                          * size is known.
1463                          */
1464                         cfg->arch.omit_fp = FALSE;
1465                 }
1466         }
1467
1468         locals_size = 0;
1469         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1470                 MonoInst *ins = cfg->varinfo [i];
1471                 int ialign;
1472
1473                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1474         }
1475 }
1476
1477 GList *
1478 mono_arch_get_global_int_regs (MonoCompile *cfg)
1479 {
1480         GList *regs = NULL;
1481
1482         mono_arch_compute_omit_fp (cfg);
1483
1484         if (cfg->globalra) {
1485                 if (cfg->arch.omit_fp)
1486                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1487
1488                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1489                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1490                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1491                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1492 #ifndef __native_client_codegen__
1493                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1494 #endif
1495
1496                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1497                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1498                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1499                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1500                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1501                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1502                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1503                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1504         } else {
1505                 if (cfg->arch.omit_fp)
1506                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1507
1508                 /* We use the callee saved registers for global allocation */
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1510                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1511                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1513 #ifndef __native_client_codegen__
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1515 #endif
1516 #ifdef HOST_WIN32
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1519 #endif
1520         }
1521
1522         return regs;
1523 }
1524
1525 GList*
1526 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1527 {
1528         GList *regs = NULL;
1529         int i;
1530
1531         /* All XMM registers */
1532         for (i = 0; i < 16; ++i)
1533                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1534
1535         return regs;
1536 }
1537
1538 GList*
1539 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1540 {
1541         static GList *r = NULL;
1542
1543         if (r == NULL) {
1544                 GList *regs = NULL;
1545
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1547                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1548                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1551 #ifndef __native_client_codegen__
1552                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1553 #endif
1554
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1558                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1559                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1560                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1561                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1562                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1563
1564                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1565         }
1566
1567         return r;
1568 }
1569
1570 GList*
1571 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         int i;
1574         static GList *r = NULL;
1575
1576         if (r == NULL) {
1577                 GList *regs = NULL;
1578
1579                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1580                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1581
1582                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1583         }
1584
1585         return r;
1586 }
1587
1588 /*
1589  * mono_arch_regalloc_cost:
1590  *
1591  *  Return the cost, in number of memory references, of the action of
1592  * allocating the variable VMV into a register during global register
1593  * allocation.
1594  */
1595 guint32
1596 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1597 {
1598         MonoInst *ins = cfg->varinfo [vmv->idx];
1599
1600         if (cfg->method->save_lmf)
1601                 /* The register is already saved */
1602                 /* substract 1 for the invisible store in the prolog */
1603                 return (ins->opcode == OP_ARG) ? 0 : 1;
1604         else
1605                 /* push+pop */
1606                 return (ins->opcode == OP_ARG) ? 1 : 2;
1607 }
1608
1609 /*
1610  * mono_arch_fill_argument_info:
1611  *
1612  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1613  * of the method.
1614  */
1615 void
1616 mono_arch_fill_argument_info (MonoCompile *cfg)
1617 {
1618         MonoType *sig_ret;
1619         MonoMethodSignature *sig;
1620         MonoMethodHeader *header;
1621         MonoInst *ins;
1622         int i;
1623         CallInfo *cinfo;
1624
1625         header = cfg->header;
1626
1627         sig = mono_method_signature (cfg->method);
1628
1629         cinfo = cfg->arch.cinfo;
1630         sig_ret = mini_replace_type (sig->ret);
1631
1632         /*
1633          * Contrary to mono_arch_allocate_vars (), the information should describe
1634          * where the arguments are at the beginning of the method, not where they can be
1635          * accessed during the execution of the method. The later makes no sense for the
1636          * global register allocator, since a variable can be in more than one location.
1637          */
1638         if (sig_ret->type != MONO_TYPE_VOID) {
1639                 switch (cinfo->ret.storage) {
1640                 case ArgInIReg:
1641                 case ArgInFloatSSEReg:
1642                 case ArgInDoubleSSEReg:
1643                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1644                                 cfg->vret_addr->opcode = OP_REGVAR;
1645                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1646                         }
1647                         else {
1648                                 cfg->ret->opcode = OP_REGVAR;
1649                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1650                         }
1651                         break;
1652                 case ArgValuetypeInReg:
1653                         cfg->ret->opcode = OP_REGOFFSET;
1654                         cfg->ret->inst_basereg = -1;
1655                         cfg->ret->inst_offset = -1;
1656                         break;
1657                 default:
1658                         g_assert_not_reached ();
1659                 }
1660         }
1661
1662         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1663                 ArgInfo *ainfo = &cinfo->args [i];
1664                 MonoType *arg_type;
1665
1666                 ins = cfg->args [i];
1667
1668                 if (sig->hasthis && (i == 0))
1669                         arg_type = &mono_defaults.object_class->byval_arg;
1670                 else
1671                         arg_type = sig->params [i - sig->hasthis];
1672
1673                 switch (ainfo->storage) {
1674                 case ArgInIReg:
1675                 case ArgInFloatSSEReg:
1676                 case ArgInDoubleSSEReg:
1677                         ins->opcode = OP_REGVAR;
1678                         ins->inst_c0 = ainfo->reg;
1679                         break;
1680                 case ArgOnStack:
1681                         ins->opcode = OP_REGOFFSET;
1682                         ins->inst_basereg = -1;
1683                         ins->inst_offset = -1;
1684                         break;
1685                 case ArgValuetypeInReg:
1686                         /* Dummy */
1687                         ins->opcode = OP_NOP;
1688                         break;
1689                 default:
1690                         g_assert_not_reached ();
1691                 }
1692         }
1693 }
1694
1695 void
1696 mono_arch_allocate_vars (MonoCompile *cfg)
1697 {
1698         MonoType *sig_ret;
1699         MonoMethodSignature *sig;
1700         MonoMethodHeader *header;
1701         MonoInst *ins;
1702         int i, offset;
1703         guint32 locals_stack_size, locals_stack_align;
1704         gint32 *offsets;
1705         CallInfo *cinfo;
1706
1707         header = cfg->header;
1708
1709         sig = mono_method_signature (cfg->method);
1710
1711         cinfo = cfg->arch.cinfo;
1712         sig_ret = mini_replace_type (sig->ret);
1713
1714         mono_arch_compute_omit_fp (cfg);
1715
1716         /*
1717          * We use the ABI calling conventions for managed code as well.
1718          * Exception: valuetypes are only sometimes passed or returned in registers.
1719          */
1720
1721         /*
1722          * The stack looks like this:
1723          * <incoming arguments passed on the stack>
1724          * <return value>
1725          * <lmf/caller saved registers>
1726          * <locals>
1727          * <spill area>
1728          * <localloc area>  -> grows dynamically
1729          * <params area>
1730          */
1731
1732         if (cfg->arch.omit_fp) {
1733                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1734                 cfg->frame_reg = AMD64_RSP;
1735                 offset = 0;
1736         } else {
1737                 /* Locals are allocated backwards from %fp */
1738                 cfg->frame_reg = AMD64_RBP;
1739                 offset = 0;
1740         }
1741
1742         cfg->arch.saved_iregs = cfg->used_int_regs;
1743         if (cfg->method->save_lmf)
1744                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1745                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1746
1747         if (cfg->arch.omit_fp)
1748                 cfg->arch.reg_save_area_offset = offset;
1749         /* Reserve space for callee saved registers */
1750         for (i = 0; i < AMD64_NREG; ++i)
1751                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1752                         offset += sizeof(mgreg_t);
1753                 }
1754         if (!cfg->arch.omit_fp)
1755                 cfg->arch.reg_save_area_offset = -offset;
1756
1757         if (sig_ret->type != MONO_TYPE_VOID) {
1758                 switch (cinfo->ret.storage) {
1759                 case ArgInIReg:
1760                 case ArgInFloatSSEReg:
1761                 case ArgInDoubleSSEReg:
1762                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1763                                 if (cfg->globalra) {
1764                                         cfg->vret_addr->opcode = OP_REGVAR;
1765                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1766                                 } else {
1767                                         /* The register is volatile */
1768                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1769                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1770                                         if (cfg->arch.omit_fp) {
1771                                                 cfg->vret_addr->inst_offset = offset;
1772                                                 offset += 8;
1773                                         } else {
1774                                                 offset += 8;
1775                                                 cfg->vret_addr->inst_offset = -offset;
1776                                         }
1777                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1778                                                 printf ("vret_addr =");
1779                                                 mono_print_ins (cfg->vret_addr);
1780                                         }
1781                                 }
1782                         }
1783                         else {
1784                                 cfg->ret->opcode = OP_REGVAR;
1785                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1786                         }
1787                         break;
1788                 case ArgValuetypeInReg:
1789                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1790                         cfg->ret->opcode = OP_REGOFFSET;
1791                         cfg->ret->inst_basereg = cfg->frame_reg;
1792                         if (cfg->arch.omit_fp) {
1793                                 cfg->ret->inst_offset = offset;
1794                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1795                         } else {
1796                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1797                                 cfg->ret->inst_offset = - offset;
1798                         }
1799                         break;
1800                 default:
1801                         g_assert_not_reached ();
1802                 }
1803                 if (!cfg->globalra)
1804                         cfg->ret->dreg = cfg->ret->inst_c0;
1805         }
1806
1807         /* Allocate locals */
1808         if (!cfg->globalra) {
1809                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1810                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1811                         char *mname = mono_method_full_name (cfg->method, TRUE);
1812                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1813                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1814                         g_free (mname);
1815                         return;
1816                 }
1817
1818                 if (locals_stack_align) {
1819                         offset += (locals_stack_align - 1);
1820                         offset &= ~(locals_stack_align - 1);
1821                 }
1822                 if (cfg->arch.omit_fp) {
1823                         cfg->locals_min_stack_offset = offset;
1824                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1825                 } else {
1826                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1827                         cfg->locals_max_stack_offset = - offset;
1828                 }
1829
1830                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1831                         if (offsets [i] != -1) {
1832                                 MonoInst *ins = cfg->varinfo [i];
1833                                 ins->opcode = OP_REGOFFSET;
1834                                 ins->inst_basereg = cfg->frame_reg;
1835                                 if (cfg->arch.omit_fp)
1836                                         ins->inst_offset = (offset + offsets [i]);
1837                                 else
1838                                         ins->inst_offset = - (offset + offsets [i]);
1839                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1840                         }
1841                 }
1842                 offset += locals_stack_size;
1843         }
1844
1845         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1846                 g_assert (!cfg->arch.omit_fp);
1847                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1848                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1849         }
1850
1851         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1852                 ins = cfg->args [i];
1853                 if (ins->opcode != OP_REGVAR) {
1854                         ArgInfo *ainfo = &cinfo->args [i];
1855                         gboolean inreg = TRUE;
1856                         MonoType *arg_type;
1857
1858                         if (sig->hasthis && (i == 0))
1859                                 arg_type = &mono_defaults.object_class->byval_arg;
1860                         else
1861                                 arg_type = sig->params [i - sig->hasthis];
1862
1863                         if (cfg->globalra) {
1864                                 /* The new allocator needs info about the original locations of the arguments */
1865                                 switch (ainfo->storage) {
1866                                 case ArgInIReg:
1867                                 case ArgInFloatSSEReg:
1868                                 case ArgInDoubleSSEReg:
1869                                         ins->opcode = OP_REGVAR;
1870                                         ins->inst_c0 = ainfo->reg;
1871                                         break;
1872                                 case ArgOnStack:
1873                                         g_assert (!cfg->arch.omit_fp);
1874                                         ins->opcode = OP_REGOFFSET;
1875                                         ins->inst_basereg = cfg->frame_reg;
1876                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1877                                         break;
1878                                 case ArgValuetypeInReg:
1879                                         ins->opcode = OP_REGOFFSET;
1880                                         ins->inst_basereg = cfg->frame_reg;
1881                                         /* These arguments are saved to the stack in the prolog */
1882                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1883                                         if (cfg->arch.omit_fp) {
1884                                                 ins->inst_offset = offset;
1885                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1886                                         } else {
1887                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1888                                                 ins->inst_offset = - offset;
1889                                         }
1890                                         break;
1891                                 default:
1892                                         g_assert_not_reached ();
1893                                 }
1894
1895                                 continue;
1896                         }
1897
1898                         /* FIXME: Allocate volatile arguments to registers */
1899                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1900                                 inreg = FALSE;
1901
1902                         /*
1903                          * Under AMD64, all registers used to pass arguments to functions
1904                          * are volatile across calls.
1905                          * FIXME: Optimize this.
1906                          */
1907                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1908                                 inreg = FALSE;
1909
1910                         ins->opcode = OP_REGOFFSET;
1911
1912                         switch (ainfo->storage) {
1913                         case ArgInIReg:
1914                         case ArgInFloatSSEReg:
1915                         case ArgInDoubleSSEReg:
1916                                 if (inreg) {
1917                                         ins->opcode = OP_REGVAR;
1918                                         ins->dreg = ainfo->reg;
1919                                 }
1920                                 break;
1921                         case ArgOnStack:
1922                                 g_assert (!cfg->arch.omit_fp);
1923                                 ins->opcode = OP_REGOFFSET;
1924                                 ins->inst_basereg = cfg->frame_reg;
1925                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1926                                 break;
1927                         case ArgValuetypeInReg:
1928                                 break;
1929                         case ArgValuetypeAddrInIReg: {
1930                                 MonoInst *indir;
1931                                 g_assert (!cfg->arch.omit_fp);
1932
1933                                 MONO_INST_NEW (cfg, indir, 0);
1934                                 indir->opcode = OP_REGOFFSET;
1935                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1936                                         indir->inst_basereg = cfg->frame_reg;
1937                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1938                                         offset += (sizeof (gpointer));
1939                                         indir->inst_offset = - offset;
1940                                 }
1941                                 else {
1942                                         indir->inst_basereg = cfg->frame_reg;
1943                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1944                                 }
1945
1946                                 ins->opcode = OP_VTARG_ADDR;
1947                                 ins->inst_left = indir;
1948
1949                                 break;
1950                         }
1951                         default:
1952                                 NOT_IMPLEMENTED;
1953                         }
1954
1955                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1956                                 ins->opcode = OP_REGOFFSET;
1957                                 ins->inst_basereg = cfg->frame_reg;
1958                                 /* These arguments are saved to the stack in the prolog */
1959                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1960                                 if (cfg->arch.omit_fp) {
1961                                         ins->inst_offset = offset;
1962                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1963                                         // Arguments are yet supported by the stack map creation code
1964                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1965                                 } else {
1966                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1967                                         ins->inst_offset = - offset;
1968                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1969                                 }
1970                         }
1971                 }
1972         }
1973
1974         cfg->stack_offset = offset;
1975 }
1976
1977 void
1978 mono_arch_create_vars (MonoCompile *cfg)
1979 {
1980         MonoMethodSignature *sig;
1981         CallInfo *cinfo;
1982         MonoType *sig_ret;
1983
1984         sig = mono_method_signature (cfg->method);
1985
1986         if (!cfg->arch.cinfo)
1987                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1988         cinfo = cfg->arch.cinfo;
1989
1990         if (cinfo->ret.storage == ArgValuetypeInReg)
1991                 cfg->ret_var_is_local = TRUE;
1992
1993         sig_ret = mini_replace_type (sig->ret);
1994         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1995                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1996                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1997                         printf ("vret_addr = ");
1998                         mono_print_ins (cfg->vret_addr);
1999                 }
2000         }
2001
2002         if (cfg->gen_seq_points) {
2003                 MonoInst *ins;
2004
2005                 if (cfg->compile_aot) {
2006                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2007                         ins->flags |= MONO_INST_VOLATILE;
2008                         cfg->arch.seq_point_info_var = ins;
2009                 }
2010
2011             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2012                 ins->flags |= MONO_INST_VOLATILE;
2013                 cfg->arch.ss_trigger_page_var = ins;
2014         }
2015
2016 #ifdef MONO_AMD64_NO_PUSHES
2017         /*
2018          * When this is set, we pass arguments on the stack by moves, and by allocating
2019          * a bigger stack frame, instead of pushes.
2020          * Pushes complicate exception handling because the arguments on the stack have
2021          * to be popped each time a frame is unwound. They also make fp elimination
2022          * impossible.
2023          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2024          * on a new frame which doesn't include a param area.
2025          */
2026         cfg->arch.no_pushes = TRUE;
2027 #endif
2028
2029         if (cfg->method->save_lmf)
2030                 cfg->create_lmf_var = TRUE;
2031
2032 #if !defined(HOST_WIN32)
2033         if (cfg->method->save_lmf) {
2034                 cfg->lmf_ir = TRUE;
2035                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2036                         cfg->lmf_ir_mono_lmf = TRUE;
2037         }
2038 #endif
2039
2040 #ifndef MONO_AMD64_NO_PUSHES
2041         cfg->arch_eh_jit_info = 1;
2042 #endif
2043 }
2044
2045 static void
2046 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2047 {
2048         MonoInst *ins;
2049
2050         switch (storage) {
2051         case ArgInIReg:
2052                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2053                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2054                 ins->sreg1 = tree->dreg;
2055                 MONO_ADD_INS (cfg->cbb, ins);
2056                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2057                 break;
2058         case ArgInFloatSSEReg:
2059                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2060                 ins->dreg = mono_alloc_freg (cfg);
2061                 ins->sreg1 = tree->dreg;
2062                 MONO_ADD_INS (cfg->cbb, ins);
2063
2064                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2065                 break;
2066         case ArgInDoubleSSEReg:
2067                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2068                 ins->dreg = mono_alloc_freg (cfg);
2069                 ins->sreg1 = tree->dreg;
2070                 MONO_ADD_INS (cfg->cbb, ins);
2071
2072                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2073
2074                 break;
2075         default:
2076                 g_assert_not_reached ();
2077         }
2078 }
2079
2080 static int
2081 arg_storage_to_load_membase (ArgStorage storage)
2082 {
2083         switch (storage) {
2084         case ArgInIReg:
2085 #if defined(__mono_ilp32__)
2086                 return OP_LOADI8_MEMBASE;
2087 #else
2088                 return OP_LOAD_MEMBASE;
2089 #endif
2090         case ArgInDoubleSSEReg:
2091                 return OP_LOADR8_MEMBASE;
2092         case ArgInFloatSSEReg:
2093                 return OP_LOADR4_MEMBASE;
2094         default:
2095                 g_assert_not_reached ();
2096         }
2097
2098         return -1;
2099 }
2100
2101 static void
2102 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2103 {
2104         MonoInst *arg;
2105         MonoMethodSignature *tmp_sig;
2106         int sig_reg;
2107
2108         if (call->tail_call)
2109                 NOT_IMPLEMENTED;
2110
2111         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2112
2113         /*
2114          * mono_ArgIterator_Setup assumes the signature cookie is
2115          * passed first and all the arguments which were before it are
2116          * passed on the stack after the signature. So compensate by
2117          * passing a different signature.
2118          */
2119         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2120         tmp_sig->param_count -= call->signature->sentinelpos;
2121         tmp_sig->sentinelpos = 0;
2122         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2123
2124         sig_reg = mono_alloc_ireg (cfg);
2125         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2126
2127         if (cfg->arch.no_pushes) {
2128                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2129         } else {
2130                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2131                 arg->sreg1 = sig_reg;
2132                 MONO_ADD_INS (cfg->cbb, arg);
2133         }
2134 }
2135
2136 static inline LLVMArgStorage
2137 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2138 {
2139         switch (storage) {
2140         case ArgInIReg:
2141                 return LLVMArgInIReg;
2142         case ArgNone:
2143                 return LLVMArgNone;
2144         default:
2145                 g_assert_not_reached ();
2146                 return LLVMArgNone;
2147         }
2148 }
2149
2150 #ifdef ENABLE_LLVM
2151 LLVMCallInfo*
2152 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2153 {
2154         int i, n;
2155         CallInfo *cinfo;
2156         ArgInfo *ainfo;
2157         int j;
2158         LLVMCallInfo *linfo;
2159         MonoType *t, *sig_ret;
2160
2161         n = sig->param_count + sig->hasthis;
2162         sig_ret = mini_replace_type (sig->ret);
2163
2164         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2165
2166         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2167
2168         /*
2169          * LLVM always uses the native ABI while we use our own ABI, the
2170          * only difference is the handling of vtypes:
2171          * - we only pass/receive them in registers in some cases, and only
2172          *   in 1 or 2 integer registers.
2173          */
2174         if (cinfo->ret.storage == ArgValuetypeInReg) {
2175                 if (sig->pinvoke) {
2176                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2177                         cfg->disable_llvm = TRUE;
2178                         return linfo;
2179                 }
2180
2181                 linfo->ret.storage = LLVMArgVtypeInReg;
2182                 for (j = 0; j < 2; ++j)
2183                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2184         }
2185
2186         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2187                 /* Vtype returned using a hidden argument */
2188                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2189                 linfo->vret_arg_index = cinfo->vret_arg_index;
2190         }
2191
2192         for (i = 0; i < n; ++i) {
2193                 ainfo = cinfo->args + i;
2194
2195                 if (i >= sig->hasthis)
2196                         t = sig->params [i - sig->hasthis];
2197                 else
2198                         t = &mono_defaults.int_class->byval_arg;
2199
2200                 linfo->args [i].storage = LLVMArgNone;
2201
2202                 switch (ainfo->storage) {
2203                 case ArgInIReg:
2204                         linfo->args [i].storage = LLVMArgInIReg;
2205                         break;
2206                 case ArgInDoubleSSEReg:
2207                 case ArgInFloatSSEReg:
2208                         linfo->args [i].storage = LLVMArgInFPReg;
2209                         break;
2210                 case ArgOnStack:
2211                         if (MONO_TYPE_ISSTRUCT (t)) {
2212                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2213                         } else {
2214                                 linfo->args [i].storage = LLVMArgInIReg;
2215                                 if (!t->byref) {
2216                                         if (t->type == MONO_TYPE_R4)
2217                                                 linfo->args [i].storage = LLVMArgInFPReg;
2218                                         else if (t->type == MONO_TYPE_R8)
2219                                                 linfo->args [i].storage = LLVMArgInFPReg;
2220                                 }
2221                         }
2222                         break;
2223                 case ArgValuetypeInReg:
2224                         if (sig->pinvoke) {
2225                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2226                                 cfg->disable_llvm = TRUE;
2227                                 return linfo;
2228                         }
2229
2230                         linfo->args [i].storage = LLVMArgVtypeInReg;
2231                         for (j = 0; j < 2; ++j)
2232                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2233                         break;
2234                 default:
2235                         cfg->exception_message = g_strdup ("ainfo->storage");
2236                         cfg->disable_llvm = TRUE;
2237                         break;
2238                 }
2239         }
2240
2241         return linfo;
2242 }
2243 #endif
2244
2245 void
2246 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2247 {
2248         MonoInst *arg, *in;
2249         MonoMethodSignature *sig;
2250         MonoType *sig_ret;
2251         int i, n, stack_size;
2252         CallInfo *cinfo;
2253         ArgInfo *ainfo;
2254
2255         stack_size = 0;
2256
2257         sig = call->signature;
2258         n = sig->param_count + sig->hasthis;
2259
2260         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2261
2262         sig_ret = sig->ret;
2263
2264         if (COMPILE_LLVM (cfg)) {
2265                 /* We shouldn't be called in the llvm case */
2266                 cfg->disable_llvm = TRUE;
2267                 return;
2268         }
2269
2270         if (cinfo->need_stack_align) {
2271                 if (!cfg->arch.no_pushes)
2272                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2273         }
2274
2275         /*
2276          * Emit all arguments which are passed on the stack to prevent register
2277          * allocation problems.
2278          */
2279         if (cfg->arch.no_pushes) {
2280                 for (i = 0; i < n; ++i) {
2281                         MonoType *t;
2282                         ainfo = cinfo->args + i;
2283
2284                         in = call->args [i];
2285
2286                         if (sig->hasthis && i == 0)
2287                                 t = &mono_defaults.object_class->byval_arg;
2288                         else
2289                                 t = sig->params [i - sig->hasthis];
2290
2291                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2292                                 if (!t->byref) {
2293                                         if (t->type == MONO_TYPE_R4)
2294                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2295                                         else if (t->type == MONO_TYPE_R8)
2296                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                         else
2298                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 } else {
2300                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                                 }
2302                                 if (cfg->compute_gc_maps) {
2303                                         MonoInst *def;
2304
2305                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2306                                 }
2307                         }
2308                 }
2309         }
2310
2311         /*
2312          * Emit all parameters passed in registers in non-reverse order for better readability
2313          * and to help the optimization in emit_prolog ().
2314          */
2315         for (i = 0; i < n; ++i) {
2316                 ainfo = cinfo->args + i;
2317
2318                 in = call->args [i];
2319
2320                 if (ainfo->storage == ArgInIReg)
2321                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2322         }
2323
2324         for (i = n - 1; i >= 0; --i) {
2325                 ainfo = cinfo->args + i;
2326
2327                 in = call->args [i];
2328
2329                 switch (ainfo->storage) {
2330                 case ArgInIReg:
2331                         /* Already done */
2332                         break;
2333                 case ArgInFloatSSEReg:
2334                 case ArgInDoubleSSEReg:
2335                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2336                         break;
2337                 case ArgOnStack:
2338                 case ArgValuetypeInReg:
2339                 case ArgValuetypeAddrInIReg:
2340                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2341                                 MonoInst *call_inst = (MonoInst*)call;
2342                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2343                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2344                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2345                                 guint32 align;
2346                                 guint32 size;
2347
2348                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2349                                         size = sizeof (MonoTypedRef);
2350                                         align = sizeof (gpointer);
2351                                 }
2352                                 else {
2353                                         if (sig->pinvoke)
2354                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2355                                         else {
2356                                                 /*
2357                                                  * Other backends use mono_type_stack_size (), but that
2358                                                  * aligns the size to 8, which is larger than the size of
2359                                                  * the source, leading to reads of invalid memory if the
2360                                                  * source is at the end of address space.
2361                                                  */
2362                                                 size = mono_class_value_size (in->klass, &align);
2363                                         }
2364                                 }
2365                                 g_assert (in->klass);
2366
2367                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2368                                         /* Avoid asserts in emit_memcpy () */
2369                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2370                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2371                                         /* Continue normally */
2372                                 }
2373
2374                                 if (size > 0) {
2375                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2376                                         arg->sreg1 = in->dreg;
2377                                         arg->klass = in->klass;
2378                                         arg->backend.size = size;
2379                                         arg->inst_p0 = call;
2380                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2381                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2382
2383                                         MONO_ADD_INS (cfg->cbb, arg);
2384                                 }
2385                         } else {
2386                                 if (cfg->arch.no_pushes) {
2387                                         /* Already done */
2388                                 } else {
2389                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2390                                         arg->sreg1 = in->dreg;
2391                                         if (!sig->params [i - sig->hasthis]->byref) {
2392                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2393                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2394                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2395                                                         arg->inst_destbasereg = X86_ESP;
2396                                                         arg->inst_offset = 0;
2397                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2398                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2399                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2400                                                         arg->inst_destbasereg = X86_ESP;
2401                                                         arg->inst_offset = 0;
2402                                                 }
2403                                         }
2404                                         MONO_ADD_INS (cfg->cbb, arg);
2405                                 }
2406                         }
2407                         break;
2408                 default:
2409                         g_assert_not_reached ();
2410                 }
2411
2412                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2413                         /* Emit the signature cookie just before the implicit arguments */
2414                         emit_sig_cookie (cfg, call, cinfo);
2415         }
2416
2417         /* Handle the case where there are no implicit arguments */
2418         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2419                 emit_sig_cookie (cfg, call, cinfo);
2420
2421         sig_ret = mini_replace_type (sig->ret);
2422         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2423                 MonoInst *vtarg;
2424
2425                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2426                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2427                                 /*
2428                                  * Tell the JIT to use a more efficient calling convention: call using
2429                                  * OP_CALL, compute the result location after the call, and save the
2430                                  * result there.
2431                                  */
2432                                 call->vret_in_reg = TRUE;
2433                                 /*
2434                                  * Nullify the instruction computing the vret addr to enable
2435                                  * future optimizations.
2436                                  */
2437                                 if (call->vret_var)
2438                                         NULLIFY_INS (call->vret_var);
2439                         } else {
2440                                 if (call->tail_call)
2441                                         NOT_IMPLEMENTED;
2442                                 /*
2443                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2444                                  * the stack. Push the address here, so the call instruction can
2445                                  * access it.
2446                                  */
2447                                 if (!cfg->arch.vret_addr_loc) {
2448                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2449                                         /* Prevent it from being register allocated or optimized away */
2450                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2451                                 }
2452
2453                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2454                         }
2455                 }
2456                 else {
2457                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2458                         vtarg->sreg1 = call->vret_var->dreg;
2459                         vtarg->dreg = mono_alloc_preg (cfg);
2460                         MONO_ADD_INS (cfg->cbb, vtarg);
2461
2462                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2463                 }
2464         }
2465
2466 #ifdef HOST_WIN32
2467         if (call->inst.opcode != OP_TAILCALL) {
2468                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2469         }
2470 #endif
2471
2472         if (cfg->method->save_lmf) {
2473                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2474                 MONO_ADD_INS (cfg->cbb, arg);
2475         }
2476
2477         call->stack_usage = cinfo->stack_usage;
2478 }
2479
2480 void
2481 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2482 {
2483         MonoInst *arg;
2484         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2485         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2486         int size = ins->backend.size;
2487
2488         if (ainfo->storage == ArgValuetypeInReg) {
2489                 MonoInst *load;
2490                 int part;
2491
2492                 for (part = 0; part < 2; ++part) {
2493                         if (ainfo->pair_storage [part] == ArgNone)
2494                                 continue;
2495
2496                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2497                         load->inst_basereg = src->dreg;
2498                         load->inst_offset = part * sizeof(mgreg_t);
2499
2500                         switch (ainfo->pair_storage [part]) {
2501                         case ArgInIReg:
2502                                 load->dreg = mono_alloc_ireg (cfg);
2503                                 break;
2504                         case ArgInDoubleSSEReg:
2505                         case ArgInFloatSSEReg:
2506                                 load->dreg = mono_alloc_freg (cfg);
2507                                 break;
2508                         default:
2509                                 g_assert_not_reached ();
2510                         }
2511                         MONO_ADD_INS (cfg->cbb, load);
2512
2513                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2514                 }
2515         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2516                 MonoInst *vtaddr, *load;
2517                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2518
2519                 g_assert (!cfg->arch.no_pushes);
2520
2521                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2522                 cfg->has_indirection = TRUE;
2523                 load->inst_p0 = vtaddr;
2524                 vtaddr->flags |= MONO_INST_INDIRECT;
2525                 load->type = STACK_MP;
2526                 load->klass = vtaddr->klass;
2527                 load->dreg = mono_alloc_ireg (cfg);
2528                 MONO_ADD_INS (cfg->cbb, load);
2529                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2530
2531                 if (ainfo->pair_storage [0] == ArgInIReg) {
2532                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2533                         arg->dreg = mono_alloc_ireg (cfg);
2534                         arg->sreg1 = load->dreg;
2535                         arg->inst_imm = 0;
2536                         MONO_ADD_INS (cfg->cbb, arg);
2537                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2538                 } else {
2539                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2540                         arg->sreg1 = load->dreg;
2541                         MONO_ADD_INS (cfg->cbb, arg);
2542                 }
2543         } else {
2544                 if (size == 8) {
2545                         if (cfg->arch.no_pushes) {
2546                                 int dreg = mono_alloc_ireg (cfg);
2547
2548                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2549                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2550                         } else {
2551                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2552                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2553                                 arg->inst_basereg = src->dreg;
2554                                 arg->inst_offset = 0;
2555                                 MONO_ADD_INS (cfg->cbb, arg);
2556                         }
2557                 } else if (size <= 40) {
2558                         if (cfg->arch.no_pushes) {
2559                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2560                         } else {
2561                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2562                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2563                         }
2564                 } else {
2565                         if (cfg->arch.no_pushes) {
2566                                 // FIXME: Code growth
2567                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2568                         } else {
2569                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2570                                 arg->inst_basereg = src->dreg;
2571                                 arg->inst_offset = 0;
2572                                 arg->inst_imm = size;
2573                                 MONO_ADD_INS (cfg->cbb, arg);
2574                         }
2575                 }
2576
2577                 if (cfg->compute_gc_maps) {
2578                         MonoInst *def;
2579                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2580                 }
2581         }
2582 }
2583
2584 void
2585 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2586 {
2587         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2588
2589         if (ret->type == MONO_TYPE_R4) {
2590                 if (COMPILE_LLVM (cfg))
2591                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2592                 else
2593                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2594                 return;
2595         } else if (ret->type == MONO_TYPE_R8) {
2596                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2597                 return;
2598         }
2599
2600         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2601 }
2602
2603 #endif /* DISABLE_JIT */
2604
2605 #define EMIT_COND_BRANCH(ins,cond,sign) \
2606         if (ins->inst_true_bb->native_offset) { \
2607                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2608         } else { \
2609                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2610                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2611             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2612                         x86_branch8 (code, cond, 0, sign); \
2613                 else \
2614                         x86_branch32 (code, cond, 0, sign); \
2615 }
2616
2617 typedef struct {
2618         MonoMethodSignature *sig;
2619         CallInfo *cinfo;
2620 } ArchDynCallInfo;
2621
2622 typedef struct {
2623         mgreg_t regs [PARAM_REGS];
2624         mgreg_t res;
2625         guint8 *ret;
2626 } DynCallArgs;
2627
2628 static gboolean
2629 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2630 {
2631         int i;
2632
2633 #ifdef HOST_WIN32
2634         return FALSE;
2635 #endif
2636
2637         switch (cinfo->ret.storage) {
2638         case ArgNone:
2639         case ArgInIReg:
2640                 break;
2641         case ArgValuetypeInReg: {
2642                 ArgInfo *ainfo = &cinfo->ret;
2643
2644                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2645                         return FALSE;
2646                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2647                         return FALSE;
2648                 break;
2649         }
2650         default:
2651                 return FALSE;
2652         }
2653
2654         for (i = 0; i < cinfo->nargs; ++i) {
2655                 ArgInfo *ainfo = &cinfo->args [i];
2656                 switch (ainfo->storage) {
2657                 case ArgInIReg:
2658                         break;
2659                 case ArgValuetypeInReg:
2660                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2661                                 return FALSE;
2662                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2663                                 return FALSE;
2664                         break;
2665                 default:
2666                         return FALSE;
2667                 }
2668         }
2669
2670         return TRUE;
2671 }
2672
2673 /*
2674  * mono_arch_dyn_call_prepare:
2675  *
2676  *   Return a pointer to an arch-specific structure which contains information
2677  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2678  * supported for SIG.
2679  * This function is equivalent to ffi_prep_cif in libffi.
2680  */
2681 MonoDynCallInfo*
2682 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2683 {
2684         ArchDynCallInfo *info;
2685         CallInfo *cinfo;
2686
2687         cinfo = get_call_info (NULL, NULL, sig);
2688
2689         if (!dyn_call_supported (sig, cinfo)) {
2690                 g_free (cinfo);
2691                 return NULL;
2692         }
2693
2694         info = g_new0 (ArchDynCallInfo, 1);
2695         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2696         info->sig = sig;
2697         info->cinfo = cinfo;
2698
2699         return (MonoDynCallInfo*)info;
2700 }
2701
2702 /*
2703  * mono_arch_dyn_call_free:
2704  *
2705  *   Free a MonoDynCallInfo structure.
2706  */
2707 void
2708 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2709 {
2710         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2711
2712         g_free (ainfo->cinfo);
2713         g_free (ainfo);
2714 }
2715
2716 #if !defined(__native_client__)
2717 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2718 #define GREG_TO_PTR(greg) (gpointer)(greg)
2719 #else
2720 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2721 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2722 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2723 #endif
2724
2725 /*
2726  * mono_arch_get_start_dyn_call:
2727  *
2728  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2729  * store the result into BUF.
2730  * ARGS should be an array of pointers pointing to the arguments.
2731  * RET should point to a memory buffer large enought to hold the result of the
2732  * call.
2733  * This function should be as fast as possible, any work which does not depend
2734  * on the actual values of the arguments should be done in
2735  * mono_arch_dyn_call_prepare ().
2736  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2737  * libffi.
2738  */
2739 void
2740 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2741 {
2742         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2743         DynCallArgs *p = (DynCallArgs*)buf;
2744         int arg_index, greg, i, pindex;
2745         MonoMethodSignature *sig = dinfo->sig;
2746
2747         g_assert (buf_len >= sizeof (DynCallArgs));
2748
2749         p->res = 0;
2750         p->ret = ret;
2751
2752         arg_index = 0;
2753         greg = 0;
2754         pindex = 0;
2755
2756         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2757                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2758                 if (!sig->hasthis)
2759                         pindex = 1;
2760         }
2761
2762         if (dinfo->cinfo->vtype_retaddr)
2763                 p->regs [greg ++] = PTR_TO_GREG(ret);
2764
2765         for (i = pindex; i < sig->param_count; i++) {
2766                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2767                 gpointer *arg = args [arg_index ++];
2768
2769                 if (t->byref) {
2770                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2771                         continue;
2772                 }
2773
2774                 switch (t->type) {
2775                 case MONO_TYPE_STRING:
2776                 case MONO_TYPE_CLASS:
2777                 case MONO_TYPE_ARRAY:
2778                 case MONO_TYPE_SZARRAY:
2779                 case MONO_TYPE_OBJECT:
2780                 case MONO_TYPE_PTR:
2781                 case MONO_TYPE_I:
2782                 case MONO_TYPE_U:
2783 #if !defined(__mono_ilp32__)
2784                 case MONO_TYPE_I8:
2785                 case MONO_TYPE_U8:
2786 #endif
2787                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2788                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2789                         break;
2790 #if defined(__mono_ilp32__)
2791                 case MONO_TYPE_I8:
2792                 case MONO_TYPE_U8:
2793                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2794                         p->regs [greg ++] = *(guint64*)(arg);
2795                         break;
2796 #endif
2797                 case MONO_TYPE_BOOLEAN:
2798                 case MONO_TYPE_U1:
2799                         p->regs [greg ++] = *(guint8*)(arg);
2800                         break;
2801                 case MONO_TYPE_I1:
2802                         p->regs [greg ++] = *(gint8*)(arg);
2803                         break;
2804                 case MONO_TYPE_I2:
2805                         p->regs [greg ++] = *(gint16*)(arg);
2806                         break;
2807                 case MONO_TYPE_U2:
2808                 case MONO_TYPE_CHAR:
2809                         p->regs [greg ++] = *(guint16*)(arg);
2810                         break;
2811                 case MONO_TYPE_I4:
2812                         p->regs [greg ++] = *(gint32*)(arg);
2813                         break;
2814                 case MONO_TYPE_U4:
2815                         p->regs [greg ++] = *(guint32*)(arg);
2816                         break;
2817                 case MONO_TYPE_GENERICINST:
2818                     if (MONO_TYPE_IS_REFERENCE (t)) {
2819                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2820                                 break;
2821                         } else {
2822                                 /* Fall through */
2823                         }
2824                 case MONO_TYPE_VALUETYPE: {
2825                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2826
2827                         g_assert (ainfo->storage == ArgValuetypeInReg);
2828                         if (ainfo->pair_storage [0] != ArgNone) {
2829                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2830                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2831                         }
2832                         if (ainfo->pair_storage [1] != ArgNone) {
2833                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2834                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2835                         }
2836                         break;
2837                 }
2838                 default:
2839                         g_assert_not_reached ();
2840                 }
2841         }
2842
2843         g_assert (greg <= PARAM_REGS);
2844 }
2845
2846 /*
2847  * mono_arch_finish_dyn_call:
2848  *
2849  *   Store the result of a dyn call into the return value buffer passed to
2850  * start_dyn_call ().
2851  * This function should be as fast as possible, any work which does not depend
2852  * on the actual values of the arguments should be done in
2853  * mono_arch_dyn_call_prepare ().
2854  */
2855 void
2856 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2857 {
2858         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2859         MonoMethodSignature *sig = dinfo->sig;
2860         guint8 *ret = ((DynCallArgs*)buf)->ret;
2861         mgreg_t res = ((DynCallArgs*)buf)->res;
2862         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2863
2864         switch (sig_ret->type) {
2865         case MONO_TYPE_VOID:
2866                 *(gpointer*)ret = NULL;
2867                 break;
2868         case MONO_TYPE_STRING:
2869         case MONO_TYPE_CLASS:
2870         case MONO_TYPE_ARRAY:
2871         case MONO_TYPE_SZARRAY:
2872         case MONO_TYPE_OBJECT:
2873         case MONO_TYPE_I:
2874         case MONO_TYPE_U:
2875         case MONO_TYPE_PTR:
2876                 *(gpointer*)ret = GREG_TO_PTR(res);
2877                 break;
2878         case MONO_TYPE_I1:
2879                 *(gint8*)ret = res;
2880                 break;
2881         case MONO_TYPE_U1:
2882         case MONO_TYPE_BOOLEAN:
2883                 *(guint8*)ret = res;
2884                 break;
2885         case MONO_TYPE_I2:
2886                 *(gint16*)ret = res;
2887                 break;
2888         case MONO_TYPE_U2:
2889         case MONO_TYPE_CHAR:
2890                 *(guint16*)ret = res;
2891                 break;
2892         case MONO_TYPE_I4:
2893                 *(gint32*)ret = res;
2894                 break;
2895         case MONO_TYPE_U4:
2896                 *(guint32*)ret = res;
2897                 break;
2898         case MONO_TYPE_I8:
2899                 *(gint64*)ret = res;
2900                 break;
2901         case MONO_TYPE_U8:
2902                 *(guint64*)ret = res;
2903                 break;
2904         case MONO_TYPE_GENERICINST:
2905                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2906                         *(gpointer*)ret = GREG_TO_PTR(res);
2907                         break;
2908                 } else {
2909                         /* Fall through */
2910                 }
2911         case MONO_TYPE_VALUETYPE:
2912                 if (dinfo->cinfo->vtype_retaddr) {
2913                         /* Nothing to do */
2914                 } else {
2915                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2916
2917                         g_assert (ainfo->storage == ArgValuetypeInReg);
2918
2919                         if (ainfo->pair_storage [0] != ArgNone) {
2920                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2921                                 ((mgreg_t*)ret)[0] = res;
2922                         }
2923
2924                         g_assert (ainfo->pair_storage [1] == ArgNone);
2925                 }
2926                 break;
2927         default:
2928                 g_assert_not_reached ();
2929         }
2930 }
2931
2932 /* emit an exception if condition is fail */
2933 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2934         do {                                                        \
2935                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2936                 if (tins == NULL) {                                                                             \
2937                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2938                                         MONO_PATCH_INFO_EXC, exc_name);  \
2939                         x86_branch32 (code, cond, 0, signed);               \
2940                 } else {        \
2941                         EMIT_COND_BRANCH (tins, cond, signed);  \
2942                 }                       \
2943         } while (0);
2944
2945 #define EMIT_FPCOMPARE(code) do { \
2946         amd64_fcompp (code); \
2947         amd64_fnstsw (code); \
2948 } while (0);
2949
2950 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2951     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2952         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2953         amd64_ ##op (code); \
2954         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2955         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2956 } while (0);
2957
2958 static guint8*
2959 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2960 {
2961         gboolean no_patch = FALSE;
2962
2963         /*
2964          * FIXME: Add support for thunks
2965          */
2966         {
2967                 gboolean near_call = FALSE;
2968
2969                 /*
2970                  * Indirect calls are expensive so try to make a near call if possible.
2971                  * The caller memory is allocated by the code manager so it is
2972                  * guaranteed to be at a 32 bit offset.
2973                  */
2974
2975                 if (patch_type != MONO_PATCH_INFO_ABS) {
2976                         /* The target is in memory allocated using the code manager */
2977                         near_call = TRUE;
2978
2979                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2980                                 if (((MonoMethod*)data)->klass->image->aot_module)
2981                                         /* The callee might be an AOT method */
2982                                         near_call = FALSE;
2983                                 if (((MonoMethod*)data)->dynamic)
2984                                         /* The target is in malloc-ed memory */
2985                                         near_call = FALSE;
2986                         }
2987
2988                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2989                                 /*
2990                                  * The call might go directly to a native function without
2991                                  * the wrapper.
2992                                  */
2993                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2994                                 if (mi) {
2995                                         gconstpointer target = mono_icall_get_wrapper (mi);
2996                                         if ((((guint64)target) >> 32) != 0)
2997                                                 near_call = FALSE;
2998                                 }
2999                         }
3000                 }
3001                 else {
3002                         MonoJumpInfo *jinfo = NULL;
3003
3004                         if (cfg->abs_patches)
3005                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3006                         if (jinfo) {
3007                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3008                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3009                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3010                                                 near_call = TRUE;
3011                                         no_patch = TRUE;
3012                                 } else {
3013                                         /*
3014                                          * This is not really an optimization, but required because the
3015                                          * generic class init trampolines use R11 to pass the vtable.
3016                                          */
3017                                         near_call = TRUE;
3018                                 }
3019                         } else {
3020                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3021                                 if (info) {
3022                                         if (info->func == info->wrapper) {
3023                                                 /* No wrapper */
3024                                                 if ((((guint64)info->func) >> 32) == 0)
3025                                                         near_call = TRUE;
3026                                         }
3027                                         else {
3028                                                 /* See the comment in mono_codegen () */
3029                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3030                                                         near_call = TRUE;
3031                                         }
3032                                 }
3033                                 else if ((((guint64)data) >> 32) == 0) {
3034                                         near_call = TRUE;
3035                                         no_patch = TRUE;
3036                                 }
3037                         }
3038                 }
3039
3040                 if (cfg->method->dynamic)
3041                         /* These methods are allocated using malloc */
3042                         near_call = FALSE;
3043
3044 #ifdef MONO_ARCH_NOMAP32BIT
3045                 near_call = FALSE;
3046 #endif
3047 #if defined(__native_client__)
3048                 /* Always use near_call == TRUE for Native Client */
3049                 near_call = TRUE;
3050 #endif
3051                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3052                 if (optimize_for_xen)
3053                         near_call = FALSE;
3054
3055                 if (cfg->compile_aot) {
3056                         near_call = TRUE;
3057                         no_patch = TRUE;
3058                 }
3059
3060                 if (near_call) {
3061                         /*
3062                          * Align the call displacement to an address divisible by 4 so it does
3063                          * not span cache lines. This is required for code patching to work on SMP
3064                          * systems.
3065                          */
3066                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3067                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3068                                 amd64_padding (code, pad_size);
3069                         }
3070                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3071                         amd64_call_code (code, 0);
3072                 }
3073                 else {
3074                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3075                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3076                         amd64_call_reg (code, GP_SCRATCH_REG);
3077                 }
3078         }
3079
3080         return code;
3081 }
3082
3083 static inline guint8*
3084 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3085 {
3086 #ifdef HOST_WIN32
3087         if (win64_adjust_stack)
3088                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3089 #endif
3090         code = emit_call_body (cfg, code, patch_type, data);
3091 #ifdef HOST_WIN32
3092         if (win64_adjust_stack)
3093                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3094 #endif
3095
3096         return code;
3097 }
3098
3099 static inline int
3100 store_membase_imm_to_store_membase_reg (int opcode)
3101 {
3102         switch (opcode) {
3103         case OP_STORE_MEMBASE_IMM:
3104                 return OP_STORE_MEMBASE_REG;
3105         case OP_STOREI4_MEMBASE_IMM:
3106                 return OP_STOREI4_MEMBASE_REG;
3107         case OP_STOREI8_MEMBASE_IMM:
3108                 return OP_STOREI8_MEMBASE_REG;
3109         }
3110
3111         return -1;
3112 }
3113
3114 #ifndef DISABLE_JIT
3115
3116 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3117
3118 /*
3119  * mono_arch_peephole_pass_1:
3120  *
3121  *   Perform peephole opts which should/can be performed before local regalloc
3122  */
3123 void
3124 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3125 {
3126         MonoInst *ins, *n;
3127
3128         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3129                 MonoInst *last_ins = ins->prev;
3130
3131                 switch (ins->opcode) {
3132                 case OP_ADD_IMM:
3133                 case OP_IADD_IMM:
3134                 case OP_LADD_IMM:
3135                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3136                                 /*
3137                                  * X86_LEA is like ADD, but doesn't have the
3138                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3139                                  * its operand to 64 bit.
3140                                  */
3141                                 ins->opcode = OP_X86_LEA_MEMBASE;
3142                                 ins->inst_basereg = ins->sreg1;
3143                         }
3144                         break;
3145                 case OP_LXOR:
3146                 case OP_IXOR:
3147                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3148                                 MonoInst *ins2;
3149
3150                                 /*
3151                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3152                                  * the latter has length 2-3 instead of 6 (reverse constant
3153                                  * propagation). These instruction sequences are very common
3154                                  * in the initlocals bblock.
3155                                  */
3156                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3157                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3158                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3159                                                 ins2->sreg1 = ins->dreg;
3160                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3161                                                 /* Continue */
3162                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3163                                                 NULLIFY_INS (ins2);
3164                                                 /* Continue */
3165                                         } else {
3166                                                 break;
3167                                         }
3168                                 }
3169                         }
3170                         break;
3171                 case OP_COMPARE_IMM:
3172                 case OP_LCOMPARE_IMM:
3173                         /* OP_COMPARE_IMM (reg, 0)
3174                          * -->
3175                          * OP_AMD64_TEST_NULL (reg)
3176                          */
3177                         if (!ins->inst_imm)
3178                                 ins->opcode = OP_AMD64_TEST_NULL;
3179                         break;
3180                 case OP_ICOMPARE_IMM:
3181                         if (!ins->inst_imm)
3182                                 ins->opcode = OP_X86_TEST_NULL;
3183                         break;
3184                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3185                         /*
3186                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3187                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3188                          * -->
3189                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3190                          * OP_COMPARE_IMM reg, imm
3191                          *
3192                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3193                          */
3194                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3195                             ins->inst_basereg == last_ins->inst_destbasereg &&
3196                             ins->inst_offset == last_ins->inst_offset) {
3197                                         ins->opcode = OP_ICOMPARE_IMM;
3198                                         ins->sreg1 = last_ins->sreg1;
3199
3200                                         /* check if we can remove cmp reg,0 with test null */
3201                                         if (!ins->inst_imm)
3202                                                 ins->opcode = OP_X86_TEST_NULL;
3203                                 }
3204
3205                         break;
3206                 }
3207
3208                 mono_peephole_ins (bb, ins);
3209         }
3210 }
3211
3212 void
3213 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3214 {
3215         MonoInst *ins, *n;
3216
3217         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3218                 switch (ins->opcode) {
3219                 case OP_ICONST:
3220                 case OP_I8CONST: {
3221                         /* reg = 0 -> XOR (reg, reg) */
3222                         /* XOR sets cflags on x86, so we cant do it always */
3223                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3224                                 ins->opcode = OP_LXOR;
3225                                 ins->sreg1 = ins->dreg;
3226                                 ins->sreg2 = ins->dreg;
3227                                 /* Fall through */
3228                         } else {
3229                                 break;
3230                         }
3231                 }
3232                 case OP_LXOR:
3233                         /*
3234                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3235                          * 0 result into 64 bits.
3236                          */
3237                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3238                                 ins->opcode = OP_IXOR;
3239                         }
3240                         /* Fall through */
3241                 case OP_IXOR:
3242                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3243                                 MonoInst *ins2;
3244
3245                                 /*
3246                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3247                                  * the latter has length 2-3 instead of 6 (reverse constant
3248                                  * propagation). These instruction sequences are very common
3249                                  * in the initlocals bblock.
3250                                  */
3251                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3252                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3253                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3254                                                 ins2->sreg1 = ins->dreg;
3255                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3256                                                 /* Continue */
3257                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3258                                                 NULLIFY_INS (ins2);
3259                                                 /* Continue */
3260                                         } else {
3261                                                 break;
3262                                         }
3263                                 }
3264                         }
3265                         break;
3266                 case OP_IADD_IMM:
3267                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3268                                 ins->opcode = OP_X86_INC_REG;
3269                         break;
3270                 case OP_ISUB_IMM:
3271                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3272                                 ins->opcode = OP_X86_DEC_REG;
3273                         break;
3274                 }
3275
3276                 mono_peephole_ins (bb, ins);
3277         }
3278 }
3279
3280 #define NEW_INS(cfg,ins,dest,op) do {   \
3281                 MONO_INST_NEW ((cfg), (dest), (op)); \
3282         (dest)->cil_code = (ins)->cil_code; \
3283         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3284         } while (0)
3285
3286 /*
3287  * mono_arch_lowering_pass:
3288  *
3289  *  Converts complex opcodes into simpler ones so that each IR instruction
3290  * corresponds to one machine instruction.
3291  */
3292 void
3293 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3294 {
3295         MonoInst *ins, *n, *temp;
3296
3297         /*
3298          * FIXME: Need to add more instructions, but the current machine
3299          * description can't model some parts of the composite instructions like
3300          * cdq.
3301          */
3302         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3303                 switch (ins->opcode) {
3304                 case OP_DIV_IMM:
3305                 case OP_REM_IMM:
3306                 case OP_IDIV_IMM:
3307                 case OP_IDIV_UN_IMM:
3308                 case OP_IREM_UN_IMM:
3309                 case OP_LREM_IMM:
3310                 case OP_IREM_IMM:
3311                         mono_decompose_op_imm (cfg, bb, ins);
3312                         break;
3313                 case OP_COMPARE_IMM:
3314                 case OP_LCOMPARE_IMM:
3315                         if (!amd64_is_imm32 (ins->inst_imm)) {
3316                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3317                                 temp->inst_c0 = ins->inst_imm;
3318                                 temp->dreg = mono_alloc_ireg (cfg);
3319                                 ins->opcode = OP_COMPARE;
3320                                 ins->sreg2 = temp->dreg;
3321                         }
3322                         break;
3323 #ifndef __mono_ilp32__
3324                 case OP_LOAD_MEMBASE:
3325 #endif
3326                 case OP_LOADI8_MEMBASE:
3327 #ifndef __native_client_codegen__
3328                 /*  Don't generate memindex opcodes (to simplify */
3329                 /*  read sandboxing) */
3330                         if (!amd64_is_imm32 (ins->inst_offset)) {
3331                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3332                                 temp->inst_c0 = ins->inst_offset;
3333                                 temp->dreg = mono_alloc_ireg (cfg);
3334                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3335                                 ins->inst_indexreg = temp->dreg;
3336                         }
3337 #endif
3338                         break;
3339 #ifndef __mono_ilp32__
3340                 case OP_STORE_MEMBASE_IMM:
3341 #endif
3342                 case OP_STOREI8_MEMBASE_IMM:
3343                         if (!amd64_is_imm32 (ins->inst_imm)) {
3344                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3345                                 temp->inst_c0 = ins->inst_imm;
3346                                 temp->dreg = mono_alloc_ireg (cfg);
3347                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3348                                 ins->sreg1 = temp->dreg;
3349                         }
3350                         break;
3351 #ifdef MONO_ARCH_SIMD_INTRINSICS
3352                 case OP_EXPAND_I1: {
3353                                 int temp_reg1 = mono_alloc_ireg (cfg);
3354                                 int temp_reg2 = mono_alloc_ireg (cfg);
3355                                 int original_reg = ins->sreg1;
3356
3357                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3358                                 temp->sreg1 = original_reg;
3359                                 temp->dreg = temp_reg1;
3360
3361                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3362                                 temp->sreg1 = temp_reg1;
3363                                 temp->dreg = temp_reg2;
3364                                 temp->inst_imm = 8;
3365
3366                                 NEW_INS (cfg, ins, temp, OP_LOR);
3367                                 temp->sreg1 = temp->dreg = temp_reg2;
3368                                 temp->sreg2 = temp_reg1;
3369
3370                                 ins->opcode = OP_EXPAND_I2;
3371                                 ins->sreg1 = temp_reg2;
3372                         }
3373                         break;
3374 #endif
3375                 default:
3376                         break;
3377                 }
3378         }
3379
3380         bb->max_vreg = cfg->next_vreg;
3381 }
3382
3383 static const int
3384 branch_cc_table [] = {
3385         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3386         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3387         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3388 };
3389
3390 /* Maps CMP_... constants to X86_CC_... constants */
3391 static const int
3392 cc_table [] = {
3393         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3394         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3395 };
3396
3397 static const int
3398 cc_signed_table [] = {
3399         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3400         FALSE, FALSE, FALSE, FALSE
3401 };
3402
3403 /*#include "cprop.c"*/
3404
3405 static unsigned char*
3406 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3407 {
3408         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3409
3410         if (size == 1)
3411                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3412         else if (size == 2)
3413                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3414         return code;
3415 }
3416
3417 static unsigned char*
3418 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3419 {
3420         int sreg = tree->sreg1;
3421         int need_touch = FALSE;
3422
3423 #if defined(HOST_WIN32)
3424                 need_touch = TRUE;
3425 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3426         if (!tree->flags & MONO_INST_INIT)
3427                 need_touch = TRUE;
3428 #endif
3429
3430         if (need_touch) {
3431                 guint8* br[5];
3432
3433                 /*
3434                  * Under Windows:
3435                  * If requested stack size is larger than one page,
3436                  * perform stack-touch operation
3437                  */
3438                 /*
3439                  * Generate stack probe code.
3440                  * Under Windows, it is necessary to allocate one page at a time,
3441                  * "touching" stack after each successful sub-allocation. This is
3442                  * because of the way stack growth is implemented - there is a
3443                  * guard page before the lowest stack page that is currently commited.
3444                  * Stack normally grows sequentially so OS traps access to the
3445                  * guard page and commits more pages when needed.
3446                  */
3447                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3448                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3449
3450                 br[2] = code; /* loop */
3451                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3452                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3453                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3454                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3455                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3456                 amd64_patch (br[3], br[2]);
3457                 amd64_test_reg_reg (code, sreg, sreg);
3458                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3459                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3460
3461                 br[1] = code; x86_jump8 (code, 0);
3462
3463                 amd64_patch (br[0], code);
3464                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3465                 amd64_patch (br[1], code);
3466                 amd64_patch (br[4], code);
3467         }
3468         else
3469                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3470
3471         if (tree->flags & MONO_INST_INIT) {
3472                 int offset = 0;
3473                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3474                         amd64_push_reg (code, AMD64_RAX);
3475                         offset += 8;
3476                 }
3477                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3478                         amd64_push_reg (code, AMD64_RCX);
3479                         offset += 8;
3480                 }
3481                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3482                         amd64_push_reg (code, AMD64_RDI);
3483                         offset += 8;
3484                 }
3485
3486                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3487                 if (sreg != AMD64_RCX)
3488                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3489                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3490
3491                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3492                 if (cfg->param_area && cfg->arch.no_pushes)
3493                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3494                 amd64_cld (code);
3495 #if defined(__default_codegen__)
3496                 amd64_prefix (code, X86_REP_PREFIX);
3497                 amd64_stosl (code);
3498 #elif defined(__native_client_codegen__)
3499                 /* NaCl stos pseudo-instruction */
3500                 amd64_codegen_pre(code);
3501                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3502                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3503                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3504                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3505                 amd64_prefix (code, X86_REP_PREFIX);
3506                 amd64_stosl (code);
3507                 amd64_codegen_post(code);
3508 #endif /* __native_client_codegen__ */
3509
3510                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3511                         amd64_pop_reg (code, AMD64_RDI);
3512                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3513                         amd64_pop_reg (code, AMD64_RCX);
3514                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3515                         amd64_pop_reg (code, AMD64_RAX);
3516         }
3517         return code;
3518 }
3519
3520 static guint8*
3521 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3522 {
3523         CallInfo *cinfo;
3524         guint32 quad;
3525
3526         /* Move return value to the target register */
3527         /* FIXME: do this in the local reg allocator */
3528         switch (ins->opcode) {
3529         case OP_CALL:
3530         case OP_CALL_REG:
3531         case OP_CALL_MEMBASE:
3532         case OP_LCALL:
3533         case OP_LCALL_REG:
3534         case OP_LCALL_MEMBASE:
3535                 g_assert (ins->dreg == AMD64_RAX);
3536                 break;
3537         case OP_FCALL:
3538         case OP_FCALL_REG:
3539         case OP_FCALL_MEMBASE:
3540                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3541                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3542                 }
3543                 else {
3544                         if (ins->dreg != AMD64_XMM0)
3545                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3546                 }
3547                 break;
3548         case OP_VCALL:
3549         case OP_VCALL_REG:
3550         case OP_VCALL_MEMBASE:
3551         case OP_VCALL2:
3552         case OP_VCALL2_REG:
3553         case OP_VCALL2_MEMBASE:
3554                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3555                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3556                         MonoInst *loc = cfg->arch.vret_addr_loc;
3557
3558                         /* Load the destination address */
3559                         g_assert (loc->opcode == OP_REGOFFSET);
3560                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3561
3562                         for (quad = 0; quad < 2; quad ++) {
3563                                 switch (cinfo->ret.pair_storage [quad]) {
3564                                 case ArgInIReg:
3565                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3566                                         break;
3567                                 case ArgInFloatSSEReg:
3568                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3569                                         break;
3570                                 case ArgInDoubleSSEReg:
3571                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3572                                         break;
3573                                 case ArgNone:
3574                                         break;
3575                                 default:
3576                                         NOT_IMPLEMENTED;
3577                                 }
3578                         }
3579                 }
3580                 break;
3581         }
3582
3583         return code;
3584 }
3585
3586 #endif /* DISABLE_JIT */
3587
3588 #ifdef __APPLE__
3589 static int tls_gs_offset;
3590 #endif
3591
3592 gboolean
3593 mono_amd64_have_tls_get (void)
3594 {
3595 #ifdef __APPLE__
3596         static gboolean have_tls_get = FALSE;
3597         static gboolean inited = FALSE;
3598         guint8 *ins;
3599
3600         if (inited)
3601                 return have_tls_get;
3602
3603         ins = (guint8*)pthread_getspecific;
3604
3605         /*
3606          * We're looking for these two instructions:
3607          *
3608          * mov    %gs:[offset](,%rdi,8),%rax
3609          * retq
3610          */
3611         have_tls_get = ins [0] == 0x65 &&
3612                        ins [1] == 0x48 &&
3613                        ins [2] == 0x8b &&
3614                        ins [3] == 0x04 &&
3615                        ins [4] == 0xfd &&
3616                        ins [6] == 0x00 &&
3617                        ins [7] == 0x00 &&
3618                        ins [8] == 0x00 &&
3619                        ins [9] == 0xc3;
3620
3621         inited = TRUE;
3622
3623         tls_gs_offset = ins[5];
3624
3625         return have_tls_get;
3626 #else
3627         return TRUE;
3628 #endif
3629 }
3630
3631 int
3632 mono_amd64_get_tls_gs_offset (void)
3633 {
3634 #ifdef TARGET_OSX
3635         return tls_gs_offset;
3636 #else
3637         g_assert_not_reached ();
3638         return -1;
3639 #endif
3640 }
3641
3642 /*
3643  * mono_amd64_emit_tls_get:
3644  * @code: buffer to store code to
3645  * @dreg: hard register where to place the result
3646  * @tls_offset: offset info
3647  *
3648  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3649  * the dreg register the item in the thread local storage identified
3650  * by tls_offset.
3651  *
3652  * Returns: a pointer to the end of the stored code
3653  */
3654 guint8*
3655 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3656 {
3657 #ifdef HOST_WIN32
3658         g_assert (tls_offset < 64);
3659         x86_prefix (code, X86_GS_PREFIX);
3660         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3661 #elif defined(__APPLE__)
3662         x86_prefix (code, X86_GS_PREFIX);
3663         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3664 #else
3665         if (optimize_for_xen) {
3666                 x86_prefix (code, X86_FS_PREFIX);
3667                 amd64_mov_reg_mem (code, dreg, 0, 8);
3668                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3669         } else {
3670                 x86_prefix (code, X86_FS_PREFIX);
3671                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3672         }
3673 #endif
3674         return code;
3675 }
3676
3677 static guint8*
3678 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3679 {
3680         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3681 #ifdef TARGET_OSX
3682         if (dreg != offset_reg)
3683                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3684         amd64_prefix (code, X86_GS_PREFIX);
3685         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3686 #elif defined(__linux__)
3687         int tmpreg = -1;
3688
3689         if (dreg == offset_reg) {
3690                 /* Use a temporary reg by saving it to the redzone */
3691                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3692                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3693                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3694                 offset_reg = tmpreg;
3695         }
3696         x86_prefix (code, X86_FS_PREFIX);
3697         amd64_mov_reg_mem (code, dreg, 0, 8);
3698         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3699         if (tmpreg != -1)
3700                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3701 #else
3702         g_assert_not_reached ();
3703 #endif
3704         return code;
3705 }
3706
3707 static guint8*
3708 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3709 {
3710 #ifdef HOST_WIN32
3711         g_assert_not_reached ();
3712 #elif defined(__APPLE__)
3713         x86_prefix (code, X86_GS_PREFIX);
3714         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3715 #else
3716         g_assert (!optimize_for_xen);
3717         x86_prefix (code, X86_FS_PREFIX);
3718         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3719 #endif
3720         return code;
3721 }
3722
3723 static guint8*
3724 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3725 {
3726         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3727 #ifdef HOST_WIN32
3728         g_assert_not_reached ();
3729 #elif defined(__APPLE__)
3730         x86_prefix (code, X86_GS_PREFIX);
3731         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3732 #else
3733         x86_prefix (code, X86_FS_PREFIX);
3734         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3735 #endif
3736         return code;
3737 }
3738
3739  /*
3740  * mono_arch_translate_tls_offset:
3741  *
3742  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3743  */
3744 int
3745 mono_arch_translate_tls_offset (int offset)
3746 {
3747 #ifdef __APPLE__
3748         return tls_gs_offset + (offset * 8);
3749 #else
3750         return offset;
3751 #endif
3752 }
3753
3754 /*
3755  * emit_setup_lmf:
3756  *
3757  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3758  */
3759 static guint8*
3760 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3761 {
3762         /*
3763          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3764          */
3765         /*
3766          * sp is saved right before calls but we need to save it here too so
3767          * async stack walks would work.
3768          */
3769         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3770         /* Save rbp */
3771         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3772         if (cfg->arch.omit_fp && cfa_offset != -1)
3773                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp))));
3774
3775         /* These can't contain refs */
3776         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3777 #ifdef HOST_WIN32
3778         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3779 #endif
3780         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3781         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3782         /* These are handled automatically by the stack marking code */
3783         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3784
3785         return code;
3786 }
3787
3788 #ifdef HOST_WIN32
3789 /*
3790  * emit_push_lmf:
3791  *
3792  *   Emit code to push an LMF structure on the LMF stack.
3793  */
3794 static guint8*
3795 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3796 {
3797         if (jit_tls_offset != -1) {
3798                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, jit_tls_offset);
3799                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3800         } else {
3801                 /*
3802                  * The call might clobber argument registers, but they are already
3803                  * saved to the stack/global regs.
3804                  */
3805                 if (args_clobbered)
3806                         *args_clobbered = TRUE;
3807                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3808                                                   (gpointer)"mono_get_lmf_addr", TRUE);
3809         }
3810
3811         /* Save lmf_addr */
3812         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3813         /* Save previous_lmf */
3814         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3815         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3816         /* Set new lmf */
3817         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3818         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3819
3820         return code;
3821 }
3822 #endif
3823
3824 #ifdef HOST_WIN32
3825 /*
3826  * emit_pop_lmf:
3827  *
3828  *   Emit code to pop an LMF structure from the LMF stack.
3829  */
3830 static guint8*
3831 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3832 {
3833         /* Restore previous lmf */
3834         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3835         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3836         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3837
3838         return code;
3839 }
3840 #endif
3841
3842 #define REAL_PRINT_REG(text,reg) \
3843 mono_assert (reg >= 0); \
3844 amd64_push_reg (code, AMD64_RAX); \
3845 amd64_push_reg (code, AMD64_RDX); \
3846 amd64_push_reg (code, AMD64_RCX); \
3847 amd64_push_reg (code, reg); \
3848 amd64_push_imm (code, reg); \
3849 amd64_push_imm (code, text " %d %p\n"); \
3850 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3851 amd64_call_reg (code, AMD64_RAX); \
3852 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3853 amd64_pop_reg (code, AMD64_RCX); \
3854 amd64_pop_reg (code, AMD64_RDX); \
3855 amd64_pop_reg (code, AMD64_RAX);
3856
3857 /* benchmark and set based on cpu */
3858 #define LOOP_ALIGNMENT 8
3859 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3860
3861 #ifndef DISABLE_JIT
3862 void
3863 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3864 {
3865         MonoInst *ins;
3866         MonoCallInst *call;
3867         guint offset;
3868         guint8 *code = cfg->native_code + cfg->code_len;
3869         MonoInst *last_ins = NULL;
3870         guint last_offset = 0;
3871         int max_len;
3872
3873         /* Fix max_offset estimate for each successor bb */
3874         if (cfg->opt & MONO_OPT_BRANCH) {
3875                 int current_offset = cfg->code_len;
3876                 MonoBasicBlock *current_bb;
3877                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3878                         current_bb->max_offset = current_offset;
3879                         current_offset += current_bb->max_length;
3880                 }
3881         }
3882
3883         if (cfg->opt & MONO_OPT_LOOP) {
3884                 int pad, align = LOOP_ALIGNMENT;
3885                 /* set alignment depending on cpu */
3886                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3887                         pad = align - pad;
3888                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3889                         amd64_padding (code, pad);
3890                         cfg->code_len += pad;
3891                         bb->native_offset = cfg->code_len;
3892                 }
3893         }
3894
3895 #if defined(__native_client_codegen__)
3896         /* For Native Client, all indirect call/jump targets must be */
3897         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3898         /* indirectly as well.                                       */
3899         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3900                                       (bb->flags & BB_EXCEPTION_HANDLER);
3901
3902         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3903                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3904                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3905                 cfg->code_len += pad;
3906                 bb->native_offset = cfg->code_len;
3907         }
3908 #endif  /*__native_client_codegen__*/
3909
3910         if (cfg->verbose_level > 2)
3911                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3912
3913         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3914                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3915                 g_assert (!cfg->compile_aot);
3916
3917                 cov->data [bb->dfn].cil_code = bb->cil_code;
3918                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3919                 /* this is not thread save, but good enough */
3920                 amd64_inc_membase (code, AMD64_R11, 0);
3921         }
3922
3923         offset = code - cfg->native_code;
3924
3925         mono_debug_open_block (cfg, bb, offset);
3926
3927     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3928                 x86_breakpoint (code);
3929
3930         MONO_BB_FOR_EACH_INS (bb, ins) {
3931                 offset = code - cfg->native_code;
3932
3933                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3934
3935 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3936
3937                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3938                         cfg->code_size *= 2;
3939                         cfg->native_code = mono_realloc_native_code(cfg);
3940                         code = cfg->native_code + offset;
3941                         cfg->stat_code_reallocs++;
3942                 }
3943
3944                 if (cfg->debug_info)
3945                         mono_debug_record_line_number (cfg, ins, offset);
3946
3947                 switch (ins->opcode) {
3948                 case OP_BIGMUL:
3949                         amd64_mul_reg (code, ins->sreg2, TRUE);
3950                         break;
3951                 case OP_BIGMUL_UN:
3952                         amd64_mul_reg (code, ins->sreg2, FALSE);
3953                         break;
3954                 case OP_X86_SETEQ_MEMBASE:
3955                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3956                         break;
3957                 case OP_STOREI1_MEMBASE_IMM:
3958                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3959                         break;
3960                 case OP_STOREI2_MEMBASE_IMM:
3961                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3962                         break;
3963                 case OP_STOREI4_MEMBASE_IMM:
3964                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3965                         break;
3966                 case OP_STOREI1_MEMBASE_REG:
3967                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3968                         break;
3969                 case OP_STOREI2_MEMBASE_REG:
3970                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3971                         break;
3972                 /* In AMD64 NaCl, pointers are 4 bytes, */
3973                 /*  so STORE_* != STOREI8_*. Likewise below. */
3974                 case OP_STORE_MEMBASE_REG:
3975                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3976                         break;
3977                 case OP_STOREI8_MEMBASE_REG:
3978                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3979                         break;
3980                 case OP_STOREI4_MEMBASE_REG:
3981                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3982                         break;
3983                 case OP_STORE_MEMBASE_IMM:
3984 #ifndef __native_client_codegen__
3985                         /* In NaCl, this could be a PCONST type, which could */
3986                         /* mean a pointer type was copied directly into the  */
3987                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3988                         /* the value would be 0x00000000FFFFFFFF which is    */
3989                         /* not proper for an imm32 unless you cast it.       */
3990                         g_assert (amd64_is_imm32 (ins->inst_imm));
3991 #endif
3992                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3993                         break;
3994                 case OP_STOREI8_MEMBASE_IMM:
3995                         g_assert (amd64_is_imm32 (ins->inst_imm));
3996                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3997                         break;
3998                 case OP_LOAD_MEM:
3999 #ifdef __mono_ilp32__
4000                         /* In ILP32, pointers are 4 bytes, so separate these */
4001                         /* cases, use literal 8 below where we really want 8 */
4002                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4003                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4004                         break;
4005 #endif
4006                 case OP_LOADI8_MEM:
4007                         // FIXME: Decompose this earlier
4008                         if (amd64_is_imm32 (ins->inst_imm))
4009                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4010                         else {
4011                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4012                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4013                         }
4014                         break;
4015                 case OP_LOADI4_MEM:
4016                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4017                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4018                         break;
4019                 case OP_LOADU4_MEM:
4020                         // FIXME: Decompose this earlier
4021                         if (amd64_is_imm32 (ins->inst_imm))
4022                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4023                         else {
4024                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4025                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4026                         }
4027                         break;
4028                 case OP_LOADU1_MEM:
4029                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4030                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4031                         break;
4032                 case OP_LOADU2_MEM:
4033                         /* For NaCl, pointers are 4 bytes, so separate these */
4034                         /* cases, use literal 8 below where we really want 8 */
4035                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4036                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4037                         break;
4038                 case OP_LOAD_MEMBASE:
4039                         g_assert (amd64_is_imm32 (ins->inst_offset));
4040                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4041                         break;
4042                 case OP_LOADI8_MEMBASE:
4043                         /* Use literal 8 instead of sizeof pointer or */
4044                         /* register, we really want 8 for this opcode */
4045                         g_assert (amd64_is_imm32 (ins->inst_offset));
4046                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4047                         break;
4048                 case OP_LOADI4_MEMBASE:
4049                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4050                         break;
4051                 case OP_LOADU4_MEMBASE:
4052                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4053                         break;
4054                 case OP_LOADU1_MEMBASE:
4055                         /* The cpu zero extends the result into 64 bits */
4056                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4057                         break;
4058                 case OP_LOADI1_MEMBASE:
4059                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4060                         break;
4061                 case OP_LOADU2_MEMBASE:
4062                         /* The cpu zero extends the result into 64 bits */
4063                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4064                         break;
4065                 case OP_LOADI2_MEMBASE:
4066                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4067                         break;
4068                 case OP_AMD64_LOADI8_MEMINDEX:
4069                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4070                         break;
4071                 case OP_LCONV_TO_I1:
4072                 case OP_ICONV_TO_I1:
4073                 case OP_SEXT_I1:
4074                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4075                         break;
4076                 case OP_LCONV_TO_I2:
4077                 case OP_ICONV_TO_I2:
4078                 case OP_SEXT_I2:
4079                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4080                         break;
4081                 case OP_LCONV_TO_U1:
4082                 case OP_ICONV_TO_U1:
4083                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4084                         break;
4085                 case OP_LCONV_TO_U2:
4086                 case OP_ICONV_TO_U2:
4087                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4088                         break;
4089                 case OP_ZEXT_I4:
4090                         /* Clean out the upper word */
4091                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4092                         break;
4093                 case OP_SEXT_I4:
4094                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4095                         break;
4096                 case OP_COMPARE:
4097                 case OP_LCOMPARE:
4098                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4099                         break;
4100                 case OP_COMPARE_IMM:
4101 #if defined(__mono_ilp32__)
4102                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4103                         g_assert (amd64_is_imm32 (ins->inst_imm));
4104                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4105                         break;
4106 #endif
4107                 case OP_LCOMPARE_IMM:
4108                         g_assert (amd64_is_imm32 (ins->inst_imm));
4109                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4110                         break;
4111                 case OP_X86_COMPARE_REG_MEMBASE:
4112                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4113                         break;
4114                 case OP_X86_TEST_NULL:
4115                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4116                         break;
4117                 case OP_AMD64_TEST_NULL:
4118                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4119                         break;
4120
4121                 case OP_X86_ADD_REG_MEMBASE:
4122                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4123                         break;
4124                 case OP_X86_SUB_REG_MEMBASE:
4125                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4126                         break;
4127                 case OP_X86_AND_REG_MEMBASE:
4128                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4129                         break;
4130                 case OP_X86_OR_REG_MEMBASE:
4131                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4132                         break;
4133                 case OP_X86_XOR_REG_MEMBASE:
4134                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4135                         break;
4136
4137                 case OP_X86_ADD_MEMBASE_IMM:
4138                         /* FIXME: Make a 64 version too */
4139                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4140                         break;
4141                 case OP_X86_SUB_MEMBASE_IMM:
4142                         g_assert (amd64_is_imm32 (ins->inst_imm));
4143                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4144                         break;
4145                 case OP_X86_AND_MEMBASE_IMM:
4146                         g_assert (amd64_is_imm32 (ins->inst_imm));
4147                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4148                         break;
4149                 case OP_X86_OR_MEMBASE_IMM:
4150                         g_assert (amd64_is_imm32 (ins->inst_imm));
4151                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4152                         break;
4153                 case OP_X86_XOR_MEMBASE_IMM:
4154                         g_assert (amd64_is_imm32 (ins->inst_imm));
4155                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4156                         break;
4157                 case OP_X86_ADD_MEMBASE_REG:
4158                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4159                         break;
4160                 case OP_X86_SUB_MEMBASE_REG:
4161                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4162                         break;
4163                 case OP_X86_AND_MEMBASE_REG:
4164                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4165                         break;
4166                 case OP_X86_OR_MEMBASE_REG:
4167                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4168                         break;
4169                 case OP_X86_XOR_MEMBASE_REG:
4170                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4171                         break;
4172                 case OP_X86_INC_MEMBASE:
4173                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4174                         break;
4175                 case OP_X86_INC_REG:
4176                         amd64_inc_reg_size (code, ins->dreg, 4);
4177                         break;
4178                 case OP_X86_DEC_MEMBASE:
4179                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4180                         break;
4181                 case OP_X86_DEC_REG:
4182                         amd64_dec_reg_size (code, ins->dreg, 4);
4183                         break;
4184                 case OP_X86_MUL_REG_MEMBASE:
4185                 case OP_X86_MUL_MEMBASE_REG:
4186                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4187                         break;
4188                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4189                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4190                         break;
4191                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4192                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4193                         break;
4194                 case OP_AMD64_COMPARE_MEMBASE_REG:
4195                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4196                         break;
4197                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4198                         g_assert (amd64_is_imm32 (ins->inst_imm));
4199                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4200                         break;
4201                 case OP_X86_COMPARE_MEMBASE8_IMM:
4202                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4203                         break;
4204                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4205                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4206                         break;
4207                 case OP_AMD64_COMPARE_REG_MEMBASE:
4208                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4209                         break;
4210
4211                 case OP_AMD64_ADD_REG_MEMBASE:
4212                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4213                         break;
4214                 case OP_AMD64_SUB_REG_MEMBASE:
4215                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4216                         break;
4217                 case OP_AMD64_AND_REG_MEMBASE:
4218                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4219                         break;
4220                 case OP_AMD64_OR_REG_MEMBASE:
4221                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4222                         break;
4223                 case OP_AMD64_XOR_REG_MEMBASE:
4224                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4225                         break;
4226
4227                 case OP_AMD64_ADD_MEMBASE_REG:
4228                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4229                         break;
4230                 case OP_AMD64_SUB_MEMBASE_REG:
4231                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4232                         break;
4233                 case OP_AMD64_AND_MEMBASE_REG:
4234                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4235                         break;
4236                 case OP_AMD64_OR_MEMBASE_REG:
4237                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4238                         break;
4239                 case OP_AMD64_XOR_MEMBASE_REG:
4240                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4241                         break;
4242
4243                 case OP_AMD64_ADD_MEMBASE_IMM:
4244                         g_assert (amd64_is_imm32 (ins->inst_imm));
4245                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4246                         break;
4247                 case OP_AMD64_SUB_MEMBASE_IMM:
4248                         g_assert (amd64_is_imm32 (ins->inst_imm));
4249                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4250                         break;
4251                 case OP_AMD64_AND_MEMBASE_IMM:
4252                         g_assert (amd64_is_imm32 (ins->inst_imm));
4253                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4254                         break;
4255                 case OP_AMD64_OR_MEMBASE_IMM:
4256                         g_assert (amd64_is_imm32 (ins->inst_imm));
4257                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4258                         break;
4259                 case OP_AMD64_XOR_MEMBASE_IMM:
4260                         g_assert (amd64_is_imm32 (ins->inst_imm));
4261                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4262                         break;
4263
4264                 case OP_BREAK:
4265                         amd64_breakpoint (code);
4266                         break;
4267                 case OP_RELAXED_NOP:
4268                         x86_prefix (code, X86_REP_PREFIX);
4269                         x86_nop (code);
4270                         break;
4271                 case OP_HARD_NOP:
4272                         x86_nop (code);
4273                         break;
4274                 case OP_NOP:
4275                 case OP_DUMMY_USE:
4276                 case OP_DUMMY_STORE:
4277                 case OP_DUMMY_ICONST:
4278                 case OP_DUMMY_R8CONST:
4279                 case OP_NOT_REACHED:
4280                 case OP_NOT_NULL:
4281                         break;
4282                 case OP_SEQ_POINT: {
4283                         int i;
4284
4285                         /*
4286                          * Read from the single stepping trigger page. This will cause a
4287                          * SIGSEGV when single stepping is enabled.
4288                          * We do this _before_ the breakpoint, so single stepping after
4289                          * a breakpoint is hit will step to the next IL offset.
4290                          */
4291                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4292                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4293
4294                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4295                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4296                         }
4297
4298                         /*
4299                          * This is the address which is saved in seq points,
4300                          */
4301                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4302
4303                         if (cfg->compile_aot) {
4304                                 guint32 offset = code - cfg->native_code;
4305                                 guint32 val;
4306                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4307
4308                                 /* Load info var */
4309                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4310                                 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4311                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4312                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4313                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4314                         } else {
4315                                 /*
4316                                  * A placeholder for a possible breakpoint inserted by
4317                                  * mono_arch_set_breakpoint ().
4318                                  */
4319                                 for (i = 0; i < breakpoint_size; ++i)
4320                                         x86_nop (code);
4321                         }
4322                         /*
4323                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4324                          * to another IL offset.
4325                          */
4326                         x86_nop (code);
4327                         break;
4328                 }
4329                 case OP_ADDCC:
4330                 case OP_LADDCC:
4331                 case OP_LADD:
4332                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4333                         break;
4334                 case OP_ADC:
4335                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4336                         break;
4337                 case OP_ADD_IMM:
4338                 case OP_LADD_IMM:
4339                         g_assert (amd64_is_imm32 (ins->inst_imm));
4340                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4341                         break;
4342                 case OP_ADC_IMM:
4343                         g_assert (amd64_is_imm32 (ins->inst_imm));
4344                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4345                         break;
4346                 case OP_SUBCC:
4347                 case OP_LSUBCC:
4348                 case OP_LSUB:
4349                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4350                         break;
4351                 case OP_SBB:
4352                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4353                         break;
4354                 case OP_SUB_IMM:
4355                 case OP_LSUB_IMM:
4356                         g_assert (amd64_is_imm32 (ins->inst_imm));
4357                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4358                         break;
4359                 case OP_SBB_IMM:
4360                         g_assert (amd64_is_imm32 (ins->inst_imm));
4361                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4362                         break;
4363                 case OP_LAND:
4364                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4365                         break;
4366                 case OP_AND_IMM:
4367                 case OP_LAND_IMM:
4368                         g_assert (amd64_is_imm32 (ins->inst_imm));
4369                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4370                         break;
4371                 case OP_LMUL:
4372                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4373                         break;
4374                 case OP_MUL_IMM:
4375                 case OP_LMUL_IMM:
4376                 case OP_IMUL_IMM: {
4377                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4378
4379                         switch (ins->inst_imm) {
4380                         case 2:
4381                                 /* MOV r1, r2 */
4382                                 /* ADD r1, r1 */
4383                                 if (ins->dreg != ins->sreg1)
4384                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4385                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4386                                 break;
4387                         case 3:
4388                                 /* LEA r1, [r2 + r2*2] */
4389                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4390                                 break;
4391                         case 5:
4392                                 /* LEA r1, [r2 + r2*4] */
4393                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4394                                 break;
4395                         case 6:
4396                                 /* LEA r1, [r2 + r2*2] */
4397                                 /* ADD r1, r1          */
4398                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4399                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4400                                 break;
4401                         case 9:
4402                                 /* LEA r1, [r2 + r2*8] */
4403                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4404                                 break;
4405                         case 10:
4406                                 /* LEA r1, [r2 + r2*4] */
4407                                 /* ADD r1, r1          */
4408                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4409                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4410                                 break;
4411                         case 12:
4412                                 /* LEA r1, [r2 + r2*2] */
4413                                 /* SHL r1, 2           */
4414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4415                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4416                                 break;
4417                         case 25:
4418                                 /* LEA r1, [r2 + r2*4] */
4419                                 /* LEA r1, [r1 + r1*4] */
4420                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4421                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4422                                 break;
4423                         case 100:
4424                                 /* LEA r1, [r2 + r2*4] */
4425                                 /* SHL r1, 2           */
4426                                 /* LEA r1, [r1 + r1*4] */
4427                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4428                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4429                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4430                                 break;
4431                         default:
4432                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4433                                 break;
4434                         }
4435                         break;
4436                 }
4437                 case OP_LDIV:
4438                 case OP_LREM:
4439 #if defined( __native_client_codegen__ )
4440                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4441                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4442 #endif
4443                         /* Regalloc magic makes the div/rem cases the same */
4444                         if (ins->sreg2 == AMD64_RDX) {
4445                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4446                                 amd64_cdq (code);
4447                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4448                         } else {
4449                                 amd64_cdq (code);
4450                                 amd64_div_reg (code, ins->sreg2, TRUE);
4451                         }
4452                         break;
4453                 case OP_LDIV_UN:
4454                 case OP_LREM_UN:
4455 #if defined( __native_client_codegen__ )
4456                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4457                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4458 #endif
4459                         if (ins->sreg2 == AMD64_RDX) {
4460                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4461                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4462                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4463                         } else {
4464                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4465                                 amd64_div_reg (code, ins->sreg2, FALSE);
4466                         }
4467                         break;
4468                 case OP_IDIV:
4469                 case OP_IREM:
4470 #if defined( __native_client_codegen__ )
4471                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4472                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4473 #endif
4474                         if (ins->sreg2 == AMD64_RDX) {
4475                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4476                                 amd64_cdq_size (code, 4);
4477                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4478                         } else {
4479                                 amd64_cdq_size (code, 4);
4480                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4481                         }
4482                         break;
4483                 case OP_IDIV_UN:
4484                 case OP_IREM_UN:
4485 #if defined( __native_client_codegen__ )
4486                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4487                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4488 #endif
4489                         if (ins->sreg2 == AMD64_RDX) {
4490                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4491                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4492                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4493                         } else {
4494                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4495                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4496                         }
4497                         break;
4498                 case OP_LMUL_OVF:
4499                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4500                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4501                         break;
4502                 case OP_LOR:
4503                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4504                         break;
4505                 case OP_OR_IMM:
4506                 case OP_LOR_IMM:
4507                         g_assert (amd64_is_imm32 (ins->inst_imm));
4508                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4509                         break;
4510                 case OP_LXOR:
4511                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4512                         break;
4513                 case OP_XOR_IMM:
4514                 case OP_LXOR_IMM:
4515                         g_assert (amd64_is_imm32 (ins->inst_imm));
4516                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4517                         break;
4518                 case OP_LSHL:
4519                         g_assert (ins->sreg2 == AMD64_RCX);
4520                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4521                         break;
4522                 case OP_LSHR:
4523                         g_assert (ins->sreg2 == AMD64_RCX);
4524                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4525                         break;
4526                 case OP_SHR_IMM:
4527                         g_assert (amd64_is_imm32 (ins->inst_imm));
4528                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4529                         break;
4530                 case OP_LSHR_IMM:
4531                         g_assert (amd64_is_imm32 (ins->inst_imm));
4532                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4533                         break;
4534                 case OP_SHR_UN_IMM:
4535                         g_assert (amd64_is_imm32 (ins->inst_imm));
4536                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4537                         break;
4538                 case OP_LSHR_UN_IMM:
4539                         g_assert (amd64_is_imm32 (ins->inst_imm));
4540                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4541                         break;
4542                 case OP_LSHR_UN:
4543                         g_assert (ins->sreg2 == AMD64_RCX);
4544                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4545                         break;
4546                 case OP_SHL_IMM:
4547                         g_assert (amd64_is_imm32 (ins->inst_imm));
4548                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4549                         break;
4550                 case OP_LSHL_IMM:
4551                         g_assert (amd64_is_imm32 (ins->inst_imm));
4552                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4553                         break;
4554
4555                 case OP_IADDCC:
4556                 case OP_IADD:
4557                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4558                         break;
4559                 case OP_IADC:
4560                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4561                         break;
4562                 case OP_IADD_IMM:
4563                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4564                         break;
4565                 case OP_IADC_IMM:
4566                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4567                         break;
4568                 case OP_ISUBCC:
4569                 case OP_ISUB:
4570                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4571                         break;
4572                 case OP_ISBB:
4573                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4574                         break;
4575                 case OP_ISUB_IMM:
4576                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4577                         break;
4578                 case OP_ISBB_IMM:
4579                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4580                         break;
4581                 case OP_IAND:
4582                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4583                         break;
4584                 case OP_IAND_IMM:
4585                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4586                         break;
4587                 case OP_IOR:
4588                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4589                         break;
4590                 case OP_IOR_IMM:
4591                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4592                         break;
4593                 case OP_IXOR:
4594                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4595                         break;
4596                 case OP_IXOR_IMM:
4597                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4598                         break;
4599                 case OP_INEG:
4600                         amd64_neg_reg_size (code, ins->sreg1, 4);
4601                         break;
4602                 case OP_INOT:
4603                         amd64_not_reg_size (code, ins->sreg1, 4);
4604                         break;
4605                 case OP_ISHL:
4606                         g_assert (ins->sreg2 == AMD64_RCX);
4607                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4608                         break;
4609                 case OP_ISHR:
4610                         g_assert (ins->sreg2 == AMD64_RCX);
4611                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4612                         break;
4613                 case OP_ISHR_IMM:
4614                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4615                         break;
4616                 case OP_ISHR_UN_IMM:
4617                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4618                         break;
4619                 case OP_ISHR_UN:
4620                         g_assert (ins->sreg2 == AMD64_RCX);
4621                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4622                         break;
4623                 case OP_ISHL_IMM:
4624                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4625                         break;
4626                 case OP_IMUL:
4627                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4628                         break;
4629                 case OP_IMUL_OVF:
4630                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4631                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4632                         break;
4633                 case OP_IMUL_OVF_UN:
4634                 case OP_LMUL_OVF_UN: {
4635                         /* the mul operation and the exception check should most likely be split */
4636                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4637                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4638                         /*g_assert (ins->sreg2 == X86_EAX);
4639                         g_assert (ins->dreg == X86_EAX);*/
4640                         if (ins->sreg2 == X86_EAX) {
4641                                 non_eax_reg = ins->sreg1;
4642                         } else if (ins->sreg1 == X86_EAX) {
4643                                 non_eax_reg = ins->sreg2;
4644                         } else {
4645                                 /* no need to save since we're going to store to it anyway */
4646                                 if (ins->dreg != X86_EAX) {
4647                                         saved_eax = TRUE;
4648                                         amd64_push_reg (code, X86_EAX);
4649                                 }
4650                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4651                                 non_eax_reg = ins->sreg2;
4652                         }
4653                         if (ins->dreg == X86_EDX) {
4654                                 if (!saved_eax) {
4655                                         saved_eax = TRUE;
4656                                         amd64_push_reg (code, X86_EAX);
4657                                 }
4658                         } else {
4659                                 saved_edx = TRUE;
4660                                 amd64_push_reg (code, X86_EDX);
4661                         }
4662                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4663                         /* save before the check since pop and mov don't change the flags */
4664                         if (ins->dreg != X86_EAX)
4665                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4666                         if (saved_edx)
4667                                 amd64_pop_reg (code, X86_EDX);
4668                         if (saved_eax)
4669                                 amd64_pop_reg (code, X86_EAX);
4670                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4671                         break;
4672                 }
4673                 case OP_ICOMPARE:
4674                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4675                         break;
4676                 case OP_ICOMPARE_IMM:
4677                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4678                         break;
4679                 case OP_IBEQ:
4680                 case OP_IBLT:
4681                 case OP_IBGT:
4682                 case OP_IBGE:
4683                 case OP_IBLE:
4684                 case OP_LBEQ:
4685                 case OP_LBLT:
4686                 case OP_LBGT:
4687                 case OP_LBGE:
4688                 case OP_LBLE:
4689                 case OP_IBNE_UN:
4690                 case OP_IBLT_UN:
4691                 case OP_IBGT_UN:
4692                 case OP_IBGE_UN:
4693                 case OP_IBLE_UN:
4694                 case OP_LBNE_UN:
4695                 case OP_LBLT_UN:
4696                 case OP_LBGT_UN:
4697                 case OP_LBGE_UN:
4698                 case OP_LBLE_UN:
4699                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4700                         break;
4701
4702                 case OP_CMOV_IEQ:
4703                 case OP_CMOV_IGE:
4704                 case OP_CMOV_IGT:
4705                 case OP_CMOV_ILE:
4706                 case OP_CMOV_ILT:
4707                 case OP_CMOV_INE_UN:
4708                 case OP_CMOV_IGE_UN:
4709                 case OP_CMOV_IGT_UN:
4710                 case OP_CMOV_ILE_UN:
4711                 case OP_CMOV_ILT_UN:
4712                 case OP_CMOV_LEQ:
4713                 case OP_CMOV_LGE:
4714                 case OP_CMOV_LGT:
4715                 case OP_CMOV_LLE:
4716                 case OP_CMOV_LLT:
4717                 case OP_CMOV_LNE_UN:
4718                 case OP_CMOV_LGE_UN:
4719                 case OP_CMOV_LGT_UN:
4720                 case OP_CMOV_LLE_UN:
4721                 case OP_CMOV_LLT_UN:
4722                         g_assert (ins->dreg == ins->sreg1);
4723                         /* This needs to operate on 64 bit values */
4724                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4725                         break;
4726
4727                 case OP_LNOT:
4728                         amd64_not_reg (code, ins->sreg1);
4729                         break;
4730                 case OP_LNEG:
4731                         amd64_neg_reg (code, ins->sreg1);
4732                         break;
4733
4734                 case OP_ICONST:
4735                 case OP_I8CONST:
4736                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4737                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4738                         else
4739                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4740                         break;
4741                 case OP_AOTCONST:
4742                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4743                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4744                         break;
4745                 case OP_JUMP_TABLE:
4746                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4747                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4748                         break;
4749                 case OP_MOVE:
4750                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4751                         break;
4752                 case OP_AMD64_SET_XMMREG_R4: {
4753                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4754                         break;
4755                 }
4756                 case OP_AMD64_SET_XMMREG_R8: {
4757                         if (ins->dreg != ins->sreg1)
4758                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4759                         break;
4760                 }
4761                 case OP_TAILCALL: {
4762                         MonoCallInst *call = (MonoCallInst*)ins;
4763                         int i, save_area_offset;
4764
4765                         g_assert (!cfg->method->save_lmf);
4766
4767                         /* Restore callee saved registers */
4768                         save_area_offset = cfg->arch.reg_save_area_offset;
4769                         for (i = 0; i < AMD64_NREG; ++i)
4770                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4771                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4772                                         save_area_offset += 8;
4773                                 }
4774
4775                         if (cfg->arch.omit_fp) {
4776                                 if (cfg->arch.stack_alloc_size)
4777                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4778                                 // FIXME:
4779                                 if (call->stack_usage)
4780                                         NOT_IMPLEMENTED;
4781                         } else {
4782                                 /* Copy arguments on the stack to our argument area */
4783                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4784                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4785                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4786                                 }
4787
4788                                 amd64_leave (code);
4789                         }
4790
4791                         offset = code - cfg->native_code;
4792                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4793                         if (cfg->compile_aot)
4794                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4795                         else
4796                                 amd64_set_reg_template (code, AMD64_R11);
4797                         amd64_jump_reg (code, AMD64_R11);
4798                         ins->flags |= MONO_INST_GC_CALLSITE;
4799                         ins->backend.pc_offset = code - cfg->native_code;
4800                         break;
4801                 }
4802                 case OP_CHECK_THIS:
4803                         /* ensure ins->sreg1 is not NULL */
4804                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4805                         break;
4806                 case OP_ARGLIST: {
4807                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4808                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4809                         break;
4810                 }
4811                 case OP_CALL:
4812                 case OP_FCALL:
4813                 case OP_LCALL:
4814                 case OP_VCALL:
4815                 case OP_VCALL2:
4816                 case OP_VOIDCALL:
4817                         call = (MonoCallInst*)ins;
4818                         /*
4819                          * The AMD64 ABI forces callers to know about varargs.
4820                          */
4821                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4822                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4823                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4824                                 /*
4825                                  * Since the unmanaged calling convention doesn't contain a
4826                                  * 'vararg' entry, we have to treat every pinvoke call as a
4827                                  * potential vararg call.
4828                                  */
4829                                 guint32 nregs, i;
4830                                 nregs = 0;
4831                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4832                                         if (call->used_fregs & (1 << i))
4833                                                 nregs ++;
4834                                 if (!nregs)
4835                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4836                                 else
4837                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4838                         }
4839
4840                         if (ins->flags & MONO_INST_HAS_METHOD)
4841                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4842                         else
4843                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4844                         ins->flags |= MONO_INST_GC_CALLSITE;
4845                         ins->backend.pc_offset = code - cfg->native_code;
4846                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4847                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4848                         code = emit_move_return_value (cfg, ins, code);
4849                         break;
4850                 case OP_FCALL_REG:
4851                 case OP_LCALL_REG:
4852                 case OP_VCALL_REG:
4853                 case OP_VCALL2_REG:
4854                 case OP_VOIDCALL_REG:
4855                 case OP_CALL_REG:
4856                         call = (MonoCallInst*)ins;
4857
4858                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4859                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4860                                 ins->sreg1 = AMD64_R11;
4861                         }
4862
4863                         /*
4864                          * The AMD64 ABI forces callers to know about varargs.
4865                          */
4866                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4867                                 if (ins->sreg1 == AMD64_RAX) {
4868                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4869                                         ins->sreg1 = AMD64_R11;
4870                                 }
4871                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4872                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4873                                 /*
4874                                  * Since the unmanaged calling convention doesn't contain a
4875                                  * 'vararg' entry, we have to treat every pinvoke call as a
4876                                  * potential vararg call.
4877                                  */
4878                                 guint32 nregs, i;
4879                                 nregs = 0;
4880                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4881                                         if (call->used_fregs & (1 << i))
4882                                                 nregs ++;
4883                                 if (ins->sreg1 == AMD64_RAX) {
4884                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4885                                         ins->sreg1 = AMD64_R11;
4886                                 }
4887                                 if (!nregs)
4888                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4889                                 else
4890                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4891                         }
4892
4893                         amd64_call_reg (code, ins->sreg1);
4894                         ins->flags |= MONO_INST_GC_CALLSITE;
4895                         ins->backend.pc_offset = code - cfg->native_code;
4896                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4897                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4898                         code = emit_move_return_value (cfg, ins, code);
4899                         break;
4900                 case OP_FCALL_MEMBASE:
4901                 case OP_LCALL_MEMBASE:
4902                 case OP_VCALL_MEMBASE:
4903                 case OP_VCALL2_MEMBASE:
4904                 case OP_VOIDCALL_MEMBASE:
4905                 case OP_CALL_MEMBASE:
4906                         call = (MonoCallInst*)ins;
4907
4908                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4909                         ins->flags |= MONO_INST_GC_CALLSITE;
4910                         ins->backend.pc_offset = code - cfg->native_code;
4911                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4912                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4913                         code = emit_move_return_value (cfg, ins, code);
4914                         break;
4915                 case OP_DYN_CALL: {
4916                         int i;
4917                         MonoInst *var = cfg->dyn_call_var;
4918
4919                         g_assert (var->opcode == OP_REGOFFSET);
4920
4921                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4922                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4923                         /* r10 = ftn */
4924                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4925
4926                         /* Save args buffer */
4927                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4928
4929                         /* Set argument registers */
4930                         for (i = 0; i < PARAM_REGS; ++i)
4931                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4932
4933                         /* Make the call */
4934                         amd64_call_reg (code, AMD64_R10);
4935
4936                         ins->flags |= MONO_INST_GC_CALLSITE;
4937                         ins->backend.pc_offset = code - cfg->native_code;
4938
4939                         /* Save result */
4940                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4941                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4942                         break;
4943                 }
4944                 case OP_AMD64_SAVE_SP_TO_LMF: {
4945                         MonoInst *lmf_var = cfg->lmf_var;
4946                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4947                         break;
4948                 }
4949                 case OP_X86_PUSH:
4950                         g_assert (!cfg->arch.no_pushes);
4951                         amd64_push_reg (code, ins->sreg1);
4952                         break;
4953                 case OP_X86_PUSH_IMM:
4954                         g_assert (!cfg->arch.no_pushes);
4955                         g_assert (amd64_is_imm32 (ins->inst_imm));
4956                         amd64_push_imm (code, ins->inst_imm);
4957                         break;
4958                 case OP_X86_PUSH_MEMBASE:
4959                         g_assert (!cfg->arch.no_pushes);
4960                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4961                         break;
4962                 case OP_X86_PUSH_OBJ: {
4963                         int size = ALIGN_TO (ins->inst_imm, 8);
4964
4965                         g_assert (!cfg->arch.no_pushes);
4966
4967                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4968                         amd64_push_reg (code, AMD64_RDI);
4969                         amd64_push_reg (code, AMD64_RSI);
4970                         amd64_push_reg (code, AMD64_RCX);
4971                         if (ins->inst_offset)
4972                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4973                         else
4974                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4975                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4976                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4977                         amd64_cld (code);
4978                         amd64_prefix (code, X86_REP_PREFIX);
4979                         amd64_movsd (code);
4980                         amd64_pop_reg (code, AMD64_RCX);
4981                         amd64_pop_reg (code, AMD64_RSI);
4982                         amd64_pop_reg (code, AMD64_RDI);
4983                         break;
4984                 }
4985                 case OP_X86_LEA:
4986                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4987                         break;
4988                 case OP_X86_LEA_MEMBASE:
4989                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4990                         break;
4991                 case OP_X86_XCHG:
4992                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4993                         break;
4994                 case OP_LOCALLOC:
4995                         /* keep alignment */
4996                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4997                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4998                         code = mono_emit_stack_alloc (cfg, code, ins);
4999                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5000                         if (cfg->param_area && cfg->arch.no_pushes)
5001                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5002                         break;
5003                 case OP_LOCALLOC_IMM: {
5004                         guint32 size = ins->inst_imm;
5005                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5006
5007                         if (ins->flags & MONO_INST_INIT) {
5008                                 if (size < 64) {
5009                                         int i;
5010
5011                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5012                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5013
5014                                         for (i = 0; i < size; i += 8)
5015                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5016                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5017                                 } else {
5018                                         amd64_mov_reg_imm (code, ins->dreg, size);
5019                                         ins->sreg1 = ins->dreg;
5020
5021                                         code = mono_emit_stack_alloc (cfg, code, ins);
5022                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5023                                 }
5024                         } else {
5025                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5026                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5027                         }
5028                         if (cfg->param_area && cfg->arch.no_pushes)
5029                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5030                         break;
5031                 }
5032                 case OP_THROW: {
5033                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5034                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5035                                              (gpointer)"mono_arch_throw_exception", FALSE);
5036                         ins->flags |= MONO_INST_GC_CALLSITE;
5037                         ins->backend.pc_offset = code - cfg->native_code;
5038                         break;
5039                 }
5040                 case OP_RETHROW: {
5041                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5042                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5043                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5044                         ins->flags |= MONO_INST_GC_CALLSITE;
5045                         ins->backend.pc_offset = code - cfg->native_code;
5046                         break;
5047                 }
5048                 case OP_CALL_HANDLER:
5049                         /* Align stack */
5050                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5051                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5052                         amd64_call_imm (code, 0);
5053                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5054                         /* Restore stack alignment */
5055                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5056                         break;
5057                 case OP_START_HANDLER: {
5058                         /* Even though we're saving RSP, use sizeof */
5059                         /* gpointer because spvar is of type IntPtr */
5060                         /* see: mono_create_spvar_for_region */
5061                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5062                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5063
5064                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5065                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5066                                 cfg->param_area && cfg->arch.no_pushes) {
5067                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5068                         }
5069                         break;
5070                 }
5071                 case OP_ENDFINALLY: {
5072                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5073                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5074                         amd64_ret (code);
5075                         break;
5076                 }
5077                 case OP_ENDFILTER: {
5078                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5079                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5080                         /* The local allocator will put the result into RAX */
5081                         amd64_ret (code);
5082                         break;
5083                 }
5084
5085                 case OP_LABEL:
5086                         ins->inst_c0 = code - cfg->native_code;
5087                         break;
5088                 case OP_BR:
5089                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5090                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5091                         //break;
5092                                 if (ins->inst_target_bb->native_offset) {
5093                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5094                                 } else {
5095                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5096                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5097                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5098                                                 x86_jump8 (code, 0);
5099                                         else
5100                                                 x86_jump32 (code, 0);
5101                         }
5102                         break;
5103                 case OP_BR_REG:
5104                         amd64_jump_reg (code, ins->sreg1);
5105                         break;
5106                 case OP_ICNEQ:
5107                 case OP_ICGE:
5108                 case OP_ICLE:
5109                 case OP_ICGE_UN:
5110                 case OP_ICLE_UN:
5111
5112                 case OP_CEQ:
5113                 case OP_LCEQ:
5114                 case OP_ICEQ:
5115                 case OP_CLT:
5116                 case OP_LCLT:
5117                 case OP_ICLT:
5118                 case OP_CGT:
5119                 case OP_ICGT:
5120                 case OP_LCGT:
5121                 case OP_CLT_UN:
5122                 case OP_LCLT_UN:
5123                 case OP_ICLT_UN:
5124                 case OP_CGT_UN:
5125                 case OP_LCGT_UN:
5126                 case OP_ICGT_UN:
5127                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5128                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5129                         break;
5130                 case OP_COND_EXC_EQ:
5131                 case OP_COND_EXC_NE_UN:
5132                 case OP_COND_EXC_LT:
5133                 case OP_COND_EXC_LT_UN:
5134                 case OP_COND_EXC_GT:
5135                 case OP_COND_EXC_GT_UN:
5136                 case OP_COND_EXC_GE:
5137                 case OP_COND_EXC_GE_UN:
5138                 case OP_COND_EXC_LE:
5139                 case OP_COND_EXC_LE_UN:
5140                 case OP_COND_EXC_IEQ:
5141                 case OP_COND_EXC_INE_UN:
5142                 case OP_COND_EXC_ILT:
5143                 case OP_COND_EXC_ILT_UN:
5144                 case OP_COND_EXC_IGT:
5145                 case OP_COND_EXC_IGT_UN:
5146                 case OP_COND_EXC_IGE:
5147                 case OP_COND_EXC_IGE_UN:
5148                 case OP_COND_EXC_ILE:
5149                 case OP_COND_EXC_ILE_UN:
5150                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5151                         break;
5152                 case OP_COND_EXC_OV:
5153                 case OP_COND_EXC_NO:
5154                 case OP_COND_EXC_C:
5155                 case OP_COND_EXC_NC:
5156                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5157                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5158                         break;
5159                 case OP_COND_EXC_IOV:
5160                 case OP_COND_EXC_INO:
5161                 case OP_COND_EXC_IC:
5162                 case OP_COND_EXC_INC:
5163                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5164                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5165                         break;
5166
5167                 /* floating point opcodes */
5168                 case OP_R8CONST: {
5169                         double d = *(double *)ins->inst_p0;
5170
5171                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5172                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5173                         }
5174                         else {
5175                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5176                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5177                         }
5178                         break;
5179                 }
5180                 case OP_R4CONST: {
5181                         float f = *(float *)ins->inst_p0;
5182
5183                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5184                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5185                         }
5186                         else {
5187                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5188                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5189                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5190                         }
5191                         break;
5192                 }
5193                 case OP_STORER8_MEMBASE_REG:
5194                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5195                         break;
5196                 case OP_LOADR8_MEMBASE:
5197                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5198                         break;
5199                 case OP_STORER4_MEMBASE_REG:
5200                         /* This requires a double->single conversion */
5201                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5202                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5203                         break;
5204                 case OP_LOADR4_MEMBASE:
5205                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5206                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5207                         break;
5208                 case OP_ICONV_TO_R4:
5209                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5210                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5211                         break;
5212                 case OP_ICONV_TO_R8:
5213                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5214                         break;
5215                 case OP_LCONV_TO_R4:
5216                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5217                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5218                         break;
5219                 case OP_LCONV_TO_R8:
5220                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5221                         break;
5222                 case OP_FCONV_TO_R4:
5223                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5224                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5225                         break;
5226                 case OP_FCONV_TO_I1:
5227                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5228                         break;
5229                 case OP_FCONV_TO_U1:
5230                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5231                         break;
5232                 case OP_FCONV_TO_I2:
5233                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5234                         break;
5235                 case OP_FCONV_TO_U2:
5236                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5237                         break;
5238                 case OP_FCONV_TO_U4:
5239                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5240                         break;
5241                 case OP_FCONV_TO_I4:
5242                 case OP_FCONV_TO_I:
5243                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5244                         break;
5245                 case OP_FCONV_TO_I8:
5246                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5247                         break;
5248                 case OP_LCONV_TO_R_UN: {
5249                         guint8 *br [2];
5250
5251                         /* Based on gcc code */
5252                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5253                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5254
5255                         /* Positive case */
5256                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5257                         br [1] = code; x86_jump8 (code, 0);
5258                         amd64_patch (br [0], code);
5259
5260                         /* Negative case */
5261                         /* Save to the red zone */
5262                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5263                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5264                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5265                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5266                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5267                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5268                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5269                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5270                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5271                         /* Restore */
5272                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5273                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5274                         amd64_patch (br [1], code);
5275                         break;
5276                 }
5277                 case OP_LCONV_TO_OVF_U4:
5278                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5279                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5280                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5281                         break;
5282                 case OP_LCONV_TO_OVF_I4_UN:
5283                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5284                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5285                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5286                         break;
5287                 case OP_FMOVE:
5288                         if (ins->dreg != ins->sreg1)
5289                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5290                         break;
5291                 case OP_FADD:
5292                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5293                         break;
5294                 case OP_FSUB:
5295                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5296                         break;
5297                 case OP_FMUL:
5298                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5299                         break;
5300                 case OP_FDIV:
5301                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5302                         break;
5303                 case OP_FNEG: {
5304                         static double r8_0 = -0.0;
5305
5306                         g_assert (ins->sreg1 == ins->dreg);
5307
5308                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5309                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5310                         break;
5311                 }
5312                 case OP_SIN:
5313                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5314                         break;
5315                 case OP_COS:
5316                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5317                         break;
5318                 case OP_ABS: {
5319                         static guint64 d = 0x7fffffffffffffffUL;
5320
5321                         g_assert (ins->sreg1 == ins->dreg);
5322
5323                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5324                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5325                         break;
5326                 }
5327                 case OP_SQRT:
5328                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5329                         break;
5330                 case OP_IMIN:
5331                         g_assert (cfg->opt & MONO_OPT_CMOV);
5332                         g_assert (ins->dreg == ins->sreg1);
5333                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5334                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5335                         break;
5336                 case OP_IMIN_UN:
5337                         g_assert (cfg->opt & MONO_OPT_CMOV);
5338                         g_assert (ins->dreg == ins->sreg1);
5339                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5340                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5341                         break;
5342                 case OP_IMAX:
5343                         g_assert (cfg->opt & MONO_OPT_CMOV);
5344                         g_assert (ins->dreg == ins->sreg1);
5345                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5346                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5347                         break;
5348                 case OP_IMAX_UN:
5349                         g_assert (cfg->opt & MONO_OPT_CMOV);
5350                         g_assert (ins->dreg == ins->sreg1);
5351                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5352                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5353                         break;
5354                 case OP_LMIN:
5355                         g_assert (cfg->opt & MONO_OPT_CMOV);
5356                         g_assert (ins->dreg == ins->sreg1);
5357                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5358                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5359                         break;
5360                 case OP_LMIN_UN:
5361                         g_assert (cfg->opt & MONO_OPT_CMOV);
5362                         g_assert (ins->dreg == ins->sreg1);
5363                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5364                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5365                         break;
5366                 case OP_LMAX:
5367                         g_assert (cfg->opt & MONO_OPT_CMOV);
5368                         g_assert (ins->dreg == ins->sreg1);
5369                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5370                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5371                         break;
5372                 case OP_LMAX_UN:
5373                         g_assert (cfg->opt & MONO_OPT_CMOV);
5374                         g_assert (ins->dreg == ins->sreg1);
5375                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5376                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5377                         break;
5378                 case OP_X86_FPOP:
5379                         break;
5380                 case OP_FCOMPARE:
5381                         /*
5382                          * The two arguments are swapped because the fbranch instructions
5383                          * depend on this for the non-sse case to work.
5384                          */
5385                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5386                         break;
5387                 case OP_FCNEQ:
5388                 case OP_FCEQ: {
5389                         /* zeroing the register at the start results in
5390                          * shorter and faster code (we can also remove the widening op)
5391                          */
5392                         guchar *unordered_check;
5393                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5394                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5395                         unordered_check = code;
5396                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5397
5398                         if (ins->opcode == OP_FCEQ) {
5399                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5400                                 amd64_patch (unordered_check, code);
5401                         } else {
5402                                 guchar *jump_to_end;
5403                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5404                                 jump_to_end = code;
5405                                 x86_jump8 (code, 0);
5406                                 amd64_patch (unordered_check, code);
5407                                 amd64_inc_reg (code, ins->dreg);
5408                                 amd64_patch (jump_to_end, code);
5409                         }
5410                         break;
5411                 }
5412                 case OP_FCLT:
5413                 case OP_FCLT_UN:
5414                         /* zeroing the register at the start results in
5415                          * shorter and faster code (we can also remove the widening op)
5416                          */
5417                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5418                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5419                         if (ins->opcode == OP_FCLT_UN) {
5420                                 guchar *unordered_check = code;
5421                                 guchar *jump_to_end;
5422                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5423                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5424                                 jump_to_end = code;
5425                                 x86_jump8 (code, 0);
5426                                 amd64_patch (unordered_check, code);
5427                                 amd64_inc_reg (code, ins->dreg);
5428                                 amd64_patch (jump_to_end, code);
5429                         } else {
5430                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5431                         }
5432                         break;
5433                 case OP_FCLE: {
5434                         guchar *unordered_check;
5435                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5436                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5437                         unordered_check = code;
5438                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5439                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5440                         amd64_patch (unordered_check, code);
5441                         break;
5442                 }
5443                 case OP_FCGT:
5444                 case OP_FCGT_UN: {
5445                         /* zeroing the register at the start results in
5446                          * shorter and faster code (we can also remove the widening op)
5447                          */
5448                         guchar *unordered_check;
5449                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5450                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5451                         if (ins->opcode == OP_FCGT) {
5452                                 unordered_check = code;
5453                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5454                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5455                                 amd64_patch (unordered_check, code);
5456                         } else {
5457                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5458                         }
5459                         break;
5460                 }
5461                 case OP_FCGE: {
5462                         guchar *unordered_check;
5463                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5464                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5465                         unordered_check = code;
5466                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5467                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5468                         amd64_patch (unordered_check, code);
5469                         break;
5470                 }
5471
5472                 case OP_FCLT_MEMBASE:
5473                 case OP_FCGT_MEMBASE:
5474                 case OP_FCLT_UN_MEMBASE:
5475                 case OP_FCGT_UN_MEMBASE:
5476                 case OP_FCEQ_MEMBASE: {
5477                         guchar *unordered_check, *jump_to_end;
5478                         int x86_cond;
5479
5480                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5481                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5482
5483                         switch (ins->opcode) {
5484                         case OP_FCEQ_MEMBASE:
5485                                 x86_cond = X86_CC_EQ;
5486                                 break;
5487                         case OP_FCLT_MEMBASE:
5488                         case OP_FCLT_UN_MEMBASE:
5489                                 x86_cond = X86_CC_LT;
5490                                 break;
5491                         case OP_FCGT_MEMBASE:
5492                         case OP_FCGT_UN_MEMBASE:
5493                                 x86_cond = X86_CC_GT;
5494                                 break;
5495                         default:
5496                                 g_assert_not_reached ();
5497                         }
5498
5499                         unordered_check = code;
5500                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5501                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5502
5503                         switch (ins->opcode) {
5504                         case OP_FCEQ_MEMBASE:
5505                         case OP_FCLT_MEMBASE:
5506                         case OP_FCGT_MEMBASE:
5507                                 amd64_patch (unordered_check, code);
5508                                 break;
5509                         case OP_FCLT_UN_MEMBASE:
5510                         case OP_FCGT_UN_MEMBASE:
5511                                 jump_to_end = code;
5512                                 x86_jump8 (code, 0);
5513                                 amd64_patch (unordered_check, code);
5514                                 amd64_inc_reg (code, ins->dreg);
5515                                 amd64_patch (jump_to_end, code);
5516                                 break;
5517                         default:
5518                                 break;
5519                         }
5520                         break;
5521                 }
5522                 case OP_FBEQ: {
5523                         guchar *jump = code;
5524                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5525                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5526                         amd64_patch (jump, code);
5527                         break;
5528                 }
5529                 case OP_FBNE_UN:
5530                         /* Branch if C013 != 100 */
5531                         /* branch if !ZF or (PF|CF) */
5532                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5533                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5534                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5535                         break;
5536                 case OP_FBLT:
5537                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5538                         break;
5539                 case OP_FBLT_UN:
5540                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5541                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5542                         break;
5543                 case OP_FBGT:
5544                 case OP_FBGT_UN:
5545                         if (ins->opcode == OP_FBGT) {
5546                                 guchar *br1;
5547
5548                                 /* skip branch if C1=1 */
5549                                 br1 = code;
5550                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5551                                 /* branch if (C0 | C3) = 1 */
5552                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5553                                 amd64_patch (br1, code);
5554                                 break;
5555                         } else {
5556                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5557                         }
5558                         break;
5559                 case OP_FBGE: {
5560                         /* Branch if C013 == 100 or 001 */
5561                         guchar *br1;
5562
5563                         /* skip branch if C1=1 */
5564                         br1 = code;
5565                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5566                         /* branch if (C0 | C3) = 1 */
5567                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5568                         amd64_patch (br1, code);
5569                         break;
5570                 }
5571                 case OP_FBGE_UN:
5572                         /* Branch if C013 == 000 */
5573                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5574                         break;
5575                 case OP_FBLE: {
5576                         /* Branch if C013=000 or 100 */
5577                         guchar *br1;
5578
5579                         /* skip branch if C1=1 */
5580                         br1 = code;
5581                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5582                         /* branch if C0=0 */
5583                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5584                         amd64_patch (br1, code);
5585                         break;
5586                 }
5587                 case OP_FBLE_UN:
5588                         /* Branch if C013 != 001 */
5589                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5590                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5591                         break;
5592                 case OP_CKFINITE:
5593                         /* Transfer value to the fp stack */
5594                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5595                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5596                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5597
5598                         amd64_push_reg (code, AMD64_RAX);
5599                         amd64_fxam (code);
5600                         amd64_fnstsw (code);
5601                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5602                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5603                         amd64_pop_reg (code, AMD64_RAX);
5604                         amd64_fstp (code, 0);
5605                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5606                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5607                         break;
5608                 case OP_TLS_GET: {
5609                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5610                         break;
5611                 }
5612                 case OP_TLS_GET_REG:
5613                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5614                         break;
5615                 case OP_TLS_SET: {
5616                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5617                         break;
5618                 }
5619                 case OP_TLS_SET_REG: {
5620                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5621                         break;
5622                 }
5623                 case OP_MEMORY_BARRIER: {
5624                         switch (ins->backend.memory_barrier_kind) {
5625                         case StoreLoadBarrier:
5626                         case FullBarrier:
5627                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5628                                 x86_prefix (code, X86_LOCK_PREFIX);
5629                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5630                                 break;
5631                         }
5632                         break;
5633                 }
5634                 case OP_ATOMIC_ADD_I4:
5635                 case OP_ATOMIC_ADD_I8: {
5636                         int dreg = ins->dreg;
5637                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5638
5639                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5640                                 dreg = AMD64_R11;
5641
5642                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5643                         amd64_prefix (code, X86_LOCK_PREFIX);
5644                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5645                         /* dreg contains the old value, add with sreg2 value */
5646                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5647
5648                         if (ins->dreg != dreg)
5649                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5650
5651                         break;
5652                 }
5653                 case OP_ATOMIC_EXCHANGE_I4:
5654                 case OP_ATOMIC_EXCHANGE_I8: {
5655                         guchar *br[2];
5656                         int sreg2 = ins->sreg2;
5657                         int breg = ins->inst_basereg;
5658                         guint32 size;
5659                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5660
5661                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5662                                 size = 8;
5663                         else
5664                                 size = 4;
5665
5666                         /*
5667                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5668                          * an explanation of how this works.
5669                          */
5670
5671                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5672                          * hack to overcome limits in x86 reg allocator
5673                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5674                          */
5675                         g_assert (ins->dreg == AMD64_RAX);
5676
5677                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5678                                 /* Highly unlikely, but possible */
5679                                 need_push = TRUE;
5680
5681                         /* The pushes invalidate rsp */
5682                         if ((breg == AMD64_RAX) || need_push) {
5683                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5684                                 breg = AMD64_R11;
5685                         }
5686
5687                         /* We need the EAX reg for the comparand */
5688                         if (ins->sreg2 == AMD64_RAX) {
5689                                 if (breg != AMD64_R11) {
5690                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5691                                         sreg2 = AMD64_R11;
5692                                 } else {
5693                                         g_assert (need_push);
5694                                         amd64_push_reg (code, AMD64_RDX);
5695                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5696                                         sreg2 = AMD64_RDX;
5697                                         rdx_pushed = TRUE;
5698                                 }
5699                         }
5700
5701                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5702
5703                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5704                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5705                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5706                         amd64_patch (br [1], br [0]);
5707
5708                         if (rdx_pushed)
5709                                 amd64_pop_reg (code, AMD64_RDX);
5710
5711                         break;
5712                 }
5713                 case OP_ATOMIC_CAS_I4:
5714                 case OP_ATOMIC_CAS_I8: {
5715                         guint32 size;
5716
5717                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5718                                 size = 8;
5719                         else
5720                                 size = 4;
5721
5722                         /*
5723                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5724                          * an explanation of how this works.
5725                          */
5726                         g_assert (ins->sreg3 == AMD64_RAX);
5727                         g_assert (ins->sreg1 != AMD64_RAX);
5728                         g_assert (ins->sreg1 != ins->sreg2);
5729
5730                         amd64_prefix (code, X86_LOCK_PREFIX);
5731                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5732
5733                         if (ins->dreg != AMD64_RAX)
5734                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5735                         break;
5736                 }
5737                 case OP_CARD_TABLE_WBARRIER: {
5738                         int ptr = ins->sreg1;
5739                         int value = ins->sreg2;
5740                         guchar *br = 0;
5741                         int nursery_shift, card_table_shift;
5742                         gpointer card_table_mask;
5743                         size_t nursery_size;
5744
5745                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5746                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5747                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5748
5749                         /*If either point to the stack we can simply avoid the WB. This happens due to
5750                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5751                          */
5752                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5753                                 continue;
5754
5755                         /*
5756                          * We need one register we can clobber, we choose EDX and make sreg1
5757                          * fixed EAX to work around limitations in the local register allocator.
5758                          * sreg2 might get allocated to EDX, but that is not a problem since
5759                          * we use it before clobbering EDX.
5760                          */
5761                         g_assert (ins->sreg1 == AMD64_RAX);
5762
5763                         /*
5764                          * This is the code we produce:
5765                          *
5766                          *   edx = value
5767                          *   edx >>= nursery_shift
5768                          *   cmp edx, (nursery_start >> nursery_shift)
5769                          *   jne done
5770                          *   edx = ptr
5771                          *   edx >>= card_table_shift
5772                          *   edx += cardtable
5773                          *   [edx] = 1
5774                          * done:
5775                          */
5776
5777                         if (mono_gc_card_table_nursery_check ()) {
5778                                 if (value != AMD64_RDX)
5779                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5780                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5781                                 if (shifted_nursery_start >> 31) {
5782                                         /*
5783                                          * The value we need to compare against is 64 bits, so we need
5784                                          * another spare register.  We use RBX, which we save and
5785                                          * restore.
5786                                          */
5787                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5788                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5789                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5790                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5791                                 } else {
5792                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5793                                 }
5794                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5795                         }
5796                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5797                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5798                         if (card_table_mask)
5799                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5800
5801                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5802                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5803
5804                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5805
5806                         if (mono_gc_card_table_nursery_check ())
5807                                 x86_patch (br, code);
5808                         break;
5809                 }
5810 #ifdef MONO_ARCH_SIMD_INTRINSICS
5811                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5812                 case OP_ADDPS:
5813                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5814                         break;
5815                 case OP_DIVPS:
5816                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5817                         break;
5818                 case OP_MULPS:
5819                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5820                         break;
5821                 case OP_SUBPS:
5822                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_MAXPS:
5825                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_MINPS:
5828                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5829                         break;
5830                 case OP_COMPPS:
5831                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5832                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5833                         break;
5834                 case OP_ANDPS:
5835                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5836                         break;
5837                 case OP_ANDNPS:
5838                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5839                         break;
5840                 case OP_ORPS:
5841                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5842                         break;
5843                 case OP_XORPS:
5844                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5845                         break;
5846                 case OP_SQRTPS:
5847                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5848                         break;
5849                 case OP_RSQRTPS:
5850                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5851                         break;
5852                 case OP_RCPPS:
5853                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5854                         break;
5855                 case OP_ADDSUBPS:
5856                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5857                         break;
5858                 case OP_HADDPS:
5859                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5860                         break;
5861                 case OP_HSUBPS:
5862                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5863                         break;
5864                 case OP_DUPPS_HIGH:
5865                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5866                         break;
5867                 case OP_DUPPS_LOW:
5868                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5869                         break;
5870
5871                 case OP_PSHUFLEW_HIGH:
5872                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5873                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5874                         break;
5875                 case OP_PSHUFLEW_LOW:
5876                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5877                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5878                         break;
5879                 case OP_PSHUFLED:
5880                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5881                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5882                         break;
5883                 case OP_SHUFPS:
5884                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5885                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5886                         break;
5887                 case OP_SHUFPD:
5888                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5889                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5890                         break;
5891
5892                 case OP_ADDPD:
5893                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_DIVPD:
5896                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_MULPD:
5899                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_SUBPD:
5902                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_MAXPD:
5905                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_MINPD:
5908                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_COMPPD:
5911                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5912                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5913                         break;
5914                 case OP_ANDPD:
5915                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_ANDNPD:
5918                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_ORPD:
5921                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_XORPD:
5924                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_SQRTPD:
5927                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5928                         break;
5929                 case OP_ADDSUBPD:
5930                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_HADDPD:
5933                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_HSUBPD:
5936                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_DUPPD:
5939                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5940                         break;
5941
5942                 case OP_EXTRACT_MASK:
5943                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5944                         break;
5945
5946                 case OP_PAND:
5947                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_POR:
5950                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PXOR:
5953                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955
5956                 case OP_PADDB:
5957                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_PADDW:
5960                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PADDD:
5963                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PADDQ:
5966                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PSUBB:
5970                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PSUBW:
5973                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PSUBD:
5976                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_PSUBQ:
5979                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981
5982                 case OP_PMAXB_UN:
5983                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PMAXW_UN:
5986                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_PMAXD_UN:
5989                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991
5992                 case OP_PMAXB:
5993                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_PMAXW:
5996                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PMAXD:
5999                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001
6002                 case OP_PAVGB_UN:
6003                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_PAVGW_UN:
6006                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008
6009                 case OP_PMINB_UN:
6010                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PMINW_UN:
6013                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_PMIND_UN:
6016                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018
6019                 case OP_PMINB:
6020                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_PMINW:
6023                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_PMIND:
6026                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028
6029                 case OP_PCMPEQB:
6030                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_PCMPEQW:
6033                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PCMPEQD:
6036                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_PCMPEQQ:
6039                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041
6042                 case OP_PCMPGTB:
6043                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045                 case OP_PCMPGTW:
6046                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_PCMPGTD:
6049                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_PCMPGTQ:
6052                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054
6055                 case OP_PSUM_ABS_DIFF:
6056                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058
6059                 case OP_UNPACK_LOWB:
6060                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_UNPACK_LOWW:
6063                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_UNPACK_LOWD:
6066                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_UNPACK_LOWQ:
6069                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_UNPACK_LOWPS:
6072                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_UNPACK_LOWPD:
6075                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077
6078                 case OP_UNPACK_HIGHB:
6079                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081                 case OP_UNPACK_HIGHW:
6082                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084                 case OP_UNPACK_HIGHD:
6085                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_UNPACK_HIGHQ:
6088                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_UNPACK_HIGHPS:
6091                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_UNPACK_HIGHPD:
6094                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096
6097                 case OP_PACKW:
6098                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PACKD:
6101                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_PACKW_UN:
6104                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PACKD_UN:
6107                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109
6110                 case OP_PADDB_SAT_UN:
6111                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113                 case OP_PSUBB_SAT_UN:
6114                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_PADDW_SAT_UN:
6117                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PSUBW_SAT_UN:
6120                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122
6123                 case OP_PADDB_SAT:
6124                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PSUBB_SAT:
6127                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PADDW_SAT:
6130                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PSUBW_SAT:
6133                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135
6136                 case OP_PMULW:
6137                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_PMULD:
6140                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_PMULQ:
6143                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_PMULW_HIGH_UN:
6146                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_PMULW_HIGH:
6149                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151
6152                 case OP_PSHRW:
6153                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6154                         break;
6155                 case OP_PSHRW_REG:
6156                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6157                         break;
6158
6159                 case OP_PSARW:
6160                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6161                         break;
6162                 case OP_PSARW_REG:
6163                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6164                         break;
6165
6166                 case OP_PSHLW:
6167                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6168                         break;
6169                 case OP_PSHLW_REG:
6170                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6171                         break;
6172
6173                 case OP_PSHRD:
6174                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6175                         break;
6176                 case OP_PSHRD_REG:
6177                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6178                         break;
6179
6180                 case OP_PSARD:
6181                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6182                         break;
6183                 case OP_PSARD_REG:
6184                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6185                         break;
6186
6187                 case OP_PSHLD:
6188                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6189                         break;
6190                 case OP_PSHLD_REG:
6191                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6192                         break;
6193
6194                 case OP_PSHRQ:
6195                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6196                         break;
6197                 case OP_PSHRQ_REG:
6198                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6199                         break;
6200
6201                 /*TODO: This is appart of the sse spec but not added
6202                 case OP_PSARQ:
6203                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6204                         break;
6205                 case OP_PSARQ_REG:
6206                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6207                         break;
6208                 */
6209
6210                 case OP_PSHLQ:
6211                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6212                         break;
6213                 case OP_PSHLQ_REG:
6214                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6215                         break;
6216                 case OP_CVTDQ2PD:
6217                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6218                         break;
6219                 case OP_CVTDQ2PS:
6220                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6221                         break;
6222                 case OP_CVTPD2DQ:
6223                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6224                         break;
6225                 case OP_CVTPD2PS:
6226                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6227                         break;
6228                 case OP_CVTPS2DQ:
6229                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6230                         break;
6231                 case OP_CVTPS2PD:
6232                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6233                         break;
6234                 case OP_CVTTPD2DQ:
6235                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6236                         break;
6237                 case OP_CVTTPS2DQ:
6238                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6239                         break;
6240
6241                 case OP_ICONV_TO_X:
6242                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6243                         break;
6244                 case OP_EXTRACT_I4:
6245                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6246                         break;
6247                 case OP_EXTRACT_I8:
6248                         if (ins->inst_c0) {
6249                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6250                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6251                         } else {
6252                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6253                         }
6254                         break;
6255                 case OP_EXTRACT_I1:
6256                 case OP_EXTRACT_U1:
6257                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6258                         if (ins->inst_c0)
6259                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6260                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6261                         break;
6262                 case OP_EXTRACT_I2:
6263                 case OP_EXTRACT_U2:
6264                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6265                         if (ins->inst_c0)
6266                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6267                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6268                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6269                         break;
6270                 case OP_EXTRACT_R8:
6271                         if (ins->inst_c0)
6272                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6273                         else
6274                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6275                         break;
6276                 case OP_INSERT_I2:
6277                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6278                         break;
6279                 case OP_EXTRACTX_U2:
6280                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6281                         break;
6282                 case OP_INSERTX_U1_SLOW:
6283                         /*sreg1 is the extracted ireg (scratch)
6284                         /sreg2 is the to be inserted ireg (scratch)
6285                         /dreg is the xreg to receive the value*/
6286
6287                         /*clear the bits from the extracted word*/
6288                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6289                         /*shift the value to insert if needed*/
6290                         if (ins->inst_c0 & 1)
6291                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6292                         /*join them together*/
6293                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6294                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6295                         break;
6296                 case OP_INSERTX_I4_SLOW:
6297                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6298                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6299                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6300                         break;
6301                 case OP_INSERTX_I8_SLOW:
6302                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6303                         if (ins->inst_c0)
6304                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6305                         else
6306                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6307                         break;
6308
6309                 case OP_INSERTX_R4_SLOW:
6310                         switch (ins->inst_c0) {
6311                         case 0:
6312                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6313                                 break;
6314                         case 1:
6315                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6316                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6317                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6318                                 break;
6319                         case 2:
6320                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6321                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6322                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6323                                 break;
6324                         case 3:
6325                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6326                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6327                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6328                                 break;
6329                         }
6330                         break;
6331                 case OP_INSERTX_R8_SLOW:
6332                         if (ins->inst_c0)
6333                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6334                         else
6335                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6336                         break;
6337                 case OP_STOREX_MEMBASE_REG:
6338                 case OP_STOREX_MEMBASE:
6339                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6340                         break;
6341                 case OP_LOADX_MEMBASE:
6342                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6343                         break;
6344                 case OP_LOADX_ALIGNED_MEMBASE:
6345                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6346                         break;
6347                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6348                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6349                         break;
6350                 case OP_STOREX_NTA_MEMBASE_REG:
6351                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6352                         break;
6353                 case OP_PREFETCH_MEMBASE:
6354                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6355                         break;
6356
6357                 case OP_XMOVE:
6358                         /*FIXME the peephole pass should have killed this*/
6359                         if (ins->dreg != ins->sreg1)
6360                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6361                         break;
6362                 case OP_XZERO:
6363                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6364                         break;
6365                 case OP_ICONV_TO_R8_RAW:
6366                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6367                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6368                         break;
6369
6370                 case OP_FCONV_TO_R8_X:
6371                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6372                         break;
6373
6374                 case OP_XCONV_R8_TO_I4:
6375                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6376                         switch (ins->backend.source_opcode) {
6377                         case OP_FCONV_TO_I1:
6378                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6379                                 break;
6380                         case OP_FCONV_TO_U1:
6381                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6382                                 break;
6383                         case OP_FCONV_TO_I2:
6384                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6385                                 break;
6386                         case OP_FCONV_TO_U2:
6387                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6388                                 break;
6389                         }
6390                         break;
6391
6392                 case OP_EXPAND_I2:
6393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6394                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6396                         break;
6397                 case OP_EXPAND_I4:
6398                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6400                         break;
6401                 case OP_EXPAND_I8:
6402                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6403                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6404                         break;
6405                 case OP_EXPAND_R4:
6406                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6407                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6408                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6409                         break;
6410                 case OP_EXPAND_R8:
6411                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6412                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6413                         break;
6414 #endif
6415                 case OP_LIVERANGE_START: {
6416                         if (cfg->verbose_level > 1)
6417                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6418                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6419                         break;
6420                 }
6421                 case OP_LIVERANGE_END: {
6422                         if (cfg->verbose_level > 1)
6423                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6424                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6425                         break;
6426                 }
6427                 case OP_NACL_GC_SAFE_POINT: {
6428 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6429                         if (cfg->compile_aot)
6430                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6431                         else {
6432                                 guint8 *br [1];
6433
6434                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6435                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6436                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6437                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6438                                 amd64_patch (br[0], code);
6439                         }
6440 #endif
6441                         break;
6442                 }
6443                 case OP_GC_LIVENESS_DEF:
6444                 case OP_GC_LIVENESS_USE:
6445                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6446                         ins->backend.pc_offset = code - cfg->native_code;
6447                         break;
6448                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6449                         ins->backend.pc_offset = code - cfg->native_code;
6450                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6451                         break;
6452                 default:
6453                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6454                         g_assert_not_reached ();
6455                 }
6456
6457                 if ((code - cfg->native_code - offset) > max_len) {
6458 #if !defined(__native_client_codegen__)
6459                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6460                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6461                         g_assert_not_reached ();
6462 #endif
6463                 }
6464
6465                 last_ins = ins;
6466                 last_offset = offset;
6467         }
6468
6469         cfg->code_len = code - cfg->native_code;
6470 }
6471
6472 #endif /* DISABLE_JIT */
6473
6474 void
6475 mono_arch_register_lowlevel_calls (void)
6476 {
6477         /* The signature doesn't matter */
6478         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6479 }
6480
6481 void
6482 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6483 {
6484         MonoJumpInfo *patch_info;
6485         gboolean compile_aot = !run_cctors;
6486
6487         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6488                 unsigned char *ip = patch_info->ip.i + code;
6489                 unsigned char *target;
6490
6491                 if (compile_aot) {
6492                         switch (patch_info->type) {
6493                         case MONO_PATCH_INFO_BB:
6494                         case MONO_PATCH_INFO_LABEL:
6495                                 break;
6496                         default:
6497                                 /* No need to patch these */
6498                                 continue;
6499                         }
6500                 }
6501
6502                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6503
6504                 switch (patch_info->type) {
6505                 case MONO_PATCH_INFO_NONE:
6506                         continue;
6507                 case MONO_PATCH_INFO_METHOD_REL:
6508                 case MONO_PATCH_INFO_R8:
6509                 case MONO_PATCH_INFO_R4:
6510                         g_assert_not_reached ();
6511                         continue;
6512                 case MONO_PATCH_INFO_BB:
6513                         break;
6514                 default:
6515                         break;
6516                 }
6517
6518                 /*
6519                  * Debug code to help track down problems where the target of a near call is
6520                  * is not valid.
6521                  */
6522                 if (amd64_is_near_call (ip)) {
6523                         gint64 disp = (guint8*)target - (guint8*)ip;
6524
6525                         if (!amd64_is_imm32 (disp)) {
6526                                 printf ("TYPE: %d\n", patch_info->type);
6527                                 switch (patch_info->type) {
6528                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6529                                         printf ("V: %s\n", patch_info->data.name);
6530                                         break;
6531                                 case MONO_PATCH_INFO_METHOD_JUMP:
6532                                 case MONO_PATCH_INFO_METHOD:
6533                                         printf ("V: %s\n", patch_info->data.method->name);
6534                                         break;
6535                                 default:
6536                                         break;
6537                                 }
6538                         }
6539                 }
6540
6541                 amd64_patch (ip, (gpointer)target);
6542         }
6543 }
6544
6545 #ifndef DISABLE_JIT
6546
6547 static int
6548 get_max_epilog_size (MonoCompile *cfg)
6549 {
6550         int max_epilog_size = 16;
6551
6552         if (cfg->method->save_lmf)
6553                 max_epilog_size += 256;
6554
6555         if (mono_jit_trace_calls != NULL)
6556                 max_epilog_size += 50;
6557
6558         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6559                 max_epilog_size += 50;
6560
6561         max_epilog_size += (AMD64_NREG * 2);
6562
6563         return max_epilog_size;
6564 }
6565
6566 /*
6567  * This macro is used for testing whenever the unwinder works correctly at every point
6568  * where an async exception can happen.
6569  */
6570 /* This will generate a SIGSEGV at the given point in the code */
6571 #define async_exc_point(code) do { \
6572     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6573          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6574              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6575          cfg->arch.async_point_count ++; \
6576     } \
6577 } while (0)
6578
6579 guint8 *
6580 mono_arch_emit_prolog (MonoCompile *cfg)
6581 {
6582         MonoMethod *method = cfg->method;
6583         MonoBasicBlock *bb;
6584         MonoMethodSignature *sig;
6585         MonoInst *ins;
6586         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6587         guint8 *code;
6588         CallInfo *cinfo;
6589         MonoInst *lmf_var = cfg->lmf_var;
6590         gboolean args_clobbered = FALSE;
6591         gboolean trace = FALSE;
6592 #ifdef __native_client_codegen__
6593         guint alignment_check;
6594 #endif
6595
6596         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6597
6598 #if defined(__default_codegen__)
6599         code = cfg->native_code = g_malloc (cfg->code_size);
6600 #elif defined(__native_client_codegen__)
6601         /* native_code_alloc is not 32-byte aligned, native_code is. */
6602         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6603
6604         /* Align native_code to next nearest kNaclAlignment byte. */
6605         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6606         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6607
6608         code = cfg->native_code;
6609
6610         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6611         g_assert (alignment_check == 0);
6612 #endif
6613
6614         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6615                 trace = TRUE;
6616
6617         /* Amount of stack space allocated by register saving code */
6618         pos = 0;
6619
6620         /* Offset between RSP and the CFA */
6621         cfa_offset = 0;
6622
6623         /*
6624          * The prolog consists of the following parts:
6625          * FP present:
6626          * - push rbp, mov rbp, rsp
6627          * - save callee saved regs using pushes
6628          * - allocate frame
6629          * - save rgctx if needed
6630          * - save lmf if needed
6631          * FP not present:
6632          * - allocate frame
6633          * - save rgctx if needed
6634          * - save lmf if needed
6635          * - save callee saved regs using moves
6636          */
6637
6638         // CFA = sp + 8
6639         cfa_offset = 8;
6640         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6641         // IP saved at CFA - 8
6642         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6643         async_exc_point (code);
6644         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6645
6646         if (!cfg->arch.omit_fp) {
6647                 amd64_push_reg (code, AMD64_RBP);
6648                 cfa_offset += 8;
6649                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6650                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6651                 async_exc_point (code);
6652 #ifdef HOST_WIN32
6653                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6654 #endif
6655                 /* These are handled automatically by the stack marking code */
6656                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6657
6658                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6659                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6660                 async_exc_point (code);
6661 #ifdef HOST_WIN32
6662                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6663 #endif
6664         }
6665
6666         /* The param area is always at offset 0 from sp */
6667         /* This needs to be allocated here, since it has to come after the spill area */
6668         if (cfg->arch.no_pushes && cfg->param_area) {
6669                 if (cfg->arch.omit_fp)
6670                         // FIXME:
6671                         g_assert_not_reached ();
6672                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6673         }
6674
6675         if (cfg->arch.omit_fp) {
6676                 /*
6677                  * On enter, the stack is misaligned by the pushing of the return
6678                  * address. It is either made aligned by the pushing of %rbp, or by
6679                  * this.
6680                  */
6681                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6682                 if ((alloc_size % 16) == 0) {
6683                         alloc_size += 8;
6684                         /* Mark the padding slot as NOREF */
6685                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6686                 }
6687         } else {
6688                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6689                 if (cfg->stack_offset != alloc_size) {
6690                         /* Mark the padding slot as NOREF */
6691                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6692                 }
6693                 cfg->arch.sp_fp_offset = alloc_size;
6694                 alloc_size -= pos;
6695         }
6696
6697         cfg->arch.stack_alloc_size = alloc_size;
6698
6699         /* Allocate stack frame */
6700         if (alloc_size) {
6701                 /* See mono_emit_stack_alloc */
6702 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6703                 guint32 remaining_size = alloc_size;
6704                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6705                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6706                 guint32 offset = code - cfg->native_code;
6707                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6708                         while (required_code_size >= (cfg->code_size - offset))
6709                                 cfg->code_size *= 2;
6710                         cfg->native_code = mono_realloc_native_code (cfg);
6711                         code = cfg->native_code + offset;
6712                         cfg->stat_code_reallocs++;
6713                 }
6714
6715                 while (remaining_size >= 0x1000) {
6716                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6717                         if (cfg->arch.omit_fp) {
6718                                 cfa_offset += 0x1000;
6719                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6720                         }
6721                         async_exc_point (code);
6722 #ifdef HOST_WIN32
6723                         if (cfg->arch.omit_fp)
6724                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6725 #endif
6726
6727                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6728                         remaining_size -= 0x1000;
6729                 }
6730                 if (remaining_size) {
6731                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6732                         if (cfg->arch.omit_fp) {
6733                                 cfa_offset += remaining_size;
6734                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6735                                 async_exc_point (code);
6736                         }
6737 #ifdef HOST_WIN32
6738                         if (cfg->arch.omit_fp)
6739                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6740 #endif
6741                 }
6742 #else
6743                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6744                 if (cfg->arch.omit_fp) {
6745                         cfa_offset += alloc_size;
6746                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6747                         async_exc_point (code);
6748                 }
6749 #endif
6750         }
6751
6752         /* Stack alignment check */
6753 #if 0
6754         {
6755                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6756                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6757                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6758                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6759                 amd64_breakpoint (code);
6760         }
6761 #endif
6762
6763 #ifndef TARGET_WIN32
6764         if (mini_get_debug_options ()->init_stacks) {
6765                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6766
6767                 /* Save registers to the red zone */
6768                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6769                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6770
6771                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6772                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6773                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6774
6775                 amd64_cld (code);
6776 #if defined(__default_codegen__)
6777                 amd64_prefix (code, X86_REP_PREFIX);
6778                 amd64_stosl (code);
6779 #elif defined(__native_client_codegen__)
6780                 /* NaCl stos pseudo-instruction */
6781                 amd64_codegen_pre (code);
6782                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6783                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6784                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6785                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6786                 amd64_prefix (code, X86_REP_PREFIX);
6787                 amd64_stosl (code);
6788                 amd64_codegen_post (code);
6789 #endif /* __native_client_codegen__ */
6790
6791                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6792                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6793         }
6794 #endif
6795
6796         /* Save LMF */
6797         if (method->save_lmf) {
6798                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6799         }
6800
6801         /* Save callee saved registers */
6802         if (TRUE || !method->save_lmf) {
6803                 gint32 save_area_offset;
6804
6805                 if (cfg->arch.omit_fp) {
6806                         save_area_offset = cfg->arch.reg_save_area_offset;
6807                         /* Save caller saved registers after sp is adjusted */
6808                         /* The registers are saved at the bottom of the frame */
6809                         /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6810                 } else {
6811                         /* The registers are saved just below the saved rbp */
6812                         save_area_offset = cfg->arch.reg_save_area_offset;
6813                 }
6814
6815                 for (i = 0; i < AMD64_NREG; ++i)
6816                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6817                                 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6818
6819                                 if (cfg->arch.omit_fp) {
6820                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6821                                         /* These are handled automatically by the stack marking code */
6822                                         mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6823                                 } else {
6824                                         mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6825                                         // FIXME: GC
6826                                 }
6827
6828                                 save_area_offset += 8;
6829                                 async_exc_point (code);
6830                         }
6831         }
6832
6833         /* store runtime generic context */
6834         if (cfg->rgctx_var) {
6835                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6836                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6837
6838                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6839
6840                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6841                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6842         }
6843
6844         /* compute max_length in order to use short forward jumps */
6845         max_epilog_size = get_max_epilog_size (cfg);
6846         if (cfg->opt & MONO_OPT_BRANCH) {
6847                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6848                         MonoInst *ins;
6849                         int max_length = 0;
6850
6851                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6852                                 max_length += 6;
6853                         /* max alignment for loops */
6854                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6855                                 max_length += LOOP_ALIGNMENT;
6856 #ifdef __native_client_codegen__
6857                         /* max alignment for native client */
6858                         max_length += kNaClAlignment;
6859 #endif
6860
6861                         MONO_BB_FOR_EACH_INS (bb, ins) {
6862 #ifdef __native_client_codegen__
6863                                 {
6864                                         int space_in_block = kNaClAlignment -
6865                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6866                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6867                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6868                                                 max_length += space_in_block;
6869                                         }
6870                                 }
6871 #endif  /*__native_client_codegen__*/
6872                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6873                         }
6874
6875                         /* Take prolog and epilog instrumentation into account */
6876                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6877                                 max_length += max_epilog_size;
6878
6879                         bb->max_length = max_length;
6880                 }
6881         }
6882
6883         sig = mono_method_signature (method);
6884         pos = 0;
6885
6886         cinfo = cfg->arch.cinfo;
6887
6888         if (sig->ret->type != MONO_TYPE_VOID) {
6889                 /* Save volatile arguments to the stack */
6890                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6891                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6892         }
6893
6894         /* Keep this in sync with emit_load_volatile_arguments */
6895         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6896                 ArgInfo *ainfo = cinfo->args + i;
6897                 gint32 stack_offset;
6898                 MonoType *arg_type;
6899
6900                 ins = cfg->args [i];
6901
6902                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6903                         /* Unused arguments */
6904                         continue;
6905
6906                 if (sig->hasthis && (i == 0))
6907                         arg_type = &mono_defaults.object_class->byval_arg;
6908                 else
6909                         arg_type = sig->params [i - sig->hasthis];
6910
6911                 stack_offset = ainfo->offset + ARGS_OFFSET;
6912
6913                 if (cfg->globalra) {
6914                         /* All the other moves are done by the register allocator */
6915                         switch (ainfo->storage) {
6916                         case ArgInFloatSSEReg:
6917                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6918                                 break;
6919                         case ArgValuetypeInReg:
6920                                 for (quad = 0; quad < 2; quad ++) {
6921                                         switch (ainfo->pair_storage [quad]) {
6922                                         case ArgInIReg:
6923                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6924                                                 break;
6925                                         case ArgInFloatSSEReg:
6926                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6927                                                 break;
6928                                         case ArgInDoubleSSEReg:
6929                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6930                                                 break;
6931                                         case ArgNone:
6932                                                 break;
6933                                         default:
6934                                                 g_assert_not_reached ();
6935                                         }
6936                                 }
6937                                 break;
6938                         default:
6939                                 break;
6940                         }
6941
6942                         continue;
6943                 }
6944
6945                 /* Save volatile arguments to the stack */
6946                 if (ins->opcode != OP_REGVAR) {
6947                         switch (ainfo->storage) {
6948                         case ArgInIReg: {
6949                                 guint32 size = 8;
6950
6951                                 /* FIXME: I1 etc */
6952                                 /*
6953                                 if (stack_offset & 0x1)
6954                                         size = 1;
6955                                 else if (stack_offset & 0x2)
6956                                         size = 2;
6957                                 else if (stack_offset & 0x4)
6958                                         size = 4;
6959                                 else
6960                                         size = 8;
6961                                 */
6962                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6963
6964                                 /*
6965                                  * Save the original location of 'this',
6966                                  * get_generic_info_from_stack_frame () needs this to properly look up
6967                                  * the argument value during the handling of async exceptions.
6968                                  */
6969                                 if (ins == cfg->args [0]) {
6970                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6971                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6972                                 }
6973                                 break;
6974                         }
6975                         case ArgInFloatSSEReg:
6976                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6977                                 break;
6978                         case ArgInDoubleSSEReg:
6979                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6980                                 break;
6981                         case ArgValuetypeInReg:
6982                                 for (quad = 0; quad < 2; quad ++) {
6983                                         switch (ainfo->pair_storage [quad]) {
6984                                         case ArgInIReg:
6985                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6986                                                 break;
6987                                         case ArgInFloatSSEReg:
6988                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6989                                                 break;
6990                                         case ArgInDoubleSSEReg:
6991                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6992                                                 break;
6993                                         case ArgNone:
6994                                                 break;
6995                                         default:
6996                                                 g_assert_not_reached ();
6997                                         }
6998                                 }
6999                                 break;
7000                         case ArgValuetypeAddrInIReg:
7001                                 if (ainfo->pair_storage [0] == ArgInIReg)
7002                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7003                                 break;
7004                         default:
7005                                 break;
7006                         }
7007                 } else {
7008                         /* Argument allocated to (non-volatile) register */
7009                         switch (ainfo->storage) {
7010                         case ArgInIReg:
7011                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7012                                 break;
7013                         case ArgOnStack:
7014                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7015                                 break;
7016                         default:
7017                                 g_assert_not_reached ();
7018                         }
7019
7020                         if (ins == cfg->args [0]) {
7021                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7022                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7023                         }
7024                 }
7025         }
7026
7027 #ifdef HOST_WIN32
7028         if (method->save_lmf) {
7029                 code = emit_push_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7030         }
7031 #else
7032         args_clobbered = TRUE;
7033 #endif
7034
7035         if (trace) {
7036                 args_clobbered = TRUE;
7037                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7038         }
7039
7040         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7041                 args_clobbered = TRUE;
7042
7043         /*
7044          * Optimize the common case of the first bblock making a call with the same
7045          * arguments as the method. This works because the arguments are still in their
7046          * original argument registers.
7047          * FIXME: Generalize this
7048          */
7049         if (!args_clobbered) {
7050                 MonoBasicBlock *first_bb = cfg->bb_entry;
7051                 MonoInst *next;
7052
7053                 next = mono_bb_first_ins (first_bb);
7054                 if (!next && first_bb->next_bb) {
7055                         first_bb = first_bb->next_bb;
7056                         next = mono_bb_first_ins (first_bb);
7057                 }
7058
7059                 if (first_bb->in_count > 1)
7060                         next = NULL;
7061
7062                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7063                         ArgInfo *ainfo = cinfo->args + i;
7064                         gboolean match = FALSE;
7065
7066                         ins = cfg->args [i];
7067                         if (ins->opcode != OP_REGVAR) {
7068                                 switch (ainfo->storage) {
7069                                 case ArgInIReg: {
7070                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7071                                                 if (next->dreg == ainfo->reg) {
7072                                                         NULLIFY_INS (next);
7073                                                         match = TRUE;
7074                                                 } else {
7075                                                         next->opcode = OP_MOVE;
7076                                                         next->sreg1 = ainfo->reg;
7077                                                         /* Only continue if the instruction doesn't change argument regs */
7078                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7079                                                                 match = TRUE;
7080                                                 }
7081                                         }
7082                                         break;
7083                                 }
7084                                 default:
7085                                         break;
7086                                 }
7087                         } else {
7088                                 /* Argument allocated to (non-volatile) register */
7089                                 switch (ainfo->storage) {
7090                                 case ArgInIReg:
7091                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7092                                                 NULLIFY_INS (next);
7093                                                 match = TRUE;
7094                                         }
7095                                         break;
7096                                 default:
7097                                         break;
7098                                 }
7099                         }
7100
7101                         if (match) {
7102                                 next = next->next;
7103                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7104                                 if (!next)
7105                                         break;
7106                         }
7107                 }
7108         }
7109
7110         if (cfg->gen_seq_points) {
7111                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7112
7113                 /* Initialize seq_point_info_var */
7114                 if (cfg->compile_aot) {
7115                         /* Initialize the variable from a GOT slot */
7116                         /* Same as OP_AOTCONST */
7117                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7118                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7119                         g_assert (info_var->opcode == OP_REGOFFSET);
7120                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7121                 }
7122
7123                 /* Initialize ss_trigger_page_var */
7124                 ins = cfg->arch.ss_trigger_page_var;
7125
7126                 g_assert (ins->opcode == OP_REGOFFSET);
7127
7128                 if (cfg->compile_aot) {
7129                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7130                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7131                 } else {
7132                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7133                 }
7134                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7135         }
7136
7137         cfg->code_len = code - cfg->native_code;
7138
7139         g_assert (cfg->code_len < cfg->code_size);
7140
7141         return code;
7142 }
7143
7144 void
7145 mono_arch_emit_epilog (MonoCompile *cfg)
7146 {
7147         MonoMethod *method = cfg->method;
7148         int quad, pos, i;
7149         guint8 *code;
7150         int max_epilog_size;
7151         CallInfo *cinfo;
7152         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7153         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7154
7155         max_epilog_size = get_max_epilog_size (cfg);
7156
7157         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7158                 cfg->code_size *= 2;
7159                 cfg->native_code = mono_realloc_native_code (cfg);
7160                 cfg->stat_code_reallocs++;
7161         }
7162
7163         code = cfg->native_code + cfg->code_len;
7164
7165         cfg->has_unwind_info_for_epilog = TRUE;
7166
7167         /* Mark the start of the epilog */
7168         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7169
7170         /* Save the uwind state which is needed by the out-of-line code */
7171         mono_emit_unwind_op_remember_state (cfg, code);
7172
7173         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7174                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7175
7176         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7177         pos = 0;
7178
7179         if (method->save_lmf) {
7180 #ifdef HOST_WIN32
7181                 code = emit_pop_lmf (cfg, code, lmf_offset);
7182 #endif
7183
7184                 /* check if we need to restore protection of the stack after a stack overflow */
7185                 if (mono_get_jit_tls_offset () != -1) {
7186                         guint8 *patch;
7187                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7188                         /* we load the value in a separate instruction: this mechanism may be
7189                          * used later as a safer way to do thread interruption
7190                          */
7191                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7192                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7193                         patch = code;
7194                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7195                         /* note that the call trampoline will preserve eax/edx */
7196                         x86_call_reg (code, X86_ECX);
7197                         x86_patch (patch, code);
7198                 } else {
7199                         /* FIXME: maybe save the jit tls in the prolog */
7200                 }
7201                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7202                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7203                 }
7204         }
7205
7206         /* Restore callee saved regs */
7207         for (i = 0; i < AMD64_NREG; ++i) {
7208                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7209                         /* Restore only used_int_regs, not arch.saved_iregs */
7210                         if (cfg->used_int_regs & (1 << i)) {
7211                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7212                                 mono_emit_unwind_op_same_value (cfg, code, i);
7213                                 async_exc_point (code);
7214                         }
7215                         save_area_offset += 8;
7216                 }
7217         }
7218
7219         /* Load returned vtypes into registers if needed */
7220         cinfo = cfg->arch.cinfo;
7221         if (cinfo->ret.storage == ArgValuetypeInReg) {
7222                 ArgInfo *ainfo = &cinfo->ret;
7223                 MonoInst *inst = cfg->ret;
7224
7225                 for (quad = 0; quad < 2; quad ++) {
7226                         switch (ainfo->pair_storage [quad]) {
7227                         case ArgInIReg:
7228                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7229                                 break;
7230                         case ArgInFloatSSEReg:
7231                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7232                                 break;
7233                         case ArgInDoubleSSEReg:
7234                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7235                                 break;
7236                         case ArgNone:
7237                                 break;
7238                         default:
7239                                 g_assert_not_reached ();
7240                         }
7241                 }
7242         }
7243
7244         if (cfg->arch.omit_fp) {
7245                 if (cfg->arch.stack_alloc_size) {
7246                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7247                 }
7248         } else {
7249                 amd64_leave (code);
7250                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7251         }
7252         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7253         async_exc_point (code);
7254         amd64_ret (code);
7255
7256         /* Restore the unwind state to be the same as before the epilog */
7257         mono_emit_unwind_op_restore_state (cfg, code);
7258
7259         cfg->code_len = code - cfg->native_code;
7260
7261         g_assert (cfg->code_len < cfg->code_size);
7262 }
7263
7264 void
7265 mono_arch_emit_exceptions (MonoCompile *cfg)
7266 {
7267         MonoJumpInfo *patch_info;
7268         int nthrows, i;
7269         guint8 *code;
7270         MonoClass *exc_classes [16];
7271         guint8 *exc_throw_start [16], *exc_throw_end [16];
7272         guint32 code_size = 0;
7273
7274         /* Compute needed space */
7275         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7276                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7277                         code_size += 40;
7278                 if (patch_info->type == MONO_PATCH_INFO_R8)
7279                         code_size += 8 + 15; /* sizeof (double) + alignment */
7280                 if (patch_info->type == MONO_PATCH_INFO_R4)
7281                         code_size += 4 + 15; /* sizeof (float) + alignment */
7282                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7283                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7284         }
7285
7286 #ifdef __native_client_codegen__
7287         /* Give us extra room on Native Client.  This could be   */
7288         /* more carefully calculated, but bundle alignment makes */
7289         /* it much trickier, so *2 like other places is good.    */
7290         code_size *= 2;
7291 #endif
7292
7293         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7294                 cfg->code_size *= 2;
7295                 cfg->native_code = mono_realloc_native_code (cfg);
7296                 cfg->stat_code_reallocs++;
7297         }
7298
7299         code = cfg->native_code + cfg->code_len;
7300
7301         /* add code to raise exceptions */
7302         nthrows = 0;
7303         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7304                 switch (patch_info->type) {
7305                 case MONO_PATCH_INFO_EXC: {
7306                         MonoClass *exc_class;
7307                         guint8 *buf, *buf2;
7308                         guint32 throw_ip;
7309
7310                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7311
7312                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7313                         g_assert (exc_class);
7314                         throw_ip = patch_info->ip.i;
7315
7316                         //x86_breakpoint (code);
7317                         /* Find a throw sequence for the same exception class */
7318                         for (i = 0; i < nthrows; ++i)
7319                                 if (exc_classes [i] == exc_class)
7320                                         break;
7321                         if (i < nthrows) {
7322                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7323                                 x86_jump_code (code, exc_throw_start [i]);
7324                                 patch_info->type = MONO_PATCH_INFO_NONE;
7325                         }
7326                         else {
7327                                 buf = code;
7328                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7329                                 buf2 = code;
7330
7331                                 if (nthrows < 16) {
7332                                         exc_classes [nthrows] = exc_class;
7333                                         exc_throw_start [nthrows] = code;
7334                                 }
7335                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7336
7337                                 patch_info->type = MONO_PATCH_INFO_NONE;
7338
7339                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7340
7341                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7342                                 while (buf < buf2)
7343                                         x86_nop (buf);
7344
7345                                 if (nthrows < 16) {
7346                                         exc_throw_end [nthrows] = code;
7347                                         nthrows ++;
7348                                 }
7349                         }
7350                         break;
7351                 }
7352                 default:
7353                         /* do nothing */
7354                         break;
7355                 }
7356                 g_assert(code < cfg->native_code + cfg->code_size);
7357         }
7358
7359         /* Handle relocations with RIP relative addressing */
7360         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7361                 gboolean remove = FALSE;
7362                 guint8 *orig_code = code;
7363
7364                 switch (patch_info->type) {
7365                 case MONO_PATCH_INFO_R8:
7366                 case MONO_PATCH_INFO_R4: {
7367                         guint8 *pos, *patch_pos;
7368                         guint32 target_pos;
7369
7370                         /* The SSE opcodes require a 16 byte alignment */
7371 #if defined(__default_codegen__)
7372                         code = (guint8*)ALIGN_TO (code, 16);
7373 #elif defined(__native_client_codegen__)
7374                         {
7375                                 /* Pad this out with HLT instructions  */
7376                                 /* or we can get garbage bytes emitted */
7377                                 /* which will fail validation          */
7378                                 guint8 *aligned_code;
7379                                 /* extra align to make room for  */
7380                                 /* mov/push below                      */
7381                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7382                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7383                                 /* The technique of hiding data in an  */
7384                                 /* instruction has a problem here: we  */
7385                                 /* need the data aligned to a 16-byte  */
7386                                 /* boundary but the instruction cannot */
7387                                 /* cross the bundle boundary. so only  */
7388                                 /* odd multiples of 16 can be used     */
7389                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7390                                         aligned_code += 16;
7391                                 }
7392                                 while (code < aligned_code) {
7393                                         *(code++) = 0xf4; /* hlt */
7394                                 }
7395                         }
7396 #endif
7397
7398                         pos = cfg->native_code + patch_info->ip.i;
7399                         if (IS_REX (pos [1])) {
7400                                 patch_pos = pos + 5;
7401                                 target_pos = code - pos - 9;
7402                         }
7403                         else {
7404                                 patch_pos = pos + 4;
7405                                 target_pos = code - pos - 8;
7406                         }
7407
7408                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7409 #ifdef __native_client_codegen__
7410                                 /* Hide 64-bit data in a         */
7411                                 /* "mov imm64, r11" instruction. */
7412                                 /* write it before the start of  */
7413                                 /* the data*/
7414                                 *(code-2) = 0x49; /* prefix      */
7415                                 *(code-1) = 0xbb; /* mov X, %r11 */
7416 #endif
7417                                 *(double*)code = *(double*)patch_info->data.target;
7418                                 code += sizeof (double);
7419                         } else {
7420 #ifdef __native_client_codegen__
7421                                 /* Hide 32-bit data in a        */
7422                                 /* "push imm32" instruction.    */
7423                                 *(code-1) = 0x68; /* push */
7424 #endif
7425                                 *(float*)code = *(float*)patch_info->data.target;
7426                                 code += sizeof (float);
7427                         }
7428
7429                         *(guint32*)(patch_pos) = target_pos;
7430
7431                         remove = TRUE;
7432                         break;
7433                 }
7434                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7435                         guint8 *pos;
7436
7437                         if (cfg->compile_aot)
7438                                 continue;
7439
7440                         /*loading is faster against aligned addresses.*/
7441                         code = (guint8*)ALIGN_TO (code, 8);
7442                         memset (orig_code, 0, code - orig_code);
7443
7444                         pos = cfg->native_code + patch_info->ip.i;
7445
7446                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7447                         if (IS_REX (pos [1]))
7448                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7449                         else
7450                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7451
7452                         *(gpointer*)code = (gpointer)patch_info->data.target;
7453                         code += sizeof (gpointer);
7454
7455                         remove = TRUE;
7456                         break;
7457                 }
7458                 default:
7459                         break;
7460                 }
7461
7462                 if (remove) {
7463                         if (patch_info == cfg->patch_info)
7464                                 cfg->patch_info = patch_info->next;
7465                         else {
7466                                 MonoJumpInfo *tmp;
7467
7468                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7469                                         ;
7470                                 tmp->next = patch_info->next;
7471                         }
7472                 }
7473                 g_assert (code < cfg->native_code + cfg->code_size);
7474         }
7475
7476         cfg->code_len = code - cfg->native_code;
7477
7478         g_assert (cfg->code_len < cfg->code_size);
7479
7480 }
7481
7482 #endif /* DISABLE_JIT */
7483
7484 void*
7485 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7486 {
7487         guchar *code = p;
7488         CallInfo *cinfo = NULL;
7489         MonoMethodSignature *sig;
7490         MonoInst *inst;
7491         int i, n, stack_area = 0;
7492
7493         /* Keep this in sync with mono_arch_get_argument_info */
7494
7495         if (enable_arguments) {
7496                 /* Allocate a new area on the stack and save arguments there */
7497                 sig = mono_method_signature (cfg->method);
7498
7499                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7500
7501                 n = sig->param_count + sig->hasthis;
7502
7503                 stack_area = ALIGN_TO (n * 8, 16);
7504
7505                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7506
7507                 for (i = 0; i < n; ++i) {
7508                         inst = cfg->args [i];
7509
7510                         if (inst->opcode == OP_REGVAR)
7511                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7512                         else {
7513                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7514                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7515                         }
7516                 }
7517         }
7518
7519         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7520         amd64_set_reg_template (code, AMD64_ARG_REG1);
7521         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7522         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7523
7524         if (enable_arguments)
7525                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7526
7527         return code;
7528 }
7529
7530 enum {
7531         SAVE_NONE,
7532         SAVE_STRUCT,
7533         SAVE_EAX,
7534         SAVE_EAX_EDX,
7535         SAVE_XMM
7536 };
7537
7538 void*
7539 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7540 {
7541         guchar *code = p;
7542         int save_mode = SAVE_NONE;
7543         MonoMethod *method = cfg->method;
7544         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7545         int i;
7546
7547         switch (ret_type->type) {
7548         case MONO_TYPE_VOID:
7549                 /* special case string .ctor icall */
7550                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7551                         save_mode = SAVE_EAX;
7552                 else
7553                         save_mode = SAVE_NONE;
7554                 break;
7555         case MONO_TYPE_I8:
7556         case MONO_TYPE_U8:
7557                 save_mode = SAVE_EAX;
7558                 break;
7559         case MONO_TYPE_R4:
7560         case MONO_TYPE_R8:
7561                 save_mode = SAVE_XMM;
7562                 break;
7563         case MONO_TYPE_GENERICINST:
7564                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7565                         save_mode = SAVE_EAX;
7566                         break;
7567                 }
7568                 /* Fall through */
7569         case MONO_TYPE_VALUETYPE:
7570                 save_mode = SAVE_STRUCT;
7571                 break;
7572         default:
7573                 save_mode = SAVE_EAX;
7574                 break;
7575         }
7576
7577         /* Save the result and copy it into the proper argument register */
7578         switch (save_mode) {
7579         case SAVE_EAX:
7580                 amd64_push_reg (code, AMD64_RAX);
7581                 /* Align stack */
7582                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7583                 if (enable_arguments)
7584                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7585                 break;
7586         case SAVE_STRUCT:
7587                 /* FIXME: */
7588                 if (enable_arguments)
7589                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7590                 break;
7591         case SAVE_XMM:
7592                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7593                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7594                 /* Align stack */
7595                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7596                 /*
7597                  * The result is already in the proper argument register so no copying
7598                  * needed.
7599                  */
7600                 break;
7601         case SAVE_NONE:
7602                 break;
7603         default:
7604                 g_assert_not_reached ();
7605         }
7606
7607         /* Set %al since this is a varargs call */
7608         if (save_mode == SAVE_XMM)
7609                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7610         else
7611                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7612
7613         if (preserve_argument_registers) {
7614                 for (i = 0; i < PARAM_REGS; ++i)
7615                         amd64_push_reg (code, param_regs [i]);
7616         }
7617
7618         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7619         amd64_set_reg_template (code, AMD64_ARG_REG1);
7620         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7621
7622         if (preserve_argument_registers) {
7623                 for (i = PARAM_REGS - 1; i >= 0; --i)
7624                         amd64_pop_reg (code, param_regs [i]);
7625         }
7626
7627         /* Restore result */
7628         switch (save_mode) {
7629         case SAVE_EAX:
7630                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7631                 amd64_pop_reg (code, AMD64_RAX);
7632                 break;
7633         case SAVE_STRUCT:
7634                 /* FIXME: */
7635                 break;
7636         case SAVE_XMM:
7637                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7638                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7639                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7640                 break;
7641         case SAVE_NONE:
7642                 break;
7643         default:
7644                 g_assert_not_reached ();
7645         }
7646
7647         return code;
7648 }
7649
7650 void
7651 mono_arch_flush_icache (guint8 *code, gint size)
7652 {
7653         /* Not needed */
7654 }
7655
7656 void
7657 mono_arch_flush_register_windows (void)
7658 {
7659 }
7660
7661 gboolean
7662 mono_arch_is_inst_imm (gint64 imm)
7663 {
7664         return amd64_is_imm32 (imm);
7665 }
7666
7667 /*
7668  * Determine whenever the trap whose info is in SIGINFO is caused by
7669  * integer overflow.
7670  */
7671 gboolean
7672 mono_arch_is_int_overflow (void *sigctx, void *info)
7673 {
7674         MonoContext ctx;
7675         guint8* rip;
7676         int reg;
7677         gint64 value;
7678
7679         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7680
7681         rip = (guint8*)ctx.rip;
7682
7683         if (IS_REX (rip [0])) {
7684                 reg = amd64_rex_b (rip [0]);
7685                 rip ++;
7686         }
7687         else
7688                 reg = 0;
7689
7690         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7691                 /* idiv REG */
7692                 reg += x86_modrm_rm (rip [1]);
7693
7694                 switch (reg) {
7695                 case AMD64_RAX:
7696                         value = ctx.rax;
7697                         break;
7698                 case AMD64_RBX:
7699                         value = ctx.rbx;
7700                         break;
7701                 case AMD64_RCX:
7702                         value = ctx.rcx;
7703                         break;
7704                 case AMD64_RDX:
7705                         value = ctx.rdx;
7706                         break;
7707                 case AMD64_RBP:
7708                         value = ctx.rbp;
7709                         break;
7710                 case AMD64_RSP:
7711                         value = ctx.rsp;
7712                         break;
7713                 case AMD64_RSI:
7714                         value = ctx.rsi;
7715                         break;
7716                 case AMD64_RDI:
7717                         value = ctx.rdi;
7718                         break;
7719                 case AMD64_R12:
7720                         value = ctx.r12;
7721                         break;
7722                 case AMD64_R13:
7723                         value = ctx.r13;
7724                         break;
7725                 case AMD64_R14:
7726                         value = ctx.r14;
7727                         break;
7728                 case AMD64_R15:
7729                         value = ctx.r15;
7730                         break;
7731                 default:
7732                         g_assert_not_reached ();
7733                         reg = -1;
7734                 }
7735
7736                 if (value == -1)
7737                         return TRUE;
7738         }
7739
7740         return FALSE;
7741 }
7742
7743 guint32
7744 mono_arch_get_patch_offset (guint8 *code)
7745 {
7746         return 3;
7747 }
7748
7749 /**
7750  * mono_breakpoint_clean_code:
7751  *
7752  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7753  * breakpoints in the original code, they are removed in the copy.
7754  *
7755  * Returns TRUE if no sw breakpoint was present.
7756  */
7757 gboolean
7758 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7759 {
7760         int i;
7761         gboolean can_write = TRUE;
7762         /*
7763          * If method_start is non-NULL we need to perform bound checks, since we access memory
7764          * at code - offset we could go before the start of the method and end up in a different
7765          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7766          * instead.
7767          */
7768         if (!method_start || code - offset >= method_start) {
7769                 memcpy (buf, code - offset, size);
7770         } else {
7771                 int diff = code - method_start;
7772                 memset (buf, 0, size);
7773                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7774         }
7775         code -= offset;
7776         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7777                 int idx = mono_breakpoint_info_index [i];
7778                 guint8 *ptr;
7779                 if (idx < 1)
7780                         continue;
7781                 ptr = mono_breakpoint_info [idx].address;
7782                 if (ptr >= code && ptr < code + size) {
7783                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7784                         can_write = FALSE;
7785                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7786                         buf [ptr - code] = saved_byte;
7787                 }
7788         }
7789         return can_write;
7790 }
7791
7792 #if defined(__native_client_codegen__)
7793 /* For membase calls, we want the base register. for Native Client,  */
7794 /* all indirect calls have the following sequence with the given sizes: */
7795 /* mov %eXX,%eXX                                [2-3]   */
7796 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7797 /* and $0xffffffffffffffe0,%r11d                [4]     */
7798 /* add %r15,%r11                                [3]     */
7799 /* callq *%r11                                  [3]     */
7800
7801
7802 /* Determine if code points to a NaCl call-through-register sequence, */
7803 /* (i.e., the last 3 instructions listed above) */
7804 int
7805 is_nacl_call_reg_sequence(guint8* code)
7806 {
7807         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7808                                "\x4d\x03\xdf"     /* add */
7809                                "\x41\xff\xd3";   /* call */
7810         return memcmp(code, sequence, 10) == 0;
7811 }
7812
7813 /* Determine if code points to the first opcode of the mov membase component */
7814 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7815 /* (there could be a REX prefix before the opcode but it is ignored) */
7816 static int
7817 is_nacl_indirect_call_membase_sequence(guint8* code)
7818 {
7819                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7820         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7821                /* and that src reg = dest reg */
7822                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7823                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7824                IS_REX(code[2]) &&
7825                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7826                /* and has dst of r11 and base of r15 */
7827                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7828                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7829 }
7830 #endif /* __native_client_codegen__ */
7831
7832 int
7833 mono_arch_get_this_arg_reg (guint8 *code)
7834 {
7835         return AMD64_ARG_REG1;
7836 }
7837
7838 gpointer
7839 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7840 {
7841         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7842 }
7843
7844 #define MAX_ARCH_DELEGATE_PARAMS 10
7845
7846 static gpointer
7847 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7848 {
7849         guint8 *code, *start;
7850         int i;
7851
7852         if (has_target) {
7853                 start = code = mono_global_codeman_reserve (64);
7854
7855                 /* Replace the this argument with the target */
7856                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7857                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7858                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7859
7860                 g_assert ((code - start) < 64);
7861         } else {
7862                 start = code = mono_global_codeman_reserve (64);
7863
7864                 if (param_count == 0) {
7865                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7866                 } else {
7867                         /* We have to shift the arguments left */
7868                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7869                         for (i = 0; i < param_count; ++i) {
7870 #ifdef HOST_WIN32
7871                                 if (i < 3)
7872                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7873                                 else
7874                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7875 #else
7876                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7877 #endif
7878                         }
7879
7880                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7881                 }
7882                 g_assert ((code - start) < 64);
7883         }
7884
7885         nacl_global_codeman_validate(&start, 64, &code);
7886
7887         mono_debug_add_delegate_trampoline (start, code - start);
7888
7889         if (code_len)
7890                 *code_len = code - start;
7891
7892
7893         if (mono_jit_map_is_enabled ()) {
7894                 char *buff;
7895                 if (has_target)
7896                         buff = (char*)"delegate_invoke_has_target";
7897                 else
7898                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7899                 mono_emit_jit_tramp (start, code - start, buff);
7900                 if (!has_target)
7901                         g_free (buff);
7902         }
7903
7904         return start;
7905 }
7906
7907 /*
7908  * mono_arch_get_delegate_invoke_impls:
7909  *
7910  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7911  * trampolines.
7912  */
7913 GSList*
7914 mono_arch_get_delegate_invoke_impls (void)
7915 {
7916         GSList *res = NULL;
7917         guint8 *code;
7918         guint32 code_len;
7919         int i;
7920         char *tramp_name;
7921
7922         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7923         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7924
7925         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7926                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7927                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7928                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7929                 g_free (tramp_name);
7930         }
7931
7932         return res;
7933 }
7934
7935 gpointer
7936 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7937 {
7938         guint8 *code, *start;
7939         int i;
7940
7941         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7942                 return NULL;
7943
7944         /* FIXME: Support more cases */
7945         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7946                 return NULL;
7947
7948         if (has_target) {
7949                 static guint8* cached = NULL;
7950
7951                 if (cached)
7952                         return cached;
7953
7954                 if (mono_aot_only)
7955                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7956                 else
7957                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7958
7959                 mono_memory_barrier ();
7960
7961                 cached = start;
7962         } else {
7963                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7964                 for (i = 0; i < sig->param_count; ++i)
7965                         if (!mono_is_regsize_var (sig->params [i]))
7966                                 return NULL;
7967                 if (sig->param_count > 4)
7968                         return NULL;
7969
7970                 code = cache [sig->param_count];
7971                 if (code)
7972                         return code;
7973
7974                 if (mono_aot_only) {
7975                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7976                         start = mono_aot_get_trampoline (name);
7977                         g_free (name);
7978                 } else {
7979                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7980                 }
7981
7982                 mono_memory_barrier ();
7983
7984                 cache [sig->param_count] = start;
7985         }
7986
7987         return start;
7988 }
7989 void
7990 mono_arch_finish_init (void)
7991 {
7992 #ifdef HOST_WIN32
7993         /*
7994          * We need to init this multiple times, since when we are first called, the key might not
7995          * be initialized yet.
7996          */
7997         jit_tls_offset = mono_get_jit_tls_key ();
7998
7999         /* Only 64 tls entries can be accessed using inline code */
8000         if (jit_tls_offset >= 64)
8001                 jit_tls_offset = -1;
8002 #else
8003 #ifdef MONO_XEN_OPT
8004         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8005 #endif
8006 #endif
8007 }
8008
8009 void
8010 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8011 {
8012 }
8013
8014 #ifdef MONO_ARCH_HAVE_IMT
8015
8016 #if defined(__default_codegen__)
8017 #define CMP_SIZE (6 + 1)
8018 #define CMP_REG_REG_SIZE (4 + 1)
8019 #define BR_SMALL_SIZE 2
8020 #define BR_LARGE_SIZE 6
8021 #define MOV_REG_IMM_SIZE 10
8022 #define MOV_REG_IMM_32BIT_SIZE 6
8023 #define JUMP_REG_SIZE (2 + 1)
8024 #elif defined(__native_client_codegen__)
8025 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8026 #define CMP_SIZE ((6 + 1) * 2 - 1)
8027 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8028 #define BR_SMALL_SIZE (2 * 2 - 1)
8029 #define BR_LARGE_SIZE (6 * 2 - 1)
8030 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8031 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8032 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8033 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8034 /* Jump membase's size is large and unpredictable    */
8035 /* in native client, just pad it out a whole bundle. */
8036 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8037 #endif
8038
8039 static int
8040 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8041 {
8042         int i, distance = 0;
8043         for (i = start; i < target; ++i)
8044                 distance += imt_entries [i]->chunk_size;
8045         return distance;
8046 }
8047
8048 /*
8049  * LOCKING: called with the domain lock held
8050  */
8051 gpointer
8052 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8053         gpointer fail_tramp)
8054 {
8055         int i;
8056         int size = 0;
8057         guint8 *code, *start;
8058         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8059
8060         for (i = 0; i < count; ++i) {
8061                 MonoIMTCheckItem *item = imt_entries [i];
8062                 if (item->is_equals) {
8063                         if (item->check_target_idx) {
8064                                 if (!item->compare_done) {
8065                                         if (amd64_is_imm32 (item->key))
8066                                                 item->chunk_size += CMP_SIZE;
8067                                         else
8068                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8069                                 }
8070                                 if (item->has_target_code) {
8071                                         item->chunk_size += MOV_REG_IMM_SIZE;
8072                                 } else {
8073                                         if (vtable_is_32bit)
8074                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8075                                         else
8076                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8077 #ifdef __native_client_codegen__
8078                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8079 #endif
8080                                 }
8081                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8082                         } else {
8083                                 if (fail_tramp) {
8084                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8085                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8086                                 } else {
8087                                         if (vtable_is_32bit)
8088                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8089                                         else
8090                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8091                                         item->chunk_size += JUMP_REG_SIZE;
8092                                         /* with assert below:
8093                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8094                                          */
8095 #ifdef __native_client_codegen__
8096                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8097 #endif
8098                                 }
8099                         }
8100                 } else {
8101                         if (amd64_is_imm32 (item->key))
8102                                 item->chunk_size += CMP_SIZE;
8103                         else
8104                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8105                         item->chunk_size += BR_LARGE_SIZE;
8106                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8107                 }
8108                 size += item->chunk_size;
8109         }
8110 #if defined(__native_client__) && defined(__native_client_codegen__)
8111         /* In Native Client, we don't re-use thunks, allocate from the */
8112         /* normal code manager paths. */
8113         code = mono_domain_code_reserve (domain, size);
8114 #else
8115         if (fail_tramp)
8116                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8117         else
8118                 code = mono_domain_code_reserve (domain, size);
8119 #endif
8120         start = code;
8121         for (i = 0; i < count; ++i) {
8122                 MonoIMTCheckItem *item = imt_entries [i];
8123                 item->code_target = code;
8124                 if (item->is_equals) {
8125                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8126
8127                         if (item->check_target_idx || fail_case) {
8128                                 if (!item->compare_done || fail_case) {
8129                                         if (amd64_is_imm32 (item->key))
8130                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8131                                         else {
8132                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8133                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8134                                         }
8135                                 }
8136                                 item->jmp_code = code;
8137                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8138                                 if (item->has_target_code) {
8139                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8140                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8141                                 } else {
8142                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8143                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8144                                 }
8145
8146                                 if (fail_case) {
8147                                         amd64_patch (item->jmp_code, code);
8148                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8149                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8150                                         item->jmp_code = NULL;
8151                                 }
8152                         } else {
8153                                 /* enable the commented code to assert on wrong method */
8154 #if 0
8155                                 if (amd64_is_imm32 (item->key))
8156                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8157                                 else {
8158                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8159                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8160                                 }
8161                                 item->jmp_code = code;
8162                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8163                                 /* See the comment below about R10 */
8164                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8165                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8166                                 amd64_patch (item->jmp_code, code);
8167                                 amd64_breakpoint (code);
8168                                 item->jmp_code = NULL;
8169 #else
8170                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8171                                    needs to be preserved.  R10 needs
8172                                    to be preserved for calls which
8173                                    require a runtime generic context,
8174                                    but interface calls don't. */
8175                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8176                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8177 #endif
8178                         }
8179                 } else {
8180                         if (amd64_is_imm32 (item->key))
8181                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8182                         else {
8183                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8184                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8185                         }
8186                         item->jmp_code = code;
8187                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8188                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8189                         else
8190                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8191                 }
8192                 g_assert (code - item->code_target <= item->chunk_size);
8193         }
8194         /* patch the branches to get to the target items */
8195         for (i = 0; i < count; ++i) {
8196                 MonoIMTCheckItem *item = imt_entries [i];
8197                 if (item->jmp_code) {
8198                         if (item->check_target_idx) {
8199                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8200                         }
8201                 }
8202         }
8203
8204         if (!fail_tramp)
8205                 mono_stats.imt_thunks_size += code - start;
8206         g_assert (code - start <= size);
8207
8208         nacl_domain_code_validate(domain, &start, size, &code);
8209
8210         return start;
8211 }
8212
8213 MonoMethod*
8214 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8215 {
8216         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8217 }
8218 #endif
8219
8220 MonoVTable*
8221 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8222 {
8223         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8224 }
8225
8226 GSList*
8227 mono_arch_get_cie_program (void)
8228 {
8229         GSList *l = NULL;
8230
8231         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8232         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8233
8234         return l;
8235 }
8236
8237 MonoInst*
8238 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8239 {
8240         MonoInst *ins = NULL;
8241         int opcode = 0;
8242
8243         if (cmethod->klass == mono_defaults.math_class) {
8244                 if (strcmp (cmethod->name, "Sin") == 0) {
8245                         opcode = OP_SIN;
8246                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8247                         opcode = OP_COS;
8248                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8249                         opcode = OP_SQRT;
8250                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8251                         opcode = OP_ABS;
8252                 }
8253
8254                 if (opcode) {
8255                         MONO_INST_NEW (cfg, ins, opcode);
8256                         ins->type = STACK_R8;
8257                         ins->dreg = mono_alloc_freg (cfg);
8258                         ins->sreg1 = args [0]->dreg;
8259                         MONO_ADD_INS (cfg->cbb, ins);
8260                 }
8261
8262                 opcode = 0;
8263                 if (cfg->opt & MONO_OPT_CMOV) {
8264                         if (strcmp (cmethod->name, "Min") == 0) {
8265                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8266                                         opcode = OP_IMIN;
8267                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8268                                         opcode = OP_IMIN_UN;
8269                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8270                                         opcode = OP_LMIN;
8271                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8272                                         opcode = OP_LMIN_UN;
8273                         } else if (strcmp (cmethod->name, "Max") == 0) {
8274                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8275                                         opcode = OP_IMAX;
8276                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8277                                         opcode = OP_IMAX_UN;
8278                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8279                                         opcode = OP_LMAX;
8280                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8281                                         opcode = OP_LMAX_UN;
8282                         }
8283                 }
8284
8285                 if (opcode) {
8286                         MONO_INST_NEW (cfg, ins, opcode);
8287                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8288                         ins->dreg = mono_alloc_ireg (cfg);
8289                         ins->sreg1 = args [0]->dreg;
8290                         ins->sreg2 = args [1]->dreg;
8291                         MONO_ADD_INS (cfg->cbb, ins);
8292                 }
8293
8294 #if 0
8295                 /* OP_FREM is not IEEE compatible */
8296                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8297                         MONO_INST_NEW (cfg, ins, OP_FREM);
8298                         ins->inst_i0 = args [0];
8299                         ins->inst_i1 = args [1];
8300                 }
8301 #endif
8302         }
8303
8304         /*
8305          * Can't implement CompareExchange methods this way since they have
8306          * three arguments.
8307          */
8308
8309         return ins;
8310 }
8311
8312 gboolean
8313 mono_arch_print_tree (MonoInst *tree, int arity)
8314 {
8315         return 0;
8316 }
8317
8318 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8319
8320 mgreg_t
8321 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8322 {
8323         switch (reg) {
8324         case AMD64_RCX: return ctx->rcx;
8325         case AMD64_RDX: return ctx->rdx;
8326         case AMD64_RBX: return ctx->rbx;
8327         case AMD64_RBP: return ctx->rbp;
8328         case AMD64_RSP: return ctx->rsp;
8329         default:
8330                 return _CTX_REG (ctx, rax, reg);
8331         }
8332 }
8333
8334 void
8335 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8336 {
8337         switch (reg) {
8338         case AMD64_RCX:
8339                 ctx->rcx = val;
8340                 break;
8341         case AMD64_RDX:
8342                 ctx->rdx = val;
8343                 break;
8344         case AMD64_RBX:
8345                 ctx->rbx = val;
8346                 break;
8347         case AMD64_RBP:
8348                 ctx->rbp = val;
8349                 break;
8350         case AMD64_RSP:
8351                 ctx->rsp = val;
8352                 break;
8353         default:
8354                 _CTX_REG (ctx, rax, reg) = val;
8355         }
8356 }
8357
8358 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8359 gpointer
8360 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8361 {
8362         int offset;
8363         gpointer *sp, old_value;
8364         char *bp;
8365         const unsigned char *handler;
8366
8367         /*Decode the first instruction to figure out where did we store the spvar*/
8368         /*Our jit MUST generate the following:
8369          mov    %rsp, ?(%rbp)
8370
8371          Which is encoded as: REX.W 0x89 mod_rm
8372          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8373                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8374                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8375
8376         FIXME can we generate frameless methods on this case?
8377
8378         */
8379         handler = clause->handler_start;
8380
8381         /*REX.W*/
8382         if (*handler != 0x48)
8383                 return NULL;
8384         ++handler;
8385
8386         /*mov r, r/m */
8387         if (*handler != 0x89)
8388                 return NULL;
8389         ++handler;
8390
8391         if (*handler == 0x65)
8392                 offset = *(signed char*)(handler + 1);
8393         else if (*handler == 0xA5)
8394                 offset = *(int*)(handler + 1);
8395         else
8396                 return NULL;
8397
8398         /*Load the spvar*/
8399         bp = MONO_CONTEXT_GET_BP (ctx);
8400         sp = *(gpointer*)(bp + offset);
8401
8402         old_value = *sp;
8403         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8404                 return old_value;
8405
8406         *sp = new_value;
8407
8408         return old_value;
8409 }
8410
8411 /*
8412  * mono_arch_emit_load_aotconst:
8413  *
8414  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8415  * TARGET from the mscorlib GOT in full-aot code.
8416  * On AMD64, the result is placed into R11.
8417  */
8418 guint8*
8419 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8420 {
8421         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8422         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8423
8424         return code;
8425 }
8426
8427 /*
8428  * mono_arch_get_trampolines:
8429  *
8430  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8431  * for AOT.
8432  */
8433 GSList *
8434 mono_arch_get_trampolines (gboolean aot)
8435 {
8436         return mono_amd64_get_exception_trampolines (aot);
8437 }
8438
8439 /* Soft Debug support */
8440 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8441
8442 /*
8443  * mono_arch_set_breakpoint:
8444  *
8445  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8446  * The location should contain code emitted by OP_SEQ_POINT.
8447  */
8448 void
8449 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8450 {
8451         guint8 *code = ip;
8452         guint8 *orig_code = code;
8453
8454         if (ji->from_aot) {
8455                 guint32 native_offset = ip - (guint8*)ji->code_start;
8456                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8457
8458                 g_assert (info->bp_addrs [native_offset] == 0);
8459                 info->bp_addrs [native_offset] = bp_trigger_page;
8460         } else {
8461                 /*
8462                  * In production, we will use int3 (has to fix the size in the md
8463                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8464                  * instead.
8465                  */
8466                 g_assert (code [0] == 0x90);
8467                 if (breakpoint_size == 8) {
8468                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8469                 } else {
8470                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8471                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8472                 }
8473
8474                 g_assert (code - orig_code == breakpoint_size);
8475         }
8476 }
8477
8478 /*
8479  * mono_arch_clear_breakpoint:
8480  *
8481  *   Clear the breakpoint at IP.
8482  */
8483 void
8484 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8485 {
8486         guint8 *code = ip;
8487         int i;
8488
8489         if (ji->from_aot) {
8490                 guint32 native_offset = ip - (guint8*)ji->code_start;
8491                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8492
8493                 g_assert (info->bp_addrs [native_offset] == 0);
8494                 info->bp_addrs [native_offset] = info;
8495         } else {
8496                 for (i = 0; i < breakpoint_size; ++i)
8497                         x86_nop (code);
8498         }
8499 }
8500
8501 gboolean
8502 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8503 {
8504 #ifdef HOST_WIN32
8505         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8506         return FALSE;
8507 #else
8508         siginfo_t* sinfo = (siginfo_t*) info;
8509         /* Sometimes the address is off by 4 */
8510         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8511                 return TRUE;
8512         else
8513                 return FALSE;
8514 #endif
8515 }
8516
8517 /*
8518  * mono_arch_skip_breakpoint:
8519  *
8520  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8521  * we resume, the instruction is not executed again.
8522  */
8523 void
8524 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8525 {
8526         if (ji->from_aot) {
8527                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8528                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8529         } else {
8530                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8531         }
8532 }
8533
8534 /*
8535  * mono_arch_start_single_stepping:
8536  *
8537  *   Start single stepping.
8538  */
8539 void
8540 mono_arch_start_single_stepping (void)
8541 {
8542         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8543 }
8544
8545 /*
8546  * mono_arch_stop_single_stepping:
8547  *
8548  *   Stop single stepping.
8549  */
8550 void
8551 mono_arch_stop_single_stepping (void)
8552 {
8553         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8554 }
8555
8556 /*
8557  * mono_arch_is_single_step_event:
8558  *
8559  *   Return whenever the machine state in SIGCTX corresponds to a single
8560  * step event.
8561  */
8562 gboolean
8563 mono_arch_is_single_step_event (void *info, void *sigctx)
8564 {
8565 #ifdef HOST_WIN32
8566         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8567         return FALSE;
8568 #else
8569         siginfo_t* sinfo = (siginfo_t*) info;
8570         /* Sometimes the address is off by 4 */
8571         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8572                 return TRUE;
8573         else
8574                 return FALSE;
8575 #endif
8576 }
8577
8578 /*
8579  * mono_arch_skip_single_step:
8580  *
8581  *   Modify CTX so the ip is placed after the single step trigger instruction,
8582  * we resume, the instruction is not executed again.
8583  */
8584 void
8585 mono_arch_skip_single_step (MonoContext *ctx)
8586 {
8587         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8588 }
8589
8590 /*
8591  * mono_arch_create_seq_point_info:
8592  *
8593  *   Return a pointer to a data structure which is used by the sequence
8594  * point implementation in AOTed code.
8595  */
8596 gpointer
8597 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8598 {
8599         SeqPointInfo *info;
8600         MonoJitInfo *ji;
8601         int i;
8602
8603         // FIXME: Add a free function
8604
8605         mono_domain_lock (domain);
8606         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8607                                                                 code);
8608         mono_domain_unlock (domain);
8609
8610         if (!info) {
8611                 ji = mono_jit_info_table_find (domain, (char*)code);
8612                 g_assert (ji);
8613
8614                 // FIXME: Optimize the size
8615                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8616
8617                 info->ss_trigger_page = ss_trigger_page;
8618                 info->bp_trigger_page = bp_trigger_page;
8619                 /* Initialize to a valid address */
8620                 for (i = 0; i < ji->code_size; ++i)
8621                         info->bp_addrs [i] = info;
8622
8623                 mono_domain_lock (domain);
8624                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8625                                                          code, info);
8626                 mono_domain_unlock (domain);
8627         }
8628
8629         return info;
8630 }
8631
8632 void
8633 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8634 {
8635         ext->lmf.previous_lmf = prev_lmf;
8636         /* Mark that this is a MonoLMFExt */
8637         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8638         ext->lmf.rsp = (gssize)ext;
8639 }
8640
8641 #endif
8642
8643 gboolean
8644 mono_arch_opcode_supported (int opcode)
8645 {
8646         switch (opcode) {
8647         case OP_ATOMIC_ADD_I4:
8648         case OP_ATOMIC_ADD_I8:
8649         case OP_ATOMIC_EXCHANGE_I4:
8650         case OP_ATOMIC_EXCHANGE_I8:
8651         case OP_ATOMIC_CAS_I4:
8652         case OP_ATOMIC_CAS_I8:
8653                 return TRUE;
8654         default:
8655                 return FALSE;
8656         }
8657 }