mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_I1:
 598         case MONO_TYPE_U1:
 599         case MONO_TYPE_I2:
 600         case MONO_TYPE_U2:
 601         case MONO_TYPE_I4:
 602         case MONO_TYPE_U4:
 603         case MONO_TYPE_I:
 604         case MONO_TYPE_U:
 605         case MONO_TYPE_STRING:
 606         case MONO_TYPE_OBJECT:
 607         case MONO_TYPE_CLASS:
 608         case MONO_TYPE_SZARRAY:
 609         case MONO_TYPE_PTR:
 610         case MONO_TYPE_FNPTR:
 611         case MONO_TYPE_ARRAY:
 612         case MONO_TYPE_I8:
 613         case MONO_TYPE_U8:
 614                 class2 = ARG_CLASS_INTEGER;
 615                 break;
 616         case MONO_TYPE_R4:
 617         case MONO_TYPE_R8:
 618 #ifdef HOST_WIN32
 619                 class2 = ARG_CLASS_INTEGER;
 620 #else
 621                 class2 = ARG_CLASS_SSE;
 622 #endif
 623                 break;
 624
 625         case MONO_TYPE_TYPEDBYREF:
 626                 g_assert_not_reached ();
 627
 628         case MONO_TYPE_GENERICINST:
 629                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 630                         class2 = ARG_CLASS_INTEGER;
 631                         break;
 632                 }
 633                 /* fall through */
 634         case MONO_TYPE_VALUETYPE: {
 635                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 636                 int i;
 637
 638                 for (i = 0; i < info->num_fields; ++i) {
 639                         class2 = class1;
 640                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 641                 }
 642                 break;
 643         }
 644         default:
 645                 g_assert_not_reached ();
 646         }
 647
 648         /* Merge */
 649         if (class1 == class2)
 650                 ;
 651         else if (class1 == ARG_CLASS_NO_CLASS)
 652                 class1 = class2;
 653         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 654                 class1 = ARG_CLASS_MEMORY;
 655         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 656                 class1 = ARG_CLASS_INTEGER;
 657         else
 658                 class1 = ARG_CLASS_SSE;
 659
 660         return class1;
 661 }
 662 #ifdef __native_client_codegen__
 663
 664 /* Default alignment for Native Client is 32-byte. */
 665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 666
 667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 668 /* Check that alignment doesn't cross an alignment boundary.             */
 669 guint8*
 670 mono_arch_nacl_pad(guint8 *code, int pad)
 671 {
 672         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 673
 674         if (pad == 0) return code;
 675         /* assertion: alignment cannot cross a block boundary */
 676         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 677                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 678         while (pad >= kMaxPadding) {
 679                 amd64_padding (code, kMaxPadding);
 680                 pad -= kMaxPadding;
 681         }
 682         if (pad != 0) amd64_padding (code, pad);
 683         return code;
 684 }
 685 #endif
 686
 687 static int
 688 count_fields_nested (MonoClass *klass)
 689 {
 690         MonoMarshalType *info;
 691         int i, count;
 692
 693         info = mono_marshal_load_type_info (klass);
 694         g_assert(info);
 695         count = 0;
 696         for (i = 0; i < info->num_fields; ++i) {
 697                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 698                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 699                 else
 700                         count ++;
 701         }
 702         return count;
 703 }
 704
 705 static int
 706 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 707 {
 708         MonoMarshalType *info;
 709         int i;
 710
 711         info = mono_marshal_load_type_info (klass);
 712         g_assert(info);
 713         for (i = 0; i < info->num_fields; ++i) {
 714                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 715                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 716                 } else {
 717                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 718                         fields [index].offset += offset;
 719                         index ++;
 720                 }
 721         }
 722         return index;
 723 }
 724
 725 static void
 726 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 727                            gboolean is_return,
 728                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 729 {
 730         guint32 size, quad, nquads, i, nfields;
 731         /* Keep track of the size used in each quad so we can */
 732         /* use the right size when copying args/return vars.  */
 733         guint32 quadsize [2] = {8, 8};
 734         ArgumentClass args [2];
 735         MonoMarshalType *info = NULL;
 736         MonoMarshalField *fields = NULL;
 737         MonoClass *klass;
 738         MonoGenericSharingContext tmp_gsctx;
 739         gboolean pass_on_stack = FALSE;
 740
 741         /*
 742          * The gsctx currently contains no data, it is only used for checking whenever
 743          * open types are allowed, some callers like mono_arch_get_argument_info ()
 744          * don't pass it to us, so work around that.
 745          */
 746         if (!gsctx)
 747                 gsctx = &tmp_gsctx;
 748
 749         klass = mono_class_from_mono_type (type);
 750         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 751 #ifndef HOST_WIN32
 752         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 753                 /* We pass and return vtypes of size 8 in a register */
 754         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 755                 pass_on_stack = TRUE;
 756         }
 757 #else
 758         if (!sig->pinvoke) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #endif
 762
 763         /* If this struct can't be split up naturally into 8-byte */
 764         /* chunks (registers), pass it on the stack.              */
 765         if (sig->pinvoke && !pass_on_stack) {
 766                 guint32 align;
 767                 guint32 field_size;
 768
 769                 info = mono_marshal_load_type_info (klass);
 770                 g_assert (info);
 771
 772                 /*
 773                  * Collect field information recursively to be able to
 774                  * handle nested structures.
 775                  */
 776                 nfields = count_fields_nested (klass);
 777                 fields = g_new0 (MonoMarshalField, nfields);
 778                 collect_field_info_nested (klass, fields, 0, 0);
 779
 780                 for (i = 0; i < nfields; ++i) {
 781                         field_size = mono_marshal_type_size (fields [i].field->type,
 782                                                            fields [i].mspec,
 783                                                            &align, TRUE, klass->unicode);
 784                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 785                                 pass_on_stack = TRUE;
 786                                 break;
 787                         }
 788                 }
 789         }
 790
 791         if (pass_on_stack) {
 792                 /* Allways pass in memory */
 793                 ainfo->offset = *stack_size;
 794                 *stack_size += ALIGN_TO (size, 8);
 795                 ainfo->storage = ArgOnStack;
 796
 797                 g_free (fields);
 798                 return;
 799         }
 800
 801         /* FIXME: Handle structs smaller than 8 bytes */
 802         //if ((size % 8) != 0)
 803         //      NOT_IMPLEMENTED;
 804
 805         if (size > 8)
 806                 nquads = 2;
 807         else
 808                 nquads = 1;
 809
 810         if (!sig->pinvoke) {
 811                 int n = mono_class_value_size (klass, NULL);
 812
 813                 quadsize [0] = n >= 8 ? 8 : n;
 814                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 815
 816                 /* Always pass in 1 or 2 integer registers */
 817                 args [0] = ARG_CLASS_INTEGER;
 818                 args [1] = ARG_CLASS_INTEGER;
 819                 /* Only the simplest cases are supported */
 820                 if (is_return && nquads != 1) {
 821                         args [0] = ARG_CLASS_MEMORY;
 822                         args [1] = ARG_CLASS_MEMORY;
 823                 }
 824         } else {
 825                 /*
 826                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 827                  * The X87 and SSEUP stuff is left out since there are no such types in
 828                  * the CLR.
 829                  */
 830                 g_assert (info);
 831                 g_assert (fields);
 832
 833 #ifndef HOST_WIN32
 834                 if (info->native_size > 16) {
 835                         ainfo->offset = *stack_size;
 836                         *stack_size += ALIGN_TO (info->native_size, 8);
 837                         ainfo->storage = ArgOnStack;
 838
 839                         g_free (fields);
 840                         return;
 841                 }
 842 #else
 843                 switch (info->native_size) {
 844                 case 1: case 2: case 4: case 8:
 845                         break;
 846                 default:
 847                         if (is_return) {
 848                                 ainfo->storage = ArgOnStack;
 849                                 ainfo->offset = *stack_size;
 850                                 *stack_size += ALIGN_TO (info->native_size, 8);
 851                         }
 852                         else {
 853                                 ainfo->storage = ArgValuetypeAddrInIReg;
 854
 855                                 if (*gr < PARAM_REGS) {
 856                                         ainfo->pair_storage [0] = ArgInIReg;
 857                                         ainfo->pair_regs [0] = param_regs [*gr];
 858                                         (*gr) ++;
 859                                 }
 860                                 else {
 861                                         ainfo->pair_storage [0] = ArgOnStack;
 862                                         ainfo->offset = *stack_size;
 863                                         *stack_size += 8;
 864                                 }
 865                         }
 866
 867                         g_free (fields);
 868                         return;
 869                 }
 870 #endif
 871
 872                 args [0] = ARG_CLASS_NO_CLASS;
 873                 args [1] = ARG_CLASS_NO_CLASS;
 874                 for (quad = 0; quad < nquads; ++quad) {
 875                         int size;
 876                         guint32 align;
 877                         ArgumentClass class1;
 878
 879                         if (nfields == 0)
 880                                 class1 = ARG_CLASS_MEMORY;
 881                         else
 882                                 class1 = ARG_CLASS_NO_CLASS;
 883                         for (i = 0; i < nfields; ++i) {
 884                                 size = mono_marshal_type_size (fields [i].field->type,
 885                                                                                            fields [i].mspec,
 886                                                                                            &align, TRUE, klass->unicode);
 887                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 888                                         /* Unaligned field */
 889                                         NOT_IMPLEMENTED;
 890                                 }
 891
 892                                 /* Skip fields in other quad */
 893                                 if ((quad == 0) && (fields [i].offset >= 8))
 894                                         continue;
 895                                 if ((quad == 1) && (fields [i].offset < 8))
 896                                         continue;
 897
 898                                 /* How far into this quad this data extends.*/
 899                                 /* (8 is size of quad) */
 900                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 901
 902                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 903                         }
 904                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 905                         args [quad] = class1;
 906                 }
 907         }
 908
 909         g_free (fields);
 910
 911         /* Post merger cleanup */
 912         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 913                 args [0] = args [1] = ARG_CLASS_MEMORY;
 914
 915         /* Allocate registers */
 916         {
 917                 int orig_gr = *gr;
 918                 int orig_fr = *fr;
 919
 920                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 921                         quadsize [0] ++;
 922                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 923                         quadsize [1] ++;
 924
 925                 ainfo->storage = ArgValuetypeInReg;
 926                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 927                 g_assert (quadsize [0] <= 8);
 928                 g_assert (quadsize [1] <= 8);
 929                 ainfo->pair_size [0] = quadsize [0];
 930                 ainfo->pair_size [1] = quadsize [1];
 931                 ainfo->nregs = nquads;
 932                 for (quad = 0; quad < nquads; ++quad) {
 933                         switch (args [quad]) {
 934                         case ARG_CLASS_INTEGER:
 935                                 if (*gr >= PARAM_REGS)
 936                                         args [quad] = ARG_CLASS_MEMORY;
 937                                 else {
 938                                         ainfo->pair_storage [quad] = ArgInIReg;
 939                                         if (is_return)
 940                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 941                                         else
 942                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 943                                         (*gr) ++;
 944                                 }
 945                                 break;
 946                         case ARG_CLASS_SSE:
 947                                 if (*fr >= FLOAT_PARAM_REGS)
 948                                         args [quad] = ARG_CLASS_MEMORY;
 949                                 else {
 950                                         if (quadsize[quad] <= 4)
 951                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 952                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 953                                         ainfo->pair_regs [quad] = *fr;
 954                                         (*fr) ++;
 955                                 }
 956                                 break;
 957                         case ARG_CLASS_MEMORY:
 958                                 break;
 959                         default:
 960                                 g_assert_not_reached ();
 961                         }
 962                 }
 963
 964                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 965                         /* Revert possible register assignments */
 966                         *gr = orig_gr;
 967                         *fr = orig_fr;
 968
 969                         ainfo->offset = *stack_size;
 970                         if (sig->pinvoke)
 971                                 *stack_size += ALIGN_TO (info->native_size, 8);
 972                         else
 973                                 *stack_size += nquads * sizeof(mgreg_t);
 974                         ainfo->storage = ArgOnStack;
 975                 }
 976         }
 977 }
 978
 979 /*
 980  * get_call_info:
 981  *
 982  *  Obtain information about a call according to the calling convention.
 983  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 984  * Draft Version 0.23" document for more information.
 985  */
 986 static CallInfo*
 987 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 988 {
 989         guint32 i, gr, fr, pstart;
 990         MonoType *ret_type;
 991         int n = sig->hasthis + sig->param_count;
 992         guint32 stack_size = 0;
 993         CallInfo *cinfo;
 994         gboolean is_pinvoke = sig->pinvoke;
 995
 996         if (mp)
 997                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 998         else
 999                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000
1001         cinfo->nargs = n;
1002
1003         gr = 0;
1004         fr = 0;
1005
1006 #ifdef HOST_WIN32
1007         /* Reserve space where the callee can save the argument registers */
1008         stack_size = 4 * sizeof (mgreg_t);
1009 #endif
1010
1011         /* return value */
1012         ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1013         switch (ret_type->type) {
1014         case MONO_TYPE_I1:
1015         case MONO_TYPE_U1:
1016         case MONO_TYPE_I2:
1017         case MONO_TYPE_U2:
1018         case MONO_TYPE_I4:
1019         case MONO_TYPE_U4:
1020         case MONO_TYPE_I:
1021         case MONO_TYPE_U:
1022         case MONO_TYPE_PTR:
1023         case MONO_TYPE_FNPTR:
1024         case MONO_TYPE_CLASS:
1025         case MONO_TYPE_OBJECT:
1026         case MONO_TYPE_SZARRAY:
1027         case MONO_TYPE_ARRAY:
1028         case MONO_TYPE_STRING:
1029                 cinfo->ret.storage = ArgInIReg;
1030                 cinfo->ret.reg = AMD64_RAX;
1031                 break;
1032         case MONO_TYPE_U8:
1033         case MONO_TYPE_I8:
1034                 cinfo->ret.storage = ArgInIReg;
1035                 cinfo->ret.reg = AMD64_RAX;
1036                 break;
1037         case MONO_TYPE_R4:
1038                 cinfo->ret.storage = ArgInFloatSSEReg;
1039                 cinfo->ret.reg = AMD64_XMM0;
1040                 break;
1041         case MONO_TYPE_R8:
1042                 cinfo->ret.storage = ArgInDoubleSSEReg;
1043                 cinfo->ret.reg = AMD64_XMM0;
1044                 break;
1045         case MONO_TYPE_GENERICINST:
1046                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1047                         cinfo->ret.storage = ArgInIReg;
1048                         cinfo->ret.reg = AMD64_RAX;
1049                         break;
1050                 }
1051                 /* fall through */
1052 #if defined( __native_client_codegen__ )
1053         case MONO_TYPE_TYPEDBYREF:
1054 #endif
1055         case MONO_TYPE_VALUETYPE: {
1056                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1057
1058                 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1059                 if (cinfo->ret.storage == ArgOnStack) {
1060                         cinfo->vtype_retaddr = TRUE;
1061                         /* The caller passes the address where the value is stored */
1062                 }
1063                 break;
1064         }
1065 #if !defined( __native_client_codegen__ )
1066         case MONO_TYPE_TYPEDBYREF:
1067                 /* Same as a valuetype with size 24 */
1068                 cinfo->vtype_retaddr = TRUE;
1069                 break;
1070 #endif
1071         case MONO_TYPE_VOID:
1072                 break;
1073         default:
1074                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1075         }
1076
1077         pstart = 0;
1078         /*
1079          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1080          * the first argument, allowing 'this' to be always passed in the first arg reg.
1081          * Also do this if the first argument is a reference type, since virtual calls
1082          * are sometimes made using calli without sig->hasthis set, like in the delegate
1083          * invoke wrappers.
1084          */
1085         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1086                 if (sig->hasthis) {
1087                         add_general (&gr, &stack_size, cinfo->args + 0);
1088                 } else {
1089                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1090                         pstart = 1;
1091                 }
1092                 add_general (&gr, &stack_size, &cinfo->ret);
1093                 cinfo->vret_arg_index = 1;
1094         } else {
1095                 /* this */
1096                 if (sig->hasthis)
1097                         add_general (&gr, &stack_size, cinfo->args + 0);
1098
1099                 if (cinfo->vtype_retaddr)
1100                         add_general (&gr, &stack_size, &cinfo->ret);
1101         }
1102
1103         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1104                 gr = PARAM_REGS;
1105                 fr = FLOAT_PARAM_REGS;
1106
1107                 /* Emit the signature cookie just before the implicit arguments */
1108                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1109         }
1110
1111         for (i = pstart; i < sig->param_count; ++i) {
1112                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1113                 MonoType *ptype;
1114
1115 #ifdef HOST_WIN32
1116                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1117                 if (gr > fr)
1118                         fr = gr;
1119                 else if (fr > gr)
1120                         gr = fr;
1121 #endif
1122
1123                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1124                         /* We allways pass the sig cookie on the stack for simplicity */
1125                         /*
1126                          * Prevent implicit arguments + the sig cookie from being passed
1127                          * in registers.
1128                          */
1129                         gr = PARAM_REGS;
1130                         fr = FLOAT_PARAM_REGS;
1131
1132                         /* Emit the signature cookie just before the implicit arguments */
1133                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1134                 }
1135
1136                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1137                 switch (ptype->type) {
1138                 case MONO_TYPE_I1:
1139                 case MONO_TYPE_U1:
1140                         add_general (&gr, &stack_size, ainfo);
1141                         break;
1142                 case MONO_TYPE_I2:
1143                 case MONO_TYPE_U2:
1144                         add_general (&gr, &stack_size, ainfo);
1145                         break;
1146                 case MONO_TYPE_I4:
1147                 case MONO_TYPE_U4:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I:
1151                 case MONO_TYPE_U:
1152                 case MONO_TYPE_PTR:
1153                 case MONO_TYPE_FNPTR:
1154                 case MONO_TYPE_CLASS:
1155                 case MONO_TYPE_OBJECT:
1156                 case MONO_TYPE_STRING:
1157                 case MONO_TYPE_SZARRAY:
1158                 case MONO_TYPE_ARRAY:
1159                         add_general (&gr, &stack_size, ainfo);
1160                         break;
1161                 case MONO_TYPE_GENERICINST:
1162                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1163                                 add_general (&gr, &stack_size, ainfo);
1164                                 break;
1165                         }
1166                         /* fall through */
1167                 case MONO_TYPE_VALUETYPE:
1168                 case MONO_TYPE_TYPEDBYREF:
1169                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1170                         break;
1171                 case MONO_TYPE_U8:
1172
1173                 case MONO_TYPE_I8:
1174                         add_general (&gr, &stack_size, ainfo);
1175                         break;
1176                 case MONO_TYPE_R4:
1177                         add_float (&fr, &stack_size, ainfo, FALSE);
1178                         break;
1179                 case MONO_TYPE_R8:
1180                         add_float (&fr, &stack_size, ainfo, TRUE);
1181                         break;
1182                 default:
1183                         g_assert_not_reached ();
1184                 }
1185         }
1186
1187         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1188                 gr = PARAM_REGS;
1189                 fr = FLOAT_PARAM_REGS;
1190
1191                 /* Emit the signature cookie just before the implicit arguments */
1192                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1193         }
1194
1195         cinfo->stack_usage = stack_size;
1196         cinfo->reg_usage = gr;
1197         cinfo->freg_usage = fr;
1198         return cinfo;
1199 }
1200
1201 /*
1202  * mono_arch_get_argument_info:
1203  * @csig:  a method signature
1204  * @param_count: the number of parameters to consider
1205  * @arg_info: an array to store the result infos
1206  *
1207  * Gathers information on parameters such as size, alignment and
1208  * padding. arg_info should be large enought to hold param_count + 1 entries.
1209  *
1210  * Returns the size of the argument area on the stack.
1211  */
1212 int
1213 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1214 {
1215         int k;
1216         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1217         guint32 args_size = cinfo->stack_usage;
1218
1219         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1220         if (csig->hasthis) {
1221                 arg_info [0].offset = 0;
1222         }
1223
1224         for (k = 0; k < param_count; k++) {
1225                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1226                 /* FIXME: */
1227                 arg_info [k + 1].size = 0;
1228         }
1229
1230         g_free (cinfo);
1231
1232         return args_size;
1233 }
1234
1235 gboolean
1236 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1237 {
1238         CallInfo *c1, *c2;
1239         gboolean res;
1240         MonoType *callee_ret;
1241
1242         c1 = get_call_info (NULL, NULL, caller_sig);
1243         c2 = get_call_info (NULL, NULL, callee_sig);
1244         res = c1->stack_usage >= c2->stack_usage;
1245         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1246         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1247                 /* An address on the callee's stack is passed as the first argument */
1248                 res = FALSE;
1249
1250         g_free (c1);
1251         g_free (c2);
1252
1253         return res;
1254 }
1255
1256 /*
1257  * Initialize the cpu to execute managed code.
1258  */
1259 void
1260 mono_arch_cpu_init (void)
1261 {
1262 #ifndef _MSC_VER
1263         guint16 fpcw;
1264
1265         /* spec compliance requires running with double precision */
1266         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1267         fpcw &= ~X86_FPCW_PRECC_MASK;
1268         fpcw |= X86_FPCW_PREC_DOUBLE;
1269         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1270         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271 #else
1272         /* TODO: This is crashing on Win64 right now.
1273         * _control87 (_PC_53, MCW_PC);
1274         */
1275 #endif
1276 }
1277
1278 /*
1279  * Initialize architecture specific code.
1280  */
1281 void
1282 mono_arch_init (void)
1283 {
1284         int flags;
1285
1286         mono_mutex_init_recursive (&mini_arch_mutex);
1287 #if defined(__native_client_codegen__)
1288         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1289         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1290         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1291         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1292 #endif
1293
1294 #ifdef MONO_ARCH_NOMAP32BIT
1295         flags = MONO_MMAP_READ;
1296         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1297         breakpoint_size = 13;
1298         breakpoint_fault_size = 3;
1299 #else
1300         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1301         /* amd64_mov_reg_mem () */
1302         breakpoint_size = 8;
1303         breakpoint_fault_size = 8;
1304 #endif
1305
1306         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1307         single_step_fault_size = 4;
1308
1309         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1310         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1311         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1312
1313         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1314         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1315         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1316 }
1317
1318 /*
1319  * Cleanup architecture specific code.
1320  */
1321 void
1322 mono_arch_cleanup (void)
1323 {
1324         mono_mutex_destroy (&mini_arch_mutex);
1325 #if defined(__native_client_codegen__)
1326         mono_native_tls_free (nacl_instruction_depth);
1327         mono_native_tls_free (nacl_rex_tag);
1328         mono_native_tls_free (nacl_legacy_prefix_tag);
1329 #endif
1330 }
1331
1332 /*
1333  * This function returns the optimizations supported on this cpu.
1334  */
1335 guint32
1336 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1337 {
1338         guint32 opts = 0;
1339
1340         *exclude_mask = 0;
1341
1342         if (mono_hwcap_x86_has_cmov) {
1343                 opts |= MONO_OPT_CMOV;
1344
1345                 if (mono_hwcap_x86_has_fcmov)
1346                         opts |= MONO_OPT_FCMOV;
1347                 else
1348                         *exclude_mask |= MONO_OPT_FCMOV;
1349         } else {
1350                 *exclude_mask |= MONO_OPT_CMOV;
1351         }
1352
1353         return opts;
1354 }
1355
1356 /*
1357  * This function test for all SSE functions supported.
1358  *
1359  * Returns a bitmask corresponding to all supported versions.
1360  *
1361  */
1362 guint32
1363 mono_arch_cpu_enumerate_simd_versions (void)
1364 {
1365         guint32 sse_opts = 0;
1366
1367         if (mono_hwcap_x86_has_sse1)
1368                 sse_opts |= SIMD_VERSION_SSE1;
1369
1370         if (mono_hwcap_x86_has_sse2)
1371                 sse_opts |= SIMD_VERSION_SSE2;
1372
1373         if (mono_hwcap_x86_has_sse3)
1374                 sse_opts |= SIMD_VERSION_SSE3;
1375
1376         if (mono_hwcap_x86_has_ssse3)
1377                 sse_opts |= SIMD_VERSION_SSSE3;
1378
1379         if (mono_hwcap_x86_has_sse41)
1380                 sse_opts |= SIMD_VERSION_SSE41;
1381
1382         if (mono_hwcap_x86_has_sse42)
1383                 sse_opts |= SIMD_VERSION_SSE42;
1384
1385         if (mono_hwcap_x86_has_sse4a)
1386                 sse_opts |= SIMD_VERSION_SSE4a;
1387
1388         return sse_opts;
1389 }
1390
1391 #ifndef DISABLE_JIT
1392
1393 GList *
1394 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1395 {
1396         GList *vars = NULL;
1397         int i;
1398
1399         for (i = 0; i < cfg->num_varinfo; i++) {
1400                 MonoInst *ins = cfg->varinfo [i];
1401                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1402
1403                 /* unused vars */
1404                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1405                         continue;
1406
1407                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1408                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1409                         continue;
1410
1411                 if (mono_is_regsize_var (ins->inst_vtype)) {
1412                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1413                         g_assert (i == vmv->idx);
1414                         vars = g_list_prepend (vars, vmv);
1415                 }
1416         }
1417
1418         vars = mono_varlist_sort (cfg, vars, 0);
1419
1420         return vars;
1421 }
1422
1423 /**
1424  * mono_arch_compute_omit_fp:
1425  *
1426  *   Determine whenever the frame pointer can be eliminated.
1427  */
1428 static void
1429 mono_arch_compute_omit_fp (MonoCompile *cfg)
1430 {
1431         MonoMethodSignature *sig;
1432         MonoMethodHeader *header;
1433         int i, locals_size;
1434         CallInfo *cinfo;
1435
1436         if (cfg->arch.omit_fp_computed)
1437                 return;
1438
1439         header = cfg->header;
1440
1441         sig = mono_method_signature (cfg->method);
1442
1443         if (!cfg->arch.cinfo)
1444                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1445         cinfo = cfg->arch.cinfo;
1446
1447         /*
1448          * FIXME: Remove some of the restrictions.
1449          */
1450         cfg->arch.omit_fp = TRUE;
1451         cfg->arch.omit_fp_computed = TRUE;
1452
1453 #ifdef __native_client_codegen__
1454         /* NaCl modules may not change the value of RBP, so it cannot be */
1455         /* used as a normal register, but it can be used as a frame pointer*/
1456         cfg->disable_omit_fp = TRUE;
1457         cfg->arch.omit_fp = FALSE;
1458 #endif
1459
1460         if (cfg->disable_omit_fp)
1461                 cfg->arch.omit_fp = FALSE;
1462
1463         if (!debug_omit_fp ())
1464                 cfg->arch.omit_fp = FALSE;
1465         /*
1466         if (cfg->method->save_lmf)
1467                 cfg->arch.omit_fp = FALSE;
1468         */
1469         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1470                 cfg->arch.omit_fp = FALSE;
1471         if (header->num_clauses)
1472                 cfg->arch.omit_fp = FALSE;
1473         if (cfg->param_area)
1474                 cfg->arch.omit_fp = FALSE;
1475         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1476                 cfg->arch.omit_fp = FALSE;
1477         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1478                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1479                 cfg->arch.omit_fp = FALSE;
1480         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1481                 ArgInfo *ainfo = &cinfo->args [i];
1482
1483                 if (ainfo->storage == ArgOnStack) {
1484                         /*
1485                          * The stack offset can only be determined when the frame
1486                          * size is known.
1487                          */
1488                         cfg->arch.omit_fp = FALSE;
1489                 }
1490         }
1491
1492         locals_size = 0;
1493         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1494                 MonoInst *ins = cfg->varinfo [i];
1495                 int ialign;
1496
1497                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1498         }
1499 }
1500
1501 GList *
1502 mono_arch_get_global_int_regs (MonoCompile *cfg)
1503 {
1504         GList *regs = NULL;
1505
1506         mono_arch_compute_omit_fp (cfg);
1507
1508         if (cfg->globalra) {
1509                 if (cfg->arch.omit_fp)
1510                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1511
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1516 #ifndef __native_client_codegen__
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1518 #endif
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1526                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1528         } else {
1529                 if (cfg->arch.omit_fp)
1530                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1531
1532                 /* We use the callee saved registers for global allocation */
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1536                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1537 #ifndef __native_client_codegen__
1538                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1539 #endif
1540 #ifdef HOST_WIN32
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1543 #endif
1544         }
1545
1546         return regs;
1547 }
1548
1549 GList*
1550 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1551 {
1552         GList *regs = NULL;
1553         int i;
1554
1555         /* All XMM registers */
1556         for (i = 0; i < 16; ++i)
1557                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1558
1559         return regs;
1560 }
1561
1562 GList*
1563 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1564 {
1565         static GList *r = NULL;
1566
1567         if (r == NULL) {
1568                 GList *regs = NULL;
1569
1570                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1571                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1572                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1573                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1575 #ifndef __native_client_codegen__
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1577 #endif
1578
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1583                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1585                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1586                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1587
1588                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1589         }
1590
1591         return r;
1592 }
1593
1594 GList*
1595 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1596 {
1597         int i;
1598         static GList *r = NULL;
1599
1600         if (r == NULL) {
1601                 GList *regs = NULL;
1602
1603                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1604                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1605
1606                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1607         }
1608
1609         return r;
1610 }
1611
1612 /*
1613  * mono_arch_regalloc_cost:
1614  *
1615  *  Return the cost, in number of memory references, of the action of
1616  * allocating the variable VMV into a register during global register
1617  * allocation.
1618  */
1619 guint32
1620 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1621 {
1622         MonoInst *ins = cfg->varinfo [vmv->idx];
1623
1624         if (cfg->method->save_lmf)
1625                 /* The register is already saved */
1626                 /* substract 1 for the invisible store in the prolog */
1627                 return (ins->opcode == OP_ARG) ? 0 : 1;
1628         else
1629                 /* push+pop */
1630                 return (ins->opcode == OP_ARG) ? 1 : 2;
1631 }
1632
1633 /*
1634  * mono_arch_fill_argument_info:
1635  *
1636  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1637  * of the method.
1638  */
1639 void
1640 mono_arch_fill_argument_info (MonoCompile *cfg)
1641 {
1642         MonoType *sig_ret;
1643         MonoMethodSignature *sig;
1644         MonoInst *ins;
1645         int i;
1646         CallInfo *cinfo;
1647
1648         sig = mono_method_signature (cfg->method);
1649
1650         cinfo = cfg->arch.cinfo;
1651         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1652
1653         /*
1654          * Contrary to mono_arch_allocate_vars (), the information should describe
1655          * where the arguments are at the beginning of the method, not where they can be
1656          * accessed during the execution of the method. The later makes no sense for the
1657          * global register allocator, since a variable can be in more than one location.
1658          */
1659         if (sig_ret->type != MONO_TYPE_VOID) {
1660                 switch (cinfo->ret.storage) {
1661                 case ArgInIReg:
1662                 case ArgInFloatSSEReg:
1663                 case ArgInDoubleSSEReg:
1664                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1665                                 cfg->vret_addr->opcode = OP_REGVAR;
1666                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1667                         }
1668                         else {
1669                                 cfg->ret->opcode = OP_REGVAR;
1670                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1671                         }
1672                         break;
1673                 case ArgValuetypeInReg:
1674                         cfg->ret->opcode = OP_REGOFFSET;
1675                         cfg->ret->inst_basereg = -1;
1676                         cfg->ret->inst_offset = -1;
1677                         break;
1678                 default:
1679                         g_assert_not_reached ();
1680                 }
1681         }
1682
1683         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1684                 ArgInfo *ainfo = &cinfo->args [i];
1685
1686                 ins = cfg->args [i];
1687
1688                 switch (ainfo->storage) {
1689                 case ArgInIReg:
1690                 case ArgInFloatSSEReg:
1691                 case ArgInDoubleSSEReg:
1692                         ins->opcode = OP_REGVAR;
1693                         ins->inst_c0 = ainfo->reg;
1694                         break;
1695                 case ArgOnStack:
1696                         ins->opcode = OP_REGOFFSET;
1697                         ins->inst_basereg = -1;
1698                         ins->inst_offset = -1;
1699                         break;
1700                 case ArgValuetypeInReg:
1701                         /* Dummy */
1702                         ins->opcode = OP_NOP;
1703                         break;
1704                 default:
1705                         g_assert_not_reached ();
1706                 }
1707         }
1708 }
1709
1710 void
1711 mono_arch_allocate_vars (MonoCompile *cfg)
1712 {
1713         MonoType *sig_ret;
1714         MonoMethodSignature *sig;
1715         MonoInst *ins;
1716         int i, offset;
1717         guint32 locals_stack_size, locals_stack_align;
1718         gint32 *offsets;
1719         CallInfo *cinfo;
1720
1721         sig = mono_method_signature (cfg->method);
1722
1723         cinfo = cfg->arch.cinfo;
1724         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1725
1726         mono_arch_compute_omit_fp (cfg);
1727
1728         /*
1729          * We use the ABI calling conventions for managed code as well.
1730          * Exception: valuetypes are only sometimes passed or returned in registers.
1731          */
1732
1733         /*
1734          * The stack looks like this:
1735          * <incoming arguments passed on the stack>
1736          * <return value>
1737          * <lmf/caller saved registers>
1738          * <locals>
1739          * <spill area>
1740          * <localloc area>  -> grows dynamically
1741          * <params area>
1742          */
1743
1744         if (cfg->arch.omit_fp) {
1745                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1746                 cfg->frame_reg = AMD64_RSP;
1747                 offset = 0;
1748         } else {
1749                 /* Locals are allocated backwards from %fp */
1750                 cfg->frame_reg = AMD64_RBP;
1751                 offset = 0;
1752         }
1753
1754         cfg->arch.saved_iregs = cfg->used_int_regs;
1755         if (cfg->method->save_lmf)
1756                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1757                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1758
1759         if (cfg->arch.omit_fp)
1760                 cfg->arch.reg_save_area_offset = offset;
1761         /* Reserve space for callee saved registers */
1762         for (i = 0; i < AMD64_NREG; ++i)
1763                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1764                         offset += sizeof(mgreg_t);
1765                 }
1766         if (!cfg->arch.omit_fp)
1767                 cfg->arch.reg_save_area_offset = -offset;
1768
1769         if (sig_ret->type != MONO_TYPE_VOID) {
1770                 switch (cinfo->ret.storage) {
1771                 case ArgInIReg:
1772                 case ArgInFloatSSEReg:
1773                 case ArgInDoubleSSEReg:
1774                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1775                                 if (cfg->globalra) {
1776                                         cfg->vret_addr->opcode = OP_REGVAR;
1777                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1778                                 } else {
1779                                         /* The register is volatile */
1780                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1781                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1782                                         if (cfg->arch.omit_fp) {
1783                                                 cfg->vret_addr->inst_offset = offset;
1784                                                 offset += 8;
1785                                         } else {
1786                                                 offset += 8;
1787                                                 cfg->vret_addr->inst_offset = -offset;
1788                                         }
1789                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1790                                                 printf ("vret_addr =");
1791                                                 mono_print_ins (cfg->vret_addr);
1792                                         }
1793                                 }
1794                         }
1795                         else {
1796                                 cfg->ret->opcode = OP_REGVAR;
1797                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1798                         }
1799                         break;
1800                 case ArgValuetypeInReg:
1801                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1802                         cfg->ret->opcode = OP_REGOFFSET;
1803                         cfg->ret->inst_basereg = cfg->frame_reg;
1804                         if (cfg->arch.omit_fp) {
1805                                 cfg->ret->inst_offset = offset;
1806                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1807                         } else {
1808                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1809                                 cfg->ret->inst_offset = - offset;
1810                         }
1811                         break;
1812                 default:
1813                         g_assert_not_reached ();
1814                 }
1815                 if (!cfg->globalra)
1816                         cfg->ret->dreg = cfg->ret->inst_c0;
1817         }
1818
1819         /* Allocate locals */
1820         if (!cfg->globalra) {
1821                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1822                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1823                         char *mname = mono_method_full_name (cfg->method, TRUE);
1824                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1825                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1826                         g_free (mname);
1827                         return;
1828                 }
1829
1830                 if (locals_stack_align) {
1831                         offset += (locals_stack_align - 1);
1832                         offset &= ~(locals_stack_align - 1);
1833                 }
1834                 if (cfg->arch.omit_fp) {
1835                         cfg->locals_min_stack_offset = offset;
1836                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1837                 } else {
1838                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1839                         cfg->locals_max_stack_offset = - offset;
1840                 }
1841
1842                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1843                         if (offsets [i] != -1) {
1844                                 MonoInst *ins = cfg->varinfo [i];
1845                                 ins->opcode = OP_REGOFFSET;
1846                                 ins->inst_basereg = cfg->frame_reg;
1847                                 if (cfg->arch.omit_fp)
1848                                         ins->inst_offset = (offset + offsets [i]);
1849                                 else
1850                                         ins->inst_offset = - (offset + offsets [i]);
1851                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1852                         }
1853                 }
1854                 offset += locals_stack_size;
1855         }
1856
1857         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1858                 g_assert (!cfg->arch.omit_fp);
1859                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1860                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1861         }
1862
1863         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1864                 ins = cfg->args [i];
1865                 if (ins->opcode != OP_REGVAR) {
1866                         ArgInfo *ainfo = &cinfo->args [i];
1867                         gboolean inreg = TRUE;
1868
1869                         if (cfg->globalra) {
1870                                 /* The new allocator needs info about the original locations of the arguments */
1871                                 switch (ainfo->storage) {
1872                                 case ArgInIReg:
1873                                 case ArgInFloatSSEReg:
1874                                 case ArgInDoubleSSEReg:
1875                                         ins->opcode = OP_REGVAR;
1876                                         ins->inst_c0 = ainfo->reg;
1877                                         break;
1878                                 case ArgOnStack:
1879                                         g_assert (!cfg->arch.omit_fp);
1880                                         ins->opcode = OP_REGOFFSET;
1881                                         ins->inst_basereg = cfg->frame_reg;
1882                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1883                                         break;
1884                                 case ArgValuetypeInReg:
1885                                         ins->opcode = OP_REGOFFSET;
1886                                         ins->inst_basereg = cfg->frame_reg;
1887                                         /* These arguments are saved to the stack in the prolog */
1888                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1889                                         if (cfg->arch.omit_fp) {
1890                                                 ins->inst_offset = offset;
1891                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1892                                         } else {
1893                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1894                                                 ins->inst_offset = - offset;
1895                                         }
1896                                         break;
1897                                 default:
1898                                         g_assert_not_reached ();
1899                                 }
1900
1901                                 continue;
1902                         }
1903
1904                         /* FIXME: Allocate volatile arguments to registers */
1905                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1906                                 inreg = FALSE;
1907
1908                         /*
1909                          * Under AMD64, all registers used to pass arguments to functions
1910                          * are volatile across calls.
1911                          * FIXME: Optimize this.
1912                          */
1913                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1914                                 inreg = FALSE;
1915
1916                         ins->opcode = OP_REGOFFSET;
1917
1918                         switch (ainfo->storage) {
1919                         case ArgInIReg:
1920                         case ArgInFloatSSEReg:
1921                         case ArgInDoubleSSEReg:
1922                                 if (inreg) {
1923                                         ins->opcode = OP_REGVAR;
1924                                         ins->dreg = ainfo->reg;
1925                                 }
1926                                 break;
1927                         case ArgOnStack:
1928                                 g_assert (!cfg->arch.omit_fp);
1929                                 ins->opcode = OP_REGOFFSET;
1930                                 ins->inst_basereg = cfg->frame_reg;
1931                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1932                                 break;
1933                         case ArgValuetypeInReg:
1934                                 break;
1935                         case ArgValuetypeAddrInIReg: {
1936                                 MonoInst *indir;
1937                                 g_assert (!cfg->arch.omit_fp);
1938
1939                                 MONO_INST_NEW (cfg, indir, 0);
1940                                 indir->opcode = OP_REGOFFSET;
1941                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1942                                         indir->inst_basereg = cfg->frame_reg;
1943                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1944                                         offset += (sizeof (gpointer));
1945                                         indir->inst_offset = - offset;
1946                                 }
1947                                 else {
1948                                         indir->inst_basereg = cfg->frame_reg;
1949                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1950                                 }
1951
1952                                 ins->opcode = OP_VTARG_ADDR;
1953                                 ins->inst_left = indir;
1954
1955                                 break;
1956                         }
1957                         default:
1958                                 NOT_IMPLEMENTED;
1959                         }
1960
1961                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1962                                 ins->opcode = OP_REGOFFSET;
1963                                 ins->inst_basereg = cfg->frame_reg;
1964                                 /* These arguments are saved to the stack in the prolog */
1965                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1966                                 if (cfg->arch.omit_fp) {
1967                                         ins->inst_offset = offset;
1968                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1969                                         // Arguments are yet supported by the stack map creation code
1970                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1971                                 } else {
1972                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1973                                         ins->inst_offset = - offset;
1974                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1975                                 }
1976                         }
1977                 }
1978         }
1979
1980         cfg->stack_offset = offset;
1981 }
1982
1983 void
1984 mono_arch_create_vars (MonoCompile *cfg)
1985 {
1986         MonoMethodSignature *sig;
1987         CallInfo *cinfo;
1988         MonoType *sig_ret;
1989
1990         sig = mono_method_signature (cfg->method);
1991
1992         if (!cfg->arch.cinfo)
1993                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1994         cinfo = cfg->arch.cinfo;
1995
1996         if (cinfo->ret.storage == ArgValuetypeInReg)
1997                 cfg->ret_var_is_local = TRUE;
1998
1999         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2000         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2001                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2002                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2003                         printf ("vret_addr = ");
2004                         mono_print_ins (cfg->vret_addr);
2005                 }
2006         }
2007
2008         if (cfg->gen_seq_points_debug_data) {
2009                 MonoInst *ins;
2010
2011                 if (cfg->compile_aot) {
2012                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2013                         ins->flags |= MONO_INST_VOLATILE;
2014                         cfg->arch.seq_point_info_var = ins;
2015                 }
2016
2017             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2018                 ins->flags |= MONO_INST_VOLATILE;
2019                 cfg->arch.ss_trigger_page_var = ins;
2020         }
2021
2022         if (cfg->method->save_lmf)
2023                 cfg->create_lmf_var = TRUE;
2024
2025         if (cfg->method->save_lmf) {
2026                 cfg->lmf_ir = TRUE;
2027 #if !defined(HOST_WIN32)
2028                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2029                         cfg->lmf_ir_mono_lmf = TRUE;
2030 #endif
2031         }
2032 }
2033
2034 static void
2035 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2036 {
2037         MonoInst *ins;
2038
2039         switch (storage) {
2040         case ArgInIReg:
2041                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2042                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2043                 ins->sreg1 = tree->dreg;
2044                 MONO_ADD_INS (cfg->cbb, ins);
2045                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2046                 break;
2047         case ArgInFloatSSEReg:
2048                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2049                 ins->dreg = mono_alloc_freg (cfg);
2050                 ins->sreg1 = tree->dreg;
2051                 MONO_ADD_INS (cfg->cbb, ins);
2052
2053                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2054                 break;
2055         case ArgInDoubleSSEReg:
2056                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2057                 ins->dreg = mono_alloc_freg (cfg);
2058                 ins->sreg1 = tree->dreg;
2059                 MONO_ADD_INS (cfg->cbb, ins);
2060
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062
2063                 break;
2064         default:
2065                 g_assert_not_reached ();
2066         }
2067 }
2068
2069 static int
2070 arg_storage_to_load_membase (ArgStorage storage)
2071 {
2072         switch (storage) {
2073         case ArgInIReg:
2074 #if defined(__mono_ilp32__)
2075                 return OP_LOADI8_MEMBASE;
2076 #else
2077                 return OP_LOAD_MEMBASE;
2078 #endif
2079         case ArgInDoubleSSEReg:
2080                 return OP_LOADR8_MEMBASE;
2081         case ArgInFloatSSEReg:
2082                 return OP_LOADR4_MEMBASE;
2083         default:
2084                 g_assert_not_reached ();
2085         }
2086
2087         return -1;
2088 }
2089
2090 static void
2091 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2092 {
2093         MonoMethodSignature *tmp_sig;
2094         int sig_reg;
2095
2096         if (call->tail_call)
2097                 NOT_IMPLEMENTED;
2098
2099         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2100
2101         /*
2102          * mono_ArgIterator_Setup assumes the signature cookie is
2103          * passed first and all the arguments which were before it are
2104          * passed on the stack after the signature. So compensate by
2105          * passing a different signature.
2106          */
2107         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2108         tmp_sig->param_count -= call->signature->sentinelpos;
2109         tmp_sig->sentinelpos = 0;
2110         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2111
2112         sig_reg = mono_alloc_ireg (cfg);
2113         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2114
2115         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2116 }
2117
2118 #ifdef ENABLE_LLVM
2119 static inline LLVMArgStorage
2120 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2121 {
2122         switch (storage) {
2123         case ArgInIReg:
2124                 return LLVMArgInIReg;
2125         case ArgNone:
2126                 return LLVMArgNone;
2127         default:
2128                 g_assert_not_reached ();
2129                 return LLVMArgNone;
2130         }
2131 }
2132
2133 LLVMCallInfo*
2134 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2135 {
2136         int i, n;
2137         CallInfo *cinfo;
2138         ArgInfo *ainfo;
2139         int j;
2140         LLVMCallInfo *linfo;
2141         MonoType *t, *sig_ret;
2142
2143         n = sig->param_count + sig->hasthis;
2144         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2145
2146         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2147
2148         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2149
2150         /*
2151          * LLVM always uses the native ABI while we use our own ABI, the
2152          * only difference is the handling of vtypes:
2153          * - we only pass/receive them in registers in some cases, and only
2154          *   in 1 or 2 integer registers.
2155          */
2156         if (cinfo->ret.storage == ArgValuetypeInReg) {
2157                 if (sig->pinvoke) {
2158                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2159                         cfg->disable_llvm = TRUE;
2160                         return linfo;
2161                 }
2162
2163                 linfo->ret.storage = LLVMArgVtypeInReg;
2164                 for (j = 0; j < 2; ++j)
2165                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2166         }
2167
2168         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2169                 /* Vtype returned using a hidden argument */
2170                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2171                 linfo->vret_arg_index = cinfo->vret_arg_index;
2172         }
2173
2174         for (i = 0; i < n; ++i) {
2175                 ainfo = cinfo->args + i;
2176
2177                 if (i >= sig->hasthis)
2178                         t = sig->params [i - sig->hasthis];
2179                 else
2180                         t = &mono_defaults.int_class->byval_arg;
2181
2182                 linfo->args [i].storage = LLVMArgNone;
2183
2184                 switch (ainfo->storage) {
2185                 case ArgInIReg:
2186                         linfo->args [i].storage = LLVMArgInIReg;
2187                         break;
2188                 case ArgInDoubleSSEReg:
2189                 case ArgInFloatSSEReg:
2190                         linfo->args [i].storage = LLVMArgInFPReg;
2191                         break;
2192                 case ArgOnStack:
2193                         if (MONO_TYPE_ISSTRUCT (t)) {
2194                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2195                         } else {
2196                                 linfo->args [i].storage = LLVMArgInIReg;
2197                                 if (!t->byref) {
2198                                         if (t->type == MONO_TYPE_R4)
2199                                                 linfo->args [i].storage = LLVMArgInFPReg;
2200                                         else if (t->type == MONO_TYPE_R8)
2201                                                 linfo->args [i].storage = LLVMArgInFPReg;
2202                                 }
2203                         }
2204                         break;
2205                 case ArgValuetypeInReg:
2206                         if (sig->pinvoke) {
2207                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2208                                 cfg->disable_llvm = TRUE;
2209                                 return linfo;
2210                         }
2211
2212                         linfo->args [i].storage = LLVMArgVtypeInReg;
2213                         for (j = 0; j < 2; ++j)
2214                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2215                         break;
2216                 default:
2217                         cfg->exception_message = g_strdup ("ainfo->storage");
2218                         cfg->disable_llvm = TRUE;
2219                         break;
2220                 }
2221         }
2222
2223         return linfo;
2224 }
2225 #endif
2226
2227 void
2228 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2229 {
2230         MonoInst *arg, *in;
2231         MonoMethodSignature *sig;
2232         MonoType *sig_ret;
2233         int i, n;
2234         CallInfo *cinfo;
2235         ArgInfo *ainfo;
2236
2237         sig = call->signature;
2238         n = sig->param_count + sig->hasthis;
2239
2240         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2241
2242         sig_ret = sig->ret;
2243
2244         if (COMPILE_LLVM (cfg)) {
2245                 /* We shouldn't be called in the llvm case */
2246                 cfg->disable_llvm = TRUE;
2247                 return;
2248         }
2249
2250         /*
2251          * Emit all arguments which are passed on the stack to prevent register
2252          * allocation problems.
2253          */
2254         for (i = 0; i < n; ++i) {
2255                 MonoType *t;
2256                 ainfo = cinfo->args + i;
2257
2258                 in = call->args [i];
2259
2260                 if (sig->hasthis && i == 0)
2261                         t = &mono_defaults.object_class->byval_arg;
2262                 else
2263                         t = sig->params [i - sig->hasthis];
2264
2265                 t = mini_get_underlying_type (cfg, t);
2266                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2267                         if (!t->byref) {
2268                                 if (t->type == MONO_TYPE_R4)
2269                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2270                                 else if (t->type == MONO_TYPE_R8)
2271                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2272                                 else
2273                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2274                         } else {
2275                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2276                         }
2277                         if (cfg->compute_gc_maps) {
2278                                 MonoInst *def;
2279
2280                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2281                         }
2282                 }
2283         }
2284
2285         /*
2286          * Emit all parameters passed in registers in non-reverse order for better readability
2287          * and to help the optimization in emit_prolog ().
2288          */
2289         for (i = 0; i < n; ++i) {
2290                 ainfo = cinfo->args + i;
2291
2292                 in = call->args [i];
2293
2294                 if (ainfo->storage == ArgInIReg)
2295                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2296         }
2297
2298         for (i = n - 1; i >= 0; --i) {
2299                 ainfo = cinfo->args + i;
2300
2301                 in = call->args [i];
2302
2303                 switch (ainfo->storage) {
2304                 case ArgInIReg:
2305                         /* Already done */
2306                         break;
2307                 case ArgInFloatSSEReg:
2308                 case ArgInDoubleSSEReg:
2309                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2310                         break;
2311                 case ArgOnStack:
2312                 case ArgValuetypeInReg:
2313                 case ArgValuetypeAddrInIReg:
2314                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2315                                 MonoInst *call_inst = (MonoInst*)call;
2316                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2317                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2318                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2319                                 guint32 align;
2320                                 guint32 size;
2321
2322                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2323                                         size = sizeof (MonoTypedRef);
2324                                         align = sizeof (gpointer);
2325                                 }
2326                                 else {
2327                                         if (sig->pinvoke)
2328                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2329                                         else {
2330                                                 /*
2331                                                  * Other backends use mono_type_stack_size (), but that
2332                                                  * aligns the size to 8, which is larger than the size of
2333                                                  * the source, leading to reads of invalid memory if the
2334                                                  * source is at the end of address space.
2335                                                  */
2336                                                 size = mono_class_value_size (in->klass, &align);
2337                                         }
2338                                 }
2339                                 g_assert (in->klass);
2340
2341                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2342                                         /* Avoid asserts in emit_memcpy () */
2343                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2344                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2345                                         /* Continue normally */
2346                                 }
2347
2348                                 if (size > 0) {
2349                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2350                                         arg->sreg1 = in->dreg;
2351                                         arg->klass = in->klass;
2352                                         arg->backend.size = size;
2353                                         arg->inst_p0 = call;
2354                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2355                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2356
2357                                         MONO_ADD_INS (cfg->cbb, arg);
2358                                 }
2359                         }
2360                         break;
2361                 default:
2362                         g_assert_not_reached ();
2363                 }
2364
2365                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2366                         /* Emit the signature cookie just before the implicit arguments */
2367                         emit_sig_cookie (cfg, call, cinfo);
2368         }
2369
2370         /* Handle the case where there are no implicit arguments */
2371         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2372                 emit_sig_cookie (cfg, call, cinfo);
2373
2374         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2375         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2376                 MonoInst *vtarg;
2377
2378                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2379                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2380                                 /*
2381                                  * Tell the JIT to use a more efficient calling convention: call using
2382                                  * OP_CALL, compute the result location after the call, and save the
2383                                  * result there.
2384                                  */
2385                                 call->vret_in_reg = TRUE;
2386                                 /*
2387                                  * Nullify the instruction computing the vret addr to enable
2388                                  * future optimizations.
2389                                  */
2390                                 if (call->vret_var)
2391                                         NULLIFY_INS (call->vret_var);
2392                         } else {
2393                                 if (call->tail_call)
2394                                         NOT_IMPLEMENTED;
2395                                 /*
2396                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2397                                  * the stack. Push the address here, so the call instruction can
2398                                  * access it.
2399                                  */
2400                                 if (!cfg->arch.vret_addr_loc) {
2401                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2402                                         /* Prevent it from being register allocated or optimized away */
2403                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2404                                 }
2405
2406                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2407                         }
2408                 }
2409                 else {
2410                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2411                         vtarg->sreg1 = call->vret_var->dreg;
2412                         vtarg->dreg = mono_alloc_preg (cfg);
2413                         MONO_ADD_INS (cfg->cbb, vtarg);
2414
2415                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2416                 }
2417         }
2418
2419         if (cfg->method->save_lmf) {
2420                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2421                 MONO_ADD_INS (cfg->cbb, arg);
2422         }
2423
2424         call->stack_usage = cinfo->stack_usage;
2425 }
2426
2427 void
2428 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2429 {
2430         MonoInst *arg;
2431         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2432         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2433         int size = ins->backend.size;
2434
2435         if (ainfo->storage == ArgValuetypeInReg) {
2436                 MonoInst *load;
2437                 int part;
2438
2439                 for (part = 0; part < 2; ++part) {
2440                         if (ainfo->pair_storage [part] == ArgNone)
2441                                 continue;
2442
2443                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2444                         load->inst_basereg = src->dreg;
2445                         load->inst_offset = part * sizeof(mgreg_t);
2446
2447                         switch (ainfo->pair_storage [part]) {
2448                         case ArgInIReg:
2449                                 load->dreg = mono_alloc_ireg (cfg);
2450                                 break;
2451                         case ArgInDoubleSSEReg:
2452                         case ArgInFloatSSEReg:
2453                                 load->dreg = mono_alloc_freg (cfg);
2454                                 break;
2455                         default:
2456                                 g_assert_not_reached ();
2457                         }
2458                         MONO_ADD_INS (cfg->cbb, load);
2459
2460                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2461                 }
2462         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2463                 MonoInst *vtaddr, *load;
2464                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2465
2466                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2467                 cfg->has_indirection = TRUE;
2468                 load->inst_p0 = vtaddr;
2469                 vtaddr->flags |= MONO_INST_INDIRECT;
2470                 load->type = STACK_MP;
2471                 load->klass = vtaddr->klass;
2472                 load->dreg = mono_alloc_ireg (cfg);
2473                 MONO_ADD_INS (cfg->cbb, load);
2474                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2475
2476                 if (ainfo->pair_storage [0] == ArgInIReg) {
2477                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2478                         arg->dreg = mono_alloc_ireg (cfg);
2479                         arg->sreg1 = load->dreg;
2480                         arg->inst_imm = 0;
2481                         MONO_ADD_INS (cfg->cbb, arg);
2482                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2483                 } else {
2484                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2485                 }
2486         } else {
2487                 if (size == 8) {
2488                         int dreg = mono_alloc_ireg (cfg);
2489
2490                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2491                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2492                 } else if (size <= 40) {
2493                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2494                 } else {
2495                         // FIXME: Code growth
2496                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2497                 }
2498
2499                 if (cfg->compute_gc_maps) {
2500                         MonoInst *def;
2501                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2502                 }
2503         }
2504 }
2505
2506 void
2507 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2508 {
2509         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2510
2511         if (ret->type == MONO_TYPE_R4) {
2512                 if (COMPILE_LLVM (cfg))
2513                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2514                 else
2515                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2516                 return;
2517         } else if (ret->type == MONO_TYPE_R8) {
2518                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2519                 return;
2520         }
2521
2522         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2523 }
2524
2525 #endif /* DISABLE_JIT */
2526
2527 #define EMIT_COND_BRANCH(ins,cond,sign) \
2528         if (ins->inst_true_bb->native_offset) { \
2529                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2530         } else { \
2531                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2532                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2533             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2534                         x86_branch8 (code, cond, 0, sign); \
2535                 else \
2536                         x86_branch32 (code, cond, 0, sign); \
2537 }
2538
2539 typedef struct {
2540         MonoMethodSignature *sig;
2541         CallInfo *cinfo;
2542 } ArchDynCallInfo;
2543
2544 static gboolean
2545 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2546 {
2547         int i;
2548
2549 #ifdef HOST_WIN32
2550         return FALSE;
2551 #endif
2552
2553         switch (cinfo->ret.storage) {
2554         case ArgNone:
2555         case ArgInIReg:
2556                 break;
2557         case ArgValuetypeInReg: {
2558                 ArgInfo *ainfo = &cinfo->ret;
2559
2560                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2561                         return FALSE;
2562                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2563                         return FALSE;
2564                 break;
2565         }
2566         default:
2567                 return FALSE;
2568         }
2569
2570         for (i = 0; i < cinfo->nargs; ++i) {
2571                 ArgInfo *ainfo = &cinfo->args [i];
2572                 switch (ainfo->storage) {
2573                 case ArgInIReg:
2574                         break;
2575                 case ArgValuetypeInReg:
2576                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2577                                 return FALSE;
2578                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2579                                 return FALSE;
2580                         break;
2581                 default:
2582                         return FALSE;
2583                 }
2584         }
2585
2586         return TRUE;
2587 }
2588
2589 /*
2590  * mono_arch_dyn_call_prepare:
2591  *
2592  *   Return a pointer to an arch-specific structure which contains information
2593  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2594  * supported for SIG.
2595  * This function is equivalent to ffi_prep_cif in libffi.
2596  */
2597 MonoDynCallInfo*
2598 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2599 {
2600         ArchDynCallInfo *info;
2601         CallInfo *cinfo;
2602
2603         cinfo = get_call_info (NULL, NULL, sig);
2604
2605         if (!dyn_call_supported (sig, cinfo)) {
2606                 g_free (cinfo);
2607                 return NULL;
2608         }
2609
2610         info = g_new0 (ArchDynCallInfo, 1);
2611         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2612         info->sig = sig;
2613         info->cinfo = cinfo;
2614
2615         return (MonoDynCallInfo*)info;
2616 }
2617
2618 /*
2619  * mono_arch_dyn_call_free:
2620  *
2621  *   Free a MonoDynCallInfo structure.
2622  */
2623 void
2624 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2625 {
2626         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2627
2628         g_free (ainfo->cinfo);
2629         g_free (ainfo);
2630 }
2631
2632 #if !defined(__native_client__)
2633 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2634 #define GREG_TO_PTR(greg) (gpointer)(greg)
2635 #else
2636 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2637 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2638 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2639 #endif
2640
2641 /*
2642  * mono_arch_get_start_dyn_call:
2643  *
2644  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2645  * store the result into BUF.
2646  * ARGS should be an array of pointers pointing to the arguments.
2647  * RET should point to a memory buffer large enought to hold the result of the
2648  * call.
2649  * This function should be as fast as possible, any work which does not depend
2650  * on the actual values of the arguments should be done in
2651  * mono_arch_dyn_call_prepare ().
2652  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2653  * libffi.
2654  */
2655 void
2656 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2657 {
2658         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2659         DynCallArgs *p = (DynCallArgs*)buf;
2660         int arg_index, greg, i, pindex;
2661         MonoMethodSignature *sig = dinfo->sig;
2662
2663         g_assert (buf_len >= sizeof (DynCallArgs));
2664
2665         p->res = 0;
2666         p->ret = ret;
2667
2668         arg_index = 0;
2669         greg = 0;
2670         pindex = 0;
2671
2672         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2673                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2674                 if (!sig->hasthis)
2675                         pindex = 1;
2676         }
2677
2678         if (dinfo->cinfo->vtype_retaddr)
2679                 p->regs [greg ++] = PTR_TO_GREG(ret);
2680
2681         for (i = pindex; i < sig->param_count; i++) {
2682                 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2683                 gpointer *arg = args [arg_index ++];
2684
2685                 if (t->byref) {
2686                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2687                         continue;
2688                 }
2689
2690                 switch (t->type) {
2691                 case MONO_TYPE_STRING:
2692                 case MONO_TYPE_CLASS:
2693                 case MONO_TYPE_ARRAY:
2694                 case MONO_TYPE_SZARRAY:
2695                 case MONO_TYPE_OBJECT:
2696                 case MONO_TYPE_PTR:
2697                 case MONO_TYPE_I:
2698                 case MONO_TYPE_U:
2699 #if !defined(__mono_ilp32__)
2700                 case MONO_TYPE_I8:
2701                 case MONO_TYPE_U8:
2702 #endif
2703                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2704                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2705                         break;
2706 #if defined(__mono_ilp32__)
2707                 case MONO_TYPE_I8:
2708                 case MONO_TYPE_U8:
2709                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2710                         p->regs [greg ++] = *(guint64*)(arg);
2711                         break;
2712 #endif
2713                 case MONO_TYPE_U1:
2714                         p->regs [greg ++] = *(guint8*)(arg);
2715                         break;
2716                 case MONO_TYPE_I1:
2717                         p->regs [greg ++] = *(gint8*)(arg);
2718                         break;
2719                 case MONO_TYPE_I2:
2720                         p->regs [greg ++] = *(gint16*)(arg);
2721                         break;
2722                 case MONO_TYPE_U2:
2723                         p->regs [greg ++] = *(guint16*)(arg);
2724                         break;
2725                 case MONO_TYPE_I4:
2726                         p->regs [greg ++] = *(gint32*)(arg);
2727                         break;
2728                 case MONO_TYPE_U4:
2729                         p->regs [greg ++] = *(guint32*)(arg);
2730                         break;
2731                 case MONO_TYPE_GENERICINST:
2732                     if (MONO_TYPE_IS_REFERENCE (t)) {
2733                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2734                                 break;
2735                         } else {
2736                                 /* Fall through */
2737                         }
2738                 case MONO_TYPE_VALUETYPE: {
2739                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2740
2741                         g_assert (ainfo->storage == ArgValuetypeInReg);
2742                         if (ainfo->pair_storage [0] != ArgNone) {
2743                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2744                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2745                         }
2746                         if (ainfo->pair_storage [1] != ArgNone) {
2747                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2748                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2749                         }
2750                         break;
2751                 }
2752                 default:
2753                         g_assert_not_reached ();
2754                 }
2755         }
2756
2757         g_assert (greg <= PARAM_REGS);
2758 }
2759
2760 /*
2761  * mono_arch_finish_dyn_call:
2762  *
2763  *   Store the result of a dyn call into the return value buffer passed to
2764  * start_dyn_call ().
2765  * This function should be as fast as possible, any work which does not depend
2766  * on the actual values of the arguments should be done in
2767  * mono_arch_dyn_call_prepare ().
2768  */
2769 void
2770 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2771 {
2772         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2773         MonoMethodSignature *sig = dinfo->sig;
2774         guint8 *ret = ((DynCallArgs*)buf)->ret;
2775         mgreg_t res = ((DynCallArgs*)buf)->res;
2776         MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2777
2778         switch (sig_ret->type) {
2779         case MONO_TYPE_VOID:
2780                 *(gpointer*)ret = NULL;
2781                 break;
2782         case MONO_TYPE_STRING:
2783         case MONO_TYPE_CLASS:
2784         case MONO_TYPE_ARRAY:
2785         case MONO_TYPE_SZARRAY:
2786         case MONO_TYPE_OBJECT:
2787         case MONO_TYPE_I:
2788         case MONO_TYPE_U:
2789         case MONO_TYPE_PTR:
2790                 *(gpointer*)ret = GREG_TO_PTR(res);
2791                 break;
2792         case MONO_TYPE_I1:
2793                 *(gint8*)ret = res;
2794                 break;
2795         case MONO_TYPE_U1:
2796                 *(guint8*)ret = res;
2797                 break;
2798         case MONO_TYPE_I2:
2799                 *(gint16*)ret = res;
2800                 break;
2801         case MONO_TYPE_U2:
2802                 *(guint16*)ret = res;
2803                 break;
2804         case MONO_TYPE_I4:
2805                 *(gint32*)ret = res;
2806                 break;
2807         case MONO_TYPE_U4:
2808                 *(guint32*)ret = res;
2809                 break;
2810         case MONO_TYPE_I8:
2811                 *(gint64*)ret = res;
2812                 break;
2813         case MONO_TYPE_U8:
2814                 *(guint64*)ret = res;
2815                 break;
2816         case MONO_TYPE_GENERICINST:
2817                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2818                         *(gpointer*)ret = GREG_TO_PTR(res);
2819                         break;
2820                 } else {
2821                         /* Fall through */
2822                 }
2823         case MONO_TYPE_VALUETYPE:
2824                 if (dinfo->cinfo->vtype_retaddr) {
2825                         /* Nothing to do */
2826                 } else {
2827                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2828
2829                         g_assert (ainfo->storage == ArgValuetypeInReg);
2830
2831                         if (ainfo->pair_storage [0] != ArgNone) {
2832                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2833                                 ((mgreg_t*)ret)[0] = res;
2834                         }
2835
2836                         g_assert (ainfo->pair_storage [1] == ArgNone);
2837                 }
2838                 break;
2839         default:
2840                 g_assert_not_reached ();
2841         }
2842 }
2843
2844 /* emit an exception if condition is fail */
2845 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2846         do {                                                        \
2847                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2848                 if (tins == NULL) {                                                                             \
2849                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2850                                         MONO_PATCH_INFO_EXC, exc_name);  \
2851                         x86_branch32 (code, cond, 0, signed);               \
2852                 } else {        \
2853                         EMIT_COND_BRANCH (tins, cond, signed);  \
2854                 }                       \
2855         } while (0);
2856
2857 #define EMIT_FPCOMPARE(code) do { \
2858         amd64_fcompp (code); \
2859         amd64_fnstsw (code); \
2860 } while (0);
2861
2862 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2863     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2864         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2865         amd64_ ##op (code); \
2866         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2867         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2868 } while (0);
2869
2870 static guint8*
2871 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2872 {
2873         gboolean no_patch = FALSE;
2874
2875         /*
2876          * FIXME: Add support for thunks
2877          */
2878         {
2879                 gboolean near_call = FALSE;
2880
2881                 /*
2882                  * Indirect calls are expensive so try to make a near call if possible.
2883                  * The caller memory is allocated by the code manager so it is
2884                  * guaranteed to be at a 32 bit offset.
2885                  */
2886
2887                 if (patch_type != MONO_PATCH_INFO_ABS) {
2888                         /* The target is in memory allocated using the code manager */
2889                         near_call = TRUE;
2890
2891                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2892                                 if (((MonoMethod*)data)->klass->image->aot_module)
2893                                         /* The callee might be an AOT method */
2894                                         near_call = FALSE;
2895                                 if (((MonoMethod*)data)->dynamic)
2896                                         /* The target is in malloc-ed memory */
2897                                         near_call = FALSE;
2898                         }
2899
2900                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2901                                 /*
2902                                  * The call might go directly to a native function without
2903                                  * the wrapper.
2904                                  */
2905                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2906                                 if (mi) {
2907                                         gconstpointer target = mono_icall_get_wrapper (mi);
2908                                         if ((((guint64)target) >> 32) != 0)
2909                                                 near_call = FALSE;
2910                                 }
2911                         }
2912                 }
2913                 else {
2914                         MonoJumpInfo *jinfo = NULL;
2915
2916                         if (cfg->abs_patches)
2917                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2918                         if (jinfo) {
2919                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2920                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2921                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2922                                                 near_call = TRUE;
2923                                         no_patch = TRUE;
2924                                 } else {
2925                                         /*
2926                                          * This is not really an optimization, but required because the
2927                                          * generic class init trampolines use R11 to pass the vtable.
2928                                          */
2929                                         near_call = TRUE;
2930                                 }
2931                         } else {
2932                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2933                                 if (info) {
2934                                         if (info->func == info->wrapper) {
2935                                                 /* No wrapper */
2936                                                 if ((((guint64)info->func) >> 32) == 0)
2937                                                         near_call = TRUE;
2938                                         }
2939                                         else {
2940                                                 /* See the comment in mono_codegen () */
2941                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2942                                                         near_call = TRUE;
2943                                         }
2944                                 }
2945                                 else if ((((guint64)data) >> 32) == 0) {
2946                                         near_call = TRUE;
2947                                         no_patch = TRUE;
2948                                 }
2949                         }
2950                 }
2951
2952                 if (cfg->method->dynamic)
2953                         /* These methods are allocated using malloc */
2954                         near_call = FALSE;
2955
2956 #ifdef MONO_ARCH_NOMAP32BIT
2957                 near_call = FALSE;
2958 #endif
2959 #if defined(__native_client__)
2960                 /* Always use near_call == TRUE for Native Client */
2961                 near_call = TRUE;
2962 #endif
2963                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2964                 if (optimize_for_xen)
2965                         near_call = FALSE;
2966
2967                 if (cfg->compile_aot) {
2968                         near_call = TRUE;
2969                         no_patch = TRUE;
2970                 }
2971
2972                 if (near_call) {
2973                         /*
2974                          * Align the call displacement to an address divisible by 4 so it does
2975                          * not span cache lines. This is required for code patching to work on SMP
2976                          * systems.
2977                          */
2978                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2979                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2980                                 amd64_padding (code, pad_size);
2981                         }
2982                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2983                         amd64_call_code (code, 0);
2984                 }
2985                 else {
2986                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2987                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2988                         amd64_call_reg (code, GP_SCRATCH_REG);
2989                 }
2990         }
2991
2992         return code;
2993 }
2994
2995 static inline guint8*
2996 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2997 {
2998 #ifdef HOST_WIN32
2999         if (win64_adjust_stack)
3000                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3001 #endif
3002         code = emit_call_body (cfg, code, patch_type, data);
3003 #ifdef HOST_WIN32
3004         if (win64_adjust_stack)
3005                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3006 #endif
3007
3008         return code;
3009 }
3010
3011 static inline int
3012 store_membase_imm_to_store_membase_reg (int opcode)
3013 {
3014         switch (opcode) {
3015         case OP_STORE_MEMBASE_IMM:
3016                 return OP_STORE_MEMBASE_REG;
3017         case OP_STOREI4_MEMBASE_IMM:
3018                 return OP_STOREI4_MEMBASE_REG;
3019         case OP_STOREI8_MEMBASE_IMM:
3020                 return OP_STOREI8_MEMBASE_REG;
3021         }
3022
3023         return -1;
3024 }
3025
3026 #ifndef DISABLE_JIT
3027
3028 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3029
3030 /*
3031  * mono_arch_peephole_pass_1:
3032  *
3033  *   Perform peephole opts which should/can be performed before local regalloc
3034  */
3035 void
3036 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3037 {
3038         MonoInst *ins, *n;
3039
3040         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3041                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3042
3043                 switch (ins->opcode) {
3044                 case OP_ADD_IMM:
3045                 case OP_IADD_IMM:
3046                 case OP_LADD_IMM:
3047                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3048                                 /*
3049                                  * X86_LEA is like ADD, but doesn't have the
3050                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3051                                  * its operand to 64 bit.
3052                                  */
3053                                 ins->opcode = OP_X86_LEA_MEMBASE;
3054                                 ins->inst_basereg = ins->sreg1;
3055                         }
3056                         break;
3057                 case OP_LXOR:
3058                 case OP_IXOR:
3059                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3060                                 MonoInst *ins2;
3061
3062                                 /*
3063                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3064                                  * the latter has length 2-3 instead of 6 (reverse constant
3065                                  * propagation). These instruction sequences are very common
3066                                  * in the initlocals bblock.
3067                                  */
3068                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3069                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3070                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3071                                                 ins2->sreg1 = ins->dreg;
3072                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3073                                                 /* Continue */
3074                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3075                                                 NULLIFY_INS (ins2);
3076                                                 /* Continue */
3077                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3078                                                 /* Continue */
3079                                         } else {
3080                                                 break;
3081                                         }
3082                                 }
3083                         }
3084                         break;
3085                 case OP_COMPARE_IMM:
3086                 case OP_LCOMPARE_IMM:
3087                         /* OP_COMPARE_IMM (reg, 0)
3088                          * -->
3089                          * OP_AMD64_TEST_NULL (reg)
3090                          */
3091                         if (!ins->inst_imm)
3092                                 ins->opcode = OP_AMD64_TEST_NULL;
3093                         break;
3094                 case OP_ICOMPARE_IMM:
3095                         if (!ins->inst_imm)
3096                                 ins->opcode = OP_X86_TEST_NULL;
3097                         break;
3098                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3099                         /*
3100                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3101                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3102                          * -->
3103                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3104                          * OP_COMPARE_IMM reg, imm
3105                          *
3106                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3107                          */
3108                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3109                             ins->inst_basereg == last_ins->inst_destbasereg &&
3110                             ins->inst_offset == last_ins->inst_offset) {
3111                                         ins->opcode = OP_ICOMPARE_IMM;
3112                                         ins->sreg1 = last_ins->sreg1;
3113
3114                                         /* check if we can remove cmp reg,0 with test null */
3115                                         if (!ins->inst_imm)
3116                                                 ins->opcode = OP_X86_TEST_NULL;
3117                                 }
3118
3119                         break;
3120                 }
3121
3122                 mono_peephole_ins (bb, ins);
3123         }
3124 }
3125
3126 void
3127 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3128 {
3129         MonoInst *ins, *n;
3130
3131         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3132                 switch (ins->opcode) {
3133                 case OP_ICONST:
3134                 case OP_I8CONST: {
3135                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3136                         /* reg = 0 -> XOR (reg, reg) */
3137                         /* XOR sets cflags on x86, so we cant do it always */
3138                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3139                                 ins->opcode = OP_LXOR;
3140                                 ins->sreg1 = ins->dreg;
3141                                 ins->sreg2 = ins->dreg;
3142                                 /* Fall through */
3143                         } else {
3144                                 break;
3145                         }
3146                 }
3147                 case OP_LXOR:
3148                         /*
3149                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3150                          * 0 result into 64 bits.
3151                          */
3152                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3153                                 ins->opcode = OP_IXOR;
3154                         }
3155                         /* Fall through */
3156                 case OP_IXOR:
3157                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3158                                 MonoInst *ins2;
3159
3160                                 /*
3161                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3162                                  * the latter has length 2-3 instead of 6 (reverse constant
3163                                  * propagation). These instruction sequences are very common
3164                                  * in the initlocals bblock.
3165                                  */
3166                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3167                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3168                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3169                                                 ins2->sreg1 = ins->dreg;
3170                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3171                                                 /* Continue */
3172                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3173                                                 NULLIFY_INS (ins2);
3174                                                 /* Continue */
3175                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3176                                                 /* Continue */
3177                                         } else {
3178                                                 break;
3179                                         }
3180                                 }
3181                         }
3182                         break;
3183                 case OP_IADD_IMM:
3184                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3185                                 ins->opcode = OP_X86_INC_REG;
3186                         break;
3187                 case OP_ISUB_IMM:
3188                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3189                                 ins->opcode = OP_X86_DEC_REG;
3190                         break;
3191                 }
3192
3193                 mono_peephole_ins (bb, ins);
3194         }
3195 }
3196
3197 #define NEW_INS(cfg,ins,dest,op) do {   \
3198                 MONO_INST_NEW ((cfg), (dest), (op)); \
3199         (dest)->cil_code = (ins)->cil_code; \
3200         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3201         } while (0)
3202
3203 /*
3204  * mono_arch_lowering_pass:
3205  *
3206  *  Converts complex opcodes into simpler ones so that each IR instruction
3207  * corresponds to one machine instruction.
3208  */
3209 void
3210 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3211 {
3212         MonoInst *ins, *n, *temp;
3213
3214         /*
3215          * FIXME: Need to add more instructions, but the current machine
3216          * description can't model some parts of the composite instructions like
3217          * cdq.
3218          */
3219         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3220                 switch (ins->opcode) {
3221                 case OP_DIV_IMM:
3222                 case OP_REM_IMM:
3223                 case OP_IDIV_IMM:
3224                 case OP_IDIV_UN_IMM:
3225                 case OP_IREM_UN_IMM:
3226                 case OP_LREM_IMM:
3227                 case OP_IREM_IMM:
3228                         mono_decompose_op_imm (cfg, bb, ins);
3229                         break;
3230                 case OP_COMPARE_IMM:
3231                 case OP_LCOMPARE_IMM:
3232                         if (!amd64_is_imm32 (ins->inst_imm)) {
3233                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3234                                 temp->inst_c0 = ins->inst_imm;
3235                                 temp->dreg = mono_alloc_ireg (cfg);
3236                                 ins->opcode = OP_COMPARE;
3237                                 ins->sreg2 = temp->dreg;
3238                         }
3239                         break;
3240 #ifndef __mono_ilp32__
3241                 case OP_LOAD_MEMBASE:
3242 #endif
3243                 case OP_LOADI8_MEMBASE:
3244 #ifndef __native_client_codegen__
3245                 /*  Don't generate memindex opcodes (to simplify */
3246                 /*  read sandboxing) */
3247                         if (!amd64_is_imm32 (ins->inst_offset)) {
3248                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3249                                 temp->inst_c0 = ins->inst_offset;
3250                                 temp->dreg = mono_alloc_ireg (cfg);
3251                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3252                                 ins->inst_indexreg = temp->dreg;
3253                         }
3254 #endif
3255                         break;
3256 #ifndef __mono_ilp32__
3257                 case OP_STORE_MEMBASE_IMM:
3258 #endif
3259                 case OP_STOREI8_MEMBASE_IMM:
3260                         if (!amd64_is_imm32 (ins->inst_imm)) {
3261                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3262                                 temp->inst_c0 = ins->inst_imm;
3263                                 temp->dreg = mono_alloc_ireg (cfg);
3264                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3265                                 ins->sreg1 = temp->dreg;
3266                         }
3267                         break;
3268 #ifdef MONO_ARCH_SIMD_INTRINSICS
3269                 case OP_EXPAND_I1: {
3270                                 int temp_reg1 = mono_alloc_ireg (cfg);
3271                                 int temp_reg2 = mono_alloc_ireg (cfg);
3272                                 int original_reg = ins->sreg1;
3273
3274                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3275                                 temp->sreg1 = original_reg;
3276                                 temp->dreg = temp_reg1;
3277
3278                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3279                                 temp->sreg1 = temp_reg1;
3280                                 temp->dreg = temp_reg2;
3281                                 temp->inst_imm = 8;
3282
3283                                 NEW_INS (cfg, ins, temp, OP_LOR);
3284                                 temp->sreg1 = temp->dreg = temp_reg2;
3285                                 temp->sreg2 = temp_reg1;
3286
3287                                 ins->opcode = OP_EXPAND_I2;
3288                                 ins->sreg1 = temp_reg2;
3289                         }
3290                         break;
3291 #endif
3292                 default:
3293                         break;
3294                 }
3295         }
3296
3297         bb->max_vreg = cfg->next_vreg;
3298 }
3299
3300 static const int
3301 branch_cc_table [] = {
3302         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3303         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3304         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3305 };
3306
3307 /* Maps CMP_... constants to X86_CC_... constants */
3308 static const int
3309 cc_table [] = {
3310         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3311         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3312 };
3313
3314 static const int
3315 cc_signed_table [] = {
3316         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3317         FALSE, FALSE, FALSE, FALSE
3318 };
3319
3320 /*#include "cprop.c"*/
3321
3322 static unsigned char*
3323 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3324 {
3325         if (size == 8)
3326                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3327         else
3328                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3329
3330         if (size == 1)
3331                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3332         else if (size == 2)
3333                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3334         return code;
3335 }
3336
3337 static unsigned char*
3338 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3339 {
3340         int sreg = tree->sreg1;
3341         int need_touch = FALSE;
3342
3343 #if defined(HOST_WIN32)
3344         need_touch = TRUE;
3345 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3346         if (!tree->flags & MONO_INST_INIT)
3347                 need_touch = TRUE;
3348 #endif
3349
3350         if (need_touch) {
3351                 guint8* br[5];
3352
3353                 /*
3354                  * Under Windows:
3355                  * If requested stack size is larger than one page,
3356                  * perform stack-touch operation
3357                  */
3358                 /*
3359                  * Generate stack probe code.
3360                  * Under Windows, it is necessary to allocate one page at a time,
3361                  * "touching" stack after each successful sub-allocation. This is
3362                  * because of the way stack growth is implemented - there is a
3363                  * guard page before the lowest stack page that is currently commited.
3364                  * Stack normally grows sequentially so OS traps access to the
3365                  * guard page and commits more pages when needed.
3366                  */
3367                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3368                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3369
3370                 br[2] = code; /* loop */
3371                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3372                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3373                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3374                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3375                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3376                 amd64_patch (br[3], br[2]);
3377                 amd64_test_reg_reg (code, sreg, sreg);
3378                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3379                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3380
3381                 br[1] = code; x86_jump8 (code, 0);
3382
3383                 amd64_patch (br[0], code);
3384                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3385                 amd64_patch (br[1], code);
3386                 amd64_patch (br[4], code);
3387         }
3388         else
3389                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3390
3391         if (tree->flags & MONO_INST_INIT) {
3392                 int offset = 0;
3393                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3394                         amd64_push_reg (code, AMD64_RAX);
3395                         offset += 8;
3396                 }
3397                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3398                         amd64_push_reg (code, AMD64_RCX);
3399                         offset += 8;
3400                 }
3401                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3402                         amd64_push_reg (code, AMD64_RDI);
3403                         offset += 8;
3404                 }
3405
3406                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3407                 if (sreg != AMD64_RCX)
3408                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3409                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3410
3411                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3412                 if (cfg->param_area)
3413                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3414                 amd64_cld (code);
3415 #if defined(__default_codegen__)
3416                 amd64_prefix (code, X86_REP_PREFIX);
3417                 amd64_stosl (code);
3418 #elif defined(__native_client_codegen__)
3419                 /* NaCl stos pseudo-instruction */
3420                 amd64_codegen_pre(code);
3421                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3422                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3423                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3424                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3425                 amd64_prefix (code, X86_REP_PREFIX);
3426                 amd64_stosl (code);
3427                 amd64_codegen_post(code);
3428 #endif /* __native_client_codegen__ */
3429
3430                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3431                         amd64_pop_reg (code, AMD64_RDI);
3432                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3433                         amd64_pop_reg (code, AMD64_RCX);
3434                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3435                         amd64_pop_reg (code, AMD64_RAX);
3436         }
3437         return code;
3438 }
3439
3440 static guint8*
3441 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3442 {
3443         CallInfo *cinfo;
3444         guint32 quad;
3445
3446         /* Move return value to the target register */
3447         /* FIXME: do this in the local reg allocator */
3448         switch (ins->opcode) {
3449         case OP_CALL:
3450         case OP_CALL_REG:
3451         case OP_CALL_MEMBASE:
3452         case OP_LCALL:
3453         case OP_LCALL_REG:
3454         case OP_LCALL_MEMBASE:
3455                 g_assert (ins->dreg == AMD64_RAX);
3456                 break;
3457         case OP_FCALL:
3458         case OP_FCALL_REG:
3459         case OP_FCALL_MEMBASE: {
3460                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3461                 if (rtype->type == MONO_TYPE_R4) {
3462                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3463                 }
3464                 else {
3465                         if (ins->dreg != AMD64_XMM0)
3466                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3467                 }
3468                 break;
3469         }
3470         case OP_RCALL:
3471         case OP_RCALL_REG:
3472         case OP_RCALL_MEMBASE:
3473                 if (ins->dreg != AMD64_XMM0)
3474                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3475                 break;
3476         case OP_VCALL:
3477         case OP_VCALL_REG:
3478         case OP_VCALL_MEMBASE:
3479         case OP_VCALL2:
3480         case OP_VCALL2_REG:
3481         case OP_VCALL2_MEMBASE:
3482                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3483                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3484                         MonoInst *loc = cfg->arch.vret_addr_loc;
3485
3486                         /* Load the destination address */
3487                         g_assert (loc->opcode == OP_REGOFFSET);
3488                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3489
3490                         for (quad = 0; quad < 2; quad ++) {
3491                                 switch (cinfo->ret.pair_storage [quad]) {
3492                                 case ArgInIReg:
3493                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3494                                         break;
3495                                 case ArgInFloatSSEReg:
3496                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3497                                         break;
3498                                 case ArgInDoubleSSEReg:
3499                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3500                                         break;
3501                                 case ArgNone:
3502                                         break;
3503                                 default:
3504                                         NOT_IMPLEMENTED;
3505                                 }
3506                         }
3507                 }
3508                 break;
3509         }
3510
3511         return code;
3512 }
3513
3514 #endif /* DISABLE_JIT */
3515
3516 #ifdef __APPLE__
3517 static int tls_gs_offset;
3518 #endif
3519
3520 gboolean
3521 mono_amd64_have_tls_get (void)
3522 {
3523 #ifdef TARGET_MACH
3524         static gboolean have_tls_get = FALSE;
3525         static gboolean inited = FALSE;
3526         guint8 *ins;
3527
3528         if (inited)
3529                 return have_tls_get;
3530
3531         ins = (guint8*)pthread_getspecific;
3532
3533         /*
3534          * We're looking for these two instructions:
3535          *
3536          * mov    %gs:[offset](,%rdi,8),%rax
3537          * retq
3538          */
3539         have_tls_get = ins [0] == 0x65 &&
3540                        ins [1] == 0x48 &&
3541                        ins [2] == 0x8b &&
3542                        ins [3] == 0x04 &&
3543                        ins [4] == 0xfd &&
3544                        ins [6] == 0x00 &&
3545                        ins [7] == 0x00 &&
3546                        ins [8] == 0x00 &&
3547                        ins [9] == 0xc3;
3548
3549         inited = TRUE;
3550
3551         tls_gs_offset = ins[5];
3552
3553         return have_tls_get;
3554 #elif defined(TARGET_ANDROID)
3555         return FALSE;
3556 #else
3557         return TRUE;
3558 #endif
3559 }
3560
3561 int
3562 mono_amd64_get_tls_gs_offset (void)
3563 {
3564 #ifdef TARGET_OSX
3565         return tls_gs_offset;
3566 #else
3567         g_assert_not_reached ();
3568         return -1;
3569 #endif
3570 }
3571
3572 /*
3573  * mono_amd64_emit_tls_get:
3574  * @code: buffer to store code to
3575  * @dreg: hard register where to place the result
3576  * @tls_offset: offset info
3577  *
3578  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3579  * the dreg register the item in the thread local storage identified
3580  * by tls_offset.
3581  *
3582  * Returns: a pointer to the end of the stored code
3583  */
3584 guint8*
3585 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3586 {
3587 #ifdef HOST_WIN32
3588         if (tls_offset < 64) {
3589                 x86_prefix (code, X86_GS_PREFIX);
3590                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3591         } else {
3592                 guint8 *buf [16];
3593
3594                 g_assert (tls_offset < 0x440);
3595                 /* Load TEB->TlsExpansionSlots */
3596                 x86_prefix (code, X86_GS_PREFIX);
3597                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3598                 amd64_test_reg_reg (code, dreg, dreg);
3599                 buf [0] = code;
3600                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3601                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3602                 amd64_patch (buf [0], code);
3603         }
3604 #elif defined(__APPLE__)
3605         x86_prefix (code, X86_GS_PREFIX);
3606         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3607 #else
3608         if (optimize_for_xen) {
3609                 x86_prefix (code, X86_FS_PREFIX);
3610                 amd64_mov_reg_mem (code, dreg, 0, 8);
3611                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3612         } else {
3613                 x86_prefix (code, X86_FS_PREFIX);
3614                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3615         }
3616 #endif
3617         return code;
3618 }
3619
3620 static guint8*
3621 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3622 {
3623         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3624 #ifdef TARGET_OSX
3625         if (dreg != offset_reg)
3626                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3627         amd64_prefix (code, X86_GS_PREFIX);
3628         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3629 #elif defined(__linux__)
3630         int tmpreg = -1;
3631
3632         if (dreg == offset_reg) {
3633                 /* Use a temporary reg by saving it to the redzone */
3634                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3635                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3636                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3637                 offset_reg = tmpreg;
3638         }
3639         x86_prefix (code, X86_FS_PREFIX);
3640         amd64_mov_reg_mem (code, dreg, 0, 8);
3641         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3642         if (tmpreg != -1)
3643                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3644 #else
3645         g_assert_not_reached ();
3646 #endif
3647         return code;
3648 }
3649
3650 static guint8*
3651 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3652 {
3653 #ifdef HOST_WIN32
3654         g_assert_not_reached ();
3655 #elif defined(__APPLE__)
3656         x86_prefix (code, X86_GS_PREFIX);
3657         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3658 #else
3659         g_assert (!optimize_for_xen);
3660         x86_prefix (code, X86_FS_PREFIX);
3661         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3662 #endif
3663         return code;
3664 }
3665
3666 static guint8*
3667 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3668 {
3669         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3670 #ifdef HOST_WIN32
3671         g_assert_not_reached ();
3672 #elif defined(__APPLE__)
3673         x86_prefix (code, X86_GS_PREFIX);
3674         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3675 #else
3676         x86_prefix (code, X86_FS_PREFIX);
3677         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3678 #endif
3679         return code;
3680 }
3681
3682  /*
3683  * mono_arch_translate_tls_offset:
3684  *
3685  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3686  */
3687 int
3688 mono_arch_translate_tls_offset (int offset)
3689 {
3690 #ifdef __APPLE__
3691         return tls_gs_offset + (offset * 8);
3692 #else
3693         return offset;
3694 #endif
3695 }
3696
3697 /*
3698  * emit_setup_lmf:
3699  *
3700  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3701  */
3702 static guint8*
3703 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3704 {
3705         /*
3706          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3707          */
3708         /*
3709          * sp is saved right before calls but we need to save it here too so
3710          * async stack walks would work.
3711          */
3712         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3713         /* Save rbp */
3714         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3715         if (cfg->arch.omit_fp && cfa_offset != -1)
3716                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3717
3718         /* These can't contain refs */
3719         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3720         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3721         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3722         /* These are handled automatically by the stack marking code */
3723         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3724
3725         return code;
3726 }
3727
3728 #define REAL_PRINT_REG(text,reg) \
3729 mono_assert (reg >= 0); \
3730 amd64_push_reg (code, AMD64_RAX); \
3731 amd64_push_reg (code, AMD64_RDX); \
3732 amd64_push_reg (code, AMD64_RCX); \
3733 amd64_push_reg (code, reg); \
3734 amd64_push_imm (code, reg); \
3735 amd64_push_imm (code, text " %d %p\n"); \
3736 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3737 amd64_call_reg (code, AMD64_RAX); \
3738 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3739 amd64_pop_reg (code, AMD64_RCX); \
3740 amd64_pop_reg (code, AMD64_RDX); \
3741 amd64_pop_reg (code, AMD64_RAX);
3742
3743 /* benchmark and set based on cpu */
3744 #define LOOP_ALIGNMENT 8
3745 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3746
3747 #ifndef DISABLE_JIT
3748 void
3749 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3750 {
3751         MonoInst *ins;
3752         MonoCallInst *call;
3753         guint offset;
3754         guint8 *code = cfg->native_code + cfg->code_len;
3755         int max_len;
3756
3757         /* Fix max_offset estimate for each successor bb */
3758         if (cfg->opt & MONO_OPT_BRANCH) {
3759                 int current_offset = cfg->code_len;
3760                 MonoBasicBlock *current_bb;
3761                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3762                         current_bb->max_offset = current_offset;
3763                         current_offset += current_bb->max_length;
3764                 }
3765         }
3766
3767         if (cfg->opt & MONO_OPT_LOOP) {
3768                 int pad, align = LOOP_ALIGNMENT;
3769                 /* set alignment depending on cpu */
3770                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3771                         pad = align - pad;
3772                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3773                         amd64_padding (code, pad);
3774                         cfg->code_len += pad;
3775                         bb->native_offset = cfg->code_len;
3776                 }
3777         }
3778
3779 #if defined(__native_client_codegen__)
3780         /* For Native Client, all indirect call/jump targets must be */
3781         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3782         /* indirectly as well.                                       */
3783         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3784                                       (bb->flags & BB_EXCEPTION_HANDLER);
3785
3786         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3787                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3788                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3789                 cfg->code_len += pad;
3790                 bb->native_offset = cfg->code_len;
3791         }
3792 #endif  /*__native_client_codegen__*/
3793
3794         if (cfg->verbose_level > 2)
3795                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3796
3797         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3798                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3799                 g_assert (!cfg->compile_aot);
3800
3801                 cov->data [bb->dfn].cil_code = bb->cil_code;
3802                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3803                 /* this is not thread save, but good enough */
3804                 amd64_inc_membase (code, AMD64_R11, 0);
3805         }
3806
3807         offset = code - cfg->native_code;
3808
3809         mono_debug_open_block (cfg, bb, offset);
3810
3811     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3812                 x86_breakpoint (code);
3813
3814         MONO_BB_FOR_EACH_INS (bb, ins) {
3815                 offset = code - cfg->native_code;
3816
3817                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3818
3819 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3820
3821                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3822                         cfg->code_size *= 2;
3823                         cfg->native_code = mono_realloc_native_code(cfg);
3824                         code = cfg->native_code + offset;
3825                         cfg->stat_code_reallocs++;
3826                 }
3827
3828                 if (cfg->debug_info)
3829                         mono_debug_record_line_number (cfg, ins, offset);
3830
3831                 switch (ins->opcode) {
3832                 case OP_BIGMUL:
3833                         amd64_mul_reg (code, ins->sreg2, TRUE);
3834                         break;
3835                 case OP_BIGMUL_UN:
3836                         amd64_mul_reg (code, ins->sreg2, FALSE);
3837                         break;
3838                 case OP_X86_SETEQ_MEMBASE:
3839                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3840                         break;
3841                 case OP_STOREI1_MEMBASE_IMM:
3842                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3843                         break;
3844                 case OP_STOREI2_MEMBASE_IMM:
3845                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3846                         break;
3847                 case OP_STOREI4_MEMBASE_IMM:
3848                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3849                         break;
3850                 case OP_STOREI1_MEMBASE_REG:
3851                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3852                         break;
3853                 case OP_STOREI2_MEMBASE_REG:
3854                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3855                         break;
3856                 /* In AMD64 NaCl, pointers are 4 bytes, */
3857                 /*  so STORE_* != STOREI8_*. Likewise below. */
3858                 case OP_STORE_MEMBASE_REG:
3859                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3860                         break;
3861                 case OP_STOREI8_MEMBASE_REG:
3862                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3863                         break;
3864                 case OP_STOREI4_MEMBASE_REG:
3865                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3866                         break;
3867                 case OP_STORE_MEMBASE_IMM:
3868 #ifndef __native_client_codegen__
3869                         /* In NaCl, this could be a PCONST type, which could */
3870                         /* mean a pointer type was copied directly into the  */
3871                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3872                         /* the value would be 0x00000000FFFFFFFF which is    */
3873                         /* not proper for an imm32 unless you cast it.       */
3874                         g_assert (amd64_is_imm32 (ins->inst_imm));
3875 #endif
3876                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3877                         break;
3878                 case OP_STOREI8_MEMBASE_IMM:
3879                         g_assert (amd64_is_imm32 (ins->inst_imm));
3880                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3881                         break;
3882                 case OP_LOAD_MEM:
3883 #ifdef __mono_ilp32__
3884                         /* In ILP32, pointers are 4 bytes, so separate these */
3885                         /* cases, use literal 8 below where we really want 8 */
3886                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3887                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3888                         break;
3889 #endif
3890                 case OP_LOADI8_MEM:
3891                         // FIXME: Decompose this earlier
3892                         if (amd64_is_imm32 (ins->inst_imm))
3893                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3894                         else {
3895                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3896                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3897                         }
3898                         break;
3899                 case OP_LOADI4_MEM:
3900                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3901                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3902                         break;
3903                 case OP_LOADU4_MEM:
3904                         // FIXME: Decompose this earlier
3905                         if (amd64_is_imm32 (ins->inst_imm))
3906                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3907                         else {
3908                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3909                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3910                         }
3911                         break;
3912                 case OP_LOADU1_MEM:
3913                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3914                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3915                         break;
3916                 case OP_LOADU2_MEM:
3917                         /* For NaCl, pointers are 4 bytes, so separate these */
3918                         /* cases, use literal 8 below where we really want 8 */
3919                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3920                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3921                         break;
3922                 case OP_LOAD_MEMBASE:
3923                         g_assert (amd64_is_imm32 (ins->inst_offset));
3924                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3925                         break;
3926                 case OP_LOADI8_MEMBASE:
3927                         /* Use literal 8 instead of sizeof pointer or */
3928                         /* register, we really want 8 for this opcode */
3929                         g_assert (amd64_is_imm32 (ins->inst_offset));
3930                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3931                         break;
3932                 case OP_LOADI4_MEMBASE:
3933                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3934                         break;
3935                 case OP_LOADU4_MEMBASE:
3936                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3937                         break;
3938                 case OP_LOADU1_MEMBASE:
3939                         /* The cpu zero extends the result into 64 bits */
3940                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3941                         break;
3942                 case OP_LOADI1_MEMBASE:
3943                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3944                         break;
3945                 case OP_LOADU2_MEMBASE:
3946                         /* The cpu zero extends the result into 64 bits */
3947                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3948                         break;
3949                 case OP_LOADI2_MEMBASE:
3950                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3951                         break;
3952                 case OP_AMD64_LOADI8_MEMINDEX:
3953                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3954                         break;
3955                 case OP_LCONV_TO_I1:
3956                 case OP_ICONV_TO_I1:
3957                 case OP_SEXT_I1:
3958                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3959                         break;
3960                 case OP_LCONV_TO_I2:
3961                 case OP_ICONV_TO_I2:
3962                 case OP_SEXT_I2:
3963                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3964                         break;
3965                 case OP_LCONV_TO_U1:
3966                 case OP_ICONV_TO_U1:
3967                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3968                         break;
3969                 case OP_LCONV_TO_U2:
3970                 case OP_ICONV_TO_U2:
3971                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3972                         break;
3973                 case OP_ZEXT_I4:
3974                         /* Clean out the upper word */
3975                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3976                         break;
3977                 case OP_SEXT_I4:
3978                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3979                         break;
3980                 case OP_COMPARE:
3981                 case OP_LCOMPARE:
3982                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3983                         break;
3984                 case OP_COMPARE_IMM:
3985 #if defined(__mono_ilp32__)
3986                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3987                         g_assert (amd64_is_imm32 (ins->inst_imm));
3988                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3989                         break;
3990 #endif
3991                 case OP_LCOMPARE_IMM:
3992                         g_assert (amd64_is_imm32 (ins->inst_imm));
3993                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3994                         break;
3995                 case OP_X86_COMPARE_REG_MEMBASE:
3996                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3997                         break;
3998                 case OP_X86_TEST_NULL:
3999                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4000                         break;
4001                 case OP_AMD64_TEST_NULL:
4002                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4003                         break;
4004
4005                 case OP_X86_ADD_REG_MEMBASE:
4006                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4007                         break;
4008                 case OP_X86_SUB_REG_MEMBASE:
4009                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4010                         break;
4011                 case OP_X86_AND_REG_MEMBASE:
4012                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4013                         break;
4014                 case OP_X86_OR_REG_MEMBASE:
4015                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4016                         break;
4017                 case OP_X86_XOR_REG_MEMBASE:
4018                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4019                         break;
4020
4021                 case OP_X86_ADD_MEMBASE_IMM:
4022                         /* FIXME: Make a 64 version too */
4023                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4024                         break;
4025                 case OP_X86_SUB_MEMBASE_IMM:
4026                         g_assert (amd64_is_imm32 (ins->inst_imm));
4027                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4028                         break;
4029                 case OP_X86_AND_MEMBASE_IMM:
4030                         g_assert (amd64_is_imm32 (ins->inst_imm));
4031                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4032                         break;
4033                 case OP_X86_OR_MEMBASE_IMM:
4034                         g_assert (amd64_is_imm32 (ins->inst_imm));
4035                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4036                         break;
4037                 case OP_X86_XOR_MEMBASE_IMM:
4038                         g_assert (amd64_is_imm32 (ins->inst_imm));
4039                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4040                         break;
4041                 case OP_X86_ADD_MEMBASE_REG:
4042                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4043                         break;
4044                 case OP_X86_SUB_MEMBASE_REG:
4045                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4046                         break;
4047                 case OP_X86_AND_MEMBASE_REG:
4048                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4049                         break;
4050                 case OP_X86_OR_MEMBASE_REG:
4051                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4052                         break;
4053                 case OP_X86_XOR_MEMBASE_REG:
4054                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4055                         break;
4056                 case OP_X86_INC_MEMBASE:
4057                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4058                         break;
4059                 case OP_X86_INC_REG:
4060                         amd64_inc_reg_size (code, ins->dreg, 4);
4061                         break;
4062                 case OP_X86_DEC_MEMBASE:
4063                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4064                         break;
4065                 case OP_X86_DEC_REG:
4066                         amd64_dec_reg_size (code, ins->dreg, 4);
4067                         break;
4068                 case OP_X86_MUL_REG_MEMBASE:
4069                 case OP_X86_MUL_MEMBASE_REG:
4070                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4071                         break;
4072                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4073                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4074                         break;
4075                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4076                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4077                         break;
4078                 case OP_AMD64_COMPARE_MEMBASE_REG:
4079                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4080                         break;
4081                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4082                         g_assert (amd64_is_imm32 (ins->inst_imm));
4083                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4084                         break;
4085                 case OP_X86_COMPARE_MEMBASE8_IMM:
4086                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4087                         break;
4088                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4089                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4090                         break;
4091                 case OP_AMD64_COMPARE_REG_MEMBASE:
4092                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4093                         break;
4094
4095                 case OP_AMD64_ADD_REG_MEMBASE:
4096                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4097                         break;
4098                 case OP_AMD64_SUB_REG_MEMBASE:
4099                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4100                         break;
4101                 case OP_AMD64_AND_REG_MEMBASE:
4102                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4103                         break;
4104                 case OP_AMD64_OR_REG_MEMBASE:
4105                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4106                         break;
4107                 case OP_AMD64_XOR_REG_MEMBASE:
4108                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4109                         break;
4110
4111                 case OP_AMD64_ADD_MEMBASE_REG:
4112                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4113                         break;
4114                 case OP_AMD64_SUB_MEMBASE_REG:
4115                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4116                         break;
4117                 case OP_AMD64_AND_MEMBASE_REG:
4118                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4119                         break;
4120                 case OP_AMD64_OR_MEMBASE_REG:
4121                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4122                         break;
4123                 case OP_AMD64_XOR_MEMBASE_REG:
4124                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4125                         break;
4126
4127                 case OP_AMD64_ADD_MEMBASE_IMM:
4128                         g_assert (amd64_is_imm32 (ins->inst_imm));
4129                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4130                         break;
4131                 case OP_AMD64_SUB_MEMBASE_IMM:
4132                         g_assert (amd64_is_imm32 (ins->inst_imm));
4133                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4134                         break;
4135                 case OP_AMD64_AND_MEMBASE_IMM:
4136                         g_assert (amd64_is_imm32 (ins->inst_imm));
4137                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4138                         break;
4139                 case OP_AMD64_OR_MEMBASE_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4142                         break;
4143                 case OP_AMD64_XOR_MEMBASE_IMM:
4144                         g_assert (amd64_is_imm32 (ins->inst_imm));
4145                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4146                         break;
4147
4148                 case OP_BREAK:
4149                         amd64_breakpoint (code);
4150                         break;
4151                 case OP_RELAXED_NOP:
4152                         x86_prefix (code, X86_REP_PREFIX);
4153                         x86_nop (code);
4154                         break;
4155                 case OP_HARD_NOP:
4156                         x86_nop (code);
4157                         break;
4158                 case OP_NOP:
4159                 case OP_DUMMY_USE:
4160                 case OP_DUMMY_STORE:
4161                 case OP_DUMMY_ICONST:
4162                 case OP_DUMMY_R8CONST:
4163                 case OP_NOT_REACHED:
4164                 case OP_NOT_NULL:
4165                         break;
4166                 case OP_IL_SEQ_POINT:
4167                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4168                         break;
4169                 case OP_SEQ_POINT: {
4170                         int i;
4171
4172                         /*
4173                          * Read from the single stepping trigger page. This will cause a
4174                          * SIGSEGV when single stepping is enabled.
4175                          * We do this _before_ the breakpoint, so single stepping after
4176                          * a breakpoint is hit will step to the next IL offset.
4177                          */
4178                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4179                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4180
4181                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4182                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4183                         }
4184
4185                         /*
4186                          * This is the address which is saved in seq points,
4187                          */
4188                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4189
4190                         if (cfg->compile_aot) {
4191                                 guint32 offset = code - cfg->native_code;
4192                                 guint32 val;
4193                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4194
4195                                 /* Load info var */
4196                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4197                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4198                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4199                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4200                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4201                         } else {
4202                                 /*
4203                                  * A placeholder for a possible breakpoint inserted by
4204                                  * mono_arch_set_breakpoint ().
4205                                  */
4206                                 for (i = 0; i < breakpoint_size; ++i)
4207                                         x86_nop (code);
4208                         }
4209                         /*
4210                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4211                          * to another IL offset.
4212                          */
4213                         x86_nop (code);
4214                         break;
4215                 }
4216                 case OP_ADDCC:
4217                 case OP_LADDCC:
4218                 case OP_LADD:
4219                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4220                         break;
4221                 case OP_ADC:
4222                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4223                         break;
4224                 case OP_ADD_IMM:
4225                 case OP_LADD_IMM:
4226                         g_assert (amd64_is_imm32 (ins->inst_imm));
4227                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4228                         break;
4229                 case OP_ADC_IMM:
4230                         g_assert (amd64_is_imm32 (ins->inst_imm));
4231                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4232                         break;
4233                 case OP_SUBCC:
4234                 case OP_LSUBCC:
4235                 case OP_LSUB:
4236                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4237                         break;
4238                 case OP_SBB:
4239                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4240                         break;
4241                 case OP_SUB_IMM:
4242                 case OP_LSUB_IMM:
4243                         g_assert (amd64_is_imm32 (ins->inst_imm));
4244                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4245                         break;
4246                 case OP_SBB_IMM:
4247                         g_assert (amd64_is_imm32 (ins->inst_imm));
4248                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4249                         break;
4250                 case OP_LAND:
4251                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4252                         break;
4253                 case OP_AND_IMM:
4254                 case OP_LAND_IMM:
4255                         g_assert (amd64_is_imm32 (ins->inst_imm));
4256                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4257                         break;
4258                 case OP_LMUL:
4259                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4260                         break;
4261                 case OP_MUL_IMM:
4262                 case OP_LMUL_IMM:
4263                 case OP_IMUL_IMM: {
4264                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4265
4266                         switch (ins->inst_imm) {
4267                         case 2:
4268                                 /* MOV r1, r2 */
4269                                 /* ADD r1, r1 */
4270                                 if (ins->dreg != ins->sreg1)
4271                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4272                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4273                                 break;
4274                         case 3:
4275                                 /* LEA r1, [r2 + r2*2] */
4276                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4277                                 break;
4278                         case 5:
4279                                 /* LEA r1, [r2 + r2*4] */
4280                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4281                                 break;
4282                         case 6:
4283                                 /* LEA r1, [r2 + r2*2] */
4284                                 /* ADD r1, r1          */
4285                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4286                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4287                                 break;
4288                         case 9:
4289                                 /* LEA r1, [r2 + r2*8] */
4290                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4291                                 break;
4292                         case 10:
4293                                 /* LEA r1, [r2 + r2*4] */
4294                                 /* ADD r1, r1          */
4295                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4296                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4297                                 break;
4298                         case 12:
4299                                 /* LEA r1, [r2 + r2*2] */
4300                                 /* SHL r1, 2           */
4301                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4302                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4303                                 break;
4304                         case 25:
4305                                 /* LEA r1, [r2 + r2*4] */
4306                                 /* LEA r1, [r1 + r1*4] */
4307                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4308                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4309                                 break;
4310                         case 100:
4311                                 /* LEA r1, [r2 + r2*4] */
4312                                 /* SHL r1, 2           */
4313                                 /* LEA r1, [r1 + r1*4] */
4314                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4315                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4316                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4317                                 break;
4318                         default:
4319                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4320                                 break;
4321                         }
4322                         break;
4323                 }
4324                 case OP_LDIV:
4325                 case OP_LREM:
4326 #if defined( __native_client_codegen__ )
4327                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4328                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4329 #endif
4330                         /* Regalloc magic makes the div/rem cases the same */
4331                         if (ins->sreg2 == AMD64_RDX) {
4332                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4333                                 amd64_cdq (code);
4334                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4335                         } else {
4336                                 amd64_cdq (code);
4337                                 amd64_div_reg (code, ins->sreg2, TRUE);
4338                         }
4339                         break;
4340                 case OP_LDIV_UN:
4341                 case OP_LREM_UN:
4342 #if defined( __native_client_codegen__ )
4343                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4344                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4345 #endif
4346                         if (ins->sreg2 == AMD64_RDX) {
4347                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4348                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4349                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4350                         } else {
4351                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4352                                 amd64_div_reg (code, ins->sreg2, FALSE);
4353                         }
4354                         break;
4355                 case OP_IDIV:
4356                 case OP_IREM:
4357 #if defined( __native_client_codegen__ )
4358                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4359                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4360 #endif
4361                         if (ins->sreg2 == AMD64_RDX) {
4362                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4363                                 amd64_cdq_size (code, 4);
4364                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4365                         } else {
4366                                 amd64_cdq_size (code, 4);
4367                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4368                         }
4369                         break;
4370                 case OP_IDIV_UN:
4371                 case OP_IREM_UN:
4372 #if defined( __native_client_codegen__ )
4373                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4374                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4375 #endif
4376                         if (ins->sreg2 == AMD64_RDX) {
4377                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4378                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4379                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4380                         } else {
4381                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4382                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4383                         }
4384                         break;
4385                 case OP_LMUL_OVF:
4386                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4387                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4388                         break;
4389                 case OP_LOR:
4390                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4391                         break;
4392                 case OP_OR_IMM:
4393                 case OP_LOR_IMM:
4394                         g_assert (amd64_is_imm32 (ins->inst_imm));
4395                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4396                         break;
4397                 case OP_LXOR:
4398                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4399                         break;
4400                 case OP_XOR_IMM:
4401                 case OP_LXOR_IMM:
4402                         g_assert (amd64_is_imm32 (ins->inst_imm));
4403                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4404                         break;
4405                 case OP_LSHL:
4406                         g_assert (ins->sreg2 == AMD64_RCX);
4407                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4408                         break;
4409                 case OP_LSHR:
4410                         g_assert (ins->sreg2 == AMD64_RCX);
4411                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4412                         break;
4413                 case OP_SHR_IMM:
4414                         g_assert (amd64_is_imm32 (ins->inst_imm));
4415                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4416                         break;
4417                 case OP_LSHR_IMM:
4418                         g_assert (amd64_is_imm32 (ins->inst_imm));
4419                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4420                         break;
4421                 case OP_SHR_UN_IMM:
4422                         g_assert (amd64_is_imm32 (ins->inst_imm));
4423                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4424                         break;
4425                 case OP_LSHR_UN_IMM:
4426                         g_assert (amd64_is_imm32 (ins->inst_imm));
4427                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4428                         break;
4429                 case OP_LSHR_UN:
4430                         g_assert (ins->sreg2 == AMD64_RCX);
4431                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4432                         break;
4433                 case OP_SHL_IMM:
4434                         g_assert (amd64_is_imm32 (ins->inst_imm));
4435                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4436                         break;
4437                 case OP_LSHL_IMM:
4438                         g_assert (amd64_is_imm32 (ins->inst_imm));
4439                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4440                         break;
4441
4442                 case OP_IADDCC:
4443                 case OP_IADD:
4444                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4445                         break;
4446                 case OP_IADC:
4447                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4448                         break;
4449                 case OP_IADD_IMM:
4450                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4451                         break;
4452                 case OP_IADC_IMM:
4453                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4454                         break;
4455                 case OP_ISUBCC:
4456                 case OP_ISUB:
4457                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4458                         break;
4459                 case OP_ISBB:
4460                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4461                         break;
4462                 case OP_ISUB_IMM:
4463                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4464                         break;
4465                 case OP_ISBB_IMM:
4466                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4467                         break;
4468                 case OP_IAND:
4469                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4470                         break;
4471                 case OP_IAND_IMM:
4472                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4473                         break;
4474                 case OP_IOR:
4475                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4476                         break;
4477                 case OP_IOR_IMM:
4478                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4479                         break;
4480                 case OP_IXOR:
4481                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4482                         break;
4483                 case OP_IXOR_IMM:
4484                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4485                         break;
4486                 case OP_INEG:
4487                         amd64_neg_reg_size (code, ins->sreg1, 4);
4488                         break;
4489                 case OP_INOT:
4490                         amd64_not_reg_size (code, ins->sreg1, 4);
4491                         break;
4492                 case OP_ISHL:
4493                         g_assert (ins->sreg2 == AMD64_RCX);
4494                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4495                         break;
4496                 case OP_ISHR:
4497                         g_assert (ins->sreg2 == AMD64_RCX);
4498                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4499                         break;
4500                 case OP_ISHR_IMM:
4501                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4502                         break;
4503                 case OP_ISHR_UN_IMM:
4504                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4505                         break;
4506                 case OP_ISHR_UN:
4507                         g_assert (ins->sreg2 == AMD64_RCX);
4508                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4509                         break;
4510                 case OP_ISHL_IMM:
4511                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4512                         break;
4513                 case OP_IMUL:
4514                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4515                         break;
4516                 case OP_IMUL_OVF:
4517                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4518                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4519                         break;
4520                 case OP_IMUL_OVF_UN:
4521                 case OP_LMUL_OVF_UN: {
4522                         /* the mul operation and the exception check should most likely be split */
4523                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4524                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4525                         /*g_assert (ins->sreg2 == X86_EAX);
4526                         g_assert (ins->dreg == X86_EAX);*/
4527                         if (ins->sreg2 == X86_EAX) {
4528                                 non_eax_reg = ins->sreg1;
4529                         } else if (ins->sreg1 == X86_EAX) {
4530                                 non_eax_reg = ins->sreg2;
4531                         } else {
4532                                 /* no need to save since we're going to store to it anyway */
4533                                 if (ins->dreg != X86_EAX) {
4534                                         saved_eax = TRUE;
4535                                         amd64_push_reg (code, X86_EAX);
4536                                 }
4537                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4538                                 non_eax_reg = ins->sreg2;
4539                         }
4540                         if (ins->dreg == X86_EDX) {
4541                                 if (!saved_eax) {
4542                                         saved_eax = TRUE;
4543                                         amd64_push_reg (code, X86_EAX);
4544                                 }
4545                         } else {
4546                                 saved_edx = TRUE;
4547                                 amd64_push_reg (code, X86_EDX);
4548                         }
4549                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4550                         /* save before the check since pop and mov don't change the flags */
4551                         if (ins->dreg != X86_EAX)
4552                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4553                         if (saved_edx)
4554                                 amd64_pop_reg (code, X86_EDX);
4555                         if (saved_eax)
4556                                 amd64_pop_reg (code, X86_EAX);
4557                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4558                         break;
4559                 }
4560                 case OP_ICOMPARE:
4561                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4562                         break;
4563                 case OP_ICOMPARE_IMM:
4564                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4565                         break;
4566                 case OP_IBEQ:
4567                 case OP_IBLT:
4568                 case OP_IBGT:
4569                 case OP_IBGE:
4570                 case OP_IBLE:
4571                 case OP_LBEQ:
4572                 case OP_LBLT:
4573                 case OP_LBGT:
4574                 case OP_LBGE:
4575                 case OP_LBLE:
4576                 case OP_IBNE_UN:
4577                 case OP_IBLT_UN:
4578                 case OP_IBGT_UN:
4579                 case OP_IBGE_UN:
4580                 case OP_IBLE_UN:
4581                 case OP_LBNE_UN:
4582                 case OP_LBLT_UN:
4583                 case OP_LBGT_UN:
4584                 case OP_LBGE_UN:
4585                 case OP_LBLE_UN:
4586                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4587                         break;
4588
4589                 case OP_CMOV_IEQ:
4590                 case OP_CMOV_IGE:
4591                 case OP_CMOV_IGT:
4592                 case OP_CMOV_ILE:
4593                 case OP_CMOV_ILT:
4594                 case OP_CMOV_INE_UN:
4595                 case OP_CMOV_IGE_UN:
4596                 case OP_CMOV_IGT_UN:
4597                 case OP_CMOV_ILE_UN:
4598                 case OP_CMOV_ILT_UN:
4599                 case OP_CMOV_LEQ:
4600                 case OP_CMOV_LGE:
4601                 case OP_CMOV_LGT:
4602                 case OP_CMOV_LLE:
4603                 case OP_CMOV_LLT:
4604                 case OP_CMOV_LNE_UN:
4605                 case OP_CMOV_LGE_UN:
4606                 case OP_CMOV_LGT_UN:
4607                 case OP_CMOV_LLE_UN:
4608                 case OP_CMOV_LLT_UN:
4609                         g_assert (ins->dreg == ins->sreg1);
4610                         /* This needs to operate on 64 bit values */
4611                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4612                         break;
4613
4614                 case OP_LNOT:
4615                         amd64_not_reg (code, ins->sreg1);
4616                         break;
4617                 case OP_LNEG:
4618                         amd64_neg_reg (code, ins->sreg1);
4619                         break;
4620
4621                 case OP_ICONST:
4622                 case OP_I8CONST:
4623                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4624                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4625                         else
4626                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4627                         break;
4628                 case OP_AOTCONST:
4629                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4630                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4631                         break;
4632                 case OP_JUMP_TABLE:
4633                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4634                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4635                         break;
4636                 case OP_MOVE:
4637                         if (ins->dreg != ins->sreg1)
4638                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4639                         break;
4640                 case OP_AMD64_SET_XMMREG_R4: {
4641                         if (cfg->r4fp) {
4642                                 if (ins->dreg != ins->sreg1)
4643                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4644                         } else {
4645                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4646                         }
4647                         break;
4648                 }
4649                 case OP_AMD64_SET_XMMREG_R8: {
4650                         if (ins->dreg != ins->sreg1)
4651                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4652                         break;
4653                 }
4654                 case OP_TAILCALL: {
4655                         MonoCallInst *call = (MonoCallInst*)ins;
4656                         int i, save_area_offset;
4657
4658                         g_assert (!cfg->method->save_lmf);
4659
4660                         /* Restore callee saved registers */
4661                         save_area_offset = cfg->arch.reg_save_area_offset;
4662                         for (i = 0; i < AMD64_NREG; ++i)
4663                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4664                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4665                                         save_area_offset += 8;
4666                                 }
4667
4668                         if (cfg->arch.omit_fp) {
4669                                 if (cfg->arch.stack_alloc_size)
4670                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4671                                 // FIXME:
4672                                 if (call->stack_usage)
4673                                         NOT_IMPLEMENTED;
4674                         } else {
4675                                 /* Copy arguments on the stack to our argument area */
4676                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4677                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4678                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4679                                 }
4680
4681                                 amd64_leave (code);
4682                         }
4683
4684                         offset = code - cfg->native_code;
4685                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4686                         if (cfg->compile_aot)
4687                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4688                         else
4689                                 amd64_set_reg_template (code, AMD64_R11);
4690                         amd64_jump_reg (code, AMD64_R11);
4691                         ins->flags |= MONO_INST_GC_CALLSITE;
4692                         ins->backend.pc_offset = code - cfg->native_code;
4693                         break;
4694                 }
4695                 case OP_CHECK_THIS:
4696                         /* ensure ins->sreg1 is not NULL */
4697                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4698                         break;
4699                 case OP_ARGLIST: {
4700                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4701                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4702                         break;
4703                 }
4704                 case OP_CALL:
4705                 case OP_FCALL:
4706                 case OP_RCALL:
4707                 case OP_LCALL:
4708                 case OP_VCALL:
4709                 case OP_VCALL2:
4710                 case OP_VOIDCALL:
4711                         call = (MonoCallInst*)ins;
4712                         /*
4713                          * The AMD64 ABI forces callers to know about varargs.
4714                          */
4715                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4716                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4717                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4718                                 /*
4719                                  * Since the unmanaged calling convention doesn't contain a
4720                                  * 'vararg' entry, we have to treat every pinvoke call as a
4721                                  * potential vararg call.
4722                                  */
4723                                 guint32 nregs, i;
4724                                 nregs = 0;
4725                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4726                                         if (call->used_fregs & (1 << i))
4727                                                 nregs ++;
4728                                 if (!nregs)
4729                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4730                                 else
4731                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4732                         }
4733
4734                         if (ins->flags & MONO_INST_HAS_METHOD)
4735                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4736                         else
4737                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4738                         ins->flags |= MONO_INST_GC_CALLSITE;
4739                         ins->backend.pc_offset = code - cfg->native_code;
4740                         code = emit_move_return_value (cfg, ins, code);
4741                         break;
4742                 case OP_FCALL_REG:
4743                 case OP_RCALL_REG:
4744                 case OP_LCALL_REG:
4745                 case OP_VCALL_REG:
4746                 case OP_VCALL2_REG:
4747                 case OP_VOIDCALL_REG:
4748                 case OP_CALL_REG:
4749                         call = (MonoCallInst*)ins;
4750
4751                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4752                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4753                                 ins->sreg1 = AMD64_R11;
4754                         }
4755
4756                         /*
4757                          * The AMD64 ABI forces callers to know about varargs.
4758                          */
4759                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4760                                 if (ins->sreg1 == AMD64_RAX) {
4761                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4762                                         ins->sreg1 = AMD64_R11;
4763                                 }
4764                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4765                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4766                                 /*
4767                                  * Since the unmanaged calling convention doesn't contain a
4768                                  * 'vararg' entry, we have to treat every pinvoke call as a
4769                                  * potential vararg call.
4770                                  */
4771                                 guint32 nregs, i;
4772                                 nregs = 0;
4773                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4774                                         if (call->used_fregs & (1 << i))
4775                                                 nregs ++;
4776                                 if (ins->sreg1 == AMD64_RAX) {
4777                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4778                                         ins->sreg1 = AMD64_R11;
4779                                 }
4780                                 if (!nregs)
4781                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4782                                 else
4783                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4784                         }
4785
4786                         amd64_call_reg (code, ins->sreg1);
4787                         ins->flags |= MONO_INST_GC_CALLSITE;
4788                         ins->backend.pc_offset = code - cfg->native_code;
4789                         code = emit_move_return_value (cfg, ins, code);
4790                         break;
4791                 case OP_FCALL_MEMBASE:
4792                 case OP_RCALL_MEMBASE:
4793                 case OP_LCALL_MEMBASE:
4794                 case OP_VCALL_MEMBASE:
4795                 case OP_VCALL2_MEMBASE:
4796                 case OP_VOIDCALL_MEMBASE:
4797                 case OP_CALL_MEMBASE:
4798                         call = (MonoCallInst*)ins;
4799
4800                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4801                         ins->flags |= MONO_INST_GC_CALLSITE;
4802                         ins->backend.pc_offset = code - cfg->native_code;
4803                         code = emit_move_return_value (cfg, ins, code);
4804                         break;
4805                 case OP_DYN_CALL: {
4806                         int i;
4807                         MonoInst *var = cfg->dyn_call_var;
4808
4809                         g_assert (var->opcode == OP_REGOFFSET);
4810
4811                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4812                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4813                         /* r10 = ftn */
4814                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4815
4816                         /* Save args buffer */
4817                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4818
4819                         /* Set argument registers */
4820                         for (i = 0; i < PARAM_REGS; ++i)
4821                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4822
4823                         /* Make the call */
4824                         amd64_call_reg (code, AMD64_R10);
4825
4826                         ins->flags |= MONO_INST_GC_CALLSITE;
4827                         ins->backend.pc_offset = code - cfg->native_code;
4828
4829                         /* Save result */
4830                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4831                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4832                         break;
4833                 }
4834                 case OP_AMD64_SAVE_SP_TO_LMF: {
4835                         MonoInst *lmf_var = cfg->lmf_var;
4836                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4837                         break;
4838                 }
4839                 case OP_X86_PUSH:
4840                         g_assert_not_reached ();
4841                         amd64_push_reg (code, ins->sreg1);
4842                         break;
4843                 case OP_X86_PUSH_IMM:
4844                         g_assert_not_reached ();
4845                         g_assert (amd64_is_imm32 (ins->inst_imm));
4846                         amd64_push_imm (code, ins->inst_imm);
4847                         break;
4848                 case OP_X86_PUSH_MEMBASE:
4849                         g_assert_not_reached ();
4850                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4851                         break;
4852                 case OP_X86_PUSH_OBJ: {
4853                         int size = ALIGN_TO (ins->inst_imm, 8);
4854
4855                         g_assert_not_reached ();
4856
4857                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4858                         amd64_push_reg (code, AMD64_RDI);
4859                         amd64_push_reg (code, AMD64_RSI);
4860                         amd64_push_reg (code, AMD64_RCX);
4861                         if (ins->inst_offset)
4862                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4863                         else
4864                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4865                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4866                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4867                         amd64_cld (code);
4868                         amd64_prefix (code, X86_REP_PREFIX);
4869                         amd64_movsd (code);
4870                         amd64_pop_reg (code, AMD64_RCX);
4871                         amd64_pop_reg (code, AMD64_RSI);
4872                         amd64_pop_reg (code, AMD64_RDI);
4873                         break;
4874                 }
4875                 case OP_X86_LEA:
4876                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4877                         break;
4878                 case OP_X86_LEA_MEMBASE:
4879                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4880                         break;
4881                 case OP_X86_XCHG:
4882                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4883                         break;
4884                 case OP_LOCALLOC:
4885                         /* keep alignment */
4886                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4887                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4888                         code = mono_emit_stack_alloc (cfg, code, ins);
4889                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4890                         if (cfg->param_area)
4891                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4892                         break;
4893                 case OP_LOCALLOC_IMM: {
4894                         guint32 size = ins->inst_imm;
4895                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4896
4897                         if (ins->flags & MONO_INST_INIT) {
4898                                 if (size < 64) {
4899                                         int i;
4900
4901                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4902                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4903
4904                                         for (i = 0; i < size; i += 8)
4905                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4906                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4907                                 } else {
4908                                         amd64_mov_reg_imm (code, ins->dreg, size);
4909                                         ins->sreg1 = ins->dreg;
4910
4911                                         code = mono_emit_stack_alloc (cfg, code, ins);
4912                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4913                                 }
4914                         } else {
4915                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4916                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4917                         }
4918                         if (cfg->param_area)
4919                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4920                         break;
4921                 }
4922                 case OP_THROW: {
4923                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4924                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4925                                              (gpointer)"mono_arch_throw_exception", FALSE);
4926                         ins->flags |= MONO_INST_GC_CALLSITE;
4927                         ins->backend.pc_offset = code - cfg->native_code;
4928                         break;
4929                 }
4930                 case OP_RETHROW: {
4931                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4932                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4933                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4934                         ins->flags |= MONO_INST_GC_CALLSITE;
4935                         ins->backend.pc_offset = code - cfg->native_code;
4936                         break;
4937                 }
4938                 case OP_CALL_HANDLER:
4939                         /* Align stack */
4940                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4941                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4942                         amd64_call_imm (code, 0);
4943                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4944                         /* Restore stack alignment */
4945                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4946                         break;
4947                 case OP_START_HANDLER: {
4948                         /* Even though we're saving RSP, use sizeof */
4949                         /* gpointer because spvar is of type IntPtr */
4950                         /* see: mono_create_spvar_for_region */
4951                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4952                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4953
4954                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4955                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4956                                 cfg->param_area) {
4957                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4958                         }
4959                         break;
4960                 }
4961                 case OP_ENDFINALLY: {
4962                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4963                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4964                         amd64_ret (code);
4965                         break;
4966                 }
4967                 case OP_ENDFILTER: {
4968                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4969                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4970                         /* The local allocator will put the result into RAX */
4971                         amd64_ret (code);
4972                         break;
4973                 }
4974
4975                 case OP_LABEL:
4976                         ins->inst_c0 = code - cfg->native_code;
4977                         break;
4978                 case OP_BR:
4979                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4980                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4981                         //break;
4982                                 if (ins->inst_target_bb->native_offset) {
4983                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4984                                 } else {
4985                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4986                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4987                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4988                                                 x86_jump8 (code, 0);
4989                                         else
4990                                                 x86_jump32 (code, 0);
4991                         }
4992                         break;
4993                 case OP_BR_REG:
4994                         amd64_jump_reg (code, ins->sreg1);
4995                         break;
4996                 case OP_ICNEQ:
4997                 case OP_ICGE:
4998                 case OP_ICLE:
4999                 case OP_ICGE_UN:
5000                 case OP_ICLE_UN:
5001
5002                 case OP_CEQ:
5003                 case OP_LCEQ:
5004                 case OP_ICEQ:
5005                 case OP_CLT:
5006                 case OP_LCLT:
5007                 case OP_ICLT:
5008                 case OP_CGT:
5009                 case OP_ICGT:
5010                 case OP_LCGT:
5011                 case OP_CLT_UN:
5012                 case OP_LCLT_UN:
5013                 case OP_ICLT_UN:
5014                 case OP_CGT_UN:
5015                 case OP_LCGT_UN:
5016                 case OP_ICGT_UN:
5017                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5018                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5019                         break;
5020                 case OP_COND_EXC_EQ:
5021                 case OP_COND_EXC_NE_UN:
5022                 case OP_COND_EXC_LT:
5023                 case OP_COND_EXC_LT_UN:
5024                 case OP_COND_EXC_GT:
5025                 case OP_COND_EXC_GT_UN:
5026                 case OP_COND_EXC_GE:
5027                 case OP_COND_EXC_GE_UN:
5028                 case OP_COND_EXC_LE:
5029                 case OP_COND_EXC_LE_UN:
5030                 case OP_COND_EXC_IEQ:
5031                 case OP_COND_EXC_INE_UN:
5032                 case OP_COND_EXC_ILT:
5033                 case OP_COND_EXC_ILT_UN:
5034                 case OP_COND_EXC_IGT:
5035                 case OP_COND_EXC_IGT_UN:
5036                 case OP_COND_EXC_IGE:
5037                 case OP_COND_EXC_IGE_UN:
5038                 case OP_COND_EXC_ILE:
5039                 case OP_COND_EXC_ILE_UN:
5040                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5041                         break;
5042                 case OP_COND_EXC_OV:
5043                 case OP_COND_EXC_NO:
5044                 case OP_COND_EXC_C:
5045                 case OP_COND_EXC_NC:
5046                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5047                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5048                         break;
5049                 case OP_COND_EXC_IOV:
5050                 case OP_COND_EXC_INO:
5051                 case OP_COND_EXC_IC:
5052                 case OP_COND_EXC_INC:
5053                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5054                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5055                         break;
5056
5057                 /* floating point opcodes */
5058                 case OP_R8CONST: {
5059                         double d = *(double *)ins->inst_p0;
5060
5061                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5062                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5063                         }
5064                         else {
5065                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5066                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5067                         }
5068                         break;
5069                 }
5070                 case OP_R4CONST: {
5071                         float f = *(float *)ins->inst_p0;
5072
5073                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5074                                 if (cfg->r4fp)
5075                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5076                                 else
5077                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5078                         }
5079                         else {
5080                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5081                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5082                                 if (!cfg->r4fp)
5083                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5084                         }
5085                         break;
5086                 }
5087                 case OP_STORER8_MEMBASE_REG:
5088                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5089                         break;
5090                 case OP_LOADR8_MEMBASE:
5091                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5092                         break;
5093                 case OP_STORER4_MEMBASE_REG:
5094                         if (cfg->r4fp) {
5095                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5096                         } else {
5097                                 /* This requires a double->single conversion */
5098                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5099                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5100                         }
5101                         break;
5102                 case OP_LOADR4_MEMBASE:
5103                         if (cfg->r4fp) {
5104                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5105                         } else {
5106                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5107                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5108                         }
5109                         break;
5110                 case OP_ICONV_TO_R4:
5111                         if (cfg->r4fp) {
5112                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113                         } else {
5114                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5115                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5116                         }
5117                         break;
5118                 case OP_ICONV_TO_R8:
5119                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5120                         break;
5121                 case OP_LCONV_TO_R4:
5122                         if (cfg->r4fp) {
5123                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5124                         } else {
5125                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5126                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5127                         }
5128                         break;
5129                 case OP_LCONV_TO_R8:
5130                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5131                         break;
5132                 case OP_FCONV_TO_R4:
5133                         if (cfg->r4fp) {
5134                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5135                         } else {
5136                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5137                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5138                         }
5139                         break;
5140                 case OP_FCONV_TO_I1:
5141                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5142                         break;
5143                 case OP_FCONV_TO_U1:
5144                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5145                         break;
5146                 case OP_FCONV_TO_I2:
5147                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5148                         break;
5149                 case OP_FCONV_TO_U2:
5150                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5151                         break;
5152                 case OP_FCONV_TO_U4:
5153                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5154                         break;
5155                 case OP_FCONV_TO_I4:
5156                 case OP_FCONV_TO_I:
5157                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5158                         break;
5159                 case OP_FCONV_TO_I8:
5160                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5161                         break;
5162
5163                 case OP_RCONV_TO_I1:
5164                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5165                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5166                         break;
5167                 case OP_RCONV_TO_U1:
5168                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5169                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5170                         break;
5171                 case OP_RCONV_TO_I2:
5172                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5173                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5174                         break;
5175                 case OP_RCONV_TO_U2:
5176                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5177                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5178                         break;
5179                 case OP_RCONV_TO_I4:
5180                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5181                         break;
5182                 case OP_RCONV_TO_U4:
5183                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5184                         break;
5185                 case OP_RCONV_TO_I8:
5186                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5187                         break;
5188                 case OP_RCONV_TO_R8:
5189                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5190                         break;
5191                 case OP_RCONV_TO_R4:
5192                         if (ins->dreg != ins->sreg1)
5193                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5194                         break;
5195
5196                 case OP_LCONV_TO_R_UN: {
5197                         guint8 *br [2];
5198
5199                         /* Based on gcc code */
5200                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5201                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5202
5203                         /* Positive case */
5204                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5205                         br [1] = code; x86_jump8 (code, 0);
5206                         amd64_patch (br [0], code);
5207
5208                         /* Negative case */
5209                         /* Save to the red zone */
5210                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5211                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5212                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5213                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5214                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5215                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5216                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5217                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5218                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5219                         /* Restore */
5220                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5221                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5222                         amd64_patch (br [1], code);
5223                         break;
5224                 }
5225                 case OP_LCONV_TO_OVF_U4:
5226                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5227                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5228                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5229                         break;
5230                 case OP_LCONV_TO_OVF_I4_UN:
5231                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5232                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5233                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5234                         break;
5235                 case OP_FMOVE:
5236                         if (ins->dreg != ins->sreg1)
5237                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5238                         break;
5239                 case OP_RMOVE:
5240                         if (ins->dreg != ins->sreg1)
5241                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5242                         break;
5243                 case OP_MOVE_F_TO_I4:
5244                         if (cfg->r4fp) {
5245                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5246                         } else {
5247                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5248                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5249                         }
5250                         break;
5251                 case OP_MOVE_I4_TO_F:
5252                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5253                         if (!cfg->r4fp)
5254                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5255                         break;
5256                 case OP_MOVE_F_TO_I8:
5257                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5258                         break;
5259                 case OP_MOVE_I8_TO_F:
5260                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5261                         break;
5262                 case OP_FADD:
5263                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5264                         break;
5265                 case OP_FSUB:
5266                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5267                         break;
5268                 case OP_FMUL:
5269                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5270                         break;
5271                 case OP_FDIV:
5272                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5273                         break;
5274                 case OP_FNEG: {
5275                         static double r8_0 = -0.0;
5276
5277                         g_assert (ins->sreg1 == ins->dreg);
5278
5279                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5280                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5281                         break;
5282                 }
5283                 case OP_SIN:
5284                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5285                         break;
5286                 case OP_COS:
5287                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5288                         break;
5289                 case OP_ABS: {
5290                         static guint64 d = 0x7fffffffffffffffUL;
5291
5292                         g_assert (ins->sreg1 == ins->dreg);
5293
5294                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5295                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5296                         break;
5297                 }
5298                 case OP_SQRT:
5299                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5300                         break;
5301
5302                 case OP_RADD:
5303                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5304                         break;
5305                 case OP_RSUB:
5306                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5307                         break;
5308                 case OP_RMUL:
5309                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5310                         break;
5311                 case OP_RDIV:
5312                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5313                         break;
5314                 case OP_RNEG: {
5315                         static float r4_0 = -0.0;
5316
5317                         g_assert (ins->sreg1 == ins->dreg);
5318
5319                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5320                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5321                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5322                         break;
5323                 }
5324
5325                 case OP_IMIN:
5326                         g_assert (cfg->opt & MONO_OPT_CMOV);
5327                         g_assert (ins->dreg == ins->sreg1);
5328                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5329                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5330                         break;
5331                 case OP_IMIN_UN:
5332                         g_assert (cfg->opt & MONO_OPT_CMOV);
5333                         g_assert (ins->dreg == ins->sreg1);
5334                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5335                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5336                         break;
5337                 case OP_IMAX:
5338                         g_assert (cfg->opt & MONO_OPT_CMOV);
5339                         g_assert (ins->dreg == ins->sreg1);
5340                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5341                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5342                         break;
5343                 case OP_IMAX_UN:
5344                         g_assert (cfg->opt & MONO_OPT_CMOV);
5345                         g_assert (ins->dreg == ins->sreg1);
5346                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5347                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5348                         break;
5349                 case OP_LMIN:
5350                         g_assert (cfg->opt & MONO_OPT_CMOV);
5351                         g_assert (ins->dreg == ins->sreg1);
5352                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5353                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5354                         break;
5355                 case OP_LMIN_UN:
5356                         g_assert (cfg->opt & MONO_OPT_CMOV);
5357                         g_assert (ins->dreg == ins->sreg1);
5358                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5359                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5360                         break;
5361                 case OP_LMAX:
5362                         g_assert (cfg->opt & MONO_OPT_CMOV);
5363                         g_assert (ins->dreg == ins->sreg1);
5364                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5365                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5366                         break;
5367                 case OP_LMAX_UN:
5368                         g_assert (cfg->opt & MONO_OPT_CMOV);
5369                         g_assert (ins->dreg == ins->sreg1);
5370                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5371                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5372                         break;
5373                 case OP_X86_FPOP:
5374                         break;
5375                 case OP_FCOMPARE:
5376                         /*
5377                          * The two arguments are swapped because the fbranch instructions
5378                          * depend on this for the non-sse case to work.
5379                          */
5380                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5381                         break;
5382                 case OP_RCOMPARE:
5383                         /*
5384                          * FIXME: Get rid of this.
5385                          * The two arguments are swapped because the fbranch instructions
5386                          * depend on this for the non-sse case to work.
5387                          */
5388                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5389                         break;
5390                 case OP_FCNEQ:
5391                 case OP_FCEQ: {
5392                         /* zeroing the register at the start results in
5393                          * shorter and faster code (we can also remove the widening op)
5394                          */
5395                         guchar *unordered_check;
5396
5397                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5398                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5399                         unordered_check = code;
5400                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5401
5402                         if (ins->opcode == OP_FCEQ) {
5403                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5404                                 amd64_patch (unordered_check, code);
5405                         } else {
5406                                 guchar *jump_to_end;
5407                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5408                                 jump_to_end = code;
5409                                 x86_jump8 (code, 0);
5410                                 amd64_patch (unordered_check, code);
5411                                 amd64_inc_reg (code, ins->dreg);
5412                                 amd64_patch (jump_to_end, code);
5413                         }
5414                         break;
5415                 }
5416                 case OP_FCLT:
5417                 case OP_FCLT_UN: {
5418                         /* zeroing the register at the start results in
5419                          * shorter and faster code (we can also remove the widening op)
5420                          */
5421                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5422                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5423                         if (ins->opcode == OP_FCLT_UN) {
5424                                 guchar *unordered_check = code;
5425                                 guchar *jump_to_end;
5426                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5427                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5428                                 jump_to_end = code;
5429                                 x86_jump8 (code, 0);
5430                                 amd64_patch (unordered_check, code);
5431                                 amd64_inc_reg (code, ins->dreg);
5432                                 amd64_patch (jump_to_end, code);
5433                         } else {
5434                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5435                         }
5436                         break;
5437                 }
5438                 case OP_FCLE: {
5439                         guchar *unordered_check;
5440                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5441                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5442                         unordered_check = code;
5443                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5444                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5445                         amd64_patch (unordered_check, code);
5446                         break;
5447                 }
5448                 case OP_FCGT:
5449                 case OP_FCGT_UN: {
5450                         /* zeroing the register at the start results in
5451                          * shorter and faster code (we can also remove the widening op)
5452                          */
5453                         guchar *unordered_check;
5454
5455                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5456                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5457                         if (ins->opcode == OP_FCGT) {
5458                                 unordered_check = code;
5459                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5460                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5461                                 amd64_patch (unordered_check, code);
5462                         } else {
5463                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5464                         }
5465                         break;
5466                 }
5467                 case OP_FCGE: {
5468                         guchar *unordered_check;
5469                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5470                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5471                         unordered_check = code;
5472                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5473                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5474                         amd64_patch (unordered_check, code);
5475                         break;
5476                 }
5477
5478                 case OP_RCEQ:
5479                 case OP_RCGT:
5480                 case OP_RCLT:
5481                 case OP_RCLT_UN:
5482                 case OP_RCGT_UN: {
5483                         int x86_cond;
5484                         gboolean unordered = FALSE;
5485
5486                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5487                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5488
5489                         switch (ins->opcode) {
5490                         case OP_RCEQ:
5491                                 x86_cond = X86_CC_EQ;
5492                                 break;
5493                         case OP_RCGT:
5494                                 x86_cond = X86_CC_LT;
5495                                 break;
5496                         case OP_RCLT:
5497                                 x86_cond = X86_CC_GT;
5498                                 break;
5499                         case OP_RCLT_UN:
5500                                 x86_cond = X86_CC_GT;
5501                                 unordered = TRUE;
5502                                 break;
5503                         case OP_RCGT_UN:
5504                                 x86_cond = X86_CC_LT;
5505                                 unordered = TRUE;
5506                                 break;
5507                         default:
5508                                 g_assert_not_reached ();
5509                                 break;
5510                         }
5511
5512                         if (unordered) {
5513                                 guchar *unordered_check;
5514                                 guchar *jump_to_end;
5515
5516                                 unordered_check = code;
5517                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5518                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5519                                 jump_to_end = code;
5520                                 x86_jump8 (code, 0);
5521                                 amd64_patch (unordered_check, code);
5522                                 amd64_inc_reg (code, ins->dreg);
5523                                 amd64_patch (jump_to_end, code);
5524                         } else {
5525                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5526                         }
5527                         break;
5528                 }
5529                 case OP_FCLT_MEMBASE:
5530                 case OP_FCGT_MEMBASE:
5531                 case OP_FCLT_UN_MEMBASE:
5532                 case OP_FCGT_UN_MEMBASE:
5533                 case OP_FCEQ_MEMBASE: {
5534                         guchar *unordered_check, *jump_to_end;
5535                         int x86_cond;
5536
5537                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5538                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5539
5540                         switch (ins->opcode) {
5541                         case OP_FCEQ_MEMBASE:
5542                                 x86_cond = X86_CC_EQ;
5543                                 break;
5544                         case OP_FCLT_MEMBASE:
5545                         case OP_FCLT_UN_MEMBASE:
5546                                 x86_cond = X86_CC_LT;
5547                                 break;
5548                         case OP_FCGT_MEMBASE:
5549                         case OP_FCGT_UN_MEMBASE:
5550                                 x86_cond = X86_CC_GT;
5551                                 break;
5552                         default:
5553                                 g_assert_not_reached ();
5554                         }
5555
5556                         unordered_check = code;
5557                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5558                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5559
5560                         switch (ins->opcode) {
5561                         case OP_FCEQ_MEMBASE:
5562                         case OP_FCLT_MEMBASE:
5563                         case OP_FCGT_MEMBASE:
5564                                 amd64_patch (unordered_check, code);
5565                                 break;
5566                         case OP_FCLT_UN_MEMBASE:
5567                         case OP_FCGT_UN_MEMBASE:
5568                                 jump_to_end = code;
5569                                 x86_jump8 (code, 0);
5570                                 amd64_patch (unordered_check, code);
5571                                 amd64_inc_reg (code, ins->dreg);
5572                                 amd64_patch (jump_to_end, code);
5573                                 break;
5574                         default:
5575                                 break;
5576                         }
5577                         break;
5578                 }
5579                 case OP_FBEQ: {
5580                         guchar *jump = code;
5581                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5582                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5583                         amd64_patch (jump, code);
5584                         break;
5585                 }
5586                 case OP_FBNE_UN:
5587                         /* Branch if C013 != 100 */
5588                         /* branch if !ZF or (PF|CF) */
5589                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5590                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5591                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5592                         break;
5593                 case OP_FBLT:
5594                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5595                         break;
5596                 case OP_FBLT_UN:
5597                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5598                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5599                         break;
5600                 case OP_FBGT:
5601                 case OP_FBGT_UN:
5602                         if (ins->opcode == OP_FBGT) {
5603                                 guchar *br1;
5604
5605                                 /* skip branch if C1=1 */
5606                                 br1 = code;
5607                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5608                                 /* branch if (C0 | C3) = 1 */
5609                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5610                                 amd64_patch (br1, code);
5611                                 break;
5612                         } else {
5613                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5614                         }
5615                         break;
5616                 case OP_FBGE: {
5617                         /* Branch if C013 == 100 or 001 */
5618                         guchar *br1;
5619
5620                         /* skip branch if C1=1 */
5621                         br1 = code;
5622                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5623                         /* branch if (C0 | C3) = 1 */
5624                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5625                         amd64_patch (br1, code);
5626                         break;
5627                 }
5628                 case OP_FBGE_UN:
5629                         /* Branch if C013 == 000 */
5630                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5631                         break;
5632                 case OP_FBLE: {
5633                         /* Branch if C013=000 or 100 */
5634                         guchar *br1;
5635
5636                         /* skip branch if C1=1 */
5637                         br1 = code;
5638                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5639                         /* branch if C0=0 */
5640                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5641                         amd64_patch (br1, code);
5642                         break;
5643                 }
5644                 case OP_FBLE_UN:
5645                         /* Branch if C013 != 001 */
5646                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5647                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5648                         break;
5649                 case OP_CKFINITE:
5650                         /* Transfer value to the fp stack */
5651                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5652                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5653                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5654
5655                         amd64_push_reg (code, AMD64_RAX);
5656                         amd64_fxam (code);
5657                         amd64_fnstsw (code);
5658                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5659                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5660                         amd64_pop_reg (code, AMD64_RAX);
5661                         amd64_fstp (code, 0);
5662                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5663                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5664                         break;
5665                 case OP_TLS_GET: {
5666                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5667                         break;
5668                 }
5669                 case OP_TLS_GET_REG:
5670                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5671                         break;
5672                 case OP_TLS_SET: {
5673                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5674                         break;
5675                 }
5676                 case OP_TLS_SET_REG: {
5677                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5678                         break;
5679                 }
5680                 case OP_MEMORY_BARRIER: {
5681                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5682                                 x86_mfence (code);
5683                         break;
5684                 }
5685                 case OP_ATOMIC_ADD_I4:
5686                 case OP_ATOMIC_ADD_I8: {
5687                         int dreg = ins->dreg;
5688                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5689
5690                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5691                                 dreg = AMD64_R11;
5692
5693                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5694                         amd64_prefix (code, X86_LOCK_PREFIX);
5695                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5696                         /* dreg contains the old value, add with sreg2 value */
5697                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5698
5699                         if (ins->dreg != dreg)
5700                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5701
5702                         break;
5703                 }
5704                 case OP_ATOMIC_EXCHANGE_I4:
5705                 case OP_ATOMIC_EXCHANGE_I8: {
5706                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5707
5708                         /* LOCK prefix is implied. */
5709                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5710                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5711                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5712                         break;
5713                 }
5714                 case OP_ATOMIC_CAS_I4:
5715                 case OP_ATOMIC_CAS_I8: {
5716                         guint32 size;
5717
5718                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5719                                 size = 8;
5720                         else
5721                                 size = 4;
5722
5723                         /*
5724                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5725                          * an explanation of how this works.
5726                          */
5727                         g_assert (ins->sreg3 == AMD64_RAX);
5728                         g_assert (ins->sreg1 != AMD64_RAX);
5729                         g_assert (ins->sreg1 != ins->sreg2);
5730
5731                         amd64_prefix (code, X86_LOCK_PREFIX);
5732                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5733
5734                         if (ins->dreg != AMD64_RAX)
5735                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5736                         break;
5737                 }
5738                 case OP_ATOMIC_LOAD_I1: {
5739                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5740                         break;
5741                 }
5742                 case OP_ATOMIC_LOAD_U1: {
5743                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5744                         break;
5745                 }
5746                 case OP_ATOMIC_LOAD_I2: {
5747                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5748                         break;
5749                 }
5750                 case OP_ATOMIC_LOAD_U2: {
5751                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5752                         break;
5753                 }
5754                 case OP_ATOMIC_LOAD_I4: {
5755                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5756                         break;
5757                 }
5758                 case OP_ATOMIC_LOAD_U4:
5759                 case OP_ATOMIC_LOAD_I8:
5760                 case OP_ATOMIC_LOAD_U8: {
5761                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5762                         break;
5763                 }
5764                 case OP_ATOMIC_LOAD_R4: {
5765                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5766                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5767                         break;
5768                 }
5769                 case OP_ATOMIC_LOAD_R8: {
5770                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5771                         break;
5772                 }
5773                 case OP_ATOMIC_STORE_I1:
5774                 case OP_ATOMIC_STORE_U1:
5775                 case OP_ATOMIC_STORE_I2:
5776                 case OP_ATOMIC_STORE_U2:
5777                 case OP_ATOMIC_STORE_I4:
5778                 case OP_ATOMIC_STORE_U4:
5779                 case OP_ATOMIC_STORE_I8:
5780                 case OP_ATOMIC_STORE_U8: {
5781                         int size;
5782
5783                         switch (ins->opcode) {
5784                         case OP_ATOMIC_STORE_I1:
5785                         case OP_ATOMIC_STORE_U1:
5786                                 size = 1;
5787                                 break;
5788                         case OP_ATOMIC_STORE_I2:
5789                         case OP_ATOMIC_STORE_U2:
5790                                 size = 2;
5791                                 break;
5792                         case OP_ATOMIC_STORE_I4:
5793                         case OP_ATOMIC_STORE_U4:
5794                                 size = 4;
5795                                 break;
5796                         case OP_ATOMIC_STORE_I8:
5797                         case OP_ATOMIC_STORE_U8:
5798                                 size = 8;
5799                                 break;
5800                         }
5801
5802                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5803
5804                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5805                                 x86_mfence (code);
5806                         break;
5807                 }
5808                 case OP_ATOMIC_STORE_R4: {
5809                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5810                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5811
5812                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5813                                 x86_mfence (code);
5814                         break;
5815                 }
5816                 case OP_ATOMIC_STORE_R8: {
5817                         x86_nop (code);
5818                         x86_nop (code);
5819                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5820                         x86_nop (code);
5821                         x86_nop (code);
5822
5823                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5824                                 x86_mfence (code);
5825                         break;
5826                 }
5827                 case OP_CARD_TABLE_WBARRIER: {
5828                         int ptr = ins->sreg1;
5829                         int value = ins->sreg2;
5830                         guchar *br = 0;
5831                         int nursery_shift, card_table_shift;
5832                         gpointer card_table_mask;
5833                         size_t nursery_size;
5834
5835                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5836                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5837                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5838
5839                         /*If either point to the stack we can simply avoid the WB. This happens due to
5840                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5841                          */
5842                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5843                                 continue;
5844
5845                         /*
5846                          * We need one register we can clobber, we choose EDX and make sreg1
5847                          * fixed EAX to work around limitations in the local register allocator.
5848                          * sreg2 might get allocated to EDX, but that is not a problem since
5849                          * we use it before clobbering EDX.
5850                          */
5851                         g_assert (ins->sreg1 == AMD64_RAX);
5852
5853                         /*
5854                          * This is the code we produce:
5855                          *
5856                          *   edx = value
5857                          *   edx >>= nursery_shift
5858                          *   cmp edx, (nursery_start >> nursery_shift)
5859                          *   jne done
5860                          *   edx = ptr
5861                          *   edx >>= card_table_shift
5862                          *   edx += cardtable
5863                          *   [edx] = 1
5864                          * done:
5865                          */
5866
5867                         if (mono_gc_card_table_nursery_check ()) {
5868                                 if (value != AMD64_RDX)
5869                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5870                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5871                                 if (shifted_nursery_start >> 31) {
5872                                         /*
5873                                          * The value we need to compare against is 64 bits, so we need
5874                                          * another spare register.  We use RBX, which we save and
5875                                          * restore.
5876                                          */
5877                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5878                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5879                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5880                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5881                                 } else {
5882                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5883                                 }
5884                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5885                         }
5886                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5887                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5888                         if (card_table_mask)
5889                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5890
5891                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5892                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5893
5894                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5895
5896                         if (mono_gc_card_table_nursery_check ())
5897                                 x86_patch (br, code);
5898                         break;
5899                 }
5900 #ifdef MONO_ARCH_SIMD_INTRINSICS
5901                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5902                 case OP_ADDPS:
5903                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_DIVPS:
5906                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5907                         break;
5908                 case OP_MULPS:
5909                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5910                         break;
5911                 case OP_SUBPS:
5912                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_MAXPS:
5915                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_MINPS:
5918                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_COMPPS:
5921                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5922                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5923                         break;
5924                 case OP_ANDPS:
5925                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_ANDNPS:
5928                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5929                         break;
5930                 case OP_ORPS:
5931                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_XORPS:
5934                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_SQRTPS:
5937                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5938                         break;
5939                 case OP_RSQRTPS:
5940                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5941                         break;
5942                 case OP_RCPPS:
5943                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5944                         break;
5945                 case OP_ADDSUBPS:
5946                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_HADDPS:
5949                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_HSUBPS:
5952                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_DUPPS_HIGH:
5955                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5956                         break;
5957                 case OP_DUPPS_LOW:
5958                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5959                         break;
5960
5961                 case OP_PSHUFLEW_HIGH:
5962                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5963                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5964                         break;
5965                 case OP_PSHUFLEW_LOW:
5966                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5967                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5968                         break;
5969                 case OP_PSHUFLED:
5970                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5971                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5972                         break;
5973                 case OP_SHUFPS:
5974                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5975                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5976                         break;
5977                 case OP_SHUFPD:
5978                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5979                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5980                         break;
5981
5982                 case OP_ADDPD:
5983                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_DIVPD:
5986                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_MULPD:
5989                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_SUBPD:
5992                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_MAXPD:
5995                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_MINPD:
5998                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_COMPPD:
6001                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6002                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6003                         break;
6004                 case OP_ANDPD:
6005                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_ANDNPD:
6008                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010                 case OP_ORPD:
6011                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013                 case OP_XORPD:
6014                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016                 case OP_SQRTPD:
6017                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6018                         break;
6019                 case OP_ADDSUBPD:
6020                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_HADDPD:
6023                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_HSUBPD:
6026                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_DUPPD:
6029                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6030                         break;
6031
6032                 case OP_EXTRACT_MASK:
6033                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6034                         break;
6035
6036                 case OP_PAND:
6037                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6038                         break;
6039                 case OP_POR:
6040                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6041                         break;
6042                 case OP_PXOR:
6043                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045
6046                 case OP_PADDB:
6047                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_PADDW:
6050                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_PADDD:
6053                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_PADDQ:
6056                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058
6059                 case OP_PSUBB:
6060                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PSUBW:
6063                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_PSUBD:
6066                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_PSUBQ:
6069                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071
6072                 case OP_PMAXB_UN:
6073                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075                 case OP_PMAXW_UN:
6076                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078                 case OP_PMAXD_UN:
6079                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081
6082                 case OP_PMAXB:
6083                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085                 case OP_PMAXW:
6086                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PMAXD:
6089                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091
6092                 case OP_PAVGB_UN:
6093                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PAVGW_UN:
6096                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098
6099                 case OP_PMINB_UN:
6100                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PMINW_UN:
6103                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMIND_UN:
6106                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108
6109                 case OP_PMINB:
6110                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMINW:
6113                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PMIND:
6116                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118
6119                 case OP_PCMPEQB:
6120                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_PCMPEQW:
6123                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_PCMPEQD:
6126                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PCMPEQQ:
6129                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131
6132                 case OP_PCMPGTB:
6133                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_PCMPGTW:
6136                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_PCMPGTD:
6139                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_PCMPGTQ:
6142                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144
6145                 case OP_PSUM_ABS_DIFF:
6146                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148
6149                 case OP_UNPACK_LOWB:
6150                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152                 case OP_UNPACK_LOWW:
6153                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155                 case OP_UNPACK_LOWD:
6156                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158                 case OP_UNPACK_LOWQ:
6159                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_UNPACK_LOWPS:
6162                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_LOWPD:
6165                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167
6168                 case OP_UNPACK_HIGHB:
6169                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171                 case OP_UNPACK_HIGHW:
6172                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174                 case OP_UNPACK_HIGHD:
6175                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6176                         break;
6177                 case OP_UNPACK_HIGHQ:
6178                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_UNPACK_HIGHPS:
6181                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_UNPACK_HIGHPD:
6184                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186
6187                 case OP_PACKW:
6188                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6189                         break;
6190                 case OP_PACKD:
6191                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6192                         break;
6193                 case OP_PACKW_UN:
6194                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_PACKD_UN:
6197                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199
6200                 case OP_PADDB_SAT_UN:
6201                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203                 case OP_PSUBB_SAT_UN:
6204                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6205                         break;
6206                 case OP_PADDW_SAT_UN:
6207                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209                 case OP_PSUBW_SAT_UN:
6210                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212
6213                 case OP_PADDB_SAT:
6214                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216                 case OP_PSUBB_SAT:
6217                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6218                         break;
6219                 case OP_PADDW_SAT:
6220                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_PSUBW_SAT:
6223                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225
6226                 case OP_PMULW:
6227                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6228                         break;
6229                 case OP_PMULD:
6230                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6231                         break;
6232                 case OP_PMULQ:
6233                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6234                         break;
6235                 case OP_PMULW_HIGH_UN:
6236                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6237                         break;
6238                 case OP_PMULW_HIGH:
6239                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6240                         break;
6241
6242                 case OP_PSHRW:
6243                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6244                         break;
6245                 case OP_PSHRW_REG:
6246                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6247                         break;
6248
6249                 case OP_PSARW:
6250                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6251                         break;
6252                 case OP_PSARW_REG:
6253                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6254                         break;
6255
6256                 case OP_PSHLW:
6257                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6258                         break;
6259                 case OP_PSHLW_REG:
6260                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6261                         break;
6262
6263                 case OP_PSHRD:
6264                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6265                         break;
6266                 case OP_PSHRD_REG:
6267                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6268                         break;
6269
6270                 case OP_PSARD:
6271                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6272                         break;
6273                 case OP_PSARD_REG:
6274                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6275                         break;
6276
6277                 case OP_PSHLD:
6278                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSHLD_REG:
6281                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283
6284                 case OP_PSHRQ:
6285                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6286                         break;
6287                 case OP_PSHRQ_REG:
6288                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6289                         break;
6290
6291                 /*TODO: This is appart of the sse spec but not added
6292                 case OP_PSARQ:
6293                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6294                         break;
6295                 case OP_PSARQ_REG:
6296                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6297                         break;
6298                 */
6299
6300                 case OP_PSHLQ:
6301                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6302                         break;
6303                 case OP_PSHLQ_REG:
6304                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6305                         break;
6306                 case OP_CVTDQ2PD:
6307                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6308                         break;
6309                 case OP_CVTDQ2PS:
6310                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6311                         break;
6312                 case OP_CVTPD2DQ:
6313                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6314                         break;
6315                 case OP_CVTPD2PS:
6316                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6317                         break;
6318                 case OP_CVTPS2DQ:
6319                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6320                         break;
6321                 case OP_CVTPS2PD:
6322                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6323                         break;
6324                 case OP_CVTTPD2DQ:
6325                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6326                         break;
6327                 case OP_CVTTPS2DQ:
6328                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6329                         break;
6330
6331                 case OP_ICONV_TO_X:
6332                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6333                         break;
6334                 case OP_EXTRACT_I4:
6335                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6336                         break;
6337                 case OP_EXTRACT_I8:
6338                         if (ins->inst_c0) {
6339                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6340                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6341                         } else {
6342                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6343                         }
6344                         break;
6345                 case OP_EXTRACT_I1:
6346                 case OP_EXTRACT_U1:
6347                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6348                         if (ins->inst_c0)
6349                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6350                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6351                         break;
6352                 case OP_EXTRACT_I2:
6353                 case OP_EXTRACT_U2:
6354                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6355                         if (ins->inst_c0)
6356                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6357                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6358                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6359                         break;
6360                 case OP_EXTRACT_R8:
6361                         if (ins->inst_c0)
6362                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6363                         else
6364                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6365                         break;
6366                 case OP_INSERT_I2:
6367                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6368                         break;
6369                 case OP_EXTRACTX_U2:
6370                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6371                         break;
6372                 case OP_INSERTX_U1_SLOW:
6373                         /*sreg1 is the extracted ireg (scratch)
6374                         /sreg2 is the to be inserted ireg (scratch)
6375                         /dreg is the xreg to receive the value*/
6376
6377                         /*clear the bits from the extracted word*/
6378                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6379                         /*shift the value to insert if needed*/
6380                         if (ins->inst_c0 & 1)
6381                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6382                         /*join them together*/
6383                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6384                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6385                         break;
6386                 case OP_INSERTX_I4_SLOW:
6387                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6388                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6389                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6390                         break;
6391                 case OP_INSERTX_I8_SLOW:
6392                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6393                         if (ins->inst_c0)
6394                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6395                         else
6396                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6397                         break;
6398
6399                 case OP_INSERTX_R4_SLOW:
6400                         switch (ins->inst_c0) {
6401                         case 0:
6402                                 if (cfg->r4fp)
6403                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6404                                 else
6405                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406                                 break;
6407                         case 1:
6408                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6409                                 if (cfg->r4fp)
6410                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6411                                 else
6412                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6413                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6414                                 break;
6415                         case 2:
6416                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6417                                 if (cfg->r4fp)
6418                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6419                                 else
6420                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6421                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6422                                 break;
6423                         case 3:
6424                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6425                                 if (cfg->r4fp)
6426                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6427                                 else
6428                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6429                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6430                                 break;
6431                         }
6432                         break;
6433                 case OP_INSERTX_R8_SLOW:
6434                         if (ins->inst_c0)
6435                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6436                         else
6437                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6438                         break;
6439                 case OP_STOREX_MEMBASE_REG:
6440                 case OP_STOREX_MEMBASE:
6441                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6442                         break;
6443                 case OP_LOADX_MEMBASE:
6444                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6445                         break;
6446                 case OP_LOADX_ALIGNED_MEMBASE:
6447                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6448                         break;
6449                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6450                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6451                         break;
6452                 case OP_STOREX_NTA_MEMBASE_REG:
6453                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6454                         break;
6455                 case OP_PREFETCH_MEMBASE:
6456                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6457                         break;
6458
6459                 case OP_XMOVE:
6460                         /*FIXME the peephole pass should have killed this*/
6461                         if (ins->dreg != ins->sreg1)
6462                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6463                         break;
6464                 case OP_XZERO:
6465                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6466                         break;
6467                 case OP_ICONV_TO_R4_RAW:
6468                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6469                         break;
6470
6471                 case OP_FCONV_TO_R8_X:
6472                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6473                         break;
6474
6475                 case OP_XCONV_R8_TO_I4:
6476                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6477                         switch (ins->backend.source_opcode) {
6478                         case OP_FCONV_TO_I1:
6479                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6480                                 break;
6481                         case OP_FCONV_TO_U1:
6482                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6483                                 break;
6484                         case OP_FCONV_TO_I2:
6485                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6486                                 break;
6487                         case OP_FCONV_TO_U2:
6488                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6489                                 break;
6490                         }
6491                         break;
6492
6493                 case OP_EXPAND_I2:
6494                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6495                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6496                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6497                         break;
6498                 case OP_EXPAND_I4:
6499                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6500                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6501                         break;
6502                 case OP_EXPAND_I8:
6503                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6504                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6505                         break;
6506                 case OP_EXPAND_R4:
6507                         if (cfg->r4fp) {
6508                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6509                         } else {
6510                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6511                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6512                         }
6513                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6514                         break;
6515                 case OP_EXPAND_R8:
6516                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6517                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6518                         break;
6519 #endif
6520                 case OP_LIVERANGE_START: {
6521                         if (cfg->verbose_level > 1)
6522                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6523                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6524                         break;
6525                 }
6526                 case OP_LIVERANGE_END: {
6527                         if (cfg->verbose_level > 1)
6528                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6529                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6530                         break;
6531                 }
6532                 case OP_NACL_GC_SAFE_POINT: {
6533 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6534                         if (cfg->compile_aot)
6535                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6536                         else {
6537                                 guint8 *br [1];
6538
6539                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6540                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6541                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6542                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6543                                 amd64_patch (br[0], code);
6544                         }
6545 #endif
6546                         break;
6547                 }
6548                 case OP_GC_LIVENESS_DEF:
6549                 case OP_GC_LIVENESS_USE:
6550                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6551                         ins->backend.pc_offset = code - cfg->native_code;
6552                         break;
6553                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6554                         ins->backend.pc_offset = code - cfg->native_code;
6555                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6556                         break;
6557                 default:
6558                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6559                         g_assert_not_reached ();
6560                 }
6561
6562                 if ((code - cfg->native_code - offset) > max_len) {
6563 #if !defined(__native_client_codegen__)
6564                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6565                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6566                         g_assert_not_reached ();
6567 #endif
6568                 }
6569         }
6570
6571         cfg->code_len = code - cfg->native_code;
6572 }
6573
6574 #endif /* DISABLE_JIT */
6575
6576 void
6577 mono_arch_register_lowlevel_calls (void)
6578 {
6579         /* The signature doesn't matter */
6580         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6581 }
6582
6583 void
6584 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6585 {
6586         MonoJumpInfo *patch_info;
6587         gboolean compile_aot = !run_cctors;
6588
6589         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6590                 unsigned char *ip = patch_info->ip.i + code;
6591                 unsigned char *target;
6592
6593                 if (compile_aot) {
6594                         switch (patch_info->type) {
6595                         case MONO_PATCH_INFO_BB:
6596                         case MONO_PATCH_INFO_LABEL:
6597                                 break;
6598                         default:
6599                                 /* No need to patch these */
6600                                 continue;
6601                         }
6602                 }
6603
6604                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6605
6606                 switch (patch_info->type) {
6607                 case MONO_PATCH_INFO_NONE:
6608                         continue;
6609                 case MONO_PATCH_INFO_METHOD_REL:
6610                 case MONO_PATCH_INFO_R8:
6611                 case MONO_PATCH_INFO_R4:
6612                         g_assert_not_reached ();
6613                         continue;
6614                 case MONO_PATCH_INFO_BB:
6615                         break;
6616                 default:
6617                         break;
6618                 }
6619
6620                 /*
6621                  * Debug code to help track down problems where the target of a near call is
6622                  * is not valid.
6623                  */
6624                 if (amd64_is_near_call (ip)) {
6625                         gint64 disp = (guint8*)target - (guint8*)ip;
6626
6627                         if (!amd64_is_imm32 (disp)) {
6628                                 printf ("TYPE: %d\n", patch_info->type);
6629                                 switch (patch_info->type) {
6630                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6631                                         printf ("V: %s\n", patch_info->data.name);
6632                                         break;
6633                                 case MONO_PATCH_INFO_METHOD_JUMP:
6634                                 case MONO_PATCH_INFO_METHOD:
6635                                         printf ("V: %s\n", patch_info->data.method->name);
6636                                         break;
6637                                 default:
6638                                         break;
6639                                 }
6640                         }
6641                 }
6642
6643                 amd64_patch (ip, (gpointer)target);
6644         }
6645 }
6646
6647 #ifndef DISABLE_JIT
6648
6649 static int
6650 get_max_epilog_size (MonoCompile *cfg)
6651 {
6652         int max_epilog_size = 16;
6653
6654         if (cfg->method->save_lmf)
6655                 max_epilog_size += 256;
6656
6657         if (mono_jit_trace_calls != NULL)
6658                 max_epilog_size += 50;
6659
6660         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6661                 max_epilog_size += 50;
6662
6663         max_epilog_size += (AMD64_NREG * 2);
6664
6665         return max_epilog_size;
6666 }
6667
6668 /*
6669  * This macro is used for testing whenever the unwinder works correctly at every point
6670  * where an async exception can happen.
6671  */
6672 /* This will generate a SIGSEGV at the given point in the code */
6673 #define async_exc_point(code) do { \
6674     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6675          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6676              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6677          cfg->arch.async_point_count ++; \
6678     } \
6679 } while (0)
6680
6681 guint8 *
6682 mono_arch_emit_prolog (MonoCompile *cfg)
6683 {
6684         MonoMethod *method = cfg->method;
6685         MonoBasicBlock *bb;
6686         MonoMethodSignature *sig;
6687         MonoInst *ins;
6688         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6689         guint8 *code;
6690         CallInfo *cinfo;
6691         MonoInst *lmf_var = cfg->lmf_var;
6692         gboolean args_clobbered = FALSE;
6693         gboolean trace = FALSE;
6694 #ifdef __native_client_codegen__
6695         guint alignment_check;
6696 #endif
6697
6698         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6699
6700 #if defined(__default_codegen__)
6701         code = cfg->native_code = g_malloc (cfg->code_size);
6702 #elif defined(__native_client_codegen__)
6703         /* native_code_alloc is not 32-byte aligned, native_code is. */
6704         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6705
6706         /* Align native_code to next nearest kNaclAlignment byte. */
6707         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6708         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6709
6710         code = cfg->native_code;
6711
6712         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6713         g_assert (alignment_check == 0);
6714 #endif
6715
6716         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6717                 trace = TRUE;
6718
6719         /* Amount of stack space allocated by register saving code */
6720         pos = 0;
6721
6722         /* Offset between RSP and the CFA */
6723         cfa_offset = 0;
6724
6725         /*
6726          * The prolog consists of the following parts:
6727          * FP present:
6728          * - push rbp, mov rbp, rsp
6729          * - save callee saved regs using pushes
6730          * - allocate frame
6731          * - save rgctx if needed
6732          * - save lmf if needed
6733          * FP not present:
6734          * - allocate frame
6735          * - save rgctx if needed
6736          * - save lmf if needed
6737          * - save callee saved regs using moves
6738          */
6739
6740         // CFA = sp + 8
6741         cfa_offset = 8;
6742         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6743         // IP saved at CFA - 8
6744         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6745         async_exc_point (code);
6746         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6747
6748         if (!cfg->arch.omit_fp) {
6749                 amd64_push_reg (code, AMD64_RBP);
6750                 cfa_offset += 8;
6751                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6752                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6753                 async_exc_point (code);
6754 #ifdef HOST_WIN32
6755                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6756 #endif
6757                 /* These are handled automatically by the stack marking code */
6758                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6759
6760                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6761                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6762                 async_exc_point (code);
6763 #ifdef HOST_WIN32
6764                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6765 #endif
6766         }
6767
6768         /* The param area is always at offset 0 from sp */
6769         /* This needs to be allocated here, since it has to come after the spill area */
6770         if (cfg->param_area) {
6771                 if (cfg->arch.omit_fp)
6772                         // FIXME:
6773                         g_assert_not_reached ();
6774                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6775         }
6776
6777         if (cfg->arch.omit_fp) {
6778                 /*
6779                  * On enter, the stack is misaligned by the pushing of the return
6780                  * address. It is either made aligned by the pushing of %rbp, or by
6781                  * this.
6782                  */
6783                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6784                 if ((alloc_size % 16) == 0) {
6785                         alloc_size += 8;
6786                         /* Mark the padding slot as NOREF */
6787                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6788                 }
6789         } else {
6790                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6791                 if (cfg->stack_offset != alloc_size) {
6792                         /* Mark the padding slot as NOREF */
6793                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6794                 }
6795                 cfg->arch.sp_fp_offset = alloc_size;
6796                 alloc_size -= pos;
6797         }
6798
6799         cfg->arch.stack_alloc_size = alloc_size;
6800
6801         /* Allocate stack frame */
6802         if (alloc_size) {
6803                 /* See mono_emit_stack_alloc */
6804 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6805                 guint32 remaining_size = alloc_size;
6806                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6807                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6808                 guint32 offset = code - cfg->native_code;
6809                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6810                         while (required_code_size >= (cfg->code_size - offset))
6811                                 cfg->code_size *= 2;
6812                         cfg->native_code = mono_realloc_native_code (cfg);
6813                         code = cfg->native_code + offset;
6814                         cfg->stat_code_reallocs++;
6815                 }
6816
6817                 while (remaining_size >= 0x1000) {
6818                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6819                         if (cfg->arch.omit_fp) {
6820                                 cfa_offset += 0x1000;
6821                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6822                         }
6823                         async_exc_point (code);
6824 #ifdef HOST_WIN32
6825                         if (cfg->arch.omit_fp)
6826                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6827 #endif
6828
6829                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6830                         remaining_size -= 0x1000;
6831                 }
6832                 if (remaining_size) {
6833                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6834                         if (cfg->arch.omit_fp) {
6835                                 cfa_offset += remaining_size;
6836                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6837                                 async_exc_point (code);
6838                         }
6839 #ifdef HOST_WIN32
6840                         if (cfg->arch.omit_fp)
6841                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6842 #endif
6843                 }
6844 #else
6845                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6846                 if (cfg->arch.omit_fp) {
6847                         cfa_offset += alloc_size;
6848                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6849                         async_exc_point (code);
6850                 }
6851 #endif
6852         }
6853
6854         /* Stack alignment check */
6855 #if 0
6856         {
6857                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6858                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6859                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6860                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6861                 amd64_breakpoint (code);
6862         }
6863 #endif
6864
6865         if (mini_get_debug_options ()->init_stacks) {
6866                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6867
6868                 /* Save registers to the red zone */
6869                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6870                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6871
6872                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6873                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6874                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6875
6876                 amd64_cld (code);
6877 #if defined(__default_codegen__)
6878                 amd64_prefix (code, X86_REP_PREFIX);
6879                 amd64_stosl (code);
6880 #elif defined(__native_client_codegen__)
6881                 /* NaCl stos pseudo-instruction */
6882                 amd64_codegen_pre (code);
6883                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6884                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6885                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6886                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6887                 amd64_prefix (code, X86_REP_PREFIX);
6888                 amd64_stosl (code);
6889                 amd64_codegen_post (code);
6890 #endif /* __native_client_codegen__ */
6891
6892                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6893                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6894         }
6895
6896         /* Save LMF */
6897         if (method->save_lmf)
6898                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6899
6900         /* Save callee saved registers */
6901         if (cfg->arch.omit_fp) {
6902                 save_area_offset = cfg->arch.reg_save_area_offset;
6903                 /* Save caller saved registers after sp is adjusted */
6904                 /* The registers are saved at the bottom of the frame */
6905                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6906         } else {
6907                 /* The registers are saved just below the saved rbp */
6908                 save_area_offset = cfg->arch.reg_save_area_offset;
6909         }
6910
6911         for (i = 0; i < AMD64_NREG; ++i) {
6912                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6913                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6914
6915                         if (cfg->arch.omit_fp) {
6916                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6917                                 /* These are handled automatically by the stack marking code */
6918                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6919                         } else {
6920                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6921                                 // FIXME: GC
6922                         }
6923
6924                         save_area_offset += 8;
6925                         async_exc_point (code);
6926                 }
6927         }
6928
6929         /* store runtime generic context */
6930         if (cfg->rgctx_var) {
6931                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6932                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6933
6934                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6935
6936                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6937                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6938         }
6939
6940         /* compute max_length in order to use short forward jumps */
6941         max_epilog_size = get_max_epilog_size (cfg);
6942         if (cfg->opt & MONO_OPT_BRANCH) {
6943                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6944                         MonoInst *ins;
6945                         int max_length = 0;
6946
6947                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6948                                 max_length += 6;
6949                         /* max alignment for loops */
6950                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6951                                 max_length += LOOP_ALIGNMENT;
6952 #ifdef __native_client_codegen__
6953                         /* max alignment for native client */
6954                         max_length += kNaClAlignment;
6955 #endif
6956
6957                         MONO_BB_FOR_EACH_INS (bb, ins) {
6958 #ifdef __native_client_codegen__
6959                                 {
6960                                         int space_in_block = kNaClAlignment -
6961                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6962                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6963                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6964                                                 max_length += space_in_block;
6965                                         }
6966                                 }
6967 #endif  /*__native_client_codegen__*/
6968                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6969                         }
6970
6971                         /* Take prolog and epilog instrumentation into account */
6972                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6973                                 max_length += max_epilog_size;
6974
6975                         bb->max_length = max_length;
6976                 }
6977         }
6978
6979         sig = mono_method_signature (method);
6980         pos = 0;
6981
6982         cinfo = cfg->arch.cinfo;
6983
6984         if (sig->ret->type != MONO_TYPE_VOID) {
6985                 /* Save volatile arguments to the stack */
6986                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6987                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6988         }
6989
6990         /* Keep this in sync with emit_load_volatile_arguments */
6991         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6992                 ArgInfo *ainfo = cinfo->args + i;
6993
6994                 ins = cfg->args [i];
6995
6996                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6997                         /* Unused arguments */
6998                         continue;
6999
7000                 if (cfg->globalra) {
7001                         /* All the other moves are done by the register allocator */
7002                         switch (ainfo->storage) {
7003                         case ArgInFloatSSEReg:
7004                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7005                                 break;
7006                         case ArgValuetypeInReg:
7007                                 for (quad = 0; quad < 2; quad ++) {
7008                                         switch (ainfo->pair_storage [quad]) {
7009                                         case ArgInIReg:
7010                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7011                                                 break;
7012                                         case ArgInFloatSSEReg:
7013                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7014                                                 break;
7015                                         case ArgInDoubleSSEReg:
7016                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7017                                                 break;
7018                                         case ArgNone:
7019                                                 break;
7020                                         default:
7021                                                 g_assert_not_reached ();
7022                                         }
7023                                 }
7024                                 break;
7025                         default:
7026                                 break;
7027                         }
7028
7029                         continue;
7030                 }
7031
7032                 /* Save volatile arguments to the stack */
7033                 if (ins->opcode != OP_REGVAR) {
7034                         switch (ainfo->storage) {
7035                         case ArgInIReg: {
7036                                 guint32 size = 8;
7037
7038                                 /* FIXME: I1 etc */
7039                                 /*
7040                                 if (stack_offset & 0x1)
7041                                         size = 1;
7042                                 else if (stack_offset & 0x2)
7043                                         size = 2;
7044                                 else if (stack_offset & 0x4)
7045                                         size = 4;
7046                                 else
7047                                         size = 8;
7048                                 */
7049                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7050
7051                                 /*
7052                                  * Save the original location of 'this',
7053                                  * get_generic_info_from_stack_frame () needs this to properly look up
7054                                  * the argument value during the handling of async exceptions.
7055                                  */
7056                                 if (ins == cfg->args [0]) {
7057                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7058                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7059                                 }
7060                                 break;
7061                         }
7062                         case ArgInFloatSSEReg:
7063                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7064                                 break;
7065                         case ArgInDoubleSSEReg:
7066                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7067                                 break;
7068                         case ArgValuetypeInReg:
7069                                 for (quad = 0; quad < 2; quad ++) {
7070                                         switch (ainfo->pair_storage [quad]) {
7071                                         case ArgInIReg:
7072                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7073                                                 break;
7074                                         case ArgInFloatSSEReg:
7075                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7076                                                 break;
7077                                         case ArgInDoubleSSEReg:
7078                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7079                                                 break;
7080                                         case ArgNone:
7081                                                 break;
7082                                         default:
7083                                                 g_assert_not_reached ();
7084                                         }
7085                                 }
7086                                 break;
7087                         case ArgValuetypeAddrInIReg:
7088                                 if (ainfo->pair_storage [0] == ArgInIReg)
7089                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7090                                 break;
7091                         default:
7092                                 break;
7093                         }
7094                 } else {
7095                         /* Argument allocated to (non-volatile) register */
7096                         switch (ainfo->storage) {
7097                         case ArgInIReg:
7098                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7099                                 break;
7100                         case ArgOnStack:
7101                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7102                                 break;
7103                         default:
7104                                 g_assert_not_reached ();
7105                         }
7106
7107                         if (ins == cfg->args [0]) {
7108                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7109                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7110                         }
7111                 }
7112         }
7113
7114         if (cfg->method->save_lmf)
7115                 args_clobbered = TRUE;
7116
7117         if (trace) {
7118                 args_clobbered = TRUE;
7119                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7120         }
7121
7122         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7123                 args_clobbered = TRUE;
7124
7125         /*
7126          * Optimize the common case of the first bblock making a call with the same
7127          * arguments as the method. This works because the arguments are still in their
7128          * original argument registers.
7129          * FIXME: Generalize this
7130          */
7131         if (!args_clobbered) {
7132                 MonoBasicBlock *first_bb = cfg->bb_entry;
7133                 MonoInst *next;
7134                 int filter = FILTER_IL_SEQ_POINT;
7135
7136                 next = mono_bb_first_inst (first_bb, filter);
7137                 if (!next && first_bb->next_bb) {
7138                         first_bb = first_bb->next_bb;
7139                         next = mono_bb_first_inst (first_bb, filter);
7140                 }
7141
7142                 if (first_bb->in_count > 1)
7143                         next = NULL;
7144
7145                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7146                         ArgInfo *ainfo = cinfo->args + i;
7147                         gboolean match = FALSE;
7148
7149                         ins = cfg->args [i];
7150                         if (ins->opcode != OP_REGVAR) {
7151                                 switch (ainfo->storage) {
7152                                 case ArgInIReg: {
7153                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7154                                                 if (next->dreg == ainfo->reg) {
7155                                                         NULLIFY_INS (next);
7156                                                         match = TRUE;
7157                                                 } else {
7158                                                         next->opcode = OP_MOVE;
7159                                                         next->sreg1 = ainfo->reg;
7160                                                         /* Only continue if the instruction doesn't change argument regs */
7161                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7162                                                                 match = TRUE;
7163                                                 }
7164                                         }
7165                                         break;
7166                                 }
7167                                 default:
7168                                         break;
7169                                 }
7170                         } else {
7171                                 /* Argument allocated to (non-volatile) register */
7172                                 switch (ainfo->storage) {
7173                                 case ArgInIReg:
7174                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7175                                                 NULLIFY_INS (next);
7176                                                 match = TRUE;
7177                                         }
7178                                         break;
7179                                 default:
7180                                         break;
7181                                 }
7182                         }
7183
7184                         if (match) {
7185                                 next = mono_inst_next (next, filter);
7186                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7187                                 if (!next)
7188                                         break;
7189                         }
7190                 }
7191         }
7192
7193         if (cfg->gen_seq_points_debug_data) {
7194                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7195
7196                 /* Initialize seq_point_info_var */
7197                 if (cfg->compile_aot) {
7198                         /* Initialize the variable from a GOT slot */
7199                         /* Same as OP_AOTCONST */
7200                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7201                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7202                         g_assert (info_var->opcode == OP_REGOFFSET);
7203                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7204                 }
7205
7206                 /* Initialize ss_trigger_page_var */
7207                 ins = cfg->arch.ss_trigger_page_var;
7208
7209                 g_assert (ins->opcode == OP_REGOFFSET);
7210
7211                 if (cfg->compile_aot) {
7212                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7213                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7214                 } else {
7215                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7216                 }
7217                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7218         }
7219
7220         cfg->code_len = code - cfg->native_code;
7221
7222         g_assert (cfg->code_len < cfg->code_size);
7223
7224         return code;
7225 }
7226
7227 void
7228 mono_arch_emit_epilog (MonoCompile *cfg)
7229 {
7230         MonoMethod *method = cfg->method;
7231         int quad, i;
7232         guint8 *code;
7233         int max_epilog_size;
7234         CallInfo *cinfo;
7235         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7236         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7237
7238         max_epilog_size = get_max_epilog_size (cfg);
7239
7240         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7241                 cfg->code_size *= 2;
7242                 cfg->native_code = mono_realloc_native_code (cfg);
7243                 cfg->stat_code_reallocs++;
7244         }
7245         code = cfg->native_code + cfg->code_len;
7246
7247         cfg->has_unwind_info_for_epilog = TRUE;
7248
7249         /* Mark the start of the epilog */
7250         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7251
7252         /* Save the uwind state which is needed by the out-of-line code */
7253         mono_emit_unwind_op_remember_state (cfg, code);
7254
7255         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7256                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7257
7258         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7259
7260         if (method->save_lmf) {
7261                 /* check if we need to restore protection of the stack after a stack overflow */
7262                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7263                         guint8 *patch;
7264                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7265                         /* we load the value in a separate instruction: this mechanism may be
7266                          * used later as a safer way to do thread interruption
7267                          */
7268                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7269                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7270                         patch = code;
7271                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7272                         /* note that the call trampoline will preserve eax/edx */
7273                         x86_call_reg (code, X86_ECX);
7274                         x86_patch (patch, code);
7275                 } else {
7276                         /* FIXME: maybe save the jit tls in the prolog */
7277                 }
7278                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7279                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7280                 }
7281         }
7282
7283         /* Restore callee saved regs */
7284         for (i = 0; i < AMD64_NREG; ++i) {
7285                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7286                         /* Restore only used_int_regs, not arch.saved_iregs */
7287                         if (cfg->used_int_regs & (1 << i)) {
7288                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7289                                 mono_emit_unwind_op_same_value (cfg, code, i);
7290                                 async_exc_point (code);
7291                         }
7292                         save_area_offset += 8;
7293                 }
7294         }
7295
7296         /* Load returned vtypes into registers if needed */
7297         cinfo = cfg->arch.cinfo;
7298         if (cinfo->ret.storage == ArgValuetypeInReg) {
7299                 ArgInfo *ainfo = &cinfo->ret;
7300                 MonoInst *inst = cfg->ret;
7301
7302                 for (quad = 0; quad < 2; quad ++) {
7303                         switch (ainfo->pair_storage [quad]) {
7304                         case ArgInIReg:
7305                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7306                                 break;
7307                         case ArgInFloatSSEReg:
7308                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7309                                 break;
7310                         case ArgInDoubleSSEReg:
7311                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7312                                 break;
7313                         case ArgNone:
7314                                 break;
7315                         default:
7316                                 g_assert_not_reached ();
7317                         }
7318                 }
7319         }
7320
7321         if (cfg->arch.omit_fp) {
7322                 if (cfg->arch.stack_alloc_size) {
7323                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7324                 }
7325         } else {
7326                 amd64_leave (code);
7327                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7328         }
7329         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7330         async_exc_point (code);
7331         amd64_ret (code);
7332
7333         /* Restore the unwind state to be the same as before the epilog */
7334         mono_emit_unwind_op_restore_state (cfg, code);
7335
7336         cfg->code_len = code - cfg->native_code;
7337
7338         g_assert (cfg->code_len < cfg->code_size);
7339 }
7340
7341 void
7342 mono_arch_emit_exceptions (MonoCompile *cfg)
7343 {
7344         MonoJumpInfo *patch_info;
7345         int nthrows, i;
7346         guint8 *code;
7347         MonoClass *exc_classes [16];
7348         guint8 *exc_throw_start [16], *exc_throw_end [16];
7349         guint32 code_size = 0;
7350
7351         /* Compute needed space */
7352         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7353                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7354                         code_size += 40;
7355                 if (patch_info->type == MONO_PATCH_INFO_R8)
7356                         code_size += 8 + 15; /* sizeof (double) + alignment */
7357                 if (patch_info->type == MONO_PATCH_INFO_R4)
7358                         code_size += 4 + 15; /* sizeof (float) + alignment */
7359                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7360                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7361         }
7362
7363 #ifdef __native_client_codegen__
7364         /* Give us extra room on Native Client.  This could be   */
7365         /* more carefully calculated, but bundle alignment makes */
7366         /* it much trickier, so *2 like other places is good.    */
7367         code_size *= 2;
7368 #endif
7369
7370         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7371                 cfg->code_size *= 2;
7372                 cfg->native_code = mono_realloc_native_code (cfg);
7373                 cfg->stat_code_reallocs++;
7374         }
7375
7376         code = cfg->native_code + cfg->code_len;
7377
7378         /* add code to raise exceptions */
7379         nthrows = 0;
7380         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7381                 switch (patch_info->type) {
7382                 case MONO_PATCH_INFO_EXC: {
7383                         MonoClass *exc_class;
7384                         guint8 *buf, *buf2;
7385                         guint32 throw_ip;
7386
7387                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7388
7389                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7390                         g_assert (exc_class);
7391                         throw_ip = patch_info->ip.i;
7392
7393                         //x86_breakpoint (code);
7394                         /* Find a throw sequence for the same exception class */
7395                         for (i = 0; i < nthrows; ++i)
7396                                 if (exc_classes [i] == exc_class)
7397                                         break;
7398                         if (i < nthrows) {
7399                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7400                                 x86_jump_code (code, exc_throw_start [i]);
7401                                 patch_info->type = MONO_PATCH_INFO_NONE;
7402                         }
7403                         else {
7404                                 buf = code;
7405                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7406                                 buf2 = code;
7407
7408                                 if (nthrows < 16) {
7409                                         exc_classes [nthrows] = exc_class;
7410                                         exc_throw_start [nthrows] = code;
7411                                 }
7412                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7413
7414                                 patch_info->type = MONO_PATCH_INFO_NONE;
7415
7416                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7417
7418                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7419                                 while (buf < buf2)
7420                                         x86_nop (buf);
7421
7422                                 if (nthrows < 16) {
7423                                         exc_throw_end [nthrows] = code;
7424                                         nthrows ++;
7425                                 }
7426                         }
7427                         break;
7428                 }
7429                 default:
7430                         /* do nothing */
7431                         break;
7432                 }
7433                 g_assert(code < cfg->native_code + cfg->code_size);
7434         }
7435
7436         /* Handle relocations with RIP relative addressing */
7437         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7438                 gboolean remove = FALSE;
7439                 guint8 *orig_code = code;
7440
7441                 switch (patch_info->type) {
7442                 case MONO_PATCH_INFO_R8:
7443                 case MONO_PATCH_INFO_R4: {
7444                         guint8 *pos, *patch_pos;
7445                         guint32 target_pos;
7446
7447                         /* The SSE opcodes require a 16 byte alignment */
7448 #if defined(__default_codegen__)
7449                         code = (guint8*)ALIGN_TO (code, 16);
7450 #elif defined(__native_client_codegen__)
7451                         {
7452                                 /* Pad this out with HLT instructions  */
7453                                 /* or we can get garbage bytes emitted */
7454                                 /* which will fail validation          */
7455                                 guint8 *aligned_code;
7456                                 /* extra align to make room for  */
7457                                 /* mov/push below                      */
7458                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7459                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7460                                 /* The technique of hiding data in an  */
7461                                 /* instruction has a problem here: we  */
7462                                 /* need the data aligned to a 16-byte  */
7463                                 /* boundary but the instruction cannot */
7464                                 /* cross the bundle boundary. so only  */
7465                                 /* odd multiples of 16 can be used     */
7466                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7467                                         aligned_code += 16;
7468                                 }
7469                                 while (code < aligned_code) {
7470                                         *(code++) = 0xf4; /* hlt */
7471                                 }
7472                         }
7473 #endif
7474
7475                         pos = cfg->native_code + patch_info->ip.i;
7476                         if (IS_REX (pos [1])) {
7477                                 patch_pos = pos + 5;
7478                                 target_pos = code - pos - 9;
7479                         }
7480                         else {
7481                                 patch_pos = pos + 4;
7482                                 target_pos = code - pos - 8;
7483                         }
7484
7485                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7486 #ifdef __native_client_codegen__
7487                                 /* Hide 64-bit data in a         */
7488                                 /* "mov imm64, r11" instruction. */
7489                                 /* write it before the start of  */
7490                                 /* the data*/
7491                                 *(code-2) = 0x49; /* prefix      */
7492                                 *(code-1) = 0xbb; /* mov X, %r11 */
7493 #endif
7494                                 *(double*)code = *(double*)patch_info->data.target;
7495                                 code += sizeof (double);
7496                         } else {
7497 #ifdef __native_client_codegen__
7498                                 /* Hide 32-bit data in a        */
7499                                 /* "push imm32" instruction.    */
7500                                 *(code-1) = 0x68; /* push */
7501 #endif
7502                                 *(float*)code = *(float*)patch_info->data.target;
7503                                 code += sizeof (float);
7504                         }
7505
7506                         *(guint32*)(patch_pos) = target_pos;
7507
7508                         remove = TRUE;
7509                         break;
7510                 }
7511                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7512                         guint8 *pos;
7513
7514                         if (cfg->compile_aot)
7515                                 continue;
7516
7517                         /*loading is faster against aligned addresses.*/
7518                         code = (guint8*)ALIGN_TO (code, 8);
7519                         memset (orig_code, 0, code - orig_code);
7520
7521                         pos = cfg->native_code + patch_info->ip.i;
7522
7523                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7524                         if (IS_REX (pos [1]))
7525                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7526                         else
7527                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7528
7529                         *(gpointer*)code = (gpointer)patch_info->data.target;
7530                         code += sizeof (gpointer);
7531
7532                         remove = TRUE;
7533                         break;
7534                 }
7535                 default:
7536                         break;
7537                 }
7538
7539                 if (remove) {
7540                         if (patch_info == cfg->patch_info)
7541                                 cfg->patch_info = patch_info->next;
7542                         else {
7543                                 MonoJumpInfo *tmp;
7544
7545                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7546                                         ;
7547                                 tmp->next = patch_info->next;
7548                         }
7549                 }
7550                 g_assert (code < cfg->native_code + cfg->code_size);
7551         }
7552
7553         cfg->code_len = code - cfg->native_code;
7554
7555         g_assert (cfg->code_len < cfg->code_size);
7556
7557 }
7558
7559 #endif /* DISABLE_JIT */
7560
7561 void*
7562 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7563 {
7564         guchar *code = p;
7565         MonoMethodSignature *sig;
7566         MonoInst *inst;
7567         int i, n, stack_area = 0;
7568
7569         /* Keep this in sync with mono_arch_get_argument_info */
7570
7571         if (enable_arguments) {
7572                 /* Allocate a new area on the stack and save arguments there */
7573                 sig = mono_method_signature (cfg->method);
7574
7575                 n = sig->param_count + sig->hasthis;
7576
7577                 stack_area = ALIGN_TO (n * 8, 16);
7578
7579                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7580
7581                 for (i = 0; i < n; ++i) {
7582                         inst = cfg->args [i];
7583
7584                         if (inst->opcode == OP_REGVAR)
7585                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7586                         else {
7587                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7588                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7589                         }
7590                 }
7591         }
7592
7593         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7594         amd64_set_reg_template (code, AMD64_ARG_REG1);
7595         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7596         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7597
7598         if (enable_arguments)
7599                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7600
7601         return code;
7602 }
7603
7604 enum {
7605         SAVE_NONE,
7606         SAVE_STRUCT,
7607         SAVE_EAX,
7608         SAVE_EAX_EDX,
7609         SAVE_XMM
7610 };
7611
7612 void*
7613 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7614 {
7615         guchar *code = p;
7616         int save_mode = SAVE_NONE;
7617         MonoMethod *method = cfg->method;
7618         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7619         int i;
7620
7621         switch (ret_type->type) {
7622         case MONO_TYPE_VOID:
7623                 /* special case string .ctor icall */
7624                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7625                         save_mode = SAVE_EAX;
7626                 else
7627                         save_mode = SAVE_NONE;
7628                 break;
7629         case MONO_TYPE_I8:
7630         case MONO_TYPE_U8:
7631                 save_mode = SAVE_EAX;
7632                 break;
7633         case MONO_TYPE_R4:
7634         case MONO_TYPE_R8:
7635                 save_mode = SAVE_XMM;
7636                 break;
7637         case MONO_TYPE_GENERICINST:
7638                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7639                         save_mode = SAVE_EAX;
7640                         break;
7641                 }
7642                 /* Fall through */
7643         case MONO_TYPE_VALUETYPE:
7644                 save_mode = SAVE_STRUCT;
7645                 break;
7646         default:
7647                 save_mode = SAVE_EAX;
7648                 break;
7649         }
7650
7651         /* Save the result and copy it into the proper argument register */
7652         switch (save_mode) {
7653         case SAVE_EAX:
7654                 amd64_push_reg (code, AMD64_RAX);
7655                 /* Align stack */
7656                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7657                 if (enable_arguments)
7658                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7659                 break;
7660         case SAVE_STRUCT:
7661                 /* FIXME: */
7662                 if (enable_arguments)
7663                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7664                 break;
7665         case SAVE_XMM:
7666                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7667                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7668                 /* Align stack */
7669                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7670                 /*
7671                  * The result is already in the proper argument register so no copying
7672                  * needed.
7673                  */
7674                 break;
7675         case SAVE_NONE:
7676                 break;
7677         default:
7678                 g_assert_not_reached ();
7679         }
7680
7681         /* Set %al since this is a varargs call */
7682         if (save_mode == SAVE_XMM)
7683                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7684         else
7685                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7686
7687         if (preserve_argument_registers) {
7688                 for (i = 0; i < PARAM_REGS; ++i)
7689                         amd64_push_reg (code, param_regs [i]);
7690         }
7691
7692         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7693         amd64_set_reg_template (code, AMD64_ARG_REG1);
7694         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7695
7696         if (preserve_argument_registers) {
7697                 for (i = PARAM_REGS - 1; i >= 0; --i)
7698                         amd64_pop_reg (code, param_regs [i]);
7699         }
7700
7701         /* Restore result */
7702         switch (save_mode) {
7703         case SAVE_EAX:
7704                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7705                 amd64_pop_reg (code, AMD64_RAX);
7706                 break;
7707         case SAVE_STRUCT:
7708                 /* FIXME: */
7709                 break;
7710         case SAVE_XMM:
7711                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7712                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7713                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7714                 break;
7715         case SAVE_NONE:
7716                 break;
7717         default:
7718                 g_assert_not_reached ();
7719         }
7720
7721         return code;
7722 }
7723
7724 void
7725 mono_arch_flush_icache (guint8 *code, gint size)
7726 {
7727         /* Not needed */
7728 }
7729
7730 void
7731 mono_arch_flush_register_windows (void)
7732 {
7733 }
7734
7735 gboolean
7736 mono_arch_is_inst_imm (gint64 imm)
7737 {
7738         return amd64_is_imm32 (imm);
7739 }
7740
7741 /*
7742  * Determine whenever the trap whose info is in SIGINFO is caused by
7743  * integer overflow.
7744  */
7745 gboolean
7746 mono_arch_is_int_overflow (void *sigctx, void *info)
7747 {
7748         MonoContext ctx;
7749         guint8* rip;
7750         int reg;
7751         gint64 value;
7752
7753         mono_sigctx_to_monoctx (sigctx, &ctx);
7754
7755         rip = (guint8*)ctx.rip;
7756
7757         if (IS_REX (rip [0])) {
7758                 reg = amd64_rex_b (rip [0]);
7759                 rip ++;
7760         }
7761         else
7762                 reg = 0;
7763
7764         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7765                 /* idiv REG */
7766                 reg += x86_modrm_rm (rip [1]);
7767
7768                 switch (reg) {
7769                 case AMD64_RAX:
7770                         value = ctx.rax;
7771                         break;
7772                 case AMD64_RBX:
7773                         value = ctx.rbx;
7774                         break;
7775                 case AMD64_RCX:
7776                         value = ctx.rcx;
7777                         break;
7778                 case AMD64_RDX:
7779                         value = ctx.rdx;
7780                         break;
7781                 case AMD64_RBP:
7782                         value = ctx.rbp;
7783                         break;
7784                 case AMD64_RSP:
7785                         value = ctx.rsp;
7786                         break;
7787                 case AMD64_RSI:
7788                         value = ctx.rsi;
7789                         break;
7790                 case AMD64_RDI:
7791                         value = ctx.rdi;
7792                         break;
7793                 case AMD64_R12:
7794                         value = ctx.r12;
7795                         break;
7796                 case AMD64_R13:
7797                         value = ctx.r13;
7798                         break;
7799                 case AMD64_R14:
7800                         value = ctx.r14;
7801                         break;
7802                 case AMD64_R15:
7803                         value = ctx.r15;
7804                         break;
7805                 default:
7806                         g_assert_not_reached ();
7807                         reg = -1;
7808                 }
7809
7810                 if (value == -1)
7811                         return TRUE;
7812         }
7813
7814         return FALSE;
7815 }
7816
7817 guint32
7818 mono_arch_get_patch_offset (guint8 *code)
7819 {
7820         return 3;
7821 }
7822
7823 /**
7824  * mono_breakpoint_clean_code:
7825  *
7826  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7827  * breakpoints in the original code, they are removed in the copy.
7828  *
7829  * Returns TRUE if no sw breakpoint was present.
7830  */
7831 gboolean
7832 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7833 {
7834         /*
7835          * If method_start is non-NULL we need to perform bound checks, since we access memory
7836          * at code - offset we could go before the start of the method and end up in a different
7837          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7838          * instead.
7839          */
7840         if (!method_start || code - offset >= method_start) {
7841                 memcpy (buf, code - offset, size);
7842         } else {
7843                 int diff = code - method_start;
7844                 memset (buf, 0, size);
7845                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7846         }
7847         return TRUE;
7848 }
7849
7850 #if defined(__native_client_codegen__)
7851 /* For membase calls, we want the base register. for Native Client,  */
7852 /* all indirect calls have the following sequence with the given sizes: */
7853 /* mov %eXX,%eXX                                [2-3]   */
7854 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7855 /* and $0xffffffffffffffe0,%r11d                [4]     */
7856 /* add %r15,%r11                                [3]     */
7857 /* callq *%r11                                  [3]     */
7858
7859
7860 /* Determine if code points to a NaCl call-through-register sequence, */
7861 /* (i.e., the last 3 instructions listed above) */
7862 int
7863 is_nacl_call_reg_sequence(guint8* code)
7864 {
7865         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7866                                "\x4d\x03\xdf"     /* add */
7867                                "\x41\xff\xd3";   /* call */
7868         return memcmp(code, sequence, 10) == 0;
7869 }
7870
7871 /* Determine if code points to the first opcode of the mov membase component */
7872 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7873 /* (there could be a REX prefix before the opcode but it is ignored) */
7874 static int
7875 is_nacl_indirect_call_membase_sequence(guint8* code)
7876 {
7877                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7878         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7879                /* and that src reg = dest reg */
7880                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7881                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7882                IS_REX(code[2]) &&
7883                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7884                /* and has dst of r11 and base of r15 */
7885                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7886                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7887 }
7888 #endif /* __native_client_codegen__ */
7889
7890 int
7891 mono_arch_get_this_arg_reg (guint8 *code)
7892 {
7893         return AMD64_ARG_REG1;
7894 }
7895
7896 gpointer
7897 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7898 {
7899         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7900 }
7901
7902 #define MAX_ARCH_DELEGATE_PARAMS 10
7903
7904 static gpointer
7905 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7906 {
7907         guint8 *code, *start;
7908         int i;
7909
7910         if (has_target) {
7911                 start = code = mono_global_codeman_reserve (64);
7912
7913                 /* Replace the this argument with the target */
7914                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7915                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7916                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7917
7918                 g_assert ((code - start) < 64);
7919         } else {
7920                 start = code = mono_global_codeman_reserve (64);
7921
7922                 if (param_count == 0) {
7923                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7924                 } else {
7925                         /* We have to shift the arguments left */
7926                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7927                         for (i = 0; i < param_count; ++i) {
7928 #ifdef HOST_WIN32
7929                                 if (i < 3)
7930                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7931                                 else
7932                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7933 #else
7934                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7935 #endif
7936                         }
7937
7938                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7939                 }
7940                 g_assert ((code - start) < 64);
7941         }
7942
7943         nacl_global_codeman_validate (&start, 64, &code);
7944
7945         if (code_len)
7946                 *code_len = code - start;
7947
7948         if (mono_jit_map_is_enabled ()) {
7949                 char *buff;
7950                 if (has_target)
7951                         buff = (char*)"delegate_invoke_has_target";
7952                 else
7953                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7954                 mono_emit_jit_tramp (start, code - start, buff);
7955                 if (!has_target)
7956                         g_free (buff);
7957         }
7958         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7959
7960         return start;
7961 }
7962
7963 /*
7964  * mono_arch_get_delegate_invoke_impls:
7965  *
7966  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7967  * trampolines.
7968  */
7969 GSList*
7970 mono_arch_get_delegate_invoke_impls (void)
7971 {
7972         GSList *res = NULL;
7973         guint8 *code;
7974         guint32 code_len;
7975         int i;
7976         char *tramp_name;
7977
7978         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7979         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7980
7981         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7982                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7983                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7984                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7985                 g_free (tramp_name);
7986         }
7987
7988         return res;
7989 }
7990
7991 gpointer
7992 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7993 {
7994         guint8 *code, *start;
7995         int i;
7996
7997         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7998                 return NULL;
7999
8000         /* FIXME: Support more cases */
8001         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8002                 return NULL;
8003
8004         if (has_target) {
8005                 static guint8* cached = NULL;
8006
8007                 if (cached)
8008                         return cached;
8009
8010                 if (mono_aot_only)
8011                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8012                 else
8013                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8014
8015                 mono_memory_barrier ();
8016
8017                 cached = start;
8018         } else {
8019                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8020                 for (i = 0; i < sig->param_count; ++i)
8021                         if (!mono_is_regsize_var (sig->params [i]))
8022                                 return NULL;
8023                 if (sig->param_count > 4)
8024                         return NULL;
8025
8026                 code = cache [sig->param_count];
8027                 if (code)
8028                         return code;
8029
8030                 if (mono_aot_only) {
8031                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8032                         start = mono_aot_get_trampoline (name);
8033                         g_free (name);
8034                 } else {
8035                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8036                 }
8037
8038                 mono_memory_barrier ();
8039
8040                 cache [sig->param_count] = start;
8041         }
8042
8043         return start;
8044 }
8045
8046 gpointer
8047 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8048 {
8049         guint8 *code, *start;
8050         int size = 20;
8051
8052         start = code = mono_global_codeman_reserve (size);
8053
8054         /* Replace the this argument with the target */
8055         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8056         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8057
8058         if (load_imt_reg) {
8059                 /* Load the IMT reg */
8060                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8061         }
8062
8063         /* Load the vtable */
8064         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8065         amd64_jump_membase (code, AMD64_RAX, offset);
8066         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8067
8068         return start;
8069 }
8070
8071 void
8072 mono_arch_finish_init (void)
8073 {
8074 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8075         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8076 #endif
8077 }
8078
8079 void
8080 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8081 {
8082 }
8083
8084 #if defined(__default_codegen__)
8085 #define CMP_SIZE (6 + 1)
8086 #define CMP_REG_REG_SIZE (4 + 1)
8087 #define BR_SMALL_SIZE 2
8088 #define BR_LARGE_SIZE 6
8089 #define MOV_REG_IMM_SIZE 10
8090 #define MOV_REG_IMM_32BIT_SIZE 6
8091 #define JUMP_REG_SIZE (2 + 1)
8092 #elif defined(__native_client_codegen__)
8093 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8094 #define CMP_SIZE ((6 + 1) * 2 - 1)
8095 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8096 #define BR_SMALL_SIZE (2 * 2 - 1)
8097 #define BR_LARGE_SIZE (6 * 2 - 1)
8098 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8099 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8100 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8101 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8102 /* Jump membase's size is large and unpredictable    */
8103 /* in native client, just pad it out a whole bundle. */
8104 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8105 #endif
8106
8107 static int
8108 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8109 {
8110         int i, distance = 0;
8111         for (i = start; i < target; ++i)
8112                 distance += imt_entries [i]->chunk_size;
8113         return distance;
8114 }
8115
8116 /*
8117  * LOCKING: called with the domain lock held
8118  */
8119 gpointer
8120 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8121         gpointer fail_tramp)
8122 {
8123         int i;
8124         int size = 0;
8125         guint8 *code, *start;
8126         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8127
8128         for (i = 0; i < count; ++i) {
8129                 MonoIMTCheckItem *item = imt_entries [i];
8130                 if (item->is_equals) {
8131                         if (item->check_target_idx) {
8132                                 if (!item->compare_done) {
8133                                         if (amd64_is_imm32 (item->key))
8134                                                 item->chunk_size += CMP_SIZE;
8135                                         else
8136                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8137                                 }
8138                                 if (item->has_target_code) {
8139                                         item->chunk_size += MOV_REG_IMM_SIZE;
8140                                 } else {
8141                                         if (vtable_is_32bit)
8142                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8143                                         else
8144                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8145 #ifdef __native_client_codegen__
8146                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8147 #endif
8148                                 }
8149                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8150                         } else {
8151                                 if (fail_tramp) {
8152                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8153                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8154                                 } else {
8155                                         if (vtable_is_32bit)
8156                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8157                                         else
8158                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8159                                         item->chunk_size += JUMP_REG_SIZE;
8160                                         /* with assert below:
8161                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8162                                          */
8163 #ifdef __native_client_codegen__
8164                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8165 #endif
8166                                 }
8167                         }
8168                 } else {
8169                         if (amd64_is_imm32 (item->key))
8170                                 item->chunk_size += CMP_SIZE;
8171                         else
8172                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8173                         item->chunk_size += BR_LARGE_SIZE;
8174                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8175                 }
8176                 size += item->chunk_size;
8177         }
8178 #if defined(__native_client__) && defined(__native_client_codegen__)
8179         /* In Native Client, we don't re-use thunks, allocate from the */
8180         /* normal code manager paths. */
8181         code = mono_domain_code_reserve (domain, size);
8182 #else
8183         if (fail_tramp)
8184                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8185         else
8186                 code = mono_domain_code_reserve (domain, size);
8187 #endif
8188         start = code;
8189         for (i = 0; i < count; ++i) {
8190                 MonoIMTCheckItem *item = imt_entries [i];
8191                 item->code_target = code;
8192                 if (item->is_equals) {
8193                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8194
8195                         if (item->check_target_idx || fail_case) {
8196                                 if (!item->compare_done || fail_case) {
8197                                         if (amd64_is_imm32 (item->key))
8198                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8199                                         else {
8200                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8201                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8202                                         }
8203                                 }
8204                                 item->jmp_code = code;
8205                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8206                                 if (item->has_target_code) {
8207                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8208                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8209                                 } else {
8210                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8211                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8212                                 }
8213
8214                                 if (fail_case) {
8215                                         amd64_patch (item->jmp_code, code);
8216                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8217                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8218                                         item->jmp_code = NULL;
8219                                 }
8220                         } else {
8221                                 /* enable the commented code to assert on wrong method */
8222 #if 0
8223                                 if (amd64_is_imm32 (item->key))
8224                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8225                                 else {
8226                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8227                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8228                                 }
8229                                 item->jmp_code = code;
8230                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8231                                 /* See the comment below about R10 */
8232                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8233                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8234                                 amd64_patch (item->jmp_code, code);
8235                                 amd64_breakpoint (code);
8236                                 item->jmp_code = NULL;
8237 #else
8238                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8239                                    needs to be preserved.  R10 needs
8240                                    to be preserved for calls which
8241                                    require a runtime generic context,
8242                                    but interface calls don't. */
8243                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8244                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8245 #endif
8246                         }
8247                 } else {
8248                         if (amd64_is_imm32 (item->key))
8249                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8250                         else {
8251                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8252                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8253                         }
8254                         item->jmp_code = code;
8255                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8256                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8257                         else
8258                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8259                 }
8260                 g_assert (code - item->code_target <= item->chunk_size);
8261         }
8262         /* patch the branches to get to the target items */
8263         for (i = 0; i < count; ++i) {
8264                 MonoIMTCheckItem *item = imt_entries [i];
8265                 if (item->jmp_code) {
8266                         if (item->check_target_idx) {
8267                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8268                         }
8269                 }
8270         }
8271
8272         if (!fail_tramp)
8273                 mono_stats.imt_thunks_size += code - start;
8274         g_assert (code - start <= size);
8275
8276         nacl_domain_code_validate(domain, &start, size, &code);
8277         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8278
8279         return start;
8280 }
8281
8282 MonoMethod*
8283 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8284 {
8285         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8286 }
8287
8288 MonoVTable*
8289 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8290 {
8291         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8292 }
8293
8294 GSList*
8295 mono_arch_get_cie_program (void)
8296 {
8297         GSList *l = NULL;
8298
8299         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8300         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8301
8302         return l;
8303 }
8304
8305 #ifndef DISABLE_JIT
8306
8307 MonoInst*
8308 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8309 {
8310         MonoInst *ins = NULL;
8311         int opcode = 0;
8312
8313         if (cmethod->klass == mono_defaults.math_class) {
8314                 if (strcmp (cmethod->name, "Sin") == 0) {
8315                         opcode = OP_SIN;
8316                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8317                         opcode = OP_COS;
8318                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8319                         opcode = OP_SQRT;
8320                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8321                         opcode = OP_ABS;
8322                 }
8323
8324                 if (opcode && fsig->param_count == 1) {
8325                         MONO_INST_NEW (cfg, ins, opcode);
8326                         ins->type = STACK_R8;
8327                         ins->dreg = mono_alloc_freg (cfg);
8328                         ins->sreg1 = args [0]->dreg;
8329                         MONO_ADD_INS (cfg->cbb, ins);
8330                 }
8331
8332                 opcode = 0;
8333                 if (cfg->opt & MONO_OPT_CMOV) {
8334                         if (strcmp (cmethod->name, "Min") == 0) {
8335                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8336                                         opcode = OP_IMIN;
8337                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8338                                         opcode = OP_IMIN_UN;
8339                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8340                                         opcode = OP_LMIN;
8341                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8342                                         opcode = OP_LMIN_UN;
8343                         } else if (strcmp (cmethod->name, "Max") == 0) {
8344                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8345                                         opcode = OP_IMAX;
8346                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8347                                         opcode = OP_IMAX_UN;
8348                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8349                                         opcode = OP_LMAX;
8350                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8351                                         opcode = OP_LMAX_UN;
8352                         }
8353                 }
8354
8355                 if (opcode && fsig->param_count == 2) {
8356                         MONO_INST_NEW (cfg, ins, opcode);
8357                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8358                         ins->dreg = mono_alloc_ireg (cfg);
8359                         ins->sreg1 = args [0]->dreg;
8360                         ins->sreg2 = args [1]->dreg;
8361                         MONO_ADD_INS (cfg->cbb, ins);
8362                 }
8363
8364 #if 0
8365                 /* OP_FREM is not IEEE compatible */
8366                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8367                         MONO_INST_NEW (cfg, ins, OP_FREM);
8368                         ins->inst_i0 = args [0];
8369                         ins->inst_i1 = args [1];
8370                 }
8371 #endif
8372         }
8373
8374         return ins;
8375 }
8376 #endif
8377
8378 gboolean
8379 mono_arch_print_tree (MonoInst *tree, int arity)
8380 {
8381         return 0;
8382 }
8383
8384 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8385
8386 mgreg_t
8387 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8388 {
8389         switch (reg) {
8390         case AMD64_RCX: return ctx->rcx;
8391         case AMD64_RDX: return ctx->rdx;
8392         case AMD64_RBX: return ctx->rbx;
8393         case AMD64_RBP: return ctx->rbp;
8394         case AMD64_RSP: return ctx->rsp;
8395         default:
8396                 return _CTX_REG (ctx, rax, reg);
8397         }
8398 }
8399
8400 void
8401 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8402 {
8403         switch (reg) {
8404         case AMD64_RCX:
8405                 ctx->rcx = val;
8406                 break;
8407         case AMD64_RDX:
8408                 ctx->rdx = val;
8409                 break;
8410         case AMD64_RBX:
8411                 ctx->rbx = val;
8412                 break;
8413         case AMD64_RBP:
8414                 ctx->rbp = val;
8415                 break;
8416         case AMD64_RSP:
8417                 ctx->rsp = val;
8418                 break;
8419         default:
8420                 _CTX_REG (ctx, rax, reg) = val;
8421         }
8422 }
8423
8424 gpointer
8425 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8426 {
8427         gpointer *sp, old_value;
8428         char *bp;
8429
8430         /*Load the spvar*/
8431         bp = MONO_CONTEXT_GET_BP (ctx);
8432         sp = *(gpointer*)(bp + clause->exvar_offset);
8433
8434         old_value = *sp;
8435         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8436                 return old_value;
8437
8438         *sp = new_value;
8439
8440         return old_value;
8441 }
8442
8443 /*
8444  * mono_arch_emit_load_aotconst:
8445  *
8446  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8447  * TARGET from the mscorlib GOT in full-aot code.
8448  * On AMD64, the result is placed into R11.
8449  */
8450 guint8*
8451 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8452 {
8453         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8454         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8455
8456         return code;
8457 }
8458
8459 /*
8460  * mono_arch_get_trampolines:
8461  *
8462  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8463  * for AOT.
8464  */
8465 GSList *
8466 mono_arch_get_trampolines (gboolean aot)
8467 {
8468         return mono_amd64_get_exception_trampolines (aot);
8469 }
8470
8471 /* Soft Debug support */
8472 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8473
8474 /*
8475  * mono_arch_set_breakpoint:
8476  *
8477  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8478  * The location should contain code emitted by OP_SEQ_POINT.
8479  */
8480 void
8481 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8482 {
8483         guint8 *code = ip;
8484         guint8 *orig_code = code;
8485
8486         if (ji->from_aot) {
8487                 guint32 native_offset = ip - (guint8*)ji->code_start;
8488                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8489
8490                 g_assert (info->bp_addrs [native_offset] == 0);
8491                 info->bp_addrs [native_offset] = bp_trigger_page;
8492         } else {
8493                 /*
8494                  * In production, we will use int3 (has to fix the size in the md
8495                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8496                  * instead.
8497                  */
8498                 g_assert (code [0] == 0x90);
8499                 if (breakpoint_size == 8) {
8500                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8501                 } else {
8502                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8503                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8504                 }
8505
8506                 g_assert (code - orig_code == breakpoint_size);
8507         }
8508 }
8509
8510 /*
8511  * mono_arch_clear_breakpoint:
8512  *
8513  *   Clear the breakpoint at IP.
8514  */
8515 void
8516 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8517 {
8518         guint8 *code = ip;
8519         int i;
8520
8521         if (ji->from_aot) {
8522                 guint32 native_offset = ip - (guint8*)ji->code_start;
8523                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8524
8525                 g_assert (info->bp_addrs [native_offset] == 0);
8526                 info->bp_addrs [native_offset] = info;
8527         } else {
8528                 for (i = 0; i < breakpoint_size; ++i)
8529                         x86_nop (code);
8530         }
8531 }
8532
8533 gboolean
8534 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8535 {
8536 #ifdef HOST_WIN32
8537         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8538         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8539                 return TRUE;
8540         else
8541                 return FALSE;
8542 #else
8543         siginfo_t* sinfo = (siginfo_t*) info;
8544         /* Sometimes the address is off by 4 */
8545         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8546                 return TRUE;
8547         else
8548                 return FALSE;
8549 #endif
8550 }
8551
8552 /*
8553  * mono_arch_skip_breakpoint:
8554  *
8555  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8556  * we resume, the instruction is not executed again.
8557  */
8558 void
8559 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8560 {
8561         if (ji->from_aot) {
8562                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8563                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8564         } else {
8565                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8566         }
8567 }
8568
8569 /*
8570  * mono_arch_start_single_stepping:
8571  *
8572  *   Start single stepping.
8573  */
8574 void
8575 mono_arch_start_single_stepping (void)
8576 {
8577         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8578 }
8579
8580 /*
8581  * mono_arch_stop_single_stepping:
8582  *
8583  *   Stop single stepping.
8584  */
8585 void
8586 mono_arch_stop_single_stepping (void)
8587 {
8588         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8589 }
8590
8591 /*
8592  * mono_arch_is_single_step_event:
8593  *
8594  *   Return whenever the machine state in SIGCTX corresponds to a single
8595  * step event.
8596  */
8597 gboolean
8598 mono_arch_is_single_step_event (void *info, void *sigctx)
8599 {
8600 #ifdef HOST_WIN32
8601         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8602         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8603                 return TRUE;
8604         else
8605                 return FALSE;
8606 #else
8607         siginfo_t* sinfo = (siginfo_t*) info;
8608         /* Sometimes the address is off by 4 */
8609         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8610                 return TRUE;
8611         else
8612                 return FALSE;
8613 #endif
8614 }
8615
8616 /*
8617  * mono_arch_skip_single_step:
8618  *
8619  *   Modify CTX so the ip is placed after the single step trigger instruction,
8620  * we resume, the instruction is not executed again.
8621  */
8622 void
8623 mono_arch_skip_single_step (MonoContext *ctx)
8624 {
8625         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8626 }
8627
8628 /*
8629  * mono_arch_create_seq_point_info:
8630  *
8631  *   Return a pointer to a data structure which is used by the sequence
8632  * point implementation in AOTed code.
8633  */
8634 gpointer
8635 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8636 {
8637         SeqPointInfo *info;
8638         MonoJitInfo *ji;
8639         int i;
8640
8641         // FIXME: Add a free function
8642
8643         mono_domain_lock (domain);
8644         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8645                                                                 code);
8646         mono_domain_unlock (domain);
8647
8648         if (!info) {
8649                 ji = mono_jit_info_table_find (domain, (char*)code);
8650                 g_assert (ji);
8651
8652                 // FIXME: Optimize the size
8653                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8654
8655                 info->ss_trigger_page = ss_trigger_page;
8656                 info->bp_trigger_page = bp_trigger_page;
8657                 /* Initialize to a valid address */
8658                 for (i = 0; i < ji->code_size; ++i)
8659                         info->bp_addrs [i] = info;
8660
8661                 mono_domain_lock (domain);
8662                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8663                                                          code, info);
8664                 mono_domain_unlock (domain);
8665         }
8666
8667         return info;
8668 }
8669
8670 void
8671 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8672 {
8673         ext->lmf.previous_lmf = prev_lmf;
8674         /* Mark that this is a MonoLMFExt */
8675         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8676         ext->lmf.rsp = (gssize)ext;
8677 }
8678
8679 #endif
8680
8681 gboolean
8682 mono_arch_opcode_supported (int opcode)
8683 {
8684         switch (opcode) {
8685         case OP_ATOMIC_ADD_I4:
8686         case OP_ATOMIC_ADD_I8:
8687         case OP_ATOMIC_EXCHANGE_I4:
8688         case OP_ATOMIC_EXCHANGE_I8:
8689         case OP_ATOMIC_CAS_I4:
8690         case OP_ATOMIC_CAS_I8:
8691         case OP_ATOMIC_LOAD_I1:
8692         case OP_ATOMIC_LOAD_I2:
8693         case OP_ATOMIC_LOAD_I4:
8694         case OP_ATOMIC_LOAD_I8:
8695         case OP_ATOMIC_LOAD_U1:
8696         case OP_ATOMIC_LOAD_U2:
8697         case OP_ATOMIC_LOAD_U4:
8698         case OP_ATOMIC_LOAD_U8:
8699         case OP_ATOMIC_LOAD_R4:
8700         case OP_ATOMIC_LOAD_R8:
8701         case OP_ATOMIC_STORE_I1:
8702         case OP_ATOMIC_STORE_I2:
8703         case OP_ATOMIC_STORE_I4:
8704         case OP_ATOMIC_STORE_I8:
8705         case OP_ATOMIC_STORE_U1:
8706         case OP_ATOMIC_STORE_U2:
8707         case OP_ATOMIC_STORE_U4:
8708         case OP_ATOMIC_STORE_U8:
8709         case OP_ATOMIC_STORE_R4:
8710         case OP_ATOMIC_STORE_R8:
8711                 return TRUE;
8712         default:
8713                 return FALSE;
8714         }
8715 }