2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-mmap.h>
31 #include "mini-amd64.h"
32 #include "cpu-amd64.h"
33 #include "debugger-agent.h"
36 * Can't define this in mini-amd64.h cause that would turn on the generic code in
39 #define MONO_ARCH_IMT_REG AMD64_R11
41 static gint lmf_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
43 static gint appdomain_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
67 static CRITICAL_SECTION mini_arch_mutex;
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 * The code generated for sequence points reads from this location, which is
74 * made read-only when single stepping is enabled.
76 static gpointer ss_trigger_page;
78 /* Enabled breakpoints read from this trigger page */
79 static gpointer bp_trigger_page;
81 /* The size of the breakpoint sequence */
82 static int breakpoint_size;
84 /* The size of the breakpoint instruction causing the actual fault */
85 static int breakpoint_fault_size;
87 /* The size of the single step instruction causing the actual fault */
88 static int single_step_fault_size;
91 /* On Win64 always reserve first 32 bytes for first four arguments */
92 #define ARGS_OFFSET 48
94 #define ARGS_OFFSET 16
96 #define GP_SCRATCH_REG AMD64_R11
99 * AMD64 register usage:
100 * - callee saved registers are used for global register allocation
101 * - %r11 is used for materializing 64 bit constants in opcodes
102 * - the rest is used for local allocation
106 * Floating point comparison results:
116 mono_arch_regname (int reg)
119 case AMD64_RAX: return "%rax";
120 case AMD64_RBX: return "%rbx";
121 case AMD64_RCX: return "%rcx";
122 case AMD64_RDX: return "%rdx";
123 case AMD64_RSP: return "%rsp";
124 case AMD64_RBP: return "%rbp";
125 case AMD64_RDI: return "%rdi";
126 case AMD64_RSI: return "%rsi";
127 case AMD64_R8: return "%r8";
128 case AMD64_R9: return "%r9";
129 case AMD64_R10: return "%r10";
130 case AMD64_R11: return "%r11";
131 case AMD64_R12: return "%r12";
132 case AMD64_R13: return "%r13";
133 case AMD64_R14: return "%r14";
134 case AMD64_R15: return "%r15";
139 static const char * packed_xmmregs [] = {
140 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
141 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
144 static const char * single_xmmregs [] = {
145 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
146 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
150 mono_arch_fregname (int reg)
152 if (reg < AMD64_XMM_NREG)
153 return single_xmmregs [reg];
159 mono_arch_xregname (int reg)
161 if (reg < AMD64_XMM_NREG)
162 return packed_xmmregs [reg];
167 G_GNUC_UNUSED static void
172 G_GNUC_UNUSED static gboolean
175 static int count = 0;
178 if (!getenv ("COUNT"))
181 if (count == atoi (getenv ("COUNT"))) {
185 if (count > atoi (getenv ("COUNT"))) {
196 return debug_count ();
202 static inline gboolean
203 amd64_is_near_call (guint8 *code)
206 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
209 return code [0] == 0xe8;
213 amd64_patch (unsigned char* code, gpointer target)
218 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
223 if ((code [0] & 0xf8) == 0xb8) {
224 /* amd64_set_reg_template */
225 *(guint64*)(code + 1) = (guint64)target;
227 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
228 /* mov 0(%rip), %dreg */
229 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
231 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
232 /* call *<OFFSET>(%rip) */
233 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
235 else if ((code [0] == 0xe8)) {
237 gint64 disp = (guint8*)target - (guint8*)code;
238 g_assert (amd64_is_imm32 (disp));
239 x86_patch (code, (unsigned char*)target);
242 x86_patch (code, (unsigned char*)target);
246 mono_amd64_patch (unsigned char* code, gpointer target)
248 amd64_patch (code, target);
257 ArgValuetypeAddrInIReg,
258 ArgNone /* only in pair_storage */
266 /* Only if storage == ArgValuetypeInReg */
267 ArgStorage pair_storage [2];
276 gboolean need_stack_align;
277 gboolean vtype_retaddr;
283 #define DEBUG(a) if (cfg->verbose_level > 1) a
288 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
290 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
294 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
296 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
300 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
302 ainfo->offset = *stack_size;
304 if (*gr >= PARAM_REGS) {
305 ainfo->storage = ArgOnStack;
306 (*stack_size) += sizeof (gpointer);
309 ainfo->storage = ArgInIReg;
310 ainfo->reg = param_regs [*gr];
316 #define FLOAT_PARAM_REGS 4
318 #define FLOAT_PARAM_REGS 8
322 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
324 ainfo->offset = *stack_size;
326 if (*gr >= FLOAT_PARAM_REGS) {
327 ainfo->storage = ArgOnStack;
328 (*stack_size) += sizeof (gpointer);
331 /* A double register */
333 ainfo->storage = ArgInDoubleSSEReg;
335 ainfo->storage = ArgInFloatSSEReg;
341 typedef enum ArgumentClass {
349 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
351 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
354 ptype = mini_type_get_underlying_type (NULL, type);
355 switch (ptype->type) {
356 case MONO_TYPE_BOOLEAN:
366 case MONO_TYPE_STRING:
367 case MONO_TYPE_OBJECT:
368 case MONO_TYPE_CLASS:
369 case MONO_TYPE_SZARRAY:
371 case MONO_TYPE_FNPTR:
372 case MONO_TYPE_ARRAY:
375 class2 = ARG_CLASS_INTEGER;
380 class2 = ARG_CLASS_INTEGER;
382 class2 = ARG_CLASS_SSE;
386 case MONO_TYPE_TYPEDBYREF:
387 g_assert_not_reached ();
389 case MONO_TYPE_GENERICINST:
390 if (!mono_type_generic_inst_is_valuetype (ptype)) {
391 class2 = ARG_CLASS_INTEGER;
395 case MONO_TYPE_VALUETYPE: {
396 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
399 for (i = 0; i < info->num_fields; ++i) {
401 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
406 g_assert_not_reached ();
410 if (class1 == class2)
412 else if (class1 == ARG_CLASS_NO_CLASS)
414 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
415 class1 = ARG_CLASS_MEMORY;
416 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
417 class1 = ARG_CLASS_INTEGER;
419 class1 = ARG_CLASS_SSE;
425 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
427 guint32 *gr, guint32 *fr, guint32 *stack_size)
429 guint32 size, quad, nquads, i;
430 ArgumentClass args [2];
431 MonoMarshalType *info = NULL;
433 MonoGenericSharingContext tmp_gsctx;
434 gboolean pass_on_stack = FALSE;
437 * The gsctx currently contains no data, it is only used for checking whenever
438 * open types are allowed, some callers like mono_arch_get_argument_info ()
439 * don't pass it to us, so work around that.
444 klass = mono_class_from_mono_type (type);
445 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
447 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
448 /* We pass and return vtypes of size 8 in a register */
449 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
450 pass_on_stack = TRUE;
454 pass_on_stack = TRUE;
459 /* Allways pass in memory */
460 ainfo->offset = *stack_size;
461 *stack_size += ALIGN_TO (size, 8);
462 ainfo->storage = ArgOnStack;
467 /* FIXME: Handle structs smaller than 8 bytes */
468 //if ((size % 8) != 0)
477 /* Always pass in 1 or 2 integer registers */
478 args [0] = ARG_CLASS_INTEGER;
479 args [1] = ARG_CLASS_INTEGER;
480 /* Only the simplest cases are supported */
481 if (is_return && nquads != 1) {
482 args [0] = ARG_CLASS_MEMORY;
483 args [1] = ARG_CLASS_MEMORY;
487 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
488 * The X87 and SSEUP stuff is left out since there are no such types in
491 info = mono_marshal_load_type_info (klass);
495 if (info->native_size > 16) {
496 ainfo->offset = *stack_size;
497 *stack_size += ALIGN_TO (info->native_size, 8);
498 ainfo->storage = ArgOnStack;
503 switch (info->native_size) {
504 case 1: case 2: case 4: case 8:
508 ainfo->storage = ArgOnStack;
509 ainfo->offset = *stack_size;
510 *stack_size += ALIGN_TO (info->native_size, 8);
513 ainfo->storage = ArgValuetypeAddrInIReg;
515 if (*gr < PARAM_REGS) {
516 ainfo->pair_storage [0] = ArgInIReg;
517 ainfo->pair_regs [0] = param_regs [*gr];
521 ainfo->pair_storage [0] = ArgOnStack;
522 ainfo->offset = *stack_size;
531 args [0] = ARG_CLASS_NO_CLASS;
532 args [1] = ARG_CLASS_NO_CLASS;
533 for (quad = 0; quad < nquads; ++quad) {
536 ArgumentClass class1;
538 if (info->num_fields == 0)
539 class1 = ARG_CLASS_MEMORY;
541 class1 = ARG_CLASS_NO_CLASS;
542 for (i = 0; i < info->num_fields; ++i) {
543 size = mono_marshal_type_size (info->fields [i].field->type,
544 info->fields [i].mspec,
545 &align, TRUE, klass->unicode);
546 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
547 /* Unaligned field */
551 /* Skip fields in other quad */
552 if ((quad == 0) && (info->fields [i].offset >= 8))
554 if ((quad == 1) && (info->fields [i].offset < 8))
557 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
559 g_assert (class1 != ARG_CLASS_NO_CLASS);
560 args [quad] = class1;
564 /* Post merger cleanup */
565 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
566 args [0] = args [1] = ARG_CLASS_MEMORY;
568 /* Allocate registers */
573 ainfo->storage = ArgValuetypeInReg;
574 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
575 for (quad = 0; quad < nquads; ++quad) {
576 switch (args [quad]) {
577 case ARG_CLASS_INTEGER:
578 if (*gr >= PARAM_REGS)
579 args [quad] = ARG_CLASS_MEMORY;
581 ainfo->pair_storage [quad] = ArgInIReg;
583 ainfo->pair_regs [quad] = return_regs [*gr];
585 ainfo->pair_regs [quad] = param_regs [*gr];
590 if (*fr >= FLOAT_PARAM_REGS)
591 args [quad] = ARG_CLASS_MEMORY;
593 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
594 ainfo->pair_regs [quad] = *fr;
598 case ARG_CLASS_MEMORY:
601 g_assert_not_reached ();
605 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
606 /* Revert possible register assignments */
610 ainfo->offset = *stack_size;
612 *stack_size += ALIGN_TO (info->native_size, 8);
614 *stack_size += nquads * sizeof (gpointer);
615 ainfo->storage = ArgOnStack;
623 * Obtain information about a call according to the calling convention.
624 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
625 * Draft Version 0.23" document for more information.
628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
632 int n = sig->hasthis + sig->param_count;
633 guint32 stack_size = 0;
637 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
639 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
648 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
649 switch (ret_type->type) {
650 case MONO_TYPE_BOOLEAN:
661 case MONO_TYPE_FNPTR:
662 case MONO_TYPE_CLASS:
663 case MONO_TYPE_OBJECT:
664 case MONO_TYPE_SZARRAY:
665 case MONO_TYPE_ARRAY:
666 case MONO_TYPE_STRING:
667 cinfo->ret.storage = ArgInIReg;
668 cinfo->ret.reg = AMD64_RAX;
672 cinfo->ret.storage = ArgInIReg;
673 cinfo->ret.reg = AMD64_RAX;
676 cinfo->ret.storage = ArgInFloatSSEReg;
677 cinfo->ret.reg = AMD64_XMM0;
680 cinfo->ret.storage = ArgInDoubleSSEReg;
681 cinfo->ret.reg = AMD64_XMM0;
683 case MONO_TYPE_GENERICINST:
684 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
685 cinfo->ret.storage = ArgInIReg;
686 cinfo->ret.reg = AMD64_RAX;
690 case MONO_TYPE_VALUETYPE: {
691 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
693 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
694 if (cinfo->ret.storage == ArgOnStack) {
695 cinfo->vtype_retaddr = TRUE;
696 /* The caller passes the address where the value is stored */
697 add_general (&gr, &stack_size, &cinfo->ret);
701 case MONO_TYPE_TYPEDBYREF:
702 /* Same as a valuetype with size 24 */
703 add_general (&gr, &stack_size, &cinfo->ret);
709 g_error ("Can't handle as return value 0x%x", sig->ret->type);
715 add_general (&gr, &stack_size, cinfo->args + 0);
717 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
719 fr = FLOAT_PARAM_REGS;
721 /* Emit the signature cookie just before the implicit arguments */
722 add_general (&gr, &stack_size, &cinfo->sig_cookie);
725 for (i = 0; i < sig->param_count; ++i) {
726 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
730 /* The float param registers and other param registers must be the same index on Windows x64.*/
737 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
738 /* We allways pass the sig cookie on the stack for simplicity */
740 * Prevent implicit arguments + the sig cookie from being passed
744 fr = FLOAT_PARAM_REGS;
746 /* Emit the signature cookie just before the implicit arguments */
747 add_general (&gr, &stack_size, &cinfo->sig_cookie);
750 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
751 switch (ptype->type) {
752 case MONO_TYPE_BOOLEAN:
755 add_general (&gr, &stack_size, ainfo);
760 add_general (&gr, &stack_size, ainfo);
764 add_general (&gr, &stack_size, ainfo);
769 case MONO_TYPE_FNPTR:
770 case MONO_TYPE_CLASS:
771 case MONO_TYPE_OBJECT:
772 case MONO_TYPE_STRING:
773 case MONO_TYPE_SZARRAY:
774 case MONO_TYPE_ARRAY:
775 add_general (&gr, &stack_size, ainfo);
777 case MONO_TYPE_GENERICINST:
778 if (!mono_type_generic_inst_is_valuetype (ptype)) {
779 add_general (&gr, &stack_size, ainfo);
783 case MONO_TYPE_VALUETYPE:
784 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
786 case MONO_TYPE_TYPEDBYREF:
788 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
790 stack_size += sizeof (MonoTypedRef);
791 ainfo->storage = ArgOnStack;
796 add_general (&gr, &stack_size, ainfo);
799 add_float (&fr, &stack_size, ainfo, FALSE);
802 add_float (&fr, &stack_size, ainfo, TRUE);
805 g_assert_not_reached ();
809 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
811 fr = FLOAT_PARAM_REGS;
813 /* Emit the signature cookie just before the implicit arguments */
814 add_general (&gr, &stack_size, &cinfo->sig_cookie);
818 // There always is 32 bytes reserved on the stack when calling on Winx64
822 if (stack_size & 0x8) {
823 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
824 cinfo->need_stack_align = TRUE;
828 cinfo->stack_usage = stack_size;
829 cinfo->reg_usage = gr;
830 cinfo->freg_usage = fr;
835 * mono_arch_get_argument_info:
836 * @csig: a method signature
837 * @param_count: the number of parameters to consider
838 * @arg_info: an array to store the result infos
840 * Gathers information on parameters such as size, alignment and
841 * padding. arg_info should be large enought to hold param_count + 1 entries.
843 * Returns the size of the argument area on the stack.
846 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
849 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
850 guint32 args_size = cinfo->stack_usage;
852 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
854 arg_info [0].offset = 0;
857 for (k = 0; k < param_count; k++) {
858 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
860 arg_info [k + 1].size = 0;
869 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
872 __asm__ __volatile__ ("cpuid"
873 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
887 * Initialize the cpu to execute managed code.
890 mono_arch_cpu_init (void)
895 /* spec compliance requires running with double precision */
896 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
897 fpcw &= ~X86_FPCW_PRECC_MASK;
898 fpcw |= X86_FPCW_PREC_DOUBLE;
899 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
900 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
902 /* TODO: This is crashing on Win64 right now.
903 * _control87 (_PC_53, MCW_PC);
909 * Initialize architecture specific code.
912 mono_arch_init (void)
916 InitializeCriticalSection (&mini_arch_mutex);
918 #ifdef MONO_ARCH_NOMAP32BIT
919 flags = MONO_MMAP_READ;
920 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
921 breakpoint_size = 13;
922 breakpoint_fault_size = 3;
923 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
924 single_step_fault_size = 5;
926 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
927 /* amd64_mov_reg_mem () */
929 breakpoint_fault_size = 8;
930 single_step_fault_size = 8;
933 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
934 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
935 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
939 * Cleanup architecture specific code.
942 mono_arch_cleanup (void)
944 DeleteCriticalSection (&mini_arch_mutex);
948 * This function returns the optimizations supported on this cpu.
951 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
953 int eax, ebx, ecx, edx;
959 /* Feature Flags function, flags returned in EDX. */
960 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
961 if (edx & (1 << 15)) {
962 opts |= MONO_OPT_CMOV;
964 opts |= MONO_OPT_FCMOV;
966 *exclude_mask |= MONO_OPT_FCMOV;
968 *exclude_mask |= MONO_OPT_CMOV;
975 * This function test for all SSE functions supported.
977 * Returns a bitmask corresponding to all supported versions.
981 mono_arch_cpu_enumerate_simd_versions (void)
983 int eax, ebx, ecx, edx;
984 guint32 sse_opts = 0;
986 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
988 sse_opts |= SIMD_VERSION_SSE1;
990 sse_opts |= SIMD_VERSION_SSE2;
992 sse_opts |= SIMD_VERSION_SSE3;
994 sse_opts |= SIMD_VERSION_SSSE3;
996 sse_opts |= SIMD_VERSION_SSE41;
998 sse_opts |= SIMD_VERSION_SSE42;
1001 /* Yes, all this needs to be done to check for sse4a.
1002 See: "Amd: CPUID Specification"
1004 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1005 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1006 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1007 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1009 sse_opts |= SIMD_VERSION_SSE4a;
1019 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1024 for (i = 0; i < cfg->num_varinfo; i++) {
1025 MonoInst *ins = cfg->varinfo [i];
1026 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1029 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1032 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1033 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1036 if (mono_is_regsize_var (ins->inst_vtype)) {
1037 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1038 g_assert (i == vmv->idx);
1039 vars = g_list_prepend (vars, vmv);
1043 vars = mono_varlist_sort (cfg, vars, 0);
1049 * mono_arch_compute_omit_fp:
1051 * Determine whenever the frame pointer can be eliminated.
1054 mono_arch_compute_omit_fp (MonoCompile *cfg)
1056 MonoMethodSignature *sig;
1057 MonoMethodHeader *header;
1061 if (cfg->arch.omit_fp_computed)
1064 header = cfg->header;
1066 sig = mono_method_signature (cfg->method);
1068 if (!cfg->arch.cinfo)
1069 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1070 cinfo = cfg->arch.cinfo;
1073 * FIXME: Remove some of the restrictions.
1075 cfg->arch.omit_fp = TRUE;
1076 cfg->arch.omit_fp_computed = TRUE;
1078 if (cfg->disable_omit_fp)
1079 cfg->arch.omit_fp = FALSE;
1081 if (!debug_omit_fp ())
1082 cfg->arch.omit_fp = FALSE;
1084 if (cfg->method->save_lmf)
1085 cfg->arch.omit_fp = FALSE;
1087 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1088 cfg->arch.omit_fp = FALSE;
1089 if (header->num_clauses)
1090 cfg->arch.omit_fp = FALSE;
1091 if (cfg->param_area)
1092 cfg->arch.omit_fp = FALSE;
1093 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1094 cfg->arch.omit_fp = FALSE;
1095 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1096 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1097 cfg->arch.omit_fp = FALSE;
1098 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1099 ArgInfo *ainfo = &cinfo->args [i];
1101 if (ainfo->storage == ArgOnStack) {
1103 * The stack offset can only be determined when the frame
1106 cfg->arch.omit_fp = FALSE;
1111 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1112 MonoInst *ins = cfg->varinfo [i];
1115 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1120 mono_arch_get_global_int_regs (MonoCompile *cfg)
1124 mono_arch_compute_omit_fp (cfg);
1126 if (cfg->globalra) {
1127 if (cfg->arch.omit_fp)
1128 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1130 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1131 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1132 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1133 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1134 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1136 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1137 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1138 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1139 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1140 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1141 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1142 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1143 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1145 if (cfg->arch.omit_fp)
1146 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1148 /* We use the callee saved registers for global allocation */
1149 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1150 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1151 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1152 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1153 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1155 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1156 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1164 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1169 /* All XMM registers */
1170 for (i = 0; i < 16; ++i)
1171 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1177 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1179 static GList *r = NULL;
1184 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1185 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1186 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1187 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1188 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1189 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1191 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1192 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1193 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1194 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1195 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1196 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1197 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1198 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1200 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1207 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1210 static GList *r = NULL;
1215 for (i = 0; i < AMD64_XMM_NREG; ++i)
1216 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1218 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1225 * mono_arch_regalloc_cost:
1227 * Return the cost, in number of memory references, of the action of
1228 * allocating the variable VMV into a register during global register
1232 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1234 MonoInst *ins = cfg->varinfo [vmv->idx];
1236 if (cfg->method->save_lmf)
1237 /* The register is already saved */
1238 /* substract 1 for the invisible store in the prolog */
1239 return (ins->opcode == OP_ARG) ? 0 : 1;
1242 return (ins->opcode == OP_ARG) ? 1 : 2;
1246 * mono_arch_fill_argument_info:
1248 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1252 mono_arch_fill_argument_info (MonoCompile *cfg)
1254 MonoMethodSignature *sig;
1255 MonoMethodHeader *header;
1260 header = cfg->header;
1262 sig = mono_method_signature (cfg->method);
1264 cinfo = cfg->arch.cinfo;
1267 * Contrary to mono_arch_allocate_vars (), the information should describe
1268 * where the arguments are at the beginning of the method, not where they can be
1269 * accessed during the execution of the method. The later makes no sense for the
1270 * global register allocator, since a variable can be in more than one location.
1272 if (sig->ret->type != MONO_TYPE_VOID) {
1273 switch (cinfo->ret.storage) {
1275 case ArgInFloatSSEReg:
1276 case ArgInDoubleSSEReg:
1277 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1278 cfg->vret_addr->opcode = OP_REGVAR;
1279 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1282 cfg->ret->opcode = OP_REGVAR;
1283 cfg->ret->inst_c0 = cinfo->ret.reg;
1286 case ArgValuetypeInReg:
1287 cfg->ret->opcode = OP_REGOFFSET;
1288 cfg->ret->inst_basereg = -1;
1289 cfg->ret->inst_offset = -1;
1292 g_assert_not_reached ();
1296 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1297 ArgInfo *ainfo = &cinfo->args [i];
1300 ins = cfg->args [i];
1302 if (sig->hasthis && (i == 0))
1303 arg_type = &mono_defaults.object_class->byval_arg;
1305 arg_type = sig->params [i - sig->hasthis];
1307 switch (ainfo->storage) {
1309 case ArgInFloatSSEReg:
1310 case ArgInDoubleSSEReg:
1311 ins->opcode = OP_REGVAR;
1312 ins->inst_c0 = ainfo->reg;
1315 ins->opcode = OP_REGOFFSET;
1316 ins->inst_basereg = -1;
1317 ins->inst_offset = -1;
1319 case ArgValuetypeInReg:
1321 ins->opcode = OP_NOP;
1324 g_assert_not_reached ();
1330 mono_arch_allocate_vars (MonoCompile *cfg)
1332 MonoMethodSignature *sig;
1333 MonoMethodHeader *header;
1336 guint32 locals_stack_size, locals_stack_align;
1340 header = cfg->header;
1342 sig = mono_method_signature (cfg->method);
1344 cinfo = cfg->arch.cinfo;
1346 mono_arch_compute_omit_fp (cfg);
1349 * We use the ABI calling conventions for managed code as well.
1350 * Exception: valuetypes are only sometimes passed or returned in registers.
1354 * The stack looks like this:
1355 * <incoming arguments passed on the stack>
1357 * <lmf/caller saved registers>
1360 * <localloc area> -> grows dynamically
1364 if (cfg->arch.omit_fp) {
1365 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1366 cfg->frame_reg = AMD64_RSP;
1369 /* Locals are allocated backwards from %fp */
1370 cfg->frame_reg = AMD64_RBP;
1374 if (cfg->method->save_lmf) {
1375 /* Reserve stack space for saving LMF */
1376 if (cfg->arch.omit_fp) {
1377 cfg->arch.lmf_offset = offset;
1378 offset += sizeof (MonoLMF);
1381 offset += sizeof (MonoLMF);
1382 cfg->arch.lmf_offset = -offset;
1385 if (cfg->arch.omit_fp)
1386 cfg->arch.reg_save_area_offset = offset;
1387 /* Reserve space for caller saved registers */
1388 for (i = 0; i < AMD64_NREG; ++i)
1389 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1390 offset += sizeof (gpointer);
1394 if (sig->ret->type != MONO_TYPE_VOID) {
1395 switch (cinfo->ret.storage) {
1397 case ArgInFloatSSEReg:
1398 case ArgInDoubleSSEReg:
1399 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1400 if (cfg->globalra) {
1401 cfg->vret_addr->opcode = OP_REGVAR;
1402 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1404 /* The register is volatile */
1405 cfg->vret_addr->opcode = OP_REGOFFSET;
1406 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1407 if (cfg->arch.omit_fp) {
1408 cfg->vret_addr->inst_offset = offset;
1412 cfg->vret_addr->inst_offset = -offset;
1414 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1415 printf ("vret_addr =");
1416 mono_print_ins (cfg->vret_addr);
1421 cfg->ret->opcode = OP_REGVAR;
1422 cfg->ret->inst_c0 = cinfo->ret.reg;
1425 case ArgValuetypeInReg:
1426 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1427 cfg->ret->opcode = OP_REGOFFSET;
1428 cfg->ret->inst_basereg = cfg->frame_reg;
1429 if (cfg->arch.omit_fp) {
1430 cfg->ret->inst_offset = offset;
1434 cfg->ret->inst_offset = - offset;
1438 g_assert_not_reached ();
1441 cfg->ret->dreg = cfg->ret->inst_c0;
1444 /* Allocate locals */
1445 if (!cfg->globalra) {
1446 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1447 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1448 char *mname = mono_method_full_name (cfg->method, TRUE);
1449 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1450 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1455 if (locals_stack_align) {
1456 offset += (locals_stack_align - 1);
1457 offset &= ~(locals_stack_align - 1);
1459 if (cfg->arch.omit_fp) {
1460 cfg->locals_min_stack_offset = offset;
1461 cfg->locals_max_stack_offset = offset + locals_stack_size;
1463 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1464 cfg->locals_max_stack_offset = - offset;
1467 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1468 if (offsets [i] != -1) {
1469 MonoInst *ins = cfg->varinfo [i];
1470 ins->opcode = OP_REGOFFSET;
1471 ins->inst_basereg = cfg->frame_reg;
1472 if (cfg->arch.omit_fp)
1473 ins->inst_offset = (offset + offsets [i]);
1475 ins->inst_offset = - (offset + offsets [i]);
1476 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1479 offset += locals_stack_size;
1482 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1483 g_assert (!cfg->arch.omit_fp);
1484 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1485 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1488 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489 ins = cfg->args [i];
1490 if (ins->opcode != OP_REGVAR) {
1491 ArgInfo *ainfo = &cinfo->args [i];
1492 gboolean inreg = TRUE;
1495 if (sig->hasthis && (i == 0))
1496 arg_type = &mono_defaults.object_class->byval_arg;
1498 arg_type = sig->params [i - sig->hasthis];
1500 if (cfg->globalra) {
1501 /* The new allocator needs info about the original locations of the arguments */
1502 switch (ainfo->storage) {
1504 case ArgInFloatSSEReg:
1505 case ArgInDoubleSSEReg:
1506 ins->opcode = OP_REGVAR;
1507 ins->inst_c0 = ainfo->reg;
1510 g_assert (!cfg->arch.omit_fp);
1511 ins->opcode = OP_REGOFFSET;
1512 ins->inst_basereg = cfg->frame_reg;
1513 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1515 case ArgValuetypeInReg:
1516 ins->opcode = OP_REGOFFSET;
1517 ins->inst_basereg = cfg->frame_reg;
1518 /* These arguments are saved to the stack in the prolog */
1519 offset = ALIGN_TO (offset, sizeof (gpointer));
1520 if (cfg->arch.omit_fp) {
1521 ins->inst_offset = offset;
1522 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1524 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1525 ins->inst_offset = - offset;
1529 g_assert_not_reached ();
1535 /* FIXME: Allocate volatile arguments to registers */
1536 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1540 * Under AMD64, all registers used to pass arguments to functions
1541 * are volatile across calls.
1542 * FIXME: Optimize this.
1544 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1547 ins->opcode = OP_REGOFFSET;
1549 switch (ainfo->storage) {
1551 case ArgInFloatSSEReg:
1552 case ArgInDoubleSSEReg:
1554 ins->opcode = OP_REGVAR;
1555 ins->dreg = ainfo->reg;
1559 g_assert (!cfg->arch.omit_fp);
1560 ins->opcode = OP_REGOFFSET;
1561 ins->inst_basereg = cfg->frame_reg;
1562 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1564 case ArgValuetypeInReg:
1566 case ArgValuetypeAddrInIReg: {
1568 g_assert (!cfg->arch.omit_fp);
1570 MONO_INST_NEW (cfg, indir, 0);
1571 indir->opcode = OP_REGOFFSET;
1572 if (ainfo->pair_storage [0] == ArgInIReg) {
1573 indir->inst_basereg = cfg->frame_reg;
1574 offset = ALIGN_TO (offset, sizeof (gpointer));
1575 offset += (sizeof (gpointer));
1576 indir->inst_offset = - offset;
1579 indir->inst_basereg = cfg->frame_reg;
1580 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1583 ins->opcode = OP_VTARG_ADDR;
1584 ins->inst_left = indir;
1592 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1593 ins->opcode = OP_REGOFFSET;
1594 ins->inst_basereg = cfg->frame_reg;
1595 /* These arguments are saved to the stack in the prolog */
1596 offset = ALIGN_TO (offset, sizeof (gpointer));
1597 if (cfg->arch.omit_fp) {
1598 ins->inst_offset = offset;
1599 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1600 // Arguments are yet supported by the stack map creation code
1601 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1603 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1604 ins->inst_offset = - offset;
1605 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1611 cfg->stack_offset = offset;
1615 mono_arch_create_vars (MonoCompile *cfg)
1617 MonoMethodSignature *sig;
1620 sig = mono_method_signature (cfg->method);
1622 if (!cfg->arch.cinfo)
1623 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1624 cinfo = cfg->arch.cinfo;
1626 if (cinfo->ret.storage == ArgValuetypeInReg)
1627 cfg->ret_var_is_local = TRUE;
1629 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1630 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1631 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1632 printf ("vret_addr = ");
1633 mono_print_ins (cfg->vret_addr);
1637 if (cfg->gen_seq_points) {
1640 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1641 ins->flags |= MONO_INST_VOLATILE;
1642 cfg->arch.ss_trigger_page_var = ins;
1645 #ifdef MONO_AMD64_NO_PUSHES
1647 * When this is set, we pass arguments on the stack by moves, and by allocating
1648 * a bigger stack frame, instead of pushes.
1649 * Pushes complicate exception handling because the arguments on the stack have
1650 * to be popped each time a frame is unwound. They also make fp elimination
1652 * FIXME: This doesn't work inside filter/finally clauses, since those execute
1653 * on a new frame which doesn't include a param area.
1655 cfg->arch.no_pushes = TRUE;
1660 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1666 MONO_INST_NEW (cfg, ins, OP_MOVE);
1667 ins->dreg = mono_alloc_ireg (cfg);
1668 ins->sreg1 = tree->dreg;
1669 MONO_ADD_INS (cfg->cbb, ins);
1670 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1672 case ArgInFloatSSEReg:
1673 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1674 ins->dreg = mono_alloc_freg (cfg);
1675 ins->sreg1 = tree->dreg;
1676 MONO_ADD_INS (cfg->cbb, ins);
1678 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1680 case ArgInDoubleSSEReg:
1681 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1682 ins->dreg = mono_alloc_freg (cfg);
1683 ins->sreg1 = tree->dreg;
1684 MONO_ADD_INS (cfg->cbb, ins);
1686 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1690 g_assert_not_reached ();
1695 arg_storage_to_load_membase (ArgStorage storage)
1699 return OP_LOAD_MEMBASE;
1700 case ArgInDoubleSSEReg:
1701 return OP_LOADR8_MEMBASE;
1702 case ArgInFloatSSEReg:
1703 return OP_LOADR4_MEMBASE;
1705 g_assert_not_reached ();
1712 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1715 MonoMethodSignature *tmp_sig;
1718 if (call->tail_call)
1721 /* FIXME: Add support for signature tokens to AOT */
1722 cfg->disable_aot = TRUE;
1724 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1727 * mono_ArgIterator_Setup assumes the signature cookie is
1728 * passed first and all the arguments which were before it are
1729 * passed on the stack after the signature. So compensate by
1730 * passing a different signature.
1732 tmp_sig = mono_metadata_signature_dup (call->signature);
1733 tmp_sig->param_count -= call->signature->sentinelpos;
1734 tmp_sig->sentinelpos = 0;
1735 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1737 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1738 sig_arg->dreg = mono_alloc_ireg (cfg);
1739 sig_arg->inst_p0 = tmp_sig;
1740 MONO_ADD_INS (cfg->cbb, sig_arg);
1742 if (cfg->arch.no_pushes) {
1743 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1745 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1746 arg->sreg1 = sig_arg->dreg;
1747 MONO_ADD_INS (cfg->cbb, arg);
1751 static inline LLVMArgStorage
1752 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1756 return LLVMArgInIReg;
1760 g_assert_not_reached ();
1767 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1773 LLVMCallInfo *linfo;
1776 n = sig->param_count + sig->hasthis;
1778 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1780 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1783 * LLVM always uses the native ABI while we use our own ABI, the
1784 * only difference is the handling of vtypes:
1785 * - we only pass/receive them in registers in some cases, and only
1786 * in 1 or 2 integer registers.
1788 if (cinfo->ret.storage == ArgValuetypeInReg) {
1790 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1791 cfg->disable_llvm = TRUE;
1795 linfo->ret.storage = LLVMArgVtypeInReg;
1796 for (j = 0; j < 2; ++j)
1797 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1800 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1801 /* Vtype returned using a hidden argument */
1802 linfo->ret.storage = LLVMArgVtypeRetAddr;
1805 for (i = 0; i < n; ++i) {
1806 ainfo = cinfo->args + i;
1808 if (i >= sig->hasthis)
1809 t = sig->params [i - sig->hasthis];
1811 t = &mono_defaults.int_class->byval_arg;
1813 linfo->args [i].storage = LLVMArgNone;
1815 switch (ainfo->storage) {
1817 linfo->args [i].storage = LLVMArgInIReg;
1819 case ArgInDoubleSSEReg:
1820 case ArgInFloatSSEReg:
1821 linfo->args [i].storage = LLVMArgInFPReg;
1824 if (MONO_TYPE_ISSTRUCT (t)) {
1825 linfo->args [i].storage = LLVMArgVtypeByVal;
1827 linfo->args [i].storage = LLVMArgInIReg;
1829 if (t->type == MONO_TYPE_R4)
1830 linfo->args [i].storage = LLVMArgInFPReg;
1831 else if (t->type == MONO_TYPE_R8)
1832 linfo->args [i].storage = LLVMArgInFPReg;
1836 case ArgValuetypeInReg:
1838 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1839 cfg->disable_llvm = TRUE;
1843 linfo->args [i].storage = LLVMArgVtypeInReg;
1844 for (j = 0; j < 2; ++j)
1845 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1848 cfg->exception_message = g_strdup ("ainfo->storage");
1849 cfg->disable_llvm = TRUE;
1859 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1862 MonoMethodSignature *sig;
1863 int i, n, stack_size;
1869 sig = call->signature;
1870 n = sig->param_count + sig->hasthis;
1872 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1874 if (COMPILE_LLVM (cfg)) {
1875 /* We shouldn't be called in the llvm case */
1876 cfg->disable_llvm = TRUE;
1880 if (cinfo->need_stack_align) {
1881 if (!cfg->arch.no_pushes)
1882 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1886 * Emit all arguments which are passed on the stack to prevent register
1887 * allocation problems.
1889 if (cfg->arch.no_pushes) {
1890 for (i = 0; i < n; ++i) {
1892 ainfo = cinfo->args + i;
1894 in = call->args [i];
1896 if (sig->hasthis && i == 0)
1897 t = &mono_defaults.object_class->byval_arg;
1899 t = sig->params [i - sig->hasthis];
1901 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1903 if (t->type == MONO_TYPE_R4)
1904 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1905 else if (t->type == MONO_TYPE_R8)
1906 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1908 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1910 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1917 * Emit all parameters passed in registers in non-reverse order for better readability
1918 * and to help the optimization in emit_prolog ().
1920 for (i = 0; i < n; ++i) {
1921 ainfo = cinfo->args + i;
1923 in = call->args [i];
1925 if (ainfo->storage == ArgInIReg)
1926 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1929 for (i = n - 1; i >= 0; --i) {
1930 ainfo = cinfo->args + i;
1932 in = call->args [i];
1934 switch (ainfo->storage) {
1938 case ArgInFloatSSEReg:
1939 case ArgInDoubleSSEReg:
1940 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1943 case ArgValuetypeInReg:
1944 case ArgValuetypeAddrInIReg:
1945 if (ainfo->storage == ArgOnStack && call->tail_call) {
1946 MonoInst *call_inst = (MonoInst*)call;
1947 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1948 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1949 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1953 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1954 size = sizeof (MonoTypedRef);
1955 align = sizeof (gpointer);
1959 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1962 * Other backends use mono_type_stack_size (), but that
1963 * aligns the size to 8, which is larger than the size of
1964 * the source, leading to reads of invalid memory if the
1965 * source is at the end of address space.
1967 size = mono_class_value_size (in->klass, &align);
1970 g_assert (in->klass);
1973 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1974 arg->sreg1 = in->dreg;
1975 arg->klass = in->klass;
1976 arg->backend.size = size;
1977 arg->inst_p0 = call;
1978 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1979 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1981 MONO_ADD_INS (cfg->cbb, arg);
1984 if (cfg->arch.no_pushes) {
1987 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1988 arg->sreg1 = in->dreg;
1989 if (!sig->params [i - sig->hasthis]->byref) {
1990 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1991 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1992 arg->opcode = OP_STORER4_MEMBASE_REG;
1993 arg->inst_destbasereg = X86_ESP;
1994 arg->inst_offset = 0;
1995 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1996 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1997 arg->opcode = OP_STORER8_MEMBASE_REG;
1998 arg->inst_destbasereg = X86_ESP;
1999 arg->inst_offset = 0;
2002 MONO_ADD_INS (cfg->cbb, arg);
2007 g_assert_not_reached ();
2010 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2011 /* Emit the signature cookie just before the implicit arguments */
2012 emit_sig_cookie (cfg, call, cinfo);
2015 /* Handle the case where there are no implicit arguments */
2016 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2017 emit_sig_cookie (cfg, call, cinfo);
2019 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2022 if (cinfo->ret.storage == ArgValuetypeInReg) {
2023 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2025 * Tell the JIT to use a more efficient calling convention: call using
2026 * OP_CALL, compute the result location after the call, and save the
2029 call->vret_in_reg = TRUE;
2031 * Nullify the instruction computing the vret addr to enable
2032 * future optimizations.
2035 NULLIFY_INS (call->vret_var);
2037 if (call->tail_call)
2040 * The valuetype is in RAX:RDX after the call, need to be copied to
2041 * the stack. Push the address here, so the call instruction can
2044 if (!cfg->arch.vret_addr_loc) {
2045 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2046 /* Prevent it from being register allocated or optimized away */
2047 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2050 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2054 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2055 vtarg->sreg1 = call->vret_var->dreg;
2056 vtarg->dreg = mono_alloc_preg (cfg);
2057 MONO_ADD_INS (cfg->cbb, vtarg);
2059 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2064 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2065 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2069 if (cfg->method->save_lmf) {
2070 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2071 MONO_ADD_INS (cfg->cbb, arg);
2074 call->stack_usage = cinfo->stack_usage;
2078 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2081 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2082 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2083 int size = ins->backend.size;
2085 if (ainfo->storage == ArgValuetypeInReg) {
2089 for (part = 0; part < 2; ++part) {
2090 if (ainfo->pair_storage [part] == ArgNone)
2093 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2094 load->inst_basereg = src->dreg;
2095 load->inst_offset = part * sizeof (gpointer);
2097 switch (ainfo->pair_storage [part]) {
2099 load->dreg = mono_alloc_ireg (cfg);
2101 case ArgInDoubleSSEReg:
2102 case ArgInFloatSSEReg:
2103 load->dreg = mono_alloc_freg (cfg);
2106 g_assert_not_reached ();
2108 MONO_ADD_INS (cfg->cbb, load);
2110 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2112 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2113 MonoInst *vtaddr, *load;
2114 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2116 g_assert (!cfg->arch.no_pushes);
2118 MONO_INST_NEW (cfg, load, OP_LDADDR);
2119 load->inst_p0 = vtaddr;
2120 vtaddr->flags |= MONO_INST_INDIRECT;
2121 load->type = STACK_MP;
2122 load->klass = vtaddr->klass;
2123 load->dreg = mono_alloc_ireg (cfg);
2124 MONO_ADD_INS (cfg->cbb, load);
2125 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2127 if (ainfo->pair_storage [0] == ArgInIReg) {
2128 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2129 arg->dreg = mono_alloc_ireg (cfg);
2130 arg->sreg1 = load->dreg;
2132 MONO_ADD_INS (cfg->cbb, arg);
2133 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2135 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2136 arg->sreg1 = load->dreg;
2137 MONO_ADD_INS (cfg->cbb, arg);
2141 if (cfg->arch.no_pushes) {
2142 int dreg = mono_alloc_ireg (cfg);
2144 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2145 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2147 /* Can't use this for < 8 since it does an 8 byte memory load */
2148 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2149 arg->inst_basereg = src->dreg;
2150 arg->inst_offset = 0;
2151 MONO_ADD_INS (cfg->cbb, arg);
2153 } else if (size <= 40) {
2154 if (cfg->arch.no_pushes) {
2155 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2157 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2158 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2161 if (cfg->arch.no_pushes) {
2162 // FIXME: Code growth
2163 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2165 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2166 arg->inst_basereg = src->dreg;
2167 arg->inst_offset = 0;
2168 arg->inst_imm = size;
2169 MONO_ADD_INS (cfg->cbb, arg);
2176 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2178 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2180 if (ret->type == MONO_TYPE_R4) {
2181 if (COMPILE_LLVM (cfg))
2182 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2184 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2186 } else if (ret->type == MONO_TYPE_R8) {
2187 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2191 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2194 #endif /* DISABLE_JIT */
2196 #define EMIT_COND_BRANCH(ins,cond,sign) \
2197 if (ins->inst_true_bb->native_offset) { \
2198 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2200 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2201 if ((cfg->opt & MONO_OPT_BRANCH) && \
2202 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2203 x86_branch8 (code, cond, 0, sign); \
2205 x86_branch32 (code, cond, 0, sign); \
2209 MonoMethodSignature *sig;
2214 mgreg_t regs [PARAM_REGS];
2220 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2228 switch (cinfo->ret.storage) {
2232 case ArgValuetypeInReg: {
2233 ArgInfo *ainfo = &cinfo->ret;
2235 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2237 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2245 for (i = 0; i < cinfo->nargs; ++i) {
2246 ArgInfo *ainfo = &cinfo->args [i];
2247 switch (ainfo->storage) {
2250 case ArgValuetypeInReg:
2251 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2253 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2265 * mono_arch_dyn_call_prepare:
2267 * Return a pointer to an arch-specific structure which contains information
2268 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2269 * supported for SIG.
2270 * This function is equivalent to ffi_prep_cif in libffi.
2273 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2275 ArchDynCallInfo *info;
2278 cinfo = get_call_info (NULL, NULL, sig, FALSE);
2280 if (!dyn_call_supported (sig, cinfo)) {
2285 info = g_new0 (ArchDynCallInfo, 1);
2286 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2288 info->cinfo = cinfo;
2290 return (MonoDynCallInfo*)info;
2294 * mono_arch_dyn_call_free:
2296 * Free a MonoDynCallInfo structure.
2299 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2301 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2303 g_free (ainfo->cinfo);
2308 * mono_arch_get_start_dyn_call:
2310 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2311 * store the result into BUF.
2312 * ARGS should be an array of pointers pointing to the arguments.
2313 * RET should point to a memory buffer large enought to hold the result of the
2315 * This function should be as fast as possible, any work which does not depend
2316 * on the actual values of the arguments should be done in
2317 * mono_arch_dyn_call_prepare ().
2318 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2322 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2324 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2325 DynCallArgs *p = (DynCallArgs*)buf;
2326 int arg_index, greg, i;
2327 MonoMethodSignature *sig = dinfo->sig;
2329 g_assert (buf_len >= sizeof (DynCallArgs));
2337 if (dinfo->cinfo->vtype_retaddr)
2338 p->regs [greg ++] = (mgreg_t)ret;
2341 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2344 for (i = 0; i < sig->param_count; i++) {
2345 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2346 gpointer *arg = args [arg_index ++];
2349 p->regs [greg ++] = (mgreg_t)*(arg);
2354 case MONO_TYPE_STRING:
2355 case MONO_TYPE_CLASS:
2356 case MONO_TYPE_ARRAY:
2357 case MONO_TYPE_SZARRAY:
2358 case MONO_TYPE_OBJECT:
2364 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2365 p->regs [greg ++] = (mgreg_t)*(arg);
2367 case MONO_TYPE_BOOLEAN:
2369 p->regs [greg ++] = *(guint8*)(arg);
2372 p->regs [greg ++] = *(gint8*)(arg);
2375 p->regs [greg ++] = *(gint16*)(arg);
2378 case MONO_TYPE_CHAR:
2379 p->regs [greg ++] = *(guint16*)(arg);
2382 p->regs [greg ++] = *(gint32*)(arg);
2385 p->regs [greg ++] = *(guint32*)(arg);
2387 case MONO_TYPE_GENERICINST:
2388 if (MONO_TYPE_IS_REFERENCE (t)) {
2389 p->regs [greg ++] = (mgreg_t)*(arg);
2394 case MONO_TYPE_VALUETYPE: {
2395 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2397 g_assert (ainfo->storage == ArgValuetypeInReg);
2398 if (ainfo->pair_storage [0] != ArgNone) {
2399 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2400 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2402 if (ainfo->pair_storage [1] != ArgNone) {
2403 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2404 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2409 g_assert_not_reached ();
2413 g_assert (greg <= PARAM_REGS);
2417 * mono_arch_finish_dyn_call:
2419 * Store the result of a dyn call into the return value buffer passed to
2420 * start_dyn_call ().
2421 * This function should be as fast as possible, any work which does not depend
2422 * on the actual values of the arguments should be done in
2423 * mono_arch_dyn_call_prepare ().
2426 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2428 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2429 MonoMethodSignature *sig = dinfo->sig;
2430 guint8 *ret = ((DynCallArgs*)buf)->ret;
2431 mgreg_t res = ((DynCallArgs*)buf)->res;
2433 switch (mono_type_get_underlying_type (sig->ret)->type) {
2434 case MONO_TYPE_VOID:
2435 *(gpointer*)ret = NULL;
2437 case MONO_TYPE_STRING:
2438 case MONO_TYPE_CLASS:
2439 case MONO_TYPE_ARRAY:
2440 case MONO_TYPE_SZARRAY:
2441 case MONO_TYPE_OBJECT:
2445 *(gpointer*)ret = (gpointer)res;
2451 case MONO_TYPE_BOOLEAN:
2452 *(guint8*)ret = res;
2455 *(gint16*)ret = res;
2458 case MONO_TYPE_CHAR:
2459 *(guint16*)ret = res;
2462 *(gint32*)ret = res;
2465 *(guint32*)ret = res;
2468 *(gint64*)ret = res;
2471 *(guint64*)ret = res;
2473 case MONO_TYPE_GENERICINST:
2474 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2475 *(gpointer*)ret = (gpointer)res;
2480 case MONO_TYPE_VALUETYPE:
2481 if (dinfo->cinfo->vtype_retaddr) {
2484 ArgInfo *ainfo = &dinfo->cinfo->ret;
2486 g_assert (ainfo->storage == ArgValuetypeInReg);
2488 if (ainfo->pair_storage [0] != ArgNone) {
2489 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2490 ((mgreg_t*)ret)[0] = res;
2493 g_assert (ainfo->pair_storage [1] == ArgNone);
2497 g_assert_not_reached ();
2501 /* emit an exception if condition is fail */
2502 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2504 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2505 if (tins == NULL) { \
2506 mono_add_patch_info (cfg, code - cfg->native_code, \
2507 MONO_PATCH_INFO_EXC, exc_name); \
2508 x86_branch32 (code, cond, 0, signed); \
2510 EMIT_COND_BRANCH (tins, cond, signed); \
2514 #define EMIT_FPCOMPARE(code) do { \
2515 amd64_fcompp (code); \
2516 amd64_fnstsw (code); \
2519 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2520 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2521 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2522 amd64_ ##op (code); \
2523 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2524 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2528 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2530 gboolean no_patch = FALSE;
2533 * FIXME: Add support for thunks
2536 gboolean near_call = FALSE;
2539 * Indirect calls are expensive so try to make a near call if possible.
2540 * The caller memory is allocated by the code manager so it is
2541 * guaranteed to be at a 32 bit offset.
2544 if (patch_type != MONO_PATCH_INFO_ABS) {
2545 /* The target is in memory allocated using the code manager */
2548 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2549 if (((MonoMethod*)data)->klass->image->aot_module)
2550 /* The callee might be an AOT method */
2552 if (((MonoMethod*)data)->dynamic)
2553 /* The target is in malloc-ed memory */
2557 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2559 * The call might go directly to a native function without
2562 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2564 gconstpointer target = mono_icall_get_wrapper (mi);
2565 if ((((guint64)target) >> 32) != 0)
2571 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2573 * This is not really an optimization, but required because the
2574 * generic class init trampolines use R11 to pass the vtable.
2578 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2580 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2581 strstr (cfg->method->name, info->name)) {
2582 /* A call to the wrapped function */
2583 if ((((guint64)data) >> 32) == 0)
2587 else if (info->func == info->wrapper) {
2589 if ((((guint64)info->func) >> 32) == 0)
2593 /* See the comment in mono_codegen () */
2594 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2598 else if ((((guint64)data) >> 32) == 0) {
2605 if (cfg->method->dynamic)
2606 /* These methods are allocated using malloc */
2609 #ifdef MONO_ARCH_NOMAP32BIT
2613 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2614 if (optimize_for_xen)
2617 if (cfg->compile_aot) {
2624 * Align the call displacement to an address divisible by 4 so it does
2625 * not span cache lines. This is required for code patching to work on SMP
2628 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2629 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2630 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2631 amd64_call_code (code, 0);
2634 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2635 amd64_set_reg_template (code, GP_SCRATCH_REG);
2636 amd64_call_reg (code, GP_SCRATCH_REG);
2643 static inline guint8*
2644 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2647 if (win64_adjust_stack)
2648 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2650 code = emit_call_body (cfg, code, patch_type, data);
2652 if (win64_adjust_stack)
2653 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2660 store_membase_imm_to_store_membase_reg (int opcode)
2663 case OP_STORE_MEMBASE_IMM:
2664 return OP_STORE_MEMBASE_REG;
2665 case OP_STOREI4_MEMBASE_IMM:
2666 return OP_STOREI4_MEMBASE_REG;
2667 case OP_STOREI8_MEMBASE_IMM:
2668 return OP_STOREI8_MEMBASE_REG;
2676 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2679 * mono_arch_peephole_pass_1:
2681 * Perform peephole opts which should/can be performed before local regalloc
2684 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2688 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2689 MonoInst *last_ins = ins->prev;
2691 switch (ins->opcode) {
2695 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2697 * X86_LEA is like ADD, but doesn't have the
2698 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2699 * its operand to 64 bit.
2701 ins->opcode = OP_X86_LEA_MEMBASE;
2702 ins->inst_basereg = ins->sreg1;
2707 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2711 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2712 * the latter has length 2-3 instead of 6 (reverse constant
2713 * propagation). These instruction sequences are very common
2714 * in the initlocals bblock.
2716 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2717 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2718 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2719 ins2->sreg1 = ins->dreg;
2720 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2722 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2731 case OP_COMPARE_IMM:
2732 case OP_LCOMPARE_IMM:
2733 /* OP_COMPARE_IMM (reg, 0)
2735 * OP_AMD64_TEST_NULL (reg)
2738 ins->opcode = OP_AMD64_TEST_NULL;
2740 case OP_ICOMPARE_IMM:
2742 ins->opcode = OP_X86_TEST_NULL;
2744 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2746 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2747 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2749 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2750 * OP_COMPARE_IMM reg, imm
2752 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2754 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2755 ins->inst_basereg == last_ins->inst_destbasereg &&
2756 ins->inst_offset == last_ins->inst_offset) {
2757 ins->opcode = OP_ICOMPARE_IMM;
2758 ins->sreg1 = last_ins->sreg1;
2760 /* check if we can remove cmp reg,0 with test null */
2762 ins->opcode = OP_X86_TEST_NULL;
2768 mono_peephole_ins (bb, ins);
2773 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2777 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2778 switch (ins->opcode) {
2781 /* reg = 0 -> XOR (reg, reg) */
2782 /* XOR sets cflags on x86, so we cant do it always */
2783 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2784 ins->opcode = OP_LXOR;
2785 ins->sreg1 = ins->dreg;
2786 ins->sreg2 = ins->dreg;
2794 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2795 * 0 result into 64 bits.
2797 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2798 ins->opcode = OP_IXOR;
2802 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2806 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2807 * the latter has length 2-3 instead of 6 (reverse constant
2808 * propagation). These instruction sequences are very common
2809 * in the initlocals bblock.
2811 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2812 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2813 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2814 ins2->sreg1 = ins->dreg;
2815 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2817 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2827 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2828 ins->opcode = OP_X86_INC_REG;
2831 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2832 ins->opcode = OP_X86_DEC_REG;
2836 mono_peephole_ins (bb, ins);
2840 #define NEW_INS(cfg,ins,dest,op) do { \
2841 MONO_INST_NEW ((cfg), (dest), (op)); \
2842 (dest)->cil_code = (ins)->cil_code; \
2843 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2847 * mono_arch_lowering_pass:
2849 * Converts complex opcodes into simpler ones so that each IR instruction
2850 * corresponds to one machine instruction.
2853 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2855 MonoInst *ins, *n, *temp;
2858 * FIXME: Need to add more instructions, but the current machine
2859 * description can't model some parts of the composite instructions like
2862 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2863 switch (ins->opcode) {
2867 case OP_IDIV_UN_IMM:
2868 case OP_IREM_UN_IMM:
2869 mono_decompose_op_imm (cfg, bb, ins);
2872 /* Keep the opcode if we can implement it efficiently */
2873 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2874 mono_decompose_op_imm (cfg, bb, ins);
2876 case OP_COMPARE_IMM:
2877 case OP_LCOMPARE_IMM:
2878 if (!amd64_is_imm32 (ins->inst_imm)) {
2879 NEW_INS (cfg, ins, temp, OP_I8CONST);
2880 temp->inst_c0 = ins->inst_imm;
2881 temp->dreg = mono_alloc_ireg (cfg);
2882 ins->opcode = OP_COMPARE;
2883 ins->sreg2 = temp->dreg;
2886 case OP_LOAD_MEMBASE:
2887 case OP_LOADI8_MEMBASE:
2888 if (!amd64_is_imm32 (ins->inst_offset)) {
2889 NEW_INS (cfg, ins, temp, OP_I8CONST);
2890 temp->inst_c0 = ins->inst_offset;
2891 temp->dreg = mono_alloc_ireg (cfg);
2892 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2893 ins->inst_indexreg = temp->dreg;
2896 case OP_STORE_MEMBASE_IMM:
2897 case OP_STOREI8_MEMBASE_IMM:
2898 if (!amd64_is_imm32 (ins->inst_imm)) {
2899 NEW_INS (cfg, ins, temp, OP_I8CONST);
2900 temp->inst_c0 = ins->inst_imm;
2901 temp->dreg = mono_alloc_ireg (cfg);
2902 ins->opcode = OP_STOREI8_MEMBASE_REG;
2903 ins->sreg1 = temp->dreg;
2906 #ifdef MONO_ARCH_SIMD_INTRINSICS
2907 case OP_EXPAND_I1: {
2908 int temp_reg1 = mono_alloc_ireg (cfg);
2909 int temp_reg2 = mono_alloc_ireg (cfg);
2910 int original_reg = ins->sreg1;
2912 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2913 temp->sreg1 = original_reg;
2914 temp->dreg = temp_reg1;
2916 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2917 temp->sreg1 = temp_reg1;
2918 temp->dreg = temp_reg2;
2921 NEW_INS (cfg, ins, temp, OP_LOR);
2922 temp->sreg1 = temp->dreg = temp_reg2;
2923 temp->sreg2 = temp_reg1;
2925 ins->opcode = OP_EXPAND_I2;
2926 ins->sreg1 = temp_reg2;
2935 bb->max_vreg = cfg->next_vreg;
2939 branch_cc_table [] = {
2940 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2941 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2942 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2945 /* Maps CMP_... constants to X86_CC_... constants */
2948 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2949 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2953 cc_signed_table [] = {
2954 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2955 FALSE, FALSE, FALSE, FALSE
2958 /*#include "cprop.c"*/
2960 static unsigned char*
2961 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2963 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2966 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2968 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2972 static unsigned char*
2973 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2975 int sreg = tree->sreg1;
2976 int need_touch = FALSE;
2978 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2979 if (!tree->flags & MONO_INST_INIT)
2988 * If requested stack size is larger than one page,
2989 * perform stack-touch operation
2992 * Generate stack probe code.
2993 * Under Windows, it is necessary to allocate one page at a time,
2994 * "touching" stack after each successful sub-allocation. This is
2995 * because of the way stack growth is implemented - there is a
2996 * guard page before the lowest stack page that is currently commited.
2997 * Stack normally grows sequentially so OS traps access to the
2998 * guard page and commits more pages when needed.
3000 amd64_test_reg_imm (code, sreg, ~0xFFF);
3001 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3003 br[2] = code; /* loop */
3004 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3005 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3006 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3007 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3008 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3009 amd64_patch (br[3], br[2]);
3010 amd64_test_reg_reg (code, sreg, sreg);
3011 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3012 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3014 br[1] = code; x86_jump8 (code, 0);
3016 amd64_patch (br[0], code);
3017 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3018 amd64_patch (br[1], code);
3019 amd64_patch (br[4], code);
3022 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3024 if (tree->flags & MONO_INST_INIT) {
3026 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3027 amd64_push_reg (code, AMD64_RAX);
3030 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3031 amd64_push_reg (code, AMD64_RCX);
3034 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3035 amd64_push_reg (code, AMD64_RDI);
3039 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3040 if (sreg != AMD64_RCX)
3041 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3042 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3044 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3045 if (cfg->param_area && cfg->arch.no_pushes)
3046 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3048 amd64_prefix (code, X86_REP_PREFIX);
3051 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3052 amd64_pop_reg (code, AMD64_RDI);
3053 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3054 amd64_pop_reg (code, AMD64_RCX);
3055 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3056 amd64_pop_reg (code, AMD64_RAX);
3062 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3067 /* Move return value to the target register */
3068 /* FIXME: do this in the local reg allocator */
3069 switch (ins->opcode) {
3072 case OP_CALL_MEMBASE:
3075 case OP_LCALL_MEMBASE:
3076 g_assert (ins->dreg == AMD64_RAX);
3080 case OP_FCALL_MEMBASE:
3081 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3082 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3085 if (ins->dreg != AMD64_XMM0)
3086 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3091 case OP_VCALL_MEMBASE:
3094 case OP_VCALL2_MEMBASE:
3095 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3096 if (cinfo->ret.storage == ArgValuetypeInReg) {
3097 MonoInst *loc = cfg->arch.vret_addr_loc;
3099 /* Load the destination address */
3100 g_assert (loc->opcode == OP_REGOFFSET);
3101 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3103 for (quad = 0; quad < 2; quad ++) {
3104 switch (cinfo->ret.pair_storage [quad]) {
3106 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3108 case ArgInFloatSSEReg:
3109 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3111 case ArgInDoubleSSEReg:
3112 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3127 #endif /* DISABLE_JIT */
3130 * mono_amd64_emit_tls_get:
3131 * @code: buffer to store code to
3132 * @dreg: hard register where to place the result
3133 * @tls_offset: offset info
3135 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3136 * the dreg register the item in the thread local storage identified
3139 * Returns: a pointer to the end of the stored code
3142 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3145 g_assert (tls_offset < 64);
3146 x86_prefix (code, X86_GS_PREFIX);
3147 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3149 if (optimize_for_xen) {
3150 x86_prefix (code, X86_FS_PREFIX);
3151 amd64_mov_reg_mem (code, dreg, 0, 8);
3152 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3154 x86_prefix (code, X86_FS_PREFIX);
3155 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3161 #define REAL_PRINT_REG(text,reg) \
3162 mono_assert (reg >= 0); \
3163 amd64_push_reg (code, AMD64_RAX); \
3164 amd64_push_reg (code, AMD64_RDX); \
3165 amd64_push_reg (code, AMD64_RCX); \
3166 amd64_push_reg (code, reg); \
3167 amd64_push_imm (code, reg); \
3168 amd64_push_imm (code, text " %d %p\n"); \
3169 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3170 amd64_call_reg (code, AMD64_RAX); \
3171 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3172 amd64_pop_reg (code, AMD64_RCX); \
3173 amd64_pop_reg (code, AMD64_RDX); \
3174 amd64_pop_reg (code, AMD64_RAX);
3176 /* benchmark and set based on cpu */
3177 #define LOOP_ALIGNMENT 8
3178 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3183 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3188 guint8 *code = cfg->native_code + cfg->code_len;
3189 MonoInst *last_ins = NULL;
3190 guint last_offset = 0;
3193 /* Fix max_offset estimate for each successor bb */
3194 if (cfg->opt & MONO_OPT_BRANCH) {
3195 int current_offset = cfg->code_len;
3196 MonoBasicBlock *current_bb;
3197 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3198 current_bb->max_offset = current_offset;
3199 current_offset += current_bb->max_length;
3203 if (cfg->opt & MONO_OPT_LOOP) {
3204 int pad, align = LOOP_ALIGNMENT;
3205 /* set alignment depending on cpu */
3206 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3208 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3209 amd64_padding (code, pad);
3210 cfg->code_len += pad;
3211 bb->native_offset = cfg->code_len;
3215 if (cfg->verbose_level > 2)
3216 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3218 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3219 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3220 g_assert (!cfg->compile_aot);
3222 cov->data [bb->dfn].cil_code = bb->cil_code;
3223 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3224 /* this is not thread save, but good enough */
3225 amd64_inc_membase (code, AMD64_R11, 0);
3228 offset = code - cfg->native_code;
3230 mono_debug_open_block (cfg, bb, offset);
3232 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3233 x86_breakpoint (code);
3235 MONO_BB_FOR_EACH_INS (bb, ins) {
3236 offset = code - cfg->native_code;
3238 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3240 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3241 cfg->code_size *= 2;
3242 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3243 code = cfg->native_code + offset;
3244 mono_jit_stats.code_reallocs++;
3247 if (cfg->debug_info)
3248 mono_debug_record_line_number (cfg, ins, offset);
3250 switch (ins->opcode) {
3252 amd64_mul_reg (code, ins->sreg2, TRUE);
3255 amd64_mul_reg (code, ins->sreg2, FALSE);
3257 case OP_X86_SETEQ_MEMBASE:
3258 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3260 case OP_STOREI1_MEMBASE_IMM:
3261 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3263 case OP_STOREI2_MEMBASE_IMM:
3264 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3266 case OP_STOREI4_MEMBASE_IMM:
3267 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3269 case OP_STOREI1_MEMBASE_REG:
3270 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3272 case OP_STOREI2_MEMBASE_REG:
3273 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3275 case OP_STORE_MEMBASE_REG:
3276 case OP_STOREI8_MEMBASE_REG:
3277 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3279 case OP_STOREI4_MEMBASE_REG:
3280 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3282 case OP_STORE_MEMBASE_IMM:
3283 case OP_STOREI8_MEMBASE_IMM:
3284 g_assert (amd64_is_imm32 (ins->inst_imm));
3285 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3289 // FIXME: Decompose this earlier
3290 if (amd64_is_imm32 (ins->inst_imm))
3291 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3293 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3294 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3298 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3299 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3302 // FIXME: Decompose this earlier
3303 if (amd64_is_imm32 (ins->inst_imm))
3304 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3306 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3307 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3311 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3312 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3315 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3316 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3318 case OP_LOAD_MEMBASE:
3319 case OP_LOADI8_MEMBASE:
3320 g_assert (amd64_is_imm32 (ins->inst_offset));
3321 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3323 case OP_LOADI4_MEMBASE:
3324 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3326 case OP_LOADU4_MEMBASE:
3327 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3329 case OP_LOADU1_MEMBASE:
3330 /* The cpu zero extends the result into 64 bits */
3331 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3333 case OP_LOADI1_MEMBASE:
3334 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3336 case OP_LOADU2_MEMBASE:
3337 /* The cpu zero extends the result into 64 bits */
3338 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3340 case OP_LOADI2_MEMBASE:
3341 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3343 case OP_AMD64_LOADI8_MEMINDEX:
3344 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3346 case OP_LCONV_TO_I1:
3347 case OP_ICONV_TO_I1:
3349 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3351 case OP_LCONV_TO_I2:
3352 case OP_ICONV_TO_I2:
3354 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3356 case OP_LCONV_TO_U1:
3357 case OP_ICONV_TO_U1:
3358 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3360 case OP_LCONV_TO_U2:
3361 case OP_ICONV_TO_U2:
3362 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3365 /* Clean out the upper word */
3366 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3369 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3373 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3375 case OP_COMPARE_IMM:
3376 case OP_LCOMPARE_IMM:
3377 g_assert (amd64_is_imm32 (ins->inst_imm));
3378 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3380 case OP_X86_COMPARE_REG_MEMBASE:
3381 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3383 case OP_X86_TEST_NULL:
3384 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3386 case OP_AMD64_TEST_NULL:
3387 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3390 case OP_X86_ADD_REG_MEMBASE:
3391 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3393 case OP_X86_SUB_REG_MEMBASE:
3394 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3396 case OP_X86_AND_REG_MEMBASE:
3397 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3399 case OP_X86_OR_REG_MEMBASE:
3400 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3402 case OP_X86_XOR_REG_MEMBASE:
3403 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3406 case OP_X86_ADD_MEMBASE_IMM:
3407 /* FIXME: Make a 64 version too */
3408 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3410 case OP_X86_SUB_MEMBASE_IMM:
3411 g_assert (amd64_is_imm32 (ins->inst_imm));
3412 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3414 case OP_X86_AND_MEMBASE_IMM:
3415 g_assert (amd64_is_imm32 (ins->inst_imm));
3416 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3418 case OP_X86_OR_MEMBASE_IMM:
3419 g_assert (amd64_is_imm32 (ins->inst_imm));
3420 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3422 case OP_X86_XOR_MEMBASE_IMM:
3423 g_assert (amd64_is_imm32 (ins->inst_imm));
3424 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3426 case OP_X86_ADD_MEMBASE_REG:
3427 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3429 case OP_X86_SUB_MEMBASE_REG:
3430 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3432 case OP_X86_AND_MEMBASE_REG:
3433 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3435 case OP_X86_OR_MEMBASE_REG:
3436 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3438 case OP_X86_XOR_MEMBASE_REG:
3439 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3441 case OP_X86_INC_MEMBASE:
3442 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3444 case OP_X86_INC_REG:
3445 amd64_inc_reg_size (code, ins->dreg, 4);
3447 case OP_X86_DEC_MEMBASE:
3448 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3450 case OP_X86_DEC_REG:
3451 amd64_dec_reg_size (code, ins->dreg, 4);
3453 case OP_X86_MUL_REG_MEMBASE:
3454 case OP_X86_MUL_MEMBASE_REG:
3455 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3457 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3458 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3460 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3461 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3463 case OP_AMD64_COMPARE_MEMBASE_REG:
3464 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3466 case OP_AMD64_COMPARE_MEMBASE_IMM:
3467 g_assert (amd64_is_imm32 (ins->inst_imm));
3468 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3470 case OP_X86_COMPARE_MEMBASE8_IMM:
3471 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3473 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3474 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3476 case OP_AMD64_COMPARE_REG_MEMBASE:
3477 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3480 case OP_AMD64_ADD_REG_MEMBASE:
3481 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3483 case OP_AMD64_SUB_REG_MEMBASE:
3484 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3486 case OP_AMD64_AND_REG_MEMBASE:
3487 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3489 case OP_AMD64_OR_REG_MEMBASE:
3490 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3492 case OP_AMD64_XOR_REG_MEMBASE:
3493 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3496 case OP_AMD64_ADD_MEMBASE_REG:
3497 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3499 case OP_AMD64_SUB_MEMBASE_REG:
3500 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3502 case OP_AMD64_AND_MEMBASE_REG:
3503 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3505 case OP_AMD64_OR_MEMBASE_REG:
3506 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3508 case OP_AMD64_XOR_MEMBASE_REG:
3509 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3512 case OP_AMD64_ADD_MEMBASE_IMM:
3513 g_assert (amd64_is_imm32 (ins->inst_imm));
3514 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3516 case OP_AMD64_SUB_MEMBASE_IMM:
3517 g_assert (amd64_is_imm32 (ins->inst_imm));
3518 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3520 case OP_AMD64_AND_MEMBASE_IMM:
3521 g_assert (amd64_is_imm32 (ins->inst_imm));
3522 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3524 case OP_AMD64_OR_MEMBASE_IMM:
3525 g_assert (amd64_is_imm32 (ins->inst_imm));
3526 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3528 case OP_AMD64_XOR_MEMBASE_IMM:
3529 g_assert (amd64_is_imm32 (ins->inst_imm));
3530 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3534 amd64_breakpoint (code);
3536 case OP_RELAXED_NOP:
3537 x86_prefix (code, X86_REP_PREFIX);
3545 case OP_DUMMY_STORE:
3546 case OP_NOT_REACHED:
3549 case OP_SEQ_POINT: {
3552 if (cfg->compile_aot)
3556 * Read from the single stepping trigger page. This will cause a
3557 * SIGSEGV when single stepping is enabled.
3558 * We do this _before_ the breakpoint, so single stepping after
3559 * a breakpoint is hit will step to the next IL offset.
3561 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3562 if (((guint64)ss_trigger_page >> 32) == 0)
3563 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3565 MonoInst *var = cfg->arch.ss_trigger_page_var;
3567 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3568 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3573 * This is the address which is saved in seq points,
3574 * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3575 * from the address of the instruction causing the fault.
3577 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3580 * A placeholder for a possible breakpoint inserted by
3581 * mono_arch_set_breakpoint ().
3583 for (i = 0; i < breakpoint_size; ++i)
3589 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3592 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3596 g_assert (amd64_is_imm32 (ins->inst_imm));
3597 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3600 g_assert (amd64_is_imm32 (ins->inst_imm));
3601 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3605 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3608 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3612 g_assert (amd64_is_imm32 (ins->inst_imm));
3613 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3616 g_assert (amd64_is_imm32 (ins->inst_imm));
3617 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3620 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3624 g_assert (amd64_is_imm32 (ins->inst_imm));
3625 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3628 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3633 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3635 switch (ins->inst_imm) {
3639 if (ins->dreg != ins->sreg1)
3640 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3641 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3644 /* LEA r1, [r2 + r2*2] */
3645 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3648 /* LEA r1, [r2 + r2*4] */
3649 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3652 /* LEA r1, [r2 + r2*2] */
3654 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3655 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3658 /* LEA r1, [r2 + r2*8] */
3659 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3662 /* LEA r1, [r2 + r2*4] */
3664 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3665 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3668 /* LEA r1, [r2 + r2*2] */
3670 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3671 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3674 /* LEA r1, [r2 + r2*4] */
3675 /* LEA r1, [r1 + r1*4] */
3676 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3677 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3680 /* LEA r1, [r2 + r2*4] */
3682 /* LEA r1, [r1 + r1*4] */
3683 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3684 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3685 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3688 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3695 /* Regalloc magic makes the div/rem cases the same */
3696 if (ins->sreg2 == AMD64_RDX) {
3697 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3699 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3702 amd64_div_reg (code, ins->sreg2, TRUE);
3707 if (ins->sreg2 == AMD64_RDX) {
3708 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3709 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3710 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3712 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3713 amd64_div_reg (code, ins->sreg2, FALSE);
3718 if (ins->sreg2 == AMD64_RDX) {
3719 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3720 amd64_cdq_size (code, 4);
3721 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3723 amd64_cdq_size (code, 4);
3724 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3729 if (ins->sreg2 == AMD64_RDX) {
3730 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3731 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3732 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3734 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3735 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3739 int power = mono_is_power_of_two (ins->inst_imm);
3741 g_assert (ins->sreg1 == X86_EAX);
3742 g_assert (ins->dreg == X86_EAX);
3743 g_assert (power >= 0);
3746 amd64_mov_reg_imm (code, ins->dreg, 0);
3750 /* Based on gcc code */
3752 /* Add compensation for negative dividents */
3753 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3755 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3756 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3757 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3758 /* Compute remainder */
3759 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3760 /* Remove compensation */
3761 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3765 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3766 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3769 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3773 g_assert (amd64_is_imm32 (ins->inst_imm));
3774 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3777 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3781 g_assert (amd64_is_imm32 (ins->inst_imm));
3782 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3785 g_assert (ins->sreg2 == AMD64_RCX);
3786 amd64_shift_reg (code, X86_SHL, ins->dreg);
3789 g_assert (ins->sreg2 == AMD64_RCX);
3790 amd64_shift_reg (code, X86_SAR, ins->dreg);
3793 g_assert (amd64_is_imm32 (ins->inst_imm));
3794 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3797 g_assert (amd64_is_imm32 (ins->inst_imm));
3798 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3801 g_assert (amd64_is_imm32 (ins->inst_imm));
3802 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3804 case OP_LSHR_UN_IMM:
3805 g_assert (amd64_is_imm32 (ins->inst_imm));
3806 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3809 g_assert (ins->sreg2 == AMD64_RCX);
3810 amd64_shift_reg (code, X86_SHR, ins->dreg);
3813 g_assert (amd64_is_imm32 (ins->inst_imm));
3814 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3817 g_assert (amd64_is_imm32 (ins->inst_imm));
3818 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3823 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3826 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3829 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3832 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3836 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3839 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3842 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3845 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3848 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3851 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3854 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3857 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3860 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3863 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3866 amd64_neg_reg_size (code, ins->sreg1, 4);
3869 amd64_not_reg_size (code, ins->sreg1, 4);
3872 g_assert (ins->sreg2 == AMD64_RCX);
3873 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3876 g_assert (ins->sreg2 == AMD64_RCX);
3877 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3880 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3882 case OP_ISHR_UN_IMM:
3883 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3886 g_assert (ins->sreg2 == AMD64_RCX);
3887 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3890 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3893 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3896 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3897 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3899 case OP_IMUL_OVF_UN:
3900 case OP_LMUL_OVF_UN: {
3901 /* the mul operation and the exception check should most likely be split */
3902 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3903 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3904 /*g_assert (ins->sreg2 == X86_EAX);
3905 g_assert (ins->dreg == X86_EAX);*/
3906 if (ins->sreg2 == X86_EAX) {
3907 non_eax_reg = ins->sreg1;
3908 } else if (ins->sreg1 == X86_EAX) {
3909 non_eax_reg = ins->sreg2;
3911 /* no need to save since we're going to store to it anyway */
3912 if (ins->dreg != X86_EAX) {
3914 amd64_push_reg (code, X86_EAX);
3916 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3917 non_eax_reg = ins->sreg2;
3919 if (ins->dreg == X86_EDX) {
3922 amd64_push_reg (code, X86_EAX);
3926 amd64_push_reg (code, X86_EDX);
3928 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3929 /* save before the check since pop and mov don't change the flags */
3930 if (ins->dreg != X86_EAX)
3931 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3933 amd64_pop_reg (code, X86_EDX);
3935 amd64_pop_reg (code, X86_EAX);
3936 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3940 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3942 case OP_ICOMPARE_IMM:
3943 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3965 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3973 case OP_CMOV_INE_UN:
3974 case OP_CMOV_IGE_UN:
3975 case OP_CMOV_IGT_UN:
3976 case OP_CMOV_ILE_UN:
3977 case OP_CMOV_ILT_UN:
3983 case OP_CMOV_LNE_UN:
3984 case OP_CMOV_LGE_UN:
3985 case OP_CMOV_LGT_UN:
3986 case OP_CMOV_LLE_UN:
3987 case OP_CMOV_LLT_UN:
3988 g_assert (ins->dreg == ins->sreg1);
3989 /* This needs to operate on 64 bit values */
3990 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3994 amd64_not_reg (code, ins->sreg1);
3997 amd64_neg_reg (code, ins->sreg1);
4002 if ((((guint64)ins->inst_c0) >> 32) == 0)
4003 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4005 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4008 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4009 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4012 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4013 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4016 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4018 case OP_AMD64_SET_XMMREG_R4: {
4019 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4022 case OP_AMD64_SET_XMMREG_R8: {
4023 if (ins->dreg != ins->sreg1)
4024 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4029 * Note: this 'frame destruction' logic is useful for tail calls, too.
4030 * Keep in sync with the code in emit_epilog.
4034 /* FIXME: no tracing support... */
4035 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4036 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4038 g_assert (!cfg->method->save_lmf);
4040 if (cfg->arch.omit_fp) {
4041 guint32 save_offset = 0;
4042 /* Pop callee-saved registers */
4043 for (i = 0; i < AMD64_NREG; ++i)
4044 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4045 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4048 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4051 for (i = 0; i < AMD64_NREG; ++i)
4052 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4053 pos -= sizeof (gpointer);
4056 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4058 /* Pop registers in reverse order */
4059 for (i = AMD64_NREG - 1; i > 0; --i)
4060 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4061 amd64_pop_reg (code, i);
4067 offset = code - cfg->native_code;
4068 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4069 if (cfg->compile_aot)
4070 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4072 amd64_set_reg_template (code, AMD64_R11);
4073 amd64_jump_reg (code, AMD64_R11);
4077 /* ensure ins->sreg1 is not NULL */
4078 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4081 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4082 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4091 call = (MonoCallInst*)ins;
4093 * The AMD64 ABI forces callers to know about varargs.
4095 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4096 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4097 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4099 * Since the unmanaged calling convention doesn't contain a
4100 * 'vararg' entry, we have to treat every pinvoke call as a
4101 * potential vararg call.
4105 for (i = 0; i < AMD64_XMM_NREG; ++i)
4106 if (call->used_fregs & (1 << i))
4109 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4111 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4114 if (ins->flags & MONO_INST_HAS_METHOD)
4115 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4117 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4118 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4119 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4120 code = emit_move_return_value (cfg, ins, code);
4126 case OP_VOIDCALL_REG:
4128 call = (MonoCallInst*)ins;
4130 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4131 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4132 ins->sreg1 = AMD64_R11;
4136 * The AMD64 ABI forces callers to know about varargs.
4138 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4139 if (ins->sreg1 == AMD64_RAX) {
4140 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4141 ins->sreg1 = AMD64_R11;
4143 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4144 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4146 * Since the unmanaged calling convention doesn't contain a
4147 * 'vararg' entry, we have to treat every pinvoke call as a
4148 * potential vararg call.
4152 for (i = 0; i < AMD64_XMM_NREG; ++i)
4153 if (call->used_fregs & (1 << i))
4155 if (ins->sreg1 == AMD64_RAX) {
4156 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4157 ins->sreg1 = AMD64_R11;
4160 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4162 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4165 amd64_call_reg (code, ins->sreg1);
4166 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4167 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4168 code = emit_move_return_value (cfg, ins, code);
4170 case OP_FCALL_MEMBASE:
4171 case OP_LCALL_MEMBASE:
4172 case OP_VCALL_MEMBASE:
4173 case OP_VCALL2_MEMBASE:
4174 case OP_VOIDCALL_MEMBASE:
4175 case OP_CALL_MEMBASE:
4176 call = (MonoCallInst*)ins;
4178 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4180 * Can't use R11 because it is clobbered by the trampoline
4181 * code, and the reg value is needed by get_vcall_slot_addr.
4183 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4184 ins->sreg1 = AMD64_RAX;
4188 * Emit a few nops to simplify get_vcall_slot ().
4194 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4195 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4196 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4197 code = emit_move_return_value (cfg, ins, code);
4201 MonoInst *var = cfg->dyn_call_var;
4203 g_assert (var->opcode == OP_REGOFFSET);
4205 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4206 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4208 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4210 /* Save args buffer */
4211 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4213 /* Set argument registers */
4214 for (i = 0; i < PARAM_REGS; ++i)
4215 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4218 amd64_call_reg (code, AMD64_R10);
4221 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4222 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4225 case OP_AMD64_SAVE_SP_TO_LMF:
4226 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4229 g_assert (!cfg->arch.no_pushes);
4230 amd64_push_reg (code, ins->sreg1);
4232 case OP_X86_PUSH_IMM:
4233 g_assert (!cfg->arch.no_pushes);
4234 g_assert (amd64_is_imm32 (ins->inst_imm));
4235 amd64_push_imm (code, ins->inst_imm);
4237 case OP_X86_PUSH_MEMBASE:
4238 g_assert (!cfg->arch.no_pushes);
4239 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4241 case OP_X86_PUSH_OBJ: {
4242 int size = ALIGN_TO (ins->inst_imm, 8);
4244 g_assert (!cfg->arch.no_pushes);
4246 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4247 amd64_push_reg (code, AMD64_RDI);
4248 amd64_push_reg (code, AMD64_RSI);
4249 amd64_push_reg (code, AMD64_RCX);
4250 if (ins->inst_offset)
4251 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4253 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4254 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4255 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4257 amd64_prefix (code, X86_REP_PREFIX);
4259 amd64_pop_reg (code, AMD64_RCX);
4260 amd64_pop_reg (code, AMD64_RSI);
4261 amd64_pop_reg (code, AMD64_RDI);
4265 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4267 case OP_X86_LEA_MEMBASE:
4268 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4271 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4274 /* keep alignment */
4275 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4276 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4277 code = mono_emit_stack_alloc (cfg, code, ins);
4278 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4279 if (cfg->param_area && cfg->arch.no_pushes)
4280 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4282 case OP_LOCALLOC_IMM: {
4283 guint32 size = ins->inst_imm;
4284 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4286 if (ins->flags & MONO_INST_INIT) {
4290 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4291 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4293 for (i = 0; i < size; i += 8)
4294 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4295 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4297 amd64_mov_reg_imm (code, ins->dreg, size);
4298 ins->sreg1 = ins->dreg;
4300 code = mono_emit_stack_alloc (cfg, code, ins);
4301 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4304 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4305 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4307 if (cfg->param_area && cfg->arch.no_pushes)
4308 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4312 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4313 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4314 (gpointer)"mono_arch_throw_exception", FALSE);
4318 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4319 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4320 (gpointer)"mono_arch_rethrow_exception", FALSE);
4323 case OP_CALL_HANDLER:
4325 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4326 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4327 amd64_call_imm (code, 0);
4328 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4329 /* Restore stack alignment */
4330 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4332 case OP_START_HANDLER: {
4333 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4334 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4336 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4337 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4338 cfg->param_area && cfg->arch.no_pushes) {
4339 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4343 case OP_ENDFINALLY: {
4344 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4345 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4349 case OP_ENDFILTER: {
4350 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4351 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4352 /* The local allocator will put the result into RAX */
4358 ins->inst_c0 = code - cfg->native_code;
4361 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4362 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4364 if (ins->inst_target_bb->native_offset) {
4365 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4367 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4368 if ((cfg->opt & MONO_OPT_BRANCH) &&
4369 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4370 x86_jump8 (code, 0);
4372 x86_jump32 (code, 0);
4376 amd64_jump_reg (code, ins->sreg1);
4393 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4394 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4396 case OP_COND_EXC_EQ:
4397 case OP_COND_EXC_NE_UN:
4398 case OP_COND_EXC_LT:
4399 case OP_COND_EXC_LT_UN:
4400 case OP_COND_EXC_GT:
4401 case OP_COND_EXC_GT_UN:
4402 case OP_COND_EXC_GE:
4403 case OP_COND_EXC_GE_UN:
4404 case OP_COND_EXC_LE:
4405 case OP_COND_EXC_LE_UN:
4406 case OP_COND_EXC_IEQ:
4407 case OP_COND_EXC_INE_UN:
4408 case OP_COND_EXC_ILT:
4409 case OP_COND_EXC_ILT_UN:
4410 case OP_COND_EXC_IGT:
4411 case OP_COND_EXC_IGT_UN:
4412 case OP_COND_EXC_IGE:
4413 case OP_COND_EXC_IGE_UN:
4414 case OP_COND_EXC_ILE:
4415 case OP_COND_EXC_ILE_UN:
4416 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4418 case OP_COND_EXC_OV:
4419 case OP_COND_EXC_NO:
4421 case OP_COND_EXC_NC:
4422 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4423 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4425 case OP_COND_EXC_IOV:
4426 case OP_COND_EXC_INO:
4427 case OP_COND_EXC_IC:
4428 case OP_COND_EXC_INC:
4429 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4430 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4433 /* floating point opcodes */
4435 double d = *(double *)ins->inst_p0;
4437 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4438 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4441 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4442 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4447 float f = *(float *)ins->inst_p0;
4449 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4450 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4453 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4454 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4455 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4459 case OP_STORER8_MEMBASE_REG:
4460 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4462 case OP_LOADR8_MEMBASE:
4463 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4465 case OP_STORER4_MEMBASE_REG:
4466 /* This requires a double->single conversion */
4467 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4468 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4470 case OP_LOADR4_MEMBASE:
4471 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4472 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4474 case OP_ICONV_TO_R4: /* FIXME: change precision */
4475 case OP_ICONV_TO_R8:
4476 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4478 case OP_LCONV_TO_R4: /* FIXME: change precision */
4479 case OP_LCONV_TO_R8:
4480 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4482 case OP_FCONV_TO_R4:
4483 /* FIXME: nothing to do ?? */
4485 case OP_FCONV_TO_I1:
4486 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4488 case OP_FCONV_TO_U1:
4489 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4491 case OP_FCONV_TO_I2:
4492 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4494 case OP_FCONV_TO_U2:
4495 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4497 case OP_FCONV_TO_U4:
4498 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4500 case OP_FCONV_TO_I4:
4502 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4504 case OP_FCONV_TO_I8:
4505 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4507 case OP_LCONV_TO_R_UN: {
4510 /* Based on gcc code */
4511 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4512 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4515 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4516 br [1] = code; x86_jump8 (code, 0);
4517 amd64_patch (br [0], code);
4520 /* Save to the red zone */
4521 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4522 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4523 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4524 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4525 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4526 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4527 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4528 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4529 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4531 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4532 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4533 amd64_patch (br [1], code);
4536 case OP_LCONV_TO_OVF_U4:
4537 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4538 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4539 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4541 case OP_LCONV_TO_OVF_I4_UN:
4542 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4543 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4544 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4547 if (ins->dreg != ins->sreg1)
4548 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4551 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4554 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4557 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4560 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4563 static double r8_0 = -0.0;
4565 g_assert (ins->sreg1 == ins->dreg);
4567 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4568 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4572 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4575 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4578 static guint64 d = 0x7fffffffffffffffUL;
4580 g_assert (ins->sreg1 == ins->dreg);
4582 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4583 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4587 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4590 g_assert (cfg->opt & MONO_OPT_CMOV);
4591 g_assert (ins->dreg == ins->sreg1);
4592 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4593 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4596 g_assert (cfg->opt & MONO_OPT_CMOV);
4597 g_assert (ins->dreg == ins->sreg1);
4598 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4599 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4602 g_assert (cfg->opt & MONO_OPT_CMOV);
4603 g_assert (ins->dreg == ins->sreg1);
4604 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4605 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4608 g_assert (cfg->opt & MONO_OPT_CMOV);
4609 g_assert (ins->dreg == ins->sreg1);
4610 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4611 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4614 g_assert (cfg->opt & MONO_OPT_CMOV);
4615 g_assert (ins->dreg == ins->sreg1);
4616 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4617 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4620 g_assert (cfg->opt & MONO_OPT_CMOV);
4621 g_assert (ins->dreg == ins->sreg1);
4622 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4623 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4626 g_assert (cfg->opt & MONO_OPT_CMOV);
4627 g_assert (ins->dreg == ins->sreg1);
4628 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4629 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4632 g_assert (cfg->opt & MONO_OPT_CMOV);
4633 g_assert (ins->dreg == ins->sreg1);
4634 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4635 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4641 * The two arguments are swapped because the fbranch instructions
4642 * depend on this for the non-sse case to work.
4644 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4647 /* zeroing the register at the start results in
4648 * shorter and faster code (we can also remove the widening op)
4650 guchar *unordered_check;
4651 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4652 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4653 unordered_check = code;
4654 x86_branch8 (code, X86_CC_P, 0, FALSE);
4655 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4656 amd64_patch (unordered_check, code);
4661 /* zeroing the register at the start results in
4662 * shorter and faster code (we can also remove the widening op)
4664 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4665 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4666 if (ins->opcode == OP_FCLT_UN) {
4667 guchar *unordered_check = code;
4668 guchar *jump_to_end;
4669 x86_branch8 (code, X86_CC_P, 0, FALSE);
4670 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4672 x86_jump8 (code, 0);
4673 amd64_patch (unordered_check, code);
4674 amd64_inc_reg (code, ins->dreg);
4675 amd64_patch (jump_to_end, code);
4677 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4682 /* zeroing the register at the start results in
4683 * shorter and faster code (we can also remove the widening op)
4685 guchar *unordered_check;
4686 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4687 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4688 if (ins->opcode == OP_FCGT) {
4689 unordered_check = code;
4690 x86_branch8 (code, X86_CC_P, 0, FALSE);
4691 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4692 amd64_patch (unordered_check, code);
4694 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4698 case OP_FCLT_MEMBASE:
4699 case OP_FCGT_MEMBASE:
4700 case OP_FCLT_UN_MEMBASE:
4701 case OP_FCGT_UN_MEMBASE:
4702 case OP_FCEQ_MEMBASE: {
4703 guchar *unordered_check, *jump_to_end;
4706 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4707 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4709 switch (ins->opcode) {
4710 case OP_FCEQ_MEMBASE:
4711 x86_cond = X86_CC_EQ;
4713 case OP_FCLT_MEMBASE:
4714 case OP_FCLT_UN_MEMBASE:
4715 x86_cond = X86_CC_LT;
4717 case OP_FCGT_MEMBASE:
4718 case OP_FCGT_UN_MEMBASE:
4719 x86_cond = X86_CC_GT;
4722 g_assert_not_reached ();
4725 unordered_check = code;
4726 x86_branch8 (code, X86_CC_P, 0, FALSE);
4727 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4729 switch (ins->opcode) {
4730 case OP_FCEQ_MEMBASE:
4731 case OP_FCLT_MEMBASE:
4732 case OP_FCGT_MEMBASE:
4733 amd64_patch (unordered_check, code);
4735 case OP_FCLT_UN_MEMBASE:
4736 case OP_FCGT_UN_MEMBASE:
4738 x86_jump8 (code, 0);
4739 amd64_patch (unordered_check, code);
4740 amd64_inc_reg (code, ins->dreg);
4741 amd64_patch (jump_to_end, code);
4749 guchar *jump = code;
4750 x86_branch8 (code, X86_CC_P, 0, TRUE);
4751 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4752 amd64_patch (jump, code);
4756 /* Branch if C013 != 100 */
4757 /* branch if !ZF or (PF|CF) */
4758 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4759 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4760 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4763 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4766 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4767 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4771 if (ins->opcode == OP_FBGT) {
4774 /* skip branch if C1=1 */
4776 x86_branch8 (code, X86_CC_P, 0, FALSE);
4777 /* branch if (C0 | C3) = 1 */
4778 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4779 amd64_patch (br1, code);
4782 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4786 /* Branch if C013 == 100 or 001 */
4789 /* skip branch if C1=1 */
4791 x86_branch8 (code, X86_CC_P, 0, FALSE);
4792 /* branch if (C0 | C3) = 1 */
4793 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4794 amd64_patch (br1, code);
4798 /* Branch if C013 == 000 */
4799 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4802 /* Branch if C013=000 or 100 */
4805 /* skip branch if C1=1 */
4807 x86_branch8 (code, X86_CC_P, 0, FALSE);
4808 /* branch if C0=0 */
4809 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4810 amd64_patch (br1, code);
4814 /* Branch if C013 != 001 */
4815 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4816 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4819 /* Transfer value to the fp stack */
4820 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4821 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4822 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4824 amd64_push_reg (code, AMD64_RAX);
4826 amd64_fnstsw (code);
4827 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4828 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4829 amd64_pop_reg (code, AMD64_RAX);
4830 amd64_fstp (code, 0);
4831 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4832 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4835 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4838 case OP_MEMORY_BARRIER: {
4839 /* Not needed on amd64 */
4842 case OP_ATOMIC_ADD_I4:
4843 case OP_ATOMIC_ADD_I8: {
4844 int dreg = ins->dreg;
4845 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4847 if (dreg == ins->inst_basereg)
4850 if (dreg != ins->sreg2)
4851 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4853 x86_prefix (code, X86_LOCK_PREFIX);
4854 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4856 if (dreg != ins->dreg)
4857 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4861 case OP_ATOMIC_ADD_NEW_I4:
4862 case OP_ATOMIC_ADD_NEW_I8: {
4863 int dreg = ins->dreg;
4864 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4866 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4869 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4870 amd64_prefix (code, X86_LOCK_PREFIX);
4871 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4872 /* dreg contains the old value, add with sreg2 value */
4873 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4875 if (ins->dreg != dreg)
4876 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4880 case OP_ATOMIC_EXCHANGE_I4:
4881 case OP_ATOMIC_EXCHANGE_I8: {
4883 int sreg2 = ins->sreg2;
4884 int breg = ins->inst_basereg;
4886 gboolean need_push = FALSE, rdx_pushed = FALSE;
4888 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4894 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4895 * an explanation of how this works.
4898 /* cmpxchg uses eax as comperand, need to make sure we can use it
4899 * hack to overcome limits in x86 reg allocator
4900 * (req: dreg == eax and sreg2 != eax and breg != eax)
4902 g_assert (ins->dreg == AMD64_RAX);
4904 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4905 /* Highly unlikely, but possible */
4908 /* The pushes invalidate rsp */
4909 if ((breg == AMD64_RAX) || need_push) {
4910 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4914 /* We need the EAX reg for the comparand */
4915 if (ins->sreg2 == AMD64_RAX) {
4916 if (breg != AMD64_R11) {
4917 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4920 g_assert (need_push);
4921 amd64_push_reg (code, AMD64_RDX);
4922 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4928 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4930 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4931 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4932 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4933 amd64_patch (br [1], br [0]);
4936 amd64_pop_reg (code, AMD64_RDX);
4940 case OP_ATOMIC_CAS_I4:
4941 case OP_ATOMIC_CAS_I8: {
4944 if (ins->opcode == OP_ATOMIC_CAS_I8)
4950 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4951 * an explanation of how this works.
4953 g_assert (ins->sreg3 == AMD64_RAX);
4954 g_assert (ins->sreg1 != AMD64_RAX);
4955 g_assert (ins->sreg1 != ins->sreg2);
4957 amd64_prefix (code, X86_LOCK_PREFIX);
4958 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4960 if (ins->dreg != AMD64_RAX)
4961 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4964 #ifdef MONO_ARCH_SIMD_INTRINSICS
4965 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4967 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4970 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4973 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4976 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4979 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4982 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4985 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4986 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4989 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4992 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4995 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4998 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5001 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5004 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5007 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5010 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5013 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5016 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5019 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5022 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5025 case OP_PSHUFLEW_HIGH:
5026 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5027 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5029 case OP_PSHUFLEW_LOW:
5030 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5031 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5034 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5035 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5039 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5042 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5045 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5048 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5051 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5054 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5057 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5058 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5061 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5064 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5067 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5070 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5073 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5076 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5079 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5082 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5085 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5088 case OP_EXTRACT_MASK:
5089 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5093 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5096 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5099 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5103 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5106 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5109 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5112 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5116 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5119 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5122 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5125 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5129 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5132 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5135 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5139 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5142 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5145 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5149 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5152 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5156 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5159 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5162 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5166 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5169 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5172 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5176 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5179 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5182 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5185 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5189 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5192 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5195 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5198 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5201 case OP_PSUM_ABS_DIFF:
5202 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5205 case OP_UNPACK_LOWB:
5206 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5208 case OP_UNPACK_LOWW:
5209 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5211 case OP_UNPACK_LOWD:
5212 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5214 case OP_UNPACK_LOWQ:
5215 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5217 case OP_UNPACK_LOWPS:
5218 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5220 case OP_UNPACK_LOWPD:
5221 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5224 case OP_UNPACK_HIGHB:
5225 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5227 case OP_UNPACK_HIGHW:
5228 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5230 case OP_UNPACK_HIGHD:
5231 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5233 case OP_UNPACK_HIGHQ:
5234 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5236 case OP_UNPACK_HIGHPS:
5237 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5239 case OP_UNPACK_HIGHPD:
5240 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5244 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5247 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5250 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5253 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5256 case OP_PADDB_SAT_UN:
5257 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5259 case OP_PSUBB_SAT_UN:
5260 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5262 case OP_PADDW_SAT_UN:
5263 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5265 case OP_PSUBW_SAT_UN:
5266 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5270 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5273 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5276 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5279 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5283 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5286 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5289 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5291 case OP_PMULW_HIGH_UN:
5292 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5295 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5299 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5302 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5306 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5309 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5313 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5316 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5320 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5323 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5327 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5330 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5334 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5337 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5341 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5344 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5347 /*TODO: This is appart of the sse spec but not added
5349 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5352 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5357 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5360 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5364 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5367 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5371 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5372 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5374 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5379 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5381 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5382 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5386 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5388 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5389 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5390 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5394 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5396 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5399 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5401 case OP_EXTRACTX_U2:
5402 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5404 case OP_INSERTX_U1_SLOW:
5405 /*sreg1 is the extracted ireg (scratch)
5406 /sreg2 is the to be inserted ireg (scratch)
5407 /dreg is the xreg to receive the value*/
5409 /*clear the bits from the extracted word*/
5410 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5411 /*shift the value to insert if needed*/
5412 if (ins->inst_c0 & 1)
5413 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5414 /*join them together*/
5415 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5416 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5418 case OP_INSERTX_I4_SLOW:
5419 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5420 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5421 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5423 case OP_INSERTX_I8_SLOW:
5424 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5426 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5428 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5431 case OP_INSERTX_R4_SLOW:
5432 switch (ins->inst_c0) {
5434 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5437 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5438 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5439 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5442 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5443 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5444 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5447 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5448 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5449 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5453 case OP_INSERTX_R8_SLOW:
5455 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5457 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5459 case OP_STOREX_MEMBASE_REG:
5460 case OP_STOREX_MEMBASE:
5461 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5463 case OP_LOADX_MEMBASE:
5464 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5466 case OP_LOADX_ALIGNED_MEMBASE:
5467 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5469 case OP_STOREX_ALIGNED_MEMBASE_REG:
5470 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5472 case OP_STOREX_NTA_MEMBASE_REG:
5473 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5475 case OP_PREFETCH_MEMBASE:
5476 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5480 /*FIXME the peephole pass should have killed this*/
5481 if (ins->dreg != ins->sreg1)
5482 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5485 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5487 case OP_ICONV_TO_R8_RAW:
5488 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5489 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5492 case OP_FCONV_TO_R8_X:
5493 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5496 case OP_XCONV_R8_TO_I4:
5497 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5498 switch (ins->backend.source_opcode) {
5499 case OP_FCONV_TO_I1:
5500 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5502 case OP_FCONV_TO_U1:
5503 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5505 case OP_FCONV_TO_I2:
5506 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5508 case OP_FCONV_TO_U2:
5509 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5515 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5516 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5517 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5520 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5521 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5524 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5525 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5528 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5529 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5530 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5533 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5534 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5537 case OP_LIVERANGE_START: {
5538 if (cfg->verbose_level > 1)
5539 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5540 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5543 case OP_LIVERANGE_END: {
5544 if (cfg->verbose_level > 1)
5545 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5546 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5550 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5551 g_assert_not_reached ();
5554 if ((code - cfg->native_code - offset) > max_len) {
5555 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5556 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5557 g_assert_not_reached ();
5561 last_offset = offset;
5564 cfg->code_len = code - cfg->native_code;
5567 #endif /* DISABLE_JIT */
5570 mono_arch_register_lowlevel_calls (void)
5572 /* The signature doesn't matter */
5573 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5577 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5579 MonoJumpInfo *patch_info;
5580 gboolean compile_aot = !run_cctors;
5582 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5583 unsigned char *ip = patch_info->ip.i + code;
5584 unsigned char *target;
5586 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5589 switch (patch_info->type) {
5590 case MONO_PATCH_INFO_BB:
5591 case MONO_PATCH_INFO_LABEL:
5594 /* No need to patch these */
5599 switch (patch_info->type) {
5600 case MONO_PATCH_INFO_NONE:
5602 case MONO_PATCH_INFO_METHOD_REL:
5603 case MONO_PATCH_INFO_R8:
5604 case MONO_PATCH_INFO_R4:
5605 g_assert_not_reached ();
5607 case MONO_PATCH_INFO_BB:
5614 * Debug code to help track down problems where the target of a near call is
5617 if (amd64_is_near_call (ip)) {
5618 gint64 disp = (guint8*)target - (guint8*)ip;
5620 if (!amd64_is_imm32 (disp)) {
5621 printf ("TYPE: %d\n", patch_info->type);
5622 switch (patch_info->type) {
5623 case MONO_PATCH_INFO_INTERNAL_METHOD:
5624 printf ("V: %s\n", patch_info->data.name);
5626 case MONO_PATCH_INFO_METHOD_JUMP:
5627 case MONO_PATCH_INFO_METHOD:
5628 printf ("V: %s\n", patch_info->data.method->name);
5636 amd64_patch (ip, (gpointer)target);
5643 get_max_epilog_size (MonoCompile *cfg)
5645 int max_epilog_size = 16;
5647 if (cfg->method->save_lmf)
5648 max_epilog_size += 256;
5650 if (mono_jit_trace_calls != NULL)
5651 max_epilog_size += 50;
5653 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5654 max_epilog_size += 50;
5656 max_epilog_size += (AMD64_NREG * 2);
5658 return max_epilog_size;
5662 * This macro is used for testing whenever the unwinder works correctly at every point
5663 * where an async exception can happen.
5665 /* This will generate a SIGSEGV at the given point in the code */
5666 #define async_exc_point(code) do { \
5667 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5668 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5669 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5670 cfg->arch.async_point_count ++; \
5675 mono_arch_emit_prolog (MonoCompile *cfg)
5677 MonoMethod *method = cfg->method;
5679 MonoMethodSignature *sig;
5681 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5684 gint32 lmf_offset = cfg->arch.lmf_offset;
5685 gboolean args_clobbered = FALSE;
5686 gboolean trace = FALSE;
5688 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5690 code = cfg->native_code = g_malloc (cfg->code_size);
5692 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5695 /* Amount of stack space allocated by register saving code */
5698 /* Offset between RSP and the CFA */
5702 * The prolog consists of the following parts:
5704 * - push rbp, mov rbp, rsp
5705 * - save callee saved regs using pushes
5707 * - save rgctx if needed
5708 * - save lmf if needed
5711 * - save rgctx if needed
5712 * - save lmf if needed
5713 * - save callee saved regs using moves
5718 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5719 // IP saved at CFA - 8
5720 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5721 async_exc_point (code);
5723 if (!cfg->arch.omit_fp) {
5724 amd64_push_reg (code, AMD64_RBP);
5726 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5727 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5728 async_exc_point (code);
5730 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5733 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5734 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5735 async_exc_point (code);
5737 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5741 /* Save callee saved registers */
5742 if (!cfg->arch.omit_fp && !method->save_lmf) {
5743 int offset = cfa_offset;
5745 for (i = 0; i < AMD64_NREG; ++i)
5746 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5747 amd64_push_reg (code, i);
5748 pos += sizeof (gpointer);
5750 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5751 async_exc_point (code);
5755 /* The param area is always at offset 0 from sp */
5756 /* This needs to be allocated here, since it has to come after the spill area */
5757 if (cfg->arch.no_pushes && cfg->param_area) {
5758 if (cfg->arch.omit_fp)
5760 g_assert_not_reached ();
5761 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5764 if (cfg->arch.omit_fp) {
5766 * On enter, the stack is misaligned by the the pushing of the return
5767 * address. It is either made aligned by the pushing of %rbp, or by
5770 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5771 if ((alloc_size % 16) == 0)
5774 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5779 cfg->arch.stack_alloc_size = alloc_size;
5781 /* Allocate stack frame */
5783 /* See mono_emit_stack_alloc */
5784 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5785 guint32 remaining_size = alloc_size;
5786 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5787 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5788 guint32 offset = code - cfg->native_code;
5789 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5790 while (required_code_size >= (cfg->code_size - offset))
5791 cfg->code_size *= 2;
5792 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5793 code = cfg->native_code + offset;
5794 mono_jit_stats.code_reallocs++;
5797 while (remaining_size >= 0x1000) {
5798 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5799 if (cfg->arch.omit_fp) {
5800 cfa_offset += 0x1000;
5801 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5803 async_exc_point (code);
5805 if (cfg->arch.omit_fp)
5806 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5809 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5810 remaining_size -= 0x1000;
5812 if (remaining_size) {
5813 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5814 if (cfg->arch.omit_fp) {
5815 cfa_offset += remaining_size;
5816 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5817 async_exc_point (code);
5820 if (cfg->arch.omit_fp)
5821 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5825 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5826 if (cfg->arch.omit_fp) {
5827 cfa_offset += alloc_size;
5828 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5829 async_exc_point (code);
5834 /* Stack alignment check */
5837 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5838 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5839 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5840 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5841 amd64_breakpoint (code);
5845 #ifndef TARGET_WIN32
5846 if (mini_get_debug_options ()->init_stacks) {
5847 /* Fill the stack frame with a dummy value to force deterministic behavior */
5849 /* Save registers to the red zone */
5850 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5851 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5853 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5854 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5855 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5858 amd64_prefix (code, X86_REP_PREFIX);
5861 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5862 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5867 if (method->save_lmf) {
5869 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5872 * sp is saved right before calls but we need to save it here too so
5873 * async stack walks would work.
5875 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5876 /* Skip method (only needed for trampoline LMF frames) */
5877 /* Save callee saved regs */
5878 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5882 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5883 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5884 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5885 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5886 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5887 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5889 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5890 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5898 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5899 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5900 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5905 /* Save callee saved registers */
5906 if (cfg->arch.omit_fp && !method->save_lmf) {
5907 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5909 /* Save caller saved registers after sp is adjusted */
5910 /* The registers are saved at the bottom of the frame */
5911 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5912 for (i = 0; i < AMD64_NREG; ++i)
5913 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5914 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5915 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5916 save_area_offset += 8;
5917 async_exc_point (code);
5921 /* store runtime generic context */
5922 if (cfg->rgctx_var) {
5923 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5924 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5926 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5929 /* compute max_length in order to use short forward jumps */
5930 max_epilog_size = get_max_epilog_size (cfg);
5931 if (cfg->opt & MONO_OPT_BRANCH) {
5932 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5936 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5938 /* max alignment for loops */
5939 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5940 max_length += LOOP_ALIGNMENT;
5942 MONO_BB_FOR_EACH_INS (bb, ins) {
5943 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5946 /* Take prolog and epilog instrumentation into account */
5947 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5948 max_length += max_epilog_size;
5950 bb->max_length = max_length;
5954 sig = mono_method_signature (method);
5957 cinfo = cfg->arch.cinfo;
5959 if (sig->ret->type != MONO_TYPE_VOID) {
5960 /* Save volatile arguments to the stack */
5961 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5962 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5965 /* Keep this in sync with emit_load_volatile_arguments */
5966 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5967 ArgInfo *ainfo = cinfo->args + i;
5968 gint32 stack_offset;
5971 ins = cfg->args [i];
5973 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5974 /* Unused arguments */
5977 if (sig->hasthis && (i == 0))
5978 arg_type = &mono_defaults.object_class->byval_arg;
5980 arg_type = sig->params [i - sig->hasthis];
5982 stack_offset = ainfo->offset + ARGS_OFFSET;
5984 if (cfg->globalra) {
5985 /* All the other moves are done by the register allocator */
5986 switch (ainfo->storage) {
5987 case ArgInFloatSSEReg:
5988 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5990 case ArgValuetypeInReg:
5991 for (quad = 0; quad < 2; quad ++) {
5992 switch (ainfo->pair_storage [quad]) {
5994 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5996 case ArgInFloatSSEReg:
5997 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5999 case ArgInDoubleSSEReg:
6000 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6005 g_assert_not_reached ();
6016 /* Save volatile arguments to the stack */
6017 if (ins->opcode != OP_REGVAR) {
6018 switch (ainfo->storage) {
6024 if (stack_offset & 0x1)
6026 else if (stack_offset & 0x2)
6028 else if (stack_offset & 0x4)
6033 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6036 case ArgInFloatSSEReg:
6037 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6039 case ArgInDoubleSSEReg:
6040 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6042 case ArgValuetypeInReg:
6043 for (quad = 0; quad < 2; quad ++) {
6044 switch (ainfo->pair_storage [quad]) {
6046 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6048 case ArgInFloatSSEReg:
6049 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6051 case ArgInDoubleSSEReg:
6052 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6057 g_assert_not_reached ();
6061 case ArgValuetypeAddrInIReg:
6062 if (ainfo->pair_storage [0] == ArgInIReg)
6063 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6069 /* Argument allocated to (non-volatile) register */
6070 switch (ainfo->storage) {
6072 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6075 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6078 g_assert_not_reached ();
6083 /* Might need to attach the thread to the JIT or change the domain for the callback */
6084 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6085 guint64 domain = (guint64)cfg->domain;
6087 args_clobbered = TRUE;
6090 * The call might clobber argument registers, but they are already
6091 * saved to the stack/global regs.
6093 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6094 guint8 *buf, *no_domain_branch;
6096 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6097 if (cfg->compile_aot) {
6098 /* AOT code is only used in the root domain */
6099 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6101 if ((domain >> 32) == 0)
6102 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6104 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6106 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6107 no_domain_branch = code;
6108 x86_branch8 (code, X86_CC_NE, 0, 0);
6109 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6110 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6112 x86_branch8 (code, X86_CC_NE, 0, 0);
6113 amd64_patch (no_domain_branch, code);
6114 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6115 (gpointer)"mono_jit_thread_attach", TRUE);
6116 amd64_patch (buf, code);
6118 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6119 /* FIXME: Add a separate key for LMF to avoid this */
6120 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6123 g_assert (!cfg->compile_aot);
6124 if (cfg->compile_aot) {
6125 /* AOT code is only used in the root domain */
6126 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6128 if ((domain >> 32) == 0)
6129 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6131 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6133 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6134 (gpointer)"mono_jit_thread_attach", TRUE);
6138 if (method->save_lmf) {
6139 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6141 * Optimized version which uses the mono_lmf TLS variable instead of
6142 * indirection through the mono_lmf_addr TLS variable.
6144 /* %rax = previous_lmf */
6145 x86_prefix (code, X86_FS_PREFIX);
6146 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6148 /* Save previous_lmf */
6149 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6151 if (lmf_offset == 0) {
6152 x86_prefix (code, X86_FS_PREFIX);
6153 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6155 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6156 x86_prefix (code, X86_FS_PREFIX);
6157 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6160 if (lmf_addr_tls_offset != -1) {
6161 /* Load lmf quicky using the FS register */
6162 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6164 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6165 /* FIXME: Add a separate key for LMF to avoid this */
6166 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6171 * The call might clobber argument registers, but they are already
6172 * saved to the stack/global regs.
6174 args_clobbered = TRUE;
6175 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6176 (gpointer)"mono_get_lmf_addr", TRUE);
6180 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6181 /* Save previous_lmf */
6182 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6183 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6185 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6186 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6191 args_clobbered = TRUE;
6192 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6195 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6196 args_clobbered = TRUE;
6199 * Optimize the common case of the first bblock making a call with the same
6200 * arguments as the method. This works because the arguments are still in their
6201 * original argument registers.
6202 * FIXME: Generalize this
6204 if (!args_clobbered) {
6205 MonoBasicBlock *first_bb = cfg->bb_entry;
6208 next = mono_bb_first_ins (first_bb);
6209 if (!next && first_bb->next_bb) {
6210 first_bb = first_bb->next_bb;
6211 next = mono_bb_first_ins (first_bb);
6214 if (first_bb->in_count > 1)
6217 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6218 ArgInfo *ainfo = cinfo->args + i;
6219 gboolean match = FALSE;
6221 ins = cfg->args [i];
6222 if (ins->opcode != OP_REGVAR) {
6223 switch (ainfo->storage) {
6225 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6226 if (next->dreg == ainfo->reg) {
6230 next->opcode = OP_MOVE;
6231 next->sreg1 = ainfo->reg;
6232 /* Only continue if the instruction doesn't change argument regs */
6233 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6243 /* Argument allocated to (non-volatile) register */
6244 switch (ainfo->storage) {
6246 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6258 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6265 /* Initialize ss_trigger_page_var */
6266 if (cfg->arch.ss_trigger_page_var) {
6267 MonoInst *var = cfg->arch.ss_trigger_page_var;
6269 g_assert (!cfg->compile_aot);
6270 g_assert (var->opcode == OP_REGOFFSET);
6272 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6273 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6276 cfg->code_len = code - cfg->native_code;
6278 g_assert (cfg->code_len < cfg->code_size);
6284 mono_arch_emit_epilog (MonoCompile *cfg)
6286 MonoMethod *method = cfg->method;
6289 int max_epilog_size;
6291 gint32 lmf_offset = cfg->arch.lmf_offset;
6293 max_epilog_size = get_max_epilog_size (cfg);
6295 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6296 cfg->code_size *= 2;
6297 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6298 mono_jit_stats.code_reallocs++;
6301 code = cfg->native_code + cfg->code_len;
6303 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6304 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6306 /* the code restoring the registers must be kept in sync with OP_JMP */
6309 if (method->save_lmf) {
6310 /* check if we need to restore protection of the stack after a stack overflow */
6311 if (mono_get_jit_tls_offset () != -1) {
6313 code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6314 /* we load the value in a separate instruction: this mechanism may be
6315 * used later as a safer way to do thread interruption
6317 amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6318 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6320 x86_branch8 (code, X86_CC_Z, 0, FALSE);
6321 /* note that the call trampoline will preserve eax/edx */
6322 x86_call_reg (code, X86_ECX);
6323 x86_patch (patch, code);
6325 /* FIXME: maybe save the jit tls in the prolog */
6327 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6329 * Optimized version which uses the mono_lmf TLS variable instead of indirection
6330 * through the mono_lmf_addr TLS variable.
6332 /* reg = previous_lmf */
6333 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6334 x86_prefix (code, X86_FS_PREFIX);
6335 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6337 /* Restore previous lmf */
6338 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6339 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6340 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6343 /* Restore caller saved regs */
6344 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6345 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6347 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6348 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6350 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6351 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6353 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6354 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6356 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6357 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6359 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6360 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6363 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6364 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6366 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6367 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6372 if (cfg->arch.omit_fp) {
6373 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6375 for (i = 0; i < AMD64_NREG; ++i)
6376 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6377 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6378 save_area_offset += 8;
6382 for (i = 0; i < AMD64_NREG; ++i)
6383 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6384 pos -= sizeof (gpointer);
6387 if (pos == - sizeof (gpointer)) {
6388 /* Only one register, so avoid lea */
6389 for (i = AMD64_NREG - 1; i > 0; --i)
6390 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6391 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6395 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6397 /* Pop registers in reverse order */
6398 for (i = AMD64_NREG - 1; i > 0; --i)
6399 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6400 amd64_pop_reg (code, i);
6407 /* Load returned vtypes into registers if needed */
6408 cinfo = cfg->arch.cinfo;
6409 if (cinfo->ret.storage == ArgValuetypeInReg) {
6410 ArgInfo *ainfo = &cinfo->ret;
6411 MonoInst *inst = cfg->ret;
6413 for (quad = 0; quad < 2; quad ++) {
6414 switch (ainfo->pair_storage [quad]) {
6416 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6418 case ArgInFloatSSEReg:
6419 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6421 case ArgInDoubleSSEReg:
6422 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6427 g_assert_not_reached ();
6432 if (cfg->arch.omit_fp) {
6433 if (cfg->arch.stack_alloc_size)
6434 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6438 async_exc_point (code);
6441 cfg->code_len = code - cfg->native_code;
6443 g_assert (cfg->code_len < cfg->code_size);
6447 mono_arch_emit_exceptions (MonoCompile *cfg)
6449 MonoJumpInfo *patch_info;
6452 MonoClass *exc_classes [16];
6453 guint8 *exc_throw_start [16], *exc_throw_end [16];
6454 guint32 code_size = 0;
6456 /* Compute needed space */
6457 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6458 if (patch_info->type == MONO_PATCH_INFO_EXC)
6460 if (patch_info->type == MONO_PATCH_INFO_R8)
6461 code_size += 8 + 15; /* sizeof (double) + alignment */
6462 if (patch_info->type == MONO_PATCH_INFO_R4)
6463 code_size += 4 + 15; /* sizeof (float) + alignment */
6466 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6467 cfg->code_size *= 2;
6468 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6469 mono_jit_stats.code_reallocs++;
6472 code = cfg->native_code + cfg->code_len;
6474 /* add code to raise exceptions */
6476 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6477 switch (patch_info->type) {
6478 case MONO_PATCH_INFO_EXC: {
6479 MonoClass *exc_class;
6483 amd64_patch (patch_info->ip.i + cfg->native_code, code);
6485 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6486 g_assert (exc_class);
6487 throw_ip = patch_info->ip.i;
6489 //x86_breakpoint (code);
6490 /* Find a throw sequence for the same exception class */
6491 for (i = 0; i < nthrows; ++i)
6492 if (exc_classes [i] == exc_class)
6495 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6496 x86_jump_code (code, exc_throw_start [i]);
6497 patch_info->type = MONO_PATCH_INFO_NONE;
6501 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6505 exc_classes [nthrows] = exc_class;
6506 exc_throw_start [nthrows] = code;
6508 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6510 patch_info->type = MONO_PATCH_INFO_NONE;
6512 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6514 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6519 exc_throw_end [nthrows] = code;
6531 /* Handle relocations with RIP relative addressing */
6532 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6533 gboolean remove = FALSE;
6535 switch (patch_info->type) {
6536 case MONO_PATCH_INFO_R8:
6537 case MONO_PATCH_INFO_R4: {
6540 /* The SSE opcodes require a 16 byte alignment */
6541 code = (guint8*)ALIGN_TO (code, 16);
6543 pos = cfg->native_code + patch_info->ip.i;
6545 if (IS_REX (pos [1]))
6546 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6548 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6550 if (patch_info->type == MONO_PATCH_INFO_R8) {
6551 *(double*)code = *(double*)patch_info->data.target;
6552 code += sizeof (double);
6554 *(float*)code = *(float*)patch_info->data.target;
6555 code += sizeof (float);
6566 if (patch_info == cfg->patch_info)
6567 cfg->patch_info = patch_info->next;
6571 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6573 tmp->next = patch_info->next;
6578 cfg->code_len = code - cfg->native_code;
6580 g_assert (cfg->code_len < cfg->code_size);
6584 #endif /* DISABLE_JIT */
6587 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6590 CallInfo *cinfo = NULL;
6591 MonoMethodSignature *sig;
6593 int i, n, stack_area = 0;
6595 /* Keep this in sync with mono_arch_get_argument_info */
6597 if (enable_arguments) {
6598 /* Allocate a new area on the stack and save arguments there */
6599 sig = mono_method_signature (cfg->method);
6601 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6603 n = sig->param_count + sig->hasthis;
6605 stack_area = ALIGN_TO (n * 8, 16);
6607 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6609 for (i = 0; i < n; ++i) {
6610 inst = cfg->args [i];
6612 if (inst->opcode == OP_REGVAR)
6613 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6615 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6616 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6621 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6622 amd64_set_reg_template (code, AMD64_ARG_REG1);
6623 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6624 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6626 if (enable_arguments)
6627 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6641 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6644 int save_mode = SAVE_NONE;
6645 MonoMethod *method = cfg->method;
6646 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6648 switch (ret_type->type) {
6649 case MONO_TYPE_VOID:
6650 /* special case string .ctor icall */
6651 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6652 save_mode = SAVE_EAX;
6654 save_mode = SAVE_NONE;
6658 save_mode = SAVE_EAX;
6662 save_mode = SAVE_XMM;
6664 case MONO_TYPE_GENERICINST:
6665 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6666 save_mode = SAVE_EAX;
6670 case MONO_TYPE_VALUETYPE:
6671 save_mode = SAVE_STRUCT;
6674 save_mode = SAVE_EAX;
6678 /* Save the result and copy it into the proper argument register */
6679 switch (save_mode) {
6681 amd64_push_reg (code, AMD64_RAX);
6683 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6684 if (enable_arguments)
6685 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6689 if (enable_arguments)
6690 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6693 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6694 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6696 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6698 * The result is already in the proper argument register so no copying
6705 g_assert_not_reached ();
6708 /* Set %al since this is a varargs call */
6709 if (save_mode == SAVE_XMM)
6710 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6712 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6714 if (preserve_argument_registers) {
6715 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6716 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6719 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6720 amd64_set_reg_template (code, AMD64_ARG_REG1);
6721 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6723 if (preserve_argument_registers) {
6724 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6725 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6728 /* Restore result */
6729 switch (save_mode) {
6731 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6732 amd64_pop_reg (code, AMD64_RAX);
6738 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6739 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6740 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6745 g_assert_not_reached ();
6752 mono_arch_flush_icache (guint8 *code, gint size)
6758 mono_arch_flush_register_windows (void)
6763 mono_arch_is_inst_imm (gint64 imm)
6765 return amd64_is_imm32 (imm);
6769 * Determine whenever the trap whose info is in SIGINFO is caused by
6773 mono_arch_is_int_overflow (void *sigctx, void *info)
6780 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6782 rip = (guint8*)ctx.rip;
6784 if (IS_REX (rip [0])) {
6785 reg = amd64_rex_b (rip [0]);
6791 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6793 reg += x86_modrm_rm (rip [1]);
6833 g_assert_not_reached ();
6845 mono_arch_get_patch_offset (guint8 *code)
6851 * mono_breakpoint_clean_code:
6853 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6854 * breakpoints in the original code, they are removed in the copy.
6856 * Returns TRUE if no sw breakpoint was present.
6859 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6862 gboolean can_write = TRUE;
6864 * If method_start is non-NULL we need to perform bound checks, since we access memory
6865 * at code - offset we could go before the start of the method and end up in a different
6866 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6869 if (!method_start || code - offset >= method_start) {
6870 memcpy (buf, code - offset, size);
6872 int diff = code - method_start;
6873 memset (buf, 0, size);
6874 memcpy (buf + offset - diff, method_start, diff + size - offset);
6877 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6878 int idx = mono_breakpoint_info_index [i];
6882 ptr = mono_breakpoint_info [idx].address;
6883 if (ptr >= code && ptr < code + size) {
6884 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6886 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6887 buf [ptr - code] = saved_byte;
6894 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6900 MonoJitInfo *ji = NULL;
6903 /* code - 9 might be before the start of the method */
6904 /* FIXME: Avoid this expensive call somehow */
6905 ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6908 mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6916 * A given byte sequence can match more than case here, so we have to be
6917 * really careful about the ordering of the cases. Longer sequences
6919 * There are two types of calls:
6920 * - direct calls: 0xff address_byte 8/32 bits displacement
6921 * - indirect calls: nop nop nop <call>
6922 * The nops make sure we don't confuse the instruction preceeding an indirect
6923 * call with a direct call.
6925 if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6926 /* call OFFSET(%rip) */
6927 disp = *(guint32*)(code + 3);
6928 return (gpointer*)(code + disp + 7);
6929 } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6930 /* call *[reg+disp32] using indexed addressing */
6931 /* The LLVM JIT emits this, and we emit it too for %r12 */
6932 if (IS_REX (code [-1])) {
6934 g_assert (amd64_rex_x (rex) == 0);
6936 reg = amd64_sib_base (code [2]);
6937 disp = *(gint32*)(code + 3);
6938 } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6939 /* call *[reg+disp32] */
6940 if (IS_REX (code [0]))
6942 reg = amd64_modrm_rm (code [2]);
6943 disp = *(gint32*)(code + 3);
6944 /* R10 is clobbered by the IMT thunk code */
6945 g_assert (reg != AMD64_R10);
6946 } else if (code [2] == 0xe8) {
6949 } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6950 /* call *[r12+disp8] using indexed addressing */
6951 if (IS_REX (code [2]))
6953 reg = amd64_sib_base (code [5]);
6954 disp = *(gint8*)(code + 6);
6955 } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6958 } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6959 /* call *[reg+disp8] */
6960 if (IS_REX (code [3]))
6962 reg = amd64_modrm_rm (code [5]);
6963 disp = *(gint8*)(code + 6);
6964 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6966 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6968 if (IS_REX (code [4]))
6970 reg = amd64_modrm_rm (code [6]);
6974 g_assert_not_reached ();
6976 reg += amd64_rex_b (rex);
6978 /* R11 is clobbered by the trampoline code */
6979 g_assert (reg != AMD64_R11);
6981 *displacement = disp;
6982 return (gpointer)regs [reg];
6986 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6988 int this_reg = AMD64_ARG_REG1;
6990 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6994 gsctx = mono_get_generic_context_from_code (code);
6996 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6998 if (cinfo->ret.storage != ArgValuetypeInReg)
6999 this_reg = AMD64_ARG_REG2;
7007 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
7009 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
7012 #define MAX_ARCH_DELEGATE_PARAMS 10
7015 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7017 guint8 *code, *start;
7021 start = code = mono_global_codeman_reserve (64);
7023 /* Replace the this argument with the target */
7024 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7025 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7026 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7028 g_assert ((code - start) < 64);
7030 start = code = mono_global_codeman_reserve (64);
7032 if (param_count == 0) {
7033 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7035 /* We have to shift the arguments left */
7036 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7037 for (i = 0; i < param_count; ++i) {
7040 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7042 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7044 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7048 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7050 g_assert ((code - start) < 64);
7053 mono_debug_add_delegate_trampoline (start, code - start);
7056 *code_len = code - start;
7062 * mono_arch_get_delegate_invoke_impls:
7064 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
7068 mono_arch_get_delegate_invoke_impls (void)
7075 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7076 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
7078 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7079 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7080 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
7087 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7089 guint8 *code, *start;
7092 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7095 /* FIXME: Support more cases */
7096 if (MONO_TYPE_ISSTRUCT (sig->ret))
7100 static guint8* cached = NULL;
7106 start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7108 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7110 mono_memory_barrier ();
7114 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7115 for (i = 0; i < sig->param_count; ++i)
7116 if (!mono_is_regsize_var (sig->params [i]))
7118 if (sig->param_count > 4)
7121 code = cache [sig->param_count];
7125 if (mono_aot_only) {
7126 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7127 start = mono_aot_get_named_code (name);
7130 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7133 mono_memory_barrier ();
7135 cache [sig->param_count] = start;
7142 * Support for fast access to the thread-local lmf structure using the GS
7143 * segment register on NPTL + kernel 2.6.x.
7146 static gboolean tls_offset_inited = FALSE;
7149 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7151 if (!tls_offset_inited) {
7154 * We need to init this multiple times, since when we are first called, the key might not
7155 * be initialized yet.
7157 appdomain_tls_offset = mono_domain_get_tls_key ();
7158 lmf_tls_offset = mono_get_jit_tls_key ();
7159 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7161 /* Only 64 tls entries can be accessed using inline code */
7162 if (appdomain_tls_offset >= 64)
7163 appdomain_tls_offset = -1;
7164 if (lmf_tls_offset >= 64)
7165 lmf_tls_offset = -1;
7167 tls_offset_inited = TRUE;
7169 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7171 appdomain_tls_offset = mono_domain_get_tls_offset ();
7172 lmf_tls_offset = mono_get_lmf_tls_offset ();
7173 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7179 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7183 #ifdef MONO_ARCH_HAVE_IMT
7185 #define CMP_SIZE (6 + 1)
7186 #define CMP_REG_REG_SIZE (4 + 1)
7187 #define BR_SMALL_SIZE 2
7188 #define BR_LARGE_SIZE 6
7189 #define MOV_REG_IMM_SIZE 10
7190 #define MOV_REG_IMM_32BIT_SIZE 6
7191 #define JUMP_REG_SIZE (2 + 1)
7194 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7196 int i, distance = 0;
7197 for (i = start; i < target; ++i)
7198 distance += imt_entries [i]->chunk_size;
7203 * LOCKING: called with the domain lock held
7206 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7207 gpointer fail_tramp)
7211 guint8 *code, *start;
7212 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7214 for (i = 0; i < count; ++i) {
7215 MonoIMTCheckItem *item = imt_entries [i];
7216 if (item->is_equals) {
7217 if (item->check_target_idx) {
7218 if (!item->compare_done) {
7219 if (amd64_is_imm32 (item->key))
7220 item->chunk_size += CMP_SIZE;
7222 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7224 if (item->has_target_code) {
7225 item->chunk_size += MOV_REG_IMM_SIZE;
7227 if (vtable_is_32bit)
7228 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7230 item->chunk_size += MOV_REG_IMM_SIZE;
7232 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7235 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7236 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7238 if (vtable_is_32bit)
7239 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7241 item->chunk_size += MOV_REG_IMM_SIZE;
7242 item->chunk_size += JUMP_REG_SIZE;
7243 /* with assert below:
7244 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7249 if (amd64_is_imm32 (item->key))
7250 item->chunk_size += CMP_SIZE;
7252 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7253 item->chunk_size += BR_LARGE_SIZE;
7254 imt_entries [item->check_target_idx]->compare_done = TRUE;
7256 size += item->chunk_size;
7259 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7261 code = mono_domain_code_reserve (domain, size);
7263 for (i = 0; i < count; ++i) {
7264 MonoIMTCheckItem *item = imt_entries [i];
7265 item->code_target = code;
7266 if (item->is_equals) {
7267 gboolean fail_case = !item->check_target_idx && fail_tramp;
7269 if (item->check_target_idx || fail_case) {
7270 if (!item->compare_done || fail_case) {
7271 if (amd64_is_imm32 (item->key))
7272 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7274 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7275 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7278 item->jmp_code = code;
7279 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7280 /* See the comment below about R10 */
7281 if (item->has_target_code) {
7282 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7283 amd64_jump_reg (code, AMD64_R10);
7285 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7286 amd64_jump_membase (code, AMD64_R10, 0);
7290 amd64_patch (item->jmp_code, code);
7291 amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7292 amd64_jump_reg (code, AMD64_R10);
7293 item->jmp_code = NULL;
7296 /* enable the commented code to assert on wrong method */
7298 if (amd64_is_imm32 (item->key))
7299 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7301 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7302 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7304 item->jmp_code = code;
7305 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7306 /* See the comment below about R10 */
7307 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7308 amd64_jump_membase (code, AMD64_R10, 0);
7309 amd64_patch (item->jmp_code, code);
7310 amd64_breakpoint (code);
7311 item->jmp_code = NULL;
7313 /* We're using R10 here because R11
7314 needs to be preserved. R10 needs
7315 to be preserved for calls which
7316 require a runtime generic context,
7317 but interface calls don't. */
7318 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7319 amd64_jump_membase (code, AMD64_R10, 0);
7323 if (amd64_is_imm32 (item->key))
7324 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7326 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7327 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7329 item->jmp_code = code;
7330 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7331 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7333 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7335 g_assert (code - item->code_target <= item->chunk_size);
7337 /* patch the branches to get to the target items */
7338 for (i = 0; i < count; ++i) {
7339 MonoIMTCheckItem *item = imt_entries [i];
7340 if (item->jmp_code) {
7341 if (item->check_target_idx) {
7342 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7348 mono_stats.imt_thunks_size += code - start;
7349 g_assert (code - start <= size);
7355 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7357 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7362 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7364 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7368 mono_arch_get_cie_program (void)
7372 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7373 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7379 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7381 MonoInst *ins = NULL;
7384 if (cmethod->klass == mono_defaults.math_class) {
7385 if (strcmp (cmethod->name, "Sin") == 0) {
7387 } else if (strcmp (cmethod->name, "Cos") == 0) {
7389 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7391 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7396 MONO_INST_NEW (cfg, ins, opcode);
7397 ins->type = STACK_R8;
7398 ins->dreg = mono_alloc_freg (cfg);
7399 ins->sreg1 = args [0]->dreg;
7400 MONO_ADD_INS (cfg->cbb, ins);
7404 if (cfg->opt & MONO_OPT_CMOV) {
7405 if (strcmp (cmethod->name, "Min") == 0) {
7406 if (fsig->params [0]->type == MONO_TYPE_I4)
7408 if (fsig->params [0]->type == MONO_TYPE_U4)
7409 opcode = OP_IMIN_UN;
7410 else if (fsig->params [0]->type == MONO_TYPE_I8)
7412 else if (fsig->params [0]->type == MONO_TYPE_U8)
7413 opcode = OP_LMIN_UN;
7414 } else if (strcmp (cmethod->name, "Max") == 0) {
7415 if (fsig->params [0]->type == MONO_TYPE_I4)
7417 if (fsig->params [0]->type == MONO_TYPE_U4)
7418 opcode = OP_IMAX_UN;
7419 else if (fsig->params [0]->type == MONO_TYPE_I8)
7421 else if (fsig->params [0]->type == MONO_TYPE_U8)
7422 opcode = OP_LMAX_UN;
7427 MONO_INST_NEW (cfg, ins, opcode);
7428 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7429 ins->dreg = mono_alloc_ireg (cfg);
7430 ins->sreg1 = args [0]->dreg;
7431 ins->sreg2 = args [1]->dreg;
7432 MONO_ADD_INS (cfg->cbb, ins);
7436 /* OP_FREM is not IEEE compatible */
7437 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7438 MONO_INST_NEW (cfg, ins, OP_FREM);
7439 ins->inst_i0 = args [0];
7440 ins->inst_i1 = args [1];
7446 * Can't implement CompareExchange methods this way since they have
7454 mono_arch_print_tree (MonoInst *tree, int arity)
7459 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7463 if (appdomain_tls_offset == -1)
7466 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7467 ins->inst_offset = appdomain_tls_offset;
7471 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7474 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7477 case AMD64_RCX: return (gpointer)ctx->rcx;
7478 case AMD64_RDX: return (gpointer)ctx->rdx;
7479 case AMD64_RBX: return (gpointer)ctx->rbx;
7480 case AMD64_RBP: return (gpointer)ctx->rbp;
7481 case AMD64_RSP: return (gpointer)ctx->rsp;
7484 return _CTX_REG (ctx, rax, reg);
7486 return _CTX_REG (ctx, r12, reg - 12);
7488 g_assert_not_reached ();
7492 /* Soft Debug support */
7493 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7496 * mono_arch_set_breakpoint:
7498 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7499 * The location should contain code emitted by OP_SEQ_POINT.
7502 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7505 guint8 *orig_code = code;
7508 * In production, we will use int3 (has to fix the size in the md
7509 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7512 g_assert (code [0] == 0x90);
7513 if (breakpoint_size == 8) {
7514 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7516 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7517 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7520 g_assert (code - orig_code == breakpoint_size);
7524 * mono_arch_clear_breakpoint:
7526 * Clear the breakpoint at IP.
7529 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7534 for (i = 0; i < breakpoint_size; ++i)
7539 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7542 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7545 siginfo_t* sinfo = (siginfo_t*) info;
7546 /* Sometimes the address is off by 4 */
7547 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7555 * mono_arch_get_ip_for_breakpoint:
7557 * Convert the ip in CTX to the address where a breakpoint was placed.
7560 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7562 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7564 /* ip points to the instruction causing the fault */
7565 ip -= (breakpoint_size - breakpoint_fault_size);
7571 * mono_arch_skip_breakpoint:
7573 * Modify CTX so the ip is placed after the breakpoint instruction, so when
7574 * we resume, the instruction is not executed again.
7577 mono_arch_skip_breakpoint (MonoContext *ctx)
7579 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7583 * mono_arch_start_single_stepping:
7585 * Start single stepping.
7588 mono_arch_start_single_stepping (void)
7590 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7594 * mono_arch_stop_single_stepping:
7596 * Stop single stepping.
7599 mono_arch_stop_single_stepping (void)
7601 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7605 * mono_arch_is_single_step_event:
7607 * Return whenever the machine state in SIGCTX corresponds to a single
7611 mono_arch_is_single_step_event (void *info, void *sigctx)
7614 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7617 siginfo_t* sinfo = (siginfo_t*) info;
7618 /* Sometimes the address is off by 4 */
7619 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7627 * mono_arch_get_ip_for_single_step:
7629 * Convert the ip in CTX to the address stored in seq_points.
7632 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7634 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7636 ip += single_step_fault_size;
7642 * mono_arch_skip_single_step:
7644 * Modify CTX so the ip is placed after the single step trigger instruction,
7645 * we resume, the instruction is not executed again.
7648 mono_arch_skip_single_step (MonoContext *ctx)
7650 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7654 * mono_arch_create_seq_point_info:
7656 * Return a pointer to a data structure which is used by the sequence
7657 * point implementation in AOTed code.
7660 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)