mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40
  41 #include "trace.h"
  42 #include "ir-emit.h"
  43 #include "mini-amd64.h"
  44 #include "cpu-amd64.h"
  45 #include "debugger-agent.h"
  46 #include "mini-gc.h"
  47
  48 #ifdef MONO_XEN_OPT
  49 static gboolean optimize_for_xen = TRUE;
  50 #else
  51 #define optimize_for_xen 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  57
  58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  59
  60 #ifdef TARGET_WIN32
  61 /* Under windows, the calling convention is never stdcall */
  62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  63 #else
  64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  65 #endif
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  70 static mono_mutex_t mini_arch_mutex;
  71
  72 /* The single step trampoline */
  73 static gpointer ss_trampoline;
  74
  75 /* The breakpoint trampoline */
  76 static gpointer bp_trampoline;
  77
  78 /* Offset between fp and the first argument in the callee */
  79 #define ARGS_OFFSET 16
  80 #define GP_SCRATCH_REG AMD64_R11
  81
  82 /*
  83  * AMD64 register usage:
  84  * - callee saved registers are used for global register allocation
  85  * - %r11 is used for materializing 64 bit constants in opcodes
  86  * - the rest is used for local allocation
  87  */
  88
  89 /*
  90  * Floating point comparison results:
  91  *                  ZF PF CF
  92  * A > B            0  0  0
  93  * A < B            0  0  1
  94  * A = B            1  0  0
  95  * A > B            0  0  0
  96  * UNORDERED        1  1  1
  97  */
  98
  99 const char*
 100 mono_arch_regname (int reg)
 101 {
 102         switch (reg) {
 103         case AMD64_RAX: return "%rax";
 104         case AMD64_RBX: return "%rbx";
 105         case AMD64_RCX: return "%rcx";
 106         case AMD64_RDX: return "%rdx";
 107         case AMD64_RSP: return "%rsp";
 108         case AMD64_RBP: return "%rbp";
 109         case AMD64_RDI: return "%rdi";
 110         case AMD64_RSI: return "%rsi";
 111         case AMD64_R8: return "%r8";
 112         case AMD64_R9: return "%r9";
 113         case AMD64_R10: return "%r10";
 114         case AMD64_R11: return "%r11";
 115         case AMD64_R12: return "%r12";
 116         case AMD64_R13: return "%r13";
 117         case AMD64_R14: return "%r14";
 118         case AMD64_R15: return "%r15";
 119         }
 120         return "unknown";
 121 }
 122
 123 static const char * packed_xmmregs [] = {
 124         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 125         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 126 };
 127
 128 static const char * single_xmmregs [] = {
 129         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 130         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 131 };
 132
 133 const char*
 134 mono_arch_fregname (int reg)
 135 {
 136         if (reg < AMD64_XMM_NREG)
 137                 return single_xmmregs [reg];
 138         else
 139                 return "unknown";
 140 }
 141
 142 const char *
 143 mono_arch_xregname (int reg)
 144 {
 145         if (reg < AMD64_XMM_NREG)
 146                 return packed_xmmregs [reg];
 147         else
 148                 return "unknown";
 149 }
 150
 151 static gboolean
 152 debug_omit_fp (void)
 153 {
 154 #if 0
 155         return mono_debug_count ();
 156 #else
 157         return TRUE;
 158 #endif
 159 }
 160
 161 static inline gboolean
 162 amd64_is_near_call (guint8 *code)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         return code [0] == 0xe8;
 169 }
 170
 171 static inline gboolean
 172 amd64_use_imm32 (gint64 val)
 173 {
 174         if (mini_get_debug_options()->single_imm_size)
 175                 return FALSE;
 176
 177         return amd64_is_imm32 (val);
 178 }
 179
 180 static void
 181 amd64_patch (unsigned char* code, gpointer target)
 182 {
 183         guint8 rex = 0;
 184
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 187                 rex = code [0];
 188                 code += 1;
 189         }
 190
 191         if ((code [0] & 0xf8) == 0xb8) {
 192                 /* amd64_set_reg_template */
 193                 *(guint64*)(code + 1) = (guint64)target;
 194         }
 195         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 196                 /* mov 0(%rip), %dreg */
 197                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 198         }
 199         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 200                 /* call *<OFFSET>(%rip) */
 201                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 202         }
 203         else if (code [0] == 0xe8) {
 204                 /* call <DISP> */
 205                 gint64 disp = (guint8*)target - (guint8*)code;
 206                 g_assert (amd64_is_imm32 (disp));
 207                 x86_patch (code, (unsigned char*)target);
 208         }
 209         else
 210                 x86_patch (code, (unsigned char*)target);
 211 }
 212
 213 void
 214 mono_amd64_patch (unsigned char* code, gpointer target)
 215 {
 216         amd64_patch (code, target);
 217 }
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 static void inline
 222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 ainfo->arg_size = sizeof (mgreg_t);
 229                 /* Since the same stack slot size is used for all arg */
 230                 /*  types, it needs to be big enough to hold them all */
 231                 (*stack_size) += sizeof(mgreg_t);
 232     }
 233     else {
 234                 ainfo->storage = ArgInIReg;
 235                 ainfo->reg = param_regs [*gr];
 236                 (*gr) ++;
 237     }
 238 }
 239
 240 static void inline
 241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 242 {
 243     ainfo->offset = *stack_size;
 244
 245     if (*gr >= FLOAT_PARAM_REGS) {
 246                 ainfo->storage = ArgOnStack;
 247                 ainfo->arg_size = sizeof (mgreg_t);
 248                 /* Since the same stack slot size is used for both float */
 249                 /*  types, it needs to be big enough to hold them both */
 250                 (*stack_size) += sizeof(mgreg_t);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mini_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_I1:
 279         case MONO_TYPE_U1:
 280         case MONO_TYPE_I2:
 281         case MONO_TYPE_U2:
 282         case MONO_TYPE_I4:
 283         case MONO_TYPE_U4:
 284         case MONO_TYPE_I:
 285         case MONO_TYPE_U:
 286         case MONO_TYPE_OBJECT:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_I8:
 290         case MONO_TYPE_U8:
 291                 class2 = ARG_CLASS_INTEGER;
 292                 break;
 293         case MONO_TYPE_R4:
 294         case MONO_TYPE_R8:
 295 #ifdef TARGET_WIN32
 296                 class2 = ARG_CLASS_INTEGER;
 297 #else
 298                 class2 = ARG_CLASS_SSE;
 299 #endif
 300                 break;
 301
 302         case MONO_TYPE_TYPEDBYREF:
 303                 g_assert_not_reached ();
 304
 305         case MONO_TYPE_GENERICINST:
 306                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 307                         class2 = ARG_CLASS_INTEGER;
 308                         break;
 309                 }
 310                 /* fall through */
 311         case MONO_TYPE_VALUETYPE: {
 312                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 313                 int i;
 314
 315                 for (i = 0; i < info->num_fields; ++i) {
 316                         class2 = class1;
 317                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 318                 }
 319                 break;
 320         }
 321         default:
 322                 g_assert_not_reached ();
 323         }
 324
 325         /* Merge */
 326         if (class1 == class2)
 327                 ;
 328         else if (class1 == ARG_CLASS_NO_CLASS)
 329                 class1 = class2;
 330         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 331                 class1 = ARG_CLASS_MEMORY;
 332         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 333                 class1 = ARG_CLASS_INTEGER;
 334         else
 335                 class1 = ARG_CLASS_SSE;
 336
 337         return class1;
 338 }
 339
 340 typedef struct {
 341         MonoType *type;
 342         int size, offset;
 343 } StructFieldInfo;
 344
 345 /*
 346  * collect_field_info_nested:
 347  *
 348  *   Collect field info from KLASS recursively into FIELDS.
 349  */
 350 static void
 351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 352 {
 353         MonoMarshalType *info;
 354         int i;
 355
 356         if (pinvoke) {
 357                 info = mono_marshal_load_type_info (klass);
 358                 g_assert(info);
 359                 for (i = 0; i < info->num_fields; ++i) {
 360                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 361                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 362                         } else {
 363                                 guint32 align;
 364                                 StructFieldInfo f;
 365
 366                                 f.type = info->fields [i].field->type;
 367                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 368                                                                                                                            info->fields [i].mspec,
 369                                                                                                                            &align, TRUE, unicode);
 370                                 f.offset = offset + info->fields [i].offset;
 371                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 372                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 373                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 374                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 375                                                 g_array_append_val (fields_array, f);
 376                                                 while (f.size + f.offset < info->native_size) {
 377                                                         f.offset += f.size;
 378                                                         g_array_append_val (fields_array, f);
 379                                                 }
 380                                         } else {
 381                                                 f.size = info->native_size - f.offset;
 382                                                 g_array_append_val (fields_array, f);
 383                                         }
 384                                 } else {
 385                                         g_array_append_val (fields_array, f);
 386                                 }
 387                         }
 388                 }
 389         } else {
 390                 gpointer iter;
 391                 MonoClassField *field;
 392
 393                 iter = NULL;
 394                 while ((field = mono_class_get_fields (klass, &iter))) {
 395                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 396                                 continue;
 397                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 398                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 399                         } else {
 400                                 int align;
 401                                 StructFieldInfo f;
 402
 403                                 f.type = field->type;
 404                                 f.size = mono_type_size (field->type, &align);
 405                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 406
 407                                 g_array_append_val (fields_array, f);
 408                         }
 409                 }
 410         }
 411 }
 412
 413 #ifdef TARGET_WIN32
 414
 415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 417
 418 static gboolean
 419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 420 {
 421         gboolean result = FALSE;
 422
 423         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 424         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 425
 426         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 427         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 428         arg_info->pair_size [0] = 0;
 429         arg_info->pair_size [1] = 0;
 430         arg_info->nregs = 0;
 431
 432         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 433                 /* Pass parameter in integer register. */
 434                 arg_info->pair_storage [0] = ArgInIReg;
 435                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 436                 (*current_int_reg) ++;
 437                 result = TRUE;
 438         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 439                 /* Pass parameter in float register. */
 440                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 441                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 442                 (*current_float_reg) ++;
 443                 result = TRUE;
 444         }
 445
 446         if (result == TRUE) {
 447                 arg_info->pair_size [0] = arg_size;
 448                 arg_info->nregs = 1;
 449         }
 450
 451         return result;
 452 }
 453
 454 static inline gboolean
 455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 456 {
 457         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 458 }
 459
 460 static inline gboolean
 461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 462 {
 463         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 464 }
 465
 466 static void
 467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 468                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 469 {
 470         /* Windows x64 value type ABI.
 471         *
 472         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 473         *
 474         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 475         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 476         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 477         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 478         *
 479         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 480         *
 481         * Integers/Float types smaller than or equal to 8 bytes
 482         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 483         * Properly sized struct/unions (1,2,4,8)
 484         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 485         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 486         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 487         */
 488
 489         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 490
 491         if (!is_return) {
 492
 493                 /* Parameter cases. */
 494                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 495                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 496
 497                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 498                         arg_info->storage = ArgValuetypeInReg;
 499                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 500                                 /* No more registers, fallback passing parameter on stack as value. */
 501                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 502
 503                                 /* Passing value directly on stack, so use size of value. */
 504                                 arg_info->storage = ArgOnStack;
 505                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 506                                 arg_info->offset = *stack_size;
 507                                 arg_info->arg_size = arg_size;
 508                                 *stack_size += arg_size;
 509                         }
 510                 } else {
 511                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 512                         arg_info->storage = ArgValuetypeAddrInIReg;
 513                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 514                                 /* No more registers, fallback passing address to parameter on stack. */
 515                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 516
 517                                 /* Passing an address to value on stack, so use size of register as argument size. */
 518                                 arg_info->storage = ArgValuetypeAddrOnStack;
 519                                 arg_size = sizeof (mgreg_t);
 520                                 arg_info->offset = *stack_size;
 521                                 arg_info->arg_size = arg_size;
 522                                 *stack_size += arg_size;
 523                         }
 524                 }
 525         } else {
 526                 /* Return value cases. */
 527                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 528                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 529
 530                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 531                         arg_info->storage = ArgValuetypeInReg;
 532                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 533
 534                         /* Only RAX/XMM0 should be used to return valuetype. */
 535                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 536                 } else {
 537                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 538                         arg_info->storage = ArgValuetypeAddrInIReg;
 539                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 540
 541                         /* Only RAX should be used to return valuetype address. */
 542                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 543
 544                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 545                         arg_info->offset = *stack_size;
 546                         *stack_size += arg_size;
 547                 }
 548         }
 549 }
 550
 551 static void
 552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 553 {
 554         *arg_size = 0;
 555         *arg_class = ARG_CLASS_NO_CLASS;
 556
 557         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 558
 559         if (pinvoke) {
 560                 /* Calculate argument class type and size of marshalled type. */
 561                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 562                 *arg_size = info->native_size;
 563         } else {
 564                 /* Calculate argument class type and size of managed type. */
 565                 *arg_size = mono_class_value_size (klass, NULL);
 566         }
 567
 568         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 569         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 570
 571         if (*arg_class == ARG_CLASS_MEMORY) {
 572                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 573                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 574         }
 575
 576         /*
 577         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 578         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 579         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 580         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 581         * it must be represented in call and cannot be dropped.
 582         */
 583         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 584                 arg_info->pass_empty_struct = TRUE;
 585                 *arg_size = SIZEOF_REGISTER;
 586                 *arg_class = ARG_CLASS_INTEGER;
 587         }
 588
 589         assert (*arg_class != ARG_CLASS_NO_CLASS);
 590 }
 591
 592 static void
 593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 594                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 595 {
 596         guint32 arg_size = SIZEOF_REGISTER;
 597         MonoClass *klass = NULL;
 598         ArgumentClass arg_class;
 599
 600         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 601
 602         klass = mono_class_from_mono_type (type);
 603         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 604
 605         /* Only drop value type if its not an empty struct as input that must be represented in call */
 606         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 607                 arg_info->storage = ArgValuetypeInReg;
 608                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 609         } else {
 610                 /* Alocate storage for value type. */
 611                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 612         }
 613 }
 614
 615 #endif /* TARGET_WIN32 */
 616
 617 static void
 618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 619                            gboolean is_return,
 620                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 621 {
 622 #ifdef TARGET_WIN32
 623         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 624 #else
 625         guint32 size, quad, nquads, i, nfields;
 626         /* Keep track of the size used in each quad so we can */
 627         /* use the right size when copying args/return vars.  */
 628         guint32 quadsize [2] = {8, 8};
 629         ArgumentClass args [2];
 630         StructFieldInfo *fields = NULL;
 631         GArray *fields_array;
 632         MonoClass *klass;
 633         gboolean pass_on_stack = FALSE;
 634         int struct_size;
 635
 636         klass = mono_class_from_mono_type (type);
 637         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 638
 639         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 640                 /* We pass and return vtypes of size 8 in a register */
 641         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 642                 pass_on_stack = TRUE;
 643         }
 644
 645         /* If this struct can't be split up naturally into 8-byte */
 646         /* chunks (registers), pass it on the stack.              */
 647         if (sig->pinvoke) {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 649                 g_assert (info);
 650                 struct_size = info->native_size;
 651         } else {
 652                 struct_size = mono_class_value_size (klass, NULL);
 653         }
 654         /*
 655          * Collect field information recursively to be able to
 656          * handle nested structures.
 657          */
 658         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 659         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 660         fields = (StructFieldInfo*)fields_array->data;
 661         nfields = fields_array->len;
 662
 663         for (i = 0; i < nfields; ++i) {
 664                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 665                         pass_on_stack = TRUE;
 666                         break;
 667                 }
 668         }
 669
 670         if (size == 0) {
 671                 ainfo->storage = ArgValuetypeInReg;
 672                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 673                 return;
 674         }
 675
 676         if (pass_on_stack) {
 677                 /* Allways pass in memory */
 678                 ainfo->offset = *stack_size;
 679                 *stack_size += ALIGN_TO (size, 8);
 680                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 681                 if (!is_return)
 682                         ainfo->arg_size = ALIGN_TO (size, 8);
 683
 684                 g_array_free (fields_array, TRUE);
 685                 return;
 686         }
 687
 688         if (size > 8)
 689                 nquads = 2;
 690         else
 691                 nquads = 1;
 692
 693         if (!sig->pinvoke) {
 694                 int n = mono_class_value_size (klass, NULL);
 695
 696                 quadsize [0] = n >= 8 ? 8 : n;
 697                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 698
 699                 /* Always pass in 1 or 2 integer registers */
 700                 args [0] = ARG_CLASS_INTEGER;
 701                 args [1] = ARG_CLASS_INTEGER;
 702                 /* Only the simplest cases are supported */
 703                 if (is_return && nquads != 1) {
 704                         args [0] = ARG_CLASS_MEMORY;
 705                         args [1] = ARG_CLASS_MEMORY;
 706                 }
 707         } else {
 708                 /*
 709                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 710                  * The X87 and SSEUP stuff is left out since there are no such types in
 711                  * the CLR.
 712                  */
 713                 if (!nfields) {
 714                         ainfo->storage = ArgValuetypeInReg;
 715                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 716                         return;
 717                 }
 718
 719                 if (struct_size > 16) {
 720                         ainfo->offset = *stack_size;
 721                         *stack_size += ALIGN_TO (struct_size, 8);
 722                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 723                         if (!is_return)
 724                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 725
 726                         g_array_free (fields_array, TRUE);
 727                         return;
 728                 }
 729
 730                 args [0] = ARG_CLASS_NO_CLASS;
 731                 args [1] = ARG_CLASS_NO_CLASS;
 732                 for (quad = 0; quad < nquads; ++quad) {
 733                         ArgumentClass class1;
 734
 735                         if (nfields == 0)
 736                                 class1 = ARG_CLASS_MEMORY;
 737                         else
 738                                 class1 = ARG_CLASS_NO_CLASS;
 739                         for (i = 0; i < nfields; ++i) {
 740                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 741                                         /* Unaligned field */
 742                                         NOT_IMPLEMENTED;
 743                                 }
 744
 745                                 /* Skip fields in other quad */
 746                                 if ((quad == 0) && (fields [i].offset >= 8))
 747                                         continue;
 748                                 if ((quad == 1) && (fields [i].offset < 8))
 749                                         continue;
 750
 751                                 /* How far into this quad this data extends.*/
 752                                 /* (8 is size of quad) */
 753                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 754
 755                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 756                         }
 757                         /* Empty structs have a nonzero size, causing this assert to be hit */
 758                         if (sig->pinvoke)
 759                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 760                         args [quad] = class1;
 761                 }
 762         }
 763
 764         g_array_free (fields_array, TRUE);
 765
 766         /* Post merger cleanup */
 767         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 768                 args [0] = args [1] = ARG_CLASS_MEMORY;
 769
 770         /* Allocate registers */
 771         {
 772                 int orig_gr = *gr;
 773                 int orig_fr = *fr;
 774
 775                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 776                         quadsize [0] ++;
 777                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 778                         quadsize [1] ++;
 779
 780                 ainfo->storage = ArgValuetypeInReg;
 781                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 782                 g_assert (quadsize [0] <= 8);
 783                 g_assert (quadsize [1] <= 8);
 784                 ainfo->pair_size [0] = quadsize [0];
 785                 ainfo->pair_size [1] = quadsize [1];
 786                 ainfo->nregs = nquads;
 787                 for (quad = 0; quad < nquads; ++quad) {
 788                         switch (args [quad]) {
 789                         case ARG_CLASS_INTEGER:
 790                                 if (*gr >= PARAM_REGS)
 791                                         args [quad] = ARG_CLASS_MEMORY;
 792                                 else {
 793                                         ainfo->pair_storage [quad] = ArgInIReg;
 794                                         if (is_return)
 795                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 796                                         else
 797                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 798                                         (*gr) ++;
 799                                 }
 800                                 break;
 801                         case ARG_CLASS_SSE:
 802                                 if (*fr >= FLOAT_PARAM_REGS)
 803                                         args [quad] = ARG_CLASS_MEMORY;
 804                                 else {
 805                                         if (quadsize[quad] <= 4)
 806                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 807                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 808                                         ainfo->pair_regs [quad] = *fr;
 809                                         (*fr) ++;
 810                                 }
 811                                 break;
 812                         case ARG_CLASS_MEMORY:
 813                                 break;
 814                         case ARG_CLASS_NO_CLASS:
 815                                 break;
 816                         default:
 817                                 g_assert_not_reached ();
 818                         }
 819                 }
 820
 821                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 822                         int arg_size;
 823                         /* Revert possible register assignments */
 824                         *gr = orig_gr;
 825                         *fr = orig_fr;
 826
 827                         ainfo->offset = *stack_size;
 828                         if (sig->pinvoke)
 829                                 arg_size = ALIGN_TO (struct_size, 8);
 830                         else
 831                                 arg_size = nquads * sizeof(mgreg_t);
 832                         *stack_size += arg_size;
 833                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 834                         if (!is_return)
 835                                 ainfo->arg_size = arg_size;
 836                 }
 837         }
 838 #endif /* !TARGET_WIN32 */
 839 }
 840
 841 /*
 842  * get_call_info:
 843  *
 844  * Obtain information about a call according to the calling convention.
 845  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 846  * Draft Version 0.23" document for more information.
 847  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 848  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 849  */
 850 static CallInfo*
 851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 852 {
 853         guint32 i, gr, fr, pstart;
 854         MonoType *ret_type;
 855         int n = sig->hasthis + sig->param_count;
 856         guint32 stack_size = 0;
 857         CallInfo *cinfo;
 858         gboolean is_pinvoke = sig->pinvoke;
 859
 860         if (mp)
 861                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 862         else
 863                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864
 865         cinfo->nargs = n;
 866         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 867
 868         gr = 0;
 869         fr = 0;
 870
 871 #ifdef TARGET_WIN32
 872         /* Reserve space where the callee can save the argument registers */
 873         stack_size = 4 * sizeof (mgreg_t);
 874 #endif
 875
 876         /* return value */
 877         ret_type = mini_get_underlying_type (sig->ret);
 878         switch (ret_type->type) {
 879         case MONO_TYPE_I1:
 880         case MONO_TYPE_U1:
 881         case MONO_TYPE_I2:
 882         case MONO_TYPE_U2:
 883         case MONO_TYPE_I4:
 884         case MONO_TYPE_U4:
 885         case MONO_TYPE_I:
 886         case MONO_TYPE_U:
 887         case MONO_TYPE_PTR:
 888         case MONO_TYPE_FNPTR:
 889         case MONO_TYPE_OBJECT:
 890                 cinfo->ret.storage = ArgInIReg;
 891                 cinfo->ret.reg = AMD64_RAX;
 892                 break;
 893         case MONO_TYPE_U8:
 894         case MONO_TYPE_I8:
 895                 cinfo->ret.storage = ArgInIReg;
 896                 cinfo->ret.reg = AMD64_RAX;
 897                 break;
 898         case MONO_TYPE_R4:
 899                 cinfo->ret.storage = ArgInFloatSSEReg;
 900                 cinfo->ret.reg = AMD64_XMM0;
 901                 break;
 902         case MONO_TYPE_R8:
 903                 cinfo->ret.storage = ArgInDoubleSSEReg;
 904                 cinfo->ret.reg = AMD64_XMM0;
 905                 break;
 906         case MONO_TYPE_GENERICINST:
 907                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 908                         cinfo->ret.storage = ArgInIReg;
 909                         cinfo->ret.reg = AMD64_RAX;
 910                         break;
 911                 }
 912                 if (mini_is_gsharedvt_type (ret_type)) {
 913                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 914                         break;
 915                 }
 916                 /* fall through */
 917         case MONO_TYPE_VALUETYPE:
 918         case MONO_TYPE_TYPEDBYREF: {
 919                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 920
 921                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 922                 g_assert (cinfo->ret.storage != ArgInIReg);
 923                 break;
 924         }
 925         case MONO_TYPE_VAR:
 926         case MONO_TYPE_MVAR:
 927                 g_assert (mini_is_gsharedvt_type (ret_type));
 928                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 929                 break;
 930         case MONO_TYPE_VOID:
 931                 break;
 932         default:
 933                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 934         }
 935
 936         pstart = 0;
 937         /*
 938          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 939          * the first argument, allowing 'this' to be always passed in the first arg reg.
 940          * Also do this if the first argument is a reference type, since virtual calls
 941          * are sometimes made using calli without sig->hasthis set, like in the delegate
 942          * invoke wrappers.
 943          */
 944         ArgStorage ret_storage = cinfo->ret.storage;
 945         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 946                 if (sig->hasthis) {
 947                         add_general (&gr, &stack_size, cinfo->args + 0);
 948                 } else {
 949                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 950                         pstart = 1;
 951                 }
 952                 add_general (&gr, &stack_size, &cinfo->ret);
 953                 cinfo->ret.storage = ret_storage;
 954                 cinfo->vret_arg_index = 1;
 955         } else {
 956                 /* this */
 957                 if (sig->hasthis)
 958                         add_general (&gr, &stack_size, cinfo->args + 0);
 959
 960                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 961                         add_general (&gr, &stack_size, &cinfo->ret);
 962                         cinfo->ret.storage = ret_storage;
 963                 }
 964         }
 965
 966         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 967                 gr = PARAM_REGS;
 968                 fr = FLOAT_PARAM_REGS;
 969
 970                 /* Emit the signature cookie just before the implicit arguments */
 971                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 972         }
 973
 974         for (i = pstart; i < sig->param_count; ++i) {
 975                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 976                 MonoType *ptype;
 977
 978 #ifdef TARGET_WIN32
 979                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 980                 if (gr > fr)
 981                         fr = gr;
 982                 else if (fr > gr)
 983                         gr = fr;
 984 #endif
 985
 986                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 987                         /* We allways pass the sig cookie on the stack for simplicity */
 988                         /*
 989                          * Prevent implicit arguments + the sig cookie from being passed
 990                          * in registers.
 991                          */
 992                         gr = PARAM_REGS;
 993                         fr = FLOAT_PARAM_REGS;
 994
 995                         /* Emit the signature cookie just before the implicit arguments */
 996                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 997                 }
 998
 999                 ptype = mini_get_underlying_type (sig->params [i]);
1000                 switch (ptype->type) {
1001                 case MONO_TYPE_I1:
1002                 case MONO_TYPE_U1:
1003                         add_general (&gr, &stack_size, ainfo);
1004                         ainfo->byte_arg_size = 1;
1005                         break;
1006                 case MONO_TYPE_I2:
1007                 case MONO_TYPE_U2:
1008                         add_general (&gr, &stack_size, ainfo);
1009                         ainfo->byte_arg_size = 2;
1010                         break;
1011                 case MONO_TYPE_I4:
1012                 case MONO_TYPE_U4:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         ainfo->byte_arg_size = 4;
1015                         break;
1016                 case MONO_TYPE_I:
1017                 case MONO_TYPE_U:
1018                 case MONO_TYPE_PTR:
1019                 case MONO_TYPE_FNPTR:
1020                 case MONO_TYPE_OBJECT:
1021                         add_general (&gr, &stack_size, ainfo);
1022                         break;
1023                 case MONO_TYPE_GENERICINST:
1024                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1025                                 add_general (&gr, &stack_size, ainfo);
1026                                 break;
1027                         }
1028                         if (mini_is_gsharedvt_variable_type (ptype)) {
1029                                 /* gsharedvt arguments are passed by ref */
1030                                 add_general (&gr, &stack_size, ainfo);
1031                                 if (ainfo->storage == ArgInIReg)
1032                                         ainfo->storage = ArgGSharedVtInReg;
1033                                 else
1034                                         ainfo->storage = ArgGSharedVtOnStack;
1035                                 break;
1036                         }
1037                         /* fall through */
1038                 case MONO_TYPE_VALUETYPE:
1039                 case MONO_TYPE_TYPEDBYREF:
1040                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1041                         break;
1042                 case MONO_TYPE_U8:
1043
1044                 case MONO_TYPE_I8:
1045                         add_general (&gr, &stack_size, ainfo);
1046                         break;
1047                 case MONO_TYPE_R4:
1048                         add_float (&fr, &stack_size, ainfo, FALSE);
1049                         break;
1050                 case MONO_TYPE_R8:
1051                         add_float (&fr, &stack_size, ainfo, TRUE);
1052                         break;
1053                 case MONO_TYPE_VAR:
1054                 case MONO_TYPE_MVAR:
1055                         /* gsharedvt arguments are passed by ref */
1056                         g_assert (mini_is_gsharedvt_type (ptype));
1057                         add_general (&gr, &stack_size, ainfo);
1058                         if (ainfo->storage == ArgInIReg)
1059                                 ainfo->storage = ArgGSharedVtInReg;
1060                         else
1061                                 ainfo->storage = ArgGSharedVtOnStack;
1062                         break;
1063                 default:
1064                         g_assert_not_reached ();
1065                 }
1066         }
1067
1068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1069                 gr = PARAM_REGS;
1070                 fr = FLOAT_PARAM_REGS;
1071
1072                 /* Emit the signature cookie just before the implicit arguments */
1073                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1074         }
1075
1076         cinfo->stack_usage = stack_size;
1077         cinfo->reg_usage = gr;
1078         cinfo->freg_usage = fr;
1079         return cinfo;
1080 }
1081
1082 /*
1083  * mono_arch_get_argument_info:
1084  * @csig:  a method signature
1085  * @param_count: the number of parameters to consider
1086  * @arg_info: an array to store the result infos
1087  *
1088  * Gathers information on parameters such as size, alignment and
1089  * padding. arg_info should be large enought to hold param_count + 1 entries.
1090  *
1091  * Returns the size of the argument area on the stack.
1092  */
1093 int
1094 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1095 {
1096         int k;
1097         CallInfo *cinfo = get_call_info (NULL, csig);
1098         guint32 args_size = cinfo->stack_usage;
1099
1100         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1101         if (csig->hasthis) {
1102                 arg_info [0].offset = 0;
1103         }
1104
1105         for (k = 0; k < param_count; k++) {
1106                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1107                 /* FIXME: */
1108                 arg_info [k + 1].size = 0;
1109         }
1110
1111         g_free (cinfo);
1112
1113         return args_size;
1114 }
1115
1116 gboolean
1117 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1118 {
1119         CallInfo *c1, *c2;
1120         gboolean res;
1121         MonoType *callee_ret;
1122
1123         c1 = get_call_info (NULL, caller_sig);
1124         c2 = get_call_info (NULL, callee_sig);
1125         res = c1->stack_usage >= c2->stack_usage;
1126         callee_ret = mini_get_underlying_type (callee_sig->ret);
1127         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1128                 /* An address on the callee's stack is passed as the first argument */
1129                 res = FALSE;
1130
1131         g_free (c1);
1132         g_free (c2);
1133
1134         return res;
1135 }
1136
1137 /*
1138  * Initialize the cpu to execute managed code.
1139  */
1140 void
1141 mono_arch_cpu_init (void)
1142 {
1143 #ifndef _MSC_VER
1144         guint16 fpcw;
1145
1146         /* spec compliance requires running with double precision */
1147         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1148         fpcw &= ~X86_FPCW_PRECC_MASK;
1149         fpcw |= X86_FPCW_PREC_DOUBLE;
1150         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1151         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1152 #else
1153         /* TODO: This is crashing on Win64 right now.
1154         * _control87 (_PC_53, MCW_PC);
1155         */
1156 #endif
1157 }
1158
1159 /*
1160  * Initialize architecture specific code.
1161  */
1162 void
1163 mono_arch_init (void)
1164 {
1165         mono_os_mutex_init_recursive (&mini_arch_mutex);
1166
1167         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1168         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1169         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1170         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1171         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1172
1173 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1174         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1175 #endif
1176
1177         if (!mono_aot_only)
1178                 bp_trampoline = mini_get_breakpoint_trampoline ();
1179 }
1180
1181 /*
1182  * Cleanup architecture specific code.
1183  */
1184 void
1185 mono_arch_cleanup (void)
1186 {
1187         mono_os_mutex_destroy (&mini_arch_mutex);
1188 }
1189
1190 /*
1191  * This function returns the optimizations supported on this cpu.
1192  */
1193 guint32
1194 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1195 {
1196         guint32 opts = 0;
1197
1198         *exclude_mask = 0;
1199
1200         if (mono_hwcap_x86_has_cmov) {
1201                 opts |= MONO_OPT_CMOV;
1202
1203                 if (mono_hwcap_x86_has_fcmov)
1204                         opts |= MONO_OPT_FCMOV;
1205                 else
1206                         *exclude_mask |= MONO_OPT_FCMOV;
1207         } else {
1208                 *exclude_mask |= MONO_OPT_CMOV;
1209         }
1210
1211 #ifdef TARGET_WIN32
1212         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1213         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1214         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1215         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1216         /* will now have a reference to an argument that won't be fully decomposed. */
1217         *exclude_mask |= MONO_OPT_SIMD;
1218 #endif
1219
1220         return opts;
1221 }
1222
1223 /*
1224  * This function test for all SSE functions supported.
1225  *
1226  * Returns a bitmask corresponding to all supported versions.
1227  *
1228  */
1229 guint32
1230 mono_arch_cpu_enumerate_simd_versions (void)
1231 {
1232         guint32 sse_opts = 0;
1233
1234         if (mono_hwcap_x86_has_sse1)
1235                 sse_opts |= SIMD_VERSION_SSE1;
1236
1237         if (mono_hwcap_x86_has_sse2)
1238                 sse_opts |= SIMD_VERSION_SSE2;
1239
1240         if (mono_hwcap_x86_has_sse3)
1241                 sse_opts |= SIMD_VERSION_SSE3;
1242
1243         if (mono_hwcap_x86_has_ssse3)
1244                 sse_opts |= SIMD_VERSION_SSSE3;
1245
1246         if (mono_hwcap_x86_has_sse41)
1247                 sse_opts |= SIMD_VERSION_SSE41;
1248
1249         if (mono_hwcap_x86_has_sse42)
1250                 sse_opts |= SIMD_VERSION_SSE42;
1251
1252         if (mono_hwcap_x86_has_sse4a)
1253                 sse_opts |= SIMD_VERSION_SSE4a;
1254
1255         return sse_opts;
1256 }
1257
1258 #ifndef DISABLE_JIT
1259
1260 GList *
1261 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1262 {
1263         GList *vars = NULL;
1264         int i;
1265
1266         for (i = 0; i < cfg->num_varinfo; i++) {
1267                 MonoInst *ins = cfg->varinfo [i];
1268                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1269
1270                 /* unused vars */
1271                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1272                         continue;
1273
1274                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1275                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1276                         continue;
1277
1278                 if (mono_is_regsize_var (ins->inst_vtype)) {
1279                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1280                         g_assert (i == vmv->idx);
1281                         vars = g_list_prepend (vars, vmv);
1282                 }
1283         }
1284
1285         vars = mono_varlist_sort (cfg, vars, 0);
1286
1287         return vars;
1288 }
1289
1290 /**
1291  * mono_arch_compute_omit_fp:
1292  * Determine whether the frame pointer can be eliminated.
1293  */
1294 static void
1295 mono_arch_compute_omit_fp (MonoCompile *cfg)
1296 {
1297         MonoMethodSignature *sig;
1298         MonoMethodHeader *header;
1299         int i, locals_size;
1300         CallInfo *cinfo;
1301
1302         if (cfg->arch.omit_fp_computed)
1303                 return;
1304
1305         header = cfg->header;
1306
1307         sig = mono_method_signature (cfg->method);
1308
1309         if (!cfg->arch.cinfo)
1310                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1311         cinfo = (CallInfo *)cfg->arch.cinfo;
1312
1313         /*
1314          * FIXME: Remove some of the restrictions.
1315          */
1316         cfg->arch.omit_fp = TRUE;
1317         cfg->arch.omit_fp_computed = TRUE;
1318
1319         if (cfg->disable_omit_fp)
1320                 cfg->arch.omit_fp = FALSE;
1321
1322         if (!debug_omit_fp ())
1323                 cfg->arch.omit_fp = FALSE;
1324         /*
1325         if (cfg->method->save_lmf)
1326                 cfg->arch.omit_fp = FALSE;
1327         */
1328         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1329                 cfg->arch.omit_fp = FALSE;
1330         if (header->num_clauses)
1331                 cfg->arch.omit_fp = FALSE;
1332         if (cfg->param_area)
1333                 cfg->arch.omit_fp = FALSE;
1334         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1335                 cfg->arch.omit_fp = FALSE;
1336         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1337                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1338                 cfg->arch.omit_fp = FALSE;
1339         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1340                 ArgInfo *ainfo = &cinfo->args [i];
1341
1342                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1343                         /*
1344                          * The stack offset can only be determined when the frame
1345                          * size is known.
1346                          */
1347                         cfg->arch.omit_fp = FALSE;
1348                 }
1349         }
1350
1351         locals_size = 0;
1352         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1353                 MonoInst *ins = cfg->varinfo [i];
1354                 int ialign;
1355
1356                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1357         }
1358 }
1359
1360 GList *
1361 mono_arch_get_global_int_regs (MonoCompile *cfg)
1362 {
1363         GList *regs = NULL;
1364
1365         mono_arch_compute_omit_fp (cfg);
1366
1367         if (cfg->arch.omit_fp)
1368                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1369
1370         /* We use the callee saved registers for global allocation */
1371         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1373         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1374         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1375         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1376 #ifdef TARGET_WIN32
1377         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1378         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1379 #endif
1380
1381         return regs;
1382 }
1383
1384 GList*
1385 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1386 {
1387         GList *regs = NULL;
1388         int i;
1389
1390         /* All XMM registers */
1391         for (i = 0; i < 16; ++i)
1392                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1393
1394         return regs;
1395 }
1396
1397 GList*
1398 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1399 {
1400         static GList *r = NULL;
1401
1402         if (r == NULL) {
1403                 GList *regs = NULL;
1404
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1408                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1409                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1410                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1411
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1419                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1420
1421                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1422         }
1423
1424         return r;
1425 }
1426
1427 GList*
1428 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1429 {
1430         int i;
1431         static GList *r = NULL;
1432
1433         if (r == NULL) {
1434                 GList *regs = NULL;
1435
1436                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1437                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1438
1439                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1440         }
1441
1442         return r;
1443 }
1444
1445 /*
1446  * mono_arch_regalloc_cost:
1447  *
1448  *  Return the cost, in number of memory references, of the action of
1449  * allocating the variable VMV into a register during global register
1450  * allocation.
1451  */
1452 guint32
1453 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1454 {
1455         MonoInst *ins = cfg->varinfo [vmv->idx];
1456
1457         if (cfg->method->save_lmf)
1458                 /* The register is already saved */
1459                 /* substract 1 for the invisible store in the prolog */
1460                 return (ins->opcode == OP_ARG) ? 0 : 1;
1461         else
1462                 /* push+pop */
1463                 return (ins->opcode == OP_ARG) ? 1 : 2;
1464 }
1465
1466 /*
1467  * mono_arch_fill_argument_info:
1468  *
1469  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1470  * of the method.
1471  */
1472 void
1473 mono_arch_fill_argument_info (MonoCompile *cfg)
1474 {
1475         MonoType *sig_ret;
1476         MonoMethodSignature *sig;
1477         MonoInst *ins;
1478         int i;
1479         CallInfo *cinfo;
1480
1481         sig = mono_method_signature (cfg->method);
1482
1483         cinfo = (CallInfo *)cfg->arch.cinfo;
1484         sig_ret = mini_get_underlying_type (sig->ret);
1485
1486         /*
1487          * Contrary to mono_arch_allocate_vars (), the information should describe
1488          * where the arguments are at the beginning of the method, not where they can be
1489          * accessed during the execution of the method. The later makes no sense for the
1490          * global register allocator, since a variable can be in more than one location.
1491          */
1492         switch (cinfo->ret.storage) {
1493         case ArgInIReg:
1494         case ArgInFloatSSEReg:
1495         case ArgInDoubleSSEReg:
1496                 cfg->ret->opcode = OP_REGVAR;
1497                 cfg->ret->inst_c0 = cinfo->ret.reg;
1498                 break;
1499         case ArgValuetypeInReg:
1500                 cfg->ret->opcode = OP_REGOFFSET;
1501                 cfg->ret->inst_basereg = -1;
1502                 cfg->ret->inst_offset = -1;
1503                 break;
1504         case ArgNone:
1505                 break;
1506         default:
1507                 g_assert_not_reached ();
1508         }
1509
1510         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1511                 ArgInfo *ainfo = &cinfo->args [i];
1512
1513                 ins = cfg->args [i];
1514
1515                 switch (ainfo->storage) {
1516                 case ArgInIReg:
1517                 case ArgInFloatSSEReg:
1518                 case ArgInDoubleSSEReg:
1519                         ins->opcode = OP_REGVAR;
1520                         ins->inst_c0 = ainfo->reg;
1521                         break;
1522                 case ArgOnStack:
1523                         ins->opcode = OP_REGOFFSET;
1524                         ins->inst_basereg = -1;
1525                         ins->inst_offset = -1;
1526                         break;
1527                 case ArgValuetypeInReg:
1528                         /* Dummy */
1529                         ins->opcode = OP_NOP;
1530                         break;
1531                 default:
1532                         g_assert_not_reached ();
1533                 }
1534         }
1535 }
1536
1537 void
1538 mono_arch_allocate_vars (MonoCompile *cfg)
1539 {
1540         MonoType *sig_ret;
1541         MonoMethodSignature *sig;
1542         MonoInst *ins;
1543         int i, offset;
1544         guint32 locals_stack_size, locals_stack_align;
1545         gint32 *offsets;
1546         CallInfo *cinfo;
1547
1548         sig = mono_method_signature (cfg->method);
1549
1550         cinfo = (CallInfo *)cfg->arch.cinfo;
1551         sig_ret = mini_get_underlying_type (sig->ret);
1552
1553         mono_arch_compute_omit_fp (cfg);
1554
1555         /*
1556          * We use the ABI calling conventions for managed code as well.
1557          * Exception: valuetypes are only sometimes passed or returned in registers.
1558          */
1559
1560         /*
1561          * The stack looks like this:
1562          * <incoming arguments passed on the stack>
1563          * <return value>
1564          * <lmf/caller saved registers>
1565          * <locals>
1566          * <spill area>
1567          * <localloc area>  -> grows dynamically
1568          * <params area>
1569          */
1570
1571         if (cfg->arch.omit_fp) {
1572                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1573                 cfg->frame_reg = AMD64_RSP;
1574                 offset = 0;
1575         } else {
1576                 /* Locals are allocated backwards from %fp */
1577                 cfg->frame_reg = AMD64_RBP;
1578                 offset = 0;
1579         }
1580
1581         cfg->arch.saved_iregs = cfg->used_int_regs;
1582         if (cfg->method->save_lmf) {
1583                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1584                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1585                 cfg->arch.saved_iregs |= iregs_to_save;
1586         }
1587
1588         if (cfg->arch.omit_fp)
1589                 cfg->arch.reg_save_area_offset = offset;
1590         /* Reserve space for callee saved registers */
1591         for (i = 0; i < AMD64_NREG; ++i)
1592                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1593                         offset += sizeof(mgreg_t);
1594                 }
1595         if (!cfg->arch.omit_fp)
1596                 cfg->arch.reg_save_area_offset = -offset;
1597
1598         if (sig_ret->type != MONO_TYPE_VOID) {
1599                 switch (cinfo->ret.storage) {
1600                 case ArgInIReg:
1601                 case ArgInFloatSSEReg:
1602                 case ArgInDoubleSSEReg:
1603                         cfg->ret->opcode = OP_REGVAR;
1604                         cfg->ret->inst_c0 = cinfo->ret.reg;
1605                         cfg->ret->dreg = cinfo->ret.reg;
1606                         break;
1607                 case ArgValuetypeAddrInIReg:
1608                 case ArgGsharedvtVariableInReg:
1609                         /* The register is volatile */
1610                         cfg->vret_addr->opcode = OP_REGOFFSET;
1611                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1612                         if (cfg->arch.omit_fp) {
1613                                 cfg->vret_addr->inst_offset = offset;
1614                                 offset += 8;
1615                         } else {
1616                                 offset += 8;
1617                                 cfg->vret_addr->inst_offset = -offset;
1618                         }
1619                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1620                                 printf ("vret_addr =");
1621                                 mono_print_ins (cfg->vret_addr);
1622                         }
1623                         break;
1624                 case ArgValuetypeInReg:
1625                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1626                         cfg->ret->opcode = OP_REGOFFSET;
1627                         cfg->ret->inst_basereg = cfg->frame_reg;
1628                         if (cfg->arch.omit_fp) {
1629                                 cfg->ret->inst_offset = offset;
1630                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1631                         } else {
1632                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1633                                 cfg->ret->inst_offset = - offset;
1634                         }
1635                         break;
1636                 default:
1637                         g_assert_not_reached ();
1638                 }
1639         }
1640
1641         /* Allocate locals */
1642         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1643         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1644                 char *mname = mono_method_full_name (cfg->method, TRUE);
1645                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1646                 g_free (mname);
1647                 return;
1648         }
1649
1650         if (locals_stack_align) {
1651                 offset += (locals_stack_align - 1);
1652                 offset &= ~(locals_stack_align - 1);
1653         }
1654         if (cfg->arch.omit_fp) {
1655                 cfg->locals_min_stack_offset = offset;
1656                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1657         } else {
1658                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1659                 cfg->locals_max_stack_offset = - offset;
1660         }
1661
1662         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1663                 if (offsets [i] != -1) {
1664                         MonoInst *ins = cfg->varinfo [i];
1665                         ins->opcode = OP_REGOFFSET;
1666                         ins->inst_basereg = cfg->frame_reg;
1667                         if (cfg->arch.omit_fp)
1668                                 ins->inst_offset = (offset + offsets [i]);
1669                         else
1670                                 ins->inst_offset = - (offset + offsets [i]);
1671                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1672                 }
1673         }
1674         offset += locals_stack_size;
1675
1676         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1677                 g_assert (!cfg->arch.omit_fp);
1678                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1679                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1680         }
1681
1682         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1683                 ins = cfg->args [i];
1684                 if (ins->opcode != OP_REGVAR) {
1685                         ArgInfo *ainfo = &cinfo->args [i];
1686                         gboolean inreg = TRUE;
1687
1688                         /* FIXME: Allocate volatile arguments to registers */
1689                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1690                                 inreg = FALSE;
1691
1692                         /*
1693                          * Under AMD64, all registers used to pass arguments to functions
1694                          * are volatile across calls.
1695                          * FIXME: Optimize this.
1696                          */
1697                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1698                                 inreg = FALSE;
1699
1700                         ins->opcode = OP_REGOFFSET;
1701
1702                         switch (ainfo->storage) {
1703                         case ArgInIReg:
1704                         case ArgInFloatSSEReg:
1705                         case ArgInDoubleSSEReg:
1706                         case ArgGSharedVtInReg:
1707                                 if (inreg) {
1708                                         ins->opcode = OP_REGVAR;
1709                                         ins->dreg = ainfo->reg;
1710                                 }
1711                                 break;
1712                         case ArgOnStack:
1713                         case ArgGSharedVtOnStack:
1714                                 g_assert (!cfg->arch.omit_fp);
1715                                 ins->opcode = OP_REGOFFSET;
1716                                 ins->inst_basereg = cfg->frame_reg;
1717                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1718                                 break;
1719                         case ArgValuetypeInReg:
1720                                 break;
1721                         case ArgValuetypeAddrInIReg:
1722                         case ArgValuetypeAddrOnStack: {
1723                                 MonoInst *indir;
1724                                 g_assert (!cfg->arch.omit_fp);
1725                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1726                                 MONO_INST_NEW (cfg, indir, 0);
1727
1728                                 indir->opcode = OP_REGOFFSET;
1729                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1730                                         indir->inst_basereg = cfg->frame_reg;
1731                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1732                                         offset += (sizeof (gpointer));
1733                                         indir->inst_offset = - offset;
1734                                 }
1735                                 else {
1736                                         indir->inst_basereg = cfg->frame_reg;
1737                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1738                                 }
1739
1740                                 ins->opcode = OP_VTARG_ADDR;
1741                                 ins->inst_left = indir;
1742
1743                                 break;
1744                         }
1745                         default:
1746                                 NOT_IMPLEMENTED;
1747                         }
1748
1749                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1750                                 ins->opcode = OP_REGOFFSET;
1751                                 ins->inst_basereg = cfg->frame_reg;
1752                                 /* These arguments are saved to the stack in the prolog */
1753                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1754                                 if (cfg->arch.omit_fp) {
1755                                         ins->inst_offset = offset;
1756                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1757                                         // Arguments are yet supported by the stack map creation code
1758                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1759                                 } else {
1760                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1761                                         ins->inst_offset = - offset;
1762                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1763                                 }
1764                         }
1765                 }
1766         }
1767
1768         cfg->stack_offset = offset;
1769 }
1770
1771 void
1772 mono_arch_create_vars (MonoCompile *cfg)
1773 {
1774         MonoMethodSignature *sig;
1775         CallInfo *cinfo;
1776         MonoType *sig_ret;
1777
1778         sig = mono_method_signature (cfg->method);
1779
1780         if (!cfg->arch.cinfo)
1781                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1782         cinfo = (CallInfo *)cfg->arch.cinfo;
1783
1784         if (cinfo->ret.storage == ArgValuetypeInReg)
1785                 cfg->ret_var_is_local = TRUE;
1786
1787         sig_ret = mini_get_underlying_type (sig->ret);
1788         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1789                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1790                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1791                         printf ("vret_addr = ");
1792                         mono_print_ins (cfg->vret_addr);
1793                 }
1794         }
1795
1796         if (cfg->gen_sdb_seq_points) {
1797                 MonoInst *ins;
1798
1799                 if (cfg->compile_aot) {
1800                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1801                         ins->flags |= MONO_INST_VOLATILE;
1802                         cfg->arch.seq_point_info_var = ins;
1803                 }
1804                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1805                 ins->flags |= MONO_INST_VOLATILE;
1806                 cfg->arch.ss_tramp_var = ins;
1807
1808                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1809                 ins->flags |= MONO_INST_VOLATILE;
1810                 cfg->arch.bp_tramp_var = ins;
1811         }
1812
1813         if (cfg->method->save_lmf)
1814                 cfg->create_lmf_var = TRUE;
1815
1816         if (cfg->method->save_lmf) {
1817                 cfg->lmf_ir = TRUE;
1818         }
1819 }
1820
1821 static void
1822 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1823 {
1824         MonoInst *ins;
1825
1826         switch (storage) {
1827         case ArgInIReg:
1828                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1829                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1830                 ins->sreg1 = tree->dreg;
1831                 MONO_ADD_INS (cfg->cbb, ins);
1832                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1833                 break;
1834         case ArgInFloatSSEReg:
1835                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1836                 ins->dreg = mono_alloc_freg (cfg);
1837                 ins->sreg1 = tree->dreg;
1838                 MONO_ADD_INS (cfg->cbb, ins);
1839
1840                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1841                 break;
1842         case ArgInDoubleSSEReg:
1843                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1844                 ins->dreg = mono_alloc_freg (cfg);
1845                 ins->sreg1 = tree->dreg;
1846                 MONO_ADD_INS (cfg->cbb, ins);
1847
1848                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1849
1850                 break;
1851         default:
1852                 g_assert_not_reached ();
1853         }
1854 }
1855
1856 static int
1857 arg_storage_to_load_membase (ArgStorage storage)
1858 {
1859         switch (storage) {
1860         case ArgInIReg:
1861 #if defined(__mono_ilp32__)
1862                 return OP_LOADI8_MEMBASE;
1863 #else
1864                 return OP_LOAD_MEMBASE;
1865 #endif
1866         case ArgInDoubleSSEReg:
1867                 return OP_LOADR8_MEMBASE;
1868         case ArgInFloatSSEReg:
1869                 return OP_LOADR4_MEMBASE;
1870         default:
1871                 g_assert_not_reached ();
1872         }
1873
1874         return -1;
1875 }
1876
1877 static void
1878 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1879 {
1880         MonoMethodSignature *tmp_sig;
1881         int sig_reg;
1882
1883         if (call->tail_call)
1884                 NOT_IMPLEMENTED;
1885
1886         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1887
1888         /*
1889          * mono_ArgIterator_Setup assumes the signature cookie is
1890          * passed first and all the arguments which were before it are
1891          * passed on the stack after the signature. So compensate by
1892          * passing a different signature.
1893          */
1894         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1895         tmp_sig->param_count -= call->signature->sentinelpos;
1896         tmp_sig->sentinelpos = 0;
1897         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1898
1899         sig_reg = mono_alloc_ireg (cfg);
1900         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1901
1902         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1903 }
1904
1905 #ifdef ENABLE_LLVM
1906 static inline LLVMArgStorage
1907 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1908 {
1909         switch (storage) {
1910         case ArgInIReg:
1911                 return LLVMArgInIReg;
1912         case ArgNone:
1913                 return LLVMArgNone;
1914         case ArgGSharedVtInReg:
1915         case ArgGSharedVtOnStack:
1916                 return LLVMArgGSharedVt;
1917         default:
1918                 g_assert_not_reached ();
1919                 return LLVMArgNone;
1920         }
1921 }
1922
1923 LLVMCallInfo*
1924 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1925 {
1926         int i, n;
1927         CallInfo *cinfo;
1928         ArgInfo *ainfo;
1929         int j;
1930         LLVMCallInfo *linfo;
1931         MonoType *t, *sig_ret;
1932
1933         n = sig->param_count + sig->hasthis;
1934         sig_ret = mini_get_underlying_type (sig->ret);
1935
1936         cinfo = get_call_info (cfg->mempool, sig);
1937
1938         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1939
1940         /*
1941          * LLVM always uses the native ABI while we use our own ABI, the
1942          * only difference is the handling of vtypes:
1943          * - we only pass/receive them in registers in some cases, and only
1944          *   in 1 or 2 integer registers.
1945          */
1946         switch (cinfo->ret.storage) {
1947         case ArgNone:
1948                 linfo->ret.storage = LLVMArgNone;
1949                 break;
1950         case ArgInIReg:
1951         case ArgInFloatSSEReg:
1952         case ArgInDoubleSSEReg:
1953                 linfo->ret.storage = LLVMArgNormal;
1954                 break;
1955         case ArgValuetypeInReg: {
1956                 ainfo = &cinfo->ret;
1957
1958                 if (sig->pinvoke &&
1959                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1960                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1961                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1962                         cfg->disable_llvm = TRUE;
1963                         return linfo;
1964                 }
1965
1966                 linfo->ret.storage = LLVMArgVtypeInReg;
1967                 for (j = 0; j < 2; ++j)
1968                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1969                 break;
1970         }
1971         case ArgValuetypeAddrInIReg:
1972         case ArgGsharedvtVariableInReg:
1973                 /* Vtype returned using a hidden argument */
1974                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1975                 linfo->vret_arg_index = cinfo->vret_arg_index;
1976                 break;
1977         default:
1978                 g_assert_not_reached ();
1979                 break;
1980         }
1981
1982         for (i = 0; i < n; ++i) {
1983                 ainfo = cinfo->args + i;
1984
1985                 if (i >= sig->hasthis)
1986                         t = sig->params [i - sig->hasthis];
1987                 else
1988                         t = &mono_defaults.int_class->byval_arg;
1989                 t = mini_type_get_underlying_type (t);
1990
1991                 linfo->args [i].storage = LLVMArgNone;
1992
1993                 switch (ainfo->storage) {
1994                 case ArgInIReg:
1995                         linfo->args [i].storage = LLVMArgNormal;
1996                         break;
1997                 case ArgInDoubleSSEReg:
1998                 case ArgInFloatSSEReg:
1999                         linfo->args [i].storage = LLVMArgNormal;
2000                         break;
2001                 case ArgOnStack:
2002                         if (MONO_TYPE_ISSTRUCT (t))
2003                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2004                         else
2005                                 linfo->args [i].storage = LLVMArgNormal;
2006                         break;
2007                 case ArgValuetypeInReg:
2008                         if (sig->pinvoke &&
2009                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2010                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2011                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2012                                 cfg->disable_llvm = TRUE;
2013                                 return linfo;
2014                         }
2015
2016                         linfo->args [i].storage = LLVMArgVtypeInReg;
2017                         for (j = 0; j < 2; ++j)
2018                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2019                         break;
2020                 case ArgGSharedVtInReg:
2021                 case ArgGSharedVtOnStack:
2022                         linfo->args [i].storage = LLVMArgGSharedVt;
2023                         break;
2024                 default:
2025                         cfg->exception_message = g_strdup ("ainfo->storage");
2026                         cfg->disable_llvm = TRUE;
2027                         break;
2028                 }
2029         }
2030
2031         return linfo;
2032 }
2033 #endif
2034
2035 void
2036 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2037 {
2038         MonoInst *arg, *in;
2039         MonoMethodSignature *sig;
2040         MonoType *sig_ret;
2041         int i, n;
2042         CallInfo *cinfo;
2043         ArgInfo *ainfo;
2044
2045         sig = call->signature;
2046         n = sig->param_count + sig->hasthis;
2047
2048         cinfo = get_call_info (cfg->mempool, sig);
2049
2050         sig_ret = sig->ret;
2051
2052         if (COMPILE_LLVM (cfg)) {
2053                 /* We shouldn't be called in the llvm case */
2054                 cfg->disable_llvm = TRUE;
2055                 return;
2056         }
2057
2058         /*
2059          * Emit all arguments which are passed on the stack to prevent register
2060          * allocation problems.
2061          */
2062         for (i = 0; i < n; ++i) {
2063                 MonoType *t;
2064                 ainfo = cinfo->args + i;
2065
2066                 in = call->args [i];
2067
2068                 if (sig->hasthis && i == 0)
2069                         t = &mono_defaults.object_class->byval_arg;
2070                 else
2071                         t = sig->params [i - sig->hasthis];
2072
2073                 t = mini_get_underlying_type (t);
2074                 //XXX what about ArgGSharedVtOnStack here?
2075                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2076                         if (!t->byref) {
2077                                 if (t->type == MONO_TYPE_R4)
2078                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2079                                 else if (t->type == MONO_TYPE_R8)
2080                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2081                                 else
2082                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2083                         } else {
2084                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2085                         }
2086                         if (cfg->compute_gc_maps) {
2087                                 MonoInst *def;
2088
2089                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2090                         }
2091                 }
2092         }
2093
2094         /*
2095          * Emit all parameters passed in registers in non-reverse order for better readability
2096          * and to help the optimization in emit_prolog ().
2097          */
2098         for (i = 0; i < n; ++i) {
2099                 ainfo = cinfo->args + i;
2100
2101                 in = call->args [i];
2102
2103                 if (ainfo->storage == ArgInIReg)
2104                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2105         }
2106
2107         for (i = n - 1; i >= 0; --i) {
2108                 MonoType *t;
2109
2110                 ainfo = cinfo->args + i;
2111
2112                 in = call->args [i];
2113
2114                 if (sig->hasthis && i == 0)
2115                         t = &mono_defaults.object_class->byval_arg;
2116                 else
2117                         t = sig->params [i - sig->hasthis];
2118                 t = mini_get_underlying_type (t);
2119
2120                 switch (ainfo->storage) {
2121                 case ArgInIReg:
2122                         /* Already done */
2123                         break;
2124                 case ArgInFloatSSEReg:
2125                 case ArgInDoubleSSEReg:
2126                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2127                         break;
2128                 case ArgOnStack:
2129                 case ArgValuetypeInReg:
2130                 case ArgValuetypeAddrInIReg:
2131                 case ArgValuetypeAddrOnStack:
2132                 case ArgGSharedVtInReg:
2133                 case ArgGSharedVtOnStack: {
2134                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2135                                 /* Already emitted above */
2136                                 break;
2137                         //FIXME what about ArgGSharedVtOnStack ?
2138                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2139                                 MonoInst *call_inst = (MonoInst*)call;
2140                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2141                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2142                                 break;
2143                         }
2144
2145                         guint32 align;
2146                         guint32 size;
2147
2148                         if (sig->pinvoke)
2149                                 size = mono_type_native_stack_size (t, &align);
2150                         else {
2151                                 /*
2152                                  * Other backends use mono_type_stack_size (), but that
2153                                  * aligns the size to 8, which is larger than the size of
2154                                  * the source, leading to reads of invalid memory if the
2155                                  * source is at the end of address space.
2156                                  */
2157                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2158                         }
2159
2160                         if (size >= 10000) {
2161                                 /* Avoid asserts in emit_memcpy () */
2162                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2163                                 /* Continue normally */
2164                         }
2165
2166                         if (size > 0 || ainfo->pass_empty_struct) {
2167                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2168                                 arg->sreg1 = in->dreg;
2169                                 arg->klass = mono_class_from_mono_type (t);
2170                                 arg->backend.size = size;
2171                                 arg->inst_p0 = call;
2172                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2173                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2174
2175                                 MONO_ADD_INS (cfg->cbb, arg);
2176                         }
2177                         break;
2178                 }
2179                 default:
2180                         g_assert_not_reached ();
2181                 }
2182
2183                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2184                         /* Emit the signature cookie just before the implicit arguments */
2185                         emit_sig_cookie (cfg, call, cinfo);
2186         }
2187
2188         /* Handle the case where there are no implicit arguments */
2189         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2190                 emit_sig_cookie (cfg, call, cinfo);
2191
2192         switch (cinfo->ret.storage) {
2193         case ArgValuetypeInReg:
2194                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2195                         /*
2196                          * Tell the JIT to use a more efficient calling convention: call using
2197                          * OP_CALL, compute the result location after the call, and save the
2198                          * result there.
2199                          */
2200                         call->vret_in_reg = TRUE;
2201                         /*
2202                          * Nullify the instruction computing the vret addr to enable
2203                          * future optimizations.
2204                          */
2205                         if (call->vret_var)
2206                                 NULLIFY_INS (call->vret_var);
2207                 } else {
2208                         if (call->tail_call)
2209                                 NOT_IMPLEMENTED;
2210                         /*
2211                          * The valuetype is in RAX:RDX after the call, need to be copied to
2212                          * the stack. Push the address here, so the call instruction can
2213                          * access it.
2214                          */
2215                         if (!cfg->arch.vret_addr_loc) {
2216                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2217                                 /* Prevent it from being register allocated or optimized away */
2218                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2219                         }
2220
2221                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2222                 }
2223                 break;
2224         case ArgValuetypeAddrInIReg:
2225         case ArgGsharedvtVariableInReg: {
2226                 MonoInst *vtarg;
2227                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2228                 vtarg->sreg1 = call->vret_var->dreg;
2229                 vtarg->dreg = mono_alloc_preg (cfg);
2230                 MONO_ADD_INS (cfg->cbb, vtarg);
2231
2232                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2233                 break;
2234         }
2235         default:
2236                 break;
2237         }
2238
2239         if (cfg->method->save_lmf) {
2240                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2241                 MONO_ADD_INS (cfg->cbb, arg);
2242         }
2243
2244         call->stack_usage = cinfo->stack_usage;
2245 }
2246
2247 void
2248 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2249 {
2250         MonoInst *arg;
2251         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2252         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2253         int size = ins->backend.size;
2254
2255         switch (ainfo->storage) {
2256         case ArgValuetypeInReg: {
2257                 MonoInst *load;
2258                 int part;
2259
2260                 for (part = 0; part < 2; ++part) {
2261                         if (ainfo->pair_storage [part] == ArgNone)
2262                                 continue;
2263
2264                         if (ainfo->pass_empty_struct) {
2265                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2266                                 NEW_ICONST (cfg, load, 0);
2267                         }
2268                         else {
2269                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2270                                 load->inst_basereg = src->dreg;
2271                                 load->inst_offset = part * sizeof(mgreg_t);
2272
2273                                 switch (ainfo->pair_storage [part]) {
2274                                 case ArgInIReg:
2275                                         load->dreg = mono_alloc_ireg (cfg);
2276                                         break;
2277                                 case ArgInDoubleSSEReg:
2278                                 case ArgInFloatSSEReg:
2279                                         load->dreg = mono_alloc_freg (cfg);
2280                                         break;
2281                                 default:
2282                                         g_assert_not_reached ();
2283                                 }
2284                         }
2285
2286                         MONO_ADD_INS (cfg->cbb, load);
2287
2288                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2289                 }
2290                 break;
2291         }
2292         case ArgValuetypeAddrInIReg:
2293         case ArgValuetypeAddrOnStack: {
2294                 MonoInst *vtaddr, *load;
2295
2296                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2297
2298                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2299
2300                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2301                 cfg->has_indirection = TRUE;
2302                 load->inst_p0 = vtaddr;
2303                 vtaddr->flags |= MONO_INST_INDIRECT;
2304                 load->type = STACK_MP;
2305                 load->klass = vtaddr->klass;
2306                 load->dreg = mono_alloc_ireg (cfg);
2307                 MONO_ADD_INS (cfg->cbb, load);
2308                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2309
2310                 if (ainfo->pair_storage [0] == ArgInIReg) {
2311                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2312                         arg->dreg = mono_alloc_ireg (cfg);
2313                         arg->sreg1 = load->dreg;
2314                         arg->inst_imm = 0;
2315                         MONO_ADD_INS (cfg->cbb, arg);
2316                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2317                 } else {
2318                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2319                 }
2320                 break;
2321         }
2322         case ArgGSharedVtInReg:
2323                 /* Pass by addr */
2324                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2325                 break;
2326         case ArgGSharedVtOnStack:
2327                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2328                 break;
2329         default:
2330                 if (size == 8) {
2331                         int dreg = mono_alloc_ireg (cfg);
2332
2333                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2334                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2335                 } else if (size <= 40) {
2336                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2337                 } else {
2338                         // FIXME: Code growth
2339                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2340                 }
2341
2342                 if (cfg->compute_gc_maps) {
2343                         MonoInst *def;
2344                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2345                 }
2346         }
2347 }
2348
2349 void
2350 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2351 {
2352         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2353
2354         if (ret->type == MONO_TYPE_R4) {
2355                 if (COMPILE_LLVM (cfg))
2356                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2357                 else
2358                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2359                 return;
2360         } else if (ret->type == MONO_TYPE_R8) {
2361                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2362                 return;
2363         }
2364
2365         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2366 }
2367
2368 #endif /* DISABLE_JIT */
2369
2370 #define EMIT_COND_BRANCH(ins,cond,sign) \
2371         if (ins->inst_true_bb->native_offset) { \
2372                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2373         } else { \
2374                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2375                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2376             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2377                         x86_branch8 (code, cond, 0, sign); \
2378                 else \
2379                         x86_branch32 (code, cond, 0, sign); \
2380 }
2381
2382 typedef struct {
2383         MonoMethodSignature *sig;
2384         CallInfo *cinfo;
2385 } ArchDynCallInfo;
2386
2387 static gboolean
2388 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2389 {
2390         int i;
2391
2392         switch (cinfo->ret.storage) {
2393         case ArgNone:
2394         case ArgInIReg:
2395         case ArgInFloatSSEReg:
2396         case ArgInDoubleSSEReg:
2397         case ArgValuetypeAddrInIReg:
2398         case ArgValuetypeInReg:
2399                 break;
2400         default:
2401                 return FALSE;
2402         }
2403
2404         for (i = 0; i < cinfo->nargs; ++i) {
2405                 ArgInfo *ainfo = &cinfo->args [i];
2406                 switch (ainfo->storage) {
2407                 case ArgInIReg:
2408                 case ArgInFloatSSEReg:
2409                 case ArgInDoubleSSEReg:
2410                 case ArgValuetypeInReg:
2411                         break;
2412                 case ArgOnStack:
2413                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2414                                 return FALSE;
2415                         break;
2416                 default:
2417                         return FALSE;
2418                 }
2419         }
2420
2421         return TRUE;
2422 }
2423
2424 /*
2425  * mono_arch_dyn_call_prepare:
2426  *
2427  *   Return a pointer to an arch-specific structure which contains information
2428  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2429  * supported for SIG.
2430  * This function is equivalent to ffi_prep_cif in libffi.
2431  */
2432 MonoDynCallInfo*
2433 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2434 {
2435         ArchDynCallInfo *info;
2436         CallInfo *cinfo;
2437
2438         cinfo = get_call_info (NULL, sig);
2439
2440         if (!dyn_call_supported (sig, cinfo)) {
2441                 g_free (cinfo);
2442                 return NULL;
2443         }
2444
2445         info = g_new0 (ArchDynCallInfo, 1);
2446         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2447         info->sig = sig;
2448         info->cinfo = cinfo;
2449
2450         return (MonoDynCallInfo*)info;
2451 }
2452
2453 /*
2454  * mono_arch_dyn_call_free:
2455  *
2456  *   Free a MonoDynCallInfo structure.
2457  */
2458 void
2459 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2460 {
2461         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2462
2463         g_free (ainfo->cinfo);
2464         g_free (ainfo);
2465 }
2466
2467 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2468 #define GREG_TO_PTR(greg) (gpointer)(greg)
2469
2470 /*
2471  * mono_arch_get_start_dyn_call:
2472  *
2473  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2474  * store the result into BUF.
2475  * ARGS should be an array of pointers pointing to the arguments.
2476  * RET should point to a memory buffer large enought to hold the result of the
2477  * call.
2478  * This function should be as fast as possible, any work which does not depend
2479  * on the actual values of the arguments should be done in
2480  * mono_arch_dyn_call_prepare ().
2481  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2482  * libffi.
2483  */
2484 void
2485 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2486 {
2487         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2488         DynCallArgs *p = (DynCallArgs*)buf;
2489         int arg_index, greg, freg, i, pindex;
2490         MonoMethodSignature *sig = dinfo->sig;
2491         int buffer_offset = 0;
2492         static int param_reg_to_index [16];
2493         static gboolean param_reg_to_index_inited;
2494
2495         if (!param_reg_to_index_inited) {
2496                 for (i = 0; i < PARAM_REGS; ++i)
2497                         param_reg_to_index [param_regs [i]] = i;
2498                 mono_memory_barrier ();
2499                 param_reg_to_index_inited = 1;
2500         }
2501
2502         g_assert (buf_len >= sizeof (DynCallArgs));
2503
2504         p->res = 0;
2505         p->ret = ret;
2506
2507         arg_index = 0;
2508         greg = 0;
2509         freg = 0;
2510         pindex = 0;
2511
2512         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2513                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2514                 if (!sig->hasthis)
2515                         pindex = 1;
2516         }
2517
2518         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2519                 p->regs [greg ++] = PTR_TO_GREG(ret);
2520
2521         for (; pindex < sig->param_count; pindex++) {
2522                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2523                 gpointer *arg = args [arg_index ++];
2524                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2525                 int slot;
2526
2527                 if (ainfo->storage == ArgOnStack) {
2528                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2529                 } else {
2530                         slot = param_reg_to_index [ainfo->reg];
2531                 }
2532
2533                 if (t->byref) {
2534                         p->regs [slot] = PTR_TO_GREG(*(arg));
2535                         greg ++;
2536                         continue;
2537                 }
2538
2539                 switch (t->type) {
2540                 case MONO_TYPE_OBJECT:
2541                 case MONO_TYPE_PTR:
2542                 case MONO_TYPE_I:
2543                 case MONO_TYPE_U:
2544 #if !defined(__mono_ilp32__)
2545                 case MONO_TYPE_I8:
2546                 case MONO_TYPE_U8:
2547 #endif
2548                         p->regs [slot] = PTR_TO_GREG(*(arg));
2549                         break;
2550 #if defined(__mono_ilp32__)
2551                 case MONO_TYPE_I8:
2552                 case MONO_TYPE_U8:
2553                         p->regs [slot] = *(guint64*)(arg);
2554                         break;
2555 #endif
2556                 case MONO_TYPE_U1:
2557                         p->regs [slot] = *(guint8*)(arg);
2558                         break;
2559                 case MONO_TYPE_I1:
2560                         p->regs [slot] = *(gint8*)(arg);
2561                         break;
2562                 case MONO_TYPE_I2:
2563                         p->regs [slot] = *(gint16*)(arg);
2564                         break;
2565                 case MONO_TYPE_U2:
2566                         p->regs [slot] = *(guint16*)(arg);
2567                         break;
2568                 case MONO_TYPE_I4:
2569                         p->regs [slot] = *(gint32*)(arg);
2570                         break;
2571                 case MONO_TYPE_U4:
2572                         p->regs [slot] = *(guint32*)(arg);
2573                         break;
2574                 case MONO_TYPE_R4: {
2575                         double d;
2576
2577                         *(float*)&d = *(float*)(arg);
2578                         p->has_fp = 1;
2579                         p->fregs [freg ++] = d;
2580                         break;
2581                 }
2582                 case MONO_TYPE_R8:
2583                         p->has_fp = 1;
2584                         p->fregs [freg ++] = *(double*)(arg);
2585                         break;
2586                 case MONO_TYPE_GENERICINST:
2587                     if (MONO_TYPE_IS_REFERENCE (t)) {
2588                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2589                                 break;
2590                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2591                                         MonoClass *klass = mono_class_from_mono_type (t);
2592                                         guint8 *nullable_buf;
2593                                         int size;
2594
2595                                         size = mono_class_value_size (klass, NULL);
2596                                         nullable_buf = p->buffer + buffer_offset;
2597                                         buffer_offset += size;
2598                                         g_assert (buffer_offset <= 256);
2599
2600                                         /* The argument pointed to by arg is either a boxed vtype or null */
2601                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2602
2603                                         arg = (gpointer*)nullable_buf;
2604                                         /* Fall though */
2605
2606                         } else {
2607                                 /* Fall through */
2608                         }
2609                 case MONO_TYPE_VALUETYPE: {
2610                         switch (ainfo->storage) {
2611                         case ArgValuetypeInReg:
2612                                 for (i = 0; i < 2; ++i) {
2613                                         switch (ainfo->pair_storage [i]) {
2614                                         case ArgNone:
2615                                                 break;
2616                                         case ArgInIReg:
2617                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2618                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2619                                                 break;
2620                                         case ArgInDoubleSSEReg:
2621                                                 p->has_fp = 1;
2622                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2623                                                 break;
2624                                         default:
2625                                                 g_assert_not_reached ();
2626                                                 break;
2627                                         }
2628                                 }
2629                                 break;
2630                         case ArgOnStack:
2631                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2632                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2633                                 break;
2634                         default:
2635                                 g_assert_not_reached ();
2636                                 break;
2637                         }
2638                         break;
2639                 }
2640                 default:
2641                         g_assert_not_reached ();
2642                 }
2643         }
2644 }
2645
2646 /*
2647  * mono_arch_finish_dyn_call:
2648  *
2649  *   Store the result of a dyn call into the return value buffer passed to
2650  * start_dyn_call ().
2651  * This function should be as fast as possible, any work which does not depend
2652  * on the actual values of the arguments should be done in
2653  * mono_arch_dyn_call_prepare ().
2654  */
2655 void
2656 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2657 {
2658         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2659         MonoMethodSignature *sig = dinfo->sig;
2660         DynCallArgs *dargs = (DynCallArgs*)buf;
2661         guint8 *ret = dargs->ret;
2662         mgreg_t res = dargs->res;
2663         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2664         int i;
2665
2666         switch (sig_ret->type) {
2667         case MONO_TYPE_VOID:
2668                 *(gpointer*)ret = NULL;
2669                 break;
2670         case MONO_TYPE_OBJECT:
2671         case MONO_TYPE_I:
2672         case MONO_TYPE_U:
2673         case MONO_TYPE_PTR:
2674                 *(gpointer*)ret = GREG_TO_PTR(res);
2675                 break;
2676         case MONO_TYPE_I1:
2677                 *(gint8*)ret = res;
2678                 break;
2679         case MONO_TYPE_U1:
2680                 *(guint8*)ret = res;
2681                 break;
2682         case MONO_TYPE_I2:
2683                 *(gint16*)ret = res;
2684                 break;
2685         case MONO_TYPE_U2:
2686                 *(guint16*)ret = res;
2687                 break;
2688         case MONO_TYPE_I4:
2689                 *(gint32*)ret = res;
2690                 break;
2691         case MONO_TYPE_U4:
2692                 *(guint32*)ret = res;
2693                 break;
2694         case MONO_TYPE_I8:
2695                 *(gint64*)ret = res;
2696                 break;
2697         case MONO_TYPE_U8:
2698                 *(guint64*)ret = res;
2699                 break;
2700         case MONO_TYPE_R4:
2701                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2702                 break;
2703         case MONO_TYPE_R8:
2704                 *(double*)ret = dargs->fregs [0];
2705                 break;
2706         case MONO_TYPE_GENERICINST:
2707                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2708                         *(gpointer*)ret = GREG_TO_PTR(res);
2709                         break;
2710                 } else {
2711                         /* Fall through */
2712                 }
2713         case MONO_TYPE_VALUETYPE:
2714                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2715                         /* Nothing to do */
2716                 } else {
2717                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2718
2719                         g_assert (ainfo->storage == ArgValuetypeInReg);
2720
2721                         for (i = 0; i < 2; ++i) {
2722                                 switch (ainfo->pair_storage [0]) {
2723                                 case ArgInIReg:
2724                                         ((mgreg_t*)ret)[i] = res;
2725                                         break;
2726                                 case ArgInDoubleSSEReg:
2727                                         ((double*)ret)[i] = dargs->fregs [i];
2728                                         break;
2729                                 case ArgNone:
2730                                         break;
2731                                 default:
2732                                         g_assert_not_reached ();
2733                                         break;
2734                                 }
2735                         }
2736                 }
2737                 break;
2738         default:
2739                 g_assert_not_reached ();
2740         }
2741 }
2742
2743 /* emit an exception if condition is fail */
2744 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2745         do {                                                        \
2746                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2747                 if (tins == NULL) {                                                                             \
2748                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2749                                         MONO_PATCH_INFO_EXC, exc_name);  \
2750                         x86_branch32 (code, cond, 0, signed);               \
2751                 } else {        \
2752                         EMIT_COND_BRANCH (tins, cond, signed);  \
2753                 }                       \
2754         } while (0);
2755
2756 #define EMIT_FPCOMPARE(code) do { \
2757         amd64_fcompp (code); \
2758         amd64_fnstsw (code); \
2759 } while (0);
2760
2761 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2762     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2763         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2764         amd64_ ##op (code); \
2765         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2766         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2767 } while (0);
2768
2769 static guint8*
2770 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2771 {
2772         gboolean no_patch = FALSE;
2773
2774         /*
2775          * FIXME: Add support for thunks
2776          */
2777         {
2778                 gboolean near_call = FALSE;
2779
2780                 /*
2781                  * Indirect calls are expensive so try to make a near call if possible.
2782                  * The caller memory is allocated by the code manager so it is
2783                  * guaranteed to be at a 32 bit offset.
2784                  */
2785
2786                 if (patch_type != MONO_PATCH_INFO_ABS) {
2787                         /* The target is in memory allocated using the code manager */
2788                         near_call = TRUE;
2789
2790                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2791                                 if (((MonoMethod*)data)->klass->image->aot_module)
2792                                         /* The callee might be an AOT method */
2793                                         near_call = FALSE;
2794                                 if (((MonoMethod*)data)->dynamic)
2795                                         /* The target is in malloc-ed memory */
2796                                         near_call = FALSE;
2797                         }
2798
2799                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2800                                 /*
2801                                  * The call might go directly to a native function without
2802                                  * the wrapper.
2803                                  */
2804                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2805                                 if (mi) {
2806                                         gconstpointer target = mono_icall_get_wrapper (mi);
2807                                         if ((((guint64)target) >> 32) != 0)
2808                                                 near_call = FALSE;
2809                                 }
2810                         }
2811                 }
2812                 else {
2813                         MonoJumpInfo *jinfo = NULL;
2814
2815                         if (cfg->abs_patches)
2816                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2817                         if (jinfo) {
2818                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2819                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2820                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2821                                                 near_call = TRUE;
2822                                         no_patch = TRUE;
2823                                 } else {
2824                                         /*
2825                                          * This is not really an optimization, but required because the
2826                                          * generic class init trampolines use R11 to pass the vtable.
2827                                          */
2828                                         near_call = TRUE;
2829                                 }
2830                         } else {
2831                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2832                                 if (info) {
2833                                         if (info->func == info->wrapper) {
2834                                                 /* No wrapper */
2835                                                 if ((((guint64)info->func) >> 32) == 0)
2836                                                         near_call = TRUE;
2837                                         }
2838                                         else {
2839                                                 /* See the comment in mono_codegen () */
2840                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2841                                                         near_call = TRUE;
2842                                         }
2843                                 }
2844                                 else if ((((guint64)data) >> 32) == 0) {
2845                                         near_call = TRUE;
2846                                         no_patch = TRUE;
2847                                 }
2848                         }
2849                 }
2850
2851                 if (cfg->method->dynamic)
2852                         /* These methods are allocated using malloc */
2853                         near_call = FALSE;
2854
2855 #ifdef MONO_ARCH_NOMAP32BIT
2856                 near_call = FALSE;
2857 #endif
2858                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2859                 if (optimize_for_xen)
2860                         near_call = FALSE;
2861
2862                 if (cfg->compile_aot) {
2863                         near_call = TRUE;
2864                         no_patch = TRUE;
2865                 }
2866
2867                 if (near_call) {
2868                         /*
2869                          * Align the call displacement to an address divisible by 4 so it does
2870                          * not span cache lines. This is required for code patching to work on SMP
2871                          * systems.
2872                          */
2873                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2874                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2875                                 amd64_padding (code, pad_size);
2876                         }
2877                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2878                         amd64_call_code (code, 0);
2879                 }
2880                 else {
2881                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2882                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2883                         amd64_call_reg (code, GP_SCRATCH_REG);
2884                 }
2885         }
2886
2887         return code;
2888 }
2889
2890 static inline guint8*
2891 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2892 {
2893 #ifdef TARGET_WIN32
2894         if (win64_adjust_stack)
2895                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2896 #endif
2897         code = emit_call_body (cfg, code, patch_type, data);
2898 #ifdef TARGET_WIN32
2899         if (win64_adjust_stack)
2900                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2901 #endif
2902
2903         return code;
2904 }
2905
2906 static inline int
2907 store_membase_imm_to_store_membase_reg (int opcode)
2908 {
2909         switch (opcode) {
2910         case OP_STORE_MEMBASE_IMM:
2911                 return OP_STORE_MEMBASE_REG;
2912         case OP_STOREI4_MEMBASE_IMM:
2913                 return OP_STOREI4_MEMBASE_REG;
2914         case OP_STOREI8_MEMBASE_IMM:
2915                 return OP_STOREI8_MEMBASE_REG;
2916         }
2917
2918         return -1;
2919 }
2920
2921 #ifndef DISABLE_JIT
2922
2923 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2924
2925 /*
2926  * mono_arch_peephole_pass_1:
2927  *
2928  *   Perform peephole opts which should/can be performed before local regalloc
2929  */
2930 void
2931 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2932 {
2933         MonoInst *ins, *n;
2934
2935         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2936                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2937
2938                 switch (ins->opcode) {
2939                 case OP_ADD_IMM:
2940                 case OP_IADD_IMM:
2941                 case OP_LADD_IMM:
2942                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2943                                 /*
2944                                  * X86_LEA is like ADD, but doesn't have the
2945                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2946                                  * its operand to 64 bit.
2947                                  */
2948                                 ins->opcode = OP_X86_LEA_MEMBASE;
2949                                 ins->inst_basereg = ins->sreg1;
2950                         }
2951                         break;
2952                 case OP_LXOR:
2953                 case OP_IXOR:
2954                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2955                                 MonoInst *ins2;
2956
2957                                 /*
2958                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2959                                  * the latter has length 2-3 instead of 6 (reverse constant
2960                                  * propagation). These instruction sequences are very common
2961                                  * in the initlocals bblock.
2962                                  */
2963                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2964                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2965                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2966                                                 ins2->sreg1 = ins->dreg;
2967                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2968                                                 /* Continue */
2969                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2970                                                 NULLIFY_INS (ins2);
2971                                                 /* Continue */
2972                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2973                                                 /* Continue */
2974                                         } else {
2975                                                 break;
2976                                         }
2977                                 }
2978                         }
2979                         break;
2980                 case OP_COMPARE_IMM:
2981                 case OP_LCOMPARE_IMM:
2982                         /* OP_COMPARE_IMM (reg, 0)
2983                          * -->
2984                          * OP_AMD64_TEST_NULL (reg)
2985                          */
2986                         if (!ins->inst_imm)
2987                                 ins->opcode = OP_AMD64_TEST_NULL;
2988                         break;
2989                 case OP_ICOMPARE_IMM:
2990                         if (!ins->inst_imm)
2991                                 ins->opcode = OP_X86_TEST_NULL;
2992                         break;
2993                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2994                         /*
2995                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2996                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2997                          * -->
2998                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2999                          * OP_COMPARE_IMM reg, imm
3000                          *
3001                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3002                          */
3003                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3004                             ins->inst_basereg == last_ins->inst_destbasereg &&
3005                             ins->inst_offset == last_ins->inst_offset) {
3006                                         ins->opcode = OP_ICOMPARE_IMM;
3007                                         ins->sreg1 = last_ins->sreg1;
3008
3009                                         /* check if we can remove cmp reg,0 with test null */
3010                                         if (!ins->inst_imm)
3011                                                 ins->opcode = OP_X86_TEST_NULL;
3012                                 }
3013
3014                         break;
3015                 }
3016
3017                 mono_peephole_ins (bb, ins);
3018         }
3019 }
3020
3021 void
3022 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3023 {
3024         MonoInst *ins, *n;
3025
3026         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3027                 switch (ins->opcode) {
3028                 case OP_ICONST:
3029                 case OP_I8CONST: {
3030                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3031                         /* reg = 0 -> XOR (reg, reg) */
3032                         /* XOR sets cflags on x86, so we cant do it always */
3033                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3034                                 ins->opcode = OP_LXOR;
3035                                 ins->sreg1 = ins->dreg;
3036                                 ins->sreg2 = ins->dreg;
3037                                 /* Fall through */
3038                         } else {
3039                                 break;
3040                         }
3041                 }
3042                 case OP_LXOR:
3043                         /*
3044                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3045                          * 0 result into 64 bits.
3046                          */
3047                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3048                                 ins->opcode = OP_IXOR;
3049                         }
3050                         /* Fall through */
3051                 case OP_IXOR:
3052                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3053                                 MonoInst *ins2;
3054
3055                                 /*
3056                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3057                                  * the latter has length 2-3 instead of 6 (reverse constant
3058                                  * propagation). These instruction sequences are very common
3059                                  * in the initlocals bblock.
3060                                  */
3061                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3062                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3063                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3064                                                 ins2->sreg1 = ins->dreg;
3065                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3066                                                 /* Continue */
3067                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3068                                                 NULLIFY_INS (ins2);
3069                                                 /* Continue */
3070                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3071                                                 /* Continue */
3072                                         } else {
3073                                                 break;
3074                                         }
3075                                 }
3076                         }
3077                         break;
3078                 case OP_IADD_IMM:
3079                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3080                                 ins->opcode = OP_X86_INC_REG;
3081                         break;
3082                 case OP_ISUB_IMM:
3083                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3084                                 ins->opcode = OP_X86_DEC_REG;
3085                         break;
3086                 }
3087
3088                 mono_peephole_ins (bb, ins);
3089         }
3090 }
3091
3092 #define NEW_INS(cfg,ins,dest,op) do {   \
3093                 MONO_INST_NEW ((cfg), (dest), (op)); \
3094         (dest)->cil_code = (ins)->cil_code; \
3095         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3096         } while (0)
3097
3098 /*
3099  * mono_arch_lowering_pass:
3100  *
3101  *  Converts complex opcodes into simpler ones so that each IR instruction
3102  * corresponds to one machine instruction.
3103  */
3104 void
3105 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3106 {
3107         MonoInst *ins, *n, *temp;
3108
3109         /*
3110          * FIXME: Need to add more instructions, but the current machine
3111          * description can't model some parts of the composite instructions like
3112          * cdq.
3113          */
3114         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3115                 switch (ins->opcode) {
3116                 case OP_DIV_IMM:
3117                 case OP_REM_IMM:
3118                 case OP_IDIV_IMM:
3119                 case OP_IDIV_UN_IMM:
3120                 case OP_IREM_UN_IMM:
3121                 case OP_LREM_IMM:
3122                 case OP_IREM_IMM:
3123                         mono_decompose_op_imm (cfg, bb, ins);
3124                         break;
3125                 case OP_COMPARE_IMM:
3126                 case OP_LCOMPARE_IMM:
3127                         if (!amd64_use_imm32 (ins->inst_imm)) {
3128                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3129                                 temp->inst_c0 = ins->inst_imm;
3130                                 temp->dreg = mono_alloc_ireg (cfg);
3131                                 ins->opcode = OP_COMPARE;
3132                                 ins->sreg2 = temp->dreg;
3133                         }
3134                         break;
3135 #ifndef __mono_ilp32__
3136                 case OP_LOAD_MEMBASE:
3137 #endif
3138                 case OP_LOADI8_MEMBASE:
3139                 /*  Don't generate memindex opcodes (to simplify */
3140                 /*  read sandboxing) */
3141                         if (!amd64_use_imm32 (ins->inst_offset)) {
3142                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3143                                 temp->inst_c0 = ins->inst_offset;
3144                                 temp->dreg = mono_alloc_ireg (cfg);
3145                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3146                                 ins->inst_indexreg = temp->dreg;
3147                         }
3148                         break;
3149 #ifndef __mono_ilp32__
3150                 case OP_STORE_MEMBASE_IMM:
3151 #endif
3152                 case OP_STOREI8_MEMBASE_IMM:
3153                         if (!amd64_use_imm32 (ins->inst_imm)) {
3154                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3155                                 temp->inst_c0 = ins->inst_imm;
3156                                 temp->dreg = mono_alloc_ireg (cfg);
3157                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3158                                 ins->sreg1 = temp->dreg;
3159                         }
3160                         break;
3161 #ifdef MONO_ARCH_SIMD_INTRINSICS
3162                 case OP_EXPAND_I1: {
3163                                 int temp_reg1 = mono_alloc_ireg (cfg);
3164                                 int temp_reg2 = mono_alloc_ireg (cfg);
3165                                 int original_reg = ins->sreg1;
3166
3167                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3168                                 temp->sreg1 = original_reg;
3169                                 temp->dreg = temp_reg1;
3170
3171                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3172                                 temp->sreg1 = temp_reg1;
3173                                 temp->dreg = temp_reg2;
3174                                 temp->inst_imm = 8;
3175
3176                                 NEW_INS (cfg, ins, temp, OP_LOR);
3177                                 temp->sreg1 = temp->dreg = temp_reg2;
3178                                 temp->sreg2 = temp_reg1;
3179
3180                                 ins->opcode = OP_EXPAND_I2;
3181                                 ins->sreg1 = temp_reg2;
3182                         }
3183                         break;
3184 #endif
3185                 default:
3186                         break;
3187                 }
3188         }
3189
3190         bb->max_vreg = cfg->next_vreg;
3191 }
3192
3193 static const int
3194 branch_cc_table [] = {
3195         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3196         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3197         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3198 };
3199
3200 /* Maps CMP_... constants to X86_CC_... constants */
3201 static const int
3202 cc_table [] = {
3203         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3204         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3205 };
3206
3207 static const int
3208 cc_signed_table [] = {
3209         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3210         FALSE, FALSE, FALSE, FALSE
3211 };
3212
3213 /*#include "cprop.c"*/
3214
3215 static unsigned char*
3216 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3217 {
3218         if (size == 8)
3219                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3220         else
3221                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3222
3223         if (size == 1)
3224                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3225         else if (size == 2)
3226                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3227         return code;
3228 }
3229
3230 static unsigned char*
3231 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3232 {
3233         int sreg = tree->sreg1;
3234         int need_touch = FALSE;
3235
3236 #if defined(TARGET_WIN32)
3237         need_touch = TRUE;
3238 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3239         if (!tree->flags & MONO_INST_INIT)
3240                 need_touch = TRUE;
3241 #endif
3242
3243         if (need_touch) {
3244                 guint8* br[5];
3245
3246                 /*
3247                  * Under Windows:
3248                  * If requested stack size is larger than one page,
3249                  * perform stack-touch operation
3250                  */
3251                 /*
3252                  * Generate stack probe code.
3253                  * Under Windows, it is necessary to allocate one page at a time,
3254                  * "touching" stack after each successful sub-allocation. This is
3255                  * because of the way stack growth is implemented - there is a
3256                  * guard page before the lowest stack page that is currently commited.
3257                  * Stack normally grows sequentially so OS traps access to the
3258                  * guard page and commits more pages when needed.
3259                  */
3260                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3261                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3262
3263                 br[2] = code; /* loop */
3264                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3265                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3266                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3267                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3268                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3269                 amd64_patch (br[3], br[2]);
3270                 amd64_test_reg_reg (code, sreg, sreg);
3271                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3272                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3273
3274                 br[1] = code; x86_jump8 (code, 0);
3275
3276                 amd64_patch (br[0], code);
3277                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3278                 amd64_patch (br[1], code);
3279                 amd64_patch (br[4], code);
3280         }
3281         else
3282                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3283
3284         if (tree->flags & MONO_INST_INIT) {
3285                 int offset = 0;
3286                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3287                         amd64_push_reg (code, AMD64_RAX);
3288                         offset += 8;
3289                 }
3290                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3291                         amd64_push_reg (code, AMD64_RCX);
3292                         offset += 8;
3293                 }
3294                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3295                         amd64_push_reg (code, AMD64_RDI);
3296                         offset += 8;
3297                 }
3298
3299                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3300                 if (sreg != AMD64_RCX)
3301                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3302                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3303
3304                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3305                 if (cfg->param_area)
3306                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3307                 amd64_cld (code);
3308                 amd64_prefix (code, X86_REP_PREFIX);
3309                 amd64_stosl (code);
3310
3311                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3312                         amd64_pop_reg (code, AMD64_RDI);
3313                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3314                         amd64_pop_reg (code, AMD64_RCX);
3315                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3316                         amd64_pop_reg (code, AMD64_RAX);
3317         }
3318         return code;
3319 }
3320
3321 static guint8*
3322 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3323 {
3324         CallInfo *cinfo;
3325         guint32 quad;
3326
3327         /* Move return value to the target register */
3328         /* FIXME: do this in the local reg allocator */
3329         switch (ins->opcode) {
3330         case OP_CALL:
3331         case OP_CALL_REG:
3332         case OP_CALL_MEMBASE:
3333         case OP_LCALL:
3334         case OP_LCALL_REG:
3335         case OP_LCALL_MEMBASE:
3336                 g_assert (ins->dreg == AMD64_RAX);
3337                 break;
3338         case OP_FCALL:
3339         case OP_FCALL_REG:
3340         case OP_FCALL_MEMBASE: {
3341                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3342                 if (rtype->type == MONO_TYPE_R4) {
3343                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3344                 }
3345                 else {
3346                         if (ins->dreg != AMD64_XMM0)
3347                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3348                 }
3349                 break;
3350         }
3351         case OP_RCALL:
3352         case OP_RCALL_REG:
3353         case OP_RCALL_MEMBASE:
3354                 if (ins->dreg != AMD64_XMM0)
3355                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3356                 break;
3357         case OP_VCALL:
3358         case OP_VCALL_REG:
3359         case OP_VCALL_MEMBASE:
3360         case OP_VCALL2:
3361         case OP_VCALL2_REG:
3362         case OP_VCALL2_MEMBASE:
3363                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3364                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3365                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3366
3367                         /* Load the destination address */
3368                         g_assert (loc->opcode == OP_REGOFFSET);
3369                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3370
3371                         for (quad = 0; quad < 2; quad ++) {
3372                                 switch (cinfo->ret.pair_storage [quad]) {
3373                                 case ArgInIReg:
3374                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3375                                         break;
3376                                 case ArgInFloatSSEReg:
3377                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3378                                         break;
3379                                 case ArgInDoubleSSEReg:
3380                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3381                                         break;
3382                                 case ArgNone:
3383                                         break;
3384                                 default:
3385                                         NOT_IMPLEMENTED;
3386                                 }
3387                         }
3388                 }
3389                 break;
3390         }
3391
3392         return code;
3393 }
3394
3395 #endif /* DISABLE_JIT */
3396
3397 #ifdef TARGET_MACH
3398 static int tls_gs_offset;
3399 #endif
3400
3401 gboolean
3402 mono_arch_have_fast_tls (void)
3403 {
3404 #ifdef TARGET_MACH
3405         static gboolean have_fast_tls = FALSE;
3406         static gboolean inited = FALSE;
3407         guint8 *ins;
3408
3409         if (mini_get_debug_options ()->use_fallback_tls)
3410                 return FALSE;
3411
3412         if (inited)
3413                 return have_fast_tls;
3414
3415         ins = (guint8*)pthread_getspecific;
3416
3417         /*
3418          * We're looking for these two instructions:
3419          *
3420          * mov    %gs:[offset](,%rdi,8),%rax
3421          * retq
3422          */
3423         have_fast_tls = ins [0] == 0x65 &&
3424                        ins [1] == 0x48 &&
3425                        ins [2] == 0x8b &&
3426                        ins [3] == 0x04 &&
3427                        ins [4] == 0xfd &&
3428                        ins [6] == 0x00 &&
3429                        ins [7] == 0x00 &&
3430                        ins [8] == 0x00 &&
3431                        ins [9] == 0xc3;
3432
3433         tls_gs_offset = ins[5];
3434
3435         /*
3436          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3437          * For that version we're looking for these instructions:
3438          *
3439          * pushq  %rbp
3440          * movq   %rsp, %rbp
3441          * mov    %gs:[offset](,%rdi,8),%rax
3442          * popq   %rbp
3443          * retq
3444          */
3445         if (!have_fast_tls) {
3446                 have_fast_tls = ins [0] == 0x55 &&
3447                                ins [1] == 0x48 &&
3448                                ins [2] == 0x89 &&
3449                                ins [3] == 0xe5 &&
3450                                ins [4] == 0x65 &&
3451                                ins [5] == 0x48 &&
3452                                ins [6] == 0x8b &&
3453                                ins [7] == 0x04 &&
3454                                ins [8] == 0xfd &&
3455                                ins [10] == 0x00 &&
3456                                ins [11] == 0x00 &&
3457                                ins [12] == 0x00 &&
3458                                ins [13] == 0x5d &&
3459                                ins [14] == 0xc3;
3460
3461                 tls_gs_offset = ins[9];
3462         }
3463         inited = TRUE;
3464
3465         return have_fast_tls;
3466 #elif defined(TARGET_ANDROID)
3467         return FALSE;
3468 #else
3469         if (mini_get_debug_options ()->use_fallback_tls)
3470                 return FALSE;
3471         return TRUE;
3472 #endif
3473 }
3474
3475 int
3476 mono_amd64_get_tls_gs_offset (void)
3477 {
3478 #ifdef TARGET_OSX
3479         return tls_gs_offset;
3480 #else
3481         g_assert_not_reached ();
3482         return -1;
3483 #endif
3484 }
3485
3486 /*
3487  * \param code buffer to store code to
3488  * \param dreg hard register where to place the result
3489  * \param tls_offset offset info
3490  * \return a pointer to the end of the stored code
3491  *
3492  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3493  * the dreg register the item in the thread local storage identified
3494  * by tls_offset.
3495  */
3496 static guint8*
3497 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3498 {
3499 #ifdef TARGET_WIN32
3500         if (tls_offset < 64) {
3501                 x86_prefix (code, X86_GS_PREFIX);
3502                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3503         } else {
3504                 guint8 *buf [16];
3505
3506                 g_assert (tls_offset < 0x440);
3507                 /* Load TEB->TlsExpansionSlots */
3508                 x86_prefix (code, X86_GS_PREFIX);
3509                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3510                 amd64_test_reg_reg (code, dreg, dreg);
3511                 buf [0] = code;
3512                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3513                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3514                 amd64_patch (buf [0], code);
3515         }
3516 #elif defined(TARGET_MACH)
3517         x86_prefix (code, X86_GS_PREFIX);
3518         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3519 #else
3520         if (optimize_for_xen) {
3521                 x86_prefix (code, X86_FS_PREFIX);
3522                 amd64_mov_reg_mem (code, dreg, 0, 8);
3523                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3524         } else {
3525                 x86_prefix (code, X86_FS_PREFIX);
3526                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3527         }
3528 #endif
3529         return code;
3530 }
3531
3532 static guint8*
3533 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3534 {
3535 #ifdef TARGET_WIN32
3536         g_assert_not_reached ();
3537 #elif defined(TARGET_MACH)
3538         x86_prefix (code, X86_GS_PREFIX);
3539         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3540 #else
3541         g_assert (!optimize_for_xen);
3542         x86_prefix (code, X86_FS_PREFIX);
3543         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3544 #endif
3545         return code;
3546 }
3547
3548 /*
3549  * emit_setup_lmf:
3550  *
3551  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3552  */
3553 static guint8*
3554 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3555 {
3556         /*
3557          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3558          */
3559         /*
3560          * sp is saved right before calls but we need to save it here too so
3561          * async stack walks would work.
3562          */
3563         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3564         /* Save rbp */
3565         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3566         if (cfg->arch.omit_fp && cfa_offset != -1)
3567                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3568
3569         /* These can't contain refs */
3570         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3571         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3572         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3573         /* These are handled automatically by the stack marking code */
3574         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3575
3576         return code;
3577 }
3578
3579 #ifdef TARGET_WIN32
3580
3581 #define TEB_LAST_ERROR_OFFSET 0x068
3582
3583 static guint8*
3584 emit_get_last_error (guint8* code, int dreg)
3585 {
3586         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3587         x86_prefix (code, X86_GS_PREFIX);
3588         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3589
3590         return code;
3591 }
3592
3593 #else
3594
3595 static guint8*
3596 emit_get_last_error (guint8* code, int dreg)
3597 {
3598         g_assert_not_reached ();
3599 }
3600
3601 #endif
3602
3603 /* benchmark and set based on cpu */
3604 #define LOOP_ALIGNMENT 8
3605 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3606
3607 #ifndef DISABLE_JIT
3608 void
3609 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3610 {
3611         MonoInst *ins;
3612         MonoCallInst *call;
3613         guint offset;
3614         guint8 *code = cfg->native_code + cfg->code_len;
3615         int max_len;
3616
3617         /* Fix max_offset estimate for each successor bb */
3618         if (cfg->opt & MONO_OPT_BRANCH) {
3619                 int current_offset = cfg->code_len;
3620                 MonoBasicBlock *current_bb;
3621                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3622                         current_bb->max_offset = current_offset;
3623                         current_offset += current_bb->max_length;
3624                 }
3625         }
3626
3627         if (cfg->opt & MONO_OPT_LOOP) {
3628                 int pad, align = LOOP_ALIGNMENT;
3629                 /* set alignment depending on cpu */
3630                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3631                         pad = align - pad;
3632                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3633                         amd64_padding (code, pad);
3634                         cfg->code_len += pad;
3635                         bb->native_offset = cfg->code_len;
3636                 }
3637         }
3638
3639         if (cfg->verbose_level > 2)
3640                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3641
3642         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3643                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3644                 g_assert (!cfg->compile_aot);
3645
3646                 cov->data [bb->dfn].cil_code = bb->cil_code;
3647                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3648                 /* this is not thread save, but good enough */
3649                 amd64_inc_membase (code, AMD64_R11, 0);
3650         }
3651
3652         offset = code - cfg->native_code;
3653
3654         mono_debug_open_block (cfg, bb, offset);
3655
3656     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3657                 x86_breakpoint (code);
3658
3659         MONO_BB_FOR_EACH_INS (bb, ins) {
3660                 offset = code - cfg->native_code;
3661
3662                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3663
3664 #define EXTRA_CODE_SPACE (16)
3665
3666                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3667                         cfg->code_size *= 2;
3668                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3669                         code = cfg->native_code + offset;
3670                         cfg->stat_code_reallocs++;
3671                 }
3672
3673                 if (cfg->debug_info)
3674                         mono_debug_record_line_number (cfg, ins, offset);
3675
3676                 switch (ins->opcode) {
3677                 case OP_BIGMUL:
3678                         amd64_mul_reg (code, ins->sreg2, TRUE);
3679                         break;
3680                 case OP_BIGMUL_UN:
3681                         amd64_mul_reg (code, ins->sreg2, FALSE);
3682                         break;
3683                 case OP_X86_SETEQ_MEMBASE:
3684                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3685                         break;
3686                 case OP_STOREI1_MEMBASE_IMM:
3687                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3688                         break;
3689                 case OP_STOREI2_MEMBASE_IMM:
3690                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3691                         break;
3692                 case OP_STOREI4_MEMBASE_IMM:
3693                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3694                         break;
3695                 case OP_STOREI1_MEMBASE_REG:
3696                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3697                         break;
3698                 case OP_STOREI2_MEMBASE_REG:
3699                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3700                         break;
3701                 /* In AMD64 NaCl, pointers are 4 bytes, */
3702                 /*  so STORE_* != STOREI8_*. Likewise below. */
3703                 case OP_STORE_MEMBASE_REG:
3704                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3705                         break;
3706                 case OP_STOREI8_MEMBASE_REG:
3707                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3708                         break;
3709                 case OP_STOREI4_MEMBASE_REG:
3710                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3711                         break;
3712                 case OP_STORE_MEMBASE_IMM:
3713                         /* In NaCl, this could be a PCONST type, which could */
3714                         /* mean a pointer type was copied directly into the  */
3715                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3716                         /* the value would be 0x00000000FFFFFFFF which is    */
3717                         /* not proper for an imm32 unless you cast it.       */
3718                         g_assert (amd64_is_imm32 (ins->inst_imm));
3719                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3720                         break;
3721                 case OP_STOREI8_MEMBASE_IMM:
3722                         g_assert (amd64_is_imm32 (ins->inst_imm));
3723                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3724                         break;
3725                 case OP_LOAD_MEM:
3726 #ifdef __mono_ilp32__
3727                         /* In ILP32, pointers are 4 bytes, so separate these */
3728                         /* cases, use literal 8 below where we really want 8 */
3729                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3730                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3731                         break;
3732 #endif
3733                 case OP_LOADI8_MEM:
3734                         // FIXME: Decompose this earlier
3735                         if (amd64_use_imm32 (ins->inst_imm))
3736                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3737                         else {
3738                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3739                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3740                         }
3741                         break;
3742                 case OP_LOADI4_MEM:
3743                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3744                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3745                         break;
3746                 case OP_LOADU4_MEM:
3747                         // FIXME: Decompose this earlier
3748                         if (amd64_use_imm32 (ins->inst_imm))
3749                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3750                         else {
3751                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3752                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3753                         }
3754                         break;
3755                 case OP_LOADU1_MEM:
3756                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3757                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3758                         break;
3759                 case OP_LOADU2_MEM:
3760                         /* For NaCl, pointers are 4 bytes, so separate these */
3761                         /* cases, use literal 8 below where we really want 8 */
3762                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3763                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3764                         break;
3765                 case OP_LOAD_MEMBASE:
3766                         g_assert (amd64_is_imm32 (ins->inst_offset));
3767                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3768                         break;
3769                 case OP_LOADI8_MEMBASE:
3770                         /* Use literal 8 instead of sizeof pointer or */
3771                         /* register, we really want 8 for this opcode */
3772                         g_assert (amd64_is_imm32 (ins->inst_offset));
3773                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3774                         break;
3775                 case OP_LOADI4_MEMBASE:
3776                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3777                         break;
3778                 case OP_LOADU4_MEMBASE:
3779                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3780                         break;
3781                 case OP_LOADU1_MEMBASE:
3782                         /* The cpu zero extends the result into 64 bits */
3783                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3784                         break;
3785                 case OP_LOADI1_MEMBASE:
3786                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3787                         break;
3788                 case OP_LOADU2_MEMBASE:
3789                         /* The cpu zero extends the result into 64 bits */
3790                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3791                         break;
3792                 case OP_LOADI2_MEMBASE:
3793                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3794                         break;
3795                 case OP_AMD64_LOADI8_MEMINDEX:
3796                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3797                         break;
3798                 case OP_LCONV_TO_I1:
3799                 case OP_ICONV_TO_I1:
3800                 case OP_SEXT_I1:
3801                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3802                         break;
3803                 case OP_LCONV_TO_I2:
3804                 case OP_ICONV_TO_I2:
3805                 case OP_SEXT_I2:
3806                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3807                         break;
3808                 case OP_LCONV_TO_U1:
3809                 case OP_ICONV_TO_U1:
3810                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3811                         break;
3812                 case OP_LCONV_TO_U2:
3813                 case OP_ICONV_TO_U2:
3814                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3815                         break;
3816                 case OP_ZEXT_I4:
3817                         /* Clean out the upper word */
3818                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3819                         break;
3820                 case OP_SEXT_I4:
3821                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3822                         break;
3823                 case OP_COMPARE:
3824                 case OP_LCOMPARE:
3825                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3826                         break;
3827                 case OP_COMPARE_IMM:
3828 #if defined(__mono_ilp32__)
3829                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3830                         g_assert (amd64_is_imm32 (ins->inst_imm));
3831                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3832                         break;
3833 #endif
3834                 case OP_LCOMPARE_IMM:
3835                         g_assert (amd64_is_imm32 (ins->inst_imm));
3836                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3837                         break;
3838                 case OP_X86_COMPARE_REG_MEMBASE:
3839                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3840                         break;
3841                 case OP_X86_TEST_NULL:
3842                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3843                         break;
3844                 case OP_AMD64_TEST_NULL:
3845                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3846                         break;
3847
3848                 case OP_X86_ADD_REG_MEMBASE:
3849                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3850                         break;
3851                 case OP_X86_SUB_REG_MEMBASE:
3852                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3853                         break;
3854                 case OP_X86_AND_REG_MEMBASE:
3855                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3856                         break;
3857                 case OP_X86_OR_REG_MEMBASE:
3858                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3859                         break;
3860                 case OP_X86_XOR_REG_MEMBASE:
3861                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3862                         break;
3863
3864                 case OP_X86_ADD_MEMBASE_IMM:
3865                         /* FIXME: Make a 64 version too */
3866                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3867                         break;
3868                 case OP_X86_SUB_MEMBASE_IMM:
3869                         g_assert (amd64_is_imm32 (ins->inst_imm));
3870                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3871                         break;
3872                 case OP_X86_AND_MEMBASE_IMM:
3873                         g_assert (amd64_is_imm32 (ins->inst_imm));
3874                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3875                         break;
3876                 case OP_X86_OR_MEMBASE_IMM:
3877                         g_assert (amd64_is_imm32 (ins->inst_imm));
3878                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3879                         break;
3880                 case OP_X86_XOR_MEMBASE_IMM:
3881                         g_assert (amd64_is_imm32 (ins->inst_imm));
3882                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3883                         break;
3884                 case OP_X86_ADD_MEMBASE_REG:
3885                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3886                         break;
3887                 case OP_X86_SUB_MEMBASE_REG:
3888                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3889                         break;
3890                 case OP_X86_AND_MEMBASE_REG:
3891                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3892                         break;
3893                 case OP_X86_OR_MEMBASE_REG:
3894                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3895                         break;
3896                 case OP_X86_XOR_MEMBASE_REG:
3897                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3898                         break;
3899                 case OP_X86_INC_MEMBASE:
3900                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3901                         break;
3902                 case OP_X86_INC_REG:
3903                         amd64_inc_reg_size (code, ins->dreg, 4);
3904                         break;
3905                 case OP_X86_DEC_MEMBASE:
3906                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3907                         break;
3908                 case OP_X86_DEC_REG:
3909                         amd64_dec_reg_size (code, ins->dreg, 4);
3910                         break;
3911                 case OP_X86_MUL_REG_MEMBASE:
3912                 case OP_X86_MUL_MEMBASE_REG:
3913                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3914                         break;
3915                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3916                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3917                         break;
3918                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3919                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3920                         break;
3921                 case OP_AMD64_COMPARE_MEMBASE_REG:
3922                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3923                         break;
3924                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3925                         g_assert (amd64_is_imm32 (ins->inst_imm));
3926                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3927                         break;
3928                 case OP_X86_COMPARE_MEMBASE8_IMM:
3929                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3930                         break;
3931                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3933                         break;
3934                 case OP_AMD64_COMPARE_REG_MEMBASE:
3935                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3936                         break;
3937
3938                 case OP_AMD64_ADD_REG_MEMBASE:
3939                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3940                         break;
3941                 case OP_AMD64_SUB_REG_MEMBASE:
3942                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3943                         break;
3944                 case OP_AMD64_AND_REG_MEMBASE:
3945                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3946                         break;
3947                 case OP_AMD64_OR_REG_MEMBASE:
3948                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3949                         break;
3950                 case OP_AMD64_XOR_REG_MEMBASE:
3951                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3952                         break;
3953
3954                 case OP_AMD64_ADD_MEMBASE_REG:
3955                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3956                         break;
3957                 case OP_AMD64_SUB_MEMBASE_REG:
3958                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3959                         break;
3960                 case OP_AMD64_AND_MEMBASE_REG:
3961                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3962                         break;
3963                 case OP_AMD64_OR_MEMBASE_REG:
3964                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3965                         break;
3966                 case OP_AMD64_XOR_MEMBASE_REG:
3967                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3968                         break;
3969
3970                 case OP_AMD64_ADD_MEMBASE_IMM:
3971                         g_assert (amd64_is_imm32 (ins->inst_imm));
3972                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3973                         break;
3974                 case OP_AMD64_SUB_MEMBASE_IMM:
3975                         g_assert (amd64_is_imm32 (ins->inst_imm));
3976                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3977                         break;
3978                 case OP_AMD64_AND_MEMBASE_IMM:
3979                         g_assert (amd64_is_imm32 (ins->inst_imm));
3980                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3981                         break;
3982                 case OP_AMD64_OR_MEMBASE_IMM:
3983                         g_assert (amd64_is_imm32 (ins->inst_imm));
3984                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3985                         break;
3986                 case OP_AMD64_XOR_MEMBASE_IMM:
3987                         g_assert (amd64_is_imm32 (ins->inst_imm));
3988                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3989                         break;
3990
3991                 case OP_BREAK:
3992                         amd64_breakpoint (code);
3993                         break;
3994                 case OP_RELAXED_NOP:
3995                         x86_prefix (code, X86_REP_PREFIX);
3996                         x86_nop (code);
3997                         break;
3998                 case OP_HARD_NOP:
3999                         x86_nop (code);
4000                         break;
4001                 case OP_NOP:
4002                 case OP_DUMMY_USE:
4003                 case OP_DUMMY_STORE:
4004                 case OP_DUMMY_ICONST:
4005                 case OP_DUMMY_R8CONST:
4006                 case OP_NOT_REACHED:
4007                 case OP_NOT_NULL:
4008                         break;
4009                 case OP_IL_SEQ_POINT:
4010                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4011                         break;
4012                 case OP_SEQ_POINT: {
4013                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4014                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4015                                 guint8 *label;
4016
4017                                 /* Load ss_tramp_var */
4018                                 /* This is equal to &ss_trampoline */
4019                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4020                                 /* Load the trampoline address */
4021                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4022                                 /* Call it if it is non-null */
4023                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4024                                 label = code;
4025                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4026                                 amd64_call_reg (code, AMD64_R11);
4027                                 amd64_patch (label, code);
4028                         }
4029
4030                         /*
4031                          * This is the address which is saved in seq points,
4032                          */
4033                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4034
4035                         if (cfg->compile_aot) {
4036                                 guint32 offset = code - cfg->native_code;
4037                                 guint32 val;
4038                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4039                                 guint8 *label;
4040
4041                                 /* Load info var */
4042                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4043                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4044                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4045                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4046                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4047                                 label = code;
4048                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4049                                 /* Call the trampoline */
4050                                 amd64_call_reg (code, AMD64_R11);
4051                                 amd64_patch (label, code);
4052                         } else {
4053                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4054                                 guint8 *label;
4055
4056                                 /*
4057                                  * Emit a test+branch against a constant, the constant will be overwritten
4058                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4059                                  */
4060                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4061                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4062                                 label = code;
4063                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4064
4065                                 g_assert (var);
4066                                 g_assert (var->opcode == OP_REGOFFSET);
4067                                 /* Load bp_tramp_var */
4068                                 /* This is equal to &bp_trampoline */
4069                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4070                                 /* Call the trampoline */
4071                                 amd64_call_membase (code, AMD64_R11, 0);
4072                                 amd64_patch (label, code);
4073                         }
4074                         /*
4075                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4076                          * to another IL offset.
4077                          */
4078                         x86_nop (code);
4079                         break;
4080                 }
4081                 case OP_ADDCC:
4082                 case OP_LADDCC:
4083                 case OP_LADD:
4084                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4085                         break;
4086                 case OP_ADC:
4087                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4088                         break;
4089                 case OP_ADD_IMM:
4090                 case OP_LADD_IMM:
4091                         g_assert (amd64_is_imm32 (ins->inst_imm));
4092                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4093                         break;
4094                 case OP_ADC_IMM:
4095                         g_assert (amd64_is_imm32 (ins->inst_imm));
4096                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4097                         break;
4098                 case OP_SUBCC:
4099                 case OP_LSUBCC:
4100                 case OP_LSUB:
4101                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4102                         break;
4103                 case OP_SBB:
4104                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4105                         break;
4106                 case OP_SUB_IMM:
4107                 case OP_LSUB_IMM:
4108                         g_assert (amd64_is_imm32 (ins->inst_imm));
4109                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4110                         break;
4111                 case OP_SBB_IMM:
4112                         g_assert (amd64_is_imm32 (ins->inst_imm));
4113                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4114                         break;
4115                 case OP_LAND:
4116                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4117                         break;
4118                 case OP_AND_IMM:
4119                 case OP_LAND_IMM:
4120                         g_assert (amd64_is_imm32 (ins->inst_imm));
4121                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4122                         break;
4123                 case OP_LMUL:
4124                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4125                         break;
4126                 case OP_MUL_IMM:
4127                 case OP_LMUL_IMM:
4128                 case OP_IMUL_IMM: {
4129                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4130
4131                         switch (ins->inst_imm) {
4132                         case 2:
4133                                 /* MOV r1, r2 */
4134                                 /* ADD r1, r1 */
4135                                 if (ins->dreg != ins->sreg1)
4136                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4137                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4138                                 break;
4139                         case 3:
4140                                 /* LEA r1, [r2 + r2*2] */
4141                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4142                                 break;
4143                         case 5:
4144                                 /* LEA r1, [r2 + r2*4] */
4145                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4146                                 break;
4147                         case 6:
4148                                 /* LEA r1, [r2 + r2*2] */
4149                                 /* ADD r1, r1          */
4150                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4151                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4152                                 break;
4153                         case 9:
4154                                 /* LEA r1, [r2 + r2*8] */
4155                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4156                                 break;
4157                         case 10:
4158                                 /* LEA r1, [r2 + r2*4] */
4159                                 /* ADD r1, r1          */
4160                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4161                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4162                                 break;
4163                         case 12:
4164                                 /* LEA r1, [r2 + r2*2] */
4165                                 /* SHL r1, 2           */
4166                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4167                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4168                                 break;
4169                         case 25:
4170                                 /* LEA r1, [r2 + r2*4] */
4171                                 /* LEA r1, [r1 + r1*4] */
4172                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4173                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4174                                 break;
4175                         case 100:
4176                                 /* LEA r1, [r2 + r2*4] */
4177                                 /* SHL r1, 2           */
4178                                 /* LEA r1, [r1 + r1*4] */
4179                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4180                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4181                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4182                                 break;
4183                         default:
4184                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4185                                 break;
4186                         }
4187                         break;
4188                 }
4189                 case OP_LDIV:
4190                 case OP_LREM:
4191                         /* Regalloc magic makes the div/rem cases the same */
4192                         if (ins->sreg2 == AMD64_RDX) {
4193                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4194                                 amd64_cdq (code);
4195                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4196                         } else {
4197                                 amd64_cdq (code);
4198                                 amd64_div_reg (code, ins->sreg2, TRUE);
4199                         }
4200                         break;
4201                 case OP_LDIV_UN:
4202                 case OP_LREM_UN:
4203                         if (ins->sreg2 == AMD64_RDX) {
4204                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4205                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4206                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4207                         } else {
4208                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4209                                 amd64_div_reg (code, ins->sreg2, FALSE);
4210                         }
4211                         break;
4212                 case OP_IDIV:
4213                 case OP_IREM:
4214                         if (ins->sreg2 == AMD64_RDX) {
4215                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4216                                 amd64_cdq_size (code, 4);
4217                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4218                         } else {
4219                                 amd64_cdq_size (code, 4);
4220                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4221                         }
4222                         break;
4223                 case OP_IDIV_UN:
4224                 case OP_IREM_UN:
4225                         if (ins->sreg2 == AMD64_RDX) {
4226                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4227                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4228                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4229                         } else {
4230                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4231                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4232                         }
4233                         break;
4234                 case OP_LMUL_OVF:
4235                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4236                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4237                         break;
4238                 case OP_LOR:
4239                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4240                         break;
4241                 case OP_OR_IMM:
4242                 case OP_LOR_IMM:
4243                         g_assert (amd64_is_imm32 (ins->inst_imm));
4244                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4245                         break;
4246                 case OP_LXOR:
4247                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4248                         break;
4249                 case OP_XOR_IMM:
4250                 case OP_LXOR_IMM:
4251                         g_assert (amd64_is_imm32 (ins->inst_imm));
4252                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4253                         break;
4254                 case OP_LSHL:
4255                         g_assert (ins->sreg2 == AMD64_RCX);
4256                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4257                         break;
4258                 case OP_LSHR:
4259                         g_assert (ins->sreg2 == AMD64_RCX);
4260                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4261                         break;
4262                 case OP_SHR_IMM:
4263                 case OP_LSHR_IMM:
4264                         g_assert (amd64_is_imm32 (ins->inst_imm));
4265                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4266                         break;
4267                 case OP_SHR_UN_IMM:
4268                         g_assert (amd64_is_imm32 (ins->inst_imm));
4269                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4270                         break;
4271                 case OP_LSHR_UN_IMM:
4272                         g_assert (amd64_is_imm32 (ins->inst_imm));
4273                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4274                         break;
4275                 case OP_LSHR_UN:
4276                         g_assert (ins->sreg2 == AMD64_RCX);
4277                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4278                         break;
4279                 case OP_SHL_IMM:
4280                 case OP_LSHL_IMM:
4281                         g_assert (amd64_is_imm32 (ins->inst_imm));
4282                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4283                         break;
4284
4285                 case OP_IADDCC:
4286                 case OP_IADD:
4287                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4288                         break;
4289                 case OP_IADC:
4290                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4291                         break;
4292                 case OP_IADD_IMM:
4293                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4294                         break;
4295                 case OP_IADC_IMM:
4296                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4297                         break;
4298                 case OP_ISUBCC:
4299                 case OP_ISUB:
4300                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4301                         break;
4302                 case OP_ISBB:
4303                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4304                         break;
4305                 case OP_ISUB_IMM:
4306                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4307                         break;
4308                 case OP_ISBB_IMM:
4309                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4310                         break;
4311                 case OP_IAND:
4312                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4313                         break;
4314                 case OP_IAND_IMM:
4315                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4316                         break;
4317                 case OP_IOR:
4318                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4319                         break;
4320                 case OP_IOR_IMM:
4321                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4322                         break;
4323                 case OP_IXOR:
4324                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4325                         break;
4326                 case OP_IXOR_IMM:
4327                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4328                         break;
4329                 case OP_INEG:
4330                         amd64_neg_reg_size (code, ins->sreg1, 4);
4331                         break;
4332                 case OP_INOT:
4333                         amd64_not_reg_size (code, ins->sreg1, 4);
4334                         break;
4335                 case OP_ISHL:
4336                         g_assert (ins->sreg2 == AMD64_RCX);
4337                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4338                         break;
4339                 case OP_ISHR:
4340                         g_assert (ins->sreg2 == AMD64_RCX);
4341                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4342                         break;
4343                 case OP_ISHR_IMM:
4344                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4345                         break;
4346                 case OP_ISHR_UN_IMM:
4347                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4348                         break;
4349                 case OP_ISHR_UN:
4350                         g_assert (ins->sreg2 == AMD64_RCX);
4351                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4352                         break;
4353                 case OP_ISHL_IMM:
4354                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4355                         break;
4356                 case OP_IMUL:
4357                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4358                         break;
4359                 case OP_IMUL_OVF:
4360                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4361                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4362                         break;
4363                 case OP_IMUL_OVF_UN:
4364                 case OP_LMUL_OVF_UN: {
4365                         /* the mul operation and the exception check should most likely be split */
4366                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4367                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4368                         /*g_assert (ins->sreg2 == X86_EAX);
4369                         g_assert (ins->dreg == X86_EAX);*/
4370                         if (ins->sreg2 == X86_EAX) {
4371                                 non_eax_reg = ins->sreg1;
4372                         } else if (ins->sreg1 == X86_EAX) {
4373                                 non_eax_reg = ins->sreg2;
4374                         } else {
4375                                 /* no need to save since we're going to store to it anyway */
4376                                 if (ins->dreg != X86_EAX) {
4377                                         saved_eax = TRUE;
4378                                         amd64_push_reg (code, X86_EAX);
4379                                 }
4380                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4381                                 non_eax_reg = ins->sreg2;
4382                         }
4383                         if (ins->dreg == X86_EDX) {
4384                                 if (!saved_eax) {
4385                                         saved_eax = TRUE;
4386                                         amd64_push_reg (code, X86_EAX);
4387                                 }
4388                         } else {
4389                                 saved_edx = TRUE;
4390                                 amd64_push_reg (code, X86_EDX);
4391                         }
4392                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4393                         /* save before the check since pop and mov don't change the flags */
4394                         if (ins->dreg != X86_EAX)
4395                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4396                         if (saved_edx)
4397                                 amd64_pop_reg (code, X86_EDX);
4398                         if (saved_eax)
4399                                 amd64_pop_reg (code, X86_EAX);
4400                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4401                         break;
4402                 }
4403                 case OP_ICOMPARE:
4404                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4405                         break;
4406                 case OP_ICOMPARE_IMM:
4407                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4408                         break;
4409                 case OP_IBEQ:
4410                 case OP_IBLT:
4411                 case OP_IBGT:
4412                 case OP_IBGE:
4413                 case OP_IBLE:
4414                 case OP_LBEQ:
4415                 case OP_LBLT:
4416                 case OP_LBGT:
4417                 case OP_LBGE:
4418                 case OP_LBLE:
4419                 case OP_IBNE_UN:
4420                 case OP_IBLT_UN:
4421                 case OP_IBGT_UN:
4422                 case OP_IBGE_UN:
4423                 case OP_IBLE_UN:
4424                 case OP_LBNE_UN:
4425                 case OP_LBLT_UN:
4426                 case OP_LBGT_UN:
4427                 case OP_LBGE_UN:
4428                 case OP_LBLE_UN:
4429                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4430                         break;
4431
4432                 case OP_CMOV_IEQ:
4433                 case OP_CMOV_IGE:
4434                 case OP_CMOV_IGT:
4435                 case OP_CMOV_ILE:
4436                 case OP_CMOV_ILT:
4437                 case OP_CMOV_INE_UN:
4438                 case OP_CMOV_IGE_UN:
4439                 case OP_CMOV_IGT_UN:
4440                 case OP_CMOV_ILE_UN:
4441                 case OP_CMOV_ILT_UN:
4442                 case OP_CMOV_LEQ:
4443                 case OP_CMOV_LGE:
4444                 case OP_CMOV_LGT:
4445                 case OP_CMOV_LLE:
4446                 case OP_CMOV_LLT:
4447                 case OP_CMOV_LNE_UN:
4448                 case OP_CMOV_LGE_UN:
4449                 case OP_CMOV_LGT_UN:
4450                 case OP_CMOV_LLE_UN:
4451                 case OP_CMOV_LLT_UN:
4452                         g_assert (ins->dreg == ins->sreg1);
4453                         /* This needs to operate on 64 bit values */
4454                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4455                         break;
4456
4457                 case OP_LNOT:
4458                         amd64_not_reg (code, ins->sreg1);
4459                         break;
4460                 case OP_LNEG:
4461                         amd64_neg_reg (code, ins->sreg1);
4462                         break;
4463
4464                 case OP_ICONST:
4465                 case OP_I8CONST:
4466                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4467                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4468                         else
4469                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4470                         break;
4471                 case OP_AOTCONST:
4472                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4473                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4474                         break;
4475                 case OP_JUMP_TABLE:
4476                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4477                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4478                         break;
4479                 case OP_MOVE:
4480                         if (ins->dreg != ins->sreg1)
4481                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4482                         break;
4483                 case OP_AMD64_SET_XMMREG_R4: {
4484                         if (cfg->r4fp) {
4485                                 if (ins->dreg != ins->sreg1)
4486                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4487                         } else {
4488                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4489                         }
4490                         break;
4491                 }
4492                 case OP_AMD64_SET_XMMREG_R8: {
4493                         if (ins->dreg != ins->sreg1)
4494                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4495                         break;
4496                 }
4497                 case OP_TAILCALL: {
4498                         MonoCallInst *call = (MonoCallInst*)ins;
4499                         int i, save_area_offset;
4500
4501                         g_assert (!cfg->method->save_lmf);
4502
4503                         /* Restore callee saved registers */
4504                         save_area_offset = cfg->arch.reg_save_area_offset;
4505                         for (i = 0; i < AMD64_NREG; ++i)
4506                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4507                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4508                                         save_area_offset += 8;
4509                                 }
4510
4511                         if (cfg->arch.omit_fp) {
4512                                 if (cfg->arch.stack_alloc_size)
4513                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4514                                 // FIXME:
4515                                 if (call->stack_usage)
4516                                         NOT_IMPLEMENTED;
4517                         } else {
4518                                 /* Copy arguments on the stack to our argument area */
4519                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4520                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4521                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4522                                 }
4523
4524 #ifdef TARGET_WIN32
4525                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4526                                 amd64_pop_reg (code, AMD64_RBP);
4527                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4528 #else
4529                                 amd64_leave (code);
4530 #endif
4531                         }
4532
4533                         offset = code - cfg->native_code;
4534                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4535                         if (cfg->compile_aot)
4536                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4537                         else
4538                                 amd64_set_reg_template (code, AMD64_R11);
4539                         amd64_jump_reg (code, AMD64_R11);
4540                         ins->flags |= MONO_INST_GC_CALLSITE;
4541                         ins->backend.pc_offset = code - cfg->native_code;
4542                         break;
4543                 }
4544                 case OP_CHECK_THIS:
4545                         /* ensure ins->sreg1 is not NULL */
4546                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4547                         break;
4548                 case OP_ARGLIST: {
4549                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4550                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4551                         break;
4552                 }
4553                 case OP_CALL:
4554                 case OP_FCALL:
4555                 case OP_RCALL:
4556                 case OP_LCALL:
4557                 case OP_VCALL:
4558                 case OP_VCALL2:
4559                 case OP_VOIDCALL:
4560                         call = (MonoCallInst*)ins;
4561                         /*
4562                          * The AMD64 ABI forces callers to know about varargs.
4563                          */
4564                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4565                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4566                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4567                                 /*
4568                                  * Since the unmanaged calling convention doesn't contain a
4569                                  * 'vararg' entry, we have to treat every pinvoke call as a
4570                                  * potential vararg call.
4571                                  */
4572                                 guint32 nregs, i;
4573                                 nregs = 0;
4574                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4575                                         if (call->used_fregs & (1 << i))
4576                                                 nregs ++;
4577                                 if (!nregs)
4578                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4579                                 else
4580                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4581                         }
4582
4583                         if (ins->flags & MONO_INST_HAS_METHOD)
4584                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4585                         else
4586                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4587                         ins->flags |= MONO_INST_GC_CALLSITE;
4588                         ins->backend.pc_offset = code - cfg->native_code;
4589                         code = emit_move_return_value (cfg, ins, code);
4590                         break;
4591                 case OP_FCALL_REG:
4592                 case OP_RCALL_REG:
4593                 case OP_LCALL_REG:
4594                 case OP_VCALL_REG:
4595                 case OP_VCALL2_REG:
4596                 case OP_VOIDCALL_REG:
4597                 case OP_CALL_REG:
4598                         call = (MonoCallInst*)ins;
4599
4600                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4601                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4602                                 ins->sreg1 = AMD64_R11;
4603                         }
4604
4605                         /*
4606                          * The AMD64 ABI forces callers to know about varargs.
4607                          */
4608                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4609                                 if (ins->sreg1 == AMD64_RAX) {
4610                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4611                                         ins->sreg1 = AMD64_R11;
4612                                 }
4613                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4614                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4615                                 /*
4616                                  * Since the unmanaged calling convention doesn't contain a
4617                                  * 'vararg' entry, we have to treat every pinvoke call as a
4618                                  * potential vararg call.
4619                                  */
4620                                 guint32 nregs, i;
4621                                 nregs = 0;
4622                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4623                                         if (call->used_fregs & (1 << i))
4624                                                 nregs ++;
4625                                 if (ins->sreg1 == AMD64_RAX) {
4626                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4627                                         ins->sreg1 = AMD64_R11;
4628                                 }
4629                                 if (!nregs)
4630                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4631                                 else
4632                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4633                         }
4634
4635                         amd64_call_reg (code, ins->sreg1);
4636                         ins->flags |= MONO_INST_GC_CALLSITE;
4637                         ins->backend.pc_offset = code - cfg->native_code;
4638                         code = emit_move_return_value (cfg, ins, code);
4639                         break;
4640                 case OP_FCALL_MEMBASE:
4641                 case OP_RCALL_MEMBASE:
4642                 case OP_LCALL_MEMBASE:
4643                 case OP_VCALL_MEMBASE:
4644                 case OP_VCALL2_MEMBASE:
4645                 case OP_VOIDCALL_MEMBASE:
4646                 case OP_CALL_MEMBASE:
4647                         call = (MonoCallInst*)ins;
4648
4649                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4650                         ins->flags |= MONO_INST_GC_CALLSITE;
4651                         ins->backend.pc_offset = code - cfg->native_code;
4652                         code = emit_move_return_value (cfg, ins, code);
4653                         break;
4654                 case OP_DYN_CALL: {
4655                         int i;
4656                         MonoInst *var = cfg->dyn_call_var;
4657                         guint8 *label;
4658
4659                         g_assert (var->opcode == OP_REGOFFSET);
4660
4661                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4662                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4663                         /* r10 = ftn */
4664                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4665
4666                         /* Save args buffer */
4667                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4668
4669                         /* Set fp arg regs */
4670                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4671                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4672                         label = code;
4673                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4674                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4675                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4676                         amd64_patch (label, code);
4677
4678                         /* Set stack args */
4679                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4680                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4681                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4682                         }
4683
4684                         /* Set argument registers */
4685                         for (i = 0; i < PARAM_REGS; ++i)
4686                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4687
4688                         /* Make the call */
4689                         amd64_call_reg (code, AMD64_R10);
4690
4691                         ins->flags |= MONO_INST_GC_CALLSITE;
4692                         ins->backend.pc_offset = code - cfg->native_code;
4693
4694                         /* Save result */
4695                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4696                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4697                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4698                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4699                         break;
4700                 }
4701                 case OP_AMD64_SAVE_SP_TO_LMF: {
4702                         MonoInst *lmf_var = cfg->lmf_var;
4703                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4704                         break;
4705                 }
4706                 case OP_X86_PUSH:
4707                         g_assert_not_reached ();
4708                         amd64_push_reg (code, ins->sreg1);
4709                         break;
4710                 case OP_X86_PUSH_IMM:
4711                         g_assert_not_reached ();
4712                         g_assert (amd64_is_imm32 (ins->inst_imm));
4713                         amd64_push_imm (code, ins->inst_imm);
4714                         break;
4715                 case OP_X86_PUSH_MEMBASE:
4716                         g_assert_not_reached ();
4717                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4718                         break;
4719                 case OP_X86_PUSH_OBJ: {
4720                         int size = ALIGN_TO (ins->inst_imm, 8);
4721
4722                         g_assert_not_reached ();
4723
4724                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4725                         amd64_push_reg (code, AMD64_RDI);
4726                         amd64_push_reg (code, AMD64_RSI);
4727                         amd64_push_reg (code, AMD64_RCX);
4728                         if (ins->inst_offset)
4729                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4730                         else
4731                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4732                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4733                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4734                         amd64_cld (code);
4735                         amd64_prefix (code, X86_REP_PREFIX);
4736                         amd64_movsd (code);
4737                         amd64_pop_reg (code, AMD64_RCX);
4738                         amd64_pop_reg (code, AMD64_RSI);
4739                         amd64_pop_reg (code, AMD64_RDI);
4740                         break;
4741                 }
4742                 case OP_GENERIC_CLASS_INIT: {
4743                         guint8 *jump;
4744
4745                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4746
4747                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4748                         jump = code;
4749                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4750
4751                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4752                         ins->flags |= MONO_INST_GC_CALLSITE;
4753                         ins->backend.pc_offset = code - cfg->native_code;
4754
4755                         x86_patch (jump, code);
4756                         break;
4757                 }
4758
4759                 case OP_X86_LEA:
4760                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4761                         break;
4762                 case OP_X86_LEA_MEMBASE:
4763                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4764                         break;
4765                 case OP_X86_XCHG:
4766                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4767                         break;
4768                 case OP_LOCALLOC:
4769                         /* keep alignment */
4770                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4771                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4772                         code = mono_emit_stack_alloc (cfg, code, ins);
4773                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4774                         if (cfg->param_area)
4775                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4776                         break;
4777                 case OP_LOCALLOC_IMM: {
4778                         guint32 size = ins->inst_imm;
4779                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4780
4781                         if (ins->flags & MONO_INST_INIT) {
4782                                 if (size < 64) {
4783                                         int i;
4784
4785                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4786                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4787
4788                                         for (i = 0; i < size; i += 8)
4789                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4790                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4791                                 } else {
4792                                         amd64_mov_reg_imm (code, ins->dreg, size);
4793                                         ins->sreg1 = ins->dreg;
4794
4795                                         code = mono_emit_stack_alloc (cfg, code, ins);
4796                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4797                                 }
4798                         } else {
4799                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4800                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4801                         }
4802                         if (cfg->param_area)
4803                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4804                         break;
4805                 }
4806                 case OP_THROW: {
4807                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4808                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4809                                              (gpointer)"mono_arch_throw_exception", FALSE);
4810                         ins->flags |= MONO_INST_GC_CALLSITE;
4811                         ins->backend.pc_offset = code - cfg->native_code;
4812                         break;
4813                 }
4814                 case OP_RETHROW: {
4815                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4816                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4817                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4818                         ins->flags |= MONO_INST_GC_CALLSITE;
4819                         ins->backend.pc_offset = code - cfg->native_code;
4820                         break;
4821                 }
4822                 case OP_CALL_HANDLER:
4823                         /* Align stack */
4824                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4825                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4826                         amd64_call_imm (code, 0);
4827                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4828                         /* Restore stack alignment */
4829                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4830                         break;
4831                 case OP_START_HANDLER: {
4832                         /* Even though we're saving RSP, use sizeof */
4833                         /* gpointer because spvar is of type IntPtr */
4834                         /* see: mono_create_spvar_for_region */
4835                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4836                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4837
4838                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4839                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4840                                 cfg->param_area) {
4841                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4842                         }
4843                         break;
4844                 }
4845                 case OP_ENDFINALLY: {
4846                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4847                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4848                         amd64_ret (code);
4849                         break;
4850                 }
4851                 case OP_ENDFILTER: {
4852                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4853                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4854                         /* The local allocator will put the result into RAX */
4855                         amd64_ret (code);
4856                         break;
4857                 }
4858                 case OP_GET_EX_OBJ:
4859                         if (ins->dreg != AMD64_RAX)
4860                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4861                         break;
4862                 case OP_LABEL:
4863                         ins->inst_c0 = code - cfg->native_code;
4864                         break;
4865                 case OP_BR:
4866                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4867                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4868                         //break;
4869                                 if (ins->inst_target_bb->native_offset) {
4870                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4871                                 } else {
4872                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4873                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4874                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4875                                                 x86_jump8 (code, 0);
4876                                         else
4877                                                 x86_jump32 (code, 0);
4878                         }
4879                         break;
4880                 case OP_BR_REG:
4881                         amd64_jump_reg (code, ins->sreg1);
4882                         break;
4883                 case OP_ICNEQ:
4884                 case OP_ICGE:
4885                 case OP_ICLE:
4886                 case OP_ICGE_UN:
4887                 case OP_ICLE_UN:
4888
4889                 case OP_CEQ:
4890                 case OP_LCEQ:
4891                 case OP_ICEQ:
4892                 case OP_CLT:
4893                 case OP_LCLT:
4894                 case OP_ICLT:
4895                 case OP_CGT:
4896                 case OP_ICGT:
4897                 case OP_LCGT:
4898                 case OP_CLT_UN:
4899                 case OP_LCLT_UN:
4900                 case OP_ICLT_UN:
4901                 case OP_CGT_UN:
4902                 case OP_LCGT_UN:
4903                 case OP_ICGT_UN:
4904                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4905                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4906                         break;
4907                 case OP_COND_EXC_EQ:
4908                 case OP_COND_EXC_NE_UN:
4909                 case OP_COND_EXC_LT:
4910                 case OP_COND_EXC_LT_UN:
4911                 case OP_COND_EXC_GT:
4912                 case OP_COND_EXC_GT_UN:
4913                 case OP_COND_EXC_GE:
4914                 case OP_COND_EXC_GE_UN:
4915                 case OP_COND_EXC_LE:
4916                 case OP_COND_EXC_LE_UN:
4917                 case OP_COND_EXC_IEQ:
4918                 case OP_COND_EXC_INE_UN:
4919                 case OP_COND_EXC_ILT:
4920                 case OP_COND_EXC_ILT_UN:
4921                 case OP_COND_EXC_IGT:
4922                 case OP_COND_EXC_IGT_UN:
4923                 case OP_COND_EXC_IGE:
4924                 case OP_COND_EXC_IGE_UN:
4925                 case OP_COND_EXC_ILE:
4926                 case OP_COND_EXC_ILE_UN:
4927                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4928                         break;
4929                 case OP_COND_EXC_OV:
4930                 case OP_COND_EXC_NO:
4931                 case OP_COND_EXC_C:
4932                 case OP_COND_EXC_NC:
4933                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4934                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4935                         break;
4936                 case OP_COND_EXC_IOV:
4937                 case OP_COND_EXC_INO:
4938                 case OP_COND_EXC_IC:
4939                 case OP_COND_EXC_INC:
4940                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4941                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4942                         break;
4943
4944                 /* floating point opcodes */
4945                 case OP_R8CONST: {
4946                         double d = *(double *)ins->inst_p0;
4947
4948                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4949                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4950                         }
4951                         else {
4952                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4953                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4954                         }
4955                         break;
4956                 }
4957                 case OP_R4CONST: {
4958                         float f = *(float *)ins->inst_p0;
4959
4960                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4961                                 if (cfg->r4fp)
4962                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4963                                 else
4964                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4965                         }
4966                         else {
4967                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4968                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4969                                 if (!cfg->r4fp)
4970                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4971                         }
4972                         break;
4973                 }
4974                 case OP_STORER8_MEMBASE_REG:
4975                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4976                         break;
4977                 case OP_LOADR8_MEMBASE:
4978                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4979                         break;
4980                 case OP_STORER4_MEMBASE_REG:
4981                         if (cfg->r4fp) {
4982                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4983                         } else {
4984                                 /* This requires a double->single conversion */
4985                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4986                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4987                         }
4988                         break;
4989                 case OP_LOADR4_MEMBASE:
4990                         if (cfg->r4fp) {
4991                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4992                         } else {
4993                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4994                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4995                         }
4996                         break;
4997                 case OP_ICONV_TO_R4:
4998                         if (cfg->r4fp) {
4999                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5000                         } else {
5001                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5002                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5003                         }
5004                         break;
5005                 case OP_ICONV_TO_R8:
5006                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5007                         break;
5008                 case OP_LCONV_TO_R4:
5009                         if (cfg->r4fp) {
5010                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5011                         } else {
5012                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5013                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5014                         }
5015                         break;
5016                 case OP_LCONV_TO_R8:
5017                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5018                         break;
5019                 case OP_FCONV_TO_R4:
5020                         if (cfg->r4fp) {
5021                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5022                         } else {
5023                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5024                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5025                         }
5026                         break;
5027                 case OP_FCONV_TO_I1:
5028                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5029                         break;
5030                 case OP_FCONV_TO_U1:
5031                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5032                         break;
5033                 case OP_FCONV_TO_I2:
5034                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5035                         break;
5036                 case OP_FCONV_TO_U2:
5037                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5038                         break;
5039                 case OP_FCONV_TO_U4:
5040                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5041                         break;
5042                 case OP_FCONV_TO_I4:
5043                 case OP_FCONV_TO_I:
5044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5045                         break;
5046                 case OP_FCONV_TO_I8:
5047                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5048                         break;
5049
5050                 case OP_RCONV_TO_I1:
5051                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5052                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5053                         break;
5054                 case OP_RCONV_TO_U1:
5055                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5056                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5057                         break;
5058                 case OP_RCONV_TO_I2:
5059                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5060                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5061                         break;
5062                 case OP_RCONV_TO_U2:
5063                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5064                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5065                         break;
5066                 case OP_RCONV_TO_I4:
5067                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5068                         break;
5069                 case OP_RCONV_TO_U4:
5070                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5071                         break;
5072                 case OP_RCONV_TO_I8:
5073                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5074                         break;
5075                 case OP_RCONV_TO_R8:
5076                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5077                         break;
5078                 case OP_RCONV_TO_R4:
5079                         if (ins->dreg != ins->sreg1)
5080                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5081                         break;
5082
5083                 case OP_LCONV_TO_R_UN: {
5084                         guint8 *br [2];
5085
5086                         /* Based on gcc code */
5087                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5088                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5089
5090                         /* Positive case */
5091                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5092                         br [1] = code; x86_jump8 (code, 0);
5093                         amd64_patch (br [0], code);
5094
5095                         /* Negative case */
5096                         /* Save to the red zone */
5097                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5098                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5099                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5100                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5101                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5102                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5103                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5104                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5105                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5106                         /* Restore */
5107                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5108                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5109                         amd64_patch (br [1], code);
5110                         break;
5111                 }
5112                 case OP_LCONV_TO_OVF_U4:
5113                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5114                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5115                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5116                         break;
5117                 case OP_LCONV_TO_OVF_I4_UN:
5118                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5119                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5120                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5121                         break;
5122                 case OP_FMOVE:
5123                         if (ins->dreg != ins->sreg1)
5124                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5125                         break;
5126                 case OP_RMOVE:
5127                         if (ins->dreg != ins->sreg1)
5128                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5129                         break;
5130                 case OP_MOVE_F_TO_I4:
5131                         if (cfg->r4fp) {
5132                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5133                         } else {
5134                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5135                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5136                         }
5137                         break;
5138                 case OP_MOVE_I4_TO_F:
5139                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5140                         if (!cfg->r4fp)
5141                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5142                         break;
5143                 case OP_MOVE_F_TO_I8:
5144                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5145                         break;
5146                 case OP_MOVE_I8_TO_F:
5147                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5148                         break;
5149                 case OP_FADD:
5150                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5151                         break;
5152                 case OP_FSUB:
5153                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5154                         break;
5155                 case OP_FMUL:
5156                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5157                         break;
5158                 case OP_FDIV:
5159                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5160                         break;
5161                 case OP_FNEG: {
5162                         static double r8_0 = -0.0;
5163
5164                         g_assert (ins->sreg1 == ins->dreg);
5165
5166                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5167                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5168                         break;
5169                 }
5170                 case OP_SIN:
5171                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5172                         break;
5173                 case OP_COS:
5174                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5175                         break;
5176                 case OP_ABS: {
5177                         static guint64 d = 0x7fffffffffffffffUL;
5178
5179                         g_assert (ins->sreg1 == ins->dreg);
5180
5181                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5182                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5183                         break;
5184                 }
5185                 case OP_SQRT:
5186                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5187                         break;
5188
5189                 case OP_RADD:
5190                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5191                         break;
5192                 case OP_RSUB:
5193                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5194                         break;
5195                 case OP_RMUL:
5196                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5197                         break;
5198                 case OP_RDIV:
5199                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5200                         break;
5201                 case OP_RNEG: {
5202                         static float r4_0 = -0.0;
5203
5204                         g_assert (ins->sreg1 == ins->dreg);
5205
5206                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5207                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5208                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5209                         break;
5210                 }
5211
5212                 case OP_IMIN:
5213                         g_assert (cfg->opt & MONO_OPT_CMOV);
5214                         g_assert (ins->dreg == ins->sreg1);
5215                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5216                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5217                         break;
5218                 case OP_IMIN_UN:
5219                         g_assert (cfg->opt & MONO_OPT_CMOV);
5220                         g_assert (ins->dreg == ins->sreg1);
5221                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5222                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5223                         break;
5224                 case OP_IMAX:
5225                         g_assert (cfg->opt & MONO_OPT_CMOV);
5226                         g_assert (ins->dreg == ins->sreg1);
5227                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5228                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5229                         break;
5230                 case OP_IMAX_UN:
5231                         g_assert (cfg->opt & MONO_OPT_CMOV);
5232                         g_assert (ins->dreg == ins->sreg1);
5233                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5234                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5235                         break;
5236                 case OP_LMIN:
5237                         g_assert (cfg->opt & MONO_OPT_CMOV);
5238                         g_assert (ins->dreg == ins->sreg1);
5239                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5240                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5241                         break;
5242                 case OP_LMIN_UN:
5243                         g_assert (cfg->opt & MONO_OPT_CMOV);
5244                         g_assert (ins->dreg == ins->sreg1);
5245                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5246                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5247                         break;
5248                 case OP_LMAX:
5249                         g_assert (cfg->opt & MONO_OPT_CMOV);
5250                         g_assert (ins->dreg == ins->sreg1);
5251                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5252                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5253                         break;
5254                 case OP_LMAX_UN:
5255                         g_assert (cfg->opt & MONO_OPT_CMOV);
5256                         g_assert (ins->dreg == ins->sreg1);
5257                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5258                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5259                         break;
5260                 case OP_X86_FPOP:
5261                         break;
5262                 case OP_FCOMPARE:
5263                         /*
5264                          * The two arguments are swapped because the fbranch instructions
5265                          * depend on this for the non-sse case to work.
5266                          */
5267                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5268                         break;
5269                 case OP_RCOMPARE:
5270                         /*
5271                          * FIXME: Get rid of this.
5272                          * The two arguments are swapped because the fbranch instructions
5273                          * depend on this for the non-sse case to work.
5274                          */
5275                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5276                         break;
5277                 case OP_FCNEQ:
5278                 case OP_FCEQ: {
5279                         /* zeroing the register at the start results in
5280                          * shorter and faster code (we can also remove the widening op)
5281                          */
5282                         guchar *unordered_check;
5283
5284                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5285                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5286                         unordered_check = code;
5287                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5288
5289                         if (ins->opcode == OP_FCEQ) {
5290                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5291                                 amd64_patch (unordered_check, code);
5292                         } else {
5293                                 guchar *jump_to_end;
5294                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5295                                 jump_to_end = code;
5296                                 x86_jump8 (code, 0);
5297                                 amd64_patch (unordered_check, code);
5298                                 amd64_inc_reg (code, ins->dreg);
5299                                 amd64_patch (jump_to_end, code);
5300                         }
5301                         break;
5302                 }
5303                 case OP_FCLT:
5304                 case OP_FCLT_UN: {
5305                         /* zeroing the register at the start results in
5306                          * shorter and faster code (we can also remove the widening op)
5307                          */
5308                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5309                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5310                         if (ins->opcode == OP_FCLT_UN) {
5311                                 guchar *unordered_check = code;
5312                                 guchar *jump_to_end;
5313                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5314                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5315                                 jump_to_end = code;
5316                                 x86_jump8 (code, 0);
5317                                 amd64_patch (unordered_check, code);
5318                                 amd64_inc_reg (code, ins->dreg);
5319                                 amd64_patch (jump_to_end, code);
5320                         } else {
5321                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5322                         }
5323                         break;
5324                 }
5325                 case OP_FCLE: {
5326                         guchar *unordered_check;
5327                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5328                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5329                         unordered_check = code;
5330                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5331                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5332                         amd64_patch (unordered_check, code);
5333                         break;
5334                 }
5335                 case OP_FCGT:
5336                 case OP_FCGT_UN: {
5337                         /* zeroing the register at the start results in
5338                          * shorter and faster code (we can also remove the widening op)
5339                          */
5340                         guchar *unordered_check;
5341
5342                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5343                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5344                         if (ins->opcode == OP_FCGT) {
5345                                 unordered_check = code;
5346                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5347                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5348                                 amd64_patch (unordered_check, code);
5349                         } else {
5350                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5351                         }
5352                         break;
5353                 }
5354                 case OP_FCGE: {
5355                         guchar *unordered_check;
5356                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5357                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5358                         unordered_check = code;
5359                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5360                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5361                         amd64_patch (unordered_check, code);
5362                         break;
5363                 }
5364
5365                 case OP_RCEQ:
5366                 case OP_RCGT:
5367                 case OP_RCLT:
5368                 case OP_RCLT_UN:
5369                 case OP_RCGT_UN: {
5370                         int x86_cond;
5371                         gboolean unordered = FALSE;
5372
5373                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5374                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5375
5376                         switch (ins->opcode) {
5377                         case OP_RCEQ:
5378                                 x86_cond = X86_CC_EQ;
5379                                 break;
5380                         case OP_RCGT:
5381                                 x86_cond = X86_CC_LT;
5382                                 break;
5383                         case OP_RCLT:
5384                                 x86_cond = X86_CC_GT;
5385                                 break;
5386                         case OP_RCLT_UN:
5387                                 x86_cond = X86_CC_GT;
5388                                 unordered = TRUE;
5389                                 break;
5390                         case OP_RCGT_UN:
5391                                 x86_cond = X86_CC_LT;
5392                                 unordered = TRUE;
5393                                 break;
5394                         default:
5395                                 g_assert_not_reached ();
5396                                 break;
5397                         }
5398
5399                         if (unordered) {
5400                                 guchar *unordered_check;
5401                                 guchar *jump_to_end;
5402
5403                                 unordered_check = code;
5404                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5405                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5406                                 jump_to_end = code;
5407                                 x86_jump8 (code, 0);
5408                                 amd64_patch (unordered_check, code);
5409                                 amd64_inc_reg (code, ins->dreg);
5410                                 amd64_patch (jump_to_end, code);
5411                         } else {
5412                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5413                         }
5414                         break;
5415                 }
5416                 case OP_FCLT_MEMBASE:
5417                 case OP_FCGT_MEMBASE:
5418                 case OP_FCLT_UN_MEMBASE:
5419                 case OP_FCGT_UN_MEMBASE:
5420                 case OP_FCEQ_MEMBASE: {
5421                         guchar *unordered_check, *jump_to_end;
5422                         int x86_cond;
5423
5424                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5425                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5426
5427                         switch (ins->opcode) {
5428                         case OP_FCEQ_MEMBASE:
5429                                 x86_cond = X86_CC_EQ;
5430                                 break;
5431                         case OP_FCLT_MEMBASE:
5432                         case OP_FCLT_UN_MEMBASE:
5433                                 x86_cond = X86_CC_LT;
5434                                 break;
5435                         case OP_FCGT_MEMBASE:
5436                         case OP_FCGT_UN_MEMBASE:
5437                                 x86_cond = X86_CC_GT;
5438                                 break;
5439                         default:
5440                                 g_assert_not_reached ();
5441                         }
5442
5443                         unordered_check = code;
5444                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5445                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5446
5447                         switch (ins->opcode) {
5448                         case OP_FCEQ_MEMBASE:
5449                         case OP_FCLT_MEMBASE:
5450                         case OP_FCGT_MEMBASE:
5451                                 amd64_patch (unordered_check, code);
5452                                 break;
5453                         case OP_FCLT_UN_MEMBASE:
5454                         case OP_FCGT_UN_MEMBASE:
5455                                 jump_to_end = code;
5456                                 x86_jump8 (code, 0);
5457                                 amd64_patch (unordered_check, code);
5458                                 amd64_inc_reg (code, ins->dreg);
5459                                 amd64_patch (jump_to_end, code);
5460                                 break;
5461                         default:
5462                                 break;
5463                         }
5464                         break;
5465                 }
5466                 case OP_FBEQ: {
5467                         guchar *jump = code;
5468                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5469                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5470                         amd64_patch (jump, code);
5471                         break;
5472                 }
5473                 case OP_FBNE_UN:
5474                         /* Branch if C013 != 100 */
5475                         /* branch if !ZF or (PF|CF) */
5476                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5477                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5478                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5479                         break;
5480                 case OP_FBLT:
5481                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5482                         break;
5483                 case OP_FBLT_UN:
5484                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5485                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5486                         break;
5487                 case OP_FBGT:
5488                 case OP_FBGT_UN:
5489                         if (ins->opcode == OP_FBGT) {
5490                                 guchar *br1;
5491
5492                                 /* skip branch if C1=1 */
5493                                 br1 = code;
5494                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5495                                 /* branch if (C0 | C3) = 1 */
5496                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5497                                 amd64_patch (br1, code);
5498                                 break;
5499                         } else {
5500                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5501                         }
5502                         break;
5503                 case OP_FBGE: {
5504                         /* Branch if C013 == 100 or 001 */
5505                         guchar *br1;
5506
5507                         /* skip branch if C1=1 */
5508                         br1 = code;
5509                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5510                         /* branch if (C0 | C3) = 1 */
5511                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5512                         amd64_patch (br1, code);
5513                         break;
5514                 }
5515                 case OP_FBGE_UN:
5516                         /* Branch if C013 == 000 */
5517                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5518                         break;
5519                 case OP_FBLE: {
5520                         /* Branch if C013=000 or 100 */
5521                         guchar *br1;
5522
5523                         /* skip branch if C1=1 */
5524                         br1 = code;
5525                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5526                         /* branch if C0=0 */
5527                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5528                         amd64_patch (br1, code);
5529                         break;
5530                 }
5531                 case OP_FBLE_UN:
5532                         /* Branch if C013 != 001 */
5533                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5534                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5535                         break;
5536                 case OP_CKFINITE:
5537                         /* Transfer value to the fp stack */
5538                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5539                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5540                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5541
5542                         amd64_push_reg (code, AMD64_RAX);
5543                         amd64_fxam (code);
5544                         amd64_fnstsw (code);
5545                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5546                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5547                         amd64_pop_reg (code, AMD64_RAX);
5548                         amd64_fstp (code, 0);
5549                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5550                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5551                         break;
5552                 case OP_TLS_GET: {
5553                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5554                         break;
5555                 }
5556                 case OP_TLS_SET: {
5557                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5558                         break;
5559                 }
5560                 case OP_MEMORY_BARRIER: {
5561                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5562                                 x86_mfence (code);
5563                         break;
5564                 }
5565                 case OP_ATOMIC_ADD_I4:
5566                 case OP_ATOMIC_ADD_I8: {
5567                         int dreg = ins->dreg;
5568                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5569
5570                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5571                                 dreg = AMD64_R11;
5572
5573                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5574                         amd64_prefix (code, X86_LOCK_PREFIX);
5575                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5576                         /* dreg contains the old value, add with sreg2 value */
5577                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5578
5579                         if (ins->dreg != dreg)
5580                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5581
5582                         break;
5583                 }
5584                 case OP_ATOMIC_EXCHANGE_I4:
5585                 case OP_ATOMIC_EXCHANGE_I8: {
5586                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5587
5588                         /* LOCK prefix is implied. */
5589                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5590                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5591                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5592                         break;
5593                 }
5594                 case OP_ATOMIC_CAS_I4:
5595                 case OP_ATOMIC_CAS_I8: {
5596                         guint32 size;
5597
5598                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5599                                 size = 8;
5600                         else
5601                                 size = 4;
5602
5603                         /*
5604                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5605                          * an explanation of how this works.
5606                          */
5607                         g_assert (ins->sreg3 == AMD64_RAX);
5608                         g_assert (ins->sreg1 != AMD64_RAX);
5609                         g_assert (ins->sreg1 != ins->sreg2);
5610
5611                         amd64_prefix (code, X86_LOCK_PREFIX);
5612                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5613
5614                         if (ins->dreg != AMD64_RAX)
5615                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5616                         break;
5617                 }
5618                 case OP_ATOMIC_LOAD_I1: {
5619                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5620                         break;
5621                 }
5622                 case OP_ATOMIC_LOAD_U1: {
5623                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5624                         break;
5625                 }
5626                 case OP_ATOMIC_LOAD_I2: {
5627                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5628                         break;
5629                 }
5630                 case OP_ATOMIC_LOAD_U2: {
5631                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5632                         break;
5633                 }
5634                 case OP_ATOMIC_LOAD_I4: {
5635                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5636                         break;
5637                 }
5638                 case OP_ATOMIC_LOAD_U4:
5639                 case OP_ATOMIC_LOAD_I8:
5640                 case OP_ATOMIC_LOAD_U8: {
5641                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5642                         break;
5643                 }
5644                 case OP_ATOMIC_LOAD_R4: {
5645                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5646                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5647                         break;
5648                 }
5649                 case OP_ATOMIC_LOAD_R8: {
5650                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5651                         break;
5652                 }
5653                 case OP_ATOMIC_STORE_I1:
5654                 case OP_ATOMIC_STORE_U1:
5655                 case OP_ATOMIC_STORE_I2:
5656                 case OP_ATOMIC_STORE_U2:
5657                 case OP_ATOMIC_STORE_I4:
5658                 case OP_ATOMIC_STORE_U4:
5659                 case OP_ATOMIC_STORE_I8:
5660                 case OP_ATOMIC_STORE_U8: {
5661                         int size;
5662
5663                         switch (ins->opcode) {
5664                         case OP_ATOMIC_STORE_I1:
5665                         case OP_ATOMIC_STORE_U1:
5666                                 size = 1;
5667                                 break;
5668                         case OP_ATOMIC_STORE_I2:
5669                         case OP_ATOMIC_STORE_U2:
5670                                 size = 2;
5671                                 break;
5672                         case OP_ATOMIC_STORE_I4:
5673                         case OP_ATOMIC_STORE_U4:
5674                                 size = 4;
5675                                 break;
5676                         case OP_ATOMIC_STORE_I8:
5677                         case OP_ATOMIC_STORE_U8:
5678                                 size = 8;
5679                                 break;
5680                         }
5681
5682                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5683
5684                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5685                                 x86_mfence (code);
5686                         break;
5687                 }
5688                 case OP_ATOMIC_STORE_R4: {
5689                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5690                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5691
5692                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5693                                 x86_mfence (code);
5694                         break;
5695                 }
5696                 case OP_ATOMIC_STORE_R8: {
5697                         x86_nop (code);
5698                         x86_nop (code);
5699                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5700                         x86_nop (code);
5701                         x86_nop (code);
5702
5703                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5704                                 x86_mfence (code);
5705                         break;
5706                 }
5707                 case OP_CARD_TABLE_WBARRIER: {
5708                         int ptr = ins->sreg1;
5709                         int value = ins->sreg2;
5710                         guchar *br = 0;
5711                         int nursery_shift, card_table_shift;
5712                         gpointer card_table_mask;
5713                         size_t nursery_size;
5714
5715                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5716                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5717                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5718
5719                         /*If either point to the stack we can simply avoid the WB. This happens due to
5720                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5721                          */
5722                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5723                                 continue;
5724
5725                         /*
5726                          * We need one register we can clobber, we choose EDX and make sreg1
5727                          * fixed EAX to work around limitations in the local register allocator.
5728                          * sreg2 might get allocated to EDX, but that is not a problem since
5729                          * we use it before clobbering EDX.
5730                          */
5731                         g_assert (ins->sreg1 == AMD64_RAX);
5732
5733                         /*
5734                          * This is the code we produce:
5735                          *
5736                          *   edx = value
5737                          *   edx >>= nursery_shift
5738                          *   cmp edx, (nursery_start >> nursery_shift)
5739                          *   jne done
5740                          *   edx = ptr
5741                          *   edx >>= card_table_shift
5742                          *   edx += cardtable
5743                          *   [edx] = 1
5744                          * done:
5745                          */
5746
5747                         if (mono_gc_card_table_nursery_check ()) {
5748                                 if (value != AMD64_RDX)
5749                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5750                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5751                                 if (shifted_nursery_start >> 31) {
5752                                         /*
5753                                          * The value we need to compare against is 64 bits, so we need
5754                                          * another spare register.  We use RBX, which we save and
5755                                          * restore.
5756                                          */
5757                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5758                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5759                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5760                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5761                                 } else {
5762                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5763                                 }
5764                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5765                         }
5766                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5767                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5768                         if (card_table_mask)
5769                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5770
5771                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5772                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5773
5774                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5775
5776                         if (mono_gc_card_table_nursery_check ())
5777                                 x86_patch (br, code);
5778                         break;
5779                 }
5780 #ifdef MONO_ARCH_SIMD_INTRINSICS
5781                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5782                 case OP_ADDPS:
5783                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5784                         break;
5785                 case OP_DIVPS:
5786                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5787                         break;
5788                 case OP_MULPS:
5789                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5790                         break;
5791                 case OP_SUBPS:
5792                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5793                         break;
5794                 case OP_MAXPS:
5795                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5796                         break;
5797                 case OP_MINPS:
5798                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5799                         break;
5800                 case OP_COMPPS:
5801                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5802                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5803                         break;
5804                 case OP_ANDPS:
5805                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5806                         break;
5807                 case OP_ANDNPS:
5808                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5809                         break;
5810                 case OP_ORPS:
5811                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_XORPS:
5814                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5815                         break;
5816                 case OP_SQRTPS:
5817                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5818                         break;
5819                 case OP_RSQRTPS:
5820                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5821                         break;
5822                 case OP_RCPPS:
5823                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5824                         break;
5825                 case OP_ADDSUBPS:
5826                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5827                         break;
5828                 case OP_HADDPS:
5829                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5830                         break;
5831                 case OP_HSUBPS:
5832                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5833                         break;
5834                 case OP_DUPPS_HIGH:
5835                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5836                         break;
5837                 case OP_DUPPS_LOW:
5838                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5839                         break;
5840
5841                 case OP_PSHUFLEW_HIGH:
5842                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5843                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5844                         break;
5845                 case OP_PSHUFLEW_LOW:
5846                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5847                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5848                         break;
5849                 case OP_PSHUFLED:
5850                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5851                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5852                         break;
5853                 case OP_SHUFPS:
5854                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5855                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5856                         break;
5857                 case OP_SHUFPD:
5858                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5859                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5860                         break;
5861
5862                 case OP_ADDPD:
5863                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_DIVPD:
5866                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_MULPD:
5869                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_SUBPD:
5872                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874                 case OP_MAXPD:
5875                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_MINPD:
5878                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_COMPPD:
5881                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5882                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5883                         break;
5884                 case OP_ANDPD:
5885                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_ANDNPD:
5888                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_ORPD:
5891                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_XORPD:
5894                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_SQRTPD:
5897                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5898                         break;
5899                 case OP_ADDSUBPD:
5900                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902                 case OP_HADDPD:
5903                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_HSUBPD:
5906                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5907                         break;
5908                 case OP_DUPPD:
5909                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5910                         break;
5911
5912                 case OP_EXTRACT_MASK:
5913                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5914                         break;
5915
5916                 case OP_PAND:
5917                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_POR:
5920                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_PXOR:
5923                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925
5926                 case OP_PADDB:
5927                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_PADDW:
5930                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_PADDD:
5933                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_PADDQ:
5936                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938
5939                 case OP_PSUBB:
5940                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_PSUBW:
5943                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_PSUBD:
5946                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_PSUBQ:
5949                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951
5952                 case OP_PMAXB_UN:
5953                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955                 case OP_PMAXW_UN:
5956                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_PMAXD_UN:
5959                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961
5962                 case OP_PMAXB:
5963                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PMAXW:
5966                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968                 case OP_PMAXD:
5969                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971
5972                 case OP_PAVGB_UN:
5973                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PAVGW_UN:
5976                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_PMINB_UN:
5980                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PMINW_UN:
5983                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PMIND_UN:
5986                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988
5989                 case OP_PMINB:
5990                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_PMINW:
5993                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_PMIND:
5996                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998
5999                 case OP_PCMPEQB:
6000                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PCMPEQW:
6003                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_PCMPEQD:
6006                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_PCMPEQQ:
6009                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011
6012                 case OP_PCMPGTB:
6013                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_PCMPGTW:
6016                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_PCMPGTD:
6019                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_PCMPGTQ:
6022                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024
6025                 case OP_PSUM_ABS_DIFF:
6026                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028
6029                 case OP_UNPACK_LOWB:
6030                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_UNPACK_LOWW:
6033                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_UNPACK_LOWD:
6036                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_UNPACK_LOWQ:
6039                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_UNPACK_LOWPS:
6042                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_UNPACK_LOWPD:
6045                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047
6048                 case OP_UNPACK_HIGHB:
6049                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_UNPACK_HIGHW:
6052                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_UNPACK_HIGHD:
6055                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_UNPACK_HIGHQ:
6058                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_UNPACK_HIGHPS:
6061                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_UNPACK_HIGHPD:
6064                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066
6067                 case OP_PACKW:
6068                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PACKD:
6071                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PACKW_UN:
6074                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_PACKD_UN:
6077                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079
6080                 case OP_PADDB_SAT_UN:
6081                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PSUBB_SAT_UN:
6084                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PADDW_SAT_UN:
6087                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PSUBW_SAT_UN:
6090                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092
6093                 case OP_PADDB_SAT:
6094                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PSUBB_SAT:
6097                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PADDW_SAT:
6100                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PSUBW_SAT:
6103                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105
6106                 case OP_PMULW:
6107                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMULD:
6110                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMULQ:
6113                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PMULW_HIGH_UN:
6116                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PMULW_HIGH:
6119                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121
6122                 case OP_PSHRW:
6123                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6124                         break;
6125                 case OP_PSHRW_REG:
6126                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6127                         break;
6128
6129                 case OP_PSARW:
6130                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6131                         break;
6132                 case OP_PSARW_REG:
6133                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6134                         break;
6135
6136                 case OP_PSHLW:
6137                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6138                         break;
6139                 case OP_PSHLW_REG:
6140                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6141                         break;
6142
6143                 case OP_PSHRD:
6144                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6145                         break;
6146                 case OP_PSHRD_REG:
6147                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6148                         break;
6149
6150                 case OP_PSARD:
6151                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6152                         break;
6153                 case OP_PSARD_REG:
6154                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6155                         break;
6156
6157                 case OP_PSHLD:
6158                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6159                         break;
6160                 case OP_PSHLD_REG:
6161                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6162                         break;
6163
6164                 case OP_PSHRQ:
6165                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6166                         break;
6167                 case OP_PSHRQ_REG:
6168                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6169                         break;
6170
6171                 /*TODO: This is appart of the sse spec but not added
6172                 case OP_PSARQ:
6173                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6174                         break;
6175                 case OP_PSARQ_REG:
6176                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6177                         break;
6178                 */
6179
6180                 case OP_PSHLQ:
6181                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6182                         break;
6183                 case OP_PSHLQ_REG:
6184                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6185                         break;
6186                 case OP_CVTDQ2PD:
6187                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6188                         break;
6189                 case OP_CVTDQ2PS:
6190                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6191                         break;
6192                 case OP_CVTPD2DQ:
6193                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6194                         break;
6195                 case OP_CVTPD2PS:
6196                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6197                         break;
6198                 case OP_CVTPS2DQ:
6199                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6200                         break;
6201                 case OP_CVTPS2PD:
6202                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6203                         break;
6204                 case OP_CVTTPD2DQ:
6205                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6206                         break;
6207                 case OP_CVTTPS2DQ:
6208                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6209                         break;
6210
6211                 case OP_ICONV_TO_X:
6212                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6213                         break;
6214                 case OP_EXTRACT_I4:
6215                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6216                         break;
6217                 case OP_EXTRACT_I8:
6218                         if (ins->inst_c0) {
6219                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6220                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6221                         } else {
6222                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6223                         }
6224                         break;
6225                 case OP_EXTRACT_I1:
6226                 case OP_EXTRACT_U1:
6227                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6228                         if (ins->inst_c0)
6229                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6230                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6231                         break;
6232                 case OP_EXTRACT_I2:
6233                 case OP_EXTRACT_U2:
6234                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6235                         if (ins->inst_c0)
6236                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6237                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6238                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6239                         break;
6240                 case OP_EXTRACT_R8:
6241                         if (ins->inst_c0)
6242                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6243                         else
6244                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6245                         break;
6246                 case OP_INSERT_I2:
6247                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6248                         break;
6249                 case OP_EXTRACTX_U2:
6250                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6251                         break;
6252                 case OP_INSERTX_U1_SLOW:
6253                         /*sreg1 is the extracted ireg (scratch)
6254                         /sreg2 is the to be inserted ireg (scratch)
6255                         /dreg is the xreg to receive the value*/
6256
6257                         /*clear the bits from the extracted word*/
6258                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6259                         /*shift the value to insert if needed*/
6260                         if (ins->inst_c0 & 1)
6261                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6262                         /*join them together*/
6263                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6264                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6265                         break;
6266                 case OP_INSERTX_I4_SLOW:
6267                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6268                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6269                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6270                         break;
6271                 case OP_INSERTX_I8_SLOW:
6272                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6273                         if (ins->inst_c0)
6274                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6275                         else
6276                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6277                         break;
6278
6279                 case OP_INSERTX_R4_SLOW:
6280                         switch (ins->inst_c0) {
6281                         case 0:
6282                                 if (cfg->r4fp)
6283                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6284                                 else
6285                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6286                                 break;
6287                         case 1:
6288                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6289                                 if (cfg->r4fp)
6290                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6291                                 else
6292                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6294                                 break;
6295                         case 2:
6296                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6297                                 if (cfg->r4fp)
6298                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6299                                 else
6300                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6301                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6302                                 break;
6303                         case 3:
6304                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6305                                 if (cfg->r4fp)
6306                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6307                                 else
6308                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6309                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6310                                 break;
6311                         }
6312                         break;
6313                 case OP_INSERTX_R8_SLOW:
6314                         if (ins->inst_c0)
6315                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6316                         else
6317                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6318                         break;
6319                 case OP_STOREX_MEMBASE_REG:
6320                 case OP_STOREX_MEMBASE:
6321                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6322                         break;
6323                 case OP_LOADX_MEMBASE:
6324                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6325                         break;
6326                 case OP_LOADX_ALIGNED_MEMBASE:
6327                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6328                         break;
6329                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6330                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6331                         break;
6332                 case OP_STOREX_NTA_MEMBASE_REG:
6333                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6334                         break;
6335                 case OP_PREFETCH_MEMBASE:
6336                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6337                         break;
6338
6339                 case OP_XMOVE:
6340                         /*FIXME the peephole pass should have killed this*/
6341                         if (ins->dreg != ins->sreg1)
6342                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6343                         break;
6344                 case OP_XZERO:
6345                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6346                         break;
6347                 case OP_XONES:
6348                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6349                         break;
6350                 case OP_ICONV_TO_R4_RAW:
6351                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6352                         if (!cfg->r4fp)
6353                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6354                         break;
6355
6356                 case OP_FCONV_TO_R8_X:
6357                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6358                         break;
6359
6360                 case OP_XCONV_R8_TO_I4:
6361                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6362                         switch (ins->backend.source_opcode) {
6363                         case OP_FCONV_TO_I1:
6364                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6365                                 break;
6366                         case OP_FCONV_TO_U1:
6367                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6368                                 break;
6369                         case OP_FCONV_TO_I2:
6370                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6371                                 break;
6372                         case OP_FCONV_TO_U2:
6373                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6374                                 break;
6375                         }
6376                         break;
6377
6378                 case OP_EXPAND_I2:
6379                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6380                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6381                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6382                         break;
6383                 case OP_EXPAND_I4:
6384                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6385                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6386                         break;
6387                 case OP_EXPAND_I8:
6388                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6389                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6390                         break;
6391                 case OP_EXPAND_R4:
6392                         if (cfg->r4fp) {
6393                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6394                         } else {
6395                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6396                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6397                         }
6398                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6399                         break;
6400                 case OP_EXPAND_R8:
6401                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6402                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6403                         break;
6404 #endif
6405                 case OP_LIVERANGE_START: {
6406                         if (cfg->verbose_level > 1)
6407                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6408                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6409                         break;
6410                 }
6411                 case OP_LIVERANGE_END: {
6412                         if (cfg->verbose_level > 1)
6413                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6414                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6415                         break;
6416                 }
6417                 case OP_GC_SAFE_POINT: {
6418                         guint8 *br [1];
6419
6420                         g_assert (mono_threads_is_coop_enabled ());
6421
6422                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6423                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6424                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6425                         amd64_patch (br[0], code);
6426                         break;
6427                 }
6428
6429                 case OP_GC_LIVENESS_DEF:
6430                 case OP_GC_LIVENESS_USE:
6431                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6432                         ins->backend.pc_offset = code - cfg->native_code;
6433                         break;
6434                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6435                         ins->backend.pc_offset = code - cfg->native_code;
6436                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6437                         break;
6438                 case OP_GET_LAST_ERROR:
6439                         emit_get_last_error(code, ins->dreg);
6440                         break;
6441                 default:
6442                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6443                         g_assert_not_reached ();
6444                 }
6445
6446                 if ((code - cfg->native_code - offset) > max_len) {
6447                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6448                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6449                         g_assert_not_reached ();
6450                 }
6451         }
6452
6453         cfg->code_len = code - cfg->native_code;
6454 }
6455
6456 #endif /* DISABLE_JIT */
6457
6458 void
6459 mono_arch_register_lowlevel_calls (void)
6460 {
6461         /* The signature doesn't matter */
6462         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6463
6464 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6465 #if _MSC_VER
6466         extern void __chkstk (void);
6467         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6468 #else
6469         extern void ___chkstk_ms (void);
6470         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6471 #endif
6472 #endif
6473 }
6474
6475 void
6476 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6477 {
6478         unsigned char *ip = ji->ip.i + code;
6479
6480         /*
6481          * Debug code to help track down problems where the target of a near call is
6482          * is not valid.
6483          */
6484         if (amd64_is_near_call (ip)) {
6485                 gint64 disp = (guint8*)target - (guint8*)ip;
6486
6487                 if (!amd64_is_imm32 (disp)) {
6488                         printf ("TYPE: %d\n", ji->type);
6489                         switch (ji->type) {
6490                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6491                                 printf ("V: %s\n", ji->data.name);
6492                                 break;
6493                         case MONO_PATCH_INFO_METHOD_JUMP:
6494                         case MONO_PATCH_INFO_METHOD:
6495                                 printf ("V: %s\n", ji->data.method->name);
6496                                 break;
6497                         default:
6498                                 break;
6499                         }
6500                 }
6501         }
6502
6503         amd64_patch (ip, (gpointer)target);
6504 }
6505
6506 #ifndef DISABLE_JIT
6507
6508 static int
6509 get_max_epilog_size (MonoCompile *cfg)
6510 {
6511         int max_epilog_size = 16;
6512
6513         if (cfg->method->save_lmf)
6514                 max_epilog_size += 256;
6515
6516         if (mono_jit_trace_calls != NULL)
6517                 max_epilog_size += 50;
6518
6519         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6520                 max_epilog_size += 50;
6521
6522         max_epilog_size += (AMD64_NREG * 2);
6523
6524         return max_epilog_size;
6525 }
6526
6527 /*
6528  * This macro is used for testing whenever the unwinder works correctly at every point
6529  * where an async exception can happen.
6530  */
6531 /* This will generate a SIGSEGV at the given point in the code */
6532 #define async_exc_point(code) do { \
6533     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6534          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6535              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6536          cfg->arch.async_point_count ++; \
6537     } \
6538 } while (0)
6539
6540 #ifdef TARGET_WIN32
6541 static guint8 *
6542 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6543 {
6544         int cfa_offset = *cfa_offset_input;
6545
6546         /* Allocate windows stack frame using stack probing method */
6547         if (alloc_size) {
6548
6549                 if (alloc_size >= 0x1000) {
6550                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6551                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6552                 }
6553
6554                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6555                 if (cfg->arch.omit_fp) {
6556                         cfa_offset += alloc_size;
6557                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6558                         async_exc_point (code);
6559                 }
6560
6561                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6562                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6563                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6564                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6565                 // that will retrieve the expected results.
6566                 if (cfg->arch.omit_fp)
6567                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6568         }
6569
6570         *cfa_offset_input = cfa_offset;
6571         return code;
6572 }
6573 #endif /* TARGET_WIN32 */
6574
6575 guint8 *
6576 mono_arch_emit_prolog (MonoCompile *cfg)
6577 {
6578         MonoMethod *method = cfg->method;
6579         MonoBasicBlock *bb;
6580         MonoMethodSignature *sig;
6581         MonoInst *ins;
6582         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6583         guint8 *code;
6584         CallInfo *cinfo;
6585         MonoInst *lmf_var = cfg->lmf_var;
6586         gboolean args_clobbered = FALSE;
6587         gboolean trace = FALSE;
6588
6589         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6590
6591         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6592
6593         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6594                 trace = TRUE;
6595
6596         /* Amount of stack space allocated by register saving code */
6597         pos = 0;
6598
6599         /* Offset between RSP and the CFA */
6600         cfa_offset = 0;
6601
6602         /*
6603          * The prolog consists of the following parts:
6604          * FP present:
6605          * - push rbp
6606          * - mov rbp, rsp
6607          * - save callee saved regs using moves
6608          * - allocate frame
6609          * - save rgctx if needed
6610          * - save lmf if needed
6611          * FP not present:
6612          * - allocate frame
6613          * - save rgctx if needed
6614          * - save lmf if needed
6615          * - save callee saved regs using moves
6616          */
6617
6618         // CFA = sp + 8
6619         cfa_offset = 8;
6620         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6621         // IP saved at CFA - 8
6622         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6623         async_exc_point (code);
6624         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6625
6626         if (!cfg->arch.omit_fp) {
6627                 amd64_push_reg (code, AMD64_RBP);
6628                 cfa_offset += 8;
6629                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6630                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6631                 async_exc_point (code);
6632                 /* These are handled automatically by the stack marking code */
6633                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6634
6635                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6636                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6637                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6638                 async_exc_point (code);
6639         }
6640
6641         /* The param area is always at offset 0 from sp */
6642         /* This needs to be allocated here, since it has to come after the spill area */
6643         if (cfg->param_area) {
6644                 if (cfg->arch.omit_fp)
6645                         // FIXME:
6646                         g_assert_not_reached ();
6647                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6648         }
6649
6650         if (cfg->arch.omit_fp) {
6651                 /*
6652                  * On enter, the stack is misaligned by the pushing of the return
6653                  * address. It is either made aligned by the pushing of %rbp, or by
6654                  * this.
6655                  */
6656                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6657                 if ((alloc_size % 16) == 0) {
6658                         alloc_size += 8;
6659                         /* Mark the padding slot as NOREF */
6660                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6661                 }
6662         } else {
6663                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6664                 if (cfg->stack_offset != alloc_size) {
6665                         /* Mark the padding slot as NOREF */
6666                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6667                 }
6668                 cfg->arch.sp_fp_offset = alloc_size;
6669                 alloc_size -= pos;
6670         }
6671
6672         cfg->arch.stack_alloc_size = alloc_size;
6673
6674         /* Allocate stack frame */
6675 #ifdef TARGET_WIN32
6676         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6677 #else
6678         if (alloc_size) {
6679                 /* See mono_emit_stack_alloc */
6680 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6681                 guint32 remaining_size = alloc_size;
6682                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6683                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6684                 guint32 offset = code - cfg->native_code;
6685                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6686                         while (required_code_size >= (cfg->code_size - offset))
6687                                 cfg->code_size *= 2;
6688                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6689                         code = cfg->native_code + offset;
6690                         cfg->stat_code_reallocs++;
6691                 }
6692
6693                 while (remaining_size >= 0x1000) {
6694                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6695                         if (cfg->arch.omit_fp) {
6696                                 cfa_offset += 0x1000;
6697                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6698                         }
6699                         async_exc_point (code);
6700
6701                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6702                         remaining_size -= 0x1000;
6703                 }
6704                 if (remaining_size) {
6705                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6706                         if (cfg->arch.omit_fp) {
6707                                 cfa_offset += remaining_size;
6708                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6709                                 async_exc_point (code);
6710                         }
6711                 }
6712 #else
6713                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6714                 if (cfg->arch.omit_fp) {
6715                         cfa_offset += alloc_size;
6716                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6717                         async_exc_point (code);
6718                 }
6719 #endif
6720         }
6721 #endif
6722
6723         /* Stack alignment check */
6724 #if 0
6725         {
6726                 guint8 *buf;
6727
6728                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6729                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6730                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6731                 buf = code;
6732                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6733                 amd64_breakpoint (code);
6734                 amd64_patch (buf, code);
6735         }
6736 #endif
6737
6738         if (mini_get_debug_options ()->init_stacks) {
6739                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6740
6741                 /* Save registers to the red zone */
6742                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6743                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6744
6745                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6746                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6747                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6748
6749                 amd64_cld (code);
6750                 amd64_prefix (code, X86_REP_PREFIX);
6751                 amd64_stosl (code);
6752
6753                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6754                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6755         }
6756
6757         /* Save LMF */
6758         if (method->save_lmf)
6759                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6760
6761         /* Save callee saved registers */
6762         if (cfg->arch.omit_fp) {
6763                 save_area_offset = cfg->arch.reg_save_area_offset;
6764                 /* Save caller saved registers after sp is adjusted */
6765                 /* The registers are saved at the bottom of the frame */
6766                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6767         } else {
6768                 /* The registers are saved just below the saved rbp */
6769                 save_area_offset = cfg->arch.reg_save_area_offset;
6770         }
6771
6772         for (i = 0; i < AMD64_NREG; ++i) {
6773                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6774                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6775
6776                         if (cfg->arch.omit_fp) {
6777                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6778                                 /* These are handled automatically by the stack marking code */
6779                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6780                         } else {
6781                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6782                                 // FIXME: GC
6783                         }
6784
6785                         save_area_offset += 8;
6786                         async_exc_point (code);
6787                 }
6788         }
6789
6790         /* store runtime generic context */
6791         if (cfg->rgctx_var) {
6792                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6793                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6794
6795                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6796
6797                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6798                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6799         }
6800
6801         /* compute max_length in order to use short forward jumps */
6802         max_epilog_size = get_max_epilog_size (cfg);
6803         if (cfg->opt & MONO_OPT_BRANCH) {
6804                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6805                         MonoInst *ins;
6806                         int max_length = 0;
6807
6808                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6809                                 max_length += 6;
6810                         /* max alignment for loops */
6811                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6812                                 max_length += LOOP_ALIGNMENT;
6813
6814                         MONO_BB_FOR_EACH_INS (bb, ins) {
6815                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6816                         }
6817
6818                         /* Take prolog and epilog instrumentation into account */
6819                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6820                                 max_length += max_epilog_size;
6821
6822                         bb->max_length = max_length;
6823                 }
6824         }
6825
6826         sig = mono_method_signature (method);
6827         pos = 0;
6828
6829         cinfo = (CallInfo *)cfg->arch.cinfo;
6830
6831         if (sig->ret->type != MONO_TYPE_VOID) {
6832                 /* Save volatile arguments to the stack */
6833                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6834                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6835         }
6836
6837         /* Keep this in sync with emit_load_volatile_arguments */
6838         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6839                 ArgInfo *ainfo = cinfo->args + i;
6840
6841                 ins = cfg->args [i];
6842
6843                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6844                         /* Unused arguments */
6845                         continue;
6846
6847                 /* Save volatile arguments to the stack */
6848                 if (ins->opcode != OP_REGVAR) {
6849                         switch (ainfo->storage) {
6850                         case ArgInIReg: {
6851                                 guint32 size = 8;
6852
6853                                 /* FIXME: I1 etc */
6854                                 /*
6855                                 if (stack_offset & 0x1)
6856                                         size = 1;
6857                                 else if (stack_offset & 0x2)
6858                                         size = 2;
6859                                 else if (stack_offset & 0x4)
6860                                         size = 4;
6861                                 else
6862                                         size = 8;
6863                                 */
6864                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6865
6866                                 /*
6867                                  * Save the original location of 'this',
6868                                  * get_generic_info_from_stack_frame () needs this to properly look up
6869                                  * the argument value during the handling of async exceptions.
6870                                  */
6871                                 if (ins == cfg->args [0]) {
6872                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6873                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6874                                 }
6875                                 break;
6876                         }
6877                         case ArgInFloatSSEReg:
6878                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6879                                 break;
6880                         case ArgInDoubleSSEReg:
6881                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6882                                 break;
6883                         case ArgValuetypeInReg:
6884                                 for (quad = 0; quad < 2; quad ++) {
6885                                         switch (ainfo->pair_storage [quad]) {
6886                                         case ArgInIReg:
6887                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6888                                                 break;
6889                                         case ArgInFloatSSEReg:
6890                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6891                                                 break;
6892                                         case ArgInDoubleSSEReg:
6893                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6894                                                 break;
6895                                         case ArgNone:
6896                                                 break;
6897                                         default:
6898                                                 g_assert_not_reached ();
6899                                         }
6900                                 }
6901                                 break;
6902                         case ArgValuetypeAddrInIReg:
6903                                 if (ainfo->pair_storage [0] == ArgInIReg)
6904                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6905                                 break;
6906                         case ArgValuetypeAddrOnStack:
6907                                 break;
6908                         case ArgGSharedVtInReg:
6909                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6910                                 break;
6911                         default:
6912                                 break;
6913                         }
6914                 } else {
6915                         /* Argument allocated to (non-volatile) register */
6916                         switch (ainfo->storage) {
6917                         case ArgInIReg:
6918                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6919                                 break;
6920                         case ArgOnStack:
6921                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6922                                 break;
6923                         default:
6924                                 g_assert_not_reached ();
6925                         }
6926
6927                         if (ins == cfg->args [0]) {
6928                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6929                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6930                         }
6931                 }
6932         }
6933
6934         if (cfg->method->save_lmf)
6935                 args_clobbered = TRUE;
6936
6937         if (trace) {
6938                 args_clobbered = TRUE;
6939                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6940         }
6941
6942         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6943                 args_clobbered = TRUE;
6944
6945         /*
6946          * Optimize the common case of the first bblock making a call with the same
6947          * arguments as the method. This works because the arguments are still in their
6948          * original argument registers.
6949          * FIXME: Generalize this
6950          */
6951         if (!args_clobbered) {
6952                 MonoBasicBlock *first_bb = cfg->bb_entry;
6953                 MonoInst *next;
6954                 int filter = FILTER_IL_SEQ_POINT;
6955
6956                 next = mono_bb_first_inst (first_bb, filter);
6957                 if (!next && first_bb->next_bb) {
6958                         first_bb = first_bb->next_bb;
6959                         next = mono_bb_first_inst (first_bb, filter);
6960                 }
6961
6962                 if (first_bb->in_count > 1)
6963                         next = NULL;
6964
6965                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6966                         ArgInfo *ainfo = cinfo->args + i;
6967                         gboolean match = FALSE;
6968
6969                         ins = cfg->args [i];
6970                         if (ins->opcode != OP_REGVAR) {
6971                                 switch (ainfo->storage) {
6972                                 case ArgInIReg: {
6973                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6974                                                 if (next->dreg == ainfo->reg) {
6975                                                         NULLIFY_INS (next);
6976                                                         match = TRUE;
6977                                                 } else {
6978                                                         next->opcode = OP_MOVE;
6979                                                         next->sreg1 = ainfo->reg;
6980                                                         /* Only continue if the instruction doesn't change argument regs */
6981                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6982                                                                 match = TRUE;
6983                                                 }
6984                                         }
6985                                         break;
6986                                 }
6987                                 default:
6988                                         break;
6989                                 }
6990                         } else {
6991                                 /* Argument allocated to (non-volatile) register */
6992                                 switch (ainfo->storage) {
6993                                 case ArgInIReg:
6994                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6995                                                 NULLIFY_INS (next);
6996                                                 match = TRUE;
6997                                         }
6998                                         break;
6999                                 default:
7000                                         break;
7001                                 }
7002                         }
7003
7004                         if (match) {
7005                                 next = mono_inst_next (next, filter);
7006                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7007                                 if (!next)
7008                                         break;
7009                         }
7010                 }
7011         }
7012
7013         if (cfg->gen_sdb_seq_points) {
7014                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7015
7016                 /* Initialize seq_point_info_var */
7017                 if (cfg->compile_aot) {
7018                         /* Initialize the variable from a GOT slot */
7019                         /* Same as OP_AOTCONST */
7020                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7021                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7022                         g_assert (info_var->opcode == OP_REGOFFSET);
7023                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7024                 }
7025
7026                 if (cfg->compile_aot) {
7027                         /* Initialize ss_tramp_var */
7028                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7029                         g_assert (ins->opcode == OP_REGOFFSET);
7030
7031                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7032                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7033                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7034                 } else {
7035                         /* Initialize ss_tramp_var */
7036                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7037                         g_assert (ins->opcode == OP_REGOFFSET);
7038
7039                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7040                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7041
7042                         /* Initialize bp_tramp_var */
7043                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7044                         g_assert (ins->opcode == OP_REGOFFSET);
7045
7046                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7047                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7048                 }
7049         }
7050
7051         cfg->code_len = code - cfg->native_code;
7052
7053         g_assert (cfg->code_len < cfg->code_size);
7054
7055         return code;
7056 }
7057
7058 void
7059 mono_arch_emit_epilog (MonoCompile *cfg)
7060 {
7061         MonoMethod *method = cfg->method;
7062         int quad, i;
7063         guint8 *code;
7064         int max_epilog_size;
7065         CallInfo *cinfo;
7066         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7067         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7068
7069         max_epilog_size = get_max_epilog_size (cfg);
7070
7071         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7072                 cfg->code_size *= 2;
7073                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7074                 cfg->stat_code_reallocs++;
7075         }
7076         code = cfg->native_code + cfg->code_len;
7077
7078         cfg->has_unwind_info_for_epilog = TRUE;
7079
7080         /* Mark the start of the epilog */
7081         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7082
7083         /* Save the uwind state which is needed by the out-of-line code */
7084         mono_emit_unwind_op_remember_state (cfg, code);
7085
7086         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7087                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7088
7089         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7090
7091         if (method->save_lmf) {
7092                 /* check if we need to restore protection of the stack after a stack overflow */
7093                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7094                         guint8 *patch;
7095                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7096                         /* we load the value in a separate instruction: this mechanism may be
7097                          * used later as a safer way to do thread interruption
7098                          */
7099                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7100                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7101                         patch = code;
7102                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7103                         /* note that the call trampoline will preserve eax/edx */
7104                         x86_call_reg (code, X86_ECX);
7105                         x86_patch (patch, code);
7106                 } else {
7107                         /* FIXME: maybe save the jit tls in the prolog */
7108                 }
7109                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7110                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7111                 }
7112         }
7113
7114         /* Restore callee saved regs */
7115         for (i = 0; i < AMD64_NREG; ++i) {
7116                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7117                         /* Restore only used_int_regs, not arch.saved_iregs */
7118 #if defined(MONO_SUPPORT_TASKLETS)
7119                         int restore_reg=1;
7120 #else
7121                         int restore_reg=(cfg->used_int_regs & (1 << i));
7122 #endif
7123                         if (restore_reg) {
7124                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7125                                 mono_emit_unwind_op_same_value (cfg, code, i);
7126                                 async_exc_point (code);
7127                         }
7128                         save_area_offset += 8;
7129                 }
7130         }
7131
7132         /* Load returned vtypes into registers if needed */
7133         cinfo = (CallInfo *)cfg->arch.cinfo;
7134         if (cinfo->ret.storage == ArgValuetypeInReg) {
7135                 ArgInfo *ainfo = &cinfo->ret;
7136                 MonoInst *inst = cfg->ret;
7137
7138                 for (quad = 0; quad < 2; quad ++) {
7139                         switch (ainfo->pair_storage [quad]) {
7140                         case ArgInIReg:
7141                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7142                                 break;
7143                         case ArgInFloatSSEReg:
7144                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7145                                 break;
7146                         case ArgInDoubleSSEReg:
7147                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7148                                 break;
7149                         case ArgNone:
7150                                 break;
7151                         default:
7152                                 g_assert_not_reached ();
7153                         }
7154                 }
7155         }
7156
7157         if (cfg->arch.omit_fp) {
7158                 if (cfg->arch.stack_alloc_size) {
7159                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7160                 }
7161         } else {
7162 #ifdef TARGET_WIN32
7163                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7164                 amd64_pop_reg (code, AMD64_RBP);
7165                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7166 #else
7167                 amd64_leave (code);
7168                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7169 #endif
7170         }
7171         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7172         async_exc_point (code);
7173         amd64_ret (code);
7174
7175         /* Restore the unwind state to be the same as before the epilog */
7176         mono_emit_unwind_op_restore_state (cfg, code);
7177
7178         cfg->code_len = code - cfg->native_code;
7179
7180         g_assert (cfg->code_len < cfg->code_size);
7181 }
7182
7183 void
7184 mono_arch_emit_exceptions (MonoCompile *cfg)
7185 {
7186         MonoJumpInfo *patch_info;
7187         int nthrows, i;
7188         guint8 *code;
7189         MonoClass *exc_classes [16];
7190         guint8 *exc_throw_start [16], *exc_throw_end [16];
7191         guint32 code_size = 0;
7192
7193         /* Compute needed space */
7194         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7195                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7196                         code_size += 40;
7197                 if (patch_info->type == MONO_PATCH_INFO_R8)
7198                         code_size += 8 + 15; /* sizeof (double) + alignment */
7199                 if (patch_info->type == MONO_PATCH_INFO_R4)
7200                         code_size += 4 + 15; /* sizeof (float) + alignment */
7201                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7202                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7203         }
7204
7205         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7206                 cfg->code_size *= 2;
7207                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7208                 cfg->stat_code_reallocs++;
7209         }
7210
7211         code = cfg->native_code + cfg->code_len;
7212
7213         /* add code to raise exceptions */
7214         nthrows = 0;
7215         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7216                 switch (patch_info->type) {
7217                 case MONO_PATCH_INFO_EXC: {
7218                         MonoClass *exc_class;
7219                         guint8 *buf, *buf2;
7220                         guint32 throw_ip;
7221
7222                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7223
7224                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7225                         throw_ip = patch_info->ip.i;
7226
7227                         //x86_breakpoint (code);
7228                         /* Find a throw sequence for the same exception class */
7229                         for (i = 0; i < nthrows; ++i)
7230                                 if (exc_classes [i] == exc_class)
7231                                         break;
7232                         if (i < nthrows) {
7233                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7234                                 x86_jump_code (code, exc_throw_start [i]);
7235                                 patch_info->type = MONO_PATCH_INFO_NONE;
7236                         }
7237                         else {
7238                                 buf = code;
7239                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7240                                 buf2 = code;
7241
7242                                 if (nthrows < 16) {
7243                                         exc_classes [nthrows] = exc_class;
7244                                         exc_throw_start [nthrows] = code;
7245                                 }
7246                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7247
7248                                 patch_info->type = MONO_PATCH_INFO_NONE;
7249
7250                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7251
7252                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7253                                 while (buf < buf2)
7254                                         x86_nop (buf);
7255
7256                                 if (nthrows < 16) {
7257                                         exc_throw_end [nthrows] = code;
7258                                         nthrows ++;
7259                                 }
7260                         }
7261                         break;
7262                 }
7263                 default:
7264                         /* do nothing */
7265                         break;
7266                 }
7267                 g_assert(code < cfg->native_code + cfg->code_size);
7268         }
7269
7270         /* Handle relocations with RIP relative addressing */
7271         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7272                 gboolean remove = FALSE;
7273                 guint8 *orig_code = code;
7274
7275                 switch (patch_info->type) {
7276                 case MONO_PATCH_INFO_R8:
7277                 case MONO_PATCH_INFO_R4: {
7278                         guint8 *pos, *patch_pos;
7279                         guint32 target_pos;
7280
7281                         /* The SSE opcodes require a 16 byte alignment */
7282                         code = (guint8*)ALIGN_TO (code, 16);
7283
7284                         pos = cfg->native_code + patch_info->ip.i;
7285                         if (IS_REX (pos [1])) {
7286                                 patch_pos = pos + 5;
7287                                 target_pos = code - pos - 9;
7288                         }
7289                         else {
7290                                 patch_pos = pos + 4;
7291                                 target_pos = code - pos - 8;
7292                         }
7293
7294                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7295                                 *(double*)code = *(double*)patch_info->data.target;
7296                                 code += sizeof (double);
7297                         } else {
7298                                 *(float*)code = *(float*)patch_info->data.target;
7299                                 code += sizeof (float);
7300                         }
7301
7302                         *(guint32*)(patch_pos) = target_pos;
7303
7304                         remove = TRUE;
7305                         break;
7306                 }
7307                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7308                         guint8 *pos;
7309
7310                         if (cfg->compile_aot)
7311                                 continue;
7312
7313                         /*loading is faster against aligned addresses.*/
7314                         code = (guint8*)ALIGN_TO (code, 8);
7315                         memset (orig_code, 0, code - orig_code);
7316
7317                         pos = cfg->native_code + patch_info->ip.i;
7318
7319                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7320                         if (IS_REX (pos [1]))
7321                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7322                         else
7323                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7324
7325                         *(gpointer*)code = (gpointer)patch_info->data.target;
7326                         code += sizeof (gpointer);
7327
7328                         remove = TRUE;
7329                         break;
7330                 }
7331                 default:
7332                         break;
7333                 }
7334
7335                 if (remove) {
7336                         if (patch_info == cfg->patch_info)
7337                                 cfg->patch_info = patch_info->next;
7338                         else {
7339                                 MonoJumpInfo *tmp;
7340
7341                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7342                                         ;
7343                                 tmp->next = patch_info->next;
7344                         }
7345                 }
7346                 g_assert (code < cfg->native_code + cfg->code_size);
7347         }
7348
7349         cfg->code_len = code - cfg->native_code;
7350
7351         g_assert (cfg->code_len < cfg->code_size);
7352
7353 }
7354
7355 #endif /* DISABLE_JIT */
7356
7357 void*
7358 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7359 {
7360         guchar *code = (guchar *)p;
7361         MonoMethodSignature *sig;
7362         MonoInst *inst;
7363         int i, n, stack_area = 0;
7364
7365         /* Keep this in sync with mono_arch_get_argument_info */
7366
7367         if (enable_arguments) {
7368                 /* Allocate a new area on the stack and save arguments there */
7369                 sig = mono_method_signature (cfg->method);
7370
7371                 n = sig->param_count + sig->hasthis;
7372
7373                 stack_area = ALIGN_TO (n * 8, 16);
7374
7375                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7376
7377                 for (i = 0; i < n; ++i) {
7378                         inst = cfg->args [i];
7379
7380                         if (inst->opcode == OP_REGVAR)
7381                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7382                         else {
7383                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7384                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7385                         }
7386                 }
7387         }
7388
7389         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7390         amd64_set_reg_template (code, AMD64_ARG_REG1);
7391         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7392         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7393
7394         if (enable_arguments)
7395                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7396
7397         return code;
7398 }
7399
7400 enum {
7401         SAVE_NONE,
7402         SAVE_STRUCT,
7403         SAVE_EAX,
7404         SAVE_EAX_EDX,
7405         SAVE_XMM
7406 };
7407
7408 void*
7409 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7410 {
7411         guchar *code = (guchar *)p;
7412         int save_mode = SAVE_NONE;
7413         MonoMethod *method = cfg->method;
7414         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7415         int i;
7416
7417         switch (ret_type->type) {
7418         case MONO_TYPE_VOID:
7419                 /* special case string .ctor icall */
7420                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7421                         save_mode = SAVE_EAX;
7422                 else
7423                         save_mode = SAVE_NONE;
7424                 break;
7425         case MONO_TYPE_I8:
7426         case MONO_TYPE_U8:
7427                 save_mode = SAVE_EAX;
7428                 break;
7429         case MONO_TYPE_R4:
7430         case MONO_TYPE_R8:
7431                 save_mode = SAVE_XMM;
7432                 break;
7433         case MONO_TYPE_GENERICINST:
7434                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7435                         save_mode = SAVE_EAX;
7436                         break;
7437                 }
7438                 /* Fall through */
7439         case MONO_TYPE_VALUETYPE:
7440                 save_mode = SAVE_STRUCT;
7441                 break;
7442         default:
7443                 save_mode = SAVE_EAX;
7444                 break;
7445         }
7446
7447         /* Save the result and copy it into the proper argument register */
7448         switch (save_mode) {
7449         case SAVE_EAX:
7450                 amd64_push_reg (code, AMD64_RAX);
7451                 /* Align stack */
7452                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7453                 if (enable_arguments)
7454                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7455                 break;
7456         case SAVE_STRUCT:
7457                 /* FIXME: */
7458                 if (enable_arguments)
7459                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7460                 break;
7461         case SAVE_XMM:
7462                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7463                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7464                 /* Align stack */
7465                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7466                 /*
7467                  * The result is already in the proper argument register so no copying
7468                  * needed.
7469                  */
7470                 break;
7471         case SAVE_NONE:
7472                 break;
7473         default:
7474                 g_assert_not_reached ();
7475         }
7476
7477         /* Set %al since this is a varargs call */
7478         if (save_mode == SAVE_XMM)
7479                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7480         else
7481                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7482
7483         if (preserve_argument_registers) {
7484                 for (i = 0; i < PARAM_REGS; ++i)
7485                         amd64_push_reg (code, param_regs [i]);
7486         }
7487
7488         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7489         amd64_set_reg_template (code, AMD64_ARG_REG1);
7490         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7491
7492         if (preserve_argument_registers) {
7493                 for (i = PARAM_REGS - 1; i >= 0; --i)
7494                         amd64_pop_reg (code, param_regs [i]);
7495         }
7496
7497         /* Restore result */
7498         switch (save_mode) {
7499         case SAVE_EAX:
7500                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7501                 amd64_pop_reg (code, AMD64_RAX);
7502                 break;
7503         case SAVE_STRUCT:
7504                 /* FIXME: */
7505                 break;
7506         case SAVE_XMM:
7507                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7508                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7509                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7510                 break;
7511         case SAVE_NONE:
7512                 break;
7513         default:
7514                 g_assert_not_reached ();
7515         }
7516
7517         return code;
7518 }
7519
7520 void
7521 mono_arch_flush_icache (guint8 *code, gint size)
7522 {
7523         /* Not needed */
7524 }
7525
7526 void
7527 mono_arch_flush_register_windows (void)
7528 {
7529 }
7530
7531 gboolean
7532 mono_arch_is_inst_imm (gint64 imm)
7533 {
7534         return amd64_use_imm32 (imm);
7535 }
7536
7537 /*
7538  * Determine whenever the trap whose info is in SIGINFO is caused by
7539  * integer overflow.
7540  */
7541 gboolean
7542 mono_arch_is_int_overflow (void *sigctx, void *info)
7543 {
7544         MonoContext ctx;
7545         guint8* rip;
7546         int reg;
7547         gint64 value;
7548
7549         mono_sigctx_to_monoctx (sigctx, &ctx);
7550
7551         rip = (guint8*)ctx.gregs [AMD64_RIP];
7552
7553         if (IS_REX (rip [0])) {
7554                 reg = amd64_rex_b (rip [0]);
7555                 rip ++;
7556         }
7557         else
7558                 reg = 0;
7559
7560         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7561                 /* idiv REG */
7562                 reg += x86_modrm_rm (rip [1]);
7563
7564                 value = ctx.gregs [reg];
7565
7566                 if (value == -1)
7567                         return TRUE;
7568         }
7569
7570         return FALSE;
7571 }
7572
7573 guint32
7574 mono_arch_get_patch_offset (guint8 *code)
7575 {
7576         return 3;
7577 }
7578
7579 /**
7580  * \return TRUE if no sw breakpoint was present.
7581  *
7582  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7583  * breakpoints in the original code, they are removed in the copy.
7584  */
7585 gboolean
7586 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7587 {
7588         /*
7589          * If method_start is non-NULL we need to perform bound checks, since we access memory
7590          * at code - offset we could go before the start of the method and end up in a different
7591          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7592          * instead.
7593          */
7594         if (!method_start || code - offset >= method_start) {
7595                 memcpy (buf, code - offset, size);
7596         } else {
7597                 int diff = code - method_start;
7598                 memset (buf, 0, size);
7599                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7600         }
7601         return TRUE;
7602 }
7603
7604 int
7605 mono_arch_get_this_arg_reg (guint8 *code)
7606 {
7607         return AMD64_ARG_REG1;
7608 }
7609
7610 gpointer
7611 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7612 {
7613         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7614 }
7615
7616 #define MAX_ARCH_DELEGATE_PARAMS 10
7617
7618 static gpointer
7619 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7620 {
7621         guint8 *code, *start;
7622         GSList *unwind_ops = NULL;
7623         int i;
7624
7625         unwind_ops = mono_arch_get_cie_program ();
7626
7627         if (has_target) {
7628                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7629
7630                 /* Replace the this argument with the target */
7631                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7632                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7633                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7634
7635                 g_assert ((code - start) < 64);
7636                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7637         } else {
7638                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7639
7640                 if (param_count == 0) {
7641                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7642                 } else {
7643                         /* We have to shift the arguments left */
7644                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7645                         for (i = 0; i < param_count; ++i) {
7646 #ifdef TARGET_WIN32
7647                                 if (i < 3)
7648                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7649                                 else
7650                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7651 #else
7652                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7653 #endif
7654                         }
7655
7656                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7657                 }
7658                 g_assert ((code - start) < 64);
7659                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7660         }
7661
7662         mono_arch_flush_icache (start, code - start);
7663
7664         if (has_target) {
7665                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7666         } else {
7667                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7668                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7669                 g_free (name);
7670         }
7671
7672         if (mono_jit_map_is_enabled ()) {
7673                 char *buff;
7674                 if (has_target)
7675                         buff = (char*)"delegate_invoke_has_target";
7676                 else
7677                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7678                 mono_emit_jit_tramp (start, code - start, buff);
7679                 if (!has_target)
7680                         g_free (buff);
7681         }
7682         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7683
7684         return start;
7685 }
7686
7687 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7688
7689 static gpointer
7690 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7691 {
7692         guint8 *code, *start;
7693         int size = 20;
7694         char *tramp_name;
7695         GSList *unwind_ops;
7696
7697         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7698                 return NULL;
7699
7700         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7701
7702         unwind_ops = mono_arch_get_cie_program ();
7703
7704         /* Replace the this argument with the target */
7705         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7706         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7707
7708         if (load_imt_reg) {
7709                 /* Load the IMT reg */
7710                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7711         }
7712
7713         /* Load the vtable */
7714         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7715         amd64_jump_membase (code, AMD64_RAX, offset);
7716         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7717
7718         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7719         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7720         g_free (tramp_name);
7721
7722         return start;
7723 }
7724
7725 /*
7726  * mono_arch_get_delegate_invoke_impls:
7727  *
7728  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7729  * trampolines.
7730  */
7731 GSList*
7732 mono_arch_get_delegate_invoke_impls (void)
7733 {
7734         GSList *res = NULL;
7735         MonoTrampInfo *info;
7736         int i;
7737
7738         get_delegate_invoke_impl (&info, TRUE, 0);
7739         res = g_slist_prepend (res, info);
7740
7741         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7742                 get_delegate_invoke_impl (&info, FALSE, i);
7743                 res = g_slist_prepend (res, info);
7744         }
7745
7746         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7747                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7748                 res = g_slist_prepend (res, info);
7749         }
7750
7751         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7752                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7753                 res = g_slist_prepend (res, info);
7754                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7755                 res = g_slist_prepend (res, info);
7756         }
7757
7758         return res;
7759 }
7760
7761 gpointer
7762 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7763 {
7764         guint8 *code, *start;
7765         int i;
7766
7767         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7768                 return NULL;
7769
7770         /* FIXME: Support more cases */
7771         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7772                 return NULL;
7773
7774         if (has_target) {
7775                 static guint8* cached = NULL;
7776
7777                 if (cached)
7778                         return cached;
7779
7780                 if (mono_aot_only) {
7781                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7782                 } else {
7783                         MonoTrampInfo *info;
7784                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7785                         mono_tramp_info_register (info, NULL);
7786                 }
7787
7788                 mono_memory_barrier ();
7789
7790                 cached = start;
7791         } else {
7792                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7793                 for (i = 0; i < sig->param_count; ++i)
7794                         if (!mono_is_regsize_var (sig->params [i]))
7795                                 return NULL;
7796                 if (sig->param_count > 4)
7797                         return NULL;
7798
7799                 code = cache [sig->param_count];
7800                 if (code)
7801                         return code;
7802
7803                 if (mono_aot_only) {
7804                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7805                         start = (guint8 *)mono_aot_get_trampoline (name);
7806                         g_free (name);
7807                 } else {
7808                         MonoTrampInfo *info;
7809                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7810                         mono_tramp_info_register (info, NULL);
7811                 }
7812
7813                 mono_memory_barrier ();
7814
7815                 cache [sig->param_count] = start;
7816         }
7817
7818         return start;
7819 }
7820
7821 gpointer
7822 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7823 {
7824         MonoTrampInfo *info;
7825         gpointer code;
7826
7827         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7828         if (code)
7829                 mono_tramp_info_register (info, NULL);
7830         return code;
7831 }
7832
7833 void
7834 mono_arch_finish_init (void)
7835 {
7836 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7837         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7838 #endif
7839 }
7840
7841 void
7842 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7843 {
7844 }
7845
7846 #define CMP_SIZE (6 + 1)
7847 #define CMP_REG_REG_SIZE (4 + 1)
7848 #define BR_SMALL_SIZE 2
7849 #define BR_LARGE_SIZE 6
7850 #define MOV_REG_IMM_SIZE 10
7851 #define MOV_REG_IMM_32BIT_SIZE 6
7852 #define JUMP_REG_SIZE (2 + 1)
7853
7854 static int
7855 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7856 {
7857         int i, distance = 0;
7858         for (i = start; i < target; ++i)
7859                 distance += imt_entries [i]->chunk_size;
7860         return distance;
7861 }
7862
7863 /*
7864  * LOCKING: called with the domain lock held
7865  */
7866 gpointer
7867 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7868         gpointer fail_tramp)
7869 {
7870         int i;
7871         int size = 0;
7872         guint8 *code, *start;
7873         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7874         GSList *unwind_ops;
7875
7876         for (i = 0; i < count; ++i) {
7877                 MonoIMTCheckItem *item = imt_entries [i];
7878                 if (item->is_equals) {
7879                         if (item->check_target_idx) {
7880                                 if (!item->compare_done) {
7881                                         if (amd64_use_imm32 ((gint64)item->key))
7882                                                 item->chunk_size += CMP_SIZE;
7883                                         else
7884                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7885                                 }
7886                                 if (item->has_target_code) {
7887                                         item->chunk_size += MOV_REG_IMM_SIZE;
7888                                 } else {
7889                                         if (vtable_is_32bit)
7890                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7891                                         else
7892                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7893                                 }
7894                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7895                         } else {
7896                                 if (fail_tramp) {
7897                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7898                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7899                                 } else {
7900                                         if (vtable_is_32bit)
7901                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7902                                         else
7903                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7904                                         item->chunk_size += JUMP_REG_SIZE;
7905                                         /* with assert below:
7906                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7907                                          */
7908                                 }
7909                         }
7910                 } else {
7911                         if (amd64_use_imm32 ((gint64)item->key))
7912                                 item->chunk_size += CMP_SIZE;
7913                         else
7914                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7915                         item->chunk_size += BR_LARGE_SIZE;
7916                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7917                 }
7918                 size += item->chunk_size;
7919         }
7920         if (fail_tramp)
7921                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7922         else
7923                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7924         start = code;
7925
7926         unwind_ops = mono_arch_get_cie_program ();
7927
7928         for (i = 0; i < count; ++i) {
7929                 MonoIMTCheckItem *item = imt_entries [i];
7930                 item->code_target = code;
7931                 if (item->is_equals) {
7932                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7933
7934                         if (item->check_target_idx || fail_case) {
7935                                 if (!item->compare_done || fail_case) {
7936                                         if (amd64_use_imm32 ((gint64)item->key))
7937                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7938                                         else {
7939                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7940                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7941                                         }
7942                                 }
7943                                 item->jmp_code = code;
7944                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7945                                 if (item->has_target_code) {
7946                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7947                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7948                                 } else {
7949                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7950                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7951                                 }
7952
7953                                 if (fail_case) {
7954                                         amd64_patch (item->jmp_code, code);
7955                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7956                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7957                                         item->jmp_code = NULL;
7958                                 }
7959                         } else {
7960                                 /* enable the commented code to assert on wrong method */
7961 #if 0
7962                                 if (amd64_is_imm32 (item->key))
7963                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7964                                 else {
7965                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7966                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7967                                 }
7968                                 item->jmp_code = code;
7969                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7970                                 /* See the comment below about R10 */
7971                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7972                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7973                                 amd64_patch (item->jmp_code, code);
7974                                 amd64_breakpoint (code);
7975                                 item->jmp_code = NULL;
7976 #else
7977                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7978                                    needs to be preserved.  R10 needs
7979                                    to be preserved for calls which
7980                                    require a runtime generic context,
7981                                    but interface calls don't. */
7982                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7983                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7984 #endif
7985                         }
7986                 } else {
7987                         if (amd64_use_imm32 ((gint64)item->key))
7988                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7989                         else {
7990                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7991                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7992                         }
7993                         item->jmp_code = code;
7994                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7995                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7996                         else
7997                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7998                 }
7999                 g_assert (code - item->code_target <= item->chunk_size);
8000         }
8001         /* patch the branches to get to the target items */
8002         for (i = 0; i < count; ++i) {
8003                 MonoIMTCheckItem *item = imt_entries [i];
8004                 if (item->jmp_code) {
8005                         if (item->check_target_idx) {
8006                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8007                         }
8008                 }
8009         }
8010
8011         if (!fail_tramp)
8012                 mono_stats.imt_trampolines_size += code - start;
8013         g_assert (code - start <= size);
8014         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8015
8016         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8017
8018         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8019
8020         return start;
8021 }
8022
8023 MonoMethod*
8024 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8025 {
8026         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8027 }
8028
8029 MonoVTable*
8030 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8031 {
8032         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8033 }
8034
8035 GSList*
8036 mono_arch_get_cie_program (void)
8037 {
8038         GSList *l = NULL;
8039
8040         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8041         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8042
8043         return l;
8044 }
8045
8046 #ifndef DISABLE_JIT
8047
8048 MonoInst*
8049 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8050 {
8051         MonoInst *ins = NULL;
8052         int opcode = 0;
8053
8054         if (cmethod->klass == mono_defaults.math_class) {
8055                 if (strcmp (cmethod->name, "Sin") == 0) {
8056                         opcode = OP_SIN;
8057                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8058                         opcode = OP_COS;
8059                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8060                         opcode = OP_SQRT;
8061                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8062                         opcode = OP_ABS;
8063                 }
8064
8065                 if (opcode && fsig->param_count == 1) {
8066                         MONO_INST_NEW (cfg, ins, opcode);
8067                         ins->type = STACK_R8;
8068                         ins->dreg = mono_alloc_freg (cfg);
8069                         ins->sreg1 = args [0]->dreg;
8070                         MONO_ADD_INS (cfg->cbb, ins);
8071                 }
8072
8073                 opcode = 0;
8074                 if (cfg->opt & MONO_OPT_CMOV) {
8075                         if (strcmp (cmethod->name, "Min") == 0) {
8076                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8077                                         opcode = OP_IMIN;
8078                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8079                                         opcode = OP_IMIN_UN;
8080                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8081                                         opcode = OP_LMIN;
8082                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8083                                         opcode = OP_LMIN_UN;
8084                         } else if (strcmp (cmethod->name, "Max") == 0) {
8085                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8086                                         opcode = OP_IMAX;
8087                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8088                                         opcode = OP_IMAX_UN;
8089                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8090                                         opcode = OP_LMAX;
8091                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8092                                         opcode = OP_LMAX_UN;
8093                         }
8094                 }
8095
8096                 if (opcode && fsig->param_count == 2) {
8097                         MONO_INST_NEW (cfg, ins, opcode);
8098                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8099                         ins->dreg = mono_alloc_ireg (cfg);
8100                         ins->sreg1 = args [0]->dreg;
8101                         ins->sreg2 = args [1]->dreg;
8102                         MONO_ADD_INS (cfg->cbb, ins);
8103                 }
8104
8105 #if 0
8106                 /* OP_FREM is not IEEE compatible */
8107                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8108                         MONO_INST_NEW (cfg, ins, OP_FREM);
8109                         ins->inst_i0 = args [0];
8110                         ins->inst_i1 = args [1];
8111                 }
8112 #endif
8113         }
8114
8115         return ins;
8116 }
8117 #endif
8118
8119 gboolean
8120 mono_arch_print_tree (MonoInst *tree, int arity)
8121 {
8122         return 0;
8123 }
8124
8125 mgreg_t
8126 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8127 {
8128         return ctx->gregs [reg];
8129 }
8130
8131 void
8132 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8133 {
8134         ctx->gregs [reg] = val;
8135 }
8136
8137 gpointer
8138 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8139 {
8140         gpointer *sp, old_value;
8141         char *bp;
8142
8143         /*Load the spvar*/
8144         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8145         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8146
8147         old_value = *sp;
8148         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8149                 return old_value;
8150
8151         *sp = new_value;
8152
8153         return old_value;
8154 }
8155
8156 /*
8157  * mono_arch_emit_load_aotconst:
8158  *
8159  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8160  * TARGET from the mscorlib GOT in full-aot code.
8161  * On AMD64, the result is placed into R11.
8162  */
8163 guint8*
8164 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8165 {
8166         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8167         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8168
8169         return code;
8170 }
8171
8172 /*
8173  * mono_arch_get_trampolines:
8174  *
8175  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8176  * for AOT.
8177  */
8178 GSList *
8179 mono_arch_get_trampolines (gboolean aot)
8180 {
8181         return mono_amd64_get_exception_trampolines (aot);
8182 }
8183
8184 /* Soft Debug support */
8185 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8186
8187 /*
8188  * mono_arch_set_breakpoint:
8189  *
8190  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8191  * The location should contain code emitted by OP_SEQ_POINT.
8192  */
8193 void
8194 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8195 {
8196         guint8 *code = ip;
8197
8198         if (ji->from_aot) {
8199                 guint32 native_offset = ip - (guint8*)ji->code_start;
8200                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8201
8202                 g_assert (info->bp_addrs [native_offset] == 0);
8203                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8204         } else {
8205                 /* ip points to a mov r11, 0 */
8206                 g_assert (code [0] == 0x41);
8207                 g_assert (code [1] == 0xbb);
8208                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8209         }
8210 }
8211
8212 /*
8213  * mono_arch_clear_breakpoint:
8214  *
8215  *   Clear the breakpoint at IP.
8216  */
8217 void
8218 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8219 {
8220         guint8 *code = ip;
8221
8222         if (ji->from_aot) {
8223                 guint32 native_offset = ip - (guint8*)ji->code_start;
8224                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8225
8226                 info->bp_addrs [native_offset] = NULL;
8227         } else {
8228                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8229         }
8230 }
8231
8232 gboolean
8233 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8234 {
8235         /* We use soft breakpoints on amd64 */
8236         return FALSE;
8237 }
8238
8239 /*
8240  * mono_arch_skip_breakpoint:
8241  *
8242  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8243  * we resume, the instruction is not executed again.
8244  */
8245 void
8246 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8247 {
8248         g_assert_not_reached ();
8249 }
8250
8251 /*
8252  * mono_arch_start_single_stepping:
8253  *
8254  *   Start single stepping.
8255  */
8256 void
8257 mono_arch_start_single_stepping (void)
8258 {
8259         ss_trampoline = mini_get_single_step_trampoline ();
8260 }
8261
8262 /*
8263  * mono_arch_stop_single_stepping:
8264  *
8265  *   Stop single stepping.
8266  */
8267 void
8268 mono_arch_stop_single_stepping (void)
8269 {
8270         ss_trampoline = NULL;
8271 }
8272
8273 /*
8274  * mono_arch_is_single_step_event:
8275  *
8276  *   Return whenever the machine state in SIGCTX corresponds to a single
8277  * step event.
8278  */
8279 gboolean
8280 mono_arch_is_single_step_event (void *info, void *sigctx)
8281 {
8282         /* We use soft breakpoints on amd64 */
8283         return FALSE;
8284 }
8285
8286 /*
8287  * mono_arch_skip_single_step:
8288  *
8289  *   Modify CTX so the ip is placed after the single step trigger instruction,
8290  * we resume, the instruction is not executed again.
8291  */
8292 void
8293 mono_arch_skip_single_step (MonoContext *ctx)
8294 {
8295         g_assert_not_reached ();
8296 }
8297
8298 /*
8299  * mono_arch_create_seq_point_info:
8300  *
8301  *   Return a pointer to a data structure which is used by the sequence
8302  * point implementation in AOTed code.
8303  */
8304 gpointer
8305 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8306 {
8307         SeqPointInfo *info;
8308         MonoJitInfo *ji;
8309
8310         // FIXME: Add a free function
8311
8312         mono_domain_lock (domain);
8313         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8314                                                                 code);
8315         mono_domain_unlock (domain);
8316
8317         if (!info) {
8318                 ji = mono_jit_info_table_find (domain, (char*)code);
8319                 g_assert (ji);
8320
8321                 // FIXME: Optimize the size
8322                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8323
8324                 info->ss_tramp_addr = &ss_trampoline;
8325
8326                 mono_domain_lock (domain);
8327                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8328                                                          code, info);
8329                 mono_domain_unlock (domain);
8330         }
8331
8332         return info;
8333 }
8334
8335 void
8336 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8337 {
8338         ext->lmf.previous_lmf = prev_lmf;
8339         /* Mark that this is a MonoLMFExt */
8340         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8341         ext->lmf.rsp = (gssize)ext;
8342 }
8343
8344 #endif
8345
8346 gboolean
8347 mono_arch_opcode_supported (int opcode)
8348 {
8349         switch (opcode) {
8350         case OP_ATOMIC_ADD_I4:
8351         case OP_ATOMIC_ADD_I8:
8352         case OP_ATOMIC_EXCHANGE_I4:
8353         case OP_ATOMIC_EXCHANGE_I8:
8354         case OP_ATOMIC_CAS_I4:
8355         case OP_ATOMIC_CAS_I8:
8356         case OP_ATOMIC_LOAD_I1:
8357         case OP_ATOMIC_LOAD_I2:
8358         case OP_ATOMIC_LOAD_I4:
8359         case OP_ATOMIC_LOAD_I8:
8360         case OP_ATOMIC_LOAD_U1:
8361         case OP_ATOMIC_LOAD_U2:
8362         case OP_ATOMIC_LOAD_U4:
8363         case OP_ATOMIC_LOAD_U8:
8364         case OP_ATOMIC_LOAD_R4:
8365         case OP_ATOMIC_LOAD_R8:
8366         case OP_ATOMIC_STORE_I1:
8367         case OP_ATOMIC_STORE_I2:
8368         case OP_ATOMIC_STORE_I4:
8369         case OP_ATOMIC_STORE_I8:
8370         case OP_ATOMIC_STORE_U1:
8371         case OP_ATOMIC_STORE_U2:
8372         case OP_ATOMIC_STORE_U4:
8373         case OP_ATOMIC_STORE_U8:
8374         case OP_ATOMIC_STORE_R4:
8375         case OP_ATOMIC_STORE_R8:
8376                 return TRUE;
8377         default:
8378                 return FALSE;
8379         }
8380 }
8381
8382 CallInfo*
8383 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8384 {
8385         return get_call_info (mp, sig);
8386 }