mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_replace_type (callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoMethodHeader *header;
1653         MonoInst *ins;
1654         int i;
1655         CallInfo *cinfo;
1656
1657         header = cfg->header;
1658
1659         sig = mono_method_signature (cfg->method);
1660
1661         cinfo = cfg->arch.cinfo;
1662         sig_ret = mini_replace_type (sig->ret);
1663
1664         /*
1665          * Contrary to mono_arch_allocate_vars (), the information should describe
1666          * where the arguments are at the beginning of the method, not where they can be
1667          * accessed during the execution of the method. The later makes no sense for the
1668          * global register allocator, since a variable can be in more than one location.
1669          */
1670         if (sig_ret->type != MONO_TYPE_VOID) {
1671                 switch (cinfo->ret.storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1676                                 cfg->vret_addr->opcode = OP_REGVAR;
1677                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1678                         }
1679                         else {
1680                                 cfg->ret->opcode = OP_REGVAR;
1681                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1682                         }
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         cfg->ret->opcode = OP_REGOFFSET;
1686                         cfg->ret->inst_basereg = -1;
1687                         cfg->ret->inst_offset = -1;
1688                         break;
1689                 default:
1690                         g_assert_not_reached ();
1691                 }
1692         }
1693
1694         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1695                 ArgInfo *ainfo = &cinfo->args [i];
1696                 MonoType *arg_type;
1697
1698                 ins = cfg->args [i];
1699
1700                 if (sig->hasthis && (i == 0))
1701                         arg_type = &mono_defaults.object_class->byval_arg;
1702                 else
1703                         arg_type = sig->params [i - sig->hasthis];
1704
1705                 switch (ainfo->storage) {
1706                 case ArgInIReg:
1707                 case ArgInFloatSSEReg:
1708                 case ArgInDoubleSSEReg:
1709                         ins->opcode = OP_REGVAR;
1710                         ins->inst_c0 = ainfo->reg;
1711                         break;
1712                 case ArgOnStack:
1713                         ins->opcode = OP_REGOFFSET;
1714                         ins->inst_basereg = -1;
1715                         ins->inst_offset = -1;
1716                         break;
1717                 case ArgValuetypeInReg:
1718                         /* Dummy */
1719                         ins->opcode = OP_NOP;
1720                         break;
1721                 default:
1722                         g_assert_not_reached ();
1723                 }
1724         }
1725 }
1726
1727 void
1728 mono_arch_allocate_vars (MonoCompile *cfg)
1729 {
1730         MonoType *sig_ret;
1731         MonoMethodSignature *sig;
1732         MonoMethodHeader *header;
1733         MonoInst *ins;
1734         int i, offset;
1735         guint32 locals_stack_size, locals_stack_align;
1736         gint32 *offsets;
1737         CallInfo *cinfo;
1738
1739         header = cfg->header;
1740
1741         sig = mono_method_signature (cfg->method);
1742
1743         cinfo = cfg->arch.cinfo;
1744         sig_ret = mini_replace_type (sig->ret);
1745
1746         mono_arch_compute_omit_fp (cfg);
1747
1748         /*
1749          * We use the ABI calling conventions for managed code as well.
1750          * Exception: valuetypes are only sometimes passed or returned in registers.
1751          */
1752
1753         /*
1754          * The stack looks like this:
1755          * <incoming arguments passed on the stack>
1756          * <return value>
1757          * <lmf/caller saved registers>
1758          * <locals>
1759          * <spill area>
1760          * <localloc area>  -> grows dynamically
1761          * <params area>
1762          */
1763
1764         if (cfg->arch.omit_fp) {
1765                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1766                 cfg->frame_reg = AMD64_RSP;
1767                 offset = 0;
1768         } else {
1769                 /* Locals are allocated backwards from %fp */
1770                 cfg->frame_reg = AMD64_RBP;
1771                 offset = 0;
1772         }
1773
1774         cfg->arch.saved_iregs = cfg->used_int_regs;
1775         if (cfg->method->save_lmf)
1776                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1777                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1778
1779         if (cfg->arch.omit_fp)
1780                 cfg->arch.reg_save_area_offset = offset;
1781         /* Reserve space for callee saved registers */
1782         for (i = 0; i < AMD64_NREG; ++i)
1783                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1784                         offset += sizeof(mgreg_t);
1785                 }
1786         if (!cfg->arch.omit_fp)
1787                 cfg->arch.reg_save_area_offset = -offset;
1788
1789         if (sig_ret->type != MONO_TYPE_VOID) {
1790                 switch (cinfo->ret.storage) {
1791                 case ArgInIReg:
1792                 case ArgInFloatSSEReg:
1793                 case ArgInDoubleSSEReg:
1794                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1795                                 if (cfg->globalra) {
1796                                         cfg->vret_addr->opcode = OP_REGVAR;
1797                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1798                                 } else {
1799                                         /* The register is volatile */
1800                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1801                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1802                                         if (cfg->arch.omit_fp) {
1803                                                 cfg->vret_addr->inst_offset = offset;
1804                                                 offset += 8;
1805                                         } else {
1806                                                 offset += 8;
1807                                                 cfg->vret_addr->inst_offset = -offset;
1808                                         }
1809                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1810                                                 printf ("vret_addr =");
1811                                                 mono_print_ins (cfg->vret_addr);
1812                                         }
1813                                 }
1814                         }
1815                         else {
1816                                 cfg->ret->opcode = OP_REGVAR;
1817                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1818                         }
1819                         break;
1820                 case ArgValuetypeInReg:
1821                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1822                         cfg->ret->opcode = OP_REGOFFSET;
1823                         cfg->ret->inst_basereg = cfg->frame_reg;
1824                         if (cfg->arch.omit_fp) {
1825                                 cfg->ret->inst_offset = offset;
1826                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1827                         } else {
1828                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1829                                 cfg->ret->inst_offset = - offset;
1830                         }
1831                         break;
1832                 default:
1833                         g_assert_not_reached ();
1834                 }
1835                 if (!cfg->globalra)
1836                         cfg->ret->dreg = cfg->ret->inst_c0;
1837         }
1838
1839         /* Allocate locals */
1840         if (!cfg->globalra) {
1841                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1842                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1843                         char *mname = mono_method_full_name (cfg->method, TRUE);
1844                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1845                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1846                         g_free (mname);
1847                         return;
1848                 }
1849
1850                 if (locals_stack_align) {
1851                         offset += (locals_stack_align - 1);
1852                         offset &= ~(locals_stack_align - 1);
1853                 }
1854                 if (cfg->arch.omit_fp) {
1855                         cfg->locals_min_stack_offset = offset;
1856                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1857                 } else {
1858                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1859                         cfg->locals_max_stack_offset = - offset;
1860                 }
1861
1862                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1863                         if (offsets [i] != -1) {
1864                                 MonoInst *ins = cfg->varinfo [i];
1865                                 ins->opcode = OP_REGOFFSET;
1866                                 ins->inst_basereg = cfg->frame_reg;
1867                                 if (cfg->arch.omit_fp)
1868                                         ins->inst_offset = (offset + offsets [i]);
1869                                 else
1870                                         ins->inst_offset = - (offset + offsets [i]);
1871                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1872                         }
1873                 }
1874                 offset += locals_stack_size;
1875         }
1876
1877         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1878                 g_assert (!cfg->arch.omit_fp);
1879                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1881         }
1882
1883         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1884                 ins = cfg->args [i];
1885                 if (ins->opcode != OP_REGVAR) {
1886                         ArgInfo *ainfo = &cinfo->args [i];
1887                         gboolean inreg = TRUE;
1888                         MonoType *arg_type;
1889
1890                         if (sig->hasthis && (i == 0))
1891                                 arg_type = &mono_defaults.object_class->byval_arg;
1892                         else
1893                                 arg_type = sig->params [i - sig->hasthis];
1894
1895                         if (cfg->globalra) {
1896                                 /* The new allocator needs info about the original locations of the arguments */
1897                                 switch (ainfo->storage) {
1898                                 case ArgInIReg:
1899                                 case ArgInFloatSSEReg:
1900                                 case ArgInDoubleSSEReg:
1901                                         ins->opcode = OP_REGVAR;
1902                                         ins->inst_c0 = ainfo->reg;
1903                                         break;
1904                                 case ArgOnStack:
1905                                         g_assert (!cfg->arch.omit_fp);
1906                                         ins->opcode = OP_REGOFFSET;
1907                                         ins->inst_basereg = cfg->frame_reg;
1908                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1909                                         break;
1910                                 case ArgValuetypeInReg:
1911                                         ins->opcode = OP_REGOFFSET;
1912                                         ins->inst_basereg = cfg->frame_reg;
1913                                         /* These arguments are saved to the stack in the prolog */
1914                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1915                                         if (cfg->arch.omit_fp) {
1916                                                 ins->inst_offset = offset;
1917                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1918                                         } else {
1919                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1920                                                 ins->inst_offset = - offset;
1921                                         }
1922                                         break;
1923                                 default:
1924                                         g_assert_not_reached ();
1925                                 }
1926
1927                                 continue;
1928                         }
1929
1930                         /* FIXME: Allocate volatile arguments to registers */
1931                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1932                                 inreg = FALSE;
1933
1934                         /*
1935                          * Under AMD64, all registers used to pass arguments to functions
1936                          * are volatile across calls.
1937                          * FIXME: Optimize this.
1938                          */
1939                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1940                                 inreg = FALSE;
1941
1942                         ins->opcode = OP_REGOFFSET;
1943
1944                         switch (ainfo->storage) {
1945                         case ArgInIReg:
1946                         case ArgInFloatSSEReg:
1947                         case ArgInDoubleSSEReg:
1948                                 if (inreg) {
1949                                         ins->opcode = OP_REGVAR;
1950                                         ins->dreg = ainfo->reg;
1951                                 }
1952                                 break;
1953                         case ArgOnStack:
1954                                 g_assert (!cfg->arch.omit_fp);
1955                                 ins->opcode = OP_REGOFFSET;
1956                                 ins->inst_basereg = cfg->frame_reg;
1957                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 break;
1959                         case ArgValuetypeInReg:
1960                                 break;
1961                         case ArgValuetypeAddrInIReg: {
1962                                 MonoInst *indir;
1963                                 g_assert (!cfg->arch.omit_fp);
1964
1965                                 MONO_INST_NEW (cfg, indir, 0);
1966                                 indir->opcode = OP_REGOFFSET;
1967                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1968                                         indir->inst_basereg = cfg->frame_reg;
1969                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1970                                         offset += (sizeof (gpointer));
1971                                         indir->inst_offset = - offset;
1972                                 }
1973                                 else {
1974                                         indir->inst_basereg = cfg->frame_reg;
1975                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1976                                 }
1977
1978                                 ins->opcode = OP_VTARG_ADDR;
1979                                 ins->inst_left = indir;
1980
1981                                 break;
1982                         }
1983                         default:
1984                                 NOT_IMPLEMENTED;
1985                         }
1986
1987                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1988                                 ins->opcode = OP_REGOFFSET;
1989                                 ins->inst_basereg = cfg->frame_reg;
1990                                 /* These arguments are saved to the stack in the prolog */
1991                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1992                                 if (cfg->arch.omit_fp) {
1993                                         ins->inst_offset = offset;
1994                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1995                                         // Arguments are yet supported by the stack map creation code
1996                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1997                                 } else {
1998                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1999                                         ins->inst_offset = - offset;
2000                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2001                                 }
2002                         }
2003                 }
2004         }
2005
2006         cfg->stack_offset = offset;
2007 }
2008
2009 void
2010 mono_arch_create_vars (MonoCompile *cfg)
2011 {
2012         MonoMethodSignature *sig;
2013         CallInfo *cinfo;
2014         MonoType *sig_ret;
2015
2016         sig = mono_method_signature (cfg->method);
2017
2018         if (!cfg->arch.cinfo)
2019                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2020         cinfo = cfg->arch.cinfo;
2021
2022         if (cinfo->ret.storage == ArgValuetypeInReg)
2023                 cfg->ret_var_is_local = TRUE;
2024
2025         sig_ret = mini_replace_type (sig->ret);
2026         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2027                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2028                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2029                         printf ("vret_addr = ");
2030                         mono_print_ins (cfg->vret_addr);
2031                 }
2032         }
2033
2034         if (cfg->gen_seq_points_debug_data) {
2035                 MonoInst *ins;
2036
2037                 if (cfg->compile_aot) {
2038                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2039                         ins->flags |= MONO_INST_VOLATILE;
2040                         cfg->arch.seq_point_info_var = ins;
2041                 }
2042
2043             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2044                 ins->flags |= MONO_INST_VOLATILE;
2045                 cfg->arch.ss_trigger_page_var = ins;
2046         }
2047
2048         if (cfg->method->save_lmf)
2049                 cfg->create_lmf_var = TRUE;
2050
2051         if (cfg->method->save_lmf) {
2052                 cfg->lmf_ir = TRUE;
2053 #if !defined(HOST_WIN32)
2054                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2055                         cfg->lmf_ir_mono_lmf = TRUE;
2056 #endif
2057         }
2058 }
2059
2060 static void
2061 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2062 {
2063         MonoInst *ins;
2064
2065         switch (storage) {
2066         case ArgInIReg:
2067                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2068                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2069                 ins->sreg1 = tree->dreg;
2070                 MONO_ADD_INS (cfg->cbb, ins);
2071                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2072                 break;
2073         case ArgInFloatSSEReg:
2074                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2075                 ins->dreg = mono_alloc_freg (cfg);
2076                 ins->sreg1 = tree->dreg;
2077                 MONO_ADD_INS (cfg->cbb, ins);
2078
2079                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2080                 break;
2081         case ArgInDoubleSSEReg:
2082                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2083                 ins->dreg = mono_alloc_freg (cfg);
2084                 ins->sreg1 = tree->dreg;
2085                 MONO_ADD_INS (cfg->cbb, ins);
2086
2087                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2088
2089                 break;
2090         default:
2091                 g_assert_not_reached ();
2092         }
2093 }
2094
2095 static int
2096 arg_storage_to_load_membase (ArgStorage storage)
2097 {
2098         switch (storage) {
2099         case ArgInIReg:
2100 #if defined(__mono_ilp32__)
2101                 return OP_LOADI8_MEMBASE;
2102 #else
2103                 return OP_LOAD_MEMBASE;
2104 #endif
2105         case ArgInDoubleSSEReg:
2106                 return OP_LOADR8_MEMBASE;
2107         case ArgInFloatSSEReg:
2108                 return OP_LOADR4_MEMBASE;
2109         default:
2110                 g_assert_not_reached ();
2111         }
2112
2113         return -1;
2114 }
2115
2116 static void
2117 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2118 {
2119         MonoMethodSignature *tmp_sig;
2120         int sig_reg;
2121
2122         if (call->tail_call)
2123                 NOT_IMPLEMENTED;
2124
2125         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2126
2127         /*
2128          * mono_ArgIterator_Setup assumes the signature cookie is
2129          * passed first and all the arguments which were before it are
2130          * passed on the stack after the signature. So compensate by
2131          * passing a different signature.
2132          */
2133         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2134         tmp_sig->param_count -= call->signature->sentinelpos;
2135         tmp_sig->sentinelpos = 0;
2136         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2137
2138         sig_reg = mono_alloc_ireg (cfg);
2139         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2140
2141         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2142 }
2143
2144 static inline LLVMArgStorage
2145 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2146 {
2147         switch (storage) {
2148         case ArgInIReg:
2149                 return LLVMArgInIReg;
2150         case ArgNone:
2151                 return LLVMArgNone;
2152         default:
2153                 g_assert_not_reached ();
2154                 return LLVMArgNone;
2155         }
2156 }
2157
2158 #ifdef ENABLE_LLVM
2159 LLVMCallInfo*
2160 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2161 {
2162         int i, n;
2163         CallInfo *cinfo;
2164         ArgInfo *ainfo;
2165         int j;
2166         LLVMCallInfo *linfo;
2167         MonoType *t, *sig_ret;
2168
2169         n = sig->param_count + sig->hasthis;
2170         sig_ret = mini_replace_type (sig->ret);
2171
2172         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2173
2174         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2175
2176         /*
2177          * LLVM always uses the native ABI while we use our own ABI, the
2178          * only difference is the handling of vtypes:
2179          * - we only pass/receive them in registers in some cases, and only
2180          *   in 1 or 2 integer registers.
2181          */
2182         if (cinfo->ret.storage == ArgValuetypeInReg) {
2183                 if (sig->pinvoke) {
2184                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2185                         cfg->disable_llvm = TRUE;
2186                         return linfo;
2187                 }
2188
2189                 linfo->ret.storage = LLVMArgVtypeInReg;
2190                 for (j = 0; j < 2; ++j)
2191                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2192         }
2193
2194         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2195                 /* Vtype returned using a hidden argument */
2196                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2197                 linfo->vret_arg_index = cinfo->vret_arg_index;
2198         }
2199
2200         for (i = 0; i < n; ++i) {
2201                 ainfo = cinfo->args + i;
2202
2203                 if (i >= sig->hasthis)
2204                         t = sig->params [i - sig->hasthis];
2205                 else
2206                         t = &mono_defaults.int_class->byval_arg;
2207
2208                 linfo->args [i].storage = LLVMArgNone;
2209
2210                 switch (ainfo->storage) {
2211                 case ArgInIReg:
2212                         linfo->args [i].storage = LLVMArgInIReg;
2213                         break;
2214                 case ArgInDoubleSSEReg:
2215                 case ArgInFloatSSEReg:
2216                         linfo->args [i].storage = LLVMArgInFPReg;
2217                         break;
2218                 case ArgOnStack:
2219                         if (MONO_TYPE_ISSTRUCT (t)) {
2220                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2221                         } else {
2222                                 linfo->args [i].storage = LLVMArgInIReg;
2223                                 if (!t->byref) {
2224                                         if (t->type == MONO_TYPE_R4)
2225                                                 linfo->args [i].storage = LLVMArgInFPReg;
2226                                         else if (t->type == MONO_TYPE_R8)
2227                                                 linfo->args [i].storage = LLVMArgInFPReg;
2228                                 }
2229                         }
2230                         break;
2231                 case ArgValuetypeInReg:
2232                         if (sig->pinvoke) {
2233                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2234                                 cfg->disable_llvm = TRUE;
2235                                 return linfo;
2236                         }
2237
2238                         linfo->args [i].storage = LLVMArgVtypeInReg;
2239                         for (j = 0; j < 2; ++j)
2240                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2241                         break;
2242                 default:
2243                         cfg->exception_message = g_strdup ("ainfo->storage");
2244                         cfg->disable_llvm = TRUE;
2245                         break;
2246                 }
2247         }
2248
2249         return linfo;
2250 }
2251 #endif
2252
2253 void
2254 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2255 {
2256         MonoInst *arg, *in;
2257         MonoMethodSignature *sig;
2258         MonoType *sig_ret;
2259         int i, n, stack_size;
2260         CallInfo *cinfo;
2261         ArgInfo *ainfo;
2262
2263         stack_size = 0;
2264
2265         sig = call->signature;
2266         n = sig->param_count + sig->hasthis;
2267
2268         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2269
2270         sig_ret = sig->ret;
2271
2272         if (COMPILE_LLVM (cfg)) {
2273                 /* We shouldn't be called in the llvm case */
2274                 cfg->disable_llvm = TRUE;
2275                 return;
2276         }
2277
2278         /*
2279          * Emit all arguments which are passed on the stack to prevent register
2280          * allocation problems.
2281          */
2282         for (i = 0; i < n; ++i) {
2283                 MonoType *t;
2284                 ainfo = cinfo->args + i;
2285
2286                 in = call->args [i];
2287
2288                 if (sig->hasthis && i == 0)
2289                         t = &mono_defaults.object_class->byval_arg;
2290                 else
2291                         t = sig->params [i - sig->hasthis];
2292
2293                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2294                         if (!t->byref) {
2295                                 if (t->type == MONO_TYPE_R4)
2296                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                 else if (t->type == MONO_TYPE_R8)
2298                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 else
2300                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                         } else {
2302                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                         }
2304                         if (cfg->compute_gc_maps) {
2305                                 MonoInst *def;
2306
2307                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2308                         }
2309                 }
2310         }
2311
2312         /*
2313          * Emit all parameters passed in registers in non-reverse order for better readability
2314          * and to help the optimization in emit_prolog ().
2315          */
2316         for (i = 0; i < n; ++i) {
2317                 ainfo = cinfo->args + i;
2318
2319                 in = call->args [i];
2320
2321                 if (ainfo->storage == ArgInIReg)
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323         }
2324
2325         for (i = n - 1; i >= 0; --i) {
2326                 ainfo = cinfo->args + i;
2327
2328                 in = call->args [i];
2329
2330                 switch (ainfo->storage) {
2331                 case ArgInIReg:
2332                         /* Already done */
2333                         break;
2334                 case ArgInFloatSSEReg:
2335                 case ArgInDoubleSSEReg:
2336                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2337                         break;
2338                 case ArgOnStack:
2339                 case ArgValuetypeInReg:
2340                 case ArgValuetypeAddrInIReg:
2341                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2342                                 MonoInst *call_inst = (MonoInst*)call;
2343                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2344                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2345                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2346                                 guint32 align;
2347                                 guint32 size;
2348
2349                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2350                                         size = sizeof (MonoTypedRef);
2351                                         align = sizeof (gpointer);
2352                                 }
2353                                 else {
2354                                         if (sig->pinvoke)
2355                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2356                                         else {
2357                                                 /*
2358                                                  * Other backends use mono_type_stack_size (), but that
2359                                                  * aligns the size to 8, which is larger than the size of
2360                                                  * the source, leading to reads of invalid memory if the
2361                                                  * source is at the end of address space.
2362                                                  */
2363                                                 size = mono_class_value_size (in->klass, &align);
2364                                         }
2365                                 }
2366                                 g_assert (in->klass);
2367
2368                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2369                                         /* Avoid asserts in emit_memcpy () */
2370                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2371                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2372                                         /* Continue normally */
2373                                 }
2374
2375                                 if (size > 0) {
2376                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2377                                         arg->sreg1 = in->dreg;
2378                                         arg->klass = in->klass;
2379                                         arg->backend.size = size;
2380                                         arg->inst_p0 = call;
2381                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2383
2384                                         MONO_ADD_INS (cfg->cbb, arg);
2385                                 }
2386                         }
2387                         break;
2388                 default:
2389                         g_assert_not_reached ();
2390                 }
2391
2392                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2393                         /* Emit the signature cookie just before the implicit arguments */
2394                         emit_sig_cookie (cfg, call, cinfo);
2395         }
2396
2397         /* Handle the case where there are no implicit arguments */
2398         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2399                 emit_sig_cookie (cfg, call, cinfo);
2400
2401         sig_ret = mini_replace_type (sig->ret);
2402         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2403                 MonoInst *vtarg;
2404
2405                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2406                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2407                                 /*
2408                                  * Tell the JIT to use a more efficient calling convention: call using
2409                                  * OP_CALL, compute the result location after the call, and save the
2410                                  * result there.
2411                                  */
2412                                 call->vret_in_reg = TRUE;
2413                                 /*
2414                                  * Nullify the instruction computing the vret addr to enable
2415                                  * future optimizations.
2416                                  */
2417                                 if (call->vret_var)
2418                                         NULLIFY_INS (call->vret_var);
2419                         } else {
2420                                 if (call->tail_call)
2421                                         NOT_IMPLEMENTED;
2422                                 /*
2423                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2424                                  * the stack. Push the address here, so the call instruction can
2425                                  * access it.
2426                                  */
2427                                 if (!cfg->arch.vret_addr_loc) {
2428                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2429                                         /* Prevent it from being register allocated or optimized away */
2430                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2431                                 }
2432
2433                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2434                         }
2435                 }
2436                 else {
2437                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2438                         vtarg->sreg1 = call->vret_var->dreg;
2439                         vtarg->dreg = mono_alloc_preg (cfg);
2440                         MONO_ADD_INS (cfg->cbb, vtarg);
2441
2442                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2443                 }
2444         }
2445
2446         if (cfg->method->save_lmf) {
2447                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2448                 MONO_ADD_INS (cfg->cbb, arg);
2449         }
2450
2451         call->stack_usage = cinfo->stack_usage;
2452 }
2453
2454 void
2455 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2456 {
2457         MonoInst *arg;
2458         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2460         int size = ins->backend.size;
2461
2462         if (ainfo->storage == ArgValuetypeInReg) {
2463                 MonoInst *load;
2464                 int part;
2465
2466                 for (part = 0; part < 2; ++part) {
2467                         if (ainfo->pair_storage [part] == ArgNone)
2468                                 continue;
2469
2470                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2471                         load->inst_basereg = src->dreg;
2472                         load->inst_offset = part * sizeof(mgreg_t);
2473
2474                         switch (ainfo->pair_storage [part]) {
2475                         case ArgInIReg:
2476                                 load->dreg = mono_alloc_ireg (cfg);
2477                                 break;
2478                         case ArgInDoubleSSEReg:
2479                         case ArgInFloatSSEReg:
2480                                 load->dreg = mono_alloc_freg (cfg);
2481                                 break;
2482                         default:
2483                                 g_assert_not_reached ();
2484                         }
2485                         MONO_ADD_INS (cfg->cbb, load);
2486
2487                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2488                 }
2489         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2490                 MonoInst *vtaddr, *load;
2491                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2492
2493                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2494                 cfg->has_indirection = TRUE;
2495                 load->inst_p0 = vtaddr;
2496                 vtaddr->flags |= MONO_INST_INDIRECT;
2497                 load->type = STACK_MP;
2498                 load->klass = vtaddr->klass;
2499                 load->dreg = mono_alloc_ireg (cfg);
2500                 MONO_ADD_INS (cfg->cbb, load);
2501                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2502
2503                 if (ainfo->pair_storage [0] == ArgInIReg) {
2504                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2505                         arg->dreg = mono_alloc_ireg (cfg);
2506                         arg->sreg1 = load->dreg;
2507                         arg->inst_imm = 0;
2508                         MONO_ADD_INS (cfg->cbb, arg);
2509                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2510                 } else {
2511                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2512                 }
2513         } else {
2514                 if (size == 8) {
2515                         int dreg = mono_alloc_ireg (cfg);
2516
2517                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2518                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2519                 } else if (size <= 40) {
2520                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2521                 } else {
2522                         // FIXME: Code growth
2523                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2524                 }
2525
2526                 if (cfg->compute_gc_maps) {
2527                         MonoInst *def;
2528                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2529                 }
2530         }
2531 }
2532
2533 void
2534 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2535 {
2536         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2537
2538         if (ret->type == MONO_TYPE_R4) {
2539                 if (COMPILE_LLVM (cfg))
2540                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2541                 else
2542                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2543                 return;
2544         } else if (ret->type == MONO_TYPE_R8) {
2545                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2546                 return;
2547         }
2548
2549         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2550 }
2551
2552 #endif /* DISABLE_JIT */
2553
2554 #define EMIT_COND_BRANCH(ins,cond,sign) \
2555         if (ins->inst_true_bb->native_offset) { \
2556                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2557         } else { \
2558                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2559                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2560             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2561                         x86_branch8 (code, cond, 0, sign); \
2562                 else \
2563                         x86_branch32 (code, cond, 0, sign); \
2564 }
2565
2566 typedef struct {
2567         MonoMethodSignature *sig;
2568         CallInfo *cinfo;
2569 } ArchDynCallInfo;
2570
2571 static gboolean
2572 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2573 {
2574         int i;
2575
2576 #ifdef HOST_WIN32
2577         return FALSE;
2578 #endif
2579
2580         switch (cinfo->ret.storage) {
2581         case ArgNone:
2582         case ArgInIReg:
2583                 break;
2584         case ArgValuetypeInReg: {
2585                 ArgInfo *ainfo = &cinfo->ret;
2586
2587                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2588                         return FALSE;
2589                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2590                         return FALSE;
2591                 break;
2592         }
2593         default:
2594                 return FALSE;
2595         }
2596
2597         for (i = 0; i < cinfo->nargs; ++i) {
2598                 ArgInfo *ainfo = &cinfo->args [i];
2599                 switch (ainfo->storage) {
2600                 case ArgInIReg:
2601                         break;
2602                 case ArgValuetypeInReg:
2603                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2604                                 return FALSE;
2605                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2606                                 return FALSE;
2607                         break;
2608                 default:
2609                         return FALSE;
2610                 }
2611         }
2612
2613         return TRUE;
2614 }
2615
2616 /*
2617  * mono_arch_dyn_call_prepare:
2618  *
2619  *   Return a pointer to an arch-specific structure which contains information
2620  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2621  * supported for SIG.
2622  * This function is equivalent to ffi_prep_cif in libffi.
2623  */
2624 MonoDynCallInfo*
2625 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2626 {
2627         ArchDynCallInfo *info;
2628         CallInfo *cinfo;
2629
2630         cinfo = get_call_info (NULL, NULL, sig);
2631
2632         if (!dyn_call_supported (sig, cinfo)) {
2633                 g_free (cinfo);
2634                 return NULL;
2635         }
2636
2637         info = g_new0 (ArchDynCallInfo, 1);
2638         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2639         info->sig = sig;
2640         info->cinfo = cinfo;
2641
2642         return (MonoDynCallInfo*)info;
2643 }
2644
2645 /*
2646  * mono_arch_dyn_call_free:
2647  *
2648  *   Free a MonoDynCallInfo structure.
2649  */
2650 void
2651 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2652 {
2653         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2654
2655         g_free (ainfo->cinfo);
2656         g_free (ainfo);
2657 }
2658
2659 #if !defined(__native_client__)
2660 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2661 #define GREG_TO_PTR(greg) (gpointer)(greg)
2662 #else
2663 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2664 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2665 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2666 #endif
2667
2668 /*
2669  * mono_arch_get_start_dyn_call:
2670  *
2671  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2672  * store the result into BUF.
2673  * ARGS should be an array of pointers pointing to the arguments.
2674  * RET should point to a memory buffer large enought to hold the result of the
2675  * call.
2676  * This function should be as fast as possible, any work which does not depend
2677  * on the actual values of the arguments should be done in
2678  * mono_arch_dyn_call_prepare ().
2679  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2680  * libffi.
2681  */
2682 void
2683 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2684 {
2685         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2686         DynCallArgs *p = (DynCallArgs*)buf;
2687         int arg_index, greg, i, pindex;
2688         MonoMethodSignature *sig = dinfo->sig;
2689
2690         g_assert (buf_len >= sizeof (DynCallArgs));
2691
2692         p->res = 0;
2693         p->ret = ret;
2694
2695         arg_index = 0;
2696         greg = 0;
2697         pindex = 0;
2698
2699         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2700                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2701                 if (!sig->hasthis)
2702                         pindex = 1;
2703         }
2704
2705         if (dinfo->cinfo->vtype_retaddr)
2706                 p->regs [greg ++] = PTR_TO_GREG(ret);
2707
2708         for (i = pindex; i < sig->param_count; i++) {
2709                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2710                 gpointer *arg = args [arg_index ++];
2711
2712                 if (t->byref) {
2713                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2714                         continue;
2715                 }
2716
2717                 switch (t->type) {
2718                 case MONO_TYPE_STRING:
2719                 case MONO_TYPE_CLASS:
2720                 case MONO_TYPE_ARRAY:
2721                 case MONO_TYPE_SZARRAY:
2722                 case MONO_TYPE_OBJECT:
2723                 case MONO_TYPE_PTR:
2724                 case MONO_TYPE_I:
2725                 case MONO_TYPE_U:
2726 #if !defined(__mono_ilp32__)
2727                 case MONO_TYPE_I8:
2728                 case MONO_TYPE_U8:
2729 #endif
2730                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2731                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2732                         break;
2733 #if defined(__mono_ilp32__)
2734                 case MONO_TYPE_I8:
2735                 case MONO_TYPE_U8:
2736                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2737                         p->regs [greg ++] = *(guint64*)(arg);
2738                         break;
2739 #endif
2740                 case MONO_TYPE_BOOLEAN:
2741                 case MONO_TYPE_U1:
2742                         p->regs [greg ++] = *(guint8*)(arg);
2743                         break;
2744                 case MONO_TYPE_I1:
2745                         p->regs [greg ++] = *(gint8*)(arg);
2746                         break;
2747                 case MONO_TYPE_I2:
2748                         p->regs [greg ++] = *(gint16*)(arg);
2749                         break;
2750                 case MONO_TYPE_U2:
2751                 case MONO_TYPE_CHAR:
2752                         p->regs [greg ++] = *(guint16*)(arg);
2753                         break;
2754                 case MONO_TYPE_I4:
2755                         p->regs [greg ++] = *(gint32*)(arg);
2756                         break;
2757                 case MONO_TYPE_U4:
2758                         p->regs [greg ++] = *(guint32*)(arg);
2759                         break;
2760                 case MONO_TYPE_GENERICINST:
2761                     if (MONO_TYPE_IS_REFERENCE (t)) {
2762                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2763                                 break;
2764                         } else {
2765                                 /* Fall through */
2766                         }
2767                 case MONO_TYPE_VALUETYPE: {
2768                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2769
2770                         g_assert (ainfo->storage == ArgValuetypeInReg);
2771                         if (ainfo->pair_storage [0] != ArgNone) {
2772                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2773                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2774                         }
2775                         if (ainfo->pair_storage [1] != ArgNone) {
2776                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2777                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2778                         }
2779                         break;
2780                 }
2781                 default:
2782                         g_assert_not_reached ();
2783                 }
2784         }
2785
2786         g_assert (greg <= PARAM_REGS);
2787 }
2788
2789 /*
2790  * mono_arch_finish_dyn_call:
2791  *
2792  *   Store the result of a dyn call into the return value buffer passed to
2793  * start_dyn_call ().
2794  * This function should be as fast as possible, any work which does not depend
2795  * on the actual values of the arguments should be done in
2796  * mono_arch_dyn_call_prepare ().
2797  */
2798 void
2799 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2800 {
2801         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2802         MonoMethodSignature *sig = dinfo->sig;
2803         guint8 *ret = ((DynCallArgs*)buf)->ret;
2804         mgreg_t res = ((DynCallArgs*)buf)->res;
2805         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2806
2807         switch (sig_ret->type) {
2808         case MONO_TYPE_VOID:
2809                 *(gpointer*)ret = NULL;
2810                 break;
2811         case MONO_TYPE_STRING:
2812         case MONO_TYPE_CLASS:
2813         case MONO_TYPE_ARRAY:
2814         case MONO_TYPE_SZARRAY:
2815         case MONO_TYPE_OBJECT:
2816         case MONO_TYPE_I:
2817         case MONO_TYPE_U:
2818         case MONO_TYPE_PTR:
2819                 *(gpointer*)ret = GREG_TO_PTR(res);
2820                 break;
2821         case MONO_TYPE_I1:
2822                 *(gint8*)ret = res;
2823                 break;
2824         case MONO_TYPE_U1:
2825         case MONO_TYPE_BOOLEAN:
2826                 *(guint8*)ret = res;
2827                 break;
2828         case MONO_TYPE_I2:
2829                 *(gint16*)ret = res;
2830                 break;
2831         case MONO_TYPE_U2:
2832         case MONO_TYPE_CHAR:
2833                 *(guint16*)ret = res;
2834                 break;
2835         case MONO_TYPE_I4:
2836                 *(gint32*)ret = res;
2837                 break;
2838         case MONO_TYPE_U4:
2839                 *(guint32*)ret = res;
2840                 break;
2841         case MONO_TYPE_I8:
2842                 *(gint64*)ret = res;
2843                 break;
2844         case MONO_TYPE_U8:
2845                 *(guint64*)ret = res;
2846                 break;
2847         case MONO_TYPE_GENERICINST:
2848                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2849                         *(gpointer*)ret = GREG_TO_PTR(res);
2850                         break;
2851                 } else {
2852                         /* Fall through */
2853                 }
2854         case MONO_TYPE_VALUETYPE:
2855                 if (dinfo->cinfo->vtype_retaddr) {
2856                         /* Nothing to do */
2857                 } else {
2858                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2859
2860                         g_assert (ainfo->storage == ArgValuetypeInReg);
2861
2862                         if (ainfo->pair_storage [0] != ArgNone) {
2863                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2864                                 ((mgreg_t*)ret)[0] = res;
2865                         }
2866
2867                         g_assert (ainfo->pair_storage [1] == ArgNone);
2868                 }
2869                 break;
2870         default:
2871                 g_assert_not_reached ();
2872         }
2873 }
2874
2875 /* emit an exception if condition is fail */
2876 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2877         do {                                                        \
2878                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2879                 if (tins == NULL) {                                                                             \
2880                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2881                                         MONO_PATCH_INFO_EXC, exc_name);  \
2882                         x86_branch32 (code, cond, 0, signed);               \
2883                 } else {        \
2884                         EMIT_COND_BRANCH (tins, cond, signed);  \
2885                 }                       \
2886         } while (0);
2887
2888 #define EMIT_FPCOMPARE(code) do { \
2889         amd64_fcompp (code); \
2890         amd64_fnstsw (code); \
2891 } while (0);
2892
2893 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2894     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2895         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2896         amd64_ ##op (code); \
2897         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2898         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2899 } while (0);
2900
2901 static guint8*
2902 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2903 {
2904         gboolean no_patch = FALSE;
2905
2906         /*
2907          * FIXME: Add support for thunks
2908          */
2909         {
2910                 gboolean near_call = FALSE;
2911
2912                 /*
2913                  * Indirect calls are expensive so try to make a near call if possible.
2914                  * The caller memory is allocated by the code manager so it is
2915                  * guaranteed to be at a 32 bit offset.
2916                  */
2917
2918                 if (patch_type != MONO_PATCH_INFO_ABS) {
2919                         /* The target is in memory allocated using the code manager */
2920                         near_call = TRUE;
2921
2922                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2923                                 if (((MonoMethod*)data)->klass->image->aot_module)
2924                                         /* The callee might be an AOT method */
2925                                         near_call = FALSE;
2926                                 if (((MonoMethod*)data)->dynamic)
2927                                         /* The target is in malloc-ed memory */
2928                                         near_call = FALSE;
2929                         }
2930
2931                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2932                                 /*
2933                                  * The call might go directly to a native function without
2934                                  * the wrapper.
2935                                  */
2936                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2937                                 if (mi) {
2938                                         gconstpointer target = mono_icall_get_wrapper (mi);
2939                                         if ((((guint64)target) >> 32) != 0)
2940                                                 near_call = FALSE;
2941                                 }
2942                         }
2943                 }
2944                 else {
2945                         MonoJumpInfo *jinfo = NULL;
2946
2947                         if (cfg->abs_patches)
2948                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2949                         if (jinfo) {
2950                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2951                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2952                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2953                                                 near_call = TRUE;
2954                                         no_patch = TRUE;
2955                                 } else {
2956                                         /*
2957                                          * This is not really an optimization, but required because the
2958                                          * generic class init trampolines use R11 to pass the vtable.
2959                                          */
2960                                         near_call = TRUE;
2961                                 }
2962                         } else {
2963                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2964                                 if (info) {
2965                                         if (info->func == info->wrapper) {
2966                                                 /* No wrapper */
2967                                                 if ((((guint64)info->func) >> 32) == 0)
2968                                                         near_call = TRUE;
2969                                         }
2970                                         else {
2971                                                 /* See the comment in mono_codegen () */
2972                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2973                                                         near_call = TRUE;
2974                                         }
2975                                 }
2976                                 else if ((((guint64)data) >> 32) == 0) {
2977                                         near_call = TRUE;
2978                                         no_patch = TRUE;
2979                                 }
2980                         }
2981                 }
2982
2983                 if (cfg->method->dynamic)
2984                         /* These methods are allocated using malloc */
2985                         near_call = FALSE;
2986
2987 #ifdef MONO_ARCH_NOMAP32BIT
2988                 near_call = FALSE;
2989 #endif
2990 #if defined(__native_client__)
2991                 /* Always use near_call == TRUE for Native Client */
2992                 near_call = TRUE;
2993 #endif
2994                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2995                 if (optimize_for_xen)
2996                         near_call = FALSE;
2997
2998                 if (cfg->compile_aot) {
2999                         near_call = TRUE;
3000                         no_patch = TRUE;
3001                 }
3002
3003                 if (near_call) {
3004                         /*
3005                          * Align the call displacement to an address divisible by 4 so it does
3006                          * not span cache lines. This is required for code patching to work on SMP
3007                          * systems.
3008                          */
3009                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3010                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3011                                 amd64_padding (code, pad_size);
3012                         }
3013                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3014                         amd64_call_code (code, 0);
3015                 }
3016                 else {
3017                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3018                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3019                         amd64_call_reg (code, GP_SCRATCH_REG);
3020                 }
3021         }
3022
3023         return code;
3024 }
3025
3026 static inline guint8*
3027 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3028 {
3029 #ifdef HOST_WIN32
3030         if (win64_adjust_stack)
3031                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3032 #endif
3033         code = emit_call_body (cfg, code, patch_type, data);
3034 #ifdef HOST_WIN32
3035         if (win64_adjust_stack)
3036                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3037 #endif
3038
3039         return code;
3040 }
3041
3042 static inline int
3043 store_membase_imm_to_store_membase_reg (int opcode)
3044 {
3045         switch (opcode) {
3046         case OP_STORE_MEMBASE_IMM:
3047                 return OP_STORE_MEMBASE_REG;
3048         case OP_STOREI4_MEMBASE_IMM:
3049                 return OP_STOREI4_MEMBASE_REG;
3050         case OP_STOREI8_MEMBASE_IMM:
3051                 return OP_STOREI8_MEMBASE_REG;
3052         }
3053
3054         return -1;
3055 }
3056
3057 #ifndef DISABLE_JIT
3058
3059 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3060
3061 /*
3062  * mono_arch_peephole_pass_1:
3063  *
3064  *   Perform peephole opts which should/can be performed before local regalloc
3065  */
3066 void
3067 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3068 {
3069         MonoInst *ins, *n;
3070
3071         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3072                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3073
3074                 switch (ins->opcode) {
3075                 case OP_ADD_IMM:
3076                 case OP_IADD_IMM:
3077                 case OP_LADD_IMM:
3078                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3079                                 /*
3080                                  * X86_LEA is like ADD, but doesn't have the
3081                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3082                                  * its operand to 64 bit.
3083                                  */
3084                                 ins->opcode = OP_X86_LEA_MEMBASE;
3085                                 ins->inst_basereg = ins->sreg1;
3086                         }
3087                         break;
3088                 case OP_LXOR:
3089                 case OP_IXOR:
3090                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3091                                 MonoInst *ins2;
3092
3093                                 /*
3094                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3095                                  * the latter has length 2-3 instead of 6 (reverse constant
3096                                  * propagation). These instruction sequences are very common
3097                                  * in the initlocals bblock.
3098                                  */
3099                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3100                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3101                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3102                                                 ins2->sreg1 = ins->dreg;
3103                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3104                                                 /* Continue */
3105                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3106                                                 NULLIFY_INS (ins2);
3107                                                 /* Continue */
3108                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3109                                                 /* Continue */
3110                                         } else {
3111                                                 break;
3112                                         }
3113                                 }
3114                         }
3115                         break;
3116                 case OP_COMPARE_IMM:
3117                 case OP_LCOMPARE_IMM:
3118                         /* OP_COMPARE_IMM (reg, 0)
3119                          * -->
3120                          * OP_AMD64_TEST_NULL (reg)
3121                          */
3122                         if (!ins->inst_imm)
3123                                 ins->opcode = OP_AMD64_TEST_NULL;
3124                         break;
3125                 case OP_ICOMPARE_IMM:
3126                         if (!ins->inst_imm)
3127                                 ins->opcode = OP_X86_TEST_NULL;
3128                         break;
3129                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3130                         /*
3131                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3132                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3133                          * -->
3134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3135                          * OP_COMPARE_IMM reg, imm
3136                          *
3137                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3138                          */
3139                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3140                             ins->inst_basereg == last_ins->inst_destbasereg &&
3141                             ins->inst_offset == last_ins->inst_offset) {
3142                                         ins->opcode = OP_ICOMPARE_IMM;
3143                                         ins->sreg1 = last_ins->sreg1;
3144
3145                                         /* check if we can remove cmp reg,0 with test null */
3146                                         if (!ins->inst_imm)
3147                                                 ins->opcode = OP_X86_TEST_NULL;
3148                                 }
3149
3150                         break;
3151                 }
3152
3153                 mono_peephole_ins (bb, ins);
3154         }
3155 }
3156
3157 void
3158 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3159 {
3160         MonoInst *ins, *n;
3161
3162         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163                 switch (ins->opcode) {
3164                 case OP_ICONST:
3165                 case OP_I8CONST: {
3166                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3167                         /* reg = 0 -> XOR (reg, reg) */
3168                         /* XOR sets cflags on x86, so we cant do it always */
3169                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3170                                 ins->opcode = OP_LXOR;
3171                                 ins->sreg1 = ins->dreg;
3172                                 ins->sreg2 = ins->dreg;
3173                                 /* Fall through */
3174                         } else {
3175                                 break;
3176                         }
3177                 }
3178                 case OP_LXOR:
3179                         /*
3180                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3181                          * 0 result into 64 bits.
3182                          */
3183                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3184                                 ins->opcode = OP_IXOR;
3185                         }
3186                         /* Fall through */
3187                 case OP_IXOR:
3188                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3189                                 MonoInst *ins2;
3190
3191                                 /*
3192                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3193                                  * the latter has length 2-3 instead of 6 (reverse constant
3194                                  * propagation). These instruction sequences are very common
3195                                  * in the initlocals bblock.
3196                                  */
3197                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3198                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3199                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3200                                                 ins2->sreg1 = ins->dreg;
3201                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3202                                                 /* Continue */
3203                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3204                                                 NULLIFY_INS (ins2);
3205                                                 /* Continue */
3206                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3207                                                 /* Continue */
3208                                         } else {
3209                                                 break;
3210                                         }
3211                                 }
3212                         }
3213                         break;
3214                 case OP_IADD_IMM:
3215                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3216                                 ins->opcode = OP_X86_INC_REG;
3217                         break;
3218                 case OP_ISUB_IMM:
3219                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3220                                 ins->opcode = OP_X86_DEC_REG;
3221                         break;
3222                 }
3223
3224                 mono_peephole_ins (bb, ins);
3225         }
3226 }
3227
3228 #define NEW_INS(cfg,ins,dest,op) do {   \
3229                 MONO_INST_NEW ((cfg), (dest), (op)); \
3230         (dest)->cil_code = (ins)->cil_code; \
3231         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3232         } while (0)
3233
3234 /*
3235  * mono_arch_lowering_pass:
3236  *
3237  *  Converts complex opcodes into simpler ones so that each IR instruction
3238  * corresponds to one machine instruction.
3239  */
3240 void
3241 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3242 {
3243         MonoInst *ins, *n, *temp;
3244
3245         /*
3246          * FIXME: Need to add more instructions, but the current machine
3247          * description can't model some parts of the composite instructions like
3248          * cdq.
3249          */
3250         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3251                 switch (ins->opcode) {
3252                 case OP_DIV_IMM:
3253                 case OP_REM_IMM:
3254                 case OP_IDIV_IMM:
3255                 case OP_IDIV_UN_IMM:
3256                 case OP_IREM_UN_IMM:
3257                 case OP_LREM_IMM:
3258                 case OP_IREM_IMM:
3259                         mono_decompose_op_imm (cfg, bb, ins);
3260                         break;
3261                 case OP_COMPARE_IMM:
3262                 case OP_LCOMPARE_IMM:
3263                         if (!amd64_is_imm32 (ins->inst_imm)) {
3264                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3265                                 temp->inst_c0 = ins->inst_imm;
3266                                 temp->dreg = mono_alloc_ireg (cfg);
3267                                 ins->opcode = OP_COMPARE;
3268                                 ins->sreg2 = temp->dreg;
3269                         }
3270                         break;
3271 #ifndef __mono_ilp32__
3272                 case OP_LOAD_MEMBASE:
3273 #endif
3274                 case OP_LOADI8_MEMBASE:
3275 #ifndef __native_client_codegen__
3276                 /*  Don't generate memindex opcodes (to simplify */
3277                 /*  read sandboxing) */
3278                         if (!amd64_is_imm32 (ins->inst_offset)) {
3279                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3280                                 temp->inst_c0 = ins->inst_offset;
3281                                 temp->dreg = mono_alloc_ireg (cfg);
3282                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3283                                 ins->inst_indexreg = temp->dreg;
3284                         }
3285 #endif
3286                         break;
3287 #ifndef __mono_ilp32__
3288                 case OP_STORE_MEMBASE_IMM:
3289 #endif
3290                 case OP_STOREI8_MEMBASE_IMM:
3291                         if (!amd64_is_imm32 (ins->inst_imm)) {
3292                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3293                                 temp->inst_c0 = ins->inst_imm;
3294                                 temp->dreg = mono_alloc_ireg (cfg);
3295                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3296                                 ins->sreg1 = temp->dreg;
3297                         }
3298                         break;
3299 #ifdef MONO_ARCH_SIMD_INTRINSICS
3300                 case OP_EXPAND_I1: {
3301                                 int temp_reg1 = mono_alloc_ireg (cfg);
3302                                 int temp_reg2 = mono_alloc_ireg (cfg);
3303                                 int original_reg = ins->sreg1;
3304
3305                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3306                                 temp->sreg1 = original_reg;
3307                                 temp->dreg = temp_reg1;
3308
3309                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3310                                 temp->sreg1 = temp_reg1;
3311                                 temp->dreg = temp_reg2;
3312                                 temp->inst_imm = 8;
3313
3314                                 NEW_INS (cfg, ins, temp, OP_LOR);
3315                                 temp->sreg1 = temp->dreg = temp_reg2;
3316                                 temp->sreg2 = temp_reg1;
3317
3318                                 ins->opcode = OP_EXPAND_I2;
3319                                 ins->sreg1 = temp_reg2;
3320                         }
3321                         break;
3322 #endif
3323                 default:
3324                         break;
3325                 }
3326         }
3327
3328         bb->max_vreg = cfg->next_vreg;
3329 }
3330
3331 static const int
3332 branch_cc_table [] = {
3333         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3334         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3335         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3336 };
3337
3338 /* Maps CMP_... constants to X86_CC_... constants */
3339 static const int
3340 cc_table [] = {
3341         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3342         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3343 };
3344
3345 static const int
3346 cc_signed_table [] = {
3347         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3348         FALSE, FALSE, FALSE, FALSE
3349 };
3350
3351 /*#include "cprop.c"*/
3352
3353 static unsigned char*
3354 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3355 {
3356         if (size == 8)
3357                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3358         else
3359                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3360
3361         if (size == 1)
3362                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3363         else if (size == 2)
3364                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3365         return code;
3366 }
3367
3368 static unsigned char*
3369 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3370 {
3371         int sreg = tree->sreg1;
3372         int need_touch = FALSE;
3373
3374 #if defined(HOST_WIN32)
3375         need_touch = TRUE;
3376 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3377         if (!tree->flags & MONO_INST_INIT)
3378                 need_touch = TRUE;
3379 #endif
3380
3381         if (need_touch) {
3382                 guint8* br[5];
3383
3384                 /*
3385                  * Under Windows:
3386                  * If requested stack size is larger than one page,
3387                  * perform stack-touch operation
3388                  */
3389                 /*
3390                  * Generate stack probe code.
3391                  * Under Windows, it is necessary to allocate one page at a time,
3392                  * "touching" stack after each successful sub-allocation. This is
3393                  * because of the way stack growth is implemented - there is a
3394                  * guard page before the lowest stack page that is currently commited.
3395                  * Stack normally grows sequentially so OS traps access to the
3396                  * guard page and commits more pages when needed.
3397                  */
3398                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3399                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3400
3401                 br[2] = code; /* loop */
3402                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3403                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3404                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3405                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3406                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3407                 amd64_patch (br[3], br[2]);
3408                 amd64_test_reg_reg (code, sreg, sreg);
3409                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3410                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3411
3412                 br[1] = code; x86_jump8 (code, 0);
3413
3414                 amd64_patch (br[0], code);
3415                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3416                 amd64_patch (br[1], code);
3417                 amd64_patch (br[4], code);
3418         }
3419         else
3420                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3421
3422         if (tree->flags & MONO_INST_INIT) {
3423                 int offset = 0;
3424                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3425                         amd64_push_reg (code, AMD64_RAX);
3426                         offset += 8;
3427                 }
3428                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3429                         amd64_push_reg (code, AMD64_RCX);
3430                         offset += 8;
3431                 }
3432                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3433                         amd64_push_reg (code, AMD64_RDI);
3434                         offset += 8;
3435                 }
3436
3437                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3438                 if (sreg != AMD64_RCX)
3439                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3440                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3441
3442                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3443                 if (cfg->param_area)
3444                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3445                 amd64_cld (code);
3446 #if defined(__default_codegen__)
3447                 amd64_prefix (code, X86_REP_PREFIX);
3448                 amd64_stosl (code);
3449 #elif defined(__native_client_codegen__)
3450                 /* NaCl stos pseudo-instruction */
3451                 amd64_codegen_pre(code);
3452                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3453                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3454                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3455                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3456                 amd64_prefix (code, X86_REP_PREFIX);
3457                 amd64_stosl (code);
3458                 amd64_codegen_post(code);
3459 #endif /* __native_client_codegen__ */
3460
3461                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3462                         amd64_pop_reg (code, AMD64_RDI);
3463                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3464                         amd64_pop_reg (code, AMD64_RCX);
3465                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3466                         amd64_pop_reg (code, AMD64_RAX);
3467         }
3468         return code;
3469 }
3470
3471 static guint8*
3472 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3473 {
3474         CallInfo *cinfo;
3475         guint32 quad;
3476
3477         /* Move return value to the target register */
3478         /* FIXME: do this in the local reg allocator */
3479         switch (ins->opcode) {
3480         case OP_CALL:
3481         case OP_CALL_REG:
3482         case OP_CALL_MEMBASE:
3483         case OP_LCALL:
3484         case OP_LCALL_REG:
3485         case OP_LCALL_MEMBASE:
3486                 g_assert (ins->dreg == AMD64_RAX);
3487                 break;
3488         case OP_FCALL:
3489         case OP_FCALL_REG:
3490         case OP_FCALL_MEMBASE:
3491                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3492                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3493                 }
3494                 else {
3495                         if (ins->dreg != AMD64_XMM0)
3496                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3497                 }
3498                 break;
3499         case OP_VCALL:
3500         case OP_VCALL_REG:
3501         case OP_VCALL_MEMBASE:
3502         case OP_VCALL2:
3503         case OP_VCALL2_REG:
3504         case OP_VCALL2_MEMBASE:
3505                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3506                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3507                         MonoInst *loc = cfg->arch.vret_addr_loc;
3508
3509                         /* Load the destination address */
3510                         g_assert (loc->opcode == OP_REGOFFSET);
3511                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3512
3513                         for (quad = 0; quad < 2; quad ++) {
3514                                 switch (cinfo->ret.pair_storage [quad]) {
3515                                 case ArgInIReg:
3516                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3517                                         break;
3518                                 case ArgInFloatSSEReg:
3519                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3520                                         break;
3521                                 case ArgInDoubleSSEReg:
3522                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3523                                         break;
3524                                 case ArgNone:
3525                                         break;
3526                                 default:
3527                                         NOT_IMPLEMENTED;
3528                                 }
3529                         }
3530                 }
3531                 break;
3532         }
3533
3534         return code;
3535 }
3536
3537 #endif /* DISABLE_JIT */
3538
3539 #ifdef __APPLE__
3540 static int tls_gs_offset;
3541 #endif
3542
3543 gboolean
3544 mono_amd64_have_tls_get (void)
3545 {
3546 #ifdef __APPLE__
3547         static gboolean have_tls_get = FALSE;
3548         static gboolean inited = FALSE;
3549         guint8 *ins;
3550
3551         if (inited)
3552                 return have_tls_get;
3553
3554         ins = (guint8*)pthread_getspecific;
3555
3556         /*
3557          * We're looking for these two instructions:
3558          *
3559          * mov    %gs:[offset](,%rdi,8),%rax
3560          * retq
3561          */
3562         have_tls_get = ins [0] == 0x65 &&
3563                        ins [1] == 0x48 &&
3564                        ins [2] == 0x8b &&
3565                        ins [3] == 0x04 &&
3566                        ins [4] == 0xfd &&
3567                        ins [6] == 0x00 &&
3568                        ins [7] == 0x00 &&
3569                        ins [8] == 0x00 &&
3570                        ins [9] == 0xc3;
3571
3572         inited = TRUE;
3573
3574         tls_gs_offset = ins[5];
3575
3576         return have_tls_get;
3577 #else
3578         return TRUE;
3579 #endif
3580 }
3581
3582 int
3583 mono_amd64_get_tls_gs_offset (void)
3584 {
3585 #ifdef TARGET_OSX
3586         return tls_gs_offset;
3587 #else
3588         g_assert_not_reached ();
3589         return -1;
3590 #endif
3591 }
3592
3593 /*
3594  * mono_amd64_emit_tls_get:
3595  * @code: buffer to store code to
3596  * @dreg: hard register where to place the result
3597  * @tls_offset: offset info
3598  *
3599  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3600  * the dreg register the item in the thread local storage identified
3601  * by tls_offset.
3602  *
3603  * Returns: a pointer to the end of the stored code
3604  */
3605 guint8*
3606 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3607 {
3608 #ifdef HOST_WIN32
3609         if (tls_offset < 64) {
3610                 x86_prefix (code, X86_GS_PREFIX);
3611                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3612         } else {
3613                 guint8 *buf [16];
3614
3615                 g_assert (tls_offset < 0x440);
3616                 /* Load TEB->TlsExpansionSlots */
3617                 x86_prefix (code, X86_GS_PREFIX);
3618                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3619                 amd64_test_reg_reg (code, dreg, dreg);
3620                 buf [0] = code;
3621                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3622                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3623                 amd64_patch (buf [0], code);
3624         }
3625 #elif defined(__APPLE__)
3626         x86_prefix (code, X86_GS_PREFIX);
3627         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3628 #else
3629         if (optimize_for_xen) {
3630                 x86_prefix (code, X86_FS_PREFIX);
3631                 amd64_mov_reg_mem (code, dreg, 0, 8);
3632                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3633         } else {
3634                 x86_prefix (code, X86_FS_PREFIX);
3635                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3636         }
3637 #endif
3638         return code;
3639 }
3640
3641 static guint8*
3642 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3643 {
3644         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3645 #ifdef TARGET_OSX
3646         if (dreg != offset_reg)
3647                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3648         amd64_prefix (code, X86_GS_PREFIX);
3649         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3650 #elif defined(__linux__)
3651         int tmpreg = -1;
3652
3653         if (dreg == offset_reg) {
3654                 /* Use a temporary reg by saving it to the redzone */
3655                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3656                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3657                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3658                 offset_reg = tmpreg;
3659         }
3660         x86_prefix (code, X86_FS_PREFIX);
3661         amd64_mov_reg_mem (code, dreg, 0, 8);
3662         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3663         if (tmpreg != -1)
3664                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3665 #else
3666         g_assert_not_reached ();
3667 #endif
3668         return code;
3669 }
3670
3671 static guint8*
3672 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3673 {
3674 #ifdef HOST_WIN32
3675         g_assert_not_reached ();
3676 #elif defined(__APPLE__)
3677         x86_prefix (code, X86_GS_PREFIX);
3678         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3679 #else
3680         g_assert (!optimize_for_xen);
3681         x86_prefix (code, X86_FS_PREFIX);
3682         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3683 #endif
3684         return code;
3685 }
3686
3687 static guint8*
3688 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3689 {
3690         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3691 #ifdef HOST_WIN32
3692         g_assert_not_reached ();
3693 #elif defined(__APPLE__)
3694         x86_prefix (code, X86_GS_PREFIX);
3695         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3696 #else
3697         x86_prefix (code, X86_FS_PREFIX);
3698         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3699 #endif
3700         return code;
3701 }
3702
3703  /*
3704  * mono_arch_translate_tls_offset:
3705  *
3706  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3707  */
3708 int
3709 mono_arch_translate_tls_offset (int offset)
3710 {
3711 #ifdef __APPLE__
3712         return tls_gs_offset + (offset * 8);
3713 #else
3714         return offset;
3715 #endif
3716 }
3717
3718 /*
3719  * emit_setup_lmf:
3720  *
3721  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3722  */
3723 static guint8*
3724 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3725 {
3726         /*
3727          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3728          */
3729         /*
3730          * sp is saved right before calls but we need to save it here too so
3731          * async stack walks would work.
3732          */
3733         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3734         /* Save rbp */
3735         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3736         if (cfg->arch.omit_fp && cfa_offset != -1)
3737                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3738
3739         /* These can't contain refs */
3740         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3741         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3742         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3743         /* These are handled automatically by the stack marking code */
3744         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3745
3746         return code;
3747 }
3748
3749 #define REAL_PRINT_REG(text,reg) \
3750 mono_assert (reg >= 0); \
3751 amd64_push_reg (code, AMD64_RAX); \
3752 amd64_push_reg (code, AMD64_RDX); \
3753 amd64_push_reg (code, AMD64_RCX); \
3754 amd64_push_reg (code, reg); \
3755 amd64_push_imm (code, reg); \
3756 amd64_push_imm (code, text " %d %p\n"); \
3757 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3758 amd64_call_reg (code, AMD64_RAX); \
3759 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3760 amd64_pop_reg (code, AMD64_RCX); \
3761 amd64_pop_reg (code, AMD64_RDX); \
3762 amd64_pop_reg (code, AMD64_RAX);
3763
3764 /* benchmark and set based on cpu */
3765 #define LOOP_ALIGNMENT 8
3766 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3767
3768 #ifndef DISABLE_JIT
3769 void
3770 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3771 {
3772         MonoInst *ins;
3773         MonoCallInst *call;
3774         guint offset;
3775         guint8 *code = cfg->native_code + cfg->code_len;
3776         MonoInst *last_ins = NULL;
3777         guint last_offset = 0;
3778         int max_len;
3779
3780         /* Fix max_offset estimate for each successor bb */
3781         if (cfg->opt & MONO_OPT_BRANCH) {
3782                 int current_offset = cfg->code_len;
3783                 MonoBasicBlock *current_bb;
3784                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3785                         current_bb->max_offset = current_offset;
3786                         current_offset += current_bb->max_length;
3787                 }
3788         }
3789
3790         if (cfg->opt & MONO_OPT_LOOP) {
3791                 int pad, align = LOOP_ALIGNMENT;
3792                 /* set alignment depending on cpu */
3793                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3794                         pad = align - pad;
3795                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3796                         amd64_padding (code, pad);
3797                         cfg->code_len += pad;
3798                         bb->native_offset = cfg->code_len;
3799                 }
3800         }
3801
3802 #if defined(__native_client_codegen__)
3803         /* For Native Client, all indirect call/jump targets must be */
3804         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3805         /* indirectly as well.                                       */
3806         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3807                                       (bb->flags & BB_EXCEPTION_HANDLER);
3808
3809         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3810                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3811                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3812                 cfg->code_len += pad;
3813                 bb->native_offset = cfg->code_len;
3814         }
3815 #endif  /*__native_client_codegen__*/
3816
3817         if (cfg->verbose_level > 2)
3818                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3819
3820         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3821                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3822                 g_assert (!cfg->compile_aot);
3823
3824                 cov->data [bb->dfn].cil_code = bb->cil_code;
3825                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3826                 /* this is not thread save, but good enough */
3827                 amd64_inc_membase (code, AMD64_R11, 0);
3828         }
3829
3830         offset = code - cfg->native_code;
3831
3832         mono_debug_open_block (cfg, bb, offset);
3833
3834     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3835                 x86_breakpoint (code);
3836
3837         MONO_BB_FOR_EACH_INS (bb, ins) {
3838                 offset = code - cfg->native_code;
3839
3840                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3841
3842 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3843
3844                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3845                         cfg->code_size *= 2;
3846                         cfg->native_code = mono_realloc_native_code(cfg);
3847                         code = cfg->native_code + offset;
3848                         cfg->stat_code_reallocs++;
3849                 }
3850
3851                 if (cfg->debug_info)
3852                         mono_debug_record_line_number (cfg, ins, offset);
3853
3854                 switch (ins->opcode) {
3855                 case OP_BIGMUL:
3856                         amd64_mul_reg (code, ins->sreg2, TRUE);
3857                         break;
3858                 case OP_BIGMUL_UN:
3859                         amd64_mul_reg (code, ins->sreg2, FALSE);
3860                         break;
3861                 case OP_X86_SETEQ_MEMBASE:
3862                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3863                         break;
3864                 case OP_STOREI1_MEMBASE_IMM:
3865                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3866                         break;
3867                 case OP_STOREI2_MEMBASE_IMM:
3868                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3869                         break;
3870                 case OP_STOREI4_MEMBASE_IMM:
3871                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3872                         break;
3873                 case OP_STOREI1_MEMBASE_REG:
3874                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3875                         break;
3876                 case OP_STOREI2_MEMBASE_REG:
3877                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3878                         break;
3879                 /* In AMD64 NaCl, pointers are 4 bytes, */
3880                 /*  so STORE_* != STOREI8_*. Likewise below. */
3881                 case OP_STORE_MEMBASE_REG:
3882                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3883                         break;
3884                 case OP_STOREI8_MEMBASE_REG:
3885                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3886                         break;
3887                 case OP_STOREI4_MEMBASE_REG:
3888                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3889                         break;
3890                 case OP_STORE_MEMBASE_IMM:
3891 #ifndef __native_client_codegen__
3892                         /* In NaCl, this could be a PCONST type, which could */
3893                         /* mean a pointer type was copied directly into the  */
3894                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3895                         /* the value would be 0x00000000FFFFFFFF which is    */
3896                         /* not proper for an imm32 unless you cast it.       */
3897                         g_assert (amd64_is_imm32 (ins->inst_imm));
3898 #endif
3899                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3900                         break;
3901                 case OP_STOREI8_MEMBASE_IMM:
3902                         g_assert (amd64_is_imm32 (ins->inst_imm));
3903                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3904                         break;
3905                 case OP_LOAD_MEM:
3906 #ifdef __mono_ilp32__
3907                         /* In ILP32, pointers are 4 bytes, so separate these */
3908                         /* cases, use literal 8 below where we really want 8 */
3909                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3910                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3911                         break;
3912 #endif
3913                 case OP_LOADI8_MEM:
3914                         // FIXME: Decompose this earlier
3915                         if (amd64_is_imm32 (ins->inst_imm))
3916                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3917                         else {
3918                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3919                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3920                         }
3921                         break;
3922                 case OP_LOADI4_MEM:
3923                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3924                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3925                         break;
3926                 case OP_LOADU4_MEM:
3927                         // FIXME: Decompose this earlier
3928                         if (amd64_is_imm32 (ins->inst_imm))
3929                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3930                         else {
3931                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3932                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3933                         }
3934                         break;
3935                 case OP_LOADU1_MEM:
3936                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3937                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3938                         break;
3939                 case OP_LOADU2_MEM:
3940                         /* For NaCl, pointers are 4 bytes, so separate these */
3941                         /* cases, use literal 8 below where we really want 8 */
3942                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3943                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3944                         break;
3945                 case OP_LOAD_MEMBASE:
3946                         g_assert (amd64_is_imm32 (ins->inst_offset));
3947                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3948                         break;
3949                 case OP_LOADI8_MEMBASE:
3950                         /* Use literal 8 instead of sizeof pointer or */
3951                         /* register, we really want 8 for this opcode */
3952                         g_assert (amd64_is_imm32 (ins->inst_offset));
3953                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3954                         break;
3955                 case OP_LOADI4_MEMBASE:
3956                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3957                         break;
3958                 case OP_LOADU4_MEMBASE:
3959                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3960                         break;
3961                 case OP_LOADU1_MEMBASE:
3962                         /* The cpu zero extends the result into 64 bits */
3963                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3964                         break;
3965                 case OP_LOADI1_MEMBASE:
3966                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3967                         break;
3968                 case OP_LOADU2_MEMBASE:
3969                         /* The cpu zero extends the result into 64 bits */
3970                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3971                         break;
3972                 case OP_LOADI2_MEMBASE:
3973                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3974                         break;
3975                 case OP_AMD64_LOADI8_MEMINDEX:
3976                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3977                         break;
3978                 case OP_LCONV_TO_I1:
3979                 case OP_ICONV_TO_I1:
3980                 case OP_SEXT_I1:
3981                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3982                         break;
3983                 case OP_LCONV_TO_I2:
3984                 case OP_ICONV_TO_I2:
3985                 case OP_SEXT_I2:
3986                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3987                         break;
3988                 case OP_LCONV_TO_U1:
3989                 case OP_ICONV_TO_U1:
3990                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3991                         break;
3992                 case OP_LCONV_TO_U2:
3993                 case OP_ICONV_TO_U2:
3994                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3995                         break;
3996                 case OP_ZEXT_I4:
3997                         /* Clean out the upper word */
3998                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3999                         break;
4000                 case OP_SEXT_I4:
4001                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4002                         break;
4003                 case OP_COMPARE:
4004                 case OP_LCOMPARE:
4005                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4006                         break;
4007                 case OP_COMPARE_IMM:
4008 #if defined(__mono_ilp32__)
4009                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4010                         g_assert (amd64_is_imm32 (ins->inst_imm));
4011                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4012                         break;
4013 #endif
4014                 case OP_LCOMPARE_IMM:
4015                         g_assert (amd64_is_imm32 (ins->inst_imm));
4016                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4017                         break;
4018                 case OP_X86_COMPARE_REG_MEMBASE:
4019                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4020                         break;
4021                 case OP_X86_TEST_NULL:
4022                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4023                         break;
4024                 case OP_AMD64_TEST_NULL:
4025                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4026                         break;
4027
4028                 case OP_X86_ADD_REG_MEMBASE:
4029                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4030                         break;
4031                 case OP_X86_SUB_REG_MEMBASE:
4032                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4033                         break;
4034                 case OP_X86_AND_REG_MEMBASE:
4035                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4036                         break;
4037                 case OP_X86_OR_REG_MEMBASE:
4038                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4039                         break;
4040                 case OP_X86_XOR_REG_MEMBASE:
4041                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4042                         break;
4043
4044                 case OP_X86_ADD_MEMBASE_IMM:
4045                         /* FIXME: Make a 64 version too */
4046                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4047                         break;
4048                 case OP_X86_SUB_MEMBASE_IMM:
4049                         g_assert (amd64_is_imm32 (ins->inst_imm));
4050                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4051                         break;
4052                 case OP_X86_AND_MEMBASE_IMM:
4053                         g_assert (amd64_is_imm32 (ins->inst_imm));
4054                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4055                         break;
4056                 case OP_X86_OR_MEMBASE_IMM:
4057                         g_assert (amd64_is_imm32 (ins->inst_imm));
4058                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4059                         break;
4060                 case OP_X86_XOR_MEMBASE_IMM:
4061                         g_assert (amd64_is_imm32 (ins->inst_imm));
4062                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4063                         break;
4064                 case OP_X86_ADD_MEMBASE_REG:
4065                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4066                         break;
4067                 case OP_X86_SUB_MEMBASE_REG:
4068                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4069                         break;
4070                 case OP_X86_AND_MEMBASE_REG:
4071                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4072                         break;
4073                 case OP_X86_OR_MEMBASE_REG:
4074                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4075                         break;
4076                 case OP_X86_XOR_MEMBASE_REG:
4077                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4078                         break;
4079                 case OP_X86_INC_MEMBASE:
4080                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4081                         break;
4082                 case OP_X86_INC_REG:
4083                         amd64_inc_reg_size (code, ins->dreg, 4);
4084                         break;
4085                 case OP_X86_DEC_MEMBASE:
4086                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4087                         break;
4088                 case OP_X86_DEC_REG:
4089                         amd64_dec_reg_size (code, ins->dreg, 4);
4090                         break;
4091                 case OP_X86_MUL_REG_MEMBASE:
4092                 case OP_X86_MUL_MEMBASE_REG:
4093                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4094                         break;
4095                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4096                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4097                         break;
4098                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4099                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4100                         break;
4101                 case OP_AMD64_COMPARE_MEMBASE_REG:
4102                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4103                         break;
4104                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4105                         g_assert (amd64_is_imm32 (ins->inst_imm));
4106                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4107                         break;
4108                 case OP_X86_COMPARE_MEMBASE8_IMM:
4109                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4110                         break;
4111                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4112                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4113                         break;
4114                 case OP_AMD64_COMPARE_REG_MEMBASE:
4115                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4116                         break;
4117
4118                 case OP_AMD64_ADD_REG_MEMBASE:
4119                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4120                         break;
4121                 case OP_AMD64_SUB_REG_MEMBASE:
4122                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4123                         break;
4124                 case OP_AMD64_AND_REG_MEMBASE:
4125                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4126                         break;
4127                 case OP_AMD64_OR_REG_MEMBASE:
4128                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4129                         break;
4130                 case OP_AMD64_XOR_REG_MEMBASE:
4131                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4132                         break;
4133
4134                 case OP_AMD64_ADD_MEMBASE_REG:
4135                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4136                         break;
4137                 case OP_AMD64_SUB_MEMBASE_REG:
4138                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4139                         break;
4140                 case OP_AMD64_AND_MEMBASE_REG:
4141                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4142                         break;
4143                 case OP_AMD64_OR_MEMBASE_REG:
4144                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4145                         break;
4146                 case OP_AMD64_XOR_MEMBASE_REG:
4147                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4148                         break;
4149
4150                 case OP_AMD64_ADD_MEMBASE_IMM:
4151                         g_assert (amd64_is_imm32 (ins->inst_imm));
4152                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4153                         break;
4154                 case OP_AMD64_SUB_MEMBASE_IMM:
4155                         g_assert (amd64_is_imm32 (ins->inst_imm));
4156                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4157                         break;
4158                 case OP_AMD64_AND_MEMBASE_IMM:
4159                         g_assert (amd64_is_imm32 (ins->inst_imm));
4160                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4161                         break;
4162                 case OP_AMD64_OR_MEMBASE_IMM:
4163                         g_assert (amd64_is_imm32 (ins->inst_imm));
4164                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4165                         break;
4166                 case OP_AMD64_XOR_MEMBASE_IMM:
4167                         g_assert (amd64_is_imm32 (ins->inst_imm));
4168                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4169                         break;
4170
4171                 case OP_BREAK:
4172                         amd64_breakpoint (code);
4173                         break;
4174                 case OP_RELAXED_NOP:
4175                         x86_prefix (code, X86_REP_PREFIX);
4176                         x86_nop (code);
4177                         break;
4178                 case OP_HARD_NOP:
4179                         x86_nop (code);
4180                         break;
4181                 case OP_NOP:
4182                 case OP_DUMMY_USE:
4183                 case OP_DUMMY_STORE:
4184                 case OP_DUMMY_ICONST:
4185                 case OP_DUMMY_R8CONST:
4186                 case OP_NOT_REACHED:
4187                 case OP_NOT_NULL:
4188                         break;
4189                 case OP_IL_SEQ_POINT:
4190                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4191                         break;
4192                 case OP_SEQ_POINT: {
4193                         int i;
4194
4195                         /*
4196                          * Read from the single stepping trigger page. This will cause a
4197                          * SIGSEGV when single stepping is enabled.
4198                          * We do this _before_ the breakpoint, so single stepping after
4199                          * a breakpoint is hit will step to the next IL offset.
4200                          */
4201                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4202                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4203
4204                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4205                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4206                         }
4207
4208                         /*
4209                          * This is the address which is saved in seq points,
4210                          */
4211                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4212
4213                         if (cfg->compile_aot) {
4214                                 guint32 offset = code - cfg->native_code;
4215                                 guint32 val;
4216                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4217
4218                                 /* Load info var */
4219                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4220                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4221                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4222                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4223                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4224                         } else {
4225                                 /*
4226                                  * A placeholder for a possible breakpoint inserted by
4227                                  * mono_arch_set_breakpoint ().
4228                                  */
4229                                 for (i = 0; i < breakpoint_size; ++i)
4230                                         x86_nop (code);
4231                         }
4232                         /*
4233                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4234                          * to another IL offset.
4235                          */
4236                         x86_nop (code);
4237                         break;
4238                 }
4239                 case OP_ADDCC:
4240                 case OP_LADDCC:
4241                 case OP_LADD:
4242                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4243                         break;
4244                 case OP_ADC:
4245                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4246                         break;
4247                 case OP_ADD_IMM:
4248                 case OP_LADD_IMM:
4249                         g_assert (amd64_is_imm32 (ins->inst_imm));
4250                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4251                         break;
4252                 case OP_ADC_IMM:
4253                         g_assert (amd64_is_imm32 (ins->inst_imm));
4254                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4255                         break;
4256                 case OP_SUBCC:
4257                 case OP_LSUBCC:
4258                 case OP_LSUB:
4259                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4260                         break;
4261                 case OP_SBB:
4262                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4263                         break;
4264                 case OP_SUB_IMM:
4265                 case OP_LSUB_IMM:
4266                         g_assert (amd64_is_imm32 (ins->inst_imm));
4267                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4268                         break;
4269                 case OP_SBB_IMM:
4270                         g_assert (amd64_is_imm32 (ins->inst_imm));
4271                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4272                         break;
4273                 case OP_LAND:
4274                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4275                         break;
4276                 case OP_AND_IMM:
4277                 case OP_LAND_IMM:
4278                         g_assert (amd64_is_imm32 (ins->inst_imm));
4279                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4280                         break;
4281                 case OP_LMUL:
4282                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4283                         break;
4284                 case OP_MUL_IMM:
4285                 case OP_LMUL_IMM:
4286                 case OP_IMUL_IMM: {
4287                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4288
4289                         switch (ins->inst_imm) {
4290                         case 2:
4291                                 /* MOV r1, r2 */
4292                                 /* ADD r1, r1 */
4293                                 if (ins->dreg != ins->sreg1)
4294                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4295                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4296                                 break;
4297                         case 3:
4298                                 /* LEA r1, [r2 + r2*2] */
4299                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4300                                 break;
4301                         case 5:
4302                                 /* LEA r1, [r2 + r2*4] */
4303                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4304                                 break;
4305                         case 6:
4306                                 /* LEA r1, [r2 + r2*2] */
4307                                 /* ADD r1, r1          */
4308                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4309                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4310                                 break;
4311                         case 9:
4312                                 /* LEA r1, [r2 + r2*8] */
4313                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4314                                 break;
4315                         case 10:
4316                                 /* LEA r1, [r2 + r2*4] */
4317                                 /* ADD r1, r1          */
4318                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4319                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4320                                 break;
4321                         case 12:
4322                                 /* LEA r1, [r2 + r2*2] */
4323                                 /* SHL r1, 2           */
4324                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4325                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4326                                 break;
4327                         case 25:
4328                                 /* LEA r1, [r2 + r2*4] */
4329                                 /* LEA r1, [r1 + r1*4] */
4330                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4331                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4332                                 break;
4333                         case 100:
4334                                 /* LEA r1, [r2 + r2*4] */
4335                                 /* SHL r1, 2           */
4336                                 /* LEA r1, [r1 + r1*4] */
4337                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4338                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4339                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4340                                 break;
4341                         default:
4342                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4343                                 break;
4344                         }
4345                         break;
4346                 }
4347                 case OP_LDIV:
4348                 case OP_LREM:
4349 #if defined( __native_client_codegen__ )
4350                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4351                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4352 #endif
4353                         /* Regalloc magic makes the div/rem cases the same */
4354                         if (ins->sreg2 == AMD64_RDX) {
4355                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4356                                 amd64_cdq (code);
4357                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4358                         } else {
4359                                 amd64_cdq (code);
4360                                 amd64_div_reg (code, ins->sreg2, TRUE);
4361                         }
4362                         break;
4363                 case OP_LDIV_UN:
4364                 case OP_LREM_UN:
4365 #if defined( __native_client_codegen__ )
4366                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4367                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4368 #endif
4369                         if (ins->sreg2 == AMD64_RDX) {
4370                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4371                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4372                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4373                         } else {
4374                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4375                                 amd64_div_reg (code, ins->sreg2, FALSE);
4376                         }
4377                         break;
4378                 case OP_IDIV:
4379                 case OP_IREM:
4380 #if defined( __native_client_codegen__ )
4381                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4382                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4383 #endif
4384                         if (ins->sreg2 == AMD64_RDX) {
4385                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4386                                 amd64_cdq_size (code, 4);
4387                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4388                         } else {
4389                                 amd64_cdq_size (code, 4);
4390                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4391                         }
4392                         break;
4393                 case OP_IDIV_UN:
4394                 case OP_IREM_UN:
4395 #if defined( __native_client_codegen__ )
4396                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4397                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4398 #endif
4399                         if (ins->sreg2 == AMD64_RDX) {
4400                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4401                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4402                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4403                         } else {
4404                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4405                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4406                         }
4407                         break;
4408                 case OP_LMUL_OVF:
4409                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4410                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4411                         break;
4412                 case OP_LOR:
4413                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4414                         break;
4415                 case OP_OR_IMM:
4416                 case OP_LOR_IMM:
4417                         g_assert (amd64_is_imm32 (ins->inst_imm));
4418                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4419                         break;
4420                 case OP_LXOR:
4421                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4422                         break;
4423                 case OP_XOR_IMM:
4424                 case OP_LXOR_IMM:
4425                         g_assert (amd64_is_imm32 (ins->inst_imm));
4426                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4427                         break;
4428                 case OP_LSHL:
4429                         g_assert (ins->sreg2 == AMD64_RCX);
4430                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4431                         break;
4432                 case OP_LSHR:
4433                         g_assert (ins->sreg2 == AMD64_RCX);
4434                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4435                         break;
4436                 case OP_SHR_IMM:
4437                         g_assert (amd64_is_imm32 (ins->inst_imm));
4438                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4439                         break;
4440                 case OP_LSHR_IMM:
4441                         g_assert (amd64_is_imm32 (ins->inst_imm));
4442                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4443                         break;
4444                 case OP_SHR_UN_IMM:
4445                         g_assert (amd64_is_imm32 (ins->inst_imm));
4446                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4447                         break;
4448                 case OP_LSHR_UN_IMM:
4449                         g_assert (amd64_is_imm32 (ins->inst_imm));
4450                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4451                         break;
4452                 case OP_LSHR_UN:
4453                         g_assert (ins->sreg2 == AMD64_RCX);
4454                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4455                         break;
4456                 case OP_SHL_IMM:
4457                         g_assert (amd64_is_imm32 (ins->inst_imm));
4458                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4459                         break;
4460                 case OP_LSHL_IMM:
4461                         g_assert (amd64_is_imm32 (ins->inst_imm));
4462                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4463                         break;
4464
4465                 case OP_IADDCC:
4466                 case OP_IADD:
4467                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4468                         break;
4469                 case OP_IADC:
4470                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4471                         break;
4472                 case OP_IADD_IMM:
4473                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4474                         break;
4475                 case OP_IADC_IMM:
4476                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4477                         break;
4478                 case OP_ISUBCC:
4479                 case OP_ISUB:
4480                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4481                         break;
4482                 case OP_ISBB:
4483                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4484                         break;
4485                 case OP_ISUB_IMM:
4486                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4487                         break;
4488                 case OP_ISBB_IMM:
4489                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4490                         break;
4491                 case OP_IAND:
4492                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4493                         break;
4494                 case OP_IAND_IMM:
4495                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4496                         break;
4497                 case OP_IOR:
4498                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4499                         break;
4500                 case OP_IOR_IMM:
4501                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4502                         break;
4503                 case OP_IXOR:
4504                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4505                         break;
4506                 case OP_IXOR_IMM:
4507                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4508                         break;
4509                 case OP_INEG:
4510                         amd64_neg_reg_size (code, ins->sreg1, 4);
4511                         break;
4512                 case OP_INOT:
4513                         amd64_not_reg_size (code, ins->sreg1, 4);
4514                         break;
4515                 case OP_ISHL:
4516                         g_assert (ins->sreg2 == AMD64_RCX);
4517                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4518                         break;
4519                 case OP_ISHR:
4520                         g_assert (ins->sreg2 == AMD64_RCX);
4521                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4522                         break;
4523                 case OP_ISHR_IMM:
4524                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4525                         break;
4526                 case OP_ISHR_UN_IMM:
4527                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4528                         break;
4529                 case OP_ISHR_UN:
4530                         g_assert (ins->sreg2 == AMD64_RCX);
4531                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4532                         break;
4533                 case OP_ISHL_IMM:
4534                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4535                         break;
4536                 case OP_IMUL:
4537                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4538                         break;
4539                 case OP_IMUL_OVF:
4540                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4541                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4542                         break;
4543                 case OP_IMUL_OVF_UN:
4544                 case OP_LMUL_OVF_UN: {
4545                         /* the mul operation and the exception check should most likely be split */
4546                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4547                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4548                         /*g_assert (ins->sreg2 == X86_EAX);
4549                         g_assert (ins->dreg == X86_EAX);*/
4550                         if (ins->sreg2 == X86_EAX) {
4551                                 non_eax_reg = ins->sreg1;
4552                         } else if (ins->sreg1 == X86_EAX) {
4553                                 non_eax_reg = ins->sreg2;
4554                         } else {
4555                                 /* no need to save since we're going to store to it anyway */
4556                                 if (ins->dreg != X86_EAX) {
4557                                         saved_eax = TRUE;
4558                                         amd64_push_reg (code, X86_EAX);
4559                                 }
4560                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4561                                 non_eax_reg = ins->sreg2;
4562                         }
4563                         if (ins->dreg == X86_EDX) {
4564                                 if (!saved_eax) {
4565                                         saved_eax = TRUE;
4566                                         amd64_push_reg (code, X86_EAX);
4567                                 }
4568                         } else {
4569                                 saved_edx = TRUE;
4570                                 amd64_push_reg (code, X86_EDX);
4571                         }
4572                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4573                         /* save before the check since pop and mov don't change the flags */
4574                         if (ins->dreg != X86_EAX)
4575                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4576                         if (saved_edx)
4577                                 amd64_pop_reg (code, X86_EDX);
4578                         if (saved_eax)
4579                                 amd64_pop_reg (code, X86_EAX);
4580                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4581                         break;
4582                 }
4583                 case OP_ICOMPARE:
4584                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4585                         break;
4586                 case OP_ICOMPARE_IMM:
4587                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4588                         break;
4589                 case OP_IBEQ:
4590                 case OP_IBLT:
4591                 case OP_IBGT:
4592                 case OP_IBGE:
4593                 case OP_IBLE:
4594                 case OP_LBEQ:
4595                 case OP_LBLT:
4596                 case OP_LBGT:
4597                 case OP_LBGE:
4598                 case OP_LBLE:
4599                 case OP_IBNE_UN:
4600                 case OP_IBLT_UN:
4601                 case OP_IBGT_UN:
4602                 case OP_IBGE_UN:
4603                 case OP_IBLE_UN:
4604                 case OP_LBNE_UN:
4605                 case OP_LBLT_UN:
4606                 case OP_LBGT_UN:
4607                 case OP_LBGE_UN:
4608                 case OP_LBLE_UN:
4609                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4610                         break;
4611
4612                 case OP_CMOV_IEQ:
4613                 case OP_CMOV_IGE:
4614                 case OP_CMOV_IGT:
4615                 case OP_CMOV_ILE:
4616                 case OP_CMOV_ILT:
4617                 case OP_CMOV_INE_UN:
4618                 case OP_CMOV_IGE_UN:
4619                 case OP_CMOV_IGT_UN:
4620                 case OP_CMOV_ILE_UN:
4621                 case OP_CMOV_ILT_UN:
4622                 case OP_CMOV_LEQ:
4623                 case OP_CMOV_LGE:
4624                 case OP_CMOV_LGT:
4625                 case OP_CMOV_LLE:
4626                 case OP_CMOV_LLT:
4627                 case OP_CMOV_LNE_UN:
4628                 case OP_CMOV_LGE_UN:
4629                 case OP_CMOV_LGT_UN:
4630                 case OP_CMOV_LLE_UN:
4631                 case OP_CMOV_LLT_UN:
4632                         g_assert (ins->dreg == ins->sreg1);
4633                         /* This needs to operate on 64 bit values */
4634                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4635                         break;
4636
4637                 case OP_LNOT:
4638                         amd64_not_reg (code, ins->sreg1);
4639                         break;
4640                 case OP_LNEG:
4641                         amd64_neg_reg (code, ins->sreg1);
4642                         break;
4643
4644                 case OP_ICONST:
4645                 case OP_I8CONST:
4646                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4647                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4648                         else
4649                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4650                         break;
4651                 case OP_AOTCONST:
4652                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4653                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4654                         break;
4655                 case OP_JUMP_TABLE:
4656                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4657                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4658                         break;
4659                 case OP_MOVE:
4660                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4661                         break;
4662                 case OP_AMD64_SET_XMMREG_R4: {
4663                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4664                         break;
4665                 }
4666                 case OP_AMD64_SET_XMMREG_R8: {
4667                         if (ins->dreg != ins->sreg1)
4668                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4669                         break;
4670                 }
4671                 case OP_TAILCALL: {
4672                         MonoCallInst *call = (MonoCallInst*)ins;
4673                         int i, save_area_offset;
4674
4675                         g_assert (!cfg->method->save_lmf);
4676
4677                         /* Restore callee saved registers */
4678                         save_area_offset = cfg->arch.reg_save_area_offset;
4679                         for (i = 0; i < AMD64_NREG; ++i)
4680                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4681                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4682                                         save_area_offset += 8;
4683                                 }
4684
4685                         if (cfg->arch.omit_fp) {
4686                                 if (cfg->arch.stack_alloc_size)
4687                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4688                                 // FIXME:
4689                                 if (call->stack_usage)
4690                                         NOT_IMPLEMENTED;
4691                         } else {
4692                                 /* Copy arguments on the stack to our argument area */
4693                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4694                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4695                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4696                                 }
4697
4698                                 amd64_leave (code);
4699                         }
4700
4701                         offset = code - cfg->native_code;
4702                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4703                         if (cfg->compile_aot)
4704                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4705                         else
4706                                 amd64_set_reg_template (code, AMD64_R11);
4707                         amd64_jump_reg (code, AMD64_R11);
4708                         ins->flags |= MONO_INST_GC_CALLSITE;
4709                         ins->backend.pc_offset = code - cfg->native_code;
4710                         break;
4711                 }
4712                 case OP_CHECK_THIS:
4713                         /* ensure ins->sreg1 is not NULL */
4714                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4715                         break;
4716                 case OP_ARGLIST: {
4717                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4718                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4719                         break;
4720                 }
4721                 case OP_CALL:
4722                 case OP_FCALL:
4723                 case OP_LCALL:
4724                 case OP_VCALL:
4725                 case OP_VCALL2:
4726                 case OP_VOIDCALL:
4727                         call = (MonoCallInst*)ins;
4728                         /*
4729                          * The AMD64 ABI forces callers to know about varargs.
4730                          */
4731                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4732                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4733                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4734                                 /*
4735                                  * Since the unmanaged calling convention doesn't contain a
4736                                  * 'vararg' entry, we have to treat every pinvoke call as a
4737                                  * potential vararg call.
4738                                  */
4739                                 guint32 nregs, i;
4740                                 nregs = 0;
4741                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4742                                         if (call->used_fregs & (1 << i))
4743                                                 nregs ++;
4744                                 if (!nregs)
4745                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4746                                 else
4747                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4748                         }
4749
4750                         if (ins->flags & MONO_INST_HAS_METHOD)
4751                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4752                         else
4753                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4754                         ins->flags |= MONO_INST_GC_CALLSITE;
4755                         ins->backend.pc_offset = code - cfg->native_code;
4756                         code = emit_move_return_value (cfg, ins, code);
4757                         break;
4758                 case OP_FCALL_REG:
4759                 case OP_LCALL_REG:
4760                 case OP_VCALL_REG:
4761                 case OP_VCALL2_REG:
4762                 case OP_VOIDCALL_REG:
4763                 case OP_CALL_REG:
4764                         call = (MonoCallInst*)ins;
4765
4766                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4767                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4768                                 ins->sreg1 = AMD64_R11;
4769                         }
4770
4771                         /*
4772                          * The AMD64 ABI forces callers to know about varargs.
4773                          */
4774                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4775                                 if (ins->sreg1 == AMD64_RAX) {
4776                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4777                                         ins->sreg1 = AMD64_R11;
4778                                 }
4779                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4780                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4781                                 /*
4782                                  * Since the unmanaged calling convention doesn't contain a
4783                                  * 'vararg' entry, we have to treat every pinvoke call as a
4784                                  * potential vararg call.
4785                                  */
4786                                 guint32 nregs, i;
4787                                 nregs = 0;
4788                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4789                                         if (call->used_fregs & (1 << i))
4790                                                 nregs ++;
4791                                 if (ins->sreg1 == AMD64_RAX) {
4792                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4793                                         ins->sreg1 = AMD64_R11;
4794                                 }
4795                                 if (!nregs)
4796                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4797                                 else
4798                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4799                         }
4800
4801                         amd64_call_reg (code, ins->sreg1);
4802                         ins->flags |= MONO_INST_GC_CALLSITE;
4803                         ins->backend.pc_offset = code - cfg->native_code;
4804                         code = emit_move_return_value (cfg, ins, code);
4805                         break;
4806                 case OP_FCALL_MEMBASE:
4807                 case OP_LCALL_MEMBASE:
4808                 case OP_VCALL_MEMBASE:
4809                 case OP_VCALL2_MEMBASE:
4810                 case OP_VOIDCALL_MEMBASE:
4811                 case OP_CALL_MEMBASE:
4812                         call = (MonoCallInst*)ins;
4813
4814                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4815                         ins->flags |= MONO_INST_GC_CALLSITE;
4816                         ins->backend.pc_offset = code - cfg->native_code;
4817                         code = emit_move_return_value (cfg, ins, code);
4818                         break;
4819                 case OP_DYN_CALL: {
4820                         int i;
4821                         MonoInst *var = cfg->dyn_call_var;
4822
4823                         g_assert (var->opcode == OP_REGOFFSET);
4824
4825                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4826                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4827                         /* r10 = ftn */
4828                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4829
4830                         /* Save args buffer */
4831                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4832
4833                         /* Set argument registers */
4834                         for (i = 0; i < PARAM_REGS; ++i)
4835                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4836
4837                         /* Make the call */
4838                         amd64_call_reg (code, AMD64_R10);
4839
4840                         ins->flags |= MONO_INST_GC_CALLSITE;
4841                         ins->backend.pc_offset = code - cfg->native_code;
4842
4843                         /* Save result */
4844                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4845                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4846                         break;
4847                 }
4848                 case OP_AMD64_SAVE_SP_TO_LMF: {
4849                         MonoInst *lmf_var = cfg->lmf_var;
4850                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4851                         break;
4852                 }
4853                 case OP_X86_PUSH:
4854                         g_assert_not_reached ();
4855                         amd64_push_reg (code, ins->sreg1);
4856                         break;
4857                 case OP_X86_PUSH_IMM:
4858                         g_assert_not_reached ();
4859                         g_assert (amd64_is_imm32 (ins->inst_imm));
4860                         amd64_push_imm (code, ins->inst_imm);
4861                         break;
4862                 case OP_X86_PUSH_MEMBASE:
4863                         g_assert_not_reached ();
4864                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4865                         break;
4866                 case OP_X86_PUSH_OBJ: {
4867                         int size = ALIGN_TO (ins->inst_imm, 8);
4868
4869                         g_assert_not_reached ();
4870
4871                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4872                         amd64_push_reg (code, AMD64_RDI);
4873                         amd64_push_reg (code, AMD64_RSI);
4874                         amd64_push_reg (code, AMD64_RCX);
4875                         if (ins->inst_offset)
4876                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4877                         else
4878                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4879                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4880                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4881                         amd64_cld (code);
4882                         amd64_prefix (code, X86_REP_PREFIX);
4883                         amd64_movsd (code);
4884                         amd64_pop_reg (code, AMD64_RCX);
4885                         amd64_pop_reg (code, AMD64_RSI);
4886                         amd64_pop_reg (code, AMD64_RDI);
4887                         break;
4888                 }
4889                 case OP_X86_LEA:
4890                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4891                         break;
4892                 case OP_X86_LEA_MEMBASE:
4893                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4894                         break;
4895                 case OP_X86_XCHG:
4896                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4897                         break;
4898                 case OP_LOCALLOC:
4899                         /* keep alignment */
4900                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4901                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4902                         code = mono_emit_stack_alloc (cfg, code, ins);
4903                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4904                         if (cfg->param_area)
4905                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4906                         break;
4907                 case OP_LOCALLOC_IMM: {
4908                         guint32 size = ins->inst_imm;
4909                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4910
4911                         if (ins->flags & MONO_INST_INIT) {
4912                                 if (size < 64) {
4913                                         int i;
4914
4915                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4916                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4917
4918                                         for (i = 0; i < size; i += 8)
4919                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4920                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4921                                 } else {
4922                                         amd64_mov_reg_imm (code, ins->dreg, size);
4923                                         ins->sreg1 = ins->dreg;
4924
4925                                         code = mono_emit_stack_alloc (cfg, code, ins);
4926                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4927                                 }
4928                         } else {
4929                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4930                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4931                         }
4932                         if (cfg->param_area)
4933                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4934                         break;
4935                 }
4936                 case OP_THROW: {
4937                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4938                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4939                                              (gpointer)"mono_arch_throw_exception", FALSE);
4940                         ins->flags |= MONO_INST_GC_CALLSITE;
4941                         ins->backend.pc_offset = code - cfg->native_code;
4942                         break;
4943                 }
4944                 case OP_RETHROW: {
4945                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4946                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4947                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4948                         ins->flags |= MONO_INST_GC_CALLSITE;
4949                         ins->backend.pc_offset = code - cfg->native_code;
4950                         break;
4951                 }
4952                 case OP_CALL_HANDLER:
4953                         /* Align stack */
4954                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4955                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4956                         amd64_call_imm (code, 0);
4957                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4958                         /* Restore stack alignment */
4959                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4960                         break;
4961                 case OP_START_HANDLER: {
4962                         /* Even though we're saving RSP, use sizeof */
4963                         /* gpointer because spvar is of type IntPtr */
4964                         /* see: mono_create_spvar_for_region */
4965                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4966                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4967
4968                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4969                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4970                                 cfg->param_area) {
4971                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4972                         }
4973                         break;
4974                 }
4975                 case OP_ENDFINALLY: {
4976                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4977                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4978                         amd64_ret (code);
4979                         break;
4980                 }
4981                 case OP_ENDFILTER: {
4982                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4983                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4984                         /* The local allocator will put the result into RAX */
4985                         amd64_ret (code);
4986                         break;
4987                 }
4988
4989                 case OP_LABEL:
4990                         ins->inst_c0 = code - cfg->native_code;
4991                         break;
4992                 case OP_BR:
4993                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4994                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4995                         //break;
4996                                 if (ins->inst_target_bb->native_offset) {
4997                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4998                                 } else {
4999                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5000                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5001                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5002                                                 x86_jump8 (code, 0);
5003                                         else
5004                                                 x86_jump32 (code, 0);
5005                         }
5006                         break;
5007                 case OP_BR_REG:
5008                         amd64_jump_reg (code, ins->sreg1);
5009                         break;
5010                 case OP_ICNEQ:
5011                 case OP_ICGE:
5012                 case OP_ICLE:
5013                 case OP_ICGE_UN:
5014                 case OP_ICLE_UN:
5015
5016                 case OP_CEQ:
5017                 case OP_LCEQ:
5018                 case OP_ICEQ:
5019                 case OP_CLT:
5020                 case OP_LCLT:
5021                 case OP_ICLT:
5022                 case OP_CGT:
5023                 case OP_ICGT:
5024                 case OP_LCGT:
5025                 case OP_CLT_UN:
5026                 case OP_LCLT_UN:
5027                 case OP_ICLT_UN:
5028                 case OP_CGT_UN:
5029                 case OP_LCGT_UN:
5030                 case OP_ICGT_UN:
5031                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5032                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5033                         break;
5034                 case OP_COND_EXC_EQ:
5035                 case OP_COND_EXC_NE_UN:
5036                 case OP_COND_EXC_LT:
5037                 case OP_COND_EXC_LT_UN:
5038                 case OP_COND_EXC_GT:
5039                 case OP_COND_EXC_GT_UN:
5040                 case OP_COND_EXC_GE:
5041                 case OP_COND_EXC_GE_UN:
5042                 case OP_COND_EXC_LE:
5043                 case OP_COND_EXC_LE_UN:
5044                 case OP_COND_EXC_IEQ:
5045                 case OP_COND_EXC_INE_UN:
5046                 case OP_COND_EXC_ILT:
5047                 case OP_COND_EXC_ILT_UN:
5048                 case OP_COND_EXC_IGT:
5049                 case OP_COND_EXC_IGT_UN:
5050                 case OP_COND_EXC_IGE:
5051                 case OP_COND_EXC_IGE_UN:
5052                 case OP_COND_EXC_ILE:
5053                 case OP_COND_EXC_ILE_UN:
5054                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5055                         break;
5056                 case OP_COND_EXC_OV:
5057                 case OP_COND_EXC_NO:
5058                 case OP_COND_EXC_C:
5059                 case OP_COND_EXC_NC:
5060                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5061                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5062                         break;
5063                 case OP_COND_EXC_IOV:
5064                 case OP_COND_EXC_INO:
5065                 case OP_COND_EXC_IC:
5066                 case OP_COND_EXC_INC:
5067                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5068                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5069                         break;
5070
5071                 /* floating point opcodes */
5072                 case OP_R8CONST: {
5073                         double d = *(double *)ins->inst_p0;
5074
5075                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5076                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5077                         }
5078                         else {
5079                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5080                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5081                         }
5082                         break;
5083                 }
5084                 case OP_R4CONST: {
5085                         float f = *(float *)ins->inst_p0;
5086
5087                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5088                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5089                         }
5090                         else {
5091                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5092                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5093                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5094                         }
5095                         break;
5096                 }
5097                 case OP_STORER8_MEMBASE_REG:
5098                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5099                         break;
5100                 case OP_LOADR8_MEMBASE:
5101                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5102                         break;
5103                 case OP_STORER4_MEMBASE_REG:
5104                         /* This requires a double->single conversion */
5105                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5106                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5107                         break;
5108                 case OP_LOADR4_MEMBASE:
5109                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5110                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5111                         break;
5112                 case OP_ICONV_TO_R4:
5113                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5114                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5115                         break;
5116                 case OP_ICONV_TO_R8:
5117                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5118                         break;
5119                 case OP_LCONV_TO_R4:
5120                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5121                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5122                         break;
5123                 case OP_LCONV_TO_R8:
5124                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5125                         break;
5126                 case OP_FCONV_TO_R4:
5127                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5128                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5129                         break;
5130                 case OP_FCONV_TO_I1:
5131                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5132                         break;
5133                 case OP_FCONV_TO_U1:
5134                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5135                         break;
5136                 case OP_FCONV_TO_I2:
5137                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5138                         break;
5139                 case OP_FCONV_TO_U2:
5140                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5141                         break;
5142                 case OP_FCONV_TO_U4:
5143                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5144                         break;
5145                 case OP_FCONV_TO_I4:
5146                 case OP_FCONV_TO_I:
5147                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5148                         break;
5149                 case OP_FCONV_TO_I8:
5150                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5151                         break;
5152                 case OP_LCONV_TO_R_UN: {
5153                         guint8 *br [2];
5154
5155                         /* Based on gcc code */
5156                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5157                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5158
5159                         /* Positive case */
5160                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5161                         br [1] = code; x86_jump8 (code, 0);
5162                         amd64_patch (br [0], code);
5163
5164                         /* Negative case */
5165                         /* Save to the red zone */
5166                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5167                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5168                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5169                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5170                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5171                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5172                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5173                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5174                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5175                         /* Restore */
5176                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5177                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5178                         amd64_patch (br [1], code);
5179                         break;
5180                 }
5181                 case OP_LCONV_TO_OVF_U4:
5182                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5183                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5184                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5185                         break;
5186                 case OP_LCONV_TO_OVF_I4_UN:
5187                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5188                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5189                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5190                         break;
5191                 case OP_FMOVE:
5192                         if (ins->dreg != ins->sreg1)
5193                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5194                         break;
5195                 case OP_FADD:
5196                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5197                         break;
5198                 case OP_FSUB:
5199                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5200                         break;
5201                 case OP_FMUL:
5202                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5203                         break;
5204                 case OP_FDIV:
5205                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5206                         break;
5207                 case OP_FNEG: {
5208                         static double r8_0 = -0.0;
5209
5210                         g_assert (ins->sreg1 == ins->dreg);
5211
5212                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5213                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5214                         break;
5215                 }
5216                 case OP_SIN:
5217                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5218                         break;
5219                 case OP_COS:
5220                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5221                         break;
5222                 case OP_ABS: {
5223                         static guint64 d = 0x7fffffffffffffffUL;
5224
5225                         g_assert (ins->sreg1 == ins->dreg);
5226
5227                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5228                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5229                         break;
5230                 }
5231                 case OP_SQRT:
5232                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5233                         break;
5234                 case OP_IMIN:
5235                         g_assert (cfg->opt & MONO_OPT_CMOV);
5236                         g_assert (ins->dreg == ins->sreg1);
5237                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5238                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5239                         break;
5240                 case OP_IMIN_UN:
5241                         g_assert (cfg->opt & MONO_OPT_CMOV);
5242                         g_assert (ins->dreg == ins->sreg1);
5243                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5244                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5245                         break;
5246                 case OP_IMAX:
5247                         g_assert (cfg->opt & MONO_OPT_CMOV);
5248                         g_assert (ins->dreg == ins->sreg1);
5249                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5250                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5251                         break;
5252                 case OP_IMAX_UN:
5253                         g_assert (cfg->opt & MONO_OPT_CMOV);
5254                         g_assert (ins->dreg == ins->sreg1);
5255                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5256                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5257                         break;
5258                 case OP_LMIN:
5259                         g_assert (cfg->opt & MONO_OPT_CMOV);
5260                         g_assert (ins->dreg == ins->sreg1);
5261                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5262                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5263                         break;
5264                 case OP_LMIN_UN:
5265                         g_assert (cfg->opt & MONO_OPT_CMOV);
5266                         g_assert (ins->dreg == ins->sreg1);
5267                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5268                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5269                         break;
5270                 case OP_LMAX:
5271                         g_assert (cfg->opt & MONO_OPT_CMOV);
5272                         g_assert (ins->dreg == ins->sreg1);
5273                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5274                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5275                         break;
5276                 case OP_LMAX_UN:
5277                         g_assert (cfg->opt & MONO_OPT_CMOV);
5278                         g_assert (ins->dreg == ins->sreg1);
5279                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5280                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5281                         break;
5282                 case OP_X86_FPOP:
5283                         break;
5284                 case OP_FCOMPARE:
5285                         /*
5286                          * The two arguments are swapped because the fbranch instructions
5287                          * depend on this for the non-sse case to work.
5288                          */
5289                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5290                         break;
5291                 case OP_FCNEQ:
5292                 case OP_FCEQ: {
5293                         /* zeroing the register at the start results in
5294                          * shorter and faster code (we can also remove the widening op)
5295                          */
5296                         guchar *unordered_check;
5297                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5298                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5299                         unordered_check = code;
5300                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5301
5302                         if (ins->opcode == OP_FCEQ) {
5303                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5304                                 amd64_patch (unordered_check, code);
5305                         } else {
5306                                 guchar *jump_to_end;
5307                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5308                                 jump_to_end = code;
5309                                 x86_jump8 (code, 0);
5310                                 amd64_patch (unordered_check, code);
5311                                 amd64_inc_reg (code, ins->dreg);
5312                                 amd64_patch (jump_to_end, code);
5313                         }
5314                         break;
5315                 }
5316                 case OP_FCLT:
5317                 case OP_FCLT_UN:
5318                         /* zeroing the register at the start results in
5319                          * shorter and faster code (we can also remove the widening op)
5320                          */
5321                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5322                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5323                         if (ins->opcode == OP_FCLT_UN) {
5324                                 guchar *unordered_check = code;
5325                                 guchar *jump_to_end;
5326                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5327                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5328                                 jump_to_end = code;
5329                                 x86_jump8 (code, 0);
5330                                 amd64_patch (unordered_check, code);
5331                                 amd64_inc_reg (code, ins->dreg);
5332                                 amd64_patch (jump_to_end, code);
5333                         } else {
5334                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5335                         }
5336                         break;
5337                 case OP_FCLE: {
5338                         guchar *unordered_check;
5339                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5340                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341                         unordered_check = code;
5342                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5343                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5344                         amd64_patch (unordered_check, code);
5345                         break;
5346                 }
5347                 case OP_FCGT:
5348                 case OP_FCGT_UN: {
5349                         /* zeroing the register at the start results in
5350                          * shorter and faster code (we can also remove the widening op)
5351                          */
5352                         guchar *unordered_check;
5353                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5354                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5355                         if (ins->opcode == OP_FCGT) {
5356                                 unordered_check = code;
5357                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5358                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5359                                 amd64_patch (unordered_check, code);
5360                         } else {
5361                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5362                         }
5363                         break;
5364                 }
5365                 case OP_FCGE: {
5366                         guchar *unordered_check;
5367                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5368                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5369                         unordered_check = code;
5370                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5371                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5372                         amd64_patch (unordered_check, code);
5373                         break;
5374                 }
5375
5376                 case OP_FCLT_MEMBASE:
5377                 case OP_FCGT_MEMBASE:
5378                 case OP_FCLT_UN_MEMBASE:
5379                 case OP_FCGT_UN_MEMBASE:
5380                 case OP_FCEQ_MEMBASE: {
5381                         guchar *unordered_check, *jump_to_end;
5382                         int x86_cond;
5383
5384                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5385                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5386
5387                         switch (ins->opcode) {
5388                         case OP_FCEQ_MEMBASE:
5389                                 x86_cond = X86_CC_EQ;
5390                                 break;
5391                         case OP_FCLT_MEMBASE:
5392                         case OP_FCLT_UN_MEMBASE:
5393                                 x86_cond = X86_CC_LT;
5394                                 break;
5395                         case OP_FCGT_MEMBASE:
5396                         case OP_FCGT_UN_MEMBASE:
5397                                 x86_cond = X86_CC_GT;
5398                                 break;
5399                         default:
5400                                 g_assert_not_reached ();
5401                         }
5402
5403                         unordered_check = code;
5404                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5405                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5406
5407                         switch (ins->opcode) {
5408                         case OP_FCEQ_MEMBASE:
5409                         case OP_FCLT_MEMBASE:
5410                         case OP_FCGT_MEMBASE:
5411                                 amd64_patch (unordered_check, code);
5412                                 break;
5413                         case OP_FCLT_UN_MEMBASE:
5414                         case OP_FCGT_UN_MEMBASE:
5415                                 jump_to_end = code;
5416                                 x86_jump8 (code, 0);
5417                                 amd64_patch (unordered_check, code);
5418                                 amd64_inc_reg (code, ins->dreg);
5419                                 amd64_patch (jump_to_end, code);
5420                                 break;
5421                         default:
5422                                 break;
5423                         }
5424                         break;
5425                 }
5426                 case OP_FBEQ: {
5427                         guchar *jump = code;
5428                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5429                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5430                         amd64_patch (jump, code);
5431                         break;
5432                 }
5433                 case OP_FBNE_UN:
5434                         /* Branch if C013 != 100 */
5435                         /* branch if !ZF or (PF|CF) */
5436                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5437                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5438                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5439                         break;
5440                 case OP_FBLT:
5441                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5442                         break;
5443                 case OP_FBLT_UN:
5444                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5445                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5446                         break;
5447                 case OP_FBGT:
5448                 case OP_FBGT_UN:
5449                         if (ins->opcode == OP_FBGT) {
5450                                 guchar *br1;
5451
5452                                 /* skip branch if C1=1 */
5453                                 br1 = code;
5454                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5455                                 /* branch if (C0 | C3) = 1 */
5456                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5457                                 amd64_patch (br1, code);
5458                                 break;
5459                         } else {
5460                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5461                         }
5462                         break;
5463                 case OP_FBGE: {
5464                         /* Branch if C013 == 100 or 001 */
5465                         guchar *br1;
5466
5467                         /* skip branch if C1=1 */
5468                         br1 = code;
5469                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5470                         /* branch if (C0 | C3) = 1 */
5471                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5472                         amd64_patch (br1, code);
5473                         break;
5474                 }
5475                 case OP_FBGE_UN:
5476                         /* Branch if C013 == 000 */
5477                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5478                         break;
5479                 case OP_FBLE: {
5480                         /* Branch if C013=000 or 100 */
5481                         guchar *br1;
5482
5483                         /* skip branch if C1=1 */
5484                         br1 = code;
5485                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5486                         /* branch if C0=0 */
5487                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5488                         amd64_patch (br1, code);
5489                         break;
5490                 }
5491                 case OP_FBLE_UN:
5492                         /* Branch if C013 != 001 */
5493                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5494                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5495                         break;
5496                 case OP_CKFINITE:
5497                         /* Transfer value to the fp stack */
5498                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5499                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5500                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5501
5502                         amd64_push_reg (code, AMD64_RAX);
5503                         amd64_fxam (code);
5504                         amd64_fnstsw (code);
5505                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5506                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5507                         amd64_pop_reg (code, AMD64_RAX);
5508                         amd64_fstp (code, 0);
5509                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5510                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5511                         break;
5512                 case OP_TLS_GET: {
5513                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5514                         break;
5515                 }
5516                 case OP_TLS_GET_REG:
5517                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5518                         break;
5519                 case OP_TLS_SET: {
5520                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5521                         break;
5522                 }
5523                 case OP_TLS_SET_REG: {
5524                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5525                         break;
5526                 }
5527                 case OP_MEMORY_BARRIER: {
5528                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5529                                 x86_mfence (code);
5530                         break;
5531                 }
5532                 case OP_ATOMIC_ADD_I4:
5533                 case OP_ATOMIC_ADD_I8: {
5534                         int dreg = ins->dreg;
5535                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5536
5537                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5538                                 dreg = AMD64_R11;
5539
5540                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5541                         amd64_prefix (code, X86_LOCK_PREFIX);
5542                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5543                         /* dreg contains the old value, add with sreg2 value */
5544                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5545
5546                         if (ins->dreg != dreg)
5547                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5548
5549                         break;
5550                 }
5551                 case OP_ATOMIC_EXCHANGE_I4:
5552                 case OP_ATOMIC_EXCHANGE_I8: {
5553                         guchar *br[2];
5554                         int sreg2 = ins->sreg2;
5555                         int breg = ins->inst_basereg;
5556                         guint32 size;
5557                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5558
5559                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5560                                 size = 8;
5561                         else
5562                                 size = 4;
5563
5564                         /*
5565                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5566                          * an explanation of how this works.
5567                          */
5568
5569                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5570                          * hack to overcome limits in x86 reg allocator
5571                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5572                          */
5573                         g_assert (ins->dreg == AMD64_RAX);
5574
5575                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5576                                 /* Highly unlikely, but possible */
5577                                 need_push = TRUE;
5578
5579                         /* The pushes invalidate rsp */
5580                         if ((breg == AMD64_RAX) || need_push) {
5581                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5582                                 breg = AMD64_R11;
5583                         }
5584
5585                         /* We need the EAX reg for the comparand */
5586                         if (ins->sreg2 == AMD64_RAX) {
5587                                 if (breg != AMD64_R11) {
5588                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5589                                         sreg2 = AMD64_R11;
5590                                 } else {
5591                                         g_assert (need_push);
5592                                         amd64_push_reg (code, AMD64_RDX);
5593                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5594                                         sreg2 = AMD64_RDX;
5595                                         rdx_pushed = TRUE;
5596                                 }
5597                         }
5598
5599                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5600
5601                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5602                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5603                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5604                         amd64_patch (br [1], br [0]);
5605
5606                         if (rdx_pushed)
5607                                 amd64_pop_reg (code, AMD64_RDX);
5608
5609                         break;
5610                 }
5611                 case OP_ATOMIC_CAS_I4:
5612                 case OP_ATOMIC_CAS_I8: {
5613                         guint32 size;
5614
5615                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5616                                 size = 8;
5617                         else
5618                                 size = 4;
5619
5620                         /*
5621                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5622                          * an explanation of how this works.
5623                          */
5624                         g_assert (ins->sreg3 == AMD64_RAX);
5625                         g_assert (ins->sreg1 != AMD64_RAX);
5626                         g_assert (ins->sreg1 != ins->sreg2);
5627
5628                         amd64_prefix (code, X86_LOCK_PREFIX);
5629                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5630
5631                         if (ins->dreg != AMD64_RAX)
5632                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5633                         break;
5634                 }
5635                 case OP_ATOMIC_LOAD_I1: {
5636                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5637                         break;
5638                 }
5639                 case OP_ATOMIC_LOAD_U1: {
5640                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5641                         break;
5642                 }
5643                 case OP_ATOMIC_LOAD_I2: {
5644                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5645                         break;
5646                 }
5647                 case OP_ATOMIC_LOAD_U2: {
5648                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5649                         break;
5650                 }
5651                 case OP_ATOMIC_LOAD_I4: {
5652                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5653                         break;
5654                 }
5655                 case OP_ATOMIC_LOAD_U4:
5656                 case OP_ATOMIC_LOAD_I8:
5657                 case OP_ATOMIC_LOAD_U8: {
5658                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5659                         break;
5660                 }
5661                 case OP_ATOMIC_LOAD_R4: {
5662                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5663                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5664                         break;
5665                 }
5666                 case OP_ATOMIC_LOAD_R8: {
5667                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5668                         break;
5669                 }
5670                 case OP_ATOMIC_STORE_I1:
5671                 case OP_ATOMIC_STORE_U1:
5672                 case OP_ATOMIC_STORE_I2:
5673                 case OP_ATOMIC_STORE_U2:
5674                 case OP_ATOMIC_STORE_I4:
5675                 case OP_ATOMIC_STORE_U4:
5676                 case OP_ATOMIC_STORE_I8:
5677                 case OP_ATOMIC_STORE_U8: {
5678                         int size;
5679
5680                         switch (ins->opcode) {
5681                         case OP_ATOMIC_STORE_I1:
5682                         case OP_ATOMIC_STORE_U1:
5683                                 size = 1;
5684                                 break;
5685                         case OP_ATOMIC_STORE_I2:
5686                         case OP_ATOMIC_STORE_U2:
5687                                 size = 2;
5688                                 break;
5689                         case OP_ATOMIC_STORE_I4:
5690                         case OP_ATOMIC_STORE_U4:
5691                                 size = 4;
5692                                 break;
5693                         case OP_ATOMIC_STORE_I8:
5694                         case OP_ATOMIC_STORE_U8:
5695                                 size = 8;
5696                                 break;
5697                         }
5698
5699                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5700
5701                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5702                                 x86_mfence (code);
5703                         break;
5704                 }
5705                 case OP_ATOMIC_STORE_R4: {
5706                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5707                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5708
5709                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5710                                 x86_mfence (code);
5711                         break;
5712                 }
5713                 case OP_ATOMIC_STORE_R8: {
5714                         x86_nop (code);
5715                         x86_nop (code);
5716                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5717                         x86_nop (code);
5718                         x86_nop (code);
5719
5720                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5721                                 x86_mfence (code);
5722                         break;
5723                 }
5724                 case OP_CARD_TABLE_WBARRIER: {
5725                         int ptr = ins->sreg1;
5726                         int value = ins->sreg2;
5727                         guchar *br = 0;
5728                         int nursery_shift, card_table_shift;
5729                         gpointer card_table_mask;
5730                         size_t nursery_size;
5731
5732                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5733                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5734                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5735
5736                         /*If either point to the stack we can simply avoid the WB. This happens due to
5737                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5738                          */
5739                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5740                                 continue;
5741
5742                         /*
5743                          * We need one register we can clobber, we choose EDX and make sreg1
5744                          * fixed EAX to work around limitations in the local register allocator.
5745                          * sreg2 might get allocated to EDX, but that is not a problem since
5746                          * we use it before clobbering EDX.
5747                          */
5748                         g_assert (ins->sreg1 == AMD64_RAX);
5749
5750                         /*
5751                          * This is the code we produce:
5752                          *
5753                          *   edx = value
5754                          *   edx >>= nursery_shift
5755                          *   cmp edx, (nursery_start >> nursery_shift)
5756                          *   jne done
5757                          *   edx = ptr
5758                          *   edx >>= card_table_shift
5759                          *   edx += cardtable
5760                          *   [edx] = 1
5761                          * done:
5762                          */
5763
5764                         if (mono_gc_card_table_nursery_check ()) {
5765                                 if (value != AMD64_RDX)
5766                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5767                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5768                                 if (shifted_nursery_start >> 31) {
5769                                         /*
5770                                          * The value we need to compare against is 64 bits, so we need
5771                                          * another spare register.  We use RBX, which we save and
5772                                          * restore.
5773                                          */
5774                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5775                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5776                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5777                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5778                                 } else {
5779                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5780                                 }
5781                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5782                         }
5783                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5784                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5785                         if (card_table_mask)
5786                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5787
5788                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5789                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5790
5791                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5792
5793                         if (mono_gc_card_table_nursery_check ())
5794                                 x86_patch (br, code);
5795                         break;
5796                 }
5797 #ifdef MONO_ARCH_SIMD_INTRINSICS
5798                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5799                 case OP_ADDPS:
5800                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_DIVPS:
5803                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_MULPS:
5806                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_SUBPS:
5809                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5810                         break;
5811                 case OP_MAXPS:
5812                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5813                         break;
5814                 case OP_MINPS:
5815                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5816                         break;
5817                 case OP_COMPPS:
5818                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5819                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5820                         break;
5821                 case OP_ANDPS:
5822                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_ANDNPS:
5825                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_ORPS:
5828                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5829                         break;
5830                 case OP_XORPS:
5831                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5832                         break;
5833                 case OP_SQRTPS:
5834                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5835                         break;
5836                 case OP_RSQRTPS:
5837                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5838                         break;
5839                 case OP_RCPPS:
5840                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5841                         break;
5842                 case OP_ADDSUBPS:
5843                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845                 case OP_HADDPS:
5846                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_HSUBPS:
5849                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851                 case OP_DUPPS_HIGH:
5852                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5853                         break;
5854                 case OP_DUPPS_LOW:
5855                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5856                         break;
5857
5858                 case OP_PSHUFLEW_HIGH:
5859                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5860                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5861                         break;
5862                 case OP_PSHUFLEW_LOW:
5863                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5864                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5865                         break;
5866                 case OP_PSHUFLED:
5867                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5868                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5869                         break;
5870                 case OP_SHUFPS:
5871                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5872                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5873                         break;
5874                 case OP_SHUFPD:
5875                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5876                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5877                         break;
5878
5879                 case OP_ADDPD:
5880                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_DIVPD:
5883                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_MULPD:
5886                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887                         break;
5888                 case OP_SUBPD:
5889                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5890                         break;
5891                 case OP_MAXPD:
5892                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_MINPD:
5895                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_COMPPD:
5898                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5899                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5900                         break;
5901                 case OP_ANDPD:
5902                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_ANDNPD:
5905                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_ORPD:
5908                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_XORPD:
5911                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_SQRTPD:
5914                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5915                         break;
5916                 case OP_ADDSUBPD:
5917                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_HADDPD:
5920                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_HSUBPD:
5923                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_DUPPD:
5926                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5927                         break;
5928
5929                 case OP_EXTRACT_MASK:
5930                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5931                         break;
5932
5933                 case OP_PAND:
5934                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_POR:
5937                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PXOR:
5940                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942
5943                 case OP_PADDB:
5944                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PADDW:
5947                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_PADDD:
5950                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PADDQ:
5953                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955
5956                 case OP_PSUBB:
5957                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_PSUBW:
5960                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PSUBD:
5963                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PSUBQ:
5966                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PMAXB_UN:
5970                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PMAXW_UN:
5973                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMAXD_UN:
5976                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_PMAXB:
5980                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PMAXW:
5983                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PMAXD:
5986                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988
5989                 case OP_PAVGB_UN:
5990                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_PAVGW_UN:
5993                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995
5996                 case OP_PMINB_UN:
5997                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_PMINW_UN:
6000                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PMIND_UN:
6003                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005
6006                 case OP_PMINB:
6007                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_PMINW:
6010                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PMIND:
6013                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015
6016                 case OP_PCMPEQB:
6017                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_PCMPEQW:
6020                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_PCMPEQD:
6023                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_PCMPEQQ:
6026                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028
6029                 case OP_PCMPGTB:
6030                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_PCMPGTW:
6033                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PCMPGTD:
6036                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_PCMPGTQ:
6039                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041
6042                 case OP_PSUM_ABS_DIFF:
6043                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045
6046                 case OP_UNPACK_LOWB:
6047                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_UNPACK_LOWW:
6050                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_UNPACK_LOWD:
6053                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_UNPACK_LOWQ:
6056                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058                 case OP_UNPACK_LOWPS:
6059                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_UNPACK_LOWPD:
6062                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064
6065                 case OP_UNPACK_HIGHB:
6066                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_UNPACK_HIGHW:
6069                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_UNPACK_HIGHD:
6072                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_UNPACK_HIGHQ:
6075                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_UNPACK_HIGHPS:
6078                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_UNPACK_HIGHPD:
6081                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083
6084                 case OP_PACKW:
6085                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PACKD:
6088                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PACKW_UN:
6091                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PACKD_UN:
6094                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096
6097                 case OP_PADDB_SAT_UN:
6098                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PSUBB_SAT_UN:
6101                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_PADDW_SAT_UN:
6104                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PSUBW_SAT_UN:
6107                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109
6110                 case OP_PADDB_SAT:
6111                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113                 case OP_PSUBB_SAT:
6114                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_PADDW_SAT:
6117                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PSUBW_SAT:
6120                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122
6123                 case OP_PMULW:
6124                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PMULD:
6127                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PMULQ:
6130                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PMULW_HIGH_UN:
6133                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_PMULW_HIGH:
6136                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138
6139                 case OP_PSHRW:
6140                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6141                         break;
6142                 case OP_PSHRW_REG:
6143                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6144                         break;
6145
6146                 case OP_PSARW:
6147                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6148                         break;
6149                 case OP_PSARW_REG:
6150                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6151                         break;
6152
6153                 case OP_PSHLW:
6154                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6155                         break;
6156                 case OP_PSHLW_REG:
6157                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6158                         break;
6159
6160                 case OP_PSHRD:
6161                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6162                         break;
6163                 case OP_PSHRD_REG:
6164                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6165                         break;
6166
6167                 case OP_PSARD:
6168                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6169                         break;
6170                 case OP_PSARD_REG:
6171                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6172                         break;
6173
6174                 case OP_PSHLD:
6175                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6176                         break;
6177                 case OP_PSHLD_REG:
6178                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6179                         break;
6180
6181                 case OP_PSHRQ:
6182                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6183                         break;
6184                 case OP_PSHRQ_REG:
6185                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6186                         break;
6187
6188                 /*TODO: This is appart of the sse spec but not added
6189                 case OP_PSARQ:
6190                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6191                         break;
6192                 case OP_PSARQ_REG:
6193                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6194                         break;
6195                 */
6196
6197                 case OP_PSHLQ:
6198                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6199                         break;
6200                 case OP_PSHLQ_REG:
6201                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6202                         break;
6203                 case OP_CVTDQ2PD:
6204                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206                 case OP_CVTDQ2PS:
6207                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6208                         break;
6209                 case OP_CVTPD2DQ:
6210                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6211                         break;
6212                 case OP_CVTPD2PS:
6213                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6214                         break;
6215                 case OP_CVTPS2DQ:
6216                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6217                         break;
6218                 case OP_CVTPS2PD:
6219                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6220                         break;
6221                 case OP_CVTTPD2DQ:
6222                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6223                         break;
6224                 case OP_CVTTPS2DQ:
6225                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6226                         break;
6227
6228                 case OP_ICONV_TO_X:
6229                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6230                         break;
6231                 case OP_EXTRACT_I4:
6232                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6233                         break;
6234                 case OP_EXTRACT_I8:
6235                         if (ins->inst_c0) {
6236                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6237                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6238                         } else {
6239                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6240                         }
6241                         break;
6242                 case OP_EXTRACT_I1:
6243                 case OP_EXTRACT_U1:
6244                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6245                         if (ins->inst_c0)
6246                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6247                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6248                         break;
6249                 case OP_EXTRACT_I2:
6250                 case OP_EXTRACT_U2:
6251                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6252                         if (ins->inst_c0)
6253                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6254                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6255                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6256                         break;
6257                 case OP_EXTRACT_R8:
6258                         if (ins->inst_c0)
6259                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6260                         else
6261                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6262                         break;
6263                 case OP_INSERT_I2:
6264                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6265                         break;
6266                 case OP_EXTRACTX_U2:
6267                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6268                         break;
6269                 case OP_INSERTX_U1_SLOW:
6270                         /*sreg1 is the extracted ireg (scratch)
6271                         /sreg2 is the to be inserted ireg (scratch)
6272                         /dreg is the xreg to receive the value*/
6273
6274                         /*clear the bits from the extracted word*/
6275                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6276                         /*shift the value to insert if needed*/
6277                         if (ins->inst_c0 & 1)
6278                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6279                         /*join them together*/
6280                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6281                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6282                         break;
6283                 case OP_INSERTX_I4_SLOW:
6284                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6285                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6286                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6287                         break;
6288                 case OP_INSERTX_I8_SLOW:
6289                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6290                         if (ins->inst_c0)
6291                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6292                         else
6293                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6294                         break;
6295
6296                 case OP_INSERTX_R4_SLOW:
6297                         switch (ins->inst_c0) {
6298                         case 0:
6299                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6300                                 break;
6301                         case 1:
6302                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6303                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6304                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6305                                 break;
6306                         case 2:
6307                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6308                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6309                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6310                                 break;
6311                         case 3:
6312                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6313                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6314                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6315                                 break;
6316                         }
6317                         break;
6318                 case OP_INSERTX_R8_SLOW:
6319                         if (ins->inst_c0)
6320                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6321                         else
6322                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6323                         break;
6324                 case OP_STOREX_MEMBASE_REG:
6325                 case OP_STOREX_MEMBASE:
6326                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6327                         break;
6328                 case OP_LOADX_MEMBASE:
6329                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6330                         break;
6331                 case OP_LOADX_ALIGNED_MEMBASE:
6332                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6333                         break;
6334                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6335                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6336                         break;
6337                 case OP_STOREX_NTA_MEMBASE_REG:
6338                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6339                         break;
6340                 case OP_PREFETCH_MEMBASE:
6341                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6342                         break;
6343
6344                 case OP_XMOVE:
6345                         /*FIXME the peephole pass should have killed this*/
6346                         if (ins->dreg != ins->sreg1)
6347                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6348                         break;
6349                 case OP_XZERO:
6350                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6351                         break;
6352                 case OP_ICONV_TO_R8_RAW:
6353                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6354                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6355                         break;
6356
6357                 case OP_FCONV_TO_R8_X:
6358                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6359                         break;
6360
6361                 case OP_XCONV_R8_TO_I4:
6362                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6363                         switch (ins->backend.source_opcode) {
6364                         case OP_FCONV_TO_I1:
6365                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6366                                 break;
6367                         case OP_FCONV_TO_U1:
6368                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6369                                 break;
6370                         case OP_FCONV_TO_I2:
6371                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6372                                 break;
6373                         case OP_FCONV_TO_U2:
6374                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6375                                 break;
6376                         }
6377                         break;
6378
6379                 case OP_EXPAND_I2:
6380                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6381                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6382                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6383                         break;
6384                 case OP_EXPAND_I4:
6385                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6386                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6387                         break;
6388                 case OP_EXPAND_I8:
6389                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6390                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6391                         break;
6392                 case OP_EXPAND_R4:
6393                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6394                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6396                         break;
6397                 case OP_EXPAND_R8:
6398                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6400                         break;
6401 #endif
6402                 case OP_LIVERANGE_START: {
6403                         if (cfg->verbose_level > 1)
6404                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6405                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6406                         break;
6407                 }
6408                 case OP_LIVERANGE_END: {
6409                         if (cfg->verbose_level > 1)
6410                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6411                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6412                         break;
6413                 }
6414                 case OP_NACL_GC_SAFE_POINT: {
6415 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6416                         if (cfg->compile_aot)
6417                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6418                         else {
6419                                 guint8 *br [1];
6420
6421                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6422                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6423                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6424                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6425                                 amd64_patch (br[0], code);
6426                         }
6427 #endif
6428                         break;
6429                 }
6430                 case OP_GC_LIVENESS_DEF:
6431                 case OP_GC_LIVENESS_USE:
6432                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6433                         ins->backend.pc_offset = code - cfg->native_code;
6434                         break;
6435                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6436                         ins->backend.pc_offset = code - cfg->native_code;
6437                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6438                         break;
6439                 default:
6440                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6441                         g_assert_not_reached ();
6442                 }
6443
6444                 if ((code - cfg->native_code - offset) > max_len) {
6445 #if !defined(__native_client_codegen__)
6446                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6447                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6448                         g_assert_not_reached ();
6449 #endif
6450                 }
6451
6452                 last_ins = ins;
6453                 last_offset = offset;
6454         }
6455
6456         cfg->code_len = code - cfg->native_code;
6457 }
6458
6459 #endif /* DISABLE_JIT */
6460
6461 void
6462 mono_arch_register_lowlevel_calls (void)
6463 {
6464         /* The signature doesn't matter */
6465         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6466 }
6467
6468 void
6469 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6470 {
6471         MonoJumpInfo *patch_info;
6472         gboolean compile_aot = !run_cctors;
6473
6474         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6475                 unsigned char *ip = patch_info->ip.i + code;
6476                 unsigned char *target;
6477
6478                 if (compile_aot) {
6479                         switch (patch_info->type) {
6480                         case MONO_PATCH_INFO_BB:
6481                         case MONO_PATCH_INFO_LABEL:
6482                                 break;
6483                         default:
6484                                 /* No need to patch these */
6485                                 continue;
6486                         }
6487                 }
6488
6489                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6490
6491                 switch (patch_info->type) {
6492                 case MONO_PATCH_INFO_NONE:
6493                         continue;
6494                 case MONO_PATCH_INFO_METHOD_REL:
6495                 case MONO_PATCH_INFO_R8:
6496                 case MONO_PATCH_INFO_R4:
6497                         g_assert_not_reached ();
6498                         continue;
6499                 case MONO_PATCH_INFO_BB:
6500                         break;
6501                 default:
6502                         break;
6503                 }
6504
6505                 /*
6506                  * Debug code to help track down problems where the target of a near call is
6507                  * is not valid.
6508                  */
6509                 if (amd64_is_near_call (ip)) {
6510                         gint64 disp = (guint8*)target - (guint8*)ip;
6511
6512                         if (!amd64_is_imm32 (disp)) {
6513                                 printf ("TYPE: %d\n", patch_info->type);
6514                                 switch (patch_info->type) {
6515                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6516                                         printf ("V: %s\n", patch_info->data.name);
6517                                         break;
6518                                 case MONO_PATCH_INFO_METHOD_JUMP:
6519                                 case MONO_PATCH_INFO_METHOD:
6520                                         printf ("V: %s\n", patch_info->data.method->name);
6521                                         break;
6522                                 default:
6523                                         break;
6524                                 }
6525                         }
6526                 }
6527
6528                 amd64_patch (ip, (gpointer)target);
6529         }
6530 }
6531
6532 #ifndef DISABLE_JIT
6533
6534 static int
6535 get_max_epilog_size (MonoCompile *cfg)
6536 {
6537         int max_epilog_size = 16;
6538
6539         if (cfg->method->save_lmf)
6540                 max_epilog_size += 256;
6541
6542         if (mono_jit_trace_calls != NULL)
6543                 max_epilog_size += 50;
6544
6545         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6546                 max_epilog_size += 50;
6547
6548         max_epilog_size += (AMD64_NREG * 2);
6549
6550         return max_epilog_size;
6551 }
6552
6553 /*
6554  * This macro is used for testing whenever the unwinder works correctly at every point
6555  * where an async exception can happen.
6556  */
6557 /* This will generate a SIGSEGV at the given point in the code */
6558 #define async_exc_point(code) do { \
6559     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6560          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6561              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6562          cfg->arch.async_point_count ++; \
6563     } \
6564 } while (0)
6565
6566 guint8 *
6567 mono_arch_emit_prolog (MonoCompile *cfg)
6568 {
6569         MonoMethod *method = cfg->method;
6570         MonoBasicBlock *bb;
6571         MonoMethodSignature *sig;
6572         MonoInst *ins;
6573         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6574         guint8 *code;
6575         CallInfo *cinfo;
6576         MonoInst *lmf_var = cfg->lmf_var;
6577         gboolean args_clobbered = FALSE;
6578         gboolean trace = FALSE;
6579 #ifdef __native_client_codegen__
6580         guint alignment_check;
6581 #endif
6582
6583         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6584
6585 #if defined(__default_codegen__)
6586         code = cfg->native_code = g_malloc (cfg->code_size);
6587 #elif defined(__native_client_codegen__)
6588         /* native_code_alloc is not 32-byte aligned, native_code is. */
6589         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6590
6591         /* Align native_code to next nearest kNaclAlignment byte. */
6592         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6593         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6594
6595         code = cfg->native_code;
6596
6597         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6598         g_assert (alignment_check == 0);
6599 #endif
6600
6601         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6602                 trace = TRUE;
6603
6604         /* Amount of stack space allocated by register saving code */
6605         pos = 0;
6606
6607         /* Offset between RSP and the CFA */
6608         cfa_offset = 0;
6609
6610         /*
6611          * The prolog consists of the following parts:
6612          * FP present:
6613          * - push rbp, mov rbp, rsp
6614          * - save callee saved regs using pushes
6615          * - allocate frame
6616          * - save rgctx if needed
6617          * - save lmf if needed
6618          * FP not present:
6619          * - allocate frame
6620          * - save rgctx if needed
6621          * - save lmf if needed
6622          * - save callee saved regs using moves
6623          */
6624
6625         // CFA = sp + 8
6626         cfa_offset = 8;
6627         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6628         // IP saved at CFA - 8
6629         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6630         async_exc_point (code);
6631         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6632
6633         if (!cfg->arch.omit_fp) {
6634                 amd64_push_reg (code, AMD64_RBP);
6635                 cfa_offset += 8;
6636                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6637                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6638                 async_exc_point (code);
6639 #ifdef HOST_WIN32
6640                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6641 #endif
6642                 /* These are handled automatically by the stack marking code */
6643                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6644
6645                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6646                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6647                 async_exc_point (code);
6648 #ifdef HOST_WIN32
6649                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6650 #endif
6651         }
6652
6653         /* The param area is always at offset 0 from sp */
6654         /* This needs to be allocated here, since it has to come after the spill area */
6655         if (cfg->param_area) {
6656                 if (cfg->arch.omit_fp)
6657                         // FIXME:
6658                         g_assert_not_reached ();
6659                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6660         }
6661
6662         if (cfg->arch.omit_fp) {
6663                 /*
6664                  * On enter, the stack is misaligned by the pushing of the return
6665                  * address. It is either made aligned by the pushing of %rbp, or by
6666                  * this.
6667                  */
6668                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6669                 if ((alloc_size % 16) == 0) {
6670                         alloc_size += 8;
6671                         /* Mark the padding slot as NOREF */
6672                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6673                 }
6674         } else {
6675                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6676                 if (cfg->stack_offset != alloc_size) {
6677                         /* Mark the padding slot as NOREF */
6678                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6679                 }
6680                 cfg->arch.sp_fp_offset = alloc_size;
6681                 alloc_size -= pos;
6682         }
6683
6684         cfg->arch.stack_alloc_size = alloc_size;
6685
6686         /* Allocate stack frame */
6687         if (alloc_size) {
6688                 /* See mono_emit_stack_alloc */
6689 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6690                 guint32 remaining_size = alloc_size;
6691                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6692                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6693                 guint32 offset = code - cfg->native_code;
6694                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6695                         while (required_code_size >= (cfg->code_size - offset))
6696                                 cfg->code_size *= 2;
6697                         cfg->native_code = mono_realloc_native_code (cfg);
6698                         code = cfg->native_code + offset;
6699                         cfg->stat_code_reallocs++;
6700                 }
6701
6702                 while (remaining_size >= 0x1000) {
6703                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6704                         if (cfg->arch.omit_fp) {
6705                                 cfa_offset += 0x1000;
6706                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6707                         }
6708                         async_exc_point (code);
6709 #ifdef HOST_WIN32
6710                         if (cfg->arch.omit_fp)
6711                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6712 #endif
6713
6714                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6715                         remaining_size -= 0x1000;
6716                 }
6717                 if (remaining_size) {
6718                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6719                         if (cfg->arch.omit_fp) {
6720                                 cfa_offset += remaining_size;
6721                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6722                                 async_exc_point (code);
6723                         }
6724 #ifdef HOST_WIN32
6725                         if (cfg->arch.omit_fp)
6726                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6727 #endif
6728                 }
6729 #else
6730                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6731                 if (cfg->arch.omit_fp) {
6732                         cfa_offset += alloc_size;
6733                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6734                         async_exc_point (code);
6735                 }
6736 #endif
6737         }
6738
6739         /* Stack alignment check */
6740 #if 0
6741         {
6742                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6743                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6744                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6745                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6746                 amd64_breakpoint (code);
6747         }
6748 #endif
6749
6750         if (mini_get_debug_options ()->init_stacks) {
6751                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6752
6753                 /* Save registers to the red zone */
6754                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6755                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6756
6757                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6758                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6759                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6760
6761                 amd64_cld (code);
6762 #if defined(__default_codegen__)
6763                 amd64_prefix (code, X86_REP_PREFIX);
6764                 amd64_stosl (code);
6765 #elif defined(__native_client_codegen__)
6766                 /* NaCl stos pseudo-instruction */
6767                 amd64_codegen_pre (code);
6768                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6769                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6770                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6771                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6772                 amd64_prefix (code, X86_REP_PREFIX);
6773                 amd64_stosl (code);
6774                 amd64_codegen_post (code);
6775 #endif /* __native_client_codegen__ */
6776
6777                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6778                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6779         }
6780
6781         /* Save LMF */
6782         if (method->save_lmf)
6783                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6784
6785         /* Save callee saved registers */
6786         if (cfg->arch.omit_fp) {
6787                 save_area_offset = cfg->arch.reg_save_area_offset;
6788                 /* Save caller saved registers after sp is adjusted */
6789                 /* The registers are saved at the bottom of the frame */
6790                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6791         } else {
6792                 /* The registers are saved just below the saved rbp */
6793                 save_area_offset = cfg->arch.reg_save_area_offset;
6794         }
6795
6796         for (i = 0; i < AMD64_NREG; ++i) {
6797                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6798                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6799
6800                         if (cfg->arch.omit_fp) {
6801                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6802                                 /* These are handled automatically by the stack marking code */
6803                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6804                         } else {
6805                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6806                                 // FIXME: GC
6807                         }
6808
6809                         save_area_offset += 8;
6810                         async_exc_point (code);
6811                 }
6812         }
6813
6814         /* store runtime generic context */
6815         if (cfg->rgctx_var) {
6816                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6817                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6818
6819                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6820
6821                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6822                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6823         }
6824
6825         /* compute max_length in order to use short forward jumps */
6826         max_epilog_size = get_max_epilog_size (cfg);
6827         if (cfg->opt & MONO_OPT_BRANCH) {
6828                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6829                         MonoInst *ins;
6830                         int max_length = 0;
6831
6832                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6833                                 max_length += 6;
6834                         /* max alignment for loops */
6835                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6836                                 max_length += LOOP_ALIGNMENT;
6837 #ifdef __native_client_codegen__
6838                         /* max alignment for native client */
6839                         max_length += kNaClAlignment;
6840 #endif
6841
6842                         MONO_BB_FOR_EACH_INS (bb, ins) {
6843 #ifdef __native_client_codegen__
6844                                 {
6845                                         int space_in_block = kNaClAlignment -
6846                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6847                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6848                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6849                                                 max_length += space_in_block;
6850                                         }
6851                                 }
6852 #endif  /*__native_client_codegen__*/
6853                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6854                         }
6855
6856                         /* Take prolog and epilog instrumentation into account */
6857                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6858                                 max_length += max_epilog_size;
6859
6860                         bb->max_length = max_length;
6861                 }
6862         }
6863
6864         sig = mono_method_signature (method);
6865         pos = 0;
6866
6867         cinfo = cfg->arch.cinfo;
6868
6869         if (sig->ret->type != MONO_TYPE_VOID) {
6870                 /* Save volatile arguments to the stack */
6871                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6872                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6873         }
6874
6875         /* Keep this in sync with emit_load_volatile_arguments */
6876         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6877                 ArgInfo *ainfo = cinfo->args + i;
6878                 gint32 stack_offset;
6879                 MonoType *arg_type;
6880
6881                 ins = cfg->args [i];
6882
6883                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6884                         /* Unused arguments */
6885                         continue;
6886
6887                 if (sig->hasthis && (i == 0))
6888                         arg_type = &mono_defaults.object_class->byval_arg;
6889                 else
6890                         arg_type = sig->params [i - sig->hasthis];
6891
6892                 stack_offset = ainfo->offset + ARGS_OFFSET;
6893
6894                 if (cfg->globalra) {
6895                         /* All the other moves are done by the register allocator */
6896                         switch (ainfo->storage) {
6897                         case ArgInFloatSSEReg:
6898                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6899                                 break;
6900                         case ArgValuetypeInReg:
6901                                 for (quad = 0; quad < 2; quad ++) {
6902                                         switch (ainfo->pair_storage [quad]) {
6903                                         case ArgInIReg:
6904                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6905                                                 break;
6906                                         case ArgInFloatSSEReg:
6907                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6908                                                 break;
6909                                         case ArgInDoubleSSEReg:
6910                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6911                                                 break;
6912                                         case ArgNone:
6913                                                 break;
6914                                         default:
6915                                                 g_assert_not_reached ();
6916                                         }
6917                                 }
6918                                 break;
6919                         default:
6920                                 break;
6921                         }
6922
6923                         continue;
6924                 }
6925
6926                 /* Save volatile arguments to the stack */
6927                 if (ins->opcode != OP_REGVAR) {
6928                         switch (ainfo->storage) {
6929                         case ArgInIReg: {
6930                                 guint32 size = 8;
6931
6932                                 /* FIXME: I1 etc */
6933                                 /*
6934                                 if (stack_offset & 0x1)
6935                                         size = 1;
6936                                 else if (stack_offset & 0x2)
6937                                         size = 2;
6938                                 else if (stack_offset & 0x4)
6939                                         size = 4;
6940                                 else
6941                                         size = 8;
6942                                 */
6943                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6944
6945                                 /*
6946                                  * Save the original location of 'this',
6947                                  * get_generic_info_from_stack_frame () needs this to properly look up
6948                                  * the argument value during the handling of async exceptions.
6949                                  */
6950                                 if (ins == cfg->args [0]) {
6951                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6952                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6953                                 }
6954                                 break;
6955                         }
6956                         case ArgInFloatSSEReg:
6957                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6958                                 break;
6959                         case ArgInDoubleSSEReg:
6960                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6961                                 break;
6962                         case ArgValuetypeInReg:
6963                                 for (quad = 0; quad < 2; quad ++) {
6964                                         switch (ainfo->pair_storage [quad]) {
6965                                         case ArgInIReg:
6966                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6967                                                 break;
6968                                         case ArgInFloatSSEReg:
6969                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6970                                                 break;
6971                                         case ArgInDoubleSSEReg:
6972                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6973                                                 break;
6974                                         case ArgNone:
6975                                                 break;
6976                                         default:
6977                                                 g_assert_not_reached ();
6978                                         }
6979                                 }
6980                                 break;
6981                         case ArgValuetypeAddrInIReg:
6982                                 if (ainfo->pair_storage [0] == ArgInIReg)
6983                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6984                                 break;
6985                         default:
6986                                 break;
6987                         }
6988                 } else {
6989                         /* Argument allocated to (non-volatile) register */
6990                         switch (ainfo->storage) {
6991                         case ArgInIReg:
6992                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6993                                 break;
6994                         case ArgOnStack:
6995                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6996                                 break;
6997                         default:
6998                                 g_assert_not_reached ();
6999                         }
7000
7001                         if (ins == cfg->args [0]) {
7002                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7003                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7004                         }
7005                 }
7006         }
7007
7008         if (cfg->method->save_lmf)
7009                 args_clobbered = TRUE;
7010
7011         if (trace) {
7012                 args_clobbered = TRUE;
7013                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7014         }
7015
7016         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7017                 args_clobbered = TRUE;
7018
7019         /*
7020          * Optimize the common case of the first bblock making a call with the same
7021          * arguments as the method. This works because the arguments are still in their
7022          * original argument registers.
7023          * FIXME: Generalize this
7024          */
7025         if (!args_clobbered) {
7026                 MonoBasicBlock *first_bb = cfg->bb_entry;
7027                 MonoInst *next;
7028                 int filter = FILTER_IL_SEQ_POINT;
7029
7030                 next = mono_bb_first_inst (first_bb, filter);
7031                 if (!next && first_bb->next_bb) {
7032                         first_bb = first_bb->next_bb;
7033                         next = mono_bb_first_inst (first_bb, filter);
7034                 }
7035
7036                 if (first_bb->in_count > 1)
7037                         next = NULL;
7038
7039                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7040                         ArgInfo *ainfo = cinfo->args + i;
7041                         gboolean match = FALSE;
7042
7043                         ins = cfg->args [i];
7044                         if (ins->opcode != OP_REGVAR) {
7045                                 switch (ainfo->storage) {
7046                                 case ArgInIReg: {
7047                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7048                                                 if (next->dreg == ainfo->reg) {
7049                                                         NULLIFY_INS (next);
7050                                                         match = TRUE;
7051                                                 } else {
7052                                                         next->opcode = OP_MOVE;
7053                                                         next->sreg1 = ainfo->reg;
7054                                                         /* Only continue if the instruction doesn't change argument regs */
7055                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7056                                                                 match = TRUE;
7057                                                 }
7058                                         }
7059                                         break;
7060                                 }
7061                                 default:
7062                                         break;
7063                                 }
7064                         } else {
7065                                 /* Argument allocated to (non-volatile) register */
7066                                 switch (ainfo->storage) {
7067                                 case ArgInIReg:
7068                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7069                                                 NULLIFY_INS (next);
7070                                                 match = TRUE;
7071                                         }
7072                                         break;
7073                                 default:
7074                                         break;
7075                                 }
7076                         }
7077
7078                         if (match) {
7079                                 next = mono_inst_next (next, filter);
7080                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7081                                 if (!next)
7082                                         break;
7083                         }
7084                 }
7085         }
7086
7087         if (cfg->gen_seq_points_debug_data) {
7088                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7089
7090                 /* Initialize seq_point_info_var */
7091                 if (cfg->compile_aot) {
7092                         /* Initialize the variable from a GOT slot */
7093                         /* Same as OP_AOTCONST */
7094                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7095                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7096                         g_assert (info_var->opcode == OP_REGOFFSET);
7097                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7098                 }
7099
7100                 /* Initialize ss_trigger_page_var */
7101                 ins = cfg->arch.ss_trigger_page_var;
7102
7103                 g_assert (ins->opcode == OP_REGOFFSET);
7104
7105                 if (cfg->compile_aot) {
7106                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7107                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7108                 } else {
7109                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7110                 }
7111                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7112         }
7113
7114         cfg->code_len = code - cfg->native_code;
7115
7116         g_assert (cfg->code_len < cfg->code_size);
7117
7118         return code;
7119 }
7120
7121 void
7122 mono_arch_emit_epilog (MonoCompile *cfg)
7123 {
7124         MonoMethod *method = cfg->method;
7125         int quad, pos, i;
7126         guint8 *code;
7127         int max_epilog_size;
7128         CallInfo *cinfo;
7129         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7130         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7131
7132         max_epilog_size = get_max_epilog_size (cfg);
7133
7134         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7135                 cfg->code_size *= 2;
7136                 cfg->native_code = mono_realloc_native_code (cfg);
7137                 cfg->stat_code_reallocs++;
7138         }
7139         code = cfg->native_code + cfg->code_len;
7140
7141         cfg->has_unwind_info_for_epilog = TRUE;
7142
7143         /* Mark the start of the epilog */
7144         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7145
7146         /* Save the uwind state which is needed by the out-of-line code */
7147         mono_emit_unwind_op_remember_state (cfg, code);
7148
7149         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7150                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7151
7152         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7153         pos = 0;
7154
7155         if (method->save_lmf) {
7156                 /* check if we need to restore protection of the stack after a stack overflow */
7157                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7158                         guint8 *patch;
7159                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7160                         /* we load the value in a separate instruction: this mechanism may be
7161                          * used later as a safer way to do thread interruption
7162                          */
7163                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7164                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7165                         patch = code;
7166                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7167                         /* note that the call trampoline will preserve eax/edx */
7168                         x86_call_reg (code, X86_ECX);
7169                         x86_patch (patch, code);
7170                 } else {
7171                         /* FIXME: maybe save the jit tls in the prolog */
7172                 }
7173                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7174                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7175                 }
7176         }
7177
7178         /* Restore callee saved regs */
7179         for (i = 0; i < AMD64_NREG; ++i) {
7180                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7181                         /* Restore only used_int_regs, not arch.saved_iregs */
7182                         if (cfg->used_int_regs & (1 << i)) {
7183                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7184                                 mono_emit_unwind_op_same_value (cfg, code, i);
7185                                 async_exc_point (code);
7186                         }
7187                         save_area_offset += 8;
7188                 }
7189         }
7190
7191         /* Load returned vtypes into registers if needed */
7192         cinfo = cfg->arch.cinfo;
7193         if (cinfo->ret.storage == ArgValuetypeInReg) {
7194                 ArgInfo *ainfo = &cinfo->ret;
7195                 MonoInst *inst = cfg->ret;
7196
7197                 for (quad = 0; quad < 2; quad ++) {
7198                         switch (ainfo->pair_storage [quad]) {
7199                         case ArgInIReg:
7200                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7201                                 break;
7202                         case ArgInFloatSSEReg:
7203                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7204                                 break;
7205                         case ArgInDoubleSSEReg:
7206                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7207                                 break;
7208                         case ArgNone:
7209                                 break;
7210                         default:
7211                                 g_assert_not_reached ();
7212                         }
7213                 }
7214         }
7215
7216         if (cfg->arch.omit_fp) {
7217                 if (cfg->arch.stack_alloc_size) {
7218                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7219                 }
7220         } else {
7221                 amd64_leave (code);
7222                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7223         }
7224         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7225         async_exc_point (code);
7226         amd64_ret (code);
7227
7228         /* Restore the unwind state to be the same as before the epilog */
7229         mono_emit_unwind_op_restore_state (cfg, code);
7230
7231         cfg->code_len = code - cfg->native_code;
7232
7233         g_assert (cfg->code_len < cfg->code_size);
7234 }
7235
7236 void
7237 mono_arch_emit_exceptions (MonoCompile *cfg)
7238 {
7239         MonoJumpInfo *patch_info;
7240         int nthrows, i;
7241         guint8 *code;
7242         MonoClass *exc_classes [16];
7243         guint8 *exc_throw_start [16], *exc_throw_end [16];
7244         guint32 code_size = 0;
7245
7246         /* Compute needed space */
7247         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7248                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7249                         code_size += 40;
7250                 if (patch_info->type == MONO_PATCH_INFO_R8)
7251                         code_size += 8 + 15; /* sizeof (double) + alignment */
7252                 if (patch_info->type == MONO_PATCH_INFO_R4)
7253                         code_size += 4 + 15; /* sizeof (float) + alignment */
7254                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7255                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7256         }
7257
7258 #ifdef __native_client_codegen__
7259         /* Give us extra room on Native Client.  This could be   */
7260         /* more carefully calculated, but bundle alignment makes */
7261         /* it much trickier, so *2 like other places is good.    */
7262         code_size *= 2;
7263 #endif
7264
7265         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7266                 cfg->code_size *= 2;
7267                 cfg->native_code = mono_realloc_native_code (cfg);
7268                 cfg->stat_code_reallocs++;
7269         }
7270
7271         code = cfg->native_code + cfg->code_len;
7272
7273         /* add code to raise exceptions */
7274         nthrows = 0;
7275         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7276                 switch (patch_info->type) {
7277                 case MONO_PATCH_INFO_EXC: {
7278                         MonoClass *exc_class;
7279                         guint8 *buf, *buf2;
7280                         guint32 throw_ip;
7281
7282                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7283
7284                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7285                         g_assert (exc_class);
7286                         throw_ip = patch_info->ip.i;
7287
7288                         //x86_breakpoint (code);
7289                         /* Find a throw sequence for the same exception class */
7290                         for (i = 0; i < nthrows; ++i)
7291                                 if (exc_classes [i] == exc_class)
7292                                         break;
7293                         if (i < nthrows) {
7294                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7295                                 x86_jump_code (code, exc_throw_start [i]);
7296                                 patch_info->type = MONO_PATCH_INFO_NONE;
7297                         }
7298                         else {
7299                                 buf = code;
7300                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7301                                 buf2 = code;
7302
7303                                 if (nthrows < 16) {
7304                                         exc_classes [nthrows] = exc_class;
7305                                         exc_throw_start [nthrows] = code;
7306                                 }
7307                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7308
7309                                 patch_info->type = MONO_PATCH_INFO_NONE;
7310
7311                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7312
7313                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7314                                 while (buf < buf2)
7315                                         x86_nop (buf);
7316
7317                                 if (nthrows < 16) {
7318                                         exc_throw_end [nthrows] = code;
7319                                         nthrows ++;
7320                                 }
7321                         }
7322                         break;
7323                 }
7324                 default:
7325                         /* do nothing */
7326                         break;
7327                 }
7328                 g_assert(code < cfg->native_code + cfg->code_size);
7329         }
7330
7331         /* Handle relocations with RIP relative addressing */
7332         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7333                 gboolean remove = FALSE;
7334                 guint8 *orig_code = code;
7335
7336                 switch (patch_info->type) {
7337                 case MONO_PATCH_INFO_R8:
7338                 case MONO_PATCH_INFO_R4: {
7339                         guint8 *pos, *patch_pos;
7340                         guint32 target_pos;
7341
7342                         /* The SSE opcodes require a 16 byte alignment */
7343 #if defined(__default_codegen__)
7344                         code = (guint8*)ALIGN_TO (code, 16);
7345 #elif defined(__native_client_codegen__)
7346                         {
7347                                 /* Pad this out with HLT instructions  */
7348                                 /* or we can get garbage bytes emitted */
7349                                 /* which will fail validation          */
7350                                 guint8 *aligned_code;
7351                                 /* extra align to make room for  */
7352                                 /* mov/push below                      */
7353                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7354                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7355                                 /* The technique of hiding data in an  */
7356                                 /* instruction has a problem here: we  */
7357                                 /* need the data aligned to a 16-byte  */
7358                                 /* boundary but the instruction cannot */
7359                                 /* cross the bundle boundary. so only  */
7360                                 /* odd multiples of 16 can be used     */
7361                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7362                                         aligned_code += 16;
7363                                 }
7364                                 while (code < aligned_code) {
7365                                         *(code++) = 0xf4; /* hlt */
7366                                 }
7367                         }
7368 #endif
7369
7370                         pos = cfg->native_code + patch_info->ip.i;
7371                         if (IS_REX (pos [1])) {
7372                                 patch_pos = pos + 5;
7373                                 target_pos = code - pos - 9;
7374                         }
7375                         else {
7376                                 patch_pos = pos + 4;
7377                                 target_pos = code - pos - 8;
7378                         }
7379
7380                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7381 #ifdef __native_client_codegen__
7382                                 /* Hide 64-bit data in a         */
7383                                 /* "mov imm64, r11" instruction. */
7384                                 /* write it before the start of  */
7385                                 /* the data*/
7386                                 *(code-2) = 0x49; /* prefix      */
7387                                 *(code-1) = 0xbb; /* mov X, %r11 */
7388 #endif
7389                                 *(double*)code = *(double*)patch_info->data.target;
7390                                 code += sizeof (double);
7391                         } else {
7392 #ifdef __native_client_codegen__
7393                                 /* Hide 32-bit data in a        */
7394                                 /* "push imm32" instruction.    */
7395                                 *(code-1) = 0x68; /* push */
7396 #endif
7397                                 *(float*)code = *(float*)patch_info->data.target;
7398                                 code += sizeof (float);
7399                         }
7400
7401                         *(guint32*)(patch_pos) = target_pos;
7402
7403                         remove = TRUE;
7404                         break;
7405                 }
7406                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7407                         guint8 *pos;
7408
7409                         if (cfg->compile_aot)
7410                                 continue;
7411
7412                         /*loading is faster against aligned addresses.*/
7413                         code = (guint8*)ALIGN_TO (code, 8);
7414                         memset (orig_code, 0, code - orig_code);
7415
7416                         pos = cfg->native_code + patch_info->ip.i;
7417
7418                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7419                         if (IS_REX (pos [1]))
7420                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7421                         else
7422                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7423
7424                         *(gpointer*)code = (gpointer)patch_info->data.target;
7425                         code += sizeof (gpointer);
7426
7427                         remove = TRUE;
7428                         break;
7429                 }
7430                 default:
7431                         break;
7432                 }
7433
7434                 if (remove) {
7435                         if (patch_info == cfg->patch_info)
7436                                 cfg->patch_info = patch_info->next;
7437                         else {
7438                                 MonoJumpInfo *tmp;
7439
7440                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7441                                         ;
7442                                 tmp->next = patch_info->next;
7443                         }
7444                 }
7445                 g_assert (code < cfg->native_code + cfg->code_size);
7446         }
7447
7448         cfg->code_len = code - cfg->native_code;
7449
7450         g_assert (cfg->code_len < cfg->code_size);
7451
7452 }
7453
7454 #endif /* DISABLE_JIT */
7455
7456 void*
7457 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7458 {
7459         guchar *code = p;
7460         CallInfo *cinfo = NULL;
7461         MonoMethodSignature *sig;
7462         MonoInst *inst;
7463         int i, n, stack_area = 0;
7464
7465         /* Keep this in sync with mono_arch_get_argument_info */
7466
7467         if (enable_arguments) {
7468                 /* Allocate a new area on the stack and save arguments there */
7469                 sig = mono_method_signature (cfg->method);
7470
7471                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7472
7473                 n = sig->param_count + sig->hasthis;
7474
7475                 stack_area = ALIGN_TO (n * 8, 16);
7476
7477                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7478
7479                 for (i = 0; i < n; ++i) {
7480                         inst = cfg->args [i];
7481
7482                         if (inst->opcode == OP_REGVAR)
7483                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7484                         else {
7485                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7486                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7487                         }
7488                 }
7489         }
7490
7491         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7492         amd64_set_reg_template (code, AMD64_ARG_REG1);
7493         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7494         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7495
7496         if (enable_arguments)
7497                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7498
7499         return code;
7500 }
7501
7502 enum {
7503         SAVE_NONE,
7504         SAVE_STRUCT,
7505         SAVE_EAX,
7506         SAVE_EAX_EDX,
7507         SAVE_XMM
7508 };
7509
7510 void*
7511 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7512 {
7513         guchar *code = p;
7514         int save_mode = SAVE_NONE;
7515         MonoMethod *method = cfg->method;
7516         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7517         int i;
7518
7519         switch (ret_type->type) {
7520         case MONO_TYPE_VOID:
7521                 /* special case string .ctor icall */
7522                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7523                         save_mode = SAVE_EAX;
7524                 else
7525                         save_mode = SAVE_NONE;
7526                 break;
7527         case MONO_TYPE_I8:
7528         case MONO_TYPE_U8:
7529                 save_mode = SAVE_EAX;
7530                 break;
7531         case MONO_TYPE_R4:
7532         case MONO_TYPE_R8:
7533                 save_mode = SAVE_XMM;
7534                 break;
7535         case MONO_TYPE_GENERICINST:
7536                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7537                         save_mode = SAVE_EAX;
7538                         break;
7539                 }
7540                 /* Fall through */
7541         case MONO_TYPE_VALUETYPE:
7542                 save_mode = SAVE_STRUCT;
7543                 break;
7544         default:
7545                 save_mode = SAVE_EAX;
7546                 break;
7547         }
7548
7549         /* Save the result and copy it into the proper argument register */
7550         switch (save_mode) {
7551         case SAVE_EAX:
7552                 amd64_push_reg (code, AMD64_RAX);
7553                 /* Align stack */
7554                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7555                 if (enable_arguments)
7556                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7557                 break;
7558         case SAVE_STRUCT:
7559                 /* FIXME: */
7560                 if (enable_arguments)
7561                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7562                 break;
7563         case SAVE_XMM:
7564                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7565                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7566                 /* Align stack */
7567                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7568                 /*
7569                  * The result is already in the proper argument register so no copying
7570                  * needed.
7571                  */
7572                 break;
7573         case SAVE_NONE:
7574                 break;
7575         default:
7576                 g_assert_not_reached ();
7577         }
7578
7579         /* Set %al since this is a varargs call */
7580         if (save_mode == SAVE_XMM)
7581                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7582         else
7583                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7584
7585         if (preserve_argument_registers) {
7586                 for (i = 0; i < PARAM_REGS; ++i)
7587                         amd64_push_reg (code, param_regs [i]);
7588         }
7589
7590         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7591         amd64_set_reg_template (code, AMD64_ARG_REG1);
7592         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7593
7594         if (preserve_argument_registers) {
7595                 for (i = PARAM_REGS - 1; i >= 0; --i)
7596                         amd64_pop_reg (code, param_regs [i]);
7597         }
7598
7599         /* Restore result */
7600         switch (save_mode) {
7601         case SAVE_EAX:
7602                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7603                 amd64_pop_reg (code, AMD64_RAX);
7604                 break;
7605         case SAVE_STRUCT:
7606                 /* FIXME: */
7607                 break;
7608         case SAVE_XMM:
7609                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7610                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7611                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7612                 break;
7613         case SAVE_NONE:
7614                 break;
7615         default:
7616                 g_assert_not_reached ();
7617         }
7618
7619         return code;
7620 }
7621
7622 void
7623 mono_arch_flush_icache (guint8 *code, gint size)
7624 {
7625         /* Not needed */
7626 }
7627
7628 void
7629 mono_arch_flush_register_windows (void)
7630 {
7631 }
7632
7633 gboolean
7634 mono_arch_is_inst_imm (gint64 imm)
7635 {
7636         return amd64_is_imm32 (imm);
7637 }
7638
7639 /*
7640  * Determine whenever the trap whose info is in SIGINFO is caused by
7641  * integer overflow.
7642  */
7643 gboolean
7644 mono_arch_is_int_overflow (void *sigctx, void *info)
7645 {
7646         MonoContext ctx;
7647         guint8* rip;
7648         int reg;
7649         gint64 value;
7650
7651         mono_sigctx_to_monoctx (sigctx, &ctx);
7652
7653         rip = (guint8*)ctx.rip;
7654
7655         if (IS_REX (rip [0])) {
7656                 reg = amd64_rex_b (rip [0]);
7657                 rip ++;
7658         }
7659         else
7660                 reg = 0;
7661
7662         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7663                 /* idiv REG */
7664                 reg += x86_modrm_rm (rip [1]);
7665
7666                 switch (reg) {
7667                 case AMD64_RAX:
7668                         value = ctx.rax;
7669                         break;
7670                 case AMD64_RBX:
7671                         value = ctx.rbx;
7672                         break;
7673                 case AMD64_RCX:
7674                         value = ctx.rcx;
7675                         break;
7676                 case AMD64_RDX:
7677                         value = ctx.rdx;
7678                         break;
7679                 case AMD64_RBP:
7680                         value = ctx.rbp;
7681                         break;
7682                 case AMD64_RSP:
7683                         value = ctx.rsp;
7684                         break;
7685                 case AMD64_RSI:
7686                         value = ctx.rsi;
7687                         break;
7688                 case AMD64_RDI:
7689                         value = ctx.rdi;
7690                         break;
7691                 case AMD64_R12:
7692                         value = ctx.r12;
7693                         break;
7694                 case AMD64_R13:
7695                         value = ctx.r13;
7696                         break;
7697                 case AMD64_R14:
7698                         value = ctx.r14;
7699                         break;
7700                 case AMD64_R15:
7701                         value = ctx.r15;
7702                         break;
7703                 default:
7704                         g_assert_not_reached ();
7705                         reg = -1;
7706                 }
7707
7708                 if (value == -1)
7709                         return TRUE;
7710         }
7711
7712         return FALSE;
7713 }
7714
7715 guint32
7716 mono_arch_get_patch_offset (guint8 *code)
7717 {
7718         return 3;
7719 }
7720
7721 /**
7722  * mono_breakpoint_clean_code:
7723  *
7724  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7725  * breakpoints in the original code, they are removed in the copy.
7726  *
7727  * Returns TRUE if no sw breakpoint was present.
7728  */
7729 gboolean
7730 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7731 {
7732         int i;
7733         gboolean can_write = TRUE;
7734         /*
7735          * If method_start is non-NULL we need to perform bound checks, since we access memory
7736          * at code - offset we could go before the start of the method and end up in a different
7737          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7738          * instead.
7739          */
7740         if (!method_start || code - offset >= method_start) {
7741                 memcpy (buf, code - offset, size);
7742         } else {
7743                 int diff = code - method_start;
7744                 memset (buf, 0, size);
7745                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7746         }
7747         code -= offset;
7748         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7749                 int idx = mono_breakpoint_info_index [i];
7750                 guint8 *ptr;
7751                 if (idx < 1)
7752                         continue;
7753                 ptr = mono_breakpoint_info [idx].address;
7754                 if (ptr >= code && ptr < code + size) {
7755                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7756                         can_write = FALSE;
7757                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7758                         buf [ptr - code] = saved_byte;
7759                 }
7760         }
7761         return can_write;
7762 }
7763
7764 #if defined(__native_client_codegen__)
7765 /* For membase calls, we want the base register. for Native Client,  */
7766 /* all indirect calls have the following sequence with the given sizes: */
7767 /* mov %eXX,%eXX                                [2-3]   */
7768 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7769 /* and $0xffffffffffffffe0,%r11d                [4]     */
7770 /* add %r15,%r11                                [3]     */
7771 /* callq *%r11                                  [3]     */
7772
7773
7774 /* Determine if code points to a NaCl call-through-register sequence, */
7775 /* (i.e., the last 3 instructions listed above) */
7776 int
7777 is_nacl_call_reg_sequence(guint8* code)
7778 {
7779         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7780                                "\x4d\x03\xdf"     /* add */
7781                                "\x41\xff\xd3";   /* call */
7782         return memcmp(code, sequence, 10) == 0;
7783 }
7784
7785 /* Determine if code points to the first opcode of the mov membase component */
7786 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7787 /* (there could be a REX prefix before the opcode but it is ignored) */
7788 static int
7789 is_nacl_indirect_call_membase_sequence(guint8* code)
7790 {
7791                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7792         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7793                /* and that src reg = dest reg */
7794                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7795                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7796                IS_REX(code[2]) &&
7797                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7798                /* and has dst of r11 and base of r15 */
7799                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7800                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7801 }
7802 #endif /* __native_client_codegen__ */
7803
7804 int
7805 mono_arch_get_this_arg_reg (guint8 *code)
7806 {
7807         return AMD64_ARG_REG1;
7808 }
7809
7810 gpointer
7811 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7812 {
7813         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7814 }
7815
7816 #define MAX_ARCH_DELEGATE_PARAMS 10
7817
7818 static gpointer
7819 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7820 {
7821         guint8 *code, *start;
7822         int i;
7823
7824         if (has_target) {
7825                 start = code = mono_global_codeman_reserve (64);
7826
7827                 /* Replace the this argument with the target */
7828                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7829                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7830                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7831
7832                 g_assert ((code - start) < 64);
7833         } else {
7834                 start = code = mono_global_codeman_reserve (64);
7835
7836                 if (param_count == 0) {
7837                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7838                 } else {
7839                         /* We have to shift the arguments left */
7840                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7841                         for (i = 0; i < param_count; ++i) {
7842 #ifdef HOST_WIN32
7843                                 if (i < 3)
7844                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7845                                 else
7846                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7847 #else
7848                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7849 #endif
7850                         }
7851
7852                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7853                 }
7854                 g_assert ((code - start) < 64);
7855         }
7856
7857         nacl_global_codeman_validate (&start, 64, &code);
7858
7859         if (code_len)
7860                 *code_len = code - start;
7861
7862         if (mono_jit_map_is_enabled ()) {
7863                 char *buff;
7864                 if (has_target)
7865                         buff = (char*)"delegate_invoke_has_target";
7866                 else
7867                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7868                 mono_emit_jit_tramp (start, code - start, buff);
7869                 if (!has_target)
7870                         g_free (buff);
7871         }
7872         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7873
7874         return start;
7875 }
7876
7877 /*
7878  * mono_arch_get_delegate_invoke_impls:
7879  *
7880  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7881  * trampolines.
7882  */
7883 GSList*
7884 mono_arch_get_delegate_invoke_impls (void)
7885 {
7886         GSList *res = NULL;
7887         guint8 *code;
7888         guint32 code_len;
7889         int i;
7890         char *tramp_name;
7891
7892         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7893         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7894
7895         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7896                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7897                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7898                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7899                 g_free (tramp_name);
7900         }
7901
7902         return res;
7903 }
7904
7905 gpointer
7906 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7907 {
7908         guint8 *code, *start;
7909         int i;
7910
7911         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7912                 return NULL;
7913
7914         /* FIXME: Support more cases */
7915         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7916                 return NULL;
7917
7918         if (has_target) {
7919                 static guint8* cached = NULL;
7920
7921                 if (cached)
7922                         return cached;
7923
7924                 if (mono_aot_only)
7925                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7926                 else
7927                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7928
7929                 mono_memory_barrier ();
7930
7931                 cached = start;
7932         } else {
7933                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7934                 for (i = 0; i < sig->param_count; ++i)
7935                         if (!mono_is_regsize_var (sig->params [i]))
7936                                 return NULL;
7937                 if (sig->param_count > 4)
7938                         return NULL;
7939
7940                 code = cache [sig->param_count];
7941                 if (code)
7942                         return code;
7943
7944                 if (mono_aot_only) {
7945                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7946                         start = mono_aot_get_trampoline (name);
7947                         g_free (name);
7948                 } else {
7949                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7950                 }
7951
7952                 mono_memory_barrier ();
7953
7954                 cache [sig->param_count] = start;
7955         }
7956
7957         return start;
7958 }
7959
7960 gpointer
7961 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7962 {
7963         guint8 *code, *start;
7964         int size = 20;
7965
7966         start = code = mono_global_codeman_reserve (size);
7967
7968         /* Replace the this argument with the target */
7969         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7970         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7971
7972         if (load_imt_reg) {
7973                 /* Load the IMT reg */
7974                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7975         }
7976
7977         /* Load the vtable */
7978         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7979         amd64_jump_membase (code, AMD64_RAX, offset);
7980         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7981
7982         return start;
7983 }
7984
7985 void
7986 mono_arch_finish_init (void)
7987 {
7988 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7989         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7990 #endif
7991 }
7992
7993 void
7994 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7995 {
7996 }
7997
7998 #if defined(__default_codegen__)
7999 #define CMP_SIZE (6 + 1)
8000 #define CMP_REG_REG_SIZE (4 + 1)
8001 #define BR_SMALL_SIZE 2
8002 #define BR_LARGE_SIZE 6
8003 #define MOV_REG_IMM_SIZE 10
8004 #define MOV_REG_IMM_32BIT_SIZE 6
8005 #define JUMP_REG_SIZE (2 + 1)
8006 #elif defined(__native_client_codegen__)
8007 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8008 #define CMP_SIZE ((6 + 1) * 2 - 1)
8009 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8010 #define BR_SMALL_SIZE (2 * 2 - 1)
8011 #define BR_LARGE_SIZE (6 * 2 - 1)
8012 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8013 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8014 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8015 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8016 /* Jump membase's size is large and unpredictable    */
8017 /* in native client, just pad it out a whole bundle. */
8018 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8019 #endif
8020
8021 static int
8022 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8023 {
8024         int i, distance = 0;
8025         for (i = start; i < target; ++i)
8026                 distance += imt_entries [i]->chunk_size;
8027         return distance;
8028 }
8029
8030 /*
8031  * LOCKING: called with the domain lock held
8032  */
8033 gpointer
8034 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8035         gpointer fail_tramp)
8036 {
8037         int i;
8038         int size = 0;
8039         guint8 *code, *start;
8040         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8041
8042         for (i = 0; i < count; ++i) {
8043                 MonoIMTCheckItem *item = imt_entries [i];
8044                 if (item->is_equals) {
8045                         if (item->check_target_idx) {
8046                                 if (!item->compare_done) {
8047                                         if (amd64_is_imm32 (item->key))
8048                                                 item->chunk_size += CMP_SIZE;
8049                                         else
8050                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8051                                 }
8052                                 if (item->has_target_code) {
8053                                         item->chunk_size += MOV_REG_IMM_SIZE;
8054                                 } else {
8055                                         if (vtable_is_32bit)
8056                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8057                                         else
8058                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8059 #ifdef __native_client_codegen__
8060                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8061 #endif
8062                                 }
8063                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8064                         } else {
8065                                 if (fail_tramp) {
8066                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8067                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8068                                 } else {
8069                                         if (vtable_is_32bit)
8070                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8071                                         else
8072                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8073                                         item->chunk_size += JUMP_REG_SIZE;
8074                                         /* with assert below:
8075                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8076                                          */
8077 #ifdef __native_client_codegen__
8078                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8079 #endif
8080                                 }
8081                         }
8082                 } else {
8083                         if (amd64_is_imm32 (item->key))
8084                                 item->chunk_size += CMP_SIZE;
8085                         else
8086                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8087                         item->chunk_size += BR_LARGE_SIZE;
8088                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8089                 }
8090                 size += item->chunk_size;
8091         }
8092 #if defined(__native_client__) && defined(__native_client_codegen__)
8093         /* In Native Client, we don't re-use thunks, allocate from the */
8094         /* normal code manager paths. */
8095         code = mono_domain_code_reserve (domain, size);
8096 #else
8097         if (fail_tramp)
8098                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8099         else
8100                 code = mono_domain_code_reserve (domain, size);
8101 #endif
8102         start = code;
8103         for (i = 0; i < count; ++i) {
8104                 MonoIMTCheckItem *item = imt_entries [i];
8105                 item->code_target = code;
8106                 if (item->is_equals) {
8107                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8108
8109                         if (item->check_target_idx || fail_case) {
8110                                 if (!item->compare_done || fail_case) {
8111                                         if (amd64_is_imm32 (item->key))
8112                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8113                                         else {
8114                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8115                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8116                                         }
8117                                 }
8118                                 item->jmp_code = code;
8119                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8120                                 if (item->has_target_code) {
8121                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8122                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8123                                 } else {
8124                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8125                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8126                                 }
8127
8128                                 if (fail_case) {
8129                                         amd64_patch (item->jmp_code, code);
8130                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8131                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8132                                         item->jmp_code = NULL;
8133                                 }
8134                         } else {
8135                                 /* enable the commented code to assert on wrong method */
8136 #if 0
8137                                 if (amd64_is_imm32 (item->key))
8138                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8139                                 else {
8140                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8141                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8142                                 }
8143                                 item->jmp_code = code;
8144                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8145                                 /* See the comment below about R10 */
8146                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8147                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8148                                 amd64_patch (item->jmp_code, code);
8149                                 amd64_breakpoint (code);
8150                                 item->jmp_code = NULL;
8151 #else
8152                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8153                                    needs to be preserved.  R10 needs
8154                                    to be preserved for calls which
8155                                    require a runtime generic context,
8156                                    but interface calls don't. */
8157                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8158                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8159 #endif
8160                         }
8161                 } else {
8162                         if (amd64_is_imm32 (item->key))
8163                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8164                         else {
8165                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8166                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8167                         }
8168                         item->jmp_code = code;
8169                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8170                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8171                         else
8172                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8173                 }
8174                 g_assert (code - item->code_target <= item->chunk_size);
8175         }
8176         /* patch the branches to get to the target items */
8177         for (i = 0; i < count; ++i) {
8178                 MonoIMTCheckItem *item = imt_entries [i];
8179                 if (item->jmp_code) {
8180                         if (item->check_target_idx) {
8181                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8182                         }
8183                 }
8184         }
8185
8186         if (!fail_tramp)
8187                 mono_stats.imt_thunks_size += code - start;
8188         g_assert (code - start <= size);
8189
8190         nacl_domain_code_validate(domain, &start, size, &code);
8191         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8192
8193         return start;
8194 }
8195
8196 MonoMethod*
8197 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8198 {
8199         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8200 }
8201
8202 MonoVTable*
8203 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8204 {
8205         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8206 }
8207
8208 GSList*
8209 mono_arch_get_cie_program (void)
8210 {
8211         GSList *l = NULL;
8212
8213         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8214         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8215
8216         return l;
8217 }
8218
8219 #ifndef DISABLE_JIT
8220
8221 MonoInst*
8222 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8223 {
8224         MonoInst *ins = NULL;
8225         int opcode = 0;
8226
8227         if (cmethod->klass == mono_defaults.math_class) {
8228                 if (strcmp (cmethod->name, "Sin") == 0) {
8229                         opcode = OP_SIN;
8230                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8231                         opcode = OP_COS;
8232                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8233                         opcode = OP_SQRT;
8234                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8235                         opcode = OP_ABS;
8236                 }
8237
8238                 if (opcode && fsig->param_count == 1) {
8239                         MONO_INST_NEW (cfg, ins, opcode);
8240                         ins->type = STACK_R8;
8241                         ins->dreg = mono_alloc_freg (cfg);
8242                         ins->sreg1 = args [0]->dreg;
8243                         MONO_ADD_INS (cfg->cbb, ins);
8244                 }
8245
8246                 opcode = 0;
8247                 if (cfg->opt & MONO_OPT_CMOV) {
8248                         if (strcmp (cmethod->name, "Min") == 0) {
8249                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8250                                         opcode = OP_IMIN;
8251                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8252                                         opcode = OP_IMIN_UN;
8253                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8254                                         opcode = OP_LMIN;
8255                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8256                                         opcode = OP_LMIN_UN;
8257                         } else if (strcmp (cmethod->name, "Max") == 0) {
8258                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8259                                         opcode = OP_IMAX;
8260                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8261                                         opcode = OP_IMAX_UN;
8262                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8263                                         opcode = OP_LMAX;
8264                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8265                                         opcode = OP_LMAX_UN;
8266                         }
8267                 }
8268
8269                 if (opcode && fsig->param_count == 2) {
8270                         MONO_INST_NEW (cfg, ins, opcode);
8271                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8272                         ins->dreg = mono_alloc_ireg (cfg);
8273                         ins->sreg1 = args [0]->dreg;
8274                         ins->sreg2 = args [1]->dreg;
8275                         MONO_ADD_INS (cfg->cbb, ins);
8276                 }
8277
8278 #if 0
8279                 /* OP_FREM is not IEEE compatible */
8280                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8281                         MONO_INST_NEW (cfg, ins, OP_FREM);
8282                         ins->inst_i0 = args [0];
8283                         ins->inst_i1 = args [1];
8284                 }
8285 #endif
8286         }
8287
8288         return ins;
8289 }
8290 #endif
8291
8292 gboolean
8293 mono_arch_print_tree (MonoInst *tree, int arity)
8294 {
8295         return 0;
8296 }
8297
8298 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8299
8300 mgreg_t
8301 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8302 {
8303         switch (reg) {
8304         case AMD64_RCX: return ctx->rcx;
8305         case AMD64_RDX: return ctx->rdx;
8306         case AMD64_RBX: return ctx->rbx;
8307         case AMD64_RBP: return ctx->rbp;
8308         case AMD64_RSP: return ctx->rsp;
8309         default:
8310                 return _CTX_REG (ctx, rax, reg);
8311         }
8312 }
8313
8314 void
8315 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8316 {
8317         switch (reg) {
8318         case AMD64_RCX:
8319                 ctx->rcx = val;
8320                 break;
8321         case AMD64_RDX:
8322                 ctx->rdx = val;
8323                 break;
8324         case AMD64_RBX:
8325                 ctx->rbx = val;
8326                 break;
8327         case AMD64_RBP:
8328                 ctx->rbp = val;
8329                 break;
8330         case AMD64_RSP:
8331                 ctx->rsp = val;
8332                 break;
8333         default:
8334                 _CTX_REG (ctx, rax, reg) = val;
8335         }
8336 }
8337
8338 gpointer
8339 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8340 {
8341         gpointer *sp, old_value;
8342         char *bp;
8343
8344         /*Load the spvar*/
8345         bp = MONO_CONTEXT_GET_BP (ctx);
8346         sp = *(gpointer*)(bp + clause->exvar_offset);
8347
8348         old_value = *sp;
8349         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8350                 return old_value;
8351
8352         *sp = new_value;
8353
8354         return old_value;
8355 }
8356
8357 /*
8358  * mono_arch_emit_load_aotconst:
8359  *
8360  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8361  * TARGET from the mscorlib GOT in full-aot code.
8362  * On AMD64, the result is placed into R11.
8363  */
8364 guint8*
8365 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8366 {
8367         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8368         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8369
8370         return code;
8371 }
8372
8373 /*
8374  * mono_arch_get_trampolines:
8375  *
8376  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8377  * for AOT.
8378  */
8379 GSList *
8380 mono_arch_get_trampolines (gboolean aot)
8381 {
8382         return mono_amd64_get_exception_trampolines (aot);
8383 }
8384
8385 /* Soft Debug support */
8386 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8387
8388 /*
8389  * mono_arch_set_breakpoint:
8390  *
8391  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8392  * The location should contain code emitted by OP_SEQ_POINT.
8393  */
8394 void
8395 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8396 {
8397         guint8 *code = ip;
8398         guint8 *orig_code = code;
8399
8400         if (ji->from_aot) {
8401                 guint32 native_offset = ip - (guint8*)ji->code_start;
8402                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8403
8404                 g_assert (info->bp_addrs [native_offset] == 0);
8405                 info->bp_addrs [native_offset] = bp_trigger_page;
8406         } else {
8407                 /*
8408                  * In production, we will use int3 (has to fix the size in the md
8409                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8410                  * instead.
8411                  */
8412                 g_assert (code [0] == 0x90);
8413                 if (breakpoint_size == 8) {
8414                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8415                 } else {
8416                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8417                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8418                 }
8419
8420                 g_assert (code - orig_code == breakpoint_size);
8421         }
8422 }
8423
8424 /*
8425  * mono_arch_clear_breakpoint:
8426  *
8427  *   Clear the breakpoint at IP.
8428  */
8429 void
8430 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8431 {
8432         guint8 *code = ip;
8433         int i;
8434
8435         if (ji->from_aot) {
8436                 guint32 native_offset = ip - (guint8*)ji->code_start;
8437                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8438
8439                 g_assert (info->bp_addrs [native_offset] == 0);
8440                 info->bp_addrs [native_offset] = info;
8441         } else {
8442                 for (i = 0; i < breakpoint_size; ++i)
8443                         x86_nop (code);
8444         }
8445 }
8446
8447 gboolean
8448 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8449 {
8450 #ifdef HOST_WIN32
8451         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8452         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8453                 return TRUE;
8454         else
8455                 return FALSE;
8456 #else
8457         siginfo_t* sinfo = (siginfo_t*) info;
8458         /* Sometimes the address is off by 4 */
8459         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8460                 return TRUE;
8461         else
8462                 return FALSE;
8463 #endif
8464 }
8465
8466 /*
8467  * mono_arch_skip_breakpoint:
8468  *
8469  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8470  * we resume, the instruction is not executed again.
8471  */
8472 void
8473 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8474 {
8475         if (ji->from_aot) {
8476                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8477                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8478         } else {
8479                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8480         }
8481 }
8482
8483 /*
8484  * mono_arch_start_single_stepping:
8485  *
8486  *   Start single stepping.
8487  */
8488 void
8489 mono_arch_start_single_stepping (void)
8490 {
8491         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8492 }
8493
8494 /*
8495  * mono_arch_stop_single_stepping:
8496  *
8497  *   Stop single stepping.
8498  */
8499 void
8500 mono_arch_stop_single_stepping (void)
8501 {
8502         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8503 }
8504
8505 /*
8506  * mono_arch_is_single_step_event:
8507  *
8508  *   Return whenever the machine state in SIGCTX corresponds to a single
8509  * step event.
8510  */
8511 gboolean
8512 mono_arch_is_single_step_event (void *info, void *sigctx)
8513 {
8514 #ifdef HOST_WIN32
8515         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8516         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8517                 return TRUE;
8518         else
8519                 return FALSE;
8520 #else
8521         siginfo_t* sinfo = (siginfo_t*) info;
8522         /* Sometimes the address is off by 4 */
8523         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8524                 return TRUE;
8525         else
8526                 return FALSE;
8527 #endif
8528 }
8529
8530 /*
8531  * mono_arch_skip_single_step:
8532  *
8533  *   Modify CTX so the ip is placed after the single step trigger instruction,
8534  * we resume, the instruction is not executed again.
8535  */
8536 void
8537 mono_arch_skip_single_step (MonoContext *ctx)
8538 {
8539         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8540 }
8541
8542 /*
8543  * mono_arch_create_seq_point_info:
8544  *
8545  *   Return a pointer to a data structure which is used by the sequence
8546  * point implementation in AOTed code.
8547  */
8548 gpointer
8549 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8550 {
8551         SeqPointInfo *info;
8552         MonoJitInfo *ji;
8553         int i;
8554
8555         // FIXME: Add a free function
8556
8557         mono_domain_lock (domain);
8558         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8559                                                                 code);
8560         mono_domain_unlock (domain);
8561
8562         if (!info) {
8563                 ji = mono_jit_info_table_find (domain, (char*)code);
8564                 g_assert (ji);
8565
8566                 // FIXME: Optimize the size
8567                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8568
8569                 info->ss_trigger_page = ss_trigger_page;
8570                 info->bp_trigger_page = bp_trigger_page;
8571                 /* Initialize to a valid address */
8572                 for (i = 0; i < ji->code_size; ++i)
8573                         info->bp_addrs [i] = info;
8574
8575                 mono_domain_lock (domain);
8576                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8577                                                          code, info);
8578                 mono_domain_unlock (domain);
8579         }
8580
8581         return info;
8582 }
8583
8584 void
8585 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8586 {
8587         ext->lmf.previous_lmf = prev_lmf;
8588         /* Mark that this is a MonoLMFExt */
8589         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8590         ext->lmf.rsp = (gssize)ext;
8591 }
8592
8593 #endif
8594
8595 gboolean
8596 mono_arch_opcode_supported (int opcode)
8597 {
8598         switch (opcode) {
8599         case OP_ATOMIC_ADD_I4:
8600         case OP_ATOMIC_ADD_I8:
8601         case OP_ATOMIC_EXCHANGE_I4:
8602         case OP_ATOMIC_EXCHANGE_I8:
8603         case OP_ATOMIC_CAS_I4:
8604         case OP_ATOMIC_CAS_I8:
8605         case OP_ATOMIC_LOAD_I1:
8606         case OP_ATOMIC_LOAD_I2:
8607         case OP_ATOMIC_LOAD_I4:
8608         case OP_ATOMIC_LOAD_I8:
8609         case OP_ATOMIC_LOAD_U1:
8610         case OP_ATOMIC_LOAD_U2:
8611         case OP_ATOMIC_LOAD_U4:
8612         case OP_ATOMIC_LOAD_U8:
8613         case OP_ATOMIC_LOAD_R4:
8614         case OP_ATOMIC_LOAD_R8:
8615         case OP_ATOMIC_STORE_I1:
8616         case OP_ATOMIC_STORE_I2:
8617         case OP_ATOMIC_STORE_I4:
8618         case OP_ATOMIC_STORE_I8:
8619         case OP_ATOMIC_STORE_U1:
8620         case OP_ATOMIC_STORE_U2:
8621         case OP_ATOMIC_STORE_U4:
8622         case OP_ATOMIC_STORE_U8:
8623         case OP_ATOMIC_STORE_R4:
8624         case OP_ATOMIC_STORE_R8:
8625                 return TRUE;
8626         default:
8627                 return FALSE;
8628         }
8629 }