mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16
  17 #include <mono/metadata/appdomain.h>
  18 #include <mono/metadata/debug-helpers.h>
  19 #include <mono/metadata/threads.h>
  20 #include <mono/metadata/profiler-private.h>
  21 #include <mono/metadata/mono-debug.h>
  22 #include <mono/utils/mono-math.h>
  23
  24 #include "trace.h"
  25 #include "mini-amd64.h"
  26 #include "inssel.h"
  27 #include "cpu-amd64.h"
  28
  29 static gint lmf_tls_offset = -1;
  30 static gint appdomain_tls_offset = -1;
  31 static gint thread_tls_offset = -1;
  32
  33 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  34
  35 const char * const amd64_desc [OP_LAST];
  36 static const char*const * ins_spec = amd64_desc;
  37
  38 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  39
  40 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  41
  42 #ifdef PLATFORM_WIN32
  43 /* Under windows, the default pinvoke calling convention is stdcall */
  44 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  45 #else
  46 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  47 #endif
  48
  49 #define ARGS_OFFSET 16
  50 #define GP_SCRATCH_REG AMD64_R11
  51
  52 /*
  53  * AMD64 register usage:
  54  * - callee saved registers are used for global register allocation
  55  * - %r11 is used for materializing 64 bit constants in opcodes
  56  * - the rest is used for local allocation
  57  */
  58
  59 /*
  60  * Floating point comparison results:
  61  *                  ZF PF CF
  62  * A > B            0  0  0
  63  * A < B            0  0  1
  64  * A = B            1  0  0
  65  * A > B            0  0  0
  66  * UNORDERED        1  1  1
  67  */
  68
  69 #define NOT_IMPLEMENTED g_assert_not_reached ()
  70
  71 const char*
  72 mono_arch_regname (int reg) {
  73         switch (reg) {
  74         case AMD64_RAX: return "%rax";
  75         case AMD64_RBX: return "%rbx";
  76         case AMD64_RCX: return "%rcx";
  77         case AMD64_RDX: return "%rdx";
  78         case AMD64_RSP: return "%rsp";
  79         case AMD64_RBP: return "%rbp";
  80         case AMD64_RDI: return "%rdi";
  81         case AMD64_RSI: return "%rsi";
  82         case AMD64_R8: return "%r8";
  83         case AMD64_R9: return "%r9";
  84         case AMD64_R10: return "%r10";
  85         case AMD64_R11: return "%r11";
  86         case AMD64_R12: return "%r12";
  87         case AMD64_R13: return "%r13";
  88         case AMD64_R14: return "%r14";
  89         case AMD64_R15: return "%r15";
  90         }
  91         return "unknown";
  92 }
  93
  94 static const char * xmmregs [] = {
  95         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
  96         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
  97 };
  98
  99 const char*
 100 mono_arch_fregname (int reg)
 101 {
 102         if (reg < AMD64_XMM_NREG)
 103                 return xmmregs [reg];
 104         else
 105                 return "unknown";
 106 }
 107
 108 G_GNUC_UNUSED static void
 109 break_count (void)
 110 {
 111 }
 112
 113 G_GNUC_UNUSED static gboolean
 114 debug_count (void)
 115 {
 116         static int count = 0;
 117         count ++;
 118
 119         if (!getenv ("COUNT"))
 120                 return TRUE;
 121
 122         if (count == atoi (getenv ("COUNT"))) {
 123                 break_count ();
 124         }
 125
 126         if (count > atoi (getenv ("COUNT"))) {
 127                 return FALSE;
 128         }
 129
 130         return TRUE;
 131 }
 132
 133 static gboolean
 134 debug_omit_fp (void)
 135 {
 136 #if 0
 137         return debug_count ();
 138 #else
 139         return TRUE;
 140 #endif
 141 }
 142
 143 static inline void
 144 amd64_patch (unsigned char* code, gpointer target)
 145 {
 146         /* Skip REX */
 147         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 148                 code += 1;
 149
 150         if ((code [0] & 0xf8) == 0xb8) {
 151                 /* amd64_set_reg_template */
 152                 *(guint64*)(code + 1) = (guint64)target;
 153         }
 154         else if (code [0] == 0x8b) {
 155                 /* mov 0(%rip), %dreg */
 156                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 157         }
 158         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 159                 /* call *<OFFSET>(%rip) */
 160                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 161         }
 162         else if ((code [0] == 0xe8)) {
 163                 /* call <DISP> */
 164                 gint64 disp = (guint8*)target - (guint8*)code;
 165                 g_assert (amd64_is_imm32 (disp));
 166                 x86_patch (code, (unsigned char*)target);
 167         }
 168         else
 169                 x86_patch (code, (unsigned char*)target);
 170 }
 171
 172 typedef enum {
 173         ArgInIReg,
 174         ArgInFloatSSEReg,
 175         ArgInDoubleSSEReg,
 176         ArgOnStack,
 177         ArgValuetypeInReg,
 178         ArgNone /* only in pair_storage */
 179 } ArgStorage;
 180
 181 typedef struct {
 182         gint16 offset;
 183         gint8  reg;
 184         ArgStorage storage;
 185
 186         /* Only if storage == ArgValuetypeInReg */
 187         ArgStorage pair_storage [2];
 188         gint8 pair_regs [2];
 189 } ArgInfo;
 190
 191 typedef struct {
 192         int nargs;
 193         guint32 stack_usage;
 194         guint32 reg_usage;
 195         guint32 freg_usage;
 196         gboolean need_stack_align;
 197         ArgInfo ret;
 198         ArgInfo sig_cookie;
 199         ArgInfo args [1];
 200 } CallInfo;
 201
 202 #define DEBUG(a) if (cfg->verbose_level > 1) a
 203
 204 #define NEW_ICONST(cfg,dest,val) do {   \
 205                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 206                 (dest)->opcode = OP_ICONST;     \
 207                 (dest)->inst_c0 = (val);        \
 208                 (dest)->type = STACK_I4;        \
 209         } while (0)
 210
 211 #define PARAM_REGS 6
 212
 213 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 214
 215 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 216
 217 static void inline
 218 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 219 {
 220     ainfo->offset = *stack_size;
 221
 222     if (*gr >= PARAM_REGS) {
 223                 ainfo->storage = ArgOnStack;
 224                 (*stack_size) += sizeof (gpointer);
 225     }
 226     else {
 227                 ainfo->storage = ArgInIReg;
 228                 ainfo->reg = param_regs [*gr];
 229                 (*gr) ++;
 230     }
 231 }
 232
 233 #define FLOAT_PARAM_REGS 8
 234
 235 static void inline
 236 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 237 {
 238     ainfo->offset = *stack_size;
 239
 240     if (*gr >= FLOAT_PARAM_REGS) {
 241                 ainfo->storage = ArgOnStack;
 242                 (*stack_size) += sizeof (gpointer);
 243     }
 244     else {
 245                 /* A double register */
 246                 if (is_double)
 247                         ainfo->storage = ArgInDoubleSSEReg;
 248                 else
 249                         ainfo->storage = ArgInFloatSSEReg;
 250                 ainfo->reg = *gr;
 251                 (*gr) += 1;
 252     }
 253 }
 254
 255 typedef enum ArgumentClass {
 256         ARG_CLASS_NO_CLASS,
 257         ARG_CLASS_MEMORY,
 258         ARG_CLASS_INTEGER,
 259         ARG_CLASS_SSE
 260 } ArgumentClass;
 261
 262 static ArgumentClass
 263 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 264 {
 265         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 266         MonoType *ptype;
 267
 268         ptype = mono_type_get_underlying_type (type);
 269         switch (ptype->type) {
 270         case MONO_TYPE_BOOLEAN:
 271         case MONO_TYPE_CHAR:
 272         case MONO_TYPE_I1:
 273         case MONO_TYPE_U1:
 274         case MONO_TYPE_I2:
 275         case MONO_TYPE_U2:
 276         case MONO_TYPE_I4:
 277         case MONO_TYPE_U4:
 278         case MONO_TYPE_I:
 279         case MONO_TYPE_U:
 280         case MONO_TYPE_STRING:
 281         case MONO_TYPE_OBJECT:
 282         case MONO_TYPE_CLASS:
 283         case MONO_TYPE_SZARRAY:
 284         case MONO_TYPE_PTR:
 285         case MONO_TYPE_FNPTR:
 286         case MONO_TYPE_ARRAY:
 287         case MONO_TYPE_I8:
 288         case MONO_TYPE_U8:
 289                 class2 = ARG_CLASS_INTEGER;
 290                 break;
 291         case MONO_TYPE_R4:
 292         case MONO_TYPE_R8:
 293                 class2 = ARG_CLASS_SSE;
 294                 break;
 295
 296         case MONO_TYPE_TYPEDBYREF:
 297                 g_assert_not_reached ();
 298
 299         case MONO_TYPE_VALUETYPE: {
 300                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 301                 int i;
 302
 303                 for (i = 0; i < info->num_fields; ++i) {
 304                         class2 = class1;
 305                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 306                 }
 307                 break;
 308         }
 309         default:
 310                 g_assert_not_reached ();
 311         }
 312
 313         /* Merge */
 314         if (class1 == class2)
 315                 ;
 316         else if (class1 == ARG_CLASS_NO_CLASS)
 317                 class1 = class2;
 318         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 319                 class1 = ARG_CLASS_MEMORY;
 320         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 321                 class1 = ARG_CLASS_INTEGER;
 322         else
 323                 class1 = ARG_CLASS_SSE;
 324
 325         return class1;
 326 }
 327
 328 static void
 329 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 330                gboolean is_return,
 331                guint32 *gr, guint32 *fr, guint32 *stack_size)
 332 {
 333         guint32 size, quad, nquads, i;
 334         ArgumentClass args [2];
 335         MonoMarshalType *info;
 336         MonoClass *klass;
 337
 338         klass = mono_class_from_mono_type (type);
 339         if (sig->pinvoke)
 340                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 341         else
 342                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 343
 344         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 345                 /* Allways pass in memory */
 346                 ainfo->offset = *stack_size;
 347                 *stack_size += ALIGN_TO (size, 8);
 348                 ainfo->storage = ArgOnStack;
 349
 350                 return;
 351         }
 352
 353         /* FIXME: Handle structs smaller than 8 bytes */
 354         //if ((size % 8) != 0)
 355         //      NOT_IMPLEMENTED;
 356
 357         if (size > 8)
 358                 nquads = 2;
 359         else
 360                 nquads = 1;
 361
 362         /*
 363          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 364          * The X87 and SSEUP stuff is left out since there are no such types in
 365          * the CLR.
 366          */
 367         info = mono_marshal_load_type_info (klass);
 368         g_assert (info);
 369         if (info->native_size > 16) {
 370                 ainfo->offset = *stack_size;
 371                 *stack_size += ALIGN_TO (info->native_size, 8);
 372                 ainfo->storage = ArgOnStack;
 373
 374                 return;
 375         }
 376
 377         for (quad = 0; quad < nquads; ++quad) {
 378                 int size, align;
 379                 ArgumentClass class1;
 380
 381                 class1 = ARG_CLASS_NO_CLASS;
 382                 for (i = 0; i < info->num_fields; ++i) {
 383                         size = mono_marshal_type_size (info->fields [i].field->type,
 384                                                                                    info->fields [i].mspec,
 385                                                                                    &align, TRUE, klass->unicode);
 386                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 387                                 /* Unaligned field */
 388                                 NOT_IMPLEMENTED;
 389                         }
 390
 391                         /* Skip fields in other quad */
 392                         if ((quad == 0) && (info->fields [i].offset >= 8))
 393                                 continue;
 394                         if ((quad == 1) && (info->fields [i].offset < 8))
 395                                 continue;
 396
 397                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 398                 }
 399                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 400                 args [quad] = class1;
 401         }
 402
 403         /* Post merger cleanup */
 404         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 405                 args [0] = args [1] = ARG_CLASS_MEMORY;
 406
 407         /* Allocate registers */
 408         {
 409                 int orig_gr = *gr;
 410                 int orig_fr = *fr;
 411
 412                 ainfo->storage = ArgValuetypeInReg;
 413                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 414                 for (quad = 0; quad < nquads; ++quad) {
 415                         switch (args [quad]) {
 416                         case ARG_CLASS_INTEGER:
 417                                 if (*gr >= PARAM_REGS)
 418                                         args [quad] = ARG_CLASS_MEMORY;
 419                                 else {
 420                                         ainfo->pair_storage [quad] = ArgInIReg;
 421                                         if (is_return)
 422                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 423                                         else
 424                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 425                                         (*gr) ++;
 426                                 }
 427                                 break;
 428                         case ARG_CLASS_SSE:
 429                                 if (*fr >= FLOAT_PARAM_REGS)
 430                                         args [quad] = ARG_CLASS_MEMORY;
 431                                 else {
 432                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 433                                         ainfo->pair_regs [quad] = *fr;
 434                                         (*fr) ++;
 435                                 }
 436                                 break;
 437                         case ARG_CLASS_MEMORY:
 438                                 break;
 439                         default:
 440                                 g_assert_not_reached ();
 441                         }
 442                 }
 443
 444                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 445                         /* Revert possible register assignments */
 446                         *gr = orig_gr;
 447                         *fr = orig_fr;
 448
 449                         ainfo->offset = *stack_size;
 450                         *stack_size += ALIGN_TO (info->native_size, 8);
 451                         ainfo->storage = ArgOnStack;
 452                 }
 453         }
 454 }
 455
 456 /*
 457  * get_call_info:
 458  *
 459  *  Obtain information about a call according to the calling convention.
 460  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 461  * Draft Version 0.23" document for more information.
 462  */
 463 static CallInfo*
 464 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 465 {
 466         guint32 i, gr, fr;
 467         MonoType *ret_type;
 468         int n = sig->hasthis + sig->param_count;
 469         guint32 stack_size = 0;
 470         CallInfo *cinfo;
 471
 472         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 473
 474         gr = 0;
 475         fr = 0;
 476
 477         /* return value */
 478         {
 479                 ret_type = mono_type_get_underlying_type (sig->ret);
 480                 switch (ret_type->type) {
 481                 case MONO_TYPE_BOOLEAN:
 482                 case MONO_TYPE_I1:
 483                 case MONO_TYPE_U1:
 484                 case MONO_TYPE_I2:
 485                 case MONO_TYPE_U2:
 486                 case MONO_TYPE_CHAR:
 487                 case MONO_TYPE_I4:
 488                 case MONO_TYPE_U4:
 489                 case MONO_TYPE_I:
 490                 case MONO_TYPE_U:
 491                 case MONO_TYPE_PTR:
 492                 case MONO_TYPE_FNPTR:
 493                 case MONO_TYPE_CLASS:
 494                 case MONO_TYPE_OBJECT:
 495                 case MONO_TYPE_SZARRAY:
 496                 case MONO_TYPE_ARRAY:
 497                 case MONO_TYPE_STRING:
 498                         cinfo->ret.storage = ArgInIReg;
 499                         cinfo->ret.reg = AMD64_RAX;
 500                         break;
 501                 case MONO_TYPE_U8:
 502                 case MONO_TYPE_I8:
 503                         cinfo->ret.storage = ArgInIReg;
 504                         cinfo->ret.reg = AMD64_RAX;
 505                         break;
 506                 case MONO_TYPE_R4:
 507                         cinfo->ret.storage = ArgInFloatSSEReg;
 508                         cinfo->ret.reg = AMD64_XMM0;
 509                         break;
 510                 case MONO_TYPE_R8:
 511                         cinfo->ret.storage = ArgInDoubleSSEReg;
 512                         cinfo->ret.reg = AMD64_XMM0;
 513                         break;
 514                 case MONO_TYPE_VALUETYPE: {
 515                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 516
 517                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 518                         if (cinfo->ret.storage == ArgOnStack)
 519                                 /* The caller passes the address where the value is stored */
 520                                 add_general (&gr, &stack_size, &cinfo->ret);
 521                         break;
 522                 }
 523                 case MONO_TYPE_TYPEDBYREF:
 524                         /* Same as a valuetype with size 24 */
 525                         add_general (&gr, &stack_size, &cinfo->ret);
 526                         ;
 527                         break;
 528                 case MONO_TYPE_VOID:
 529                         break;
 530                 default:
 531                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 532                 }
 533         }
 534
 535         /* this */
 536         if (sig->hasthis)
 537                 add_general (&gr, &stack_size, cinfo->args + 0);
 538
 539         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 540                 gr = PARAM_REGS;
 541                 fr = FLOAT_PARAM_REGS;
 542
 543                 /* Emit the signature cookie just before the implicit arguments */
 544                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 545         }
 546
 547         for (i = 0; i < sig->param_count; ++i) {
 548                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 549                 MonoType *ptype;
 550
 551                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 552                         /* We allways pass the sig cookie on the stack for simplicity */
 553                         /*
 554                          * Prevent implicit arguments + the sig cookie from being passed
 555                          * in registers.
 556                          */
 557                         gr = PARAM_REGS;
 558                         fr = FLOAT_PARAM_REGS;
 559
 560                         /* Emit the signature cookie just before the implicit arguments */
 561                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 562                 }
 563
 564                 if (sig->params [i]->byref) {
 565                         add_general (&gr, &stack_size, ainfo);
 566                         continue;
 567                 }
 568                 ptype = mono_type_get_underlying_type (sig->params [i]);
 569                 switch (ptype->type) {
 570                 case MONO_TYPE_BOOLEAN:
 571                 case MONO_TYPE_I1:
 572                 case MONO_TYPE_U1:
 573                         add_general (&gr, &stack_size, ainfo);
 574                         break;
 575                 case MONO_TYPE_I2:
 576                 case MONO_TYPE_U2:
 577                 case MONO_TYPE_CHAR:
 578                         add_general (&gr, &stack_size, ainfo);
 579                         break;
 580                 case MONO_TYPE_I4:
 581                 case MONO_TYPE_U4:
 582                         add_general (&gr, &stack_size, ainfo);
 583                         break;
 584                 case MONO_TYPE_I:
 585                 case MONO_TYPE_U:
 586                 case MONO_TYPE_PTR:
 587                 case MONO_TYPE_FNPTR:
 588                 case MONO_TYPE_CLASS:
 589                 case MONO_TYPE_OBJECT:
 590                 case MONO_TYPE_STRING:
 591                 case MONO_TYPE_SZARRAY:
 592                 case MONO_TYPE_ARRAY:
 593                         add_general (&gr, &stack_size, ainfo);
 594                         break;
 595                 case MONO_TYPE_VALUETYPE:
 596                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 597                         break;
 598                 case MONO_TYPE_TYPEDBYREF:
 599                         stack_size += sizeof (MonoTypedRef);
 600                         ainfo->storage = ArgOnStack;
 601                         break;
 602                 case MONO_TYPE_U8:
 603                 case MONO_TYPE_I8:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_R4:
 607                         add_float (&fr, &stack_size, ainfo, FALSE);
 608                         break;
 609                 case MONO_TYPE_R8:
 610                         add_float (&fr, &stack_size, ainfo, TRUE);
 611                         break;
 612                 default:
 613                         g_assert_not_reached ();
 614                 }
 615         }
 616
 617         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 618                 gr = PARAM_REGS;
 619                 fr = FLOAT_PARAM_REGS;
 620
 621                 /* Emit the signature cookie just before the implicit arguments */
 622                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 623         }
 624
 625         if (stack_size & 0x8) {
 626                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 627                 cinfo->need_stack_align = TRUE;
 628                 stack_size += 8;
 629         }
 630
 631         cinfo->stack_usage = stack_size;
 632         cinfo->reg_usage = gr;
 633         cinfo->freg_usage = fr;
 634         return cinfo;
 635 }
 636
 637 /*
 638  * mono_arch_get_argument_info:
 639  * @csig:  a method signature
 640  * @param_count: the number of parameters to consider
 641  * @arg_info: an array to store the result infos
 642  *
 643  * Gathers information on parameters such as size, alignment and
 644  * padding. arg_info should be large enought to hold param_count + 1 entries.
 645  *
 646  * Returns the size of the argument area on the stack.
 647  */
 648 int
 649 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 650 {
 651         int k;
 652         CallInfo *cinfo = get_call_info (csig, FALSE);
 653         guint32 args_size = cinfo->stack_usage;
 654
 655         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 656         if (csig->hasthis) {
 657                 arg_info [0].offset = 0;
 658         }
 659
 660         for (k = 0; k < param_count; k++) {
 661                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 662                 /* FIXME: */
 663                 arg_info [k + 1].size = 0;
 664         }
 665
 666         g_free (cinfo);
 667
 668         return args_size;
 669 }
 670
 671 static int
 672 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 673 {
 674         return 0;
 675 }
 676
 677 /*
 678  * Initialize the cpu to execute managed code.
 679  */
 680 void
 681 mono_arch_cpu_init (void)
 682 {
 683         guint16 fpcw;
 684
 685         /* spec compliance requires running with double precision */
 686         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 687         fpcw &= ~X86_FPCW_PRECC_MASK;
 688         fpcw |= X86_FPCW_PREC_DOUBLE;
 689         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 690         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 691 }
 692
 693 /*
 694  * This function returns the optimizations supported on this cpu.
 695  */
 696 guint32
 697 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 698 {
 699         int eax, ebx, ecx, edx;
 700         guint32 opts = 0;
 701
 702         /* FIXME: AMD64 */
 703
 704         *exclude_mask = 0;
 705         /* Feature Flags function, flags returned in EDX. */
 706         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 707                 if (edx & (1 << 15)) {
 708                         opts |= MONO_OPT_CMOV;
 709                         if (edx & 1)
 710                                 opts |= MONO_OPT_FCMOV;
 711                         else
 712                                 *exclude_mask |= MONO_OPT_FCMOV;
 713                 } else
 714                         *exclude_mask |= MONO_OPT_CMOV;
 715         }
 716         return opts;
 717 }
 718
 719 gboolean
 720 mono_amd64_is_sse2 (void)
 721 {
 722         return use_sse2;
 723 }
 724
 725 static gboolean
 726 is_regsize_var (MonoType *t) {
 727         if (t->byref)
 728                 return TRUE;
 729         t = mono_type_get_underlying_type (t);
 730         switch (t->type) {
 731         case MONO_TYPE_I4:
 732         case MONO_TYPE_U4:
 733         case MONO_TYPE_I:
 734         case MONO_TYPE_U:
 735         case MONO_TYPE_PTR:
 736         case MONO_TYPE_FNPTR:
 737                 return TRUE;
 738         case MONO_TYPE_OBJECT:
 739         case MONO_TYPE_STRING:
 740         case MONO_TYPE_CLASS:
 741         case MONO_TYPE_SZARRAY:
 742         case MONO_TYPE_ARRAY:
 743                 return TRUE;
 744         case MONO_TYPE_VALUETYPE:
 745                 return FALSE;
 746         }
 747         return FALSE;
 748 }
 749
 750 GList *
 751 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 752 {
 753         GList *vars = NULL;
 754         int i;
 755
 756         for (i = 0; i < cfg->num_varinfo; i++) {
 757                 MonoInst *ins = cfg->varinfo [i];
 758                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 759
 760                 /* unused vars */
 761                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 762                         continue;
 763
 764                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 765                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 766                         continue;
 767
 768                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 769                  * 8bit quantities in caller saved registers on x86 */
 770                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 771                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 772                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 773                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 774                         g_assert (i == vmv->idx);
 775                         vars = g_list_prepend (vars, vmv);
 776                 }
 777         }
 778
 779         vars = mono_varlist_sort (cfg, vars, 0);
 780
 781         return vars;
 782 }
 783
 784 /**
 785  * mono_arch_compute_omit_fp:
 786  *
 787  *   Determine whenever the frame pointer can be eliminated.
 788  */
 789 static void
 790 mono_arch_compute_omit_fp (MonoCompile *cfg)
 791 {
 792         MonoMethodSignature *sig;
 793         MonoMethodHeader *header;
 794         int i;
 795         CallInfo *cinfo;
 796
 797         if (cfg->arch.omit_fp_computed)
 798                 return;
 799
 800         header = mono_method_get_header (cfg->method);
 801
 802         sig = mono_method_signature (cfg->method);
 803
 804         cinfo = get_call_info (sig, FALSE);
 805
 806         /*
 807          * FIXME: Remove some of the restrictions.
 808          */
 809         cfg->arch.omit_fp = TRUE;
 810         cfg->arch.omit_fp_computed = TRUE;
 811
 812         /* Temporarily disable this when running in the debugger until we have support
 813          * for this in the debugger. */
 814         if (mono_debug_using_mono_debugger ())
 815                 cfg->arch.omit_fp = FALSE;
 816
 817         if (!debug_omit_fp ())
 818                 cfg->arch.omit_fp = FALSE;
 819         /*
 820         if (cfg->method->save_lmf)
 821                 cfg->arch.omit_fp = FALSE;
 822         */
 823         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 824                 cfg->arch.omit_fp = FALSE;
 825         if (header->num_clauses)
 826                 cfg->arch.omit_fp = FALSE;
 827         if (cfg->param_area)
 828                 cfg->arch.omit_fp = FALSE;
 829         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 830                 cfg->arch.omit_fp = FALSE;
 831         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 832                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 833                 cfg->arch.omit_fp = FALSE;
 834         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 835                 ArgInfo *ainfo = &cinfo->args [i];
 836
 837                 if (ainfo->storage == ArgOnStack) {
 838                         /*
 839                          * The stack offset can only be determined when the frame
 840                          * size is known.
 841                          */
 842                         cfg->arch.omit_fp = FALSE;
 843                 }
 844         }
 845
 846         g_free (cinfo);
 847 }
 848
 849 GList *
 850 mono_arch_get_global_int_regs (MonoCompile *cfg)
 851 {
 852         GList *regs = NULL;
 853
 854         mono_arch_compute_omit_fp (cfg);
 855
 856         if (cfg->arch.omit_fp)
 857                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 858
 859         /* We use the callee saved registers for global allocation */
 860         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 861         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 862         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 863         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 864         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 865
 866         return regs;
 867 }
 868
 869 /*
 870  * mono_arch_regalloc_cost:
 871  *
 872  *  Return the cost, in number of memory references, of the action of
 873  * allocating the variable VMV into a register during global register
 874  * allocation.
 875  */
 876 guint32
 877 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 878 {
 879         MonoInst *ins = cfg->varinfo [vmv->idx];
 880
 881         if (cfg->method->save_lmf)
 882                 /* The register is already saved */
 883                 /* substract 1 for the invisible store in the prolog */
 884                 return (ins->opcode == OP_ARG) ? 0 : 1;
 885         else
 886                 /* push+pop */
 887                 return (ins->opcode == OP_ARG) ? 1 : 2;
 888 }
 889
 890 void
 891 mono_arch_allocate_vars (MonoCompile *cfg)
 892 {
 893         MonoMethodSignature *sig;
 894         MonoMethodHeader *header;
 895         MonoInst *inst;
 896         int i, offset;
 897         guint32 locals_stack_size, locals_stack_align;
 898         gint32 *offsets;
 899         CallInfo *cinfo;
 900
 901         header = mono_method_get_header (cfg->method);
 902
 903         sig = mono_method_signature (cfg->method);
 904
 905         cinfo = get_call_info (sig, FALSE);
 906
 907         mono_arch_compute_omit_fp (cfg);
 908
 909         /*
 910          * We use the ABI calling conventions for managed code as well.
 911          * Exception: valuetypes are never passed or returned in registers.
 912          */
 913
 914         if (cfg->arch.omit_fp) {
 915                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 916                 cfg->frame_reg = AMD64_RSP;
 917                 offset = 0;
 918         } else {
 919                 /* Locals are allocated backwards from %fp */
 920                 cfg->frame_reg = AMD64_RBP;
 921                 offset = 0;
 922         }
 923
 924         cfg->arch.reg_save_area_offset = offset;
 925
 926         /* Reserve space for caller saved registers */
 927         for (i = 0; i < AMD64_NREG; ++i)
 928                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 929                         offset += sizeof (gpointer);
 930                 }
 931
 932         if (cfg->method->save_lmf) {
 933                 /* Reserve stack space for saving LMF + argument regs */
 934                 guint32 size = sizeof (MonoLMF);
 935
 936                 if (lmf_tls_offset == -1)
 937                         /* Need to save argument regs too */
 938                         size += (AMD64_NREG * 8) + (8 * 8);
 939
 940                 if (cfg->arch.omit_fp) {
 941                         cfg->arch.lmf_offset = offset;
 942                         offset += size;
 943                 }
 944                 else {
 945                         offset += size;
 946                         cfg->arch.lmf_offset = -offset;
 947                 }
 948         }
 949
 950         if (sig->ret->type != MONO_TYPE_VOID) {
 951                 switch (cinfo->ret.storage) {
 952                 case ArgInIReg:
 953                 case ArgInFloatSSEReg:
 954                 case ArgInDoubleSSEReg:
 955                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 956                                 /* The register is volatile */
 957                                 cfg->ret->opcode = OP_REGOFFSET;
 958                                 cfg->ret->inst_basereg = cfg->frame_reg;
 959                                 if (cfg->arch.omit_fp) {
 960                                         cfg->ret->inst_offset = offset;
 961                                         offset += 8;
 962                                 } else {
 963                                         offset += 8;
 964                                         cfg->ret->inst_offset = -offset;
 965                                 }
 966                         }
 967                         else {
 968                                 cfg->ret->opcode = OP_REGVAR;
 969                                 cfg->ret->inst_c0 = cinfo->ret.reg;
 970                         }
 971                         break;
 972                 case ArgValuetypeInReg:
 973                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 974                         g_assert (!cfg->arch.omit_fp);
 975                         offset += 16;
 976                         cfg->ret->opcode = OP_REGOFFSET;
 977                         cfg->ret->inst_basereg = cfg->frame_reg;
 978                         cfg->ret->inst_offset = - offset;
 979                         break;
 980                 default:
 981                         g_assert_not_reached ();
 982                 }
 983                 cfg->ret->dreg = cfg->ret->inst_c0;
 984         }
 985
 986         /* Allocate locals */
 987         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
 988         if (locals_stack_align) {
 989                 offset += (locals_stack_align - 1);
 990                 offset &= ~(locals_stack_align - 1);
 991         }
 992         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 993                 if (offsets [i] != -1) {
 994                         MonoInst *inst = cfg->varinfo [i];
 995                         inst->opcode = OP_REGOFFSET;
 996                         inst->inst_basereg = cfg->frame_reg;
 997                         if (cfg->arch.omit_fp)
 998                                 inst->inst_offset = (offset + offsets [i]);
 999                         else
1000                                 inst->inst_offset = - (offset + offsets [i]);
1001                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1002                 }
1003         }
1004         g_free (offsets);
1005         offset += locals_stack_size;
1006
1007         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1008                 g_assert (!cfg->arch.omit_fp);
1009                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1010                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1011         }
1012
1013         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1014                 inst = cfg->varinfo [i];
1015                 if (inst->opcode != OP_REGVAR) {
1016                         ArgInfo *ainfo = &cinfo->args [i];
1017                         gboolean inreg = TRUE;
1018                         MonoType *arg_type;
1019
1020                         if (sig->hasthis && (i == 0))
1021                                 arg_type = &mono_defaults.object_class->byval_arg;
1022                         else
1023                                 arg_type = sig->params [i - sig->hasthis];
1024
1025                         /* FIXME: Allocate volatile arguments to registers */
1026                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1027                                 inreg = FALSE;
1028
1029                         /*
1030                          * Under AMD64, all registers used to pass arguments to functions
1031                          * are volatile across calls.
1032                          * FIXME: Optimize this.
1033                          */
1034                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1035                                 inreg = FALSE;
1036
1037                         inst->opcode = OP_REGOFFSET;
1038
1039                         switch (ainfo->storage) {
1040                         case ArgInIReg:
1041                         case ArgInFloatSSEReg:
1042                         case ArgInDoubleSSEReg:
1043                                 inst->opcode = OP_REGVAR;
1044                                 inst->dreg = ainfo->reg;
1045                                 break;
1046                         case ArgOnStack:
1047                                 g_assert (!cfg->arch.omit_fp);
1048                                 inst->opcode = OP_REGOFFSET;
1049                                 inst->inst_basereg = cfg->frame_reg;
1050                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1051                                 break;
1052                         case ArgValuetypeInReg:
1053                                 break;
1054                         default:
1055                                 NOT_IMPLEMENTED;
1056                         }
1057
1058                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1059                                 inst->opcode = OP_REGOFFSET;
1060                                 inst->inst_basereg = cfg->frame_reg;
1061                                 /* These arguments are saved to the stack in the prolog */
1062                                 if (cfg->arch.omit_fp) {
1063                                         inst->inst_offset = offset;
1064                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1065                                 } else {
1066                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1067                                         inst->inst_offset = - offset;
1068                                 }
1069                         }
1070                 }
1071         }
1072
1073         cfg->stack_offset = offset;
1074
1075         g_free (cinfo);
1076 }
1077
1078 void
1079 mono_arch_create_vars (MonoCompile *cfg)
1080 {
1081         MonoMethodSignature *sig;
1082         CallInfo *cinfo;
1083
1084         sig = mono_method_signature (cfg->method);
1085
1086         cinfo = get_call_info (sig, FALSE);
1087
1088         if (cinfo->ret.storage == ArgValuetypeInReg)
1089                 cfg->ret_var_is_local = TRUE;
1090
1091         g_free (cinfo);
1092 }
1093
1094 static void
1095 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1096 {
1097         switch (storage) {
1098         case ArgInIReg:
1099                 arg->opcode = OP_OUTARG_REG;
1100                 arg->inst_left = tree;
1101                 arg->inst_right = (MonoInst*)call;
1102                 arg->unused = reg;
1103                 call->used_iregs |= 1 << reg;
1104                 break;
1105         case ArgInFloatSSEReg:
1106                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1107                 arg->inst_left = tree;
1108                 arg->inst_right = (MonoInst*)call;
1109                 arg->unused = reg;
1110                 call->used_fregs |= 1 << reg;
1111                 break;
1112         case ArgInDoubleSSEReg:
1113                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1114                 arg->inst_left = tree;
1115                 arg->inst_right = (MonoInst*)call;
1116                 arg->unused = reg;
1117                 call->used_fregs |= 1 << reg;
1118                 break;
1119         default:
1120                 g_assert_not_reached ();
1121         }
1122 }
1123
1124 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1125  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1126  */
1127
1128 static int
1129 arg_storage_to_ldind (ArgStorage storage)
1130 {
1131         switch (storage) {
1132         case ArgInIReg:
1133                 return CEE_LDIND_I;
1134         case ArgInDoubleSSEReg:
1135                 return CEE_LDIND_R8;
1136         case ArgInFloatSSEReg:
1137                 return CEE_LDIND_R4;
1138         default:
1139                 g_assert_not_reached ();
1140         }
1141
1142         return -1;
1143 }
1144
1145 /*
1146  * take the arguments and generate the arch-specific
1147  * instructions to properly call the function in call.
1148  * This includes pushing, moving arguments to the right register
1149  * etc.
1150  * Issue: who does the spilling if needed, and when?
1151  */
1152 MonoCallInst*
1153 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1154         MonoInst *arg, *in;
1155         MonoMethodSignature *sig;
1156         int i, n, stack_size;
1157         CallInfo *cinfo;
1158         ArgInfo *ainfo;
1159
1160         stack_size = 0;
1161
1162         sig = call->signature;
1163         n = sig->param_count + sig->hasthis;
1164
1165         cinfo = get_call_info (sig, sig->pinvoke);
1166
1167         for (i = 0; i < n; ++i) {
1168                 ainfo = cinfo->args + i;
1169
1170                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1171                         MonoMethodSignature *tmp_sig;
1172
1173                         /* Emit the signature cookie just before the implicit arguments */
1174                         MonoInst *sig_arg;
1175                         /* FIXME: Add support for signature tokens to AOT */
1176                         cfg->disable_aot = TRUE;
1177
1178                         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1179
1180                         /*
1181                          * mono_ArgIterator_Setup assumes the signature cookie is
1182                          * passed first and all the arguments which were before it are
1183                          * passed on the stack after the signature. So compensate by
1184                          * passing a different signature.
1185                          */
1186                         tmp_sig = mono_metadata_signature_dup (call->signature);
1187                         tmp_sig->param_count -= call->signature->sentinelpos;
1188                         tmp_sig->sentinelpos = 0;
1189                         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1190
1191                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1192                         sig_arg->inst_p0 = tmp_sig;
1193
1194                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1195                         arg->inst_left = sig_arg;
1196                         arg->type = STACK_PTR;
1197
1198                         /* prepend, so they get reversed */
1199                         arg->next = call->out_args;
1200                         call->out_args = arg;
1201                 }
1202
1203                 if (is_virtual && i == 0) {
1204                         /* the argument will be attached to the call instruction */
1205                         in = call->args [i];
1206                 } else {
1207                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1208                         in = call->args [i];
1209                         arg->cil_code = in->cil_code;
1210                         arg->inst_left = in;
1211                         arg->type = in->type;
1212                         /* prepend, so they get reversed */
1213                         arg->next = call->out_args;
1214                         call->out_args = arg;
1215
1216                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1217                                 gint align;
1218                                 guint32 size;
1219
1220                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1221                                         size = sizeof (MonoTypedRef);
1222                                         align = sizeof (gpointer);
1223                                 }
1224                                 else
1225                                 if (sig->pinvoke)
1226                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1227                                 else {
1228                                         /*
1229                                          * Other backends use mono_type_stack_size (), but that
1230                                          * aligns the size to 8, which is larger than the size of
1231                                          * the source, leading to reads of invalid memory if the
1232                                          * source is at the end of address space.
1233                                          */
1234                                         size = mono_class_value_size (in->klass, &align);
1235                                 }
1236                                 if (ainfo->storage == ArgValuetypeInReg) {
1237                                         if (ainfo->pair_storage [1] == ArgNone) {
1238                                                 MonoInst *load;
1239
1240                                                 /* Simpler case */
1241
1242                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1243                                                 load->inst_left = in;
1244
1245                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1246                                         }
1247                                         else {
1248                                                 /* Trees can't be shared so make a copy */
1249                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1250                                                 MonoInst *load, *load2, *offset_ins;
1251
1252                                                 /* Reg1 */
1253                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1254                                                 load->ssa_op = MONO_SSA_LOAD;
1255                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1256
1257                                                 NEW_ICONST (cfg, offset_ins, 0);
1258                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1259                                                 load2->inst_left = load;
1260                                                 load2->inst_right = offset_ins;
1261
1262                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1263                                                 load->inst_left = load2;
1264
1265                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1266
1267                                                 /* Reg2 */
1268                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1269                                                 load->ssa_op = MONO_SSA_LOAD;
1270                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1271
1272                                                 NEW_ICONST (cfg, offset_ins, 8);
1273                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1274                                                 load2->inst_left = load;
1275                                                 load2->inst_right = offset_ins;
1276
1277                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1278                                                 load->inst_left = load2;
1279
1280                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1281                                                 arg->cil_code = in->cil_code;
1282                                                 arg->type = in->type;
1283                                                 /* prepend, so they get reversed */
1284                                                 arg->next = call->out_args;
1285                                                 call->out_args = arg;
1286
1287                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1288
1289                                                 /* Prepend a copy inst */
1290                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1291                                                 arg->cil_code = in->cil_code;
1292                                                 arg->ssa_op = MONO_SSA_STORE;
1293                                                 arg->inst_left = vtaddr;
1294                                                 arg->inst_right = in;
1295                                                 arg->type = in->type;
1296
1297                                                 /* prepend, so they get reversed */
1298                                                 arg->next = call->out_args;
1299                                                 call->out_args = arg;
1300                                         }
1301                                 }
1302                                 else {
1303                                         arg->opcode = OP_OUTARG_VT;
1304                                         arg->klass = in->klass;
1305                                         arg->unused = sig->pinvoke;
1306                                         arg->inst_imm = size;
1307                                 }
1308                         }
1309                         else {
1310                                 switch (ainfo->storage) {
1311                                 case ArgInIReg:
1312                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1313                                         break;
1314                                 case ArgInFloatSSEReg:
1315                                 case ArgInDoubleSSEReg:
1316                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1317                                         break;
1318                                 case ArgOnStack:
1319                                         arg->opcode = OP_OUTARG;
1320                                         if (!sig->params [i - sig->hasthis]->byref) {
1321                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1322                                                         arg->opcode = OP_OUTARG_R4;
1323                                                 else
1324                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1325                                                                 arg->opcode = OP_OUTARG_R8;
1326                                         }
1327                                         break;
1328                                 default:
1329                                         g_assert_not_reached ();
1330                                 }
1331                         }
1332                 }
1333         }
1334
1335         if (cinfo->need_stack_align) {
1336                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1337                 /* prepend, so they get reversed */
1338                 arg->next = call->out_args;
1339                 call->out_args = arg;
1340         }
1341
1342         call->stack_usage = cinfo->stack_usage;
1343         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1344         cfg->flags |= MONO_CFG_HAS_CALLS;
1345
1346         g_free (cinfo);
1347
1348         return call;
1349 }
1350
1351 #define EMIT_COND_BRANCH(ins,cond,sign) \
1352 if (ins->flags & MONO_INST_BRLABEL) { \
1353         if (ins->inst_i0->inst_c0) { \
1354                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1355         } else { \
1356                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1357                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1358                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1359                         x86_branch8 (code, cond, 0, sign); \
1360                 else \
1361                         x86_branch32 (code, cond, 0, sign); \
1362         } \
1363 } else { \
1364         if (ins->inst_true_bb->native_offset) { \
1365                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1366         } else { \
1367                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1368                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1369                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1370                         x86_branch8 (code, cond, 0, sign); \
1371                 else \
1372                         x86_branch32 (code, cond, 0, sign); \
1373         } \
1374 }
1375
1376 /* emit an exception if condition is fail */
1377 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1378         do {                                                        \
1379                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1380                 if (tins == NULL) {                                                                             \
1381                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1382                                         MONO_PATCH_INFO_EXC, exc_name);  \
1383                         x86_branch32 (code, cond, 0, signed);               \
1384                 } else {        \
1385                         EMIT_COND_BRANCH (tins, cond, signed);  \
1386                 }                       \
1387         } while (0);
1388
1389 #define EMIT_FPCOMPARE(code) do { \
1390         amd64_fcompp (code); \
1391         amd64_fnstsw (code); \
1392 } while (0);
1393
1394 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1395     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1396         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1397         amd64_ ##op (code); \
1398         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1399         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1400 } while (0);
1401
1402 static guint8*
1403 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1404 {
1405         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1406
1407         if (cfg->compile_aot) {
1408                 amd64_call_membase (code, AMD64_RIP, 0);
1409         }
1410         else {
1411                 gboolean near_call = FALSE;
1412
1413                 /*
1414                  * Indirect calls are expensive so try to make a near call if possible.
1415                  * The caller memory is allocated by the code manager so it is
1416                  * guaranteed to be at a 32 bit offset.
1417                  */
1418
1419                 if (patch_type != MONO_PATCH_INFO_ABS) {
1420                         /* The target is in memory allocated using the code manager */
1421                         near_call = TRUE;
1422
1423                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1424                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1425                                         /* The callee might be an AOT method */
1426                                         near_call = FALSE;
1427                         }
1428
1429                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1430                                 /*
1431                                  * The call might go directly to a native function without
1432                                  * the wrapper.
1433                                  */
1434                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1435                                 if (mi) {
1436                                         gconstpointer target = mono_icall_get_wrapper (mi);
1437                                         if ((((guint64)target) >> 32) != 0)
1438                                                 near_call = FALSE;
1439                                 }
1440                         }
1441                 }
1442                 else {
1443                         if (mono_find_class_init_trampoline_by_addr (data))
1444                                 near_call = TRUE;
1445                         else {
1446                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1447                                 if (info) {
1448                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1449                                                 strstr (cfg->method->name, info->name)) {
1450                                                 /* A call to the wrapped function */
1451                                                 if ((((guint64)data) >> 32) == 0)
1452                                                         near_call = TRUE;
1453                                         }
1454                                         else if (info->func == info->wrapper) {
1455                                                 /* No wrapper */
1456                                                 if ((((guint64)info->func) >> 32) == 0)
1457                                                         near_call = TRUE;
1458                                         }
1459                                         else
1460                                                 near_call = TRUE;
1461                                 }
1462                                 else if ((((guint64)data) >> 32) == 0)
1463                                         near_call = TRUE;
1464                         }
1465                 }
1466
1467                 if (cfg->method->dynamic)
1468                         /* These methods are allocated using malloc */
1469                         near_call = FALSE;
1470
1471                 if (near_call) {
1472                         amd64_call_code (code, 0);
1473                 }
1474                 else {
1475                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1476                         amd64_call_reg (code, GP_SCRATCH_REG);
1477                 }
1478         }
1479
1480         return code;
1481 }
1482
1483 /* FIXME: Add more instructions */
1484 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1485
1486 static void
1487 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1488 {
1489         MonoInst *ins, *last_ins = NULL;
1490         ins = bb->code;
1491
1492         while (ins) {
1493
1494                 switch (ins->opcode) {
1495                 case OP_ICONST:
1496                 case OP_I8CONST:
1497                         /* reg = 0 -> XOR (reg, reg) */
1498                         /* XOR sets cflags on x86, so we cant do it always */
1499                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1500                                 ins->opcode = CEE_XOR;
1501                                 ins->sreg1 = ins->dreg;
1502                                 ins->sreg2 = ins->dreg;
1503                         }
1504                         break;
1505                 case OP_MUL_IMM:
1506                         /* remove unnecessary multiplication with 1 */
1507                         if (ins->inst_imm == 1) {
1508                                 if (ins->dreg != ins->sreg1) {
1509                                         ins->opcode = OP_MOVE;
1510                                 } else {
1511                                         last_ins->next = ins->next;
1512                                         ins = ins->next;
1513                                         continue;
1514                                 }
1515                         }
1516                         break;
1517                 case OP_COMPARE_IMM:
1518                         /* OP_COMPARE_IMM (reg, 0)
1519                          * -->
1520                          * OP_AMD64_TEST_NULL (reg)
1521                          */
1522                         if (!ins->inst_imm)
1523                                 ins->opcode = OP_AMD64_TEST_NULL;
1524                         break;
1525                 case OP_ICOMPARE_IMM:
1526                         if (!ins->inst_imm)
1527                                 ins->opcode = OP_X86_TEST_NULL;
1528                         break;
1529                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1530                         /*
1531                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1532                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1533                          * -->
1534                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1535                          * OP_COMPARE_IMM reg, imm
1536                          *
1537                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1538                          */
1539                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1540                             ins->inst_basereg == last_ins->inst_destbasereg &&
1541                             ins->inst_offset == last_ins->inst_offset) {
1542                                         ins->opcode = OP_ICOMPARE_IMM;
1543                                         ins->sreg1 = last_ins->sreg1;
1544
1545                                         /* check if we can remove cmp reg,0 with test null */
1546                                         if (!ins->inst_imm)
1547                                                 ins->opcode = OP_X86_TEST_NULL;
1548                                 }
1549
1550                         break;
1551                 case OP_LOAD_MEMBASE:
1552                 case OP_LOADI4_MEMBASE:
1553                         /*
1554                          * Note: if reg1 = reg2 the load op is removed
1555                          *
1556                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1557                          * OP_LOAD_MEMBASE offset(basereg), reg2
1558                          * -->
1559                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1560                          * OP_MOVE reg1, reg2
1561                          */
1562                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1563                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1564                             ins->inst_basereg == last_ins->inst_destbasereg &&
1565                             ins->inst_offset == last_ins->inst_offset) {
1566                                 if (ins->dreg == last_ins->sreg1) {
1567                                         last_ins->next = ins->next;
1568                                         ins = ins->next;
1569                                         continue;
1570                                 } else {
1571                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1572                                         ins->opcode = OP_MOVE;
1573                                         ins->sreg1 = last_ins->sreg1;
1574                                 }
1575
1576                         /*
1577                          * Note: reg1 must be different from the basereg in the second load
1578                          * Note: if reg1 = reg2 is equal then second load is removed
1579                          *
1580                          * OP_LOAD_MEMBASE offset(basereg), reg1
1581                          * OP_LOAD_MEMBASE offset(basereg), reg2
1582                          * -->
1583                          * OP_LOAD_MEMBASE offset(basereg), reg1
1584                          * OP_MOVE reg1, reg2
1585                          */
1586                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1587                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1588                               ins->inst_basereg != last_ins->dreg &&
1589                               ins->inst_basereg == last_ins->inst_basereg &&
1590                               ins->inst_offset == last_ins->inst_offset) {
1591
1592                                 if (ins->dreg == last_ins->dreg) {
1593                                         last_ins->next = ins->next;
1594                                         ins = ins->next;
1595                                         continue;
1596                                 } else {
1597                                         ins->opcode = OP_MOVE;
1598                                         ins->sreg1 = last_ins->dreg;
1599                                 }
1600
1601                                 //g_assert_not_reached ();
1602
1603 #if 0
1604                         /*
1605                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1606                          * OP_LOAD_MEMBASE offset(basereg), reg
1607                          * -->
1608                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1609                          * OP_ICONST reg, imm
1610                          */
1611                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1612                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1613                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1614                                    ins->inst_offset == last_ins->inst_offset) {
1615                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1616                                 ins->opcode = OP_ICONST;
1617                                 ins->inst_c0 = last_ins->inst_imm;
1618                                 g_assert_not_reached (); // check this rule
1619 #endif
1620                         }
1621                         break;
1622                 case OP_LOADU1_MEMBASE:
1623                 case OP_LOADI1_MEMBASE:
1624                         /*
1625                          * Note: if reg1 = reg2 the load op is removed
1626                          *
1627                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1628                          * OP_LOAD_MEMBASE offset(basereg), reg2
1629                          * -->
1630                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1631                          * OP_MOVE reg1, reg2
1632                          */
1633                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1634                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1635                                         ins->inst_offset == last_ins->inst_offset) {
1636                                 if (ins->dreg == last_ins->sreg1) {
1637                                         last_ins->next = ins->next;
1638                                         ins = ins->next;
1639                                         continue;
1640                                 } else {
1641                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1642                                         ins->opcode = OP_MOVE;
1643                                         ins->sreg1 = last_ins->sreg1;
1644                                 }
1645                         }
1646                         break;
1647                 case OP_LOADU2_MEMBASE:
1648                 case OP_LOADI2_MEMBASE:
1649                         /*
1650                          * Note: if reg1 = reg2 the load op is removed
1651                          *
1652                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1653                          * OP_LOAD_MEMBASE offset(basereg), reg2
1654                          * -->
1655                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1656                          * OP_MOVE reg1, reg2
1657                          */
1658                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1659                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1660                                         ins->inst_offset == last_ins->inst_offset) {
1661                                 if (ins->dreg == last_ins->sreg1) {
1662                                         last_ins->next = ins->next;
1663                                         ins = ins->next;
1664                                         continue;
1665                                 } else {
1666                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1667                                         ins->opcode = OP_MOVE;
1668                                         ins->sreg1 = last_ins->sreg1;
1669                                 }
1670                         }
1671                         break;
1672                 case CEE_CONV_I4:
1673                 case CEE_CONV_U4:
1674                 case OP_MOVE:
1675                         /*
1676                          * Removes:
1677                          *
1678                          * OP_MOVE reg, reg
1679                          */
1680                         if (ins->dreg == ins->sreg1) {
1681                                 if (last_ins)
1682                                         last_ins->next = ins->next;
1683                                 ins = ins->next;
1684                                 continue;
1685                         }
1686                         /*
1687                          * Removes:
1688                          *
1689                          * OP_MOVE sreg, dreg
1690                          * OP_MOVE dreg, sreg
1691                          */
1692                         if (last_ins && last_ins->opcode == OP_MOVE &&
1693                             ins->sreg1 == last_ins->dreg &&
1694                             ins->dreg == last_ins->sreg1) {
1695                                 last_ins->next = ins->next;
1696                                 ins = ins->next;
1697                                 continue;
1698                         }
1699                         break;
1700                 }
1701                 last_ins = ins;
1702                 ins = ins->next;
1703         }
1704         bb->last_ins = last_ins;
1705 }
1706
1707 static void
1708 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1709 {
1710         if (ins == NULL) {
1711                 ins = bb->code;
1712                 bb->code = to_insert;
1713                 to_insert->next = ins;
1714         }
1715         else {
1716                 to_insert->next = ins->next;
1717                 ins->next = to_insert;
1718         }
1719 }
1720
1721 #define NEW_INS(cfg,dest,op) do {       \
1722                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1723                 (dest)->opcode = (op);  \
1724         insert_after_ins (bb, last_ins, (dest)); \
1725         } while (0)
1726
1727 /*
1728  * mono_arch_lowering_pass:
1729  *
1730  *  Converts complex opcodes into simpler ones so that each IR instruction
1731  * corresponds to one machine instruction.
1732  */
1733 static void
1734 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1735 {
1736         MonoInst *ins, *temp, *last_ins = NULL;
1737         ins = bb->code;
1738
1739         if (bb->max_ireg > cfg->rs->next_vireg)
1740                 cfg->rs->next_vireg = bb->max_ireg;
1741         if (bb->max_freg > cfg->rs->next_vfreg)
1742                 cfg->rs->next_vfreg = bb->max_freg;
1743
1744         /*
1745          * FIXME: Need to add more instructions, but the current machine
1746          * description can't model some parts of the composite instructions like
1747          * cdq.
1748          */
1749         while (ins) {
1750                 switch (ins->opcode) {
1751                 case OP_DIV_IMM:
1752                 case OP_REM_IMM:
1753                 case OP_IDIV_IMM:
1754                 case OP_IREM_IMM:
1755                         NEW_INS (cfg, temp, OP_ICONST);
1756                         temp->inst_c0 = ins->inst_imm;
1757                         temp->dreg = mono_regstate_next_int (cfg->rs);
1758                         switch (ins->opcode) {
1759                         case OP_DIV_IMM:
1760                                 ins->opcode = OP_LDIV;
1761                                 break;
1762                         case OP_REM_IMM:
1763                                 ins->opcode = OP_LREM;
1764                                 break;
1765                         case OP_IDIV_IMM:
1766                                 ins->opcode = OP_IDIV;
1767                                 break;
1768                         case OP_IREM_IMM:
1769                                 ins->opcode = OP_IREM;
1770                                 break;
1771                         }
1772                         ins->sreg2 = temp->dreg;
1773                         break;
1774                 case OP_COMPARE_IMM:
1775                         if (!amd64_is_imm32 (ins->inst_imm)) {
1776                                 NEW_INS (cfg, temp, OP_I8CONST);
1777                                 temp->inst_c0 = ins->inst_imm;
1778                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1779                                 ins->opcode = OP_COMPARE;
1780                                 ins->sreg2 = temp->dreg;
1781                         }
1782                         break;
1783                 case OP_LOAD_MEMBASE:
1784                 case OP_LOADI8_MEMBASE:
1785                         if (!amd64_is_imm32 (ins->inst_offset)) {
1786                                 NEW_INS (cfg, temp, OP_I8CONST);
1787                                 temp->inst_c0 = ins->inst_offset;
1788                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1789                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1790                                 ins->inst_indexreg = temp->dreg;
1791                         }
1792                         break;
1793                 case OP_STORE_MEMBASE_IMM:
1794                 case OP_STOREI8_MEMBASE_IMM:
1795                         if (!amd64_is_imm32 (ins->inst_imm)) {
1796                                 NEW_INS (cfg, temp, OP_I8CONST);
1797                                 temp->inst_c0 = ins->inst_imm;
1798                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1799                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1800                                 ins->sreg1 = temp->dreg;
1801                         }
1802                         break;
1803                 default:
1804                         break;
1805                 }
1806                 last_ins = ins;
1807                 ins = ins->next;
1808         }
1809         bb->last_ins = last_ins;
1810
1811         bb->max_ireg = cfg->rs->next_vireg;
1812         bb->max_freg = cfg->rs->next_vfreg;
1813 }
1814
1815 static const int
1816 branch_cc_table [] = {
1817         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1818         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1819         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1820 };
1821
1822 static int
1823 opcode_to_x86_cond (int opcode)
1824 {
1825         switch (opcode) {
1826         case OP_IBEQ:
1827                 return X86_CC_EQ;
1828         case OP_IBNE_UN:
1829                 return X86_CC_NE;
1830         case OP_IBLT:
1831                 return X86_CC_LT;
1832         case OP_IBLT_UN:
1833                 return X86_CC_LT;
1834         case OP_IBGT:
1835                 return X86_CC_GT;
1836         case OP_IBGT_UN:
1837                 return X86_CC_GT;
1838         case OP_IBGE:
1839                 return X86_CC_GE;
1840         case OP_IBGE_UN:
1841                 return X86_CC_GE;
1842         case OP_IBLE:
1843                 return X86_CC_LE;
1844         case OP_IBLE_UN:
1845                 return X86_CC_LE;
1846         case OP_COND_EXC_IOV:
1847                 return X86_CC_O;
1848         case OP_COND_EXC_IC:
1849                 return X86_CC_C;
1850         default:
1851                 g_assert_not_reached ();
1852         }
1853
1854         return -1;
1855 }
1856
1857 /*#include "cprop.c"*/
1858
1859 /*
1860  * Local register allocation.
1861  * We first scan the list of instructions and we save the liveness info of
1862  * each register (when the register is first used, when it's value is set etc.).
1863  * We also reverse the list of instructions (in the InstList list) because assigning
1864  * registers backwards allows for more tricks to be used.
1865  */
1866 void
1867 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1868 {
1869         if (!bb->code)
1870                 return;
1871
1872         mono_arch_lowering_pass (cfg, bb);
1873
1874         mono_local_regalloc (cfg, bb);
1875 }
1876
1877 static unsigned char*
1878 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1879 {
1880         if (use_sse2) {
1881                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1882         }
1883         else {
1884                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1885                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1886                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1887                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1888                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1889                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1890                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1891                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1892                 amd64_pop_reg (code, dreg);
1893                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1894                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1895         }
1896
1897         if (size == 1)
1898                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1899         else if (size == 2)
1900                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1901         return code;
1902 }
1903
1904 static unsigned char*
1905 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1906 {
1907         int sreg = tree->sreg1;
1908         int need_touch = FALSE;
1909
1910 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1911         if (!tree->flags & MONO_INST_INIT)
1912                 need_touch = TRUE;
1913 #endif
1914
1915         if (need_touch) {
1916                 guint8* br[5];
1917
1918                 /*
1919                  * Under Windows:
1920                  * If requested stack size is larger than one page,
1921                  * perform stack-touch operation
1922                  */
1923                 /*
1924                  * Generate stack probe code.
1925                  * Under Windows, it is necessary to allocate one page at a time,
1926                  * "touching" stack after each successful sub-allocation. This is
1927                  * because of the way stack growth is implemented - there is a
1928                  * guard page before the lowest stack page that is currently commited.
1929                  * Stack normally grows sequentially so OS traps access to the
1930                  * guard page and commits more pages when needed.
1931                  */
1932                 amd64_test_reg_imm (code, sreg, ~0xFFF);
1933                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1934
1935                 br[2] = code; /* loop */
1936                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
1937                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
1938                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1939                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1940                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1941                 amd64_patch (br[3], br[2]);
1942                 amd64_test_reg_reg (code, sreg, sreg);
1943                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1944                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1945
1946                 br[1] = code; x86_jump8 (code, 0);
1947
1948                 amd64_patch (br[0], code);
1949                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1950                 amd64_patch (br[1], code);
1951                 amd64_patch (br[4], code);
1952         }
1953         else
1954                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
1955
1956         if (tree->flags & MONO_INST_INIT) {
1957                 int offset = 0;
1958                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
1959                         amd64_push_reg (code, AMD64_RAX);
1960                         offset += 8;
1961                 }
1962                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
1963                         amd64_push_reg (code, AMD64_RCX);
1964                         offset += 8;
1965                 }
1966                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
1967                         amd64_push_reg (code, AMD64_RDI);
1968                         offset += 8;
1969                 }
1970
1971                 amd64_shift_reg_imm (code, X86_SHR, sreg, 4);
1972                 if (sreg != AMD64_RCX)
1973                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
1974                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
1975
1976                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
1977                 amd64_cld (code);
1978                 amd64_prefix (code, X86_REP_PREFIX);
1979                 amd64_stosl (code);
1980
1981                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
1982                         amd64_pop_reg (code, AMD64_RDI);
1983                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
1984                         amd64_pop_reg (code, AMD64_RCX);
1985                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
1986                         amd64_pop_reg (code, AMD64_RAX);
1987         }
1988         return code;
1989 }
1990
1991 static guint8*
1992 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1993 {
1994         CallInfo *cinfo;
1995         guint32 quad;
1996
1997         /* Move return value to the target register */
1998         /* FIXME: do this in the local reg allocator */
1999         switch (ins->opcode) {
2000         case CEE_CALL:
2001         case OP_CALL_REG:
2002         case OP_CALL_MEMBASE:
2003         case OP_LCALL:
2004         case OP_LCALL_REG:
2005         case OP_LCALL_MEMBASE:
2006                 g_assert (ins->dreg == AMD64_RAX);
2007                 break;
2008         case OP_FCALL:
2009         case OP_FCALL_REG:
2010         case OP_FCALL_MEMBASE:
2011                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2012                         if (use_sse2)
2013                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2014                         else {
2015                                 /* FIXME: optimize this */
2016                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2017                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2018                         }
2019                 }
2020                 else {
2021                         if (use_sse2) {
2022                                 if (ins->dreg != AMD64_XMM0)
2023                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2024                         }
2025                         else {
2026                                 /* FIXME: optimize this */
2027                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2028                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2029                         }
2030                 }
2031                 break;
2032         case OP_VCALL:
2033         case OP_VCALL_REG:
2034         case OP_VCALL_MEMBASE:
2035                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2036                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2037                         /* Pop the destination address from the stack */
2038                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2039                         amd64_pop_reg (code, AMD64_RCX);
2040
2041                         for (quad = 0; quad < 2; quad ++) {
2042                                 switch (cinfo->ret.pair_storage [quad]) {
2043                                 case ArgInIReg:
2044                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2045                                         break;
2046                                 case ArgInFloatSSEReg:
2047                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2048                                         break;
2049                                 case ArgInDoubleSSEReg:
2050                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2051                                         break;
2052                                 case ArgNone:
2053                                         break;
2054                                 default:
2055                                         NOT_IMPLEMENTED;
2056                                 }
2057                         }
2058                 }
2059                 g_free (cinfo);
2060                 break;
2061         }
2062
2063         return code;
2064 }
2065
2066 /*
2067  * emit_load_volatile_arguments:
2068  *
2069  *  Load volatile arguments from the stack to the original input registers.
2070  * Required before a tail call.
2071  */
2072 static guint8*
2073 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2074 {
2075         MonoMethod *method = cfg->method;
2076         MonoMethodSignature *sig;
2077         MonoInst *inst;
2078         CallInfo *cinfo;
2079         guint32 i;
2080
2081         /* FIXME: Generate intermediate code instead */
2082
2083         sig = mono_method_signature (method);
2084
2085         cinfo = get_call_info (sig, FALSE);
2086
2087         /* This is the opposite of the code in emit_prolog */
2088
2089         if (sig->ret->type != MONO_TYPE_VOID) {
2090                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2091                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2092                 }
2093         }
2094
2095         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2096                 ArgInfo *ainfo = cinfo->args + i;
2097                 MonoType *arg_type;
2098                 inst = cfg->varinfo [i];
2099
2100                 if (sig->hasthis && (i == 0))
2101                         arg_type = &mono_defaults.object_class->byval_arg;
2102                 else
2103                         arg_type = sig->params [i - sig->hasthis];
2104
2105                 if (inst->opcode != OP_REGVAR) {
2106                         switch (ainfo->storage) {
2107                         case ArgInIReg: {
2108                                 guint32 size = 8;
2109
2110                                 /* FIXME: I1 etc */
2111                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2112                                 break;
2113                         }
2114                         case ArgInFloatSSEReg:
2115                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2116                                 break;
2117                         case ArgInDoubleSSEReg:
2118                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2119                                 break;
2120                         default:
2121                                 break;
2122                         }
2123                 }
2124                 else {
2125                         g_assert (ainfo->storage == ArgInIReg);
2126
2127                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2128                 }
2129         }
2130
2131         g_free (cinfo);
2132
2133         return code;
2134 }
2135
2136 #define REAL_PRINT_REG(text,reg) \
2137 mono_assert (reg >= 0); \
2138 amd64_push_reg (code, AMD64_RAX); \
2139 amd64_push_reg (code, AMD64_RDX); \
2140 amd64_push_reg (code, AMD64_RCX); \
2141 amd64_push_reg (code, reg); \
2142 amd64_push_imm (code, reg); \
2143 amd64_push_imm (code, text " %d %p\n"); \
2144 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2145 amd64_call_reg (code, AMD64_RAX); \
2146 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2147 amd64_pop_reg (code, AMD64_RCX); \
2148 amd64_pop_reg (code, AMD64_RDX); \
2149 amd64_pop_reg (code, AMD64_RAX);
2150
2151 /* benchmark and set based on cpu */
2152 #define LOOP_ALIGNMENT 8
2153 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2154
2155 void
2156 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2157 {
2158         MonoInst *ins;
2159         MonoCallInst *call;
2160         guint offset;
2161         guint8 *code = cfg->native_code + cfg->code_len;
2162         MonoInst *last_ins = NULL;
2163         guint last_offset = 0;
2164         int max_len, cpos;
2165
2166         if (cfg->opt & MONO_OPT_PEEPHOLE)
2167                 peephole_pass (cfg, bb);
2168
2169         if (cfg->opt & MONO_OPT_LOOP) {
2170                 int pad, align = LOOP_ALIGNMENT;
2171                 /* set alignment depending on cpu */
2172                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2173                         pad = align - pad;
2174                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2175                         amd64_padding (code, pad);
2176                         cfg->code_len += pad;
2177                         bb->native_offset = cfg->code_len;
2178                 }
2179         }
2180
2181         if (cfg->verbose_level > 2)
2182                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2183
2184         cpos = bb->max_offset;
2185
2186         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2187                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2188                 g_assert (!cfg->compile_aot);
2189                 cpos += 6;
2190
2191                 cov->data [bb->dfn].cil_code = bb->cil_code;
2192                 /* this is not thread save, but good enough */
2193                 amd64_inc_mem (code, (guint64)&cov->data [bb->dfn].count);
2194         }
2195
2196         offset = code - cfg->native_code;
2197
2198         ins = bb->code;
2199         while (ins) {
2200                 offset = code - cfg->native_code;
2201
2202                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2203
2204                 if (offset > (cfg->code_size - max_len - 16)) {
2205                         cfg->code_size *= 2;
2206                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2207                         code = cfg->native_code + offset;
2208                         mono_jit_stats.code_reallocs++;
2209                 }
2210
2211                 mono_debug_record_line_number (cfg, ins, offset);
2212
2213                 switch (ins->opcode) {
2214                 case OP_BIGMUL:
2215                         amd64_mul_reg (code, ins->sreg2, TRUE);
2216                         break;
2217                 case OP_BIGMUL_UN:
2218                         amd64_mul_reg (code, ins->sreg2, FALSE);
2219                         break;
2220                 case OP_X86_SETEQ_MEMBASE:
2221                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2222                         break;
2223                 case OP_STOREI1_MEMBASE_IMM:
2224                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2225                         break;
2226                 case OP_STOREI2_MEMBASE_IMM:
2227                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2228                         break;
2229                 case OP_STOREI4_MEMBASE_IMM:
2230                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2231                         break;
2232                 case OP_STOREI1_MEMBASE_REG:
2233                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2234                         break;
2235                 case OP_STOREI2_MEMBASE_REG:
2236                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2237                         break;
2238                 case OP_STORE_MEMBASE_REG:
2239                 case OP_STOREI8_MEMBASE_REG:
2240                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2241                         break;
2242                 case OP_STOREI4_MEMBASE_REG:
2243                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2244                         break;
2245                 case OP_STORE_MEMBASE_IMM:
2246                 case OP_STOREI8_MEMBASE_IMM:
2247                         g_assert (amd64_is_imm32 (ins->inst_imm));
2248                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2249                         break;
2250                 case CEE_LDIND_I:
2251                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2252                         break;
2253                 case CEE_LDIND_I4:
2254                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2255                         break;
2256                 case CEE_LDIND_U4:
2257                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2258                         break;
2259                 case OP_LOADU4_MEM:
2260                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2261                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2262                         break;
2263                 case OP_LOAD_MEMBASE:
2264                 case OP_LOADI8_MEMBASE:
2265                         g_assert (amd64_is_imm32 (ins->inst_offset));
2266                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2267                         break;
2268                 case OP_LOADI4_MEMBASE:
2269                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2270                         break;
2271                 case OP_LOADU4_MEMBASE:
2272                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2273                         break;
2274                 case OP_LOADU1_MEMBASE:
2275                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2276                         break;
2277                 case OP_LOADI1_MEMBASE:
2278                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2279                         break;
2280                 case OP_LOADU2_MEMBASE:
2281                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2282                         break;
2283                 case OP_LOADI2_MEMBASE:
2284                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2285                         break;
2286                 case OP_AMD64_LOADI8_MEMINDEX:
2287                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2288                         break;
2289                 case CEE_CONV_I1:
2290                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2291                         break;
2292                 case CEE_CONV_I2:
2293                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2294                         break;
2295                 case CEE_CONV_U1:
2296                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2297                         break;
2298                 case CEE_CONV_U2:
2299                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2300                         break;
2301                 case CEE_CONV_U8:
2302                 case CEE_CONV_U:
2303                         /* Clean out the upper word */
2304                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2305                         break;
2306                 case CEE_CONV_I8:
2307                 case CEE_CONV_I:
2308                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2309                         break;
2310                 case OP_COMPARE:
2311                 case OP_LCOMPARE:
2312                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2313                         break;
2314                 case OP_COMPARE_IMM:
2315                         g_assert (amd64_is_imm32 (ins->inst_imm));
2316                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2317                         break;
2318                 case OP_X86_COMPARE_REG_MEMBASE:
2319                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2320                         break;
2321                 case OP_X86_TEST_NULL:
2322                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2323                         break;
2324                 case OP_AMD64_TEST_NULL:
2325                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2326                         break;
2327                 case OP_X86_ADD_MEMBASE_IMM:
2328                         /* FIXME: Make a 64 version too */
2329                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2330                         break;
2331                 case OP_X86_ADD_MEMBASE:
2332                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2333                         break;
2334                 case OP_X86_SUB_MEMBASE_IMM:
2335                         g_assert (amd64_is_imm32 (ins->inst_imm));
2336                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2337                         break;
2338                 case OP_X86_SUB_MEMBASE:
2339                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2340                         break;
2341                 case OP_X86_INC_MEMBASE:
2342                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2343                         break;
2344                 case OP_X86_INC_REG:
2345                         amd64_inc_reg_size (code, ins->dreg, 4);
2346                         break;
2347                 case OP_X86_DEC_MEMBASE:
2348                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2349                         break;
2350                 case OP_X86_DEC_REG:
2351                         amd64_dec_reg_size (code, ins->dreg, 4);
2352                         break;
2353                 case OP_X86_MUL_MEMBASE:
2354                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2355                         break;
2356                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2357                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2358                         break;
2359                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2360                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2361                         break;
2362                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2363                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2364                         break;
2365                 case CEE_BREAK:
2366                         amd64_breakpoint (code);
2367                         break;
2368                 case OP_ADDCC:
2369                 case CEE_ADD:
2370                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2371                         break;
2372                 case OP_ADC:
2373                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2374                         break;
2375                 case OP_ADD_IMM:
2376                         g_assert (amd64_is_imm32 (ins->inst_imm));
2377                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2378                         break;
2379                 case OP_ADC_IMM:
2380                         g_assert (amd64_is_imm32 (ins->inst_imm));
2381                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2382                         break;
2383                 case OP_SUBCC:
2384                 case CEE_SUB:
2385                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2386                         break;
2387                 case OP_SBB:
2388                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2389                         break;
2390                 case OP_SUB_IMM:
2391                         g_assert (amd64_is_imm32 (ins->inst_imm));
2392                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2393                         break;
2394                 case OP_SBB_IMM:
2395                         g_assert (amd64_is_imm32 (ins->inst_imm));
2396                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2397                         break;
2398                 case CEE_AND:
2399                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2400                         break;
2401                 case OP_AND_IMM:
2402                         g_assert (amd64_is_imm32 (ins->inst_imm));
2403                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2404                         break;
2405                 case CEE_MUL:
2406                 case OP_LMUL:
2407                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_MUL_IMM:
2410                 case OP_LMUL_IMM:
2411                 case OP_IMUL_IMM: {
2412                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2413
2414                         switch (ins->inst_imm) {
2415                         case 2:
2416                                 /* MOV r1, r2 */
2417                                 /* ADD r1, r1 */
2418                                 if (ins->dreg != ins->sreg1)
2419                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2420                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2421                                 break;
2422                         case 3:
2423                                 /* LEA r1, [r2 + r2*2] */
2424                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2425                                 break;
2426                         case 5:
2427                                 /* LEA r1, [r2 + r2*4] */
2428                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2429                                 break;
2430                         case 6:
2431                                 /* LEA r1, [r2 + r2*2] */
2432                                 /* ADD r1, r1          */
2433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2434                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2435                                 break;
2436                         case 9:
2437                                 /* LEA r1, [r2 + r2*8] */
2438                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2439                                 break;
2440                         case 10:
2441                                 /* LEA r1, [r2 + r2*4] */
2442                                 /* ADD r1, r1          */
2443                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2444                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2445                                 break;
2446                         case 12:
2447                                 /* LEA r1, [r2 + r2*2] */
2448                                 /* SHL r1, 2           */
2449                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2450                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2451                                 break;
2452                         case 25:
2453                                 /* LEA r1, [r2 + r2*4] */
2454                                 /* LEA r1, [r1 + r1*4] */
2455                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2456                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2457                                 break;
2458                         case 100:
2459                                 /* LEA r1, [r2 + r2*4] */
2460                                 /* SHL r1, 2           */
2461                                 /* LEA r1, [r1 + r1*4] */
2462                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2463                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2464                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2465                                 break;
2466                         default:
2467                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2468                                 break;
2469                         }
2470                         break;
2471                 }
2472                 case CEE_DIV:
2473                 case OP_LDIV:
2474                         amd64_cdq (code);
2475                         amd64_div_reg (code, ins->sreg2, TRUE);
2476                         break;
2477                 case CEE_DIV_UN:
2478                 case OP_LDIV_UN:
2479                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2480                         amd64_div_reg (code, ins->sreg2, FALSE);
2481                         break;
2482                 case CEE_REM:
2483                 case OP_LREM:
2484                         amd64_cdq (code);
2485                         amd64_div_reg (code, ins->sreg2, TRUE);
2486                         break;
2487                 case CEE_REM_UN:
2488                 case OP_LREM_UN:
2489                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2490                         amd64_div_reg (code, ins->sreg2, FALSE);
2491                         break;
2492                 case OP_LMUL_OVF:
2493                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2494                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2495                         break;
2496                 case CEE_OR:
2497                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2498                         break;
2499                 case OP_OR_IMM
2500 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2501                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2502                         break;
2503                 case CEE_XOR:
2504                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2505                         break;
2506                 case OP_XOR_IMM:
2507                         g_assert (amd64_is_imm32 (ins->inst_imm));
2508                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2509                         break;
2510                 case CEE_SHL:
2511                 case OP_LSHL:
2512                         g_assert (ins->sreg2 == AMD64_RCX);
2513                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2514                         break;
2515                 case CEE_SHR:
2516                 case OP_LSHR:
2517                         g_assert (ins->sreg2 == AMD64_RCX);
2518                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2519                         break;
2520                 case OP_SHR_IMM:
2521                         g_assert (amd64_is_imm32 (ins->inst_imm));
2522                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2523                         break;
2524                 case OP_LSHR_IMM:
2525                         g_assert (amd64_is_imm32 (ins->inst_imm));
2526                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2527                         break;
2528                 case OP_SHR_UN_IMM:
2529                         g_assert (amd64_is_imm32 (ins->inst_imm));
2530                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2531                         break;
2532                 case OP_LSHR_UN_IMM:
2533                         g_assert (amd64_is_imm32 (ins->inst_imm));
2534                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2535                         break;
2536                 case CEE_SHR_UN:
2537                         g_assert (ins->sreg2 == AMD64_RCX);
2538                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2539                         break;
2540                 case OP_LSHR_UN:
2541                         g_assert (ins->sreg2 == AMD64_RCX);
2542                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2543                         break;
2544                 case OP_SHL_IMM:
2545                         g_assert (amd64_is_imm32 (ins->inst_imm));
2546                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2547                         break;
2548                 case OP_LSHL_IMM:
2549                         g_assert (amd64_is_imm32 (ins->inst_imm));
2550                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2551                         break;
2552
2553                 case OP_IADDCC:
2554                 case OP_IADD:
2555                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2556                         break;
2557                 case OP_IADC:
2558                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2559                         break;
2560                 case OP_IADD_IMM:
2561                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2562                         break;
2563                 case OP_IADC_IMM:
2564                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2565                         break;
2566                 case OP_ISUBCC:
2567                 case OP_ISUB:
2568                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2569                         break;
2570                 case OP_ISBB:
2571                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2572                         break;
2573                 case OP_ISUB_IMM:
2574                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2575                         break;
2576                 case OP_ISBB_IMM:
2577                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2578                         break;
2579                 case OP_IAND:
2580                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2581                         break;
2582                 case OP_IAND_IMM:
2583                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2584                         break;
2585                 case OP_IOR:
2586                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2587                         break;
2588                 case OP_IOR_IMM:
2589                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2590                         break;
2591                 case OP_IXOR:
2592                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2593                         break;
2594                 case OP_IXOR_IMM:
2595                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2596                         break;
2597                 case OP_INEG:
2598                         amd64_neg_reg_size (code, ins->sreg1, 4);
2599                         break;
2600                 case OP_INOT:
2601                         amd64_not_reg_size (code, ins->sreg1, 4);
2602                         break;
2603                 case OP_ISHL:
2604                         g_assert (ins->sreg2 == AMD64_RCX);
2605                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2606                         break;
2607                 case OP_ISHR:
2608                         g_assert (ins->sreg2 == AMD64_RCX);
2609                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2610                         break;
2611                 case OP_ISHR_IMM:
2612                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2613                         break;
2614                 case OP_ISHR_UN_IMM:
2615                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2616                         break;
2617                 case OP_ISHR_UN:
2618                         g_assert (ins->sreg2 == AMD64_RCX);
2619                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2620                         break;
2621                 case OP_ISHL_IMM:
2622                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2623                         break;
2624                 case OP_IMUL:
2625                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2626                         break;
2627                 case OP_IMUL_OVF:
2628                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2629                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2630                         break;
2631                 case OP_IMUL_OVF_UN:
2632                 case OP_LMUL_OVF_UN: {
2633                         /* the mul operation and the exception check should most likely be split */
2634                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2635                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2636                         /*g_assert (ins->sreg2 == X86_EAX);
2637                         g_assert (ins->dreg == X86_EAX);*/
2638                         if (ins->sreg2 == X86_EAX) {
2639                                 non_eax_reg = ins->sreg1;
2640                         } else if (ins->sreg1 == X86_EAX) {
2641                                 non_eax_reg = ins->sreg2;
2642                         } else {
2643                                 /* no need to save since we're going to store to it anyway */
2644                                 if (ins->dreg != X86_EAX) {
2645                                         saved_eax = TRUE;
2646                                         amd64_push_reg (code, X86_EAX);
2647                                 }
2648                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2649                                 non_eax_reg = ins->sreg2;
2650                         }
2651                         if (ins->dreg == X86_EDX) {
2652                                 if (!saved_eax) {
2653                                         saved_eax = TRUE;
2654                                         amd64_push_reg (code, X86_EAX);
2655                                 }
2656                         } else {
2657                                 saved_edx = TRUE;
2658                                 amd64_push_reg (code, X86_EDX);
2659                         }
2660                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2661                         /* save before the check since pop and mov don't change the flags */
2662                         if (ins->dreg != X86_EAX)
2663                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2664                         if (saved_edx)
2665                                 amd64_pop_reg (code, X86_EDX);
2666                         if (saved_eax)
2667                                 amd64_pop_reg (code, X86_EAX);
2668                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2669                         break;
2670                 }
2671                 case OP_IDIV:
2672                         amd64_cdq_size (code, 4);
2673                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2674                         break;
2675                 case OP_IDIV_UN:
2676                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2677                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2678                         break;
2679                 case OP_IREM:
2680                         amd64_cdq_size (code, 4);
2681                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2682                         break;
2683                 case OP_IREM_UN:
2684                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2685                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2686                         break;
2687                 case OP_ICOMPARE:
2688                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2689                         break;
2690                 case OP_ICOMPARE_IMM:
2691                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2692                         break;
2693                 case OP_IBEQ:
2694                 case OP_IBLT:
2695                 case OP_IBGT:
2696                 case OP_IBGE:
2697                 case OP_IBLE:
2698                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2699                         break;
2700                 case OP_IBNE_UN:
2701                 case OP_IBLT_UN:
2702                 case OP_IBGT_UN:
2703                 case OP_IBGE_UN:
2704                 case OP_IBLE_UN:
2705                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2706                         break;
2707                 case OP_COND_EXC_IOV:
2708                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2709                                                                                 TRUE, ins->inst_p1);
2710                         break;
2711                 case OP_COND_EXC_IC:
2712                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2713                                                                                 FALSE, ins->inst_p1);
2714                         break;
2715                 case CEE_NOT:
2716                         amd64_not_reg (code, ins->sreg1);
2717                         break;
2718                 case CEE_NEG:
2719                         amd64_neg_reg (code, ins->sreg1);
2720                         break;
2721                 case OP_SEXT_I1:
2722                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2723                         break;
2724                 case OP_SEXT_I2:
2725                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2726                         break;
2727                 case OP_SEXT_I4:
2728                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2729                         break;
2730                 case OP_ICONST:
2731                 case OP_I8CONST:
2732                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2733                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2734                         else
2735                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2736                         break;
2737                 case OP_AOTCONST:
2738                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2739                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2740                         break;
2741                 case CEE_CONV_I4:
2742                 case CEE_CONV_U4:
2743                 case OP_MOVE:
2744                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2745                         break;
2746                 case OP_AMD64_SET_XMMREG_R4: {
2747                         if (use_sse2) {
2748                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2749                         }
2750                         else {
2751                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2752                                 /* ins->dreg is set to -1 by the reg allocator */
2753                                 amd64_movss_reg_membase (code, ins->unused, AMD64_RSP, -8);
2754                         }
2755                         break;
2756                 }
2757                 case OP_AMD64_SET_XMMREG_R8: {
2758                         if (use_sse2) {
2759                                 if (ins->dreg != ins->sreg1)
2760                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2761                         }
2762                         else {
2763                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2764                                 /* ins->dreg is set to -1 by the reg allocator */
2765                                 amd64_movsd_reg_membase (code, ins->unused, AMD64_RSP, -8);
2766                         }
2767                         break;
2768                 }
2769                 case CEE_JMP: {
2770                         /*
2771                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2772                          * Keep in sync with the code in emit_epilog.
2773                          */
2774                         int pos = 0, i;
2775
2776                         /* FIXME: no tracing support... */
2777                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2778                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2779
2780                         g_assert (!cfg->method->save_lmf);
2781
2782                         code = emit_load_volatile_arguments (cfg, code);
2783
2784                         if (cfg->arch.omit_fp) {
2785                                 guint32 save_offset = 0;
2786                                 /* Pop callee-saved registers */
2787                                 for (i = 0; i < AMD64_NREG; ++i)
2788                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2789                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2790                                                 save_offset += 8;
2791                                         }
2792                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2793                         }
2794                         else {
2795                                 for (i = 0; i < AMD64_NREG; ++i)
2796                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2797                                                 pos -= sizeof (gpointer);
2798
2799                                 if (pos)
2800                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2801
2802                                 /* Pop registers in reverse order */
2803                                 for (i = AMD64_NREG - 1; i > 0; --i)
2804                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2805                                                 amd64_pop_reg (code, i);
2806                                         }
2807
2808                                 amd64_leave (code);
2809                         }
2810
2811                         offset = code - cfg->native_code;
2812                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2813                         if (cfg->compile_aot)
2814                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2815                         else
2816                                 amd64_set_reg_template (code, AMD64_R11);
2817                         amd64_jump_reg (code, AMD64_R11);
2818                         break;
2819                 }
2820                 case OP_CHECK_THIS:
2821                         /* ensure ins->sreg1 is not NULL */
2822                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2823                         break;
2824                 case OP_ARGLIST: {
2825                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2826                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2827                         break;
2828                 }
2829                 case OP_FCALL:
2830                 case OP_LCALL:
2831                 case OP_VCALL:
2832                 case OP_VOIDCALL:
2833                 case CEE_CALL:
2834                         call = (MonoCallInst*)ins;
2835                         /*
2836                          * The AMD64 ABI forces callers to know about varargs.
2837                          */
2838                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2839                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2840                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2841                                 /*
2842                                  * Since the unmanaged calling convention doesn't contain a
2843                                  * 'vararg' entry, we have to treat every pinvoke call as a
2844                                  * potential vararg call.
2845                                  */
2846                                 guint32 nregs, i;
2847                                 nregs = 0;
2848                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2849                                         if (call->used_fregs & (1 << i))
2850                                                 nregs ++;
2851                                 if (!nregs)
2852                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2853                                 else
2854                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2855                         }
2856
2857                         if (ins->flags & MONO_INST_HAS_METHOD)
2858                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2859                         else
2860                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2861                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2862                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2863                         code = emit_move_return_value (cfg, ins, code);
2864                         break;
2865                 case OP_FCALL_REG:
2866                 case OP_LCALL_REG:
2867                 case OP_VCALL_REG:
2868                 case OP_VOIDCALL_REG:
2869                 case OP_CALL_REG:
2870                         call = (MonoCallInst*)ins;
2871
2872                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2873                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2874                                 ins->sreg1 = AMD64_R11;
2875                         }
2876
2877                         /*
2878                          * The AMD64 ABI forces callers to know about varargs.
2879                          */
2880                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2881                                 if (ins->sreg1 == AMD64_RAX) {
2882                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2883                                         ins->sreg1 = AMD64_R11;
2884                                 }
2885                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2886                         }
2887                         amd64_call_reg (code, ins->sreg1);
2888                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2889                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2890                         code = emit_move_return_value (cfg, ins, code);
2891                         break;
2892                 case OP_FCALL_MEMBASE:
2893                 case OP_LCALL_MEMBASE:
2894                 case OP_VCALL_MEMBASE:
2895                 case OP_VOIDCALL_MEMBASE:
2896                 case OP_CALL_MEMBASE:
2897                         call = (MonoCallInst*)ins;
2898
2899                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2900                                 /*
2901                                  * Can't use R11 because it is clobbered by the trampoline
2902                                  * code, and the reg value is needed by get_vcall_slot_addr.
2903                                  */
2904                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
2905                                 ins->sreg1 = AMD64_RAX;
2906                         }
2907
2908                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
2909                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2910                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2911                         code = emit_move_return_value (cfg, ins, code);
2912                         break;
2913                 case OP_OUTARG:
2914                 case OP_X86_PUSH:
2915                         amd64_push_reg (code, ins->sreg1);
2916                         break;
2917                 case OP_X86_PUSH_IMM:
2918                         g_assert (amd64_is_imm32 (ins->inst_imm));
2919                         amd64_push_imm (code, ins->inst_imm);
2920                         break;
2921                 case OP_X86_PUSH_MEMBASE:
2922                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
2923                         break;
2924                 case OP_X86_PUSH_OBJ:
2925                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
2926                         amd64_push_reg (code, AMD64_RDI);
2927                         amd64_push_reg (code, AMD64_RSI);
2928                         amd64_push_reg (code, AMD64_RCX);
2929                         if (ins->inst_offset)
2930                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
2931                         else
2932                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
2933                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
2934                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
2935                         amd64_cld (code);
2936                         amd64_prefix (code, X86_REP_PREFIX);
2937                         amd64_movsd (code);
2938                         amd64_pop_reg (code, AMD64_RCX);
2939                         amd64_pop_reg (code, AMD64_RSI);
2940                         amd64_pop_reg (code, AMD64_RDI);
2941                         break;
2942                 case OP_X86_LEA:
2943                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2944                         break;
2945                 case OP_X86_LEA_MEMBASE:
2946                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2947                         break;
2948                 case OP_X86_XCHG:
2949                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2950                         break;
2951                 case OP_LOCALLOC:
2952                         /* keep alignment */
2953                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2954                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2955                         code = mono_emit_stack_alloc (code, ins);
2956                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
2957                         break;
2958                 case CEE_RET:
2959                         amd64_ret (code);
2960                         break;
2961                 case CEE_THROW: {
2962                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
2963                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2964                                              (gpointer)"mono_arch_throw_exception");
2965                         break;
2966                 }
2967                 case OP_RETHROW: {
2968                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
2969                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2970                                              (gpointer)"mono_arch_rethrow_exception");
2971                         break;
2972                 }
2973                 case OP_CALL_HANDLER:
2974                         /* Align stack */
2975                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
2976                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2977                         amd64_call_imm (code, 0);
2978                         /* Restore stack alignment */
2979                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2980                         break;
2981                 case OP_LABEL:
2982                         ins->inst_c0 = code - cfg->native_code;
2983                         break;
2984                 case CEE_BR:
2985                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2986                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2987                         //break;
2988                         if (ins->flags & MONO_INST_BRLABEL) {
2989                                 if (ins->inst_i0->inst_c0) {
2990                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2991                                 } else {
2992                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2993                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
2994                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
2995                                                 x86_jump8 (code, 0);
2996                                         else
2997                                                 x86_jump32 (code, 0);
2998                                 }
2999                         } else {
3000                                 if (ins->inst_target_bb->native_offset) {
3001                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3002                                 } else {
3003                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3004                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3005                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3006                                                 x86_jump8 (code, 0);
3007                                         else
3008                                                 x86_jump32 (code, 0);
3009                                 }
3010                         }
3011                         break;
3012                 case OP_BR_REG:
3013                         amd64_jump_reg (code, ins->sreg1);
3014                         break;
3015                 case OP_CEQ:
3016                 case OP_ICEQ:
3017                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3018                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3019                         break;
3020                 case OP_CLT:
3021                 case OP_ICLT:
3022                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3023                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3024                         break;
3025                 case OP_CLT_UN:
3026                 case OP_ICLT_UN:
3027                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3028                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3029                         break;
3030                 case OP_CGT:
3031                 case OP_ICGT:
3032                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3033                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3034                         break;
3035                 case OP_CGT_UN:
3036                 case OP_ICGT_UN:
3037                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3038                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3039                         break;
3040                 case OP_COND_EXC_EQ:
3041                 case OP_COND_EXC_NE_UN:
3042                 case OP_COND_EXC_LT:
3043                 case OP_COND_EXC_LT_UN:
3044                 case OP_COND_EXC_GT:
3045                 case OP_COND_EXC_GT_UN:
3046                 case OP_COND_EXC_GE:
3047                 case OP_COND_EXC_GE_UN:
3048                 case OP_COND_EXC_LE:
3049                 case OP_COND_EXC_LE_UN:
3050                 case OP_COND_EXC_OV:
3051                 case OP_COND_EXC_NO:
3052                 case OP_COND_EXC_C:
3053                 case OP_COND_EXC_NC:
3054                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3055                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3056                         break;
3057                 case CEE_BEQ:
3058                 case CEE_BNE_UN:
3059                 case CEE_BLT:
3060                 case CEE_BLT_UN:
3061                 case CEE_BGT:
3062                 case CEE_BGT_UN:
3063                 case CEE_BGE:
3064                 case CEE_BGE_UN:
3065                 case CEE_BLE:
3066                 case CEE_BLE_UN:
3067                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3068                         break;
3069
3070                 /* floating point opcodes */
3071                 case OP_R8CONST: {
3072                         double d = *(double *)ins->inst_p0;
3073
3074                         if (use_sse2) {
3075                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3076                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3077                                 }
3078                                 else {
3079                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3080                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3081                                 }
3082                         }
3083                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3084                                 amd64_fldz (code);
3085                         } else if (d == 1.0) {
3086                                 x86_fld1 (code);
3087                         } else {
3088                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3089                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3090                         }
3091                         break;
3092                 }
3093                 case OP_R4CONST: {
3094                         float f = *(float *)ins->inst_p0;
3095
3096                         if (use_sse2) {
3097                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3098                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3099                                 }
3100                                 else {
3101                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3102                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3103                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3104                                 }
3105                         }
3106                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3107                                 amd64_fldz (code);
3108                         } else if (f == 1.0) {
3109                                 x86_fld1 (code);
3110                         } else {
3111                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3112                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3113                         }
3114                         break;
3115                 }
3116                 case OP_STORER8_MEMBASE_REG:
3117                         if (use_sse2)
3118                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3119                         else
3120                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3121                         break;
3122                 case OP_LOADR8_SPILL_MEMBASE:
3123                         if (use_sse2)
3124                                 g_assert_not_reached ();
3125                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3126                         amd64_fxch (code, 1);
3127                         break;
3128                 case OP_LOADR8_MEMBASE:
3129                         if (use_sse2)
3130                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3131                         else
3132                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3133                         break;
3134                 case OP_STORER4_MEMBASE_REG:
3135                         if (use_sse2) {
3136                                 /* This requires a double->single conversion */
3137                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3138                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3139                         }
3140                         else
3141                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3142                         break;
3143                 case OP_LOADR4_MEMBASE:
3144                         if (use_sse2) {
3145                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3146                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3147                         }
3148                         else
3149                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3150                         break;
3151                 case CEE_CONV_R4: /* FIXME: change precision */
3152                 case CEE_CONV_R8:
3153                         if (use_sse2)
3154                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3155                         else {
3156                                 amd64_push_reg (code, ins->sreg1);
3157                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3158                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3159                         }
3160                         break;
3161                 case CEE_CONV_R_UN:
3162                         /* Emulated */
3163                         g_assert_not_reached ();
3164                         break;
3165                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3166                 case OP_LCONV_TO_R8:
3167                         if (use_sse2)
3168                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3169                         else {
3170                                 amd64_push_reg (code, ins->sreg1);
3171                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3172                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3173                         }
3174                         break;
3175                 case OP_X86_FP_LOAD_I8:
3176                         if (use_sse2)
3177                                 g_assert_not_reached ();
3178                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3179                         break;
3180                 case OP_X86_FP_LOAD_I4:
3181                         if (use_sse2)
3182                                 g_assert_not_reached ();
3183                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3184                         break;
3185                 case OP_FCONV_TO_I1:
3186                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3187                         break;
3188                 case OP_FCONV_TO_U1:
3189                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3190                         break;
3191                 case OP_FCONV_TO_I2:
3192                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3193                         break;
3194                 case OP_FCONV_TO_U2:
3195                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3196                         break;
3197                 case OP_FCONV_TO_I4:
3198                 case OP_FCONV_TO_I:
3199                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3200                         break;
3201                 case OP_FCONV_TO_I8:
3202                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3203                         break;
3204                 case OP_LCONV_TO_R_UN: {
3205                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3206                         guint8 *br;
3207
3208                         if (use_sse2)
3209                                 g_assert_not_reached ();
3210
3211                         /* load 64bit integer to FP stack */
3212                         amd64_push_imm (code, 0);
3213                         amd64_push_reg (code, ins->sreg2);
3214                         amd64_push_reg (code, ins->sreg1);
3215                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3216                         /* store as 80bit FP value */
3217                         x86_fst80_membase (code, AMD64_RSP, 0);
3218
3219                         /* test if lreg is negative */
3220                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3221                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3222
3223                         /* add correction constant mn */
3224                         x86_fld80_mem (code, mn);
3225                         x86_fld80_membase (code, AMD64_RSP, 0);
3226                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3227                         x86_fst80_membase (code, AMD64_RSP, 0);
3228
3229                         amd64_patch (br, code);
3230
3231                         x86_fld80_membase (code, AMD64_RSP, 0);
3232                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3233
3234                         break;
3235                 }
3236                 case CEE_CONV_OVF_U4:
3237                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3238                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3239                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3240                         break;
3241                 case CEE_CONV_OVF_I4_UN:
3242                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3243                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3244                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3245                         break;
3246                 case OP_FMOVE:
3247                         if (use_sse2 && (ins->dreg != ins->sreg1))
3248                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3249                         break;
3250                 case OP_FADD:
3251                         if (use_sse2)
3252                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3253                         else
3254                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3255                         break;
3256                 case OP_FSUB:
3257                         if (use_sse2)
3258                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3259                         else
3260                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3261                         break;
3262                 case OP_FMUL:
3263                         if (use_sse2)
3264                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3265                         else
3266                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3267                         break;
3268                 case OP_FDIV:
3269                         if (use_sse2)
3270                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3271                         else
3272                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3273                         break;
3274                 case OP_FNEG:
3275                         if (use_sse2) {
3276                                 amd64_mov_reg_imm_size (code, AMD64_R11, 0x8000000000000000, 8);
3277                                 amd64_push_reg (code, AMD64_R11);
3278                                 amd64_push_reg (code, AMD64_R11);
3279                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RSP, 0);
3280                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3281                         }
3282                         else
3283                                 amd64_fchs (code);
3284                         break;
3285                 case OP_SIN:
3286                         if (use_sse2) {
3287                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3288                         }
3289                         else {
3290                                 amd64_fsin (code);
3291                                 amd64_fldz (code);
3292                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3293                         }
3294                         break;
3295                 case OP_COS:
3296                         if (use_sse2) {
3297                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3298                         }
3299                         else {
3300                                 amd64_fcos (code);
3301                                 amd64_fldz (code);
3302                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3303                         }
3304                         break;
3305                 case OP_ABS:
3306                         if (use_sse2) {
3307                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3308                         }
3309                         else
3310                                 amd64_fabs (code);
3311                         break;
3312                 case OP_TAN: {
3313                         /*
3314                          * it really doesn't make sense to inline all this code,
3315                          * it's here just to show that things may not be as simple
3316                          * as they appear.
3317                          */
3318                         guchar *check_pos, *end_tan, *pop_jump;
3319                         if (use_sse2)
3320                                 g_assert_not_reached ();
3321                         amd64_push_reg (code, AMD64_RAX);
3322                         amd64_fptan (code);
3323                         amd64_fnstsw (code);
3324                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3325                         check_pos = code;
3326                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3327                         amd64_fstp (code, 0); /* pop the 1.0 */
3328                         end_tan = code;
3329                         x86_jump8 (code, 0);
3330                         amd64_fldpi (code);
3331                         amd64_fp_op (code, X86_FADD, 0);
3332                         amd64_fxch (code, 1);
3333                         x86_fprem1 (code);
3334                         amd64_fstsw (code);
3335                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3336                         pop_jump = code;
3337                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3338                         amd64_fstp (code, 1);
3339                         amd64_fptan (code);
3340                         amd64_patch (pop_jump, code);
3341                         amd64_fstp (code, 0); /* pop the 1.0 */
3342                         amd64_patch (check_pos, code);
3343                         amd64_patch (end_tan, code);
3344                         amd64_fldz (code);
3345                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3346                         amd64_pop_reg (code, AMD64_RAX);
3347                         break;
3348                 }
3349                 case OP_ATAN:
3350                         if (use_sse2)
3351                                 g_assert_not_reached ();
3352                         x86_fld1 (code);
3353                         amd64_fpatan (code);
3354                         amd64_fldz (code);
3355                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3356                         break;
3357                 case OP_SQRT:
3358                         if (use_sse2) {
3359                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3360                         }
3361                         else
3362                                 amd64_fsqrt (code);
3363                         break;
3364                 case OP_X86_FPOP:
3365                         if (!use_sse2)
3366                                 amd64_fstp (code, 0);
3367                         break;
3368                 case OP_FREM: {
3369                         guint8 *l1, *l2;
3370
3371                         if (use_sse2)
3372                                 g_assert_not_reached ();
3373                         amd64_push_reg (code, AMD64_RAX);
3374                         /* we need to exchange ST(0) with ST(1) */
3375                         amd64_fxch (code, 1);
3376
3377                         /* this requires a loop, because fprem somtimes
3378                          * returns a partial remainder */
3379                         l1 = code;
3380                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3381                         /* x86_fprem1 (code); */
3382                         amd64_fprem (code);
3383                         amd64_fnstsw (code);
3384                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3385                         l2 = code + 2;
3386                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3387
3388                         /* pop result */
3389                         amd64_fstp (code, 1);
3390
3391                         amd64_pop_reg (code, AMD64_RAX);
3392                         break;
3393                 }
3394                 case OP_FCOMPARE:
3395                         if (use_sse2) {
3396                                 /*
3397                                  * The two arguments are swapped because the fbranch instructions
3398                                  * depend on this for the non-sse case to work.
3399                                  */
3400                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3401                                 break;
3402                         }
3403                         if (cfg->opt & MONO_OPT_FCMOV) {
3404                                 amd64_fcomip (code, 1);
3405                                 amd64_fstp (code, 0);
3406                                 break;
3407                         }
3408                         /* this overwrites EAX */
3409                         EMIT_FPCOMPARE(code);
3410                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3411                         break;
3412                 case OP_FCEQ:
3413                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3414                                 /* zeroing the register at the start results in
3415                                  * shorter and faster code (we can also remove the widening op)
3416                                  */
3417                                 guchar *unordered_check;
3418                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3419
3420                                 if (use_sse2)
3421                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3422                                 else {
3423                                         amd64_fcomip (code, 1);
3424                                         amd64_fstp (code, 0);
3425                                 }
3426                                 unordered_check = code;
3427                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3428                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3429                                 amd64_patch (unordered_check, code);
3430                                 break;
3431                         }
3432                         if (ins->dreg != AMD64_RAX)
3433                                 amd64_push_reg (code, AMD64_RAX);
3434
3435                         EMIT_FPCOMPARE(code);
3436                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3437                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3438                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3439                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3440
3441                         if (ins->dreg != AMD64_RAX)
3442                                 amd64_pop_reg (code, AMD64_RAX);
3443                         break;
3444                 case OP_FCLT:
3445                 case OP_FCLT_UN:
3446                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3447                                 /* zeroing the register at the start results in
3448                                  * shorter and faster code (we can also remove the widening op)
3449                                  */
3450                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3451                                 if (use_sse2)
3452                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3453                                 else {
3454                                         amd64_fcomip (code, 1);
3455                                         amd64_fstp (code, 0);
3456                                 }
3457                                 if (ins->opcode == OP_FCLT_UN) {
3458                                         guchar *unordered_check = code;
3459                                         guchar *jump_to_end;
3460                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3461                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3462                                         jump_to_end = code;
3463                                         x86_jump8 (code, 0);
3464                                         amd64_patch (unordered_check, code);
3465                                         amd64_inc_reg (code, ins->dreg);
3466                                         amd64_patch (jump_to_end, code);
3467                                 } else {
3468                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3469                                 }
3470                                 break;
3471                         }
3472                         if (ins->dreg != AMD64_RAX)
3473                                 amd64_push_reg (code, AMD64_RAX);
3474
3475                         EMIT_FPCOMPARE(code);
3476                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3477                         if (ins->opcode == OP_FCLT_UN) {
3478                                 guchar *is_not_zero_check, *end_jump;
3479                                 is_not_zero_check = code;
3480                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3481                                 end_jump = code;
3482                                 x86_jump8 (code, 0);
3483                                 amd64_patch (is_not_zero_check, code);
3484                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3485
3486                                 amd64_patch (end_jump, code);
3487                         }
3488                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3489                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3490
3491                         if (ins->dreg != AMD64_RAX)
3492                                 amd64_pop_reg (code, AMD64_RAX);
3493                         break;
3494                 case OP_FCGT:
3495                 case OP_FCGT_UN:
3496                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3497                                 /* zeroing the register at the start results in
3498                                  * shorter and faster code (we can also remove the widening op)
3499                                  */
3500                                 guchar *unordered_check;
3501                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3502                                 if (use_sse2)
3503                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3504                                 else {
3505                                         amd64_fcomip (code, 1);
3506                                         amd64_fstp (code, 0);
3507                                 }
3508                                 if (ins->opcode == OP_FCGT) {
3509                                         unordered_check = code;
3510                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3511                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3512                                         amd64_patch (unordered_check, code);
3513                                 } else {
3514                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3515                                 }
3516                                 break;
3517                         }
3518                         if (ins->dreg != AMD64_RAX)
3519                                 amd64_push_reg (code, AMD64_RAX);
3520
3521                         EMIT_FPCOMPARE(code);
3522                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3523                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3524                         if (ins->opcode == OP_FCGT_UN) {
3525                                 guchar *is_not_zero_check, *end_jump;
3526                                 is_not_zero_check = code;
3527                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3528                                 end_jump = code;
3529                                 x86_jump8 (code, 0);
3530                                 amd64_patch (is_not_zero_check, code);
3531                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3532
3533                                 amd64_patch (end_jump, code);
3534                         }
3535                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3536                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3537
3538                         if (ins->dreg != AMD64_RAX)
3539                                 amd64_pop_reg (code, AMD64_RAX);
3540                         break;
3541                 case OP_FCLT_MEMBASE:
3542                 case OP_FCGT_MEMBASE:
3543                 case OP_FCLT_UN_MEMBASE:
3544                 case OP_FCGT_UN_MEMBASE:
3545                 case OP_FCEQ_MEMBASE: {
3546                         guchar *unordered_check, *jump_to_end;
3547                         int x86_cond;
3548                         g_assert (use_sse2);
3549
3550                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3551                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3552
3553                         switch (ins->opcode) {
3554                         case OP_FCEQ_MEMBASE:
3555                                 x86_cond = X86_CC_EQ;
3556                                 break;
3557                         case OP_FCLT_MEMBASE:
3558                         case OP_FCLT_UN_MEMBASE:
3559                                 x86_cond = X86_CC_LT;
3560                                 break;
3561                         case OP_FCGT_MEMBASE:
3562                         case OP_FCGT_UN_MEMBASE:
3563                                 x86_cond = X86_CC_GT;
3564                                 break;
3565                         default:
3566                                 g_assert_not_reached ();
3567                         }
3568
3569                         unordered_check = code;
3570                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3571                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3572
3573                         switch (ins->opcode) {
3574                         case OP_FCEQ_MEMBASE:
3575                         case OP_FCLT_MEMBASE:
3576                         case OP_FCGT_MEMBASE:
3577                                 amd64_patch (unordered_check, code);
3578                                 break;
3579                         case OP_FCLT_UN_MEMBASE:
3580                         case OP_FCGT_UN_MEMBASE:
3581                                 jump_to_end = code;
3582                                 x86_jump8 (code, 0);
3583                                 amd64_patch (unordered_check, code);
3584                                 amd64_inc_reg (code, ins->dreg);
3585                                 amd64_patch (jump_to_end, code);
3586                                 break;
3587                         default:
3588                                 break;
3589                         }
3590                         break;
3591                 }
3592                 case OP_FBEQ:
3593                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3594                                 guchar *jump = code;
3595                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3596                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3597                                 amd64_patch (jump, code);
3598                                 break;
3599                         }
3600                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3601                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3602                         break;
3603                 case OP_FBNE_UN:
3604                         /* Branch if C013 != 100 */
3605                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3606                                 /* branch if !ZF or (PF|CF) */
3607                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3608                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3609                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3610                                 break;
3611                         }
3612                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3613                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3614                         break;
3615                 case OP_FBLT:
3616                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3617                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3618                                 break;
3619                         }
3620                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3621                         break;
3622                 case OP_FBLT_UN:
3623                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3624                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3625                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3626                                 break;
3627                         }
3628                         if (ins->opcode == OP_FBLT_UN) {
3629                                 guchar *is_not_zero_check, *end_jump;
3630                                 is_not_zero_check = code;
3631                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3632                                 end_jump = code;
3633                                 x86_jump8 (code, 0);
3634                                 amd64_patch (is_not_zero_check, code);
3635                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3636
3637                                 amd64_patch (end_jump, code);
3638                         }
3639                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3640                         break;
3641                 case OP_FBGT:
3642                 case OP_FBGT_UN:
3643                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3644                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3645                                 break;
3646                         }
3647                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3648                         if (ins->opcode == OP_FBGT_UN) {
3649                                 guchar *is_not_zero_check, *end_jump;
3650                                 is_not_zero_check = code;
3651                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3652                                 end_jump = code;
3653                                 x86_jump8 (code, 0);
3654                                 amd64_patch (is_not_zero_check, code);
3655                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3656
3657                                 amd64_patch (end_jump, code);
3658                         }
3659                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3660                         break;
3661                 case OP_FBGE:
3662                         /* Branch if C013 == 100 or 001 */
3663                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3664                                 guchar *br1;
3665
3666                                 /* skip branch if C1=1 */
3667                                 br1 = code;
3668                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3669                                 /* branch if (C0 | C3) = 1 */
3670                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3671                                 amd64_patch (br1, code);
3672                                 break;
3673                         }
3674                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3675                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3676                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3677                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3678                         break;
3679                 case OP_FBGE_UN:
3680                         /* Branch if C013 == 000 */
3681                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3682                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3683                                 break;
3684                         }
3685                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3686                         break;
3687                 case OP_FBLE:
3688                         /* Branch if C013=000 or 100 */
3689                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3690                                 guchar *br1;
3691
3692                                 /* skip branch if C1=1 */
3693                                 br1 = code;
3694                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3695                                 /* branch if C0=0 */
3696                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3697                                 amd64_patch (br1, code);
3698                                 break;
3699                         }
3700                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3701                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3702                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3703                         break;
3704                 case OP_FBLE_UN:
3705                         /* Branch if C013 != 001 */
3706                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3707                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3708                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3709                                 break;
3710                         }
3711                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3712                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3713                         break;
3714                 case CEE_CKFINITE: {
3715                         if (use_sse2) {
3716                                 /* Transfer value to the fp stack */
3717                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3718                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3719                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3720                         }
3721                         amd64_push_reg (code, AMD64_RAX);
3722                         amd64_fxam (code);
3723                         amd64_fnstsw (code);
3724                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3725                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3726                         amd64_pop_reg (code, AMD64_RAX);
3727                         if (use_sse2) {
3728                                 amd64_fstp (code, 0);
3729                         }
3730                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3731                         if (use_sse2)
3732                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3733                         break;
3734                 }
3735                 case OP_TLS_GET: {
3736                         x86_prefix (code, X86_FS_PREFIX);
3737                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_offset, 8);
3738                         break;
3739                 }
3740                 case OP_MEMORY_BARRIER: {
3741                         /* Not needed on amd64 */
3742                         break;
3743                 }
3744                 case OP_ATOMIC_ADD_I4:
3745                 case OP_ATOMIC_ADD_I8: {
3746                         int dreg = ins->dreg;
3747                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3748
3749                         if (dreg == ins->inst_basereg)
3750                                 dreg = AMD64_R11;
3751
3752                         if (dreg != ins->sreg2)
3753                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3754
3755                         x86_prefix (code, X86_LOCK_PREFIX);
3756                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3757
3758                         if (dreg != ins->dreg)
3759                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3760
3761                         break;
3762                 }
3763                 case OP_ATOMIC_ADD_NEW_I4:
3764                 case OP_ATOMIC_ADD_NEW_I8: {
3765                         int dreg = ins->dreg;
3766                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3767
3768                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3769                                 dreg = AMD64_R11;
3770
3771                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3772                         amd64_prefix (code, X86_LOCK_PREFIX);
3773                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3774                         /* dreg contains the old value, add with sreg2 value */
3775                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3776
3777                         if (ins->dreg != dreg)
3778                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3779
3780                         break;
3781                 }
3782                 case OP_ATOMIC_EXCHANGE_I4:
3783                 case OP_ATOMIC_EXCHANGE_I8: {
3784                         guchar *br[2];
3785                         int sreg2 = ins->sreg2;
3786                         int breg = ins->inst_basereg;
3787                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3788
3789                         /*
3790                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3791                          * an explanation of how this works.
3792                          */
3793
3794                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3795                          * hack to overcome limits in x86 reg allocator
3796                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3797                          */
3798                         if (ins->dreg != AMD64_RAX)
3799                                 amd64_push_reg (code, AMD64_RAX);
3800
3801                         /* We need the EAX reg for the cmpxchg */
3802                         if (ins->sreg2 == AMD64_RAX) {
3803                                 amd64_push_reg (code, AMD64_RDX);
3804                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3805                                 sreg2 = AMD64_RDX;
3806                         }
3807
3808                         if (breg == AMD64_RAX) {
3809                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, size);
3810                                 breg = AMD64_R11;
3811                         }
3812
3813                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3814
3815                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3816                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3817                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3818                         amd64_patch (br [1], br [0]);
3819
3820                         if (ins->dreg != AMD64_RAX) {
3821                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3822                                 amd64_pop_reg (code, AMD64_RAX);
3823                         }
3824
3825                         if (ins->sreg2 != sreg2)
3826                                 amd64_pop_reg (code, AMD64_RDX);
3827
3828                         break;
3829                 }
3830                 default:
3831                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3832                         g_assert_not_reached ();
3833                 }
3834
3835                 if ((code - cfg->native_code - offset) > max_len) {
3836                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3837                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3838                         g_assert_not_reached ();
3839                 }
3840
3841                 cpos += max_len;
3842
3843                 last_ins = ins;
3844                 last_offset = offset;
3845
3846                 ins = ins->next;
3847         }
3848
3849         cfg->code_len = code - cfg->native_code;
3850 }
3851
3852 void
3853 mono_arch_register_lowlevel_calls (void)
3854 {
3855 }
3856
3857 void
3858 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3859 {
3860         MonoJumpInfo *patch_info;
3861         gboolean compile_aot = !run_cctors;
3862
3863         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3864                 unsigned char *ip = patch_info->ip.i + code;
3865                 const unsigned char *target;
3866
3867                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3868
3869                 if (compile_aot) {
3870                         switch (patch_info->type) {
3871                         case MONO_PATCH_INFO_BB:
3872                         case MONO_PATCH_INFO_LABEL:
3873                                 break;
3874                         default:
3875                                 /* No need to patch these */
3876                                 continue;
3877                         }
3878                 }
3879
3880                 switch (patch_info->type) {
3881                 case MONO_PATCH_INFO_NONE:
3882                         continue;
3883                 case MONO_PATCH_INFO_CLASS_INIT: {
3884                         /* Might already been changed to a nop */
3885                         guint8* ip2 = ip;
3886                         amd64_call_code (ip2, 0);
3887                         break;
3888                 }
3889                 case MONO_PATCH_INFO_METHOD_REL:
3890                 case MONO_PATCH_INFO_R8:
3891                 case MONO_PATCH_INFO_R4:
3892                         g_assert_not_reached ();
3893                         continue;
3894                 case MONO_PATCH_INFO_BB:
3895                         break;
3896                 default:
3897                         break;
3898                 }
3899                 amd64_patch (ip, (gpointer)target);
3900         }
3901 }
3902
3903 guint8 *
3904 mono_arch_emit_prolog (MonoCompile *cfg)
3905 {
3906         MonoMethod *method = cfg->method;
3907         MonoBasicBlock *bb;
3908         MonoMethodSignature *sig;
3909         MonoInst *inst;
3910         int alloc_size, pos, max_offset, i, quad;
3911         guint8 *code;
3912         CallInfo *cinfo;
3913         gint32 lmf_offset = cfg->arch.lmf_offset;
3914
3915         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
3916         code = cfg->native_code = g_malloc (cfg->code_size);
3917
3918         /* Amount of stack space allocated by register saving code */
3919         pos = 0;
3920
3921         /*
3922          * The prolog consists of the following parts:
3923          * FP present:
3924          * - push rbp, mov rbp, rsp
3925          * - save callee saved regs using pushes
3926          * - allocate frame
3927          * - save lmf if needed
3928          * FP not present:
3929          * - allocate frame
3930          * - save lmf if needed
3931          * - save callee saved regs using moves
3932          */
3933
3934         if (!cfg->arch.omit_fp) {
3935                 amd64_push_reg (code, AMD64_RBP);
3936                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
3937         }
3938
3939         /* Save callee saved registers */
3940         if (!cfg->arch.omit_fp && !method->save_lmf) {
3941                 for (i = 0; i < AMD64_NREG; ++i)
3942                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3943                                 amd64_push_reg (code, i);
3944                                 pos += sizeof (gpointer);
3945                         }
3946         }
3947
3948         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3949
3950         alloc_size -= pos;
3951
3952         if (cfg->arch.omit_fp)
3953                 /*
3954                  * On enter, the stack is misaligned by the the pushing of the return
3955                  * address. It is either made aligned by the pushing of %rbp, or by
3956                  * this.
3957                  */
3958                 alloc_size += 8;
3959
3960         cfg->arch.stack_alloc_size = alloc_size;
3961
3962         /* Allocate stack frame */
3963         if (alloc_size) {
3964                 /* See mono_emit_stack_alloc */
3965 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3966                 guint32 remaining_size = alloc_size;
3967                 while (remaining_size >= 0x1000) {
3968                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3969                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3970                         remaining_size -= 0x1000;
3971                 }
3972                 if (remaining_size)
3973                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
3974 #else
3975                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
3976 #endif
3977         }
3978
3979         /* Stack alignment check */
3980 #if 0
3981         {
3982                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
3983                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
3984                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3985                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
3986                 amd64_breakpoint (code);
3987         }
3988 #endif
3989
3990         /* Save LMF */
3991         if (method->save_lmf) {
3992                 /* Save ip */
3993                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
3994                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
3995                 /* Save fp */
3996                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
3997                 /* Save sp */
3998                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3999                 /* Save method */
4000                 /* FIXME: add a relocation for this */
4001                 if (IS_IMM32 (cfg->method))
4002                         amd64_mov_membase_imm (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), (guint64)cfg->method, 8);
4003                 else {
4004                         amd64_mov_reg_imm (code, AMD64_R11, cfg->method);
4005                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), AMD64_R11, 8);
4006                 }
4007                 /* Save callee saved regs */
4008                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4009                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4010                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4011                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4012                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4013         }
4014
4015         /* Save callee saved registers */
4016         if (cfg->arch.omit_fp && !method->save_lmf) {
4017                 gint32 save_area_offset = 0;
4018
4019                 /* Save caller saved registers after sp is adjusted */
4020                 /* The registers are saved at the bottom of the frame */
4021                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4022                 for (i = 0; i < AMD64_NREG; ++i)
4023                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4024                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4025                                 save_area_offset += 8;
4026                         }
4027         }
4028
4029         /* compute max_offset in order to use short forward jumps */
4030         max_offset = 0;
4031         if (cfg->opt & MONO_OPT_BRANCH) {
4032                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4033                         MonoInst *ins = bb->code;
4034                         bb->max_offset = max_offset;
4035
4036                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4037                                 max_offset += 6;
4038                         /* max alignment for loops */
4039                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4040                                 max_offset += LOOP_ALIGNMENT;
4041
4042                         while (ins) {
4043                                 if (ins->opcode == OP_LABEL)
4044                                         ins->inst_c1 = max_offset;
4045
4046                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
4047                                 ins = ins->next;
4048                         }
4049                 }
4050         }
4051
4052         sig = mono_method_signature (method);
4053         pos = 0;
4054
4055         cinfo = get_call_info (sig, FALSE);
4056
4057         if (sig->ret->type != MONO_TYPE_VOID) {
4058                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4059                         /* Save volatile arguments to the stack */
4060                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4061                 }
4062         }
4063
4064         /* Keep this in sync with emit_load_volatile_arguments */
4065         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4066                 ArgInfo *ainfo = cinfo->args + i;
4067                 gint32 stack_offset;
4068                 MonoType *arg_type;
4069                 inst = cfg->varinfo [i];
4070
4071                 if (sig->hasthis && (i == 0))
4072                         arg_type = &mono_defaults.object_class->byval_arg;
4073                 else
4074                         arg_type = sig->params [i - sig->hasthis];
4075
4076                 stack_offset = ainfo->offset + ARGS_OFFSET;
4077
4078                 /* Save volatile arguments to the stack */
4079                 if (inst->opcode != OP_REGVAR) {
4080                         switch (ainfo->storage) {
4081                         case ArgInIReg: {
4082                                 guint32 size = 8;
4083
4084                                 /* FIXME: I1 etc */
4085                                 /*
4086                                 if (stack_offset & 0x1)
4087                                         size = 1;
4088                                 else if (stack_offset & 0x2)
4089                                         size = 2;
4090                                 else if (stack_offset & 0x4)
4091                                         size = 4;
4092                                 else
4093                                         size = 8;
4094                                 */
4095                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4096                                 break;
4097                         }
4098                         case ArgInFloatSSEReg:
4099                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4100                                 break;
4101                         case ArgInDoubleSSEReg:
4102                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4103                                 break;
4104                         case ArgValuetypeInReg:
4105                                 for (quad = 0; quad < 2; quad ++) {
4106                                         switch (ainfo->pair_storage [quad]) {
4107                                         case ArgInIReg:
4108                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4109                                                 break;
4110                                         case ArgInFloatSSEReg:
4111                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4112                                                 break;
4113                                         case ArgInDoubleSSEReg:
4114                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4115                                                 break;
4116                                         case ArgNone:
4117                                                 break;
4118                                         default:
4119                                                 g_assert_not_reached ();
4120                                         }
4121                                 }
4122                                 break;
4123                         default:
4124                                 break;
4125                         }
4126                 }
4127
4128                 if (inst->opcode == OP_REGVAR) {
4129                         /* Argument allocated to (non-volatile) register */
4130                         switch (ainfo->storage) {
4131                         case ArgInIReg:
4132                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4133                                 break;
4134                         case ArgOnStack:
4135                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4136                                 break;
4137                         default:
4138                                 g_assert_not_reached ();
4139                         }
4140                 }
4141         }
4142
4143         if (method->save_lmf) {
4144                 if (lmf_tls_offset != -1) {
4145                         /* Load lmf quicky using the FS register */
4146                         x86_prefix (code, X86_FS_PREFIX);
4147                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4148                 }
4149                 else {
4150                         /*
4151                          * The call might clobber argument registers, but they are already
4152                          * saved to the stack/global regs.
4153                          */
4154
4155                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4156                                                                  (gpointer)"mono_get_lmf_addr");
4157                 }
4158
4159                 /* Save lmf_addr */
4160                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4161                 /* Save previous_lmf */
4162                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4163                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4164                 /* Set new lmf */
4165                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4166                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4167         }
4168
4169
4170         g_free (cinfo);
4171
4172         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4173                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4174
4175         cfg->code_len = code - cfg->native_code;
4176
4177         g_assert (cfg->code_len < cfg->code_size);
4178
4179         return code;
4180 }
4181
4182 void
4183 mono_arch_emit_epilog (MonoCompile *cfg)
4184 {
4185         MonoMethod *method = cfg->method;
4186         int quad, pos, i;
4187         guint8 *code;
4188         int max_epilog_size = 16;
4189         CallInfo *cinfo;
4190         gint32 lmf_offset = cfg->arch.lmf_offset;
4191
4192         if (cfg->method->save_lmf)
4193                 max_epilog_size += 256;
4194
4195         if (mono_jit_trace_calls != NULL)
4196                 max_epilog_size += 50;
4197
4198         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4199                 max_epilog_size += 50;
4200
4201         max_epilog_size += (AMD64_NREG * 2);
4202
4203         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4204                 cfg->code_size *= 2;
4205                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4206                 mono_jit_stats.code_reallocs++;
4207         }
4208
4209         code = cfg->native_code + cfg->code_len;
4210
4211         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4212                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4213
4214         /* the code restoring the registers must be kept in sync with CEE_JMP */
4215         pos = 0;
4216
4217         if (method->save_lmf) {
4218                 /* Restore previous lmf */
4219                 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4220                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4221                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4222
4223                 /* Restore caller saved regs */
4224                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4225                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4226                 }
4227                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4228                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4229                 }
4230                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4231                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4232                 }
4233                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4234                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4235                 }
4236                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4237                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4238                 }
4239                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4240                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4241                 }
4242         } else {
4243
4244                 if (cfg->arch.omit_fp) {
4245                         gint32 save_area_offset = 0;
4246
4247                         for (i = 0; i < AMD64_NREG; ++i)
4248                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4249                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4250                                         save_area_offset += 8;
4251                                 }
4252                 }
4253                 else {
4254                         for (i = 0; i < AMD64_NREG; ++i)
4255                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4256                                         pos -= sizeof (gpointer);
4257
4258                         if (pos) {
4259                                 if (pos == - sizeof (gpointer)) {
4260                                         /* Only one register, so avoid lea */
4261                                         for (i = AMD64_NREG - 1; i > 0; --i)
4262                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4263                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4264                                                 }
4265                                 }
4266                                 else {
4267                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4268
4269                                         /* Pop registers in reverse order */
4270                                         for (i = AMD64_NREG - 1; i > 0; --i)
4271                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4272                                                         amd64_pop_reg (code, i);
4273                                                 }
4274                                 }
4275                         }
4276                 }
4277         }
4278
4279         /* Load returned vtypes into registers if needed */
4280         cinfo = get_call_info (mono_method_signature (method), FALSE);
4281         if (cinfo->ret.storage == ArgValuetypeInReg) {
4282                 ArgInfo *ainfo = &cinfo->ret;
4283                 MonoInst *inst = cfg->ret;
4284
4285                 for (quad = 0; quad < 2; quad ++) {
4286                         switch (ainfo->pair_storage [quad]) {
4287                         case ArgInIReg:
4288                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4289                                 break;
4290                         case ArgInFloatSSEReg:
4291                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4292                                 break;
4293                         case ArgInDoubleSSEReg:
4294                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4295                                 break;
4296                         case ArgNone:
4297                                 break;
4298                         default:
4299                                 g_assert_not_reached ();
4300                         }
4301                 }
4302         }
4303         g_free (cinfo);
4304
4305         if (cfg->arch.omit_fp) {
4306                 if (cfg->arch.stack_alloc_size)
4307                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4308         } else {
4309                 amd64_leave (code);
4310         }
4311         amd64_ret (code);
4312
4313         cfg->code_len = code - cfg->native_code;
4314
4315         g_assert (cfg->code_len < cfg->code_size);
4316
4317         if (cfg->arch.omit_fp) {
4318                 /*
4319                  * Encode the stack size into used_int_regs so the exception handler
4320                  * can access it.
4321                  */
4322                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4323                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4324         }
4325 }
4326
4327 void
4328 mono_arch_emit_exceptions (MonoCompile *cfg)
4329 {
4330         MonoJumpInfo *patch_info;
4331         int nthrows, i;
4332         guint8 *code;
4333         MonoClass *exc_classes [16];
4334         guint8 *exc_throw_start [16], *exc_throw_end [16];
4335         guint32 code_size = 0;
4336
4337         /* Compute needed space */
4338         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4339                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4340                         code_size += 40;
4341                 if (patch_info->type == MONO_PATCH_INFO_R8)
4342                         code_size += 8 + 7; /* sizeof (double) + alignment */
4343                 if (patch_info->type == MONO_PATCH_INFO_R4)
4344                         code_size += 4 + 7; /* sizeof (float) + alignment */
4345         }
4346
4347         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4348                 cfg->code_size *= 2;
4349                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4350                 mono_jit_stats.code_reallocs++;
4351         }
4352
4353         code = cfg->native_code + cfg->code_len;
4354
4355         /* add code to raise exceptions */
4356         nthrows = 0;
4357         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4358                 switch (patch_info->type) {
4359                 case MONO_PATCH_INFO_EXC: {
4360                         MonoClass *exc_class;
4361                         guint8 *buf, *buf2;
4362                         guint32 throw_ip;
4363
4364                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4365
4366                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4367                         g_assert (exc_class);
4368                         throw_ip = patch_info->ip.i;
4369
4370                         //x86_breakpoint (code);
4371                         /* Find a throw sequence for the same exception class */
4372                         for (i = 0; i < nthrows; ++i)
4373                                 if (exc_classes [i] == exc_class)
4374                                         break;
4375                         if (i < nthrows) {
4376                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4377                                 x86_jump_code (code, exc_throw_start [i]);
4378                                 patch_info->type = MONO_PATCH_INFO_NONE;
4379                         }
4380                         else {
4381                                 buf = code;
4382                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4383                                 buf2 = code;
4384
4385                                 if (nthrows < 16) {
4386                                         exc_classes [nthrows] = exc_class;
4387                                         exc_throw_start [nthrows] = code;
4388                                 }
4389
4390                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4391                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4392                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4393                                 patch_info->ip.i = code - cfg->native_code;
4394
4395                                 if (cfg->compile_aot) {
4396                                         amd64_mov_reg_membase (code, GP_SCRATCH_REG, AMD64_RIP, 0, 8);
4397                                         amd64_call_reg (code, GP_SCRATCH_REG);
4398                                 } else {
4399                                         /* The callee is in memory allocated using the code manager */
4400                                         amd64_call_code (code, 0);
4401                                 }
4402
4403                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4404                                 while (buf < buf2)
4405                                         x86_nop (buf);
4406
4407                                 if (nthrows < 16) {
4408                                         exc_throw_end [nthrows] = code;
4409                                         nthrows ++;
4410                                 }
4411                         }
4412                         break;
4413                 }
4414                 default:
4415                         /* do nothing */
4416                         break;
4417                 }
4418         }
4419
4420         /* Handle relocations with RIP relative addressing */
4421         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4422                 gboolean remove = FALSE;
4423
4424                 switch (patch_info->type) {
4425                 case MONO_PATCH_INFO_R8: {
4426                         guint8 *pos;
4427
4428                         code = (guint8*)ALIGN_TO (code, 8);
4429
4430                         pos = cfg->native_code + patch_info->ip.i;
4431
4432                         *(double*)code = *(double*)patch_info->data.target;
4433
4434                         if (use_sse2)
4435                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4436                         else
4437                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4438                         code += 8;
4439
4440                         remove = TRUE;
4441                         break;
4442                 }
4443                 case MONO_PATCH_INFO_R4: {
4444                         guint8 *pos;
4445
4446                         code = (guint8*)ALIGN_TO (code, 8);
4447
4448                         pos = cfg->native_code + patch_info->ip.i;
4449
4450                         *(float*)code = *(float*)patch_info->data.target;
4451
4452                         if (use_sse2)
4453                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4454                         else
4455                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4456                         code += 4;
4457
4458                         remove = TRUE;
4459                         break;
4460                 }
4461                 default:
4462                         break;
4463                 }
4464
4465                 if (remove) {
4466                         if (patch_info == cfg->patch_info)
4467                                 cfg->patch_info = patch_info->next;
4468                         else {
4469                                 MonoJumpInfo *tmp;
4470
4471                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4472                                         ;
4473                                 tmp->next = patch_info->next;
4474                         }
4475                 }
4476         }
4477
4478         cfg->code_len = code - cfg->native_code;
4479
4480         g_assert (cfg->code_len < cfg->code_size);
4481
4482 }
4483
4484 void*
4485 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4486 {
4487         guchar *code = p;
4488         CallInfo *cinfo = NULL;
4489         MonoMethodSignature *sig;
4490         MonoInst *inst;
4491         int i, n, stack_area = 0;
4492
4493         /* Keep this in sync with mono_arch_get_argument_info */
4494
4495         if (enable_arguments) {
4496                 /* Allocate a new area on the stack and save arguments there */
4497                 sig = mono_method_signature (cfg->method);
4498
4499                 cinfo = get_call_info (sig, FALSE);
4500
4501                 n = sig->param_count + sig->hasthis;
4502
4503                 stack_area = ALIGN_TO (n * 8, 16);
4504
4505                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4506
4507                 for (i = 0; i < n; ++i) {
4508                         inst = cfg->varinfo [i];
4509
4510                         if (inst->opcode == OP_REGVAR)
4511                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4512                         else {
4513                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4514                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4515                         }
4516                 }
4517         }
4518
4519         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4520         amd64_set_reg_template (code, AMD64_RDI);
4521         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4522         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4523
4524         if (enable_arguments) {
4525                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4526
4527                 g_free (cinfo);
4528         }
4529
4530         return code;
4531 }
4532
4533 enum {
4534         SAVE_NONE,
4535         SAVE_STRUCT,
4536         SAVE_EAX,
4537         SAVE_EAX_EDX,
4538         SAVE_XMM
4539 };
4540
4541 void*
4542 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4543 {
4544         guchar *code = p;
4545         int save_mode = SAVE_NONE;
4546         MonoMethod *method = cfg->method;
4547         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4548
4549         switch (rtype) {
4550         case MONO_TYPE_VOID:
4551                 /* special case string .ctor icall */
4552                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4553                         save_mode = SAVE_EAX;
4554                 else
4555                         save_mode = SAVE_NONE;
4556                 break;
4557         case MONO_TYPE_I8:
4558         case MONO_TYPE_U8:
4559                 save_mode = SAVE_EAX;
4560                 break;
4561         case MONO_TYPE_R4:
4562         case MONO_TYPE_R8:
4563                 save_mode = SAVE_XMM;
4564                 break;
4565         case MONO_TYPE_VALUETYPE:
4566                 save_mode = SAVE_STRUCT;
4567                 break;
4568         default:
4569                 save_mode = SAVE_EAX;
4570                 break;
4571         }
4572
4573         /* Save the result and copy it into the proper argument register */
4574         switch (save_mode) {
4575         case SAVE_EAX:
4576                 amd64_push_reg (code, AMD64_RAX);
4577                 /* Align stack */
4578                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4579                 if (enable_arguments)
4580                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4581                 break;
4582         case SAVE_STRUCT:
4583                 /* FIXME: */
4584                 if (enable_arguments)
4585                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4586                 break;
4587         case SAVE_XMM:
4588                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4589                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4590                 /* Align stack */
4591                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4592                 /*
4593                  * The result is already in the proper argument register so no copying
4594                  * needed.
4595                  */
4596                 break;
4597         case SAVE_NONE:
4598                 break;
4599         default:
4600                 g_assert_not_reached ();
4601         }
4602
4603         /* Set %al since this is a varargs call */
4604         if (save_mode == SAVE_XMM)
4605                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4606         else
4607                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4608
4609         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4610         amd64_set_reg_template (code, AMD64_RDI);
4611         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4612
4613         /* Restore result */
4614         switch (save_mode) {
4615         case SAVE_EAX:
4616                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4617                 amd64_pop_reg (code, AMD64_RAX);
4618                 break;
4619         case SAVE_STRUCT:
4620                 /* FIXME: */
4621                 break;
4622         case SAVE_XMM:
4623                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4624                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4625                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4626                 break;
4627         case SAVE_NONE:
4628                 break;
4629         default:
4630                 g_assert_not_reached ();
4631         }
4632
4633         return code;
4634 }
4635
4636 void
4637 mono_arch_flush_icache (guint8 *code, gint size)
4638 {
4639         /* Not needed */
4640 }
4641
4642 void
4643 mono_arch_flush_register_windows (void)
4644 {
4645 }
4646
4647 gboolean
4648 mono_arch_is_inst_imm (gint64 imm)
4649 {
4650         return amd64_is_imm32 (imm);
4651 }
4652
4653 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4654
4655 static int reg_to_ucontext_reg [] = {
4656         REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
4657         REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
4658         REG_RIP
4659 };
4660
4661 /*
4662  * Determine whenever the trap whose info is in SIGINFO is caused by
4663  * integer overflow.
4664  */
4665 gboolean
4666 mono_arch_is_int_overflow (void *sigctx, void *info)
4667 {
4668         ucontext_t *ctx = (ucontext_t*)sigctx;
4669         guint8* rip;
4670         int reg;
4671
4672         rip = (guint8*)ctx->uc_mcontext.gregs [REG_RIP];
4673
4674         if (IS_REX (rip [0])) {
4675                 reg = amd64_rex_b (rip [0]);
4676                 rip ++;
4677         }
4678         else
4679                 reg = 0;
4680
4681         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4682                 /* idiv REG */
4683                 reg += x86_modrm_rm (rip [1]);
4684
4685                 if (ctx->uc_mcontext.gregs [reg_to_ucontext_reg [reg]] == -1)
4686                         return TRUE;
4687         }
4688
4689         return FALSE;
4690 }
4691
4692 guint32
4693 mono_arch_get_patch_offset (guint8 *code)
4694 {
4695         return 3;
4696 }
4697
4698 gpointer*
4699 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4700 {
4701         guint32 reg;
4702         guint32 disp;
4703         guint8 rex = 0;
4704
4705         /* go to the start of the call instruction
4706          *
4707          * address_byte = (m << 6) | (o << 3) | reg
4708          * call opcode: 0xff address_byte displacement
4709          * 0xff m=1,o=2 imm8
4710          * 0xff m=2,o=2 imm32
4711          */
4712         code -= 7;
4713
4714         /*
4715          * A given byte sequence can match more than case here, so we have to be
4716          * really careful about the ordering of the cases. Longer sequences
4717          * come first.
4718          */
4719         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4720                 /* call OFFSET(%rip) */
4721                 disp = *(guint32*)(code + 3);
4722                 return (gpointer*)(code + disp + 7);
4723         }
4724         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4725                 /* call *[reg+disp32] */
4726                 if (IS_REX (code [0]))
4727                         rex = code [0];
4728                 reg = amd64_modrm_rm (code [2]);
4729                 disp = *(guint32*)(code + 3);
4730                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4731         }
4732         else if (code [2] == 0xe8) {
4733                 /* call <ADDR> */
4734                 return NULL;
4735         }
4736         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4737                 /* call *%reg */
4738                 return NULL;
4739         }
4740         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4741                 /* call *[reg+disp8] */
4742                 if (IS_REX (code [3]))
4743                         rex = code [3];
4744                 reg = amd64_modrm_rm (code [5]);
4745                 disp = *(guint8*)(code + 6);
4746                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4747         }
4748         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4749                         /*
4750                          * This is a interface call: should check the above code can't catch it earlier
4751                          * 8b 40 30   mov    0x30(%eax),%eax
4752                          * ff 10      call   *(%eax)
4753                          */
4754                 if (IS_REX (code [4]))
4755                         rex = code [4];
4756                 reg = amd64_modrm_rm (code [6]);
4757                 disp = 0;
4758         }
4759         else
4760                 g_assert_not_reached ();
4761
4762         reg += amd64_rex_b (rex);
4763
4764         /* R11 is clobbered by the trampoline code */
4765         g_assert (reg != AMD64_R11);
4766
4767         return (gpointer)(((guint64)(regs [reg])) + disp);
4768 }
4769
4770 gpointer*
4771 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4772 {
4773         guint32 reg;
4774         guint32 disp;
4775
4776         code -= 10;
4777
4778         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
4779                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
4780                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
4781                 disp = code [6];
4782
4783                 if (reg == AMD64_RAX)
4784                         return NULL;
4785                 else
4786                         return (gpointer*)(((guint64)(regs [reg])) + disp);
4787         }
4788
4789         return NULL;
4790 }
4791
4792 /*
4793  * Support for fast access to the thread-local lmf structure using the GS
4794  * segment register on NPTL + kernel 2.6.x.
4795  */
4796
4797 static gboolean tls_offset_inited = FALSE;
4798
4799 void
4800 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4801 {
4802         if (!tls_offset_inited) {
4803                 tls_offset_inited = TRUE;
4804
4805                 appdomain_tls_offset = mono_domain_get_tls_offset ();
4806                 lmf_tls_offset = mono_get_lmf_tls_offset ();
4807                 thread_tls_offset = mono_thread_get_tls_offset ();
4808         }
4809 }
4810
4811 void
4812 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4813 {
4814 }
4815
4816 void
4817 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
4818 {
4819         MonoCallInst *call = (MonoCallInst*)inst;
4820         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
4821
4822         if (vt_reg != -1) {
4823                 MonoInst *vtarg;
4824
4825                 if (cinfo->ret.storage == ArgValuetypeInReg) {
4826                         /*
4827                          * The valuetype is in RAX:RDX after the call, need to be copied to
4828                          * the stack. Push the address here, so the call instruction can
4829                          * access it.
4830                          */
4831                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
4832                         vtarg->sreg1 = vt_reg;
4833                         mono_bblock_add_inst (cfg->cbb, vtarg);
4834
4835                         /* Align stack */
4836                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
4837                 }
4838                 else {
4839                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
4840                         vtarg->sreg1 = vt_reg;
4841                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
4842                         mono_bblock_add_inst (cfg->cbb, vtarg);
4843
4844                         mono_call_inst_add_outarg_reg (call, vtarg->dreg, cinfo->ret.reg, FALSE);
4845                 }
4846         }
4847
4848         /* add the this argument */
4849         if (this_reg != -1) {
4850                 MonoInst *this;
4851                 MONO_INST_NEW (cfg, this, OP_MOVE);
4852                 this->type = this_type;
4853                 this->sreg1 = this_reg;
4854                 this->dreg = mono_regstate_next_int (cfg->rs);
4855                 mono_bblock_add_inst (cfg->cbb, this);
4856
4857                 mono_call_inst_add_outarg_reg (call, this->dreg, cinfo->args [0].reg, FALSE);
4858         }
4859
4860         g_free (cinfo);
4861 }
4862
4863 MonoInst*
4864 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4865 {
4866         MonoInst *ins = NULL;
4867
4868         if (cmethod->klass == mono_defaults.math_class) {
4869                 if (strcmp (cmethod->name, "Sin") == 0) {
4870                         MONO_INST_NEW (cfg, ins, OP_SIN);
4871                         ins->inst_i0 = args [0];
4872                 } else if (strcmp (cmethod->name, "Cos") == 0) {
4873                         MONO_INST_NEW (cfg, ins, OP_COS);
4874                         ins->inst_i0 = args [0];
4875                 } else if (strcmp (cmethod->name, "Tan") == 0) {
4876                         if (use_sse2)
4877                                 return ins;
4878                         MONO_INST_NEW (cfg, ins, OP_TAN);
4879                         ins->inst_i0 = args [0];
4880                 } else if (strcmp (cmethod->name, "Atan") == 0) {
4881                         if (use_sse2)
4882                                 return ins;
4883                         MONO_INST_NEW (cfg, ins, OP_ATAN);
4884                         ins->inst_i0 = args [0];
4885                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
4886                         MONO_INST_NEW (cfg, ins, OP_SQRT);
4887                         ins->inst_i0 = args [0];
4888                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
4889                         MONO_INST_NEW (cfg, ins, OP_ABS);
4890                         ins->inst_i0 = args [0];
4891                 }
4892 #if 0
4893                 /* OP_FREM is not IEEE compatible */
4894                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
4895                         MONO_INST_NEW (cfg, ins, OP_FREM);
4896                         ins->inst_i0 = args [0];
4897                         ins->inst_i1 = args [1];
4898                 }
4899 #endif
4900         } else if (cmethod->klass == mono_defaults.thread_class &&
4901                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
4902                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
4903         } else if(cmethod->klass->image == mono_defaults.corlib &&
4904                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4905                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4906
4907                 if (strcmp (cmethod->name, "Increment") == 0) {
4908                         MonoInst *ins_iconst;
4909                         guint32 opcode;
4910
4911                         if (fsig->params [0]->type == MONO_TYPE_I4)
4912                                 opcode = OP_ATOMIC_ADD_NEW_I4;
4913                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4914                                 opcode = OP_ATOMIC_ADD_NEW_I8;
4915                         else
4916                                 g_assert_not_reached ();
4917                         MONO_INST_NEW (cfg, ins, opcode);
4918                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
4919                         ins_iconst->inst_c0 = 1;
4920
4921                         ins->inst_i0 = args [0];
4922                         ins->inst_i1 = ins_iconst;
4923                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4924                         MonoInst *ins_iconst;
4925                         guint32 opcode;
4926
4927                         if (fsig->params [0]->type == MONO_TYPE_I4)
4928                                 opcode = OP_ATOMIC_ADD_NEW_I4;
4929                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4930                                 opcode = OP_ATOMIC_ADD_NEW_I8;
4931                         else
4932                                 g_assert_not_reached ();
4933                         MONO_INST_NEW (cfg, ins, opcode);
4934                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
4935                         ins_iconst->inst_c0 = -1;
4936
4937                         ins->inst_i0 = args [0];
4938                         ins->inst_i1 = ins_iconst;
4939                 } else if (strcmp (cmethod->name, "Add") == 0) {
4940                         guint32 opcode;
4941
4942                         if (fsig->params [0]->type == MONO_TYPE_I4)
4943                                 opcode = OP_ATOMIC_ADD_I4;
4944                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4945                                 opcode = OP_ATOMIC_ADD_I8;
4946                         else
4947                                 g_assert_not_reached ();
4948
4949                         MONO_INST_NEW (cfg, ins, opcode);
4950
4951                         ins->inst_i0 = args [0];
4952                         ins->inst_i1 = args [1];
4953                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
4954                         guint32 opcode;
4955
4956                         if (fsig->params [0]->type == MONO_TYPE_I4)
4957                                 opcode = OP_ATOMIC_EXCHANGE_I4;
4958                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
4959                                          (fsig->params [0]->type == MONO_TYPE_I) ||
4960                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
4961                                 opcode = OP_ATOMIC_EXCHANGE_I8;
4962                         else
4963                                 return NULL;
4964
4965                         MONO_INST_NEW (cfg, ins, opcode);
4966
4967                         ins->inst_i0 = args [0];
4968                         ins->inst_i1 = args [1];
4969                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
4970                         /* 64 bit reads are already atomic */
4971                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
4972                         ins->inst_i0 = args [0];
4973                 }
4974
4975                 /*
4976                  * Can't implement CompareExchange methods this way since they have
4977                  * three arguments.
4978                  */
4979         }
4980
4981         return ins;
4982 }
4983
4984 gboolean
4985 mono_arch_print_tree (MonoInst *tree, int arity)
4986 {
4987         return 0;
4988 }
4989
4990 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4991 {
4992         MonoInst* ins;
4993
4994         if (appdomain_tls_offset == -1)
4995                 return NULL;
4996
4997         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
4998         ins->inst_offset = appdomain_tls_offset;
4999         return ins;
5000 }
5001
5002 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5003 {
5004         MonoInst* ins;
5005
5006         if (thread_tls_offset == -1)
5007                 return NULL;
5008
5009         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5010         ins->inst_offset = thread_tls_offset;
5011         return ins;
5012 }