mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         /* The size of each pair */
 510         int pair_size [2];
 511         int nregs;
 512 } ArgInfo;
 513
 514 typedef struct {
 515         int nargs;
 516         guint32 stack_usage;
 517         guint32 reg_usage;
 518         guint32 freg_usage;
 519         gboolean need_stack_align;
 520         gboolean vtype_retaddr;
 521         /* The index of the vret arg in the argument list */
 522         int vret_arg_index;
 523         ArgInfo ret;
 524         ArgInfo sig_cookie;
 525         ArgInfo args [1];
 526 } CallInfo;
 527
 528 #define DEBUG(a) if (cfg->verbose_level > 1) a
 529
 530 #ifdef TARGET_WIN32
 531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 532
 533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #else
 535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 536
 537  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 538 #endif
 539
 540 static void inline
 541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 542 {
 543     ainfo->offset = *stack_size;
 544
 545     if (*gr >= PARAM_REGS) {
 546                 ainfo->storage = ArgOnStack;
 547                 /* Since the same stack slot size is used for all arg */
 548                 /*  types, it needs to be big enough to hold them all */
 549                 (*stack_size) += sizeof(mgreg_t);
 550     }
 551     else {
 552                 ainfo->storage = ArgInIReg;
 553                 ainfo->reg = param_regs [*gr];
 554                 (*gr) ++;
 555     }
 556 }
 557
 558 #ifdef TARGET_WIN32
 559 #define FLOAT_PARAM_REGS 4
 560 #else
 561 #define FLOAT_PARAM_REGS 8
 562 #endif
 563
 564 static void inline
 565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 566 {
 567     ainfo->offset = *stack_size;
 568
 569     if (*gr >= FLOAT_PARAM_REGS) {
 570                 ainfo->storage = ArgOnStack;
 571                 /* Since the same stack slot size is used for both float */
 572                 /*  types, it needs to be big enough to hold them both */
 573                 (*stack_size) += sizeof(mgreg_t);
 574     }
 575     else {
 576                 /* A double register */
 577                 if (is_double)
 578                         ainfo->storage = ArgInDoubleSSEReg;
 579                 else
 580                         ainfo->storage = ArgInFloatSSEReg;
 581                 ainfo->reg = *gr;
 582                 (*gr) += 1;
 583     }
 584 }
 585
 586 typedef enum ArgumentClass {
 587         ARG_CLASS_NO_CLASS,
 588         ARG_CLASS_MEMORY,
 589         ARG_CLASS_INTEGER,
 590         ARG_CLASS_SSE
 591 } ArgumentClass;
 592
 593 static ArgumentClass
 594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 595 {
 596         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 597         MonoType *ptype;
 598
 599         ptype = mini_type_get_underlying_type (gsctx, type);
 600         switch (ptype->type) {
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef TARGET_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static int
 692 count_fields_nested (MonoClass *klass)
 693 {
 694         MonoMarshalType *info;
 695         int i, count;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         count = 0;
 700         for (i = 0; i < info->num_fields; ++i) {
 701                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 702                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 703                 else
 704                         count ++;
 705         }
 706         return count;
 707 }
 708
 709 static int
 710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 711 {
 712         MonoMarshalType *info;
 713         int i;
 714
 715         info = mono_marshal_load_type_info (klass);
 716         g_assert(info);
 717         for (i = 0; i < info->num_fields; ++i) {
 718                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 719                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 720                 } else {
 721                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 722                         fields [index].offset += offset;
 723                         index ++;
 724                 }
 725         }
 726         return index;
 727 }
 728
 729 static void
 730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 731                            gboolean is_return,
 732                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 733 {
 734         guint32 size, quad, nquads, i, nfields;
 735         /* Keep track of the size used in each quad so we can */
 736         /* use the right size when copying args/return vars.  */
 737         guint32 quadsize [2] = {8, 8};
 738         ArgumentClass args [2];
 739         MonoMarshalType *info = NULL;
 740         MonoMarshalField *fields = NULL;
 741         MonoClass *klass;
 742         MonoGenericSharingContext tmp_gsctx;
 743         gboolean pass_on_stack = FALSE;
 744
 745         /*
 746          * The gsctx currently contains no data, it is only used for checking whenever
 747          * open types are allowed, some callers like mono_arch_get_argument_info ()
 748          * don't pass it to us, so work around that.
 749          */
 750         if (!gsctx)
 751                 gsctx = &tmp_gsctx;
 752
 753         klass = mono_class_from_mono_type (type);
 754         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 755 #ifndef TARGET_WIN32
 756         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 757                 /* We pass and return vtypes of size 8 in a register */
 758         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #else
 762         if (!sig->pinvoke) {
 763                 pass_on_stack = TRUE;
 764         }
 765 #endif
 766
 767         /* If this struct can't be split up naturally into 8-byte */
 768         /* chunks (registers), pass it on the stack.              */
 769         if (sig->pinvoke && !pass_on_stack) {
 770                 guint32 align;
 771                 guint32 field_size;
 772
 773                 info = mono_marshal_load_type_info (klass);
 774                 g_assert (info);
 775
 776                 /*
 777                  * Collect field information recursively to be able to
 778                  * handle nested structures.
 779                  */
 780                 nfields = count_fields_nested (klass);
 781                 fields = g_new0 (MonoMarshalField, nfields);
 782                 collect_field_info_nested (klass, fields, 0, 0);
 783
 784                 for (i = 0; i < nfields; ++i) {
 785                         field_size = mono_marshal_type_size (fields [i].field->type,
 786                                                            fields [i].mspec,
 787                                                            &align, TRUE, klass->unicode);
 788                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 789                                 pass_on_stack = TRUE;
 790                                 break;
 791                         }
 792                 }
 793         }
 794
 795         if (pass_on_stack) {
 796                 /* Allways pass in memory */
 797                 ainfo->offset = *stack_size;
 798                 *stack_size += ALIGN_TO (size, 8);
 799                 ainfo->storage = ArgOnStack;
 800
 801                 g_free (fields);
 802                 return;
 803         }
 804
 805         /* FIXME: Handle structs smaller than 8 bytes */
 806         //if ((size % 8) != 0)
 807         //      NOT_IMPLEMENTED;
 808
 809         if (size > 8)
 810                 nquads = 2;
 811         else
 812                 nquads = 1;
 813
 814         if (!sig->pinvoke) {
 815                 int n = mono_class_value_size (klass, NULL);
 816
 817                 quadsize [0] = n >= 8 ? 8 : n;
 818                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 819
 820                 /* Always pass in 1 or 2 integer registers */
 821                 args [0] = ARG_CLASS_INTEGER;
 822                 args [1] = ARG_CLASS_INTEGER;
 823                 /* Only the simplest cases are supported */
 824                 if (is_return && nquads != 1) {
 825                         args [0] = ARG_CLASS_MEMORY;
 826                         args [1] = ARG_CLASS_MEMORY;
 827                 }
 828         } else {
 829                 /*
 830                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 831                  * The X87 and SSEUP stuff is left out since there are no such types in
 832                  * the CLR.
 833                  */
 834                 g_assert (info);
 835                 g_assert (fields);
 836
 837 #ifndef TARGET_WIN32
 838                 if (info->native_size > 16) {
 839                         ainfo->offset = *stack_size;
 840                         *stack_size += ALIGN_TO (info->native_size, 8);
 841                         ainfo->storage = ArgOnStack;
 842
 843                         g_free (fields);
 844                         return;
 845                 }
 846 #else
 847                 switch (info->native_size) {
 848                 case 1: case 2: case 4: case 8:
 849                         break;
 850                 default:
 851                         if (is_return) {
 852                                 ainfo->storage = ArgOnStack;
 853                                 ainfo->offset = *stack_size;
 854                                 *stack_size += ALIGN_TO (info->native_size, 8);
 855                         }
 856                         else {
 857                                 ainfo->storage = ArgValuetypeAddrInIReg;
 858
 859                                 if (*gr < PARAM_REGS) {
 860                                         ainfo->pair_storage [0] = ArgInIReg;
 861                                         ainfo->pair_regs [0] = param_regs [*gr];
 862                                         (*gr) ++;
 863                                 }
 864                                 else {
 865                                         ainfo->pair_storage [0] = ArgOnStack;
 866                                         ainfo->offset = *stack_size;
 867                                         *stack_size += 8;
 868                                 }
 869                         }
 870
 871                         g_free (fields);
 872                         return;
 873                 }
 874 #endif
 875
 876                 args [0] = ARG_CLASS_NO_CLASS;
 877                 args [1] = ARG_CLASS_NO_CLASS;
 878                 for (quad = 0; quad < nquads; ++quad) {
 879                         int size;
 880                         guint32 align;
 881                         ArgumentClass class1;
 882
 883                         if (nfields == 0)
 884                                 class1 = ARG_CLASS_MEMORY;
 885                         else
 886                                 class1 = ARG_CLASS_NO_CLASS;
 887                         for (i = 0; i < nfields; ++i) {
 888                                 size = mono_marshal_type_size (fields [i].field->type,
 889                                                                                            fields [i].mspec,
 890                                                                                            &align, TRUE, klass->unicode);
 891                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 892                                         /* Unaligned field */
 893                                         NOT_IMPLEMENTED;
 894                                 }
 895
 896                                 /* Skip fields in other quad */
 897                                 if ((quad == 0) && (fields [i].offset >= 8))
 898                                         continue;
 899                                 if ((quad == 1) && (fields [i].offset < 8))
 900                                         continue;
 901
 902                                 /* How far into this quad this data extends.*/
 903                                 /* (8 is size of quad) */
 904                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 905
 906                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 907                         }
 908                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 909                         args [quad] = class1;
 910                 }
 911         }
 912
 913         g_free (fields);
 914
 915         /* Post merger cleanup */
 916         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 917                 args [0] = args [1] = ARG_CLASS_MEMORY;
 918
 919         /* Allocate registers */
 920         {
 921                 int orig_gr = *gr;
 922                 int orig_fr = *fr;
 923
 924                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 925                         quadsize [0] ++;
 926                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 927                         quadsize [1] ++;
 928
 929                 ainfo->storage = ArgValuetypeInReg;
 930                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 931                 g_assert (quadsize [0] <= 8);
 932                 g_assert (quadsize [1] <= 8);
 933                 ainfo->pair_size [0] = quadsize [0];
 934                 ainfo->pair_size [1] = quadsize [1];
 935                 ainfo->nregs = nquads;
 936                 for (quad = 0; quad < nquads; ++quad) {
 937                         switch (args [quad]) {
 938                         case ARG_CLASS_INTEGER:
 939                                 if (*gr >= PARAM_REGS)
 940                                         args [quad] = ARG_CLASS_MEMORY;
 941                                 else {
 942                                         ainfo->pair_storage [quad] = ArgInIReg;
 943                                         if (is_return)
 944                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 945                                         else
 946                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 947                                         (*gr) ++;
 948                                 }
 949                                 break;
 950                         case ARG_CLASS_SSE:
 951                                 if (*fr >= FLOAT_PARAM_REGS)
 952                                         args [quad] = ARG_CLASS_MEMORY;
 953                                 else {
 954                                         if (quadsize[quad] <= 4)
 955                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 956                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 957                                         ainfo->pair_regs [quad] = *fr;
 958                                         (*fr) ++;
 959                                 }
 960                                 break;
 961                         case ARG_CLASS_MEMORY:
 962                                 break;
 963                         default:
 964                                 g_assert_not_reached ();
 965                         }
 966                 }
 967
 968                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 969                         /* Revert possible register assignments */
 970                         *gr = orig_gr;
 971                         *fr = orig_fr;
 972
 973                         ainfo->offset = *stack_size;
 974                         if (sig->pinvoke)
 975                                 *stack_size += ALIGN_TO (info->native_size, 8);
 976                         else
 977                                 *stack_size += nquads * sizeof(mgreg_t);
 978                         ainfo->storage = ArgOnStack;
 979                 }
 980         }
 981 }
 982
 983 /*
 984  * get_call_info:
 985  *
 986  *  Obtain information about a call according to the calling convention.
 987  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 988  * Draft Version 0.23" document for more information.
 989  */
 990 static CallInfo*
 991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 992 {
 993         guint32 i, gr, fr, pstart;
 994         MonoType *ret_type;
 995         int n = sig->hasthis + sig->param_count;
 996         guint32 stack_size = 0;
 997         CallInfo *cinfo;
 998         gboolean is_pinvoke = sig->pinvoke;
 999
1000         if (mp)
1001                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002         else
1003                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1004
1005         cinfo->nargs = n;
1006
1007         gr = 0;
1008         fr = 0;
1009
1010 #ifdef TARGET_WIN32
1011         /* Reserve space where the callee can save the argument registers */
1012         stack_size = 4 * sizeof (mgreg_t);
1013 #endif
1014
1015         /* return value */
1016         ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017         switch (ret_type->type) {
1018         case MONO_TYPE_I1:
1019         case MONO_TYPE_U1:
1020         case MONO_TYPE_I2:
1021         case MONO_TYPE_U2:
1022         case MONO_TYPE_I4:
1023         case MONO_TYPE_U4:
1024         case MONO_TYPE_I:
1025         case MONO_TYPE_U:
1026         case MONO_TYPE_PTR:
1027         case MONO_TYPE_FNPTR:
1028         case MONO_TYPE_CLASS:
1029         case MONO_TYPE_OBJECT:
1030         case MONO_TYPE_SZARRAY:
1031         case MONO_TYPE_ARRAY:
1032         case MONO_TYPE_STRING:
1033                 cinfo->ret.storage = ArgInIReg;
1034                 cinfo->ret.reg = AMD64_RAX;
1035                 break;
1036         case MONO_TYPE_U8:
1037         case MONO_TYPE_I8:
1038                 cinfo->ret.storage = ArgInIReg;
1039                 cinfo->ret.reg = AMD64_RAX;
1040                 break;
1041         case MONO_TYPE_R4:
1042                 cinfo->ret.storage = ArgInFloatSSEReg;
1043                 cinfo->ret.reg = AMD64_XMM0;
1044                 break;
1045         case MONO_TYPE_R8:
1046                 cinfo->ret.storage = ArgInDoubleSSEReg;
1047                 cinfo->ret.reg = AMD64_XMM0;
1048                 break;
1049         case MONO_TYPE_GENERICINST:
1050                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051                         cinfo->ret.storage = ArgInIReg;
1052                         cinfo->ret.reg = AMD64_RAX;
1053                         break;
1054                 }
1055                 /* fall through */
1056 #if defined( __native_client_codegen__ )
1057         case MONO_TYPE_TYPEDBYREF:
1058 #endif
1059         case MONO_TYPE_VALUETYPE: {
1060                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1061
1062                 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063                 if (cinfo->ret.storage == ArgOnStack) {
1064                         cinfo->vtype_retaddr = TRUE;
1065                         /* The caller passes the address where the value is stored */
1066                 }
1067                 break;
1068         }
1069 #if !defined( __native_client_codegen__ )
1070         case MONO_TYPE_TYPEDBYREF:
1071                 /* Same as a valuetype with size 24 */
1072                 cinfo->vtype_retaddr = TRUE;
1073                 break;
1074 #endif
1075         case MONO_TYPE_VOID:
1076                 break;
1077         default:
1078                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1079         }
1080
1081         pstart = 0;
1082         /*
1083          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084          * the first argument, allowing 'this' to be always passed in the first arg reg.
1085          * Also do this if the first argument is a reference type, since virtual calls
1086          * are sometimes made using calli without sig->hasthis set, like in the delegate
1087          * invoke wrappers.
1088          */
1089         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1090                 if (sig->hasthis) {
1091                         add_general (&gr, &stack_size, cinfo->args + 0);
1092                 } else {
1093                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1094                         pstart = 1;
1095                 }
1096                 add_general (&gr, &stack_size, &cinfo->ret);
1097                 cinfo->vret_arg_index = 1;
1098         } else {
1099                 /* this */
1100                 if (sig->hasthis)
1101                         add_general (&gr, &stack_size, cinfo->args + 0);
1102
1103                 if (cinfo->vtype_retaddr)
1104                         add_general (&gr, &stack_size, &cinfo->ret);
1105         }
1106
1107         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1108                 gr = PARAM_REGS;
1109                 fr = FLOAT_PARAM_REGS;
1110
1111                 /* Emit the signature cookie just before the implicit arguments */
1112                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1113         }
1114
1115         for (i = pstart; i < sig->param_count; ++i) {
1116                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1117                 MonoType *ptype;
1118
1119 #ifdef TARGET_WIN32
1120                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1121                 if (gr > fr)
1122                         fr = gr;
1123                 else if (fr > gr)
1124                         gr = fr;
1125 #endif
1126
1127                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128                         /* We allways pass the sig cookie on the stack for simplicity */
1129                         /*
1130                          * Prevent implicit arguments + the sig cookie from being passed
1131                          * in registers.
1132                          */
1133                         gr = PARAM_REGS;
1134                         fr = FLOAT_PARAM_REGS;
1135
1136                         /* Emit the signature cookie just before the implicit arguments */
1137                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1138                 }
1139
1140                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141                 switch (ptype->type) {
1142                 case MONO_TYPE_I1:
1143                 case MONO_TYPE_U1:
1144                         add_general (&gr, &stack_size, ainfo);
1145                         break;
1146                 case MONO_TYPE_I2:
1147                 case MONO_TYPE_U2:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I4:
1151                 case MONO_TYPE_U4:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I:
1155                 case MONO_TYPE_U:
1156                 case MONO_TYPE_PTR:
1157                 case MONO_TYPE_FNPTR:
1158                 case MONO_TYPE_CLASS:
1159                 case MONO_TYPE_OBJECT:
1160                 case MONO_TYPE_STRING:
1161                 case MONO_TYPE_SZARRAY:
1162                 case MONO_TYPE_ARRAY:
1163                         add_general (&gr, &stack_size, ainfo);
1164                         break;
1165                 case MONO_TYPE_GENERICINST:
1166                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167                                 add_general (&gr, &stack_size, ainfo);
1168                                 break;
1169                         }
1170                         /* fall through */
1171                 case MONO_TYPE_VALUETYPE:
1172                 case MONO_TYPE_TYPEDBYREF:
1173                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1174                         break;
1175                 case MONO_TYPE_U8:
1176
1177                 case MONO_TYPE_I8:
1178                         add_general (&gr, &stack_size, ainfo);
1179                         break;
1180                 case MONO_TYPE_R4:
1181                         add_float (&fr, &stack_size, ainfo, FALSE);
1182                         break;
1183                 case MONO_TYPE_R8:
1184                         add_float (&fr, &stack_size, ainfo, TRUE);
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1192                 gr = PARAM_REGS;
1193                 fr = FLOAT_PARAM_REGS;
1194
1195                 /* Emit the signature cookie just before the implicit arguments */
1196                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1197         }
1198
1199         cinfo->stack_usage = stack_size;
1200         cinfo->reg_usage = gr;
1201         cinfo->freg_usage = fr;
1202         return cinfo;
1203 }
1204
1205 /*
1206  * mono_arch_get_argument_info:
1207  * @csig:  a method signature
1208  * @param_count: the number of parameters to consider
1209  * @arg_info: an array to store the result infos
1210  *
1211  * Gathers information on parameters such as size, alignment and
1212  * padding. arg_info should be large enought to hold param_count + 1 entries.
1213  *
1214  * Returns the size of the argument area on the stack.
1215  */
1216 int
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1218 {
1219         int k;
1220         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221         guint32 args_size = cinfo->stack_usage;
1222
1223         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224         if (csig->hasthis) {
1225                 arg_info [0].offset = 0;
1226         }
1227
1228         for (k = 0; k < param_count; k++) {
1229                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1230                 /* FIXME: */
1231                 arg_info [k + 1].size = 0;
1232         }
1233
1234         g_free (cinfo);
1235
1236         return args_size;
1237 }
1238
1239 gboolean
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1241 {
1242         CallInfo *c1, *c2;
1243         gboolean res;
1244         MonoType *callee_ret;
1245
1246         c1 = get_call_info (NULL, NULL, caller_sig);
1247         c2 = get_call_info (NULL, NULL, callee_sig);
1248         res = c1->stack_usage >= c2->stack_usage;
1249         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251                 /* An address on the callee's stack is passed as the first argument */
1252                 res = FALSE;
1253
1254         g_free (c1);
1255         g_free (c2);
1256
1257         return res;
1258 }
1259
1260 /*
1261  * Initialize the cpu to execute managed code.
1262  */
1263 void
1264 mono_arch_cpu_init (void)
1265 {
1266 #ifndef _MSC_VER
1267         guint16 fpcw;
1268
1269         /* spec compliance requires running with double precision */
1270         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271         fpcw &= ~X86_FPCW_PRECC_MASK;
1272         fpcw |= X86_FPCW_PREC_DOUBLE;
1273         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 #else
1276         /* TODO: This is crashing on Win64 right now.
1277         * _control87 (_PC_53, MCW_PC);
1278         */
1279 #endif
1280 }
1281
1282 /*
1283  * Initialize architecture specific code.
1284  */
1285 void
1286 mono_arch_init (void)
1287 {
1288         int flags;
1289
1290         mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1296 #endif
1297
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299         flags = MONO_MMAP_READ;
1300         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301         breakpoint_size = 13;
1302         breakpoint_fault_size = 3;
1303 #else
1304         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305         /* amd64_mov_reg_mem () */
1306         breakpoint_size = 8;
1307         breakpoint_fault_size = 8;
1308 #endif
1309
1310         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311         single_step_fault_size = 4;
1312
1313         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1316
1317         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1320 }
1321
1322 /*
1323  * Cleanup architecture specific code.
1324  */
1325 void
1326 mono_arch_cleanup (void)
1327 {
1328         mono_mutex_destroy (&mini_arch_mutex);
1329 #if defined(__native_client_codegen__)
1330         mono_native_tls_free (nacl_instruction_depth);
1331         mono_native_tls_free (nacl_rex_tag);
1332         mono_native_tls_free (nacl_legacy_prefix_tag);
1333 #endif
1334 }
1335
1336 /*
1337  * This function returns the optimizations supported on this cpu.
1338  */
1339 guint32
1340 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1341 {
1342         guint32 opts = 0;
1343
1344         *exclude_mask = 0;
1345
1346         if (mono_hwcap_x86_has_cmov) {
1347                 opts |= MONO_OPT_CMOV;
1348
1349                 if (mono_hwcap_x86_has_fcmov)
1350                         opts |= MONO_OPT_FCMOV;
1351                 else
1352                         *exclude_mask |= MONO_OPT_FCMOV;
1353         } else {
1354                 *exclude_mask |= MONO_OPT_CMOV;
1355         }
1356
1357         return opts;
1358 }
1359
1360 /*
1361  * This function test for all SSE functions supported.
1362  *
1363  * Returns a bitmask corresponding to all supported versions.
1364  *
1365  */
1366 guint32
1367 mono_arch_cpu_enumerate_simd_versions (void)
1368 {
1369         guint32 sse_opts = 0;
1370
1371         if (mono_hwcap_x86_has_sse1)
1372                 sse_opts |= SIMD_VERSION_SSE1;
1373
1374         if (mono_hwcap_x86_has_sse2)
1375                 sse_opts |= SIMD_VERSION_SSE2;
1376
1377         if (mono_hwcap_x86_has_sse3)
1378                 sse_opts |= SIMD_VERSION_SSE3;
1379
1380         if (mono_hwcap_x86_has_ssse3)
1381                 sse_opts |= SIMD_VERSION_SSSE3;
1382
1383         if (mono_hwcap_x86_has_sse41)
1384                 sse_opts |= SIMD_VERSION_SSE41;
1385
1386         if (mono_hwcap_x86_has_sse42)
1387                 sse_opts |= SIMD_VERSION_SSE42;
1388
1389         if (mono_hwcap_x86_has_sse4a)
1390                 sse_opts |= SIMD_VERSION_SSE4a;
1391
1392         return sse_opts;
1393 }
1394
1395 #ifndef DISABLE_JIT
1396
1397 GList *
1398 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1399 {
1400         GList *vars = NULL;
1401         int i;
1402
1403         for (i = 0; i < cfg->num_varinfo; i++) {
1404                 MonoInst *ins = cfg->varinfo [i];
1405                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1406
1407                 /* unused vars */
1408                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1409                         continue;
1410
1411                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1412                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1413                         continue;
1414
1415                 if (mono_is_regsize_var (ins->inst_vtype)) {
1416                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1417                         g_assert (i == vmv->idx);
1418                         vars = g_list_prepend (vars, vmv);
1419                 }
1420         }
1421
1422         vars = mono_varlist_sort (cfg, vars, 0);
1423
1424         return vars;
1425 }
1426
1427 /**
1428  * mono_arch_compute_omit_fp:
1429  *
1430  *   Determine whenever the frame pointer can be eliminated.
1431  */
1432 static void
1433 mono_arch_compute_omit_fp (MonoCompile *cfg)
1434 {
1435         MonoMethodSignature *sig;
1436         MonoMethodHeader *header;
1437         int i, locals_size;
1438         CallInfo *cinfo;
1439
1440         if (cfg->arch.omit_fp_computed)
1441                 return;
1442
1443         header = cfg->header;
1444
1445         sig = mono_method_signature (cfg->method);
1446
1447         if (!cfg->arch.cinfo)
1448                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1449         cinfo = cfg->arch.cinfo;
1450
1451         /*
1452          * FIXME: Remove some of the restrictions.
1453          */
1454         cfg->arch.omit_fp = TRUE;
1455         cfg->arch.omit_fp_computed = TRUE;
1456
1457 #ifdef __native_client_codegen__
1458         /* NaCl modules may not change the value of RBP, so it cannot be */
1459         /* used as a normal register, but it can be used as a frame pointer*/
1460         cfg->disable_omit_fp = TRUE;
1461         cfg->arch.omit_fp = FALSE;
1462 #endif
1463
1464         if (cfg->disable_omit_fp)
1465                 cfg->arch.omit_fp = FALSE;
1466
1467         if (!debug_omit_fp ())
1468                 cfg->arch.omit_fp = FALSE;
1469         /*
1470         if (cfg->method->save_lmf)
1471                 cfg->arch.omit_fp = FALSE;
1472         */
1473         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1474                 cfg->arch.omit_fp = FALSE;
1475         if (header->num_clauses)
1476                 cfg->arch.omit_fp = FALSE;
1477         if (cfg->param_area)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1480                 cfg->arch.omit_fp = FALSE;
1481         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1482                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1483                 cfg->arch.omit_fp = FALSE;
1484         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1485                 ArgInfo *ainfo = &cinfo->args [i];
1486
1487                 if (ainfo->storage == ArgOnStack) {
1488                         /*
1489                          * The stack offset can only be determined when the frame
1490                          * size is known.
1491                          */
1492                         cfg->arch.omit_fp = FALSE;
1493                 }
1494         }
1495
1496         locals_size = 0;
1497         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1498                 MonoInst *ins = cfg->varinfo [i];
1499                 int ialign;
1500
1501                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1502         }
1503 }
1504
1505 GList *
1506 mono_arch_get_global_int_regs (MonoCompile *cfg)
1507 {
1508         GList *regs = NULL;
1509
1510         mono_arch_compute_omit_fp (cfg);
1511
1512         if (cfg->globalra) {
1513                 if (cfg->arch.omit_fp)
1514                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1515
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1519                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1520 #ifndef __native_client_codegen__
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1522 #endif
1523
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1526                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1532         } else {
1533                 if (cfg->arch.omit_fp)
1534                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1535
1536                 /* We use the callee saved registers for global allocation */
1537                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1538                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1539                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1540                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1541 #ifndef __native_client_codegen__
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1543 #endif
1544 #ifdef TARGET_WIN32
1545                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1547 #endif
1548         }
1549
1550         return regs;
1551 }
1552
1553 GList*
1554 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1555 {
1556         GList *regs = NULL;
1557         int i;
1558
1559         /* All XMM registers */
1560         for (i = 0; i < 16; ++i)
1561                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1562
1563         return regs;
1564 }
1565
1566 GList*
1567 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1568 {
1569         static GList *r = NULL;
1570
1571         if (r == NULL) {
1572                 GList *regs = NULL;
1573
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1579 #ifndef __native_client_codegen__
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1581 #endif
1582
1583                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1585                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1586                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1591
1592                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1593         }
1594
1595         return r;
1596 }
1597
1598 GList*
1599 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1600 {
1601         int i;
1602         static GList *r = NULL;
1603
1604         if (r == NULL) {
1605                 GList *regs = NULL;
1606
1607                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1608                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1609
1610                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1611         }
1612
1613         return r;
1614 }
1615
1616 /*
1617  * mono_arch_regalloc_cost:
1618  *
1619  *  Return the cost, in number of memory references, of the action of
1620  * allocating the variable VMV into a register during global register
1621  * allocation.
1622  */
1623 guint32
1624 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1625 {
1626         MonoInst *ins = cfg->varinfo [vmv->idx];
1627
1628         if (cfg->method->save_lmf)
1629                 /* The register is already saved */
1630                 /* substract 1 for the invisible store in the prolog */
1631                 return (ins->opcode == OP_ARG) ? 0 : 1;
1632         else
1633                 /* push+pop */
1634                 return (ins->opcode == OP_ARG) ? 1 : 2;
1635 }
1636
1637 /*
1638  * mono_arch_fill_argument_info:
1639  *
1640  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1641  * of the method.
1642  */
1643 void
1644 mono_arch_fill_argument_info (MonoCompile *cfg)
1645 {
1646         MonoType *sig_ret;
1647         MonoMethodSignature *sig;
1648         MonoInst *ins;
1649         int i;
1650         CallInfo *cinfo;
1651
1652         sig = mono_method_signature (cfg->method);
1653
1654         cinfo = cfg->arch.cinfo;
1655         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1656
1657         /*
1658          * Contrary to mono_arch_allocate_vars (), the information should describe
1659          * where the arguments are at the beginning of the method, not where they can be
1660          * accessed during the execution of the method. The later makes no sense for the
1661          * global register allocator, since a variable can be in more than one location.
1662          */
1663         if (sig_ret->type != MONO_TYPE_VOID) {
1664                 switch (cinfo->ret.storage) {
1665                 case ArgInIReg:
1666                 case ArgInFloatSSEReg:
1667                 case ArgInDoubleSSEReg:
1668                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1669                                 cfg->vret_addr->opcode = OP_REGVAR;
1670                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1671                         }
1672                         else {
1673                                 cfg->ret->opcode = OP_REGVAR;
1674                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1675                         }
1676                         break;
1677                 case ArgValuetypeInReg:
1678                         cfg->ret->opcode = OP_REGOFFSET;
1679                         cfg->ret->inst_basereg = -1;
1680                         cfg->ret->inst_offset = -1;
1681                         break;
1682                 default:
1683                         g_assert_not_reached ();
1684                 }
1685         }
1686
1687         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1688                 ArgInfo *ainfo = &cinfo->args [i];
1689
1690                 ins = cfg->args [i];
1691
1692                 switch (ainfo->storage) {
1693                 case ArgInIReg:
1694                 case ArgInFloatSSEReg:
1695                 case ArgInDoubleSSEReg:
1696                         ins->opcode = OP_REGVAR;
1697                         ins->inst_c0 = ainfo->reg;
1698                         break;
1699                 case ArgOnStack:
1700                         ins->opcode = OP_REGOFFSET;
1701                         ins->inst_basereg = -1;
1702                         ins->inst_offset = -1;
1703                         break;
1704                 case ArgValuetypeInReg:
1705                         /* Dummy */
1706                         ins->opcode = OP_NOP;
1707                         break;
1708                 default:
1709                         g_assert_not_reached ();
1710                 }
1711         }
1712 }
1713
1714 void
1715 mono_arch_allocate_vars (MonoCompile *cfg)
1716 {
1717         MonoType *sig_ret;
1718         MonoMethodSignature *sig;
1719         MonoInst *ins;
1720         int i, offset;
1721         guint32 locals_stack_size, locals_stack_align;
1722         gint32 *offsets;
1723         CallInfo *cinfo;
1724
1725         sig = mono_method_signature (cfg->method);
1726
1727         cinfo = cfg->arch.cinfo;
1728         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1729
1730         mono_arch_compute_omit_fp (cfg);
1731
1732         /*
1733          * We use the ABI calling conventions for managed code as well.
1734          * Exception: valuetypes are only sometimes passed or returned in registers.
1735          */
1736
1737         /*
1738          * The stack looks like this:
1739          * <incoming arguments passed on the stack>
1740          * <return value>
1741          * <lmf/caller saved registers>
1742          * <locals>
1743          * <spill area>
1744          * <localloc area>  -> grows dynamically
1745          * <params area>
1746          */
1747
1748         if (cfg->arch.omit_fp) {
1749                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1750                 cfg->frame_reg = AMD64_RSP;
1751                 offset = 0;
1752         } else {
1753                 /* Locals are allocated backwards from %fp */
1754                 cfg->frame_reg = AMD64_RBP;
1755                 offset = 0;
1756         }
1757
1758         cfg->arch.saved_iregs = cfg->used_int_regs;
1759         if (cfg->method->save_lmf)
1760                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1761                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1762
1763         if (cfg->arch.omit_fp)
1764                 cfg->arch.reg_save_area_offset = offset;
1765         /* Reserve space for callee saved registers */
1766         for (i = 0; i < AMD64_NREG; ++i)
1767                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1768                         offset += sizeof(mgreg_t);
1769                 }
1770         if (!cfg->arch.omit_fp)
1771                 cfg->arch.reg_save_area_offset = -offset;
1772
1773         if (sig_ret->type != MONO_TYPE_VOID) {
1774                 switch (cinfo->ret.storage) {
1775                 case ArgInIReg:
1776                 case ArgInFloatSSEReg:
1777                 case ArgInDoubleSSEReg:
1778                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1779                                 if (cfg->globalra) {
1780                                         cfg->vret_addr->opcode = OP_REGVAR;
1781                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1782                                 } else {
1783                                         /* The register is volatile */
1784                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1785                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1786                                         if (cfg->arch.omit_fp) {
1787                                                 cfg->vret_addr->inst_offset = offset;
1788                                                 offset += 8;
1789                                         } else {
1790                                                 offset += 8;
1791                                                 cfg->vret_addr->inst_offset = -offset;
1792                                         }
1793                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1794                                                 printf ("vret_addr =");
1795                                                 mono_print_ins (cfg->vret_addr);
1796                                         }
1797                                 }
1798                         }
1799                         else {
1800                                 cfg->ret->opcode = OP_REGVAR;
1801                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1802                         }
1803                         break;
1804                 case ArgValuetypeInReg:
1805                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1806                         cfg->ret->opcode = OP_REGOFFSET;
1807                         cfg->ret->inst_basereg = cfg->frame_reg;
1808                         if (cfg->arch.omit_fp) {
1809                                 cfg->ret->inst_offset = offset;
1810                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1811                         } else {
1812                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1813                                 cfg->ret->inst_offset = - offset;
1814                         }
1815                         break;
1816                 default:
1817                         g_assert_not_reached ();
1818                 }
1819                 if (!cfg->globalra)
1820                         cfg->ret->dreg = cfg->ret->inst_c0;
1821         }
1822
1823         /* Allocate locals */
1824         if (!cfg->globalra) {
1825                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1826                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1827                         char *mname = mono_method_full_name (cfg->method, TRUE);
1828                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1829                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1830                         g_free (mname);
1831                         return;
1832                 }
1833
1834                 if (locals_stack_align) {
1835                         offset += (locals_stack_align - 1);
1836                         offset &= ~(locals_stack_align - 1);
1837                 }
1838                 if (cfg->arch.omit_fp) {
1839                         cfg->locals_min_stack_offset = offset;
1840                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1841                 } else {
1842                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1843                         cfg->locals_max_stack_offset = - offset;
1844                 }
1845
1846                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1847                         if (offsets [i] != -1) {
1848                                 MonoInst *ins = cfg->varinfo [i];
1849                                 ins->opcode = OP_REGOFFSET;
1850                                 ins->inst_basereg = cfg->frame_reg;
1851                                 if (cfg->arch.omit_fp)
1852                                         ins->inst_offset = (offset + offsets [i]);
1853                                 else
1854                                         ins->inst_offset = - (offset + offsets [i]);
1855                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1856                         }
1857                 }
1858                 offset += locals_stack_size;
1859         }
1860
1861         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1862                 g_assert (!cfg->arch.omit_fp);
1863                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1864                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1865         }
1866
1867         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1868                 ins = cfg->args [i];
1869                 if (ins->opcode != OP_REGVAR) {
1870                         ArgInfo *ainfo = &cinfo->args [i];
1871                         gboolean inreg = TRUE;
1872
1873                         if (cfg->globalra) {
1874                                 /* The new allocator needs info about the original locations of the arguments */
1875                                 switch (ainfo->storage) {
1876                                 case ArgInIReg:
1877                                 case ArgInFloatSSEReg:
1878                                 case ArgInDoubleSSEReg:
1879                                         ins->opcode = OP_REGVAR;
1880                                         ins->inst_c0 = ainfo->reg;
1881                                         break;
1882                                 case ArgOnStack:
1883                                         g_assert (!cfg->arch.omit_fp);
1884                                         ins->opcode = OP_REGOFFSET;
1885                                         ins->inst_basereg = cfg->frame_reg;
1886                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1887                                         break;
1888                                 case ArgValuetypeInReg:
1889                                         ins->opcode = OP_REGOFFSET;
1890                                         ins->inst_basereg = cfg->frame_reg;
1891                                         /* These arguments are saved to the stack in the prolog */
1892                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1893                                         if (cfg->arch.omit_fp) {
1894                                                 ins->inst_offset = offset;
1895                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1896                                         } else {
1897                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1898                                                 ins->inst_offset = - offset;
1899                                         }
1900                                         break;
1901                                 default:
1902                                         g_assert_not_reached ();
1903                                 }
1904
1905                                 continue;
1906                         }
1907
1908                         /* FIXME: Allocate volatile arguments to registers */
1909                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1910                                 inreg = FALSE;
1911
1912                         /*
1913                          * Under AMD64, all registers used to pass arguments to functions
1914                          * are volatile across calls.
1915                          * FIXME: Optimize this.
1916                          */
1917                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1918                                 inreg = FALSE;
1919
1920                         ins->opcode = OP_REGOFFSET;
1921
1922                         switch (ainfo->storage) {
1923                         case ArgInIReg:
1924                         case ArgInFloatSSEReg:
1925                         case ArgInDoubleSSEReg:
1926                                 if (inreg) {
1927                                         ins->opcode = OP_REGVAR;
1928                                         ins->dreg = ainfo->reg;
1929                                 }
1930                                 break;
1931                         case ArgOnStack:
1932                                 g_assert (!cfg->arch.omit_fp);
1933                                 ins->opcode = OP_REGOFFSET;
1934                                 ins->inst_basereg = cfg->frame_reg;
1935                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1936                                 break;
1937                         case ArgValuetypeInReg:
1938                                 break;
1939                         case ArgValuetypeAddrInIReg: {
1940                                 MonoInst *indir;
1941                                 g_assert (!cfg->arch.omit_fp);
1942
1943                                 MONO_INST_NEW (cfg, indir, 0);
1944                                 indir->opcode = OP_REGOFFSET;
1945                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1946                                         indir->inst_basereg = cfg->frame_reg;
1947                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1948                                         offset += (sizeof (gpointer));
1949                                         indir->inst_offset = - offset;
1950                                 }
1951                                 else {
1952                                         indir->inst_basereg = cfg->frame_reg;
1953                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1954                                 }
1955
1956                                 ins->opcode = OP_VTARG_ADDR;
1957                                 ins->inst_left = indir;
1958
1959                                 break;
1960                         }
1961                         default:
1962                                 NOT_IMPLEMENTED;
1963                         }
1964
1965                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1966                                 ins->opcode = OP_REGOFFSET;
1967                                 ins->inst_basereg = cfg->frame_reg;
1968                                 /* These arguments are saved to the stack in the prolog */
1969                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1970                                 if (cfg->arch.omit_fp) {
1971                                         ins->inst_offset = offset;
1972                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1973                                         // Arguments are yet supported by the stack map creation code
1974                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1975                                 } else {
1976                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1977                                         ins->inst_offset = - offset;
1978                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1979                                 }
1980                         }
1981                 }
1982         }
1983
1984         cfg->stack_offset = offset;
1985 }
1986
1987 void
1988 mono_arch_create_vars (MonoCompile *cfg)
1989 {
1990         MonoMethodSignature *sig;
1991         CallInfo *cinfo;
1992         MonoType *sig_ret;
1993
1994         sig = mono_method_signature (cfg->method);
1995
1996         if (!cfg->arch.cinfo)
1997                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1998         cinfo = cfg->arch.cinfo;
1999
2000         if (cinfo->ret.storage == ArgValuetypeInReg)
2001                 cfg->ret_var_is_local = TRUE;
2002
2003         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2004         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2005                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2006                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2007                         printf ("vret_addr = ");
2008                         mono_print_ins (cfg->vret_addr);
2009                 }
2010         }
2011
2012         if (cfg->gen_sdb_seq_points) {
2013                 MonoInst *ins;
2014
2015                 if (cfg->compile_aot) {
2016                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2017                         ins->flags |= MONO_INST_VOLATILE;
2018                         cfg->arch.seq_point_info_var = ins;
2019
2020                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2021                         ins->flags |= MONO_INST_VOLATILE;
2022                         cfg->arch.ss_tramp_var = ins;
2023                 }
2024
2025             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2026                 ins->flags |= MONO_INST_VOLATILE;
2027                 cfg->arch.ss_trigger_page_var = ins;
2028         }
2029
2030         if (cfg->method->save_lmf)
2031                 cfg->create_lmf_var = TRUE;
2032
2033         if (cfg->method->save_lmf) {
2034                 cfg->lmf_ir = TRUE;
2035 #if !defined(TARGET_WIN32)
2036                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2037                         cfg->lmf_ir_mono_lmf = TRUE;
2038 #endif
2039         }
2040 }
2041
2042 static void
2043 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2044 {
2045         MonoInst *ins;
2046
2047         switch (storage) {
2048         case ArgInIReg:
2049                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2050                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2051                 ins->sreg1 = tree->dreg;
2052                 MONO_ADD_INS (cfg->cbb, ins);
2053                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2054                 break;
2055         case ArgInFloatSSEReg:
2056                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2057                 ins->dreg = mono_alloc_freg (cfg);
2058                 ins->sreg1 = tree->dreg;
2059                 MONO_ADD_INS (cfg->cbb, ins);
2060
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062                 break;
2063         case ArgInDoubleSSEReg:
2064                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2065                 ins->dreg = mono_alloc_freg (cfg);
2066                 ins->sreg1 = tree->dreg;
2067                 MONO_ADD_INS (cfg->cbb, ins);
2068
2069                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2070
2071                 break;
2072         default:
2073                 g_assert_not_reached ();
2074         }
2075 }
2076
2077 static int
2078 arg_storage_to_load_membase (ArgStorage storage)
2079 {
2080         switch (storage) {
2081         case ArgInIReg:
2082 #if defined(__mono_ilp32__)
2083                 return OP_LOADI8_MEMBASE;
2084 #else
2085                 return OP_LOAD_MEMBASE;
2086 #endif
2087         case ArgInDoubleSSEReg:
2088                 return OP_LOADR8_MEMBASE;
2089         case ArgInFloatSSEReg:
2090                 return OP_LOADR4_MEMBASE;
2091         default:
2092                 g_assert_not_reached ();
2093         }
2094
2095         return -1;
2096 }
2097
2098 static void
2099 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2100 {
2101         MonoMethodSignature *tmp_sig;
2102         int sig_reg;
2103
2104         if (call->tail_call)
2105                 NOT_IMPLEMENTED;
2106
2107         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2108
2109         /*
2110          * mono_ArgIterator_Setup assumes the signature cookie is
2111          * passed first and all the arguments which were before it are
2112          * passed on the stack after the signature. So compensate by
2113          * passing a different signature.
2114          */
2115         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2116         tmp_sig->param_count -= call->signature->sentinelpos;
2117         tmp_sig->sentinelpos = 0;
2118         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2119
2120         sig_reg = mono_alloc_ireg (cfg);
2121         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2122
2123         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2124 }
2125
2126 #ifdef ENABLE_LLVM
2127 static inline LLVMArgStorage
2128 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2129 {
2130         switch (storage) {
2131         case ArgInIReg:
2132                 return LLVMArgInIReg;
2133         case ArgNone:
2134                 return LLVMArgNone;
2135         default:
2136                 g_assert_not_reached ();
2137                 return LLVMArgNone;
2138         }
2139 }
2140
2141 LLVMCallInfo*
2142 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2143 {
2144         int i, n;
2145         CallInfo *cinfo;
2146         ArgInfo *ainfo;
2147         int j;
2148         LLVMCallInfo *linfo;
2149         MonoType *t, *sig_ret;
2150
2151         n = sig->param_count + sig->hasthis;
2152         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2153
2154         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2155
2156         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2157
2158         /*
2159          * LLVM always uses the native ABI while we use our own ABI, the
2160          * only difference is the handling of vtypes:
2161          * - we only pass/receive them in registers in some cases, and only
2162          *   in 1 or 2 integer registers.
2163          */
2164         if (cinfo->ret.storage == ArgValuetypeInReg) {
2165                 if (sig->pinvoke) {
2166                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2167                         cfg->disable_llvm = TRUE;
2168                         return linfo;
2169                 }
2170
2171                 linfo->ret.storage = LLVMArgVtypeInReg;
2172                 for (j = 0; j < 2; ++j)
2173                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2174         }
2175
2176         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2177                 /* Vtype returned using a hidden argument */
2178                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2179                 linfo->vret_arg_index = cinfo->vret_arg_index;
2180         }
2181
2182         for (i = 0; i < n; ++i) {
2183                 ainfo = cinfo->args + i;
2184
2185                 if (i >= sig->hasthis)
2186                         t = sig->params [i - sig->hasthis];
2187                 else
2188                         t = &mono_defaults.int_class->byval_arg;
2189
2190                 linfo->args [i].storage = LLVMArgNone;
2191
2192                 switch (ainfo->storage) {
2193                 case ArgInIReg:
2194                         linfo->args [i].storage = LLVMArgInIReg;
2195                         break;
2196                 case ArgInDoubleSSEReg:
2197                 case ArgInFloatSSEReg:
2198                         linfo->args [i].storage = LLVMArgInFPReg;
2199                         break;
2200                 case ArgOnStack:
2201                         if (MONO_TYPE_ISSTRUCT (t)) {
2202                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2203                         } else {
2204                                 linfo->args [i].storage = LLVMArgInIReg;
2205                                 if (!t->byref) {
2206                                         if (t->type == MONO_TYPE_R4)
2207                                                 linfo->args [i].storage = LLVMArgInFPReg;
2208                                         else if (t->type == MONO_TYPE_R8)
2209                                                 linfo->args [i].storage = LLVMArgInFPReg;
2210                                 }
2211                         }
2212                         break;
2213                 case ArgValuetypeInReg:
2214                         if (sig->pinvoke) {
2215                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2216                                 cfg->disable_llvm = TRUE;
2217                                 return linfo;
2218                         }
2219
2220                         linfo->args [i].storage = LLVMArgVtypeInReg;
2221                         for (j = 0; j < 2; ++j)
2222                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2223                         break;
2224                 default:
2225                         cfg->exception_message = g_strdup ("ainfo->storage");
2226                         cfg->disable_llvm = TRUE;
2227                         break;
2228                 }
2229         }
2230
2231         return linfo;
2232 }
2233 #endif
2234
2235 void
2236 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 {
2238         MonoInst *arg, *in;
2239         MonoMethodSignature *sig;
2240         MonoType *sig_ret;
2241         int i, n;
2242         CallInfo *cinfo;
2243         ArgInfo *ainfo;
2244
2245         sig = call->signature;
2246         n = sig->param_count + sig->hasthis;
2247
2248         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2249
2250         sig_ret = sig->ret;
2251
2252         if (COMPILE_LLVM (cfg)) {
2253                 /* We shouldn't be called in the llvm case */
2254                 cfg->disable_llvm = TRUE;
2255                 return;
2256         }
2257
2258         /*
2259          * Emit all arguments which are passed on the stack to prevent register
2260          * allocation problems.
2261          */
2262         for (i = 0; i < n; ++i) {
2263                 MonoType *t;
2264                 ainfo = cinfo->args + i;
2265
2266                 in = call->args [i];
2267
2268                 if (sig->hasthis && i == 0)
2269                         t = &mono_defaults.object_class->byval_arg;
2270                 else
2271                         t = sig->params [i - sig->hasthis];
2272
2273                 t = mini_get_underlying_type (cfg, t);
2274                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2275                         if (!t->byref) {
2276                                 if (t->type == MONO_TYPE_R4)
2277                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2278                                 else if (t->type == MONO_TYPE_R8)
2279                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2280                                 else
2281                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2282                         } else {
2283                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2284                         }
2285                         if (cfg->compute_gc_maps) {
2286                                 MonoInst *def;
2287
2288                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2289                         }
2290                 }
2291         }
2292
2293         /*
2294          * Emit all parameters passed in registers in non-reverse order for better readability
2295          * and to help the optimization in emit_prolog ().
2296          */
2297         for (i = 0; i < n; ++i) {
2298                 ainfo = cinfo->args + i;
2299
2300                 in = call->args [i];
2301
2302                 if (ainfo->storage == ArgInIReg)
2303                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2304         }
2305
2306         for (i = n - 1; i >= 0; --i) {
2307                 ainfo = cinfo->args + i;
2308
2309                 in = call->args [i];
2310
2311                 switch (ainfo->storage) {
2312                 case ArgInIReg:
2313                         /* Already done */
2314                         break;
2315                 case ArgInFloatSSEReg:
2316                 case ArgInDoubleSSEReg:
2317                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2318                         break;
2319                 case ArgOnStack:
2320                 case ArgValuetypeInReg:
2321                 case ArgValuetypeAddrInIReg:
2322                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2323                                 MonoInst *call_inst = (MonoInst*)call;
2324                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2325                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2326                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2327                                 guint32 align;
2328                                 guint32 size;
2329
2330                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2331                                         size = sizeof (MonoTypedRef);
2332                                         align = sizeof (gpointer);
2333                                 }
2334                                 else {
2335                                         if (sig->pinvoke)
2336                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2337                                         else {
2338                                                 /*
2339                                                  * Other backends use mono_type_stack_size (), but that
2340                                                  * aligns the size to 8, which is larger than the size of
2341                                                  * the source, leading to reads of invalid memory if the
2342                                                  * source is at the end of address space.
2343                                                  */
2344                                                 size = mono_class_value_size (in->klass, &align);
2345                                         }
2346                                 }
2347                                 g_assert (in->klass);
2348
2349                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2350                                         /* Avoid asserts in emit_memcpy () */
2351                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2352                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2353                                         /* Continue normally */
2354                                 }
2355
2356                                 if (size > 0) {
2357                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2358                                         arg->sreg1 = in->dreg;
2359                                         arg->klass = in->klass;
2360                                         arg->backend.size = size;
2361                                         arg->inst_p0 = call;
2362                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2363                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2364
2365                                         MONO_ADD_INS (cfg->cbb, arg);
2366                                 }
2367                         }
2368                         break;
2369                 default:
2370                         g_assert_not_reached ();
2371                 }
2372
2373                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2374                         /* Emit the signature cookie just before the implicit arguments */
2375                         emit_sig_cookie (cfg, call, cinfo);
2376         }
2377
2378         /* Handle the case where there are no implicit arguments */
2379         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2380                 emit_sig_cookie (cfg, call, cinfo);
2381
2382         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2383         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2384                 MonoInst *vtarg;
2385
2386                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2387                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2388                                 /*
2389                                  * Tell the JIT to use a more efficient calling convention: call using
2390                                  * OP_CALL, compute the result location after the call, and save the
2391                                  * result there.
2392                                  */
2393                                 call->vret_in_reg = TRUE;
2394                                 /*
2395                                  * Nullify the instruction computing the vret addr to enable
2396                                  * future optimizations.
2397                                  */
2398                                 if (call->vret_var)
2399                                         NULLIFY_INS (call->vret_var);
2400                         } else {
2401                                 if (call->tail_call)
2402                                         NOT_IMPLEMENTED;
2403                                 /*
2404                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2405                                  * the stack. Push the address here, so the call instruction can
2406                                  * access it.
2407                                  */
2408                                 if (!cfg->arch.vret_addr_loc) {
2409                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2410                                         /* Prevent it from being register allocated or optimized away */
2411                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2412                                 }
2413
2414                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2415                         }
2416                 }
2417                 else {
2418                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2419                         vtarg->sreg1 = call->vret_var->dreg;
2420                         vtarg->dreg = mono_alloc_preg (cfg);
2421                         MONO_ADD_INS (cfg->cbb, vtarg);
2422
2423                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2424                 }
2425         }
2426
2427         if (cfg->method->save_lmf) {
2428                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2429                 MONO_ADD_INS (cfg->cbb, arg);
2430         }
2431
2432         call->stack_usage = cinfo->stack_usage;
2433 }
2434
2435 void
2436 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2437 {
2438         MonoInst *arg;
2439         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2440         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2441         int size = ins->backend.size;
2442
2443         if (ainfo->storage == ArgValuetypeInReg) {
2444                 MonoInst *load;
2445                 int part;
2446
2447                 for (part = 0; part < 2; ++part) {
2448                         if (ainfo->pair_storage [part] == ArgNone)
2449                                 continue;
2450
2451                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2452                         load->inst_basereg = src->dreg;
2453                         load->inst_offset = part * sizeof(mgreg_t);
2454
2455                         switch (ainfo->pair_storage [part]) {
2456                         case ArgInIReg:
2457                                 load->dreg = mono_alloc_ireg (cfg);
2458                                 break;
2459                         case ArgInDoubleSSEReg:
2460                         case ArgInFloatSSEReg:
2461                                 load->dreg = mono_alloc_freg (cfg);
2462                                 break;
2463                         default:
2464                                 g_assert_not_reached ();
2465                         }
2466                         MONO_ADD_INS (cfg->cbb, load);
2467
2468                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2469                 }
2470         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2471                 MonoInst *vtaddr, *load;
2472                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2473
2474                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2475                 cfg->has_indirection = TRUE;
2476                 load->inst_p0 = vtaddr;
2477                 vtaddr->flags |= MONO_INST_INDIRECT;
2478                 load->type = STACK_MP;
2479                 load->klass = vtaddr->klass;
2480                 load->dreg = mono_alloc_ireg (cfg);
2481                 MONO_ADD_INS (cfg->cbb, load);
2482                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2483
2484                 if (ainfo->pair_storage [0] == ArgInIReg) {
2485                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2486                         arg->dreg = mono_alloc_ireg (cfg);
2487                         arg->sreg1 = load->dreg;
2488                         arg->inst_imm = 0;
2489                         MONO_ADD_INS (cfg->cbb, arg);
2490                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2491                 } else {
2492                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2493                 }
2494         } else {
2495                 if (size == 8) {
2496                         int dreg = mono_alloc_ireg (cfg);
2497
2498                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2499                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2500                 } else if (size <= 40) {
2501                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2502                 } else {
2503                         // FIXME: Code growth
2504                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2505                 }
2506
2507                 if (cfg->compute_gc_maps) {
2508                         MonoInst *def;
2509                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2510                 }
2511         }
2512 }
2513
2514 void
2515 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2516 {
2517         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2518
2519         if (ret->type == MONO_TYPE_R4) {
2520                 if (COMPILE_LLVM (cfg))
2521                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2522                 else
2523                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2524                 return;
2525         } else if (ret->type == MONO_TYPE_R8) {
2526                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2527                 return;
2528         }
2529
2530         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2531 }
2532
2533 #endif /* DISABLE_JIT */
2534
2535 #define EMIT_COND_BRANCH(ins,cond,sign) \
2536         if (ins->inst_true_bb->native_offset) { \
2537                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2538         } else { \
2539                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2540                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2541             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2542                         x86_branch8 (code, cond, 0, sign); \
2543                 else \
2544                         x86_branch32 (code, cond, 0, sign); \
2545 }
2546
2547 typedef struct {
2548         MonoMethodSignature *sig;
2549         CallInfo *cinfo;
2550 } ArchDynCallInfo;
2551
2552 static gboolean
2553 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2554 {
2555         int i;
2556
2557 #ifdef HOST_WIN32
2558         return FALSE;
2559 #endif
2560
2561         switch (cinfo->ret.storage) {
2562         case ArgNone:
2563         case ArgInIReg:
2564                 break;
2565         case ArgValuetypeInReg: {
2566                 ArgInfo *ainfo = &cinfo->ret;
2567
2568                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2569                         return FALSE;
2570                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2571                         return FALSE;
2572                 break;
2573         }
2574         default:
2575                 return FALSE;
2576         }
2577
2578         for (i = 0; i < cinfo->nargs; ++i) {
2579                 ArgInfo *ainfo = &cinfo->args [i];
2580                 switch (ainfo->storage) {
2581                 case ArgInIReg:
2582                         break;
2583                 case ArgValuetypeInReg:
2584                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2585                                 return FALSE;
2586                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2587                                 return FALSE;
2588                         break;
2589                 default:
2590                         return FALSE;
2591                 }
2592         }
2593
2594         return TRUE;
2595 }
2596
2597 /*
2598  * mono_arch_dyn_call_prepare:
2599  *
2600  *   Return a pointer to an arch-specific structure which contains information
2601  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2602  * supported for SIG.
2603  * This function is equivalent to ffi_prep_cif in libffi.
2604  */
2605 MonoDynCallInfo*
2606 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2607 {
2608         ArchDynCallInfo *info;
2609         CallInfo *cinfo;
2610
2611         cinfo = get_call_info (NULL, NULL, sig);
2612
2613         if (!dyn_call_supported (sig, cinfo)) {
2614                 g_free (cinfo);
2615                 return NULL;
2616         }
2617
2618         info = g_new0 (ArchDynCallInfo, 1);
2619         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2620         info->sig = sig;
2621         info->cinfo = cinfo;
2622
2623         return (MonoDynCallInfo*)info;
2624 }
2625
2626 /*
2627  * mono_arch_dyn_call_free:
2628  *
2629  *   Free a MonoDynCallInfo structure.
2630  */
2631 void
2632 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2633 {
2634         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2635
2636         g_free (ainfo->cinfo);
2637         g_free (ainfo);
2638 }
2639
2640 #if !defined(__native_client__)
2641 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2642 #define GREG_TO_PTR(greg) (gpointer)(greg)
2643 #else
2644 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2645 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2646 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2647 #endif
2648
2649 /*
2650  * mono_arch_get_start_dyn_call:
2651  *
2652  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2653  * store the result into BUF.
2654  * ARGS should be an array of pointers pointing to the arguments.
2655  * RET should point to a memory buffer large enought to hold the result of the
2656  * call.
2657  * This function should be as fast as possible, any work which does not depend
2658  * on the actual values of the arguments should be done in
2659  * mono_arch_dyn_call_prepare ().
2660  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2661  * libffi.
2662  */
2663 void
2664 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2665 {
2666         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2667         DynCallArgs *p = (DynCallArgs*)buf;
2668         int arg_index, greg, i, pindex;
2669         MonoMethodSignature *sig = dinfo->sig;
2670
2671         g_assert (buf_len >= sizeof (DynCallArgs));
2672
2673         p->res = 0;
2674         p->ret = ret;
2675
2676         arg_index = 0;
2677         greg = 0;
2678         pindex = 0;
2679
2680         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2681                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2682                 if (!sig->hasthis)
2683                         pindex = 1;
2684         }
2685
2686         if (dinfo->cinfo->vtype_retaddr)
2687                 p->regs [greg ++] = PTR_TO_GREG(ret);
2688
2689         for (i = pindex; i < sig->param_count; i++) {
2690                 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2691                 gpointer *arg = args [arg_index ++];
2692
2693                 if (t->byref) {
2694                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2695                         continue;
2696                 }
2697
2698                 switch (t->type) {
2699                 case MONO_TYPE_STRING:
2700                 case MONO_TYPE_CLASS:
2701                 case MONO_TYPE_ARRAY:
2702                 case MONO_TYPE_SZARRAY:
2703                 case MONO_TYPE_OBJECT:
2704                 case MONO_TYPE_PTR:
2705                 case MONO_TYPE_I:
2706                 case MONO_TYPE_U:
2707 #if !defined(__mono_ilp32__)
2708                 case MONO_TYPE_I8:
2709                 case MONO_TYPE_U8:
2710 #endif
2711                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2712                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2713                         break;
2714 #if defined(__mono_ilp32__)
2715                 case MONO_TYPE_I8:
2716                 case MONO_TYPE_U8:
2717                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2718                         p->regs [greg ++] = *(guint64*)(arg);
2719                         break;
2720 #endif
2721                 case MONO_TYPE_U1:
2722                         p->regs [greg ++] = *(guint8*)(arg);
2723                         break;
2724                 case MONO_TYPE_I1:
2725                         p->regs [greg ++] = *(gint8*)(arg);
2726                         break;
2727                 case MONO_TYPE_I2:
2728                         p->regs [greg ++] = *(gint16*)(arg);
2729                         break;
2730                 case MONO_TYPE_U2:
2731                         p->regs [greg ++] = *(guint16*)(arg);
2732                         break;
2733                 case MONO_TYPE_I4:
2734                         p->regs [greg ++] = *(gint32*)(arg);
2735                         break;
2736                 case MONO_TYPE_U4:
2737                         p->regs [greg ++] = *(guint32*)(arg);
2738                         break;
2739                 case MONO_TYPE_GENERICINST:
2740                     if (MONO_TYPE_IS_REFERENCE (t)) {
2741                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2742                                 break;
2743                         } else {
2744                                 /* Fall through */
2745                         }
2746                 case MONO_TYPE_VALUETYPE: {
2747                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2748
2749                         g_assert (ainfo->storage == ArgValuetypeInReg);
2750                         if (ainfo->pair_storage [0] != ArgNone) {
2751                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2752                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2753                         }
2754                         if (ainfo->pair_storage [1] != ArgNone) {
2755                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2756                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2757                         }
2758                         break;
2759                 }
2760                 default:
2761                         g_assert_not_reached ();
2762                 }
2763         }
2764
2765         g_assert (greg <= PARAM_REGS);
2766 }
2767
2768 /*
2769  * mono_arch_finish_dyn_call:
2770  *
2771  *   Store the result of a dyn call into the return value buffer passed to
2772  * start_dyn_call ().
2773  * This function should be as fast as possible, any work which does not depend
2774  * on the actual values of the arguments should be done in
2775  * mono_arch_dyn_call_prepare ().
2776  */
2777 void
2778 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2779 {
2780         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2781         MonoMethodSignature *sig = dinfo->sig;
2782         guint8 *ret = ((DynCallArgs*)buf)->ret;
2783         mgreg_t res = ((DynCallArgs*)buf)->res;
2784         MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2785
2786         switch (sig_ret->type) {
2787         case MONO_TYPE_VOID:
2788                 *(gpointer*)ret = NULL;
2789                 break;
2790         case MONO_TYPE_STRING:
2791         case MONO_TYPE_CLASS:
2792         case MONO_TYPE_ARRAY:
2793         case MONO_TYPE_SZARRAY:
2794         case MONO_TYPE_OBJECT:
2795         case MONO_TYPE_I:
2796         case MONO_TYPE_U:
2797         case MONO_TYPE_PTR:
2798                 *(gpointer*)ret = GREG_TO_PTR(res);
2799                 break;
2800         case MONO_TYPE_I1:
2801                 *(gint8*)ret = res;
2802                 break;
2803         case MONO_TYPE_U1:
2804                 *(guint8*)ret = res;
2805                 break;
2806         case MONO_TYPE_I2:
2807                 *(gint16*)ret = res;
2808                 break;
2809         case MONO_TYPE_U2:
2810                 *(guint16*)ret = res;
2811                 break;
2812         case MONO_TYPE_I4:
2813                 *(gint32*)ret = res;
2814                 break;
2815         case MONO_TYPE_U4:
2816                 *(guint32*)ret = res;
2817                 break;
2818         case MONO_TYPE_I8:
2819                 *(gint64*)ret = res;
2820                 break;
2821         case MONO_TYPE_U8:
2822                 *(guint64*)ret = res;
2823                 break;
2824         case MONO_TYPE_GENERICINST:
2825                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2826                         *(gpointer*)ret = GREG_TO_PTR(res);
2827                         break;
2828                 } else {
2829                         /* Fall through */
2830                 }
2831         case MONO_TYPE_VALUETYPE:
2832                 if (dinfo->cinfo->vtype_retaddr) {
2833                         /* Nothing to do */
2834                 } else {
2835                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2836
2837                         g_assert (ainfo->storage == ArgValuetypeInReg);
2838
2839                         if (ainfo->pair_storage [0] != ArgNone) {
2840                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2841                                 ((mgreg_t*)ret)[0] = res;
2842                         }
2843
2844                         g_assert (ainfo->pair_storage [1] == ArgNone);
2845                 }
2846                 break;
2847         default:
2848                 g_assert_not_reached ();
2849         }
2850 }
2851
2852 /* emit an exception if condition is fail */
2853 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2854         do {                                                        \
2855                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2856                 if (tins == NULL) {                                                                             \
2857                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2858                                         MONO_PATCH_INFO_EXC, exc_name);  \
2859                         x86_branch32 (code, cond, 0, signed);               \
2860                 } else {        \
2861                         EMIT_COND_BRANCH (tins, cond, signed);  \
2862                 }                       \
2863         } while (0);
2864
2865 #define EMIT_FPCOMPARE(code) do { \
2866         amd64_fcompp (code); \
2867         amd64_fnstsw (code); \
2868 } while (0);
2869
2870 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2871     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2872         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2873         amd64_ ##op (code); \
2874         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2875         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2876 } while (0);
2877
2878 static guint8*
2879 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2880 {
2881         gboolean no_patch = FALSE;
2882
2883         /*
2884          * FIXME: Add support for thunks
2885          */
2886         {
2887                 gboolean near_call = FALSE;
2888
2889                 /*
2890                  * Indirect calls are expensive so try to make a near call if possible.
2891                  * The caller memory is allocated by the code manager so it is
2892                  * guaranteed to be at a 32 bit offset.
2893                  */
2894
2895                 if (patch_type != MONO_PATCH_INFO_ABS) {
2896                         /* The target is in memory allocated using the code manager */
2897                         near_call = TRUE;
2898
2899                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2900                                 if (((MonoMethod*)data)->klass->image->aot_module)
2901                                         /* The callee might be an AOT method */
2902                                         near_call = FALSE;
2903                                 if (((MonoMethod*)data)->dynamic)
2904                                         /* The target is in malloc-ed memory */
2905                                         near_call = FALSE;
2906                         }
2907
2908                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2909                                 /*
2910                                  * The call might go directly to a native function without
2911                                  * the wrapper.
2912                                  */
2913                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2914                                 if (mi) {
2915                                         gconstpointer target = mono_icall_get_wrapper (mi);
2916                                         if ((((guint64)target) >> 32) != 0)
2917                                                 near_call = FALSE;
2918                                 }
2919                         }
2920                 }
2921                 else {
2922                         MonoJumpInfo *jinfo = NULL;
2923
2924                         if (cfg->abs_patches)
2925                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2926                         if (jinfo) {
2927                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2928                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2929                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2930                                                 near_call = TRUE;
2931                                         no_patch = TRUE;
2932                                 } else {
2933                                         /*
2934                                          * This is not really an optimization, but required because the
2935                                          * generic class init trampolines use R11 to pass the vtable.
2936                                          */
2937                                         near_call = TRUE;
2938                                 }
2939                         } else {
2940                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2941                                 if (info) {
2942                                         if (info->func == info->wrapper) {
2943                                                 /* No wrapper */
2944                                                 if ((((guint64)info->func) >> 32) == 0)
2945                                                         near_call = TRUE;
2946                                         }
2947                                         else {
2948                                                 /* See the comment in mono_codegen () */
2949                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2950                                                         near_call = TRUE;
2951                                         }
2952                                 }
2953                                 else if ((((guint64)data) >> 32) == 0) {
2954                                         near_call = TRUE;
2955                                         no_patch = TRUE;
2956                                 }
2957                         }
2958                 }
2959
2960                 if (cfg->method->dynamic)
2961                         /* These methods are allocated using malloc */
2962                         near_call = FALSE;
2963
2964 #ifdef MONO_ARCH_NOMAP32BIT
2965                 near_call = FALSE;
2966 #endif
2967 #if defined(__native_client__)
2968                 /* Always use near_call == TRUE for Native Client */
2969                 near_call = TRUE;
2970 #endif
2971                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2972                 if (optimize_for_xen)
2973                         near_call = FALSE;
2974
2975                 if (cfg->compile_aot) {
2976                         near_call = TRUE;
2977                         no_patch = TRUE;
2978                 }
2979
2980                 if (near_call) {
2981                         /*
2982                          * Align the call displacement to an address divisible by 4 so it does
2983                          * not span cache lines. This is required for code patching to work on SMP
2984                          * systems.
2985                          */
2986                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2987                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2988                                 amd64_padding (code, pad_size);
2989                         }
2990                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2991                         amd64_call_code (code, 0);
2992                 }
2993                 else {
2994                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2995                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2996                         amd64_call_reg (code, GP_SCRATCH_REG);
2997                 }
2998         }
2999
3000         return code;
3001 }
3002
3003 static inline guint8*
3004 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3005 {
3006 #ifdef TARGET_WIN32
3007         if (win64_adjust_stack)
3008                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3009 #endif
3010         code = emit_call_body (cfg, code, patch_type, data);
3011 #ifdef TARGET_WIN32
3012         if (win64_adjust_stack)
3013                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3014 #endif
3015
3016         return code;
3017 }
3018
3019 static inline int
3020 store_membase_imm_to_store_membase_reg (int opcode)
3021 {
3022         switch (opcode) {
3023         case OP_STORE_MEMBASE_IMM:
3024                 return OP_STORE_MEMBASE_REG;
3025         case OP_STOREI4_MEMBASE_IMM:
3026                 return OP_STOREI4_MEMBASE_REG;
3027         case OP_STOREI8_MEMBASE_IMM:
3028                 return OP_STOREI8_MEMBASE_REG;
3029         }
3030
3031         return -1;
3032 }
3033
3034 #ifndef DISABLE_JIT
3035
3036 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3037
3038 /*
3039  * mono_arch_peephole_pass_1:
3040  *
3041  *   Perform peephole opts which should/can be performed before local regalloc
3042  */
3043 void
3044 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3045 {
3046         MonoInst *ins, *n;
3047
3048         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3049                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3050
3051                 switch (ins->opcode) {
3052                 case OP_ADD_IMM:
3053                 case OP_IADD_IMM:
3054                 case OP_LADD_IMM:
3055                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3056                                 /*
3057                                  * X86_LEA is like ADD, but doesn't have the
3058                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3059                                  * its operand to 64 bit.
3060                                  */
3061                                 ins->opcode = OP_X86_LEA_MEMBASE;
3062                                 ins->inst_basereg = ins->sreg1;
3063                         }
3064                         break;
3065                 case OP_LXOR:
3066                 case OP_IXOR:
3067                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3068                                 MonoInst *ins2;
3069
3070                                 /*
3071                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3072                                  * the latter has length 2-3 instead of 6 (reverse constant
3073                                  * propagation). These instruction sequences are very common
3074                                  * in the initlocals bblock.
3075                                  */
3076                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3077                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3078                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3079                                                 ins2->sreg1 = ins->dreg;
3080                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3081                                                 /* Continue */
3082                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3083                                                 NULLIFY_INS (ins2);
3084                                                 /* Continue */
3085                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3086                                                 /* Continue */
3087                                         } else {
3088                                                 break;
3089                                         }
3090                                 }
3091                         }
3092                         break;
3093                 case OP_COMPARE_IMM:
3094                 case OP_LCOMPARE_IMM:
3095                         /* OP_COMPARE_IMM (reg, 0)
3096                          * -->
3097                          * OP_AMD64_TEST_NULL (reg)
3098                          */
3099                         if (!ins->inst_imm)
3100                                 ins->opcode = OP_AMD64_TEST_NULL;
3101                         break;
3102                 case OP_ICOMPARE_IMM:
3103                         if (!ins->inst_imm)
3104                                 ins->opcode = OP_X86_TEST_NULL;
3105                         break;
3106                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3107                         /*
3108                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3109                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3110                          * -->
3111                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3112                          * OP_COMPARE_IMM reg, imm
3113                          *
3114                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3115                          */
3116                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3117                             ins->inst_basereg == last_ins->inst_destbasereg &&
3118                             ins->inst_offset == last_ins->inst_offset) {
3119                                         ins->opcode = OP_ICOMPARE_IMM;
3120                                         ins->sreg1 = last_ins->sreg1;
3121
3122                                         /* check if we can remove cmp reg,0 with test null */
3123                                         if (!ins->inst_imm)
3124                                                 ins->opcode = OP_X86_TEST_NULL;
3125                                 }
3126
3127                         break;
3128                 }
3129
3130                 mono_peephole_ins (bb, ins);
3131         }
3132 }
3133
3134 void
3135 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3136 {
3137         MonoInst *ins, *n;
3138
3139         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3140                 switch (ins->opcode) {
3141                 case OP_ICONST:
3142                 case OP_I8CONST: {
3143                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3144                         /* reg = 0 -> XOR (reg, reg) */
3145                         /* XOR sets cflags on x86, so we cant do it always */
3146                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3147                                 ins->opcode = OP_LXOR;
3148                                 ins->sreg1 = ins->dreg;
3149                                 ins->sreg2 = ins->dreg;
3150                                 /* Fall through */
3151                         } else {
3152                                 break;
3153                         }
3154                 }
3155                 case OP_LXOR:
3156                         /*
3157                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3158                          * 0 result into 64 bits.
3159                          */
3160                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3161                                 ins->opcode = OP_IXOR;
3162                         }
3163                         /* Fall through */
3164                 case OP_IXOR:
3165                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3166                                 MonoInst *ins2;
3167
3168                                 /*
3169                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3170                                  * the latter has length 2-3 instead of 6 (reverse constant
3171                                  * propagation). These instruction sequences are very common
3172                                  * in the initlocals bblock.
3173                                  */
3174                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3175                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3176                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3177                                                 ins2->sreg1 = ins->dreg;
3178                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3179                                                 /* Continue */
3180                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3181                                                 NULLIFY_INS (ins2);
3182                                                 /* Continue */
3183                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3184                                                 /* Continue */
3185                                         } else {
3186                                                 break;
3187                                         }
3188                                 }
3189                         }
3190                         break;
3191                 case OP_IADD_IMM:
3192                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3193                                 ins->opcode = OP_X86_INC_REG;
3194                         break;
3195                 case OP_ISUB_IMM:
3196                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3197                                 ins->opcode = OP_X86_DEC_REG;
3198                         break;
3199                 }
3200
3201                 mono_peephole_ins (bb, ins);
3202         }
3203 }
3204
3205 #define NEW_INS(cfg,ins,dest,op) do {   \
3206                 MONO_INST_NEW ((cfg), (dest), (op)); \
3207         (dest)->cil_code = (ins)->cil_code; \
3208         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3209         } while (0)
3210
3211 /*
3212  * mono_arch_lowering_pass:
3213  *
3214  *  Converts complex opcodes into simpler ones so that each IR instruction
3215  * corresponds to one machine instruction.
3216  */
3217 void
3218 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3219 {
3220         MonoInst *ins, *n, *temp;
3221
3222         /*
3223          * FIXME: Need to add more instructions, but the current machine
3224          * description can't model some parts of the composite instructions like
3225          * cdq.
3226          */
3227         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3228                 switch (ins->opcode) {
3229                 case OP_DIV_IMM:
3230                 case OP_REM_IMM:
3231                 case OP_IDIV_IMM:
3232                 case OP_IDIV_UN_IMM:
3233                 case OP_IREM_UN_IMM:
3234                 case OP_LREM_IMM:
3235                 case OP_IREM_IMM:
3236                         mono_decompose_op_imm (cfg, bb, ins);
3237                         break;
3238                 case OP_COMPARE_IMM:
3239                 case OP_LCOMPARE_IMM:
3240                         if (!amd64_is_imm32 (ins->inst_imm)) {
3241                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3242                                 temp->inst_c0 = ins->inst_imm;
3243                                 temp->dreg = mono_alloc_ireg (cfg);
3244                                 ins->opcode = OP_COMPARE;
3245                                 ins->sreg2 = temp->dreg;
3246                         }
3247                         break;
3248 #ifndef __mono_ilp32__
3249                 case OP_LOAD_MEMBASE:
3250 #endif
3251                 case OP_LOADI8_MEMBASE:
3252 #ifndef __native_client_codegen__
3253                 /*  Don't generate memindex opcodes (to simplify */
3254                 /*  read sandboxing) */
3255                         if (!amd64_is_imm32 (ins->inst_offset)) {
3256                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3257                                 temp->inst_c0 = ins->inst_offset;
3258                                 temp->dreg = mono_alloc_ireg (cfg);
3259                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3260                                 ins->inst_indexreg = temp->dreg;
3261                         }
3262 #endif
3263                         break;
3264 #ifndef __mono_ilp32__
3265                 case OP_STORE_MEMBASE_IMM:
3266 #endif
3267                 case OP_STOREI8_MEMBASE_IMM:
3268                         if (!amd64_is_imm32 (ins->inst_imm)) {
3269                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3270                                 temp->inst_c0 = ins->inst_imm;
3271                                 temp->dreg = mono_alloc_ireg (cfg);
3272                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3273                                 ins->sreg1 = temp->dreg;
3274                         }
3275                         break;
3276 #ifdef MONO_ARCH_SIMD_INTRINSICS
3277                 case OP_EXPAND_I1: {
3278                                 int temp_reg1 = mono_alloc_ireg (cfg);
3279                                 int temp_reg2 = mono_alloc_ireg (cfg);
3280                                 int original_reg = ins->sreg1;
3281
3282                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3283                                 temp->sreg1 = original_reg;
3284                                 temp->dreg = temp_reg1;
3285
3286                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3287                                 temp->sreg1 = temp_reg1;
3288                                 temp->dreg = temp_reg2;
3289                                 temp->inst_imm = 8;
3290
3291                                 NEW_INS (cfg, ins, temp, OP_LOR);
3292                                 temp->sreg1 = temp->dreg = temp_reg2;
3293                                 temp->sreg2 = temp_reg1;
3294
3295                                 ins->opcode = OP_EXPAND_I2;
3296                                 ins->sreg1 = temp_reg2;
3297                         }
3298                         break;
3299 #endif
3300                 default:
3301                         break;
3302                 }
3303         }
3304
3305         bb->max_vreg = cfg->next_vreg;
3306 }
3307
3308 static const int
3309 branch_cc_table [] = {
3310         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3311         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3312         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3313 };
3314
3315 /* Maps CMP_... constants to X86_CC_... constants */
3316 static const int
3317 cc_table [] = {
3318         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3319         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3320 };
3321
3322 static const int
3323 cc_signed_table [] = {
3324         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3325         FALSE, FALSE, FALSE, FALSE
3326 };
3327
3328 /*#include "cprop.c"*/
3329
3330 static unsigned char*
3331 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3332 {
3333         if (size == 8)
3334                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3335         else
3336                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3337
3338         if (size == 1)
3339                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3340         else if (size == 2)
3341                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3342         return code;
3343 }
3344
3345 static unsigned char*
3346 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3347 {
3348         int sreg = tree->sreg1;
3349         int need_touch = FALSE;
3350
3351 #if defined(TARGET_WIN32)
3352         need_touch = TRUE;
3353 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3354         if (!tree->flags & MONO_INST_INIT)
3355                 need_touch = TRUE;
3356 #endif
3357
3358         if (need_touch) {
3359                 guint8* br[5];
3360
3361                 /*
3362                  * Under Windows:
3363                  * If requested stack size is larger than one page,
3364                  * perform stack-touch operation
3365                  */
3366                 /*
3367                  * Generate stack probe code.
3368                  * Under Windows, it is necessary to allocate one page at a time,
3369                  * "touching" stack after each successful sub-allocation. This is
3370                  * because of the way stack growth is implemented - there is a
3371                  * guard page before the lowest stack page that is currently commited.
3372                  * Stack normally grows sequentially so OS traps access to the
3373                  * guard page and commits more pages when needed.
3374                  */
3375                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3376                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3377
3378                 br[2] = code; /* loop */
3379                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3380                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3381                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3382                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3383                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3384                 amd64_patch (br[3], br[2]);
3385                 amd64_test_reg_reg (code, sreg, sreg);
3386                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3387                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3388
3389                 br[1] = code; x86_jump8 (code, 0);
3390
3391                 amd64_patch (br[0], code);
3392                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3393                 amd64_patch (br[1], code);
3394                 amd64_patch (br[4], code);
3395         }
3396         else
3397                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3398
3399         if (tree->flags & MONO_INST_INIT) {
3400                 int offset = 0;
3401                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3402                         amd64_push_reg (code, AMD64_RAX);
3403                         offset += 8;
3404                 }
3405                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3406                         amd64_push_reg (code, AMD64_RCX);
3407                         offset += 8;
3408                 }
3409                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3410                         amd64_push_reg (code, AMD64_RDI);
3411                         offset += 8;
3412                 }
3413
3414                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3415                 if (sreg != AMD64_RCX)
3416                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3417                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3418
3419                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3420                 if (cfg->param_area)
3421                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3422                 amd64_cld (code);
3423 #if defined(__default_codegen__)
3424                 amd64_prefix (code, X86_REP_PREFIX);
3425                 amd64_stosl (code);
3426 #elif defined(__native_client_codegen__)
3427                 /* NaCl stos pseudo-instruction */
3428                 amd64_codegen_pre(code);
3429                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3430                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3431                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3432                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3433                 amd64_prefix (code, X86_REP_PREFIX);
3434                 amd64_stosl (code);
3435                 amd64_codegen_post(code);
3436 #endif /* __native_client_codegen__ */
3437
3438                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3439                         amd64_pop_reg (code, AMD64_RDI);
3440                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3441                         amd64_pop_reg (code, AMD64_RCX);
3442                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3443                         amd64_pop_reg (code, AMD64_RAX);
3444         }
3445         return code;
3446 }
3447
3448 static guint8*
3449 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3450 {
3451         CallInfo *cinfo;
3452         guint32 quad;
3453
3454         /* Move return value to the target register */
3455         /* FIXME: do this in the local reg allocator */
3456         switch (ins->opcode) {
3457         case OP_CALL:
3458         case OP_CALL_REG:
3459         case OP_CALL_MEMBASE:
3460         case OP_LCALL:
3461         case OP_LCALL_REG:
3462         case OP_LCALL_MEMBASE:
3463                 g_assert (ins->dreg == AMD64_RAX);
3464                 break;
3465         case OP_FCALL:
3466         case OP_FCALL_REG:
3467         case OP_FCALL_MEMBASE: {
3468                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3469                 if (rtype->type == MONO_TYPE_R4) {
3470                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3471                 }
3472                 else {
3473                         if (ins->dreg != AMD64_XMM0)
3474                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3475                 }
3476                 break;
3477         }
3478         case OP_RCALL:
3479         case OP_RCALL_REG:
3480         case OP_RCALL_MEMBASE:
3481                 if (ins->dreg != AMD64_XMM0)
3482                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3483                 break;
3484         case OP_VCALL:
3485         case OP_VCALL_REG:
3486         case OP_VCALL_MEMBASE:
3487         case OP_VCALL2:
3488         case OP_VCALL2_REG:
3489         case OP_VCALL2_MEMBASE:
3490                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3491                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3492                         MonoInst *loc = cfg->arch.vret_addr_loc;
3493
3494                         /* Load the destination address */
3495                         g_assert (loc->opcode == OP_REGOFFSET);
3496                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3497
3498                         for (quad = 0; quad < 2; quad ++) {
3499                                 switch (cinfo->ret.pair_storage [quad]) {
3500                                 case ArgInIReg:
3501                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3502                                         break;
3503                                 case ArgInFloatSSEReg:
3504                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3505                                         break;
3506                                 case ArgInDoubleSSEReg:
3507                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3508                                         break;
3509                                 case ArgNone:
3510                                         break;
3511                                 default:
3512                                         NOT_IMPLEMENTED;
3513                                 }
3514                         }
3515                 }
3516                 break;
3517         }
3518
3519         return code;
3520 }
3521
3522 #endif /* DISABLE_JIT */
3523
3524 #ifdef __APPLE__
3525 static int tls_gs_offset;
3526 #endif
3527
3528 gboolean
3529 mono_amd64_have_tls_get (void)
3530 {
3531 #ifdef TARGET_MACH
3532         static gboolean have_tls_get = FALSE;
3533         static gboolean inited = FALSE;
3534         guint8 *ins;
3535
3536         if (inited)
3537                 return have_tls_get;
3538
3539         ins = (guint8*)pthread_getspecific;
3540
3541         /*
3542          * We're looking for these two instructions:
3543          *
3544          * mov    %gs:[offset](,%rdi,8),%rax
3545          * retq
3546          */
3547         have_tls_get = ins [0] == 0x65 &&
3548                        ins [1] == 0x48 &&
3549                        ins [2] == 0x8b &&
3550                        ins [3] == 0x04 &&
3551                        ins [4] == 0xfd &&
3552                        ins [6] == 0x00 &&
3553                        ins [7] == 0x00 &&
3554                        ins [8] == 0x00 &&
3555                        ins [9] == 0xc3;
3556
3557         inited = TRUE;
3558
3559         tls_gs_offset = ins[5];
3560
3561         return have_tls_get;
3562 #elif defined(TARGET_ANDROID)
3563         return FALSE;
3564 #else
3565         return TRUE;
3566 #endif
3567 }
3568
3569 int
3570 mono_amd64_get_tls_gs_offset (void)
3571 {
3572 #ifdef TARGET_OSX
3573         return tls_gs_offset;
3574 #else
3575         g_assert_not_reached ();
3576         return -1;
3577 #endif
3578 }
3579
3580 /*
3581  * mono_amd64_emit_tls_get:
3582  * @code: buffer to store code to
3583  * @dreg: hard register where to place the result
3584  * @tls_offset: offset info
3585  *
3586  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3587  * the dreg register the item in the thread local storage identified
3588  * by tls_offset.
3589  *
3590  * Returns: a pointer to the end of the stored code
3591  */
3592 guint8*
3593 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3594 {
3595 #ifdef TARGET_WIN32
3596         if (tls_offset < 64) {
3597                 x86_prefix (code, X86_GS_PREFIX);
3598                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3599         } else {
3600                 guint8 *buf [16];
3601
3602                 g_assert (tls_offset < 0x440);
3603                 /* Load TEB->TlsExpansionSlots */
3604                 x86_prefix (code, X86_GS_PREFIX);
3605                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3606                 amd64_test_reg_reg (code, dreg, dreg);
3607                 buf [0] = code;
3608                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3609                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3610                 amd64_patch (buf [0], code);
3611         }
3612 #elif defined(__APPLE__)
3613         x86_prefix (code, X86_GS_PREFIX);
3614         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3615 #else
3616         if (optimize_for_xen) {
3617                 x86_prefix (code, X86_FS_PREFIX);
3618                 amd64_mov_reg_mem (code, dreg, 0, 8);
3619                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3620         } else {
3621                 x86_prefix (code, X86_FS_PREFIX);
3622                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3623         }
3624 #endif
3625         return code;
3626 }
3627
3628 static guint8*
3629 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3630 {
3631         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3632 #ifdef TARGET_OSX
3633         if (dreg != offset_reg)
3634                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3635         amd64_prefix (code, X86_GS_PREFIX);
3636         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3637 #elif defined(__linux__)
3638         int tmpreg = -1;
3639
3640         if (dreg == offset_reg) {
3641                 /* Use a temporary reg by saving it to the redzone */
3642                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3643                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3644                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3645                 offset_reg = tmpreg;
3646         }
3647         x86_prefix (code, X86_FS_PREFIX);
3648         amd64_mov_reg_mem (code, dreg, 0, 8);
3649         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3650         if (tmpreg != -1)
3651                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3652 #else
3653         g_assert_not_reached ();
3654 #endif
3655         return code;
3656 }
3657
3658 static guint8*
3659 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3660 {
3661 #ifdef TARGET_WIN32
3662         g_assert_not_reached ();
3663 #elif defined(__APPLE__)
3664         x86_prefix (code, X86_GS_PREFIX);
3665         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3666 #else
3667         g_assert (!optimize_for_xen);
3668         x86_prefix (code, X86_FS_PREFIX);
3669         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3670 #endif
3671         return code;
3672 }
3673
3674 static guint8*
3675 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3676 {
3677         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3678 #ifdef TARGET_WIN32
3679         g_assert_not_reached ();
3680 #elif defined(__APPLE__)
3681         x86_prefix (code, X86_GS_PREFIX);
3682         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3683 #else
3684         x86_prefix (code, X86_FS_PREFIX);
3685         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3686 #endif
3687         return code;
3688 }
3689
3690  /*
3691  * mono_arch_translate_tls_offset:
3692  *
3693  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3694  */
3695 int
3696 mono_arch_translate_tls_offset (int offset)
3697 {
3698 #ifdef __APPLE__
3699         return tls_gs_offset + (offset * 8);
3700 #else
3701         return offset;
3702 #endif
3703 }
3704
3705 /*
3706  * emit_setup_lmf:
3707  *
3708  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3709  */
3710 static guint8*
3711 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3712 {
3713         /*
3714          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3715          */
3716         /*
3717          * sp is saved right before calls but we need to save it here too so
3718          * async stack walks would work.
3719          */
3720         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3721         /* Save rbp */
3722         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3723         if (cfg->arch.omit_fp && cfa_offset != -1)
3724                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3725
3726         /* These can't contain refs */
3727         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3728         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3729         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3730         /* These are handled automatically by the stack marking code */
3731         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3732
3733         return code;
3734 }
3735
3736 #define REAL_PRINT_REG(text,reg) \
3737 mono_assert (reg >= 0); \
3738 amd64_push_reg (code, AMD64_RAX); \
3739 amd64_push_reg (code, AMD64_RDX); \
3740 amd64_push_reg (code, AMD64_RCX); \
3741 amd64_push_reg (code, reg); \
3742 amd64_push_imm (code, reg); \
3743 amd64_push_imm (code, text " %d %p\n"); \
3744 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3745 amd64_call_reg (code, AMD64_RAX); \
3746 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3747 amd64_pop_reg (code, AMD64_RCX); \
3748 amd64_pop_reg (code, AMD64_RDX); \
3749 amd64_pop_reg (code, AMD64_RAX);
3750
3751 /* benchmark and set based on cpu */
3752 #define LOOP_ALIGNMENT 8
3753 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3754
3755 #ifndef DISABLE_JIT
3756 void
3757 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3758 {
3759         MonoInst *ins;
3760         MonoCallInst *call;
3761         guint offset;
3762         guint8 *code = cfg->native_code + cfg->code_len;
3763         int max_len;
3764
3765         /* Fix max_offset estimate for each successor bb */
3766         if (cfg->opt & MONO_OPT_BRANCH) {
3767                 int current_offset = cfg->code_len;
3768                 MonoBasicBlock *current_bb;
3769                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3770                         current_bb->max_offset = current_offset;
3771                         current_offset += current_bb->max_length;
3772                 }
3773         }
3774
3775         if (cfg->opt & MONO_OPT_LOOP) {
3776                 int pad, align = LOOP_ALIGNMENT;
3777                 /* set alignment depending on cpu */
3778                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3779                         pad = align - pad;
3780                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3781                         amd64_padding (code, pad);
3782                         cfg->code_len += pad;
3783                         bb->native_offset = cfg->code_len;
3784                 }
3785         }
3786
3787 #if defined(__native_client_codegen__)
3788         /* For Native Client, all indirect call/jump targets must be */
3789         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3790         /* indirectly as well.                                       */
3791         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3792                                       (bb->flags & BB_EXCEPTION_HANDLER);
3793
3794         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3795                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3796                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3797                 cfg->code_len += pad;
3798                 bb->native_offset = cfg->code_len;
3799         }
3800 #endif  /*__native_client_codegen__*/
3801
3802         if (cfg->verbose_level > 2)
3803                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3804
3805         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3806                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3807                 g_assert (!cfg->compile_aot);
3808
3809                 cov->data [bb->dfn].cil_code = bb->cil_code;
3810                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3811                 /* this is not thread save, but good enough */
3812                 amd64_inc_membase (code, AMD64_R11, 0);
3813         }
3814
3815         offset = code - cfg->native_code;
3816
3817         mono_debug_open_block (cfg, bb, offset);
3818
3819     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3820                 x86_breakpoint (code);
3821
3822         MONO_BB_FOR_EACH_INS (bb, ins) {
3823                 offset = code - cfg->native_code;
3824
3825                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3826
3827 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3828
3829                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3830                         cfg->code_size *= 2;
3831                         cfg->native_code = mono_realloc_native_code(cfg);
3832                         code = cfg->native_code + offset;
3833                         cfg->stat_code_reallocs++;
3834                 }
3835
3836                 if (cfg->debug_info)
3837                         mono_debug_record_line_number (cfg, ins, offset);
3838
3839                 switch (ins->opcode) {
3840                 case OP_BIGMUL:
3841                         amd64_mul_reg (code, ins->sreg2, TRUE);
3842                         break;
3843                 case OP_BIGMUL_UN:
3844                         amd64_mul_reg (code, ins->sreg2, FALSE);
3845                         break;
3846                 case OP_X86_SETEQ_MEMBASE:
3847                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3848                         break;
3849                 case OP_STOREI1_MEMBASE_IMM:
3850                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3851                         break;
3852                 case OP_STOREI2_MEMBASE_IMM:
3853                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3854                         break;
3855                 case OP_STOREI4_MEMBASE_IMM:
3856                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3857                         break;
3858                 case OP_STOREI1_MEMBASE_REG:
3859                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3860                         break;
3861                 case OP_STOREI2_MEMBASE_REG:
3862                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3863                         break;
3864                 /* In AMD64 NaCl, pointers are 4 bytes, */
3865                 /*  so STORE_* != STOREI8_*. Likewise below. */
3866                 case OP_STORE_MEMBASE_REG:
3867                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3868                         break;
3869                 case OP_STOREI8_MEMBASE_REG:
3870                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3871                         break;
3872                 case OP_STOREI4_MEMBASE_REG:
3873                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3874                         break;
3875                 case OP_STORE_MEMBASE_IMM:
3876 #ifndef __native_client_codegen__
3877                         /* In NaCl, this could be a PCONST type, which could */
3878                         /* mean a pointer type was copied directly into the  */
3879                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3880                         /* the value would be 0x00000000FFFFFFFF which is    */
3881                         /* not proper for an imm32 unless you cast it.       */
3882                         g_assert (amd64_is_imm32 (ins->inst_imm));
3883 #endif
3884                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3885                         break;
3886                 case OP_STOREI8_MEMBASE_IMM:
3887                         g_assert (amd64_is_imm32 (ins->inst_imm));
3888                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3889                         break;
3890                 case OP_LOAD_MEM:
3891 #ifdef __mono_ilp32__
3892                         /* In ILP32, pointers are 4 bytes, so separate these */
3893                         /* cases, use literal 8 below where we really want 8 */
3894                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3895                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3896                         break;
3897 #endif
3898                 case OP_LOADI8_MEM:
3899                         // FIXME: Decompose this earlier
3900                         if (amd64_is_imm32 (ins->inst_imm))
3901                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3902                         else {
3903                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3904                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3905                         }
3906                         break;
3907                 case OP_LOADI4_MEM:
3908                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3909                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3910                         break;
3911                 case OP_LOADU4_MEM:
3912                         // FIXME: Decompose this earlier
3913                         if (amd64_is_imm32 (ins->inst_imm))
3914                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3915                         else {
3916                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3917                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3918                         }
3919                         break;
3920                 case OP_LOADU1_MEM:
3921                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3922                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3923                         break;
3924                 case OP_LOADU2_MEM:
3925                         /* For NaCl, pointers are 4 bytes, so separate these */
3926                         /* cases, use literal 8 below where we really want 8 */
3927                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3928                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3929                         break;
3930                 case OP_LOAD_MEMBASE:
3931                         g_assert (amd64_is_imm32 (ins->inst_offset));
3932                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3933                         break;
3934                 case OP_LOADI8_MEMBASE:
3935                         /* Use literal 8 instead of sizeof pointer or */
3936                         /* register, we really want 8 for this opcode */
3937                         g_assert (amd64_is_imm32 (ins->inst_offset));
3938                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3939                         break;
3940                 case OP_LOADI4_MEMBASE:
3941                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3942                         break;
3943                 case OP_LOADU4_MEMBASE:
3944                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3945                         break;
3946                 case OP_LOADU1_MEMBASE:
3947                         /* The cpu zero extends the result into 64 bits */
3948                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3949                         break;
3950                 case OP_LOADI1_MEMBASE:
3951                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3952                         break;
3953                 case OP_LOADU2_MEMBASE:
3954                         /* The cpu zero extends the result into 64 bits */
3955                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3956                         break;
3957                 case OP_LOADI2_MEMBASE:
3958                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3959                         break;
3960                 case OP_AMD64_LOADI8_MEMINDEX:
3961                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3962                         break;
3963                 case OP_LCONV_TO_I1:
3964                 case OP_ICONV_TO_I1:
3965                 case OP_SEXT_I1:
3966                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3967                         break;
3968                 case OP_LCONV_TO_I2:
3969                 case OP_ICONV_TO_I2:
3970                 case OP_SEXT_I2:
3971                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3972                         break;
3973                 case OP_LCONV_TO_U1:
3974                 case OP_ICONV_TO_U1:
3975                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3976                         break;
3977                 case OP_LCONV_TO_U2:
3978                 case OP_ICONV_TO_U2:
3979                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3980                         break;
3981                 case OP_ZEXT_I4:
3982                         /* Clean out the upper word */
3983                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3984                         break;
3985                 case OP_SEXT_I4:
3986                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3987                         break;
3988                 case OP_COMPARE:
3989                 case OP_LCOMPARE:
3990                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3991                         break;
3992                 case OP_COMPARE_IMM:
3993 #if defined(__mono_ilp32__)
3994                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3995                         g_assert (amd64_is_imm32 (ins->inst_imm));
3996                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3997                         break;
3998 #endif
3999                 case OP_LCOMPARE_IMM:
4000                         g_assert (amd64_is_imm32 (ins->inst_imm));
4001                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4002                         break;
4003                 case OP_X86_COMPARE_REG_MEMBASE:
4004                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4005                         break;
4006                 case OP_X86_TEST_NULL:
4007                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4008                         break;
4009                 case OP_AMD64_TEST_NULL:
4010                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4011                         break;
4012
4013                 case OP_X86_ADD_REG_MEMBASE:
4014                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4015                         break;
4016                 case OP_X86_SUB_REG_MEMBASE:
4017                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4018                         break;
4019                 case OP_X86_AND_REG_MEMBASE:
4020                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4021                         break;
4022                 case OP_X86_OR_REG_MEMBASE:
4023                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4024                         break;
4025                 case OP_X86_XOR_REG_MEMBASE:
4026                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4027                         break;
4028
4029                 case OP_X86_ADD_MEMBASE_IMM:
4030                         /* FIXME: Make a 64 version too */
4031                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4032                         break;
4033                 case OP_X86_SUB_MEMBASE_IMM:
4034                         g_assert (amd64_is_imm32 (ins->inst_imm));
4035                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4036                         break;
4037                 case OP_X86_AND_MEMBASE_IMM:
4038                         g_assert (amd64_is_imm32 (ins->inst_imm));
4039                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4040                         break;
4041                 case OP_X86_OR_MEMBASE_IMM:
4042                         g_assert (amd64_is_imm32 (ins->inst_imm));
4043                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4044                         break;
4045                 case OP_X86_XOR_MEMBASE_IMM:
4046                         g_assert (amd64_is_imm32 (ins->inst_imm));
4047                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4048                         break;
4049                 case OP_X86_ADD_MEMBASE_REG:
4050                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4051                         break;
4052                 case OP_X86_SUB_MEMBASE_REG:
4053                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4054                         break;
4055                 case OP_X86_AND_MEMBASE_REG:
4056                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4057                         break;
4058                 case OP_X86_OR_MEMBASE_REG:
4059                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4060                         break;
4061                 case OP_X86_XOR_MEMBASE_REG:
4062                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4063                         break;
4064                 case OP_X86_INC_MEMBASE:
4065                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4066                         break;
4067                 case OP_X86_INC_REG:
4068                         amd64_inc_reg_size (code, ins->dreg, 4);
4069                         break;
4070                 case OP_X86_DEC_MEMBASE:
4071                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4072                         break;
4073                 case OP_X86_DEC_REG:
4074                         amd64_dec_reg_size (code, ins->dreg, 4);
4075                         break;
4076                 case OP_X86_MUL_REG_MEMBASE:
4077                 case OP_X86_MUL_MEMBASE_REG:
4078                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4079                         break;
4080                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4081                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4082                         break;
4083                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4084                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4085                         break;
4086                 case OP_AMD64_COMPARE_MEMBASE_REG:
4087                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4088                         break;
4089                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4090                         g_assert (amd64_is_imm32 (ins->inst_imm));
4091                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092                         break;
4093                 case OP_X86_COMPARE_MEMBASE8_IMM:
4094                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4095                         break;
4096                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4097                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4098                         break;
4099                 case OP_AMD64_COMPARE_REG_MEMBASE:
4100                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4101                         break;
4102
4103                 case OP_AMD64_ADD_REG_MEMBASE:
4104                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4105                         break;
4106                 case OP_AMD64_SUB_REG_MEMBASE:
4107                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4108                         break;
4109                 case OP_AMD64_AND_REG_MEMBASE:
4110                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4111                         break;
4112                 case OP_AMD64_OR_REG_MEMBASE:
4113                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4114                         break;
4115                 case OP_AMD64_XOR_REG_MEMBASE:
4116                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4117                         break;
4118
4119                 case OP_AMD64_ADD_MEMBASE_REG:
4120                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4121                         break;
4122                 case OP_AMD64_SUB_MEMBASE_REG:
4123                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124                         break;
4125                 case OP_AMD64_AND_MEMBASE_REG:
4126                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4127                         break;
4128                 case OP_AMD64_OR_MEMBASE_REG:
4129                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4130                         break;
4131                 case OP_AMD64_XOR_MEMBASE_REG:
4132                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4133                         break;
4134
4135                 case OP_AMD64_ADD_MEMBASE_IMM:
4136                         g_assert (amd64_is_imm32 (ins->inst_imm));
4137                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4138                         break;
4139                 case OP_AMD64_SUB_MEMBASE_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4142                         break;
4143                 case OP_AMD64_AND_MEMBASE_IMM:
4144                         g_assert (amd64_is_imm32 (ins->inst_imm));
4145                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4146                         break;
4147                 case OP_AMD64_OR_MEMBASE_IMM:
4148                         g_assert (amd64_is_imm32 (ins->inst_imm));
4149                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4150                         break;
4151                 case OP_AMD64_XOR_MEMBASE_IMM:
4152                         g_assert (amd64_is_imm32 (ins->inst_imm));
4153                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4154                         break;
4155
4156                 case OP_BREAK:
4157                         amd64_breakpoint (code);
4158                         break;
4159                 case OP_RELAXED_NOP:
4160                         x86_prefix (code, X86_REP_PREFIX);
4161                         x86_nop (code);
4162                         break;
4163                 case OP_HARD_NOP:
4164                         x86_nop (code);
4165                         break;
4166                 case OP_NOP:
4167                 case OP_DUMMY_USE:
4168                 case OP_DUMMY_STORE:
4169                 case OP_DUMMY_ICONST:
4170                 case OP_DUMMY_R8CONST:
4171                 case OP_NOT_REACHED:
4172                 case OP_NOT_NULL:
4173                         break;
4174                 case OP_IL_SEQ_POINT:
4175                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4176                         break;
4177                 case OP_SEQ_POINT: {
4178                         int i;
4179
4180                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4181                                 if (cfg->compile_aot) {
4182                                         MonoInst *var = cfg->arch.ss_tramp_var;
4183                                         guint8 *label;
4184
4185                                         /* Load ss_tramp_var */
4186                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4187                                         /* Load the trampoline address */
4188                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4189                                         /* Call it if it is non-null */
4190                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4191                                         label = code;
4192                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4193                                         amd64_call_reg (code, AMD64_R11);
4194                                         amd64_patch (label, code);
4195                                 } else {
4196                                         /*
4197                                          * Read from the single stepping trigger page. This will cause a
4198                                          * SIGSEGV when single stepping is enabled.
4199                                          * We do this _before_ the breakpoint, so single stepping after
4200                                          * a breakpoint is hit will step to the next IL offset.
4201                                          */
4202                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4203
4204                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4205                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4206                                 }
4207                         }
4208
4209                         /*
4210                          * This is the address which is saved in seq points,
4211                          */
4212                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4213
4214                         if (cfg->compile_aot) {
4215                                 guint32 offset = code - cfg->native_code;
4216                                 guint32 val;
4217                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4218                                 guint8 *label;
4219
4220                                 /* Load info var */
4221                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4222                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4223                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4224                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4225                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4226                                 label = code;
4227                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4228                                 /* Call the trampoline */
4229                                 amd64_call_reg (code, AMD64_R11);
4230                                 amd64_patch (label, code);
4231                         } else {
4232                                 /*
4233                                  * A placeholder for a possible breakpoint inserted by
4234                                  * mono_arch_set_breakpoint ().
4235                                  */
4236                                 for (i = 0; i < breakpoint_size; ++i)
4237                                         x86_nop (code);
4238                         }
4239                         /*
4240                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4241                          * to another IL offset.
4242                          */
4243                         x86_nop (code);
4244                         break;
4245                 }
4246                 case OP_ADDCC:
4247                 case OP_LADDCC:
4248                 case OP_LADD:
4249                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4250                         break;
4251                 case OP_ADC:
4252                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4253                         break;
4254                 case OP_ADD_IMM:
4255                 case OP_LADD_IMM:
4256                         g_assert (amd64_is_imm32 (ins->inst_imm));
4257                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4258                         break;
4259                 case OP_ADC_IMM:
4260                         g_assert (amd64_is_imm32 (ins->inst_imm));
4261                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4262                         break;
4263                 case OP_SUBCC:
4264                 case OP_LSUBCC:
4265                 case OP_LSUB:
4266                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4267                         break;
4268                 case OP_SBB:
4269                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4270                         break;
4271                 case OP_SUB_IMM:
4272                 case OP_LSUB_IMM:
4273                         g_assert (amd64_is_imm32 (ins->inst_imm));
4274                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4275                         break;
4276                 case OP_SBB_IMM:
4277                         g_assert (amd64_is_imm32 (ins->inst_imm));
4278                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4279                         break;
4280                 case OP_LAND:
4281                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4282                         break;
4283                 case OP_AND_IMM:
4284                 case OP_LAND_IMM:
4285                         g_assert (amd64_is_imm32 (ins->inst_imm));
4286                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4287                         break;
4288                 case OP_LMUL:
4289                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4290                         break;
4291                 case OP_MUL_IMM:
4292                 case OP_LMUL_IMM:
4293                 case OP_IMUL_IMM: {
4294                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4295
4296                         switch (ins->inst_imm) {
4297                         case 2:
4298                                 /* MOV r1, r2 */
4299                                 /* ADD r1, r1 */
4300                                 if (ins->dreg != ins->sreg1)
4301                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4302                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4303                                 break;
4304                         case 3:
4305                                 /* LEA r1, [r2 + r2*2] */
4306                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4307                                 break;
4308                         case 5:
4309                                 /* LEA r1, [r2 + r2*4] */
4310                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4311                                 break;
4312                         case 6:
4313                                 /* LEA r1, [r2 + r2*2] */
4314                                 /* ADD r1, r1          */
4315                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4316                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4317                                 break;
4318                         case 9:
4319                                 /* LEA r1, [r2 + r2*8] */
4320                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4321                                 break;
4322                         case 10:
4323                                 /* LEA r1, [r2 + r2*4] */
4324                                 /* ADD r1, r1          */
4325                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4326                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4327                                 break;
4328                         case 12:
4329                                 /* LEA r1, [r2 + r2*2] */
4330                                 /* SHL r1, 2           */
4331                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4332                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4333                                 break;
4334                         case 25:
4335                                 /* LEA r1, [r2 + r2*4] */
4336                                 /* LEA r1, [r1 + r1*4] */
4337                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4338                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4339                                 break;
4340                         case 100:
4341                                 /* LEA r1, [r2 + r2*4] */
4342                                 /* SHL r1, 2           */
4343                                 /* LEA r1, [r1 + r1*4] */
4344                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4345                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4346                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4347                                 break;
4348                         default:
4349                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4350                                 break;
4351                         }
4352                         break;
4353                 }
4354                 case OP_LDIV:
4355                 case OP_LREM:
4356 #if defined( __native_client_codegen__ )
4357                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4358                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4359 #endif
4360                         /* Regalloc magic makes the div/rem cases the same */
4361                         if (ins->sreg2 == AMD64_RDX) {
4362                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4363                                 amd64_cdq (code);
4364                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4365                         } else {
4366                                 amd64_cdq (code);
4367                                 amd64_div_reg (code, ins->sreg2, TRUE);
4368                         }
4369                         break;
4370                 case OP_LDIV_UN:
4371                 case OP_LREM_UN:
4372 #if defined( __native_client_codegen__ )
4373                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4374                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4375 #endif
4376                         if (ins->sreg2 == AMD64_RDX) {
4377                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4378                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4379                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4380                         } else {
4381                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4382                                 amd64_div_reg (code, ins->sreg2, FALSE);
4383                         }
4384                         break;
4385                 case OP_IDIV:
4386                 case OP_IREM:
4387 #if defined( __native_client_codegen__ )
4388                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4389                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4390 #endif
4391                         if (ins->sreg2 == AMD64_RDX) {
4392                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4393                                 amd64_cdq_size (code, 4);
4394                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4395                         } else {
4396                                 amd64_cdq_size (code, 4);
4397                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4398                         }
4399                         break;
4400                 case OP_IDIV_UN:
4401                 case OP_IREM_UN:
4402 #if defined( __native_client_codegen__ )
4403                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4404                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4405 #endif
4406                         if (ins->sreg2 == AMD64_RDX) {
4407                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4408                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4409                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4410                         } else {
4411                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4412                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4413                         }
4414                         break;
4415                 case OP_LMUL_OVF:
4416                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4417                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4418                         break;
4419                 case OP_LOR:
4420                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4421                         break;
4422                 case OP_OR_IMM:
4423                 case OP_LOR_IMM:
4424                         g_assert (amd64_is_imm32 (ins->inst_imm));
4425                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4426                         break;
4427                 case OP_LXOR:
4428                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4429                         break;
4430                 case OP_XOR_IMM:
4431                 case OP_LXOR_IMM:
4432                         g_assert (amd64_is_imm32 (ins->inst_imm));
4433                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4434                         break;
4435                 case OP_LSHL:
4436                         g_assert (ins->sreg2 == AMD64_RCX);
4437                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4438                         break;
4439                 case OP_LSHR:
4440                         g_assert (ins->sreg2 == AMD64_RCX);
4441                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4442                         break;
4443                 case OP_SHR_IMM:
4444                 case OP_LSHR_IMM:
4445                         g_assert (amd64_is_imm32 (ins->inst_imm));
4446                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4447                         break;
4448                 case OP_SHR_UN_IMM:
4449                         g_assert (amd64_is_imm32 (ins->inst_imm));
4450                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4451                         break;
4452                 case OP_LSHR_UN_IMM:
4453                         g_assert (amd64_is_imm32 (ins->inst_imm));
4454                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4455                         break;
4456                 case OP_LSHR_UN:
4457                         g_assert (ins->sreg2 == AMD64_RCX);
4458                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4459                         break;
4460                 case OP_SHL_IMM:
4461                 case OP_LSHL_IMM:
4462                         g_assert (amd64_is_imm32 (ins->inst_imm));
4463                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4464                         break;
4465
4466                 case OP_IADDCC:
4467                 case OP_IADD:
4468                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4469                         break;
4470                 case OP_IADC:
4471                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4472                         break;
4473                 case OP_IADD_IMM:
4474                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4475                         break;
4476                 case OP_IADC_IMM:
4477                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4478                         break;
4479                 case OP_ISUBCC:
4480                 case OP_ISUB:
4481                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4482                         break;
4483                 case OP_ISBB:
4484                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4485                         break;
4486                 case OP_ISUB_IMM:
4487                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4488                         break;
4489                 case OP_ISBB_IMM:
4490                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4491                         break;
4492                 case OP_IAND:
4493                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4494                         break;
4495                 case OP_IAND_IMM:
4496                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4497                         break;
4498                 case OP_IOR:
4499                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4500                         break;
4501                 case OP_IOR_IMM:
4502                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4503                         break;
4504                 case OP_IXOR:
4505                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4506                         break;
4507                 case OP_IXOR_IMM:
4508                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4509                         break;
4510                 case OP_INEG:
4511                         amd64_neg_reg_size (code, ins->sreg1, 4);
4512                         break;
4513                 case OP_INOT:
4514                         amd64_not_reg_size (code, ins->sreg1, 4);
4515                         break;
4516                 case OP_ISHL:
4517                         g_assert (ins->sreg2 == AMD64_RCX);
4518                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4519                         break;
4520                 case OP_ISHR:
4521                         g_assert (ins->sreg2 == AMD64_RCX);
4522                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4523                         break;
4524                 case OP_ISHR_IMM:
4525                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4526                         break;
4527                 case OP_ISHR_UN_IMM:
4528                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4529                         break;
4530                 case OP_ISHR_UN:
4531                         g_assert (ins->sreg2 == AMD64_RCX);
4532                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4533                         break;
4534                 case OP_ISHL_IMM:
4535                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4536                         break;
4537                 case OP_IMUL:
4538                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4539                         break;
4540                 case OP_IMUL_OVF:
4541                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4542                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4543                         break;
4544                 case OP_IMUL_OVF_UN:
4545                 case OP_LMUL_OVF_UN: {
4546                         /* the mul operation and the exception check should most likely be split */
4547                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4548                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4549                         /*g_assert (ins->sreg2 == X86_EAX);
4550                         g_assert (ins->dreg == X86_EAX);*/
4551                         if (ins->sreg2 == X86_EAX) {
4552                                 non_eax_reg = ins->sreg1;
4553                         } else if (ins->sreg1 == X86_EAX) {
4554                                 non_eax_reg = ins->sreg2;
4555                         } else {
4556                                 /* no need to save since we're going to store to it anyway */
4557                                 if (ins->dreg != X86_EAX) {
4558                                         saved_eax = TRUE;
4559                                         amd64_push_reg (code, X86_EAX);
4560                                 }
4561                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4562                                 non_eax_reg = ins->sreg2;
4563                         }
4564                         if (ins->dreg == X86_EDX) {
4565                                 if (!saved_eax) {
4566                                         saved_eax = TRUE;
4567                                         amd64_push_reg (code, X86_EAX);
4568                                 }
4569                         } else {
4570                                 saved_edx = TRUE;
4571                                 amd64_push_reg (code, X86_EDX);
4572                         }
4573                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4574                         /* save before the check since pop and mov don't change the flags */
4575                         if (ins->dreg != X86_EAX)
4576                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4577                         if (saved_edx)
4578                                 amd64_pop_reg (code, X86_EDX);
4579                         if (saved_eax)
4580                                 amd64_pop_reg (code, X86_EAX);
4581                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4582                         break;
4583                 }
4584                 case OP_ICOMPARE:
4585                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4586                         break;
4587                 case OP_ICOMPARE_IMM:
4588                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4589                         break;
4590                 case OP_IBEQ:
4591                 case OP_IBLT:
4592                 case OP_IBGT:
4593                 case OP_IBGE:
4594                 case OP_IBLE:
4595                 case OP_LBEQ:
4596                 case OP_LBLT:
4597                 case OP_LBGT:
4598                 case OP_LBGE:
4599                 case OP_LBLE:
4600                 case OP_IBNE_UN:
4601                 case OP_IBLT_UN:
4602                 case OP_IBGT_UN:
4603                 case OP_IBGE_UN:
4604                 case OP_IBLE_UN:
4605                 case OP_LBNE_UN:
4606                 case OP_LBLT_UN:
4607                 case OP_LBGT_UN:
4608                 case OP_LBGE_UN:
4609                 case OP_LBLE_UN:
4610                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4611                         break;
4612
4613                 case OP_CMOV_IEQ:
4614                 case OP_CMOV_IGE:
4615                 case OP_CMOV_IGT:
4616                 case OP_CMOV_ILE:
4617                 case OP_CMOV_ILT:
4618                 case OP_CMOV_INE_UN:
4619                 case OP_CMOV_IGE_UN:
4620                 case OP_CMOV_IGT_UN:
4621                 case OP_CMOV_ILE_UN:
4622                 case OP_CMOV_ILT_UN:
4623                 case OP_CMOV_LEQ:
4624                 case OP_CMOV_LGE:
4625                 case OP_CMOV_LGT:
4626                 case OP_CMOV_LLE:
4627                 case OP_CMOV_LLT:
4628                 case OP_CMOV_LNE_UN:
4629                 case OP_CMOV_LGE_UN:
4630                 case OP_CMOV_LGT_UN:
4631                 case OP_CMOV_LLE_UN:
4632                 case OP_CMOV_LLT_UN:
4633                         g_assert (ins->dreg == ins->sreg1);
4634                         /* This needs to operate on 64 bit values */
4635                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4636                         break;
4637
4638                 case OP_LNOT:
4639                         amd64_not_reg (code, ins->sreg1);
4640                         break;
4641                 case OP_LNEG:
4642                         amd64_neg_reg (code, ins->sreg1);
4643                         break;
4644
4645                 case OP_ICONST:
4646                 case OP_I8CONST:
4647                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4648                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4649                         else
4650                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4651                         break;
4652                 case OP_AOTCONST:
4653                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4654                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4655                         break;
4656                 case OP_JUMP_TABLE:
4657                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4658                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4659                         break;
4660                 case OP_MOVE:
4661                         if (ins->dreg != ins->sreg1)
4662                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4663                         break;
4664                 case OP_AMD64_SET_XMMREG_R4: {
4665                         if (cfg->r4fp) {
4666                                 if (ins->dreg != ins->sreg1)
4667                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4668                         } else {
4669                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4670                         }
4671                         break;
4672                 }
4673                 case OP_AMD64_SET_XMMREG_R8: {
4674                         if (ins->dreg != ins->sreg1)
4675                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4676                         break;
4677                 }
4678                 case OP_TAILCALL: {
4679                         MonoCallInst *call = (MonoCallInst*)ins;
4680                         int i, save_area_offset;
4681
4682                         g_assert (!cfg->method->save_lmf);
4683
4684                         /* Restore callee saved registers */
4685                         save_area_offset = cfg->arch.reg_save_area_offset;
4686                         for (i = 0; i < AMD64_NREG; ++i)
4687                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4688                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4689                                         save_area_offset += 8;
4690                                 }
4691
4692                         if (cfg->arch.omit_fp) {
4693                                 if (cfg->arch.stack_alloc_size)
4694                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4695                                 // FIXME:
4696                                 if (call->stack_usage)
4697                                         NOT_IMPLEMENTED;
4698                         } else {
4699                                 /* Copy arguments on the stack to our argument area */
4700                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4701                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4702                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4703                                 }
4704
4705                                 amd64_leave (code);
4706                         }
4707
4708                         offset = code - cfg->native_code;
4709                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4710                         if (cfg->compile_aot)
4711                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4712                         else
4713                                 amd64_set_reg_template (code, AMD64_R11);
4714                         amd64_jump_reg (code, AMD64_R11);
4715                         ins->flags |= MONO_INST_GC_CALLSITE;
4716                         ins->backend.pc_offset = code - cfg->native_code;
4717                         break;
4718                 }
4719                 case OP_CHECK_THIS:
4720                         /* ensure ins->sreg1 is not NULL */
4721                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4722                         break;
4723                 case OP_ARGLIST: {
4724                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4725                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4726                         break;
4727                 }
4728                 case OP_CALL:
4729                 case OP_FCALL:
4730                 case OP_RCALL:
4731                 case OP_LCALL:
4732                 case OP_VCALL:
4733                 case OP_VCALL2:
4734                 case OP_VOIDCALL:
4735                         call = (MonoCallInst*)ins;
4736                         /*
4737                          * The AMD64 ABI forces callers to know about varargs.
4738                          */
4739                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4740                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4741                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4742                                 /*
4743                                  * Since the unmanaged calling convention doesn't contain a
4744                                  * 'vararg' entry, we have to treat every pinvoke call as a
4745                                  * potential vararg call.
4746                                  */
4747                                 guint32 nregs, i;
4748                                 nregs = 0;
4749                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4750                                         if (call->used_fregs & (1 << i))
4751                                                 nregs ++;
4752                                 if (!nregs)
4753                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4754                                 else
4755                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4756                         }
4757
4758                         if (ins->flags & MONO_INST_HAS_METHOD)
4759                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4760                         else
4761                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4762                         ins->flags |= MONO_INST_GC_CALLSITE;
4763                         ins->backend.pc_offset = code - cfg->native_code;
4764                         code = emit_move_return_value (cfg, ins, code);
4765                         break;
4766                 case OP_FCALL_REG:
4767                 case OP_RCALL_REG:
4768                 case OP_LCALL_REG:
4769                 case OP_VCALL_REG:
4770                 case OP_VCALL2_REG:
4771                 case OP_VOIDCALL_REG:
4772                 case OP_CALL_REG:
4773                         call = (MonoCallInst*)ins;
4774
4775                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4776                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4777                                 ins->sreg1 = AMD64_R11;
4778                         }
4779
4780                         /*
4781                          * The AMD64 ABI forces callers to know about varargs.
4782                          */
4783                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4784                                 if (ins->sreg1 == AMD64_RAX) {
4785                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4786                                         ins->sreg1 = AMD64_R11;
4787                                 }
4788                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4789                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4790                                 /*
4791                                  * Since the unmanaged calling convention doesn't contain a
4792                                  * 'vararg' entry, we have to treat every pinvoke call as a
4793                                  * potential vararg call.
4794                                  */
4795                                 guint32 nregs, i;
4796                                 nregs = 0;
4797                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4798                                         if (call->used_fregs & (1 << i))
4799                                                 nregs ++;
4800                                 if (ins->sreg1 == AMD64_RAX) {
4801                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4802                                         ins->sreg1 = AMD64_R11;
4803                                 }
4804                                 if (!nregs)
4805                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4806                                 else
4807                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4808                         }
4809
4810                         amd64_call_reg (code, ins->sreg1);
4811                         ins->flags |= MONO_INST_GC_CALLSITE;
4812                         ins->backend.pc_offset = code - cfg->native_code;
4813                         code = emit_move_return_value (cfg, ins, code);
4814                         break;
4815                 case OP_FCALL_MEMBASE:
4816                 case OP_RCALL_MEMBASE:
4817                 case OP_LCALL_MEMBASE:
4818                 case OP_VCALL_MEMBASE:
4819                 case OP_VCALL2_MEMBASE:
4820                 case OP_VOIDCALL_MEMBASE:
4821                 case OP_CALL_MEMBASE:
4822                         call = (MonoCallInst*)ins;
4823
4824                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4825                         ins->flags |= MONO_INST_GC_CALLSITE;
4826                         ins->backend.pc_offset = code - cfg->native_code;
4827                         code = emit_move_return_value (cfg, ins, code);
4828                         break;
4829                 case OP_DYN_CALL: {
4830                         int i;
4831                         MonoInst *var = cfg->dyn_call_var;
4832
4833                         g_assert (var->opcode == OP_REGOFFSET);
4834
4835                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4836                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4837                         /* r10 = ftn */
4838                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4839
4840                         /* Save args buffer */
4841                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4842
4843                         /* Set argument registers */
4844                         for (i = 0; i < PARAM_REGS; ++i)
4845                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4846
4847                         /* Make the call */
4848                         amd64_call_reg (code, AMD64_R10);
4849
4850                         ins->flags |= MONO_INST_GC_CALLSITE;
4851                         ins->backend.pc_offset = code - cfg->native_code;
4852
4853                         /* Save result */
4854                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4855                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4856                         break;
4857                 }
4858                 case OP_AMD64_SAVE_SP_TO_LMF: {
4859                         MonoInst *lmf_var = cfg->lmf_var;
4860                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4861                         break;
4862                 }
4863                 case OP_X86_PUSH:
4864                         g_assert_not_reached ();
4865                         amd64_push_reg (code, ins->sreg1);
4866                         break;
4867                 case OP_X86_PUSH_IMM:
4868                         g_assert_not_reached ();
4869                         g_assert (amd64_is_imm32 (ins->inst_imm));
4870                         amd64_push_imm (code, ins->inst_imm);
4871                         break;
4872                 case OP_X86_PUSH_MEMBASE:
4873                         g_assert_not_reached ();
4874                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4875                         break;
4876                 case OP_X86_PUSH_OBJ: {
4877                         int size = ALIGN_TO (ins->inst_imm, 8);
4878
4879                         g_assert_not_reached ();
4880
4881                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4882                         amd64_push_reg (code, AMD64_RDI);
4883                         amd64_push_reg (code, AMD64_RSI);
4884                         amd64_push_reg (code, AMD64_RCX);
4885                         if (ins->inst_offset)
4886                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4887                         else
4888                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4889                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4890                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4891                         amd64_cld (code);
4892                         amd64_prefix (code, X86_REP_PREFIX);
4893                         amd64_movsd (code);
4894                         amd64_pop_reg (code, AMD64_RCX);
4895                         amd64_pop_reg (code, AMD64_RSI);
4896                         amd64_pop_reg (code, AMD64_RDI);
4897                         break;
4898                 }
4899                 case OP_X86_LEA:
4900                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4901                         break;
4902                 case OP_X86_LEA_MEMBASE:
4903                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4904                         break;
4905                 case OP_X86_XCHG:
4906                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4907                         break;
4908                 case OP_LOCALLOC:
4909                         /* keep alignment */
4910                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4911                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4912                         code = mono_emit_stack_alloc (cfg, code, ins);
4913                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4914                         if (cfg->param_area)
4915                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4916                         break;
4917                 case OP_LOCALLOC_IMM: {
4918                         guint32 size = ins->inst_imm;
4919                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4920
4921                         if (ins->flags & MONO_INST_INIT) {
4922                                 if (size < 64) {
4923                                         int i;
4924
4925                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4926                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4927
4928                                         for (i = 0; i < size; i += 8)
4929                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4930                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4931                                 } else {
4932                                         amd64_mov_reg_imm (code, ins->dreg, size);
4933                                         ins->sreg1 = ins->dreg;
4934
4935                                         code = mono_emit_stack_alloc (cfg, code, ins);
4936                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4937                                 }
4938                         } else {
4939                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4940                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4941                         }
4942                         if (cfg->param_area)
4943                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4944                         break;
4945                 }
4946                 case OP_THROW: {
4947                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4948                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4949                                              (gpointer)"mono_arch_throw_exception", FALSE);
4950                         ins->flags |= MONO_INST_GC_CALLSITE;
4951                         ins->backend.pc_offset = code - cfg->native_code;
4952                         break;
4953                 }
4954                 case OP_RETHROW: {
4955                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4956                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4957                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4958                         ins->flags |= MONO_INST_GC_CALLSITE;
4959                         ins->backend.pc_offset = code - cfg->native_code;
4960                         break;
4961                 }
4962                 case OP_CALL_HANDLER:
4963                         /* Align stack */
4964                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4965                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4966                         amd64_call_imm (code, 0);
4967                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4968                         /* Restore stack alignment */
4969                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4970                         break;
4971                 case OP_START_HANDLER: {
4972                         /* Even though we're saving RSP, use sizeof */
4973                         /* gpointer because spvar is of type IntPtr */
4974                         /* see: mono_create_spvar_for_region */
4975                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4976                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4977
4978                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4979                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4980                                 cfg->param_area) {
4981                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4982                         }
4983                         break;
4984                 }
4985                 case OP_ENDFINALLY: {
4986                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4987                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4988                         amd64_ret (code);
4989                         break;
4990                 }
4991                 case OP_ENDFILTER: {
4992                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4993                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4994                         /* The local allocator will put the result into RAX */
4995                         amd64_ret (code);
4996                         break;
4997                 }
4998                 case OP_GET_EX_OBJ:
4999                         if (ins->dreg != AMD64_RAX)
5000                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5001                         break;
5002                 case OP_LABEL:
5003                         ins->inst_c0 = code - cfg->native_code;
5004                         break;
5005                 case OP_BR:
5006                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5007                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5008                         //break;
5009                                 if (ins->inst_target_bb->native_offset) {
5010                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5011                                 } else {
5012                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5013                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5014                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5015                                                 x86_jump8 (code, 0);
5016                                         else
5017                                                 x86_jump32 (code, 0);
5018                         }
5019                         break;
5020                 case OP_BR_REG:
5021                         amd64_jump_reg (code, ins->sreg1);
5022                         break;
5023                 case OP_ICNEQ:
5024                 case OP_ICGE:
5025                 case OP_ICLE:
5026                 case OP_ICGE_UN:
5027                 case OP_ICLE_UN:
5028
5029                 case OP_CEQ:
5030                 case OP_LCEQ:
5031                 case OP_ICEQ:
5032                 case OP_CLT:
5033                 case OP_LCLT:
5034                 case OP_ICLT:
5035                 case OP_CGT:
5036                 case OP_ICGT:
5037                 case OP_LCGT:
5038                 case OP_CLT_UN:
5039                 case OP_LCLT_UN:
5040                 case OP_ICLT_UN:
5041                 case OP_CGT_UN:
5042                 case OP_LCGT_UN:
5043                 case OP_ICGT_UN:
5044                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5045                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5046                         break;
5047                 case OP_COND_EXC_EQ:
5048                 case OP_COND_EXC_NE_UN:
5049                 case OP_COND_EXC_LT:
5050                 case OP_COND_EXC_LT_UN:
5051                 case OP_COND_EXC_GT:
5052                 case OP_COND_EXC_GT_UN:
5053                 case OP_COND_EXC_GE:
5054                 case OP_COND_EXC_GE_UN:
5055                 case OP_COND_EXC_LE:
5056                 case OP_COND_EXC_LE_UN:
5057                 case OP_COND_EXC_IEQ:
5058                 case OP_COND_EXC_INE_UN:
5059                 case OP_COND_EXC_ILT:
5060                 case OP_COND_EXC_ILT_UN:
5061                 case OP_COND_EXC_IGT:
5062                 case OP_COND_EXC_IGT_UN:
5063                 case OP_COND_EXC_IGE:
5064                 case OP_COND_EXC_IGE_UN:
5065                 case OP_COND_EXC_ILE:
5066                 case OP_COND_EXC_ILE_UN:
5067                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5068                         break;
5069                 case OP_COND_EXC_OV:
5070                 case OP_COND_EXC_NO:
5071                 case OP_COND_EXC_C:
5072                 case OP_COND_EXC_NC:
5073                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5074                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5075                         break;
5076                 case OP_COND_EXC_IOV:
5077                 case OP_COND_EXC_INO:
5078                 case OP_COND_EXC_IC:
5079                 case OP_COND_EXC_INC:
5080                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5081                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5082                         break;
5083
5084                 /* floating point opcodes */
5085                 case OP_R8CONST: {
5086                         double d = *(double *)ins->inst_p0;
5087
5088                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5089                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5090                         }
5091                         else {
5092                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5093                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5094                         }
5095                         break;
5096                 }
5097                 case OP_R4CONST: {
5098                         float f = *(float *)ins->inst_p0;
5099
5100                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5101                                 if (cfg->r4fp)
5102                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5103                                 else
5104                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5105                         }
5106                         else {
5107                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5108                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5109                                 if (!cfg->r4fp)
5110                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5111                         }
5112                         break;
5113                 }
5114                 case OP_STORER8_MEMBASE_REG:
5115                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5116                         break;
5117                 case OP_LOADR8_MEMBASE:
5118                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5119                         break;
5120                 case OP_STORER4_MEMBASE_REG:
5121                         if (cfg->r4fp) {
5122                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5123                         } else {
5124                                 /* This requires a double->single conversion */
5125                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5126                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5127                         }
5128                         break;
5129                 case OP_LOADR4_MEMBASE:
5130                         if (cfg->r4fp) {
5131                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5132                         } else {
5133                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5134                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5135                         }
5136                         break;
5137                 case OP_ICONV_TO_R4:
5138                         if (cfg->r4fp) {
5139                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5140                         } else {
5141                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5142                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5143                         }
5144                         break;
5145                 case OP_ICONV_TO_R8:
5146                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5147                         break;
5148                 case OP_LCONV_TO_R4:
5149                         if (cfg->r4fp) {
5150                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5151                         } else {
5152                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5153                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5154                         }
5155                         break;
5156                 case OP_LCONV_TO_R8:
5157                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5158                         break;
5159                 case OP_FCONV_TO_R4:
5160                         if (cfg->r4fp) {
5161                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5162                         } else {
5163                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5164                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5165                         }
5166                         break;
5167                 case OP_FCONV_TO_I1:
5168                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5169                         break;
5170                 case OP_FCONV_TO_U1:
5171                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5172                         break;
5173                 case OP_FCONV_TO_I2:
5174                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5175                         break;
5176                 case OP_FCONV_TO_U2:
5177                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5178                         break;
5179                 case OP_FCONV_TO_U4:
5180                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5181                         break;
5182                 case OP_FCONV_TO_I4:
5183                 case OP_FCONV_TO_I:
5184                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5185                         break;
5186                 case OP_FCONV_TO_I8:
5187                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5188                         break;
5189
5190                 case OP_RCONV_TO_I1:
5191                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5192                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5193                         break;
5194                 case OP_RCONV_TO_U1:
5195                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5196                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5197                         break;
5198                 case OP_RCONV_TO_I2:
5199                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5200                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5201                         break;
5202                 case OP_RCONV_TO_U2:
5203                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5204                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5205                         break;
5206                 case OP_RCONV_TO_I4:
5207                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5208                         break;
5209                 case OP_RCONV_TO_U4:
5210                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5211                         break;
5212                 case OP_RCONV_TO_I8:
5213                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5214                         break;
5215                 case OP_RCONV_TO_R8:
5216                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5217                         break;
5218                 case OP_RCONV_TO_R4:
5219                         if (ins->dreg != ins->sreg1)
5220                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5221                         break;
5222
5223                 case OP_LCONV_TO_R_UN: {
5224                         guint8 *br [2];
5225
5226                         /* Based on gcc code */
5227                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5228                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5229
5230                         /* Positive case */
5231                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5232                         br [1] = code; x86_jump8 (code, 0);
5233                         amd64_patch (br [0], code);
5234
5235                         /* Negative case */
5236                         /* Save to the red zone */
5237                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5238                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5239                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5240                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5241                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5242                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5243                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5244                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5245                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5246                         /* Restore */
5247                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5248                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5249                         amd64_patch (br [1], code);
5250                         break;
5251                 }
5252                 case OP_LCONV_TO_OVF_U4:
5253                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5254                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5255                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5256                         break;
5257                 case OP_LCONV_TO_OVF_I4_UN:
5258                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5259                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5260                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5261                         break;
5262                 case OP_FMOVE:
5263                         if (ins->dreg != ins->sreg1)
5264                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5265                         break;
5266                 case OP_RMOVE:
5267                         if (ins->dreg != ins->sreg1)
5268                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5269                         break;
5270                 case OP_MOVE_F_TO_I4:
5271                         if (cfg->r4fp) {
5272                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5273                         } else {
5274                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5275                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5276                         }
5277                         break;
5278                 case OP_MOVE_I4_TO_F:
5279                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5280                         if (!cfg->r4fp)
5281                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5282                         break;
5283                 case OP_MOVE_F_TO_I8:
5284                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5285                         break;
5286                 case OP_MOVE_I8_TO_F:
5287                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5288                         break;
5289                 case OP_FADD:
5290                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5291                         break;
5292                 case OP_FSUB:
5293                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5294                         break;
5295                 case OP_FMUL:
5296                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5297                         break;
5298                 case OP_FDIV:
5299                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5300                         break;
5301                 case OP_FNEG: {
5302                         static double r8_0 = -0.0;
5303
5304                         g_assert (ins->sreg1 == ins->dreg);
5305
5306                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5307                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5308                         break;
5309                 }
5310                 case OP_SIN:
5311                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5312                         break;
5313                 case OP_COS:
5314                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5315                         break;
5316                 case OP_ABS: {
5317                         static guint64 d = 0x7fffffffffffffffUL;
5318
5319                         g_assert (ins->sreg1 == ins->dreg);
5320
5321                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5322                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5323                         break;
5324                 }
5325                 case OP_SQRT:
5326                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5327                         break;
5328
5329                 case OP_RADD:
5330                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5331                         break;
5332                 case OP_RSUB:
5333                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5334                         break;
5335                 case OP_RMUL:
5336                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5337                         break;
5338                 case OP_RDIV:
5339                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5340                         break;
5341                 case OP_RNEG: {
5342                         static float r4_0 = -0.0;
5343
5344                         g_assert (ins->sreg1 == ins->dreg);
5345
5346                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5347                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5348                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5349                         break;
5350                 }
5351
5352                 case OP_IMIN:
5353                         g_assert (cfg->opt & MONO_OPT_CMOV);
5354                         g_assert (ins->dreg == ins->sreg1);
5355                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5356                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5357                         break;
5358                 case OP_IMIN_UN:
5359                         g_assert (cfg->opt & MONO_OPT_CMOV);
5360                         g_assert (ins->dreg == ins->sreg1);
5361                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5362                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5363                         break;
5364                 case OP_IMAX:
5365                         g_assert (cfg->opt & MONO_OPT_CMOV);
5366                         g_assert (ins->dreg == ins->sreg1);
5367                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5368                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5369                         break;
5370                 case OP_IMAX_UN:
5371                         g_assert (cfg->opt & MONO_OPT_CMOV);
5372                         g_assert (ins->dreg == ins->sreg1);
5373                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5374                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5375                         break;
5376                 case OP_LMIN:
5377                         g_assert (cfg->opt & MONO_OPT_CMOV);
5378                         g_assert (ins->dreg == ins->sreg1);
5379                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5380                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5381                         break;
5382                 case OP_LMIN_UN:
5383                         g_assert (cfg->opt & MONO_OPT_CMOV);
5384                         g_assert (ins->dreg == ins->sreg1);
5385                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5386                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5387                         break;
5388                 case OP_LMAX:
5389                         g_assert (cfg->opt & MONO_OPT_CMOV);
5390                         g_assert (ins->dreg == ins->sreg1);
5391                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5392                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5393                         break;
5394                 case OP_LMAX_UN:
5395                         g_assert (cfg->opt & MONO_OPT_CMOV);
5396                         g_assert (ins->dreg == ins->sreg1);
5397                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5398                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5399                         break;
5400                 case OP_X86_FPOP:
5401                         break;
5402                 case OP_FCOMPARE:
5403                         /*
5404                          * The two arguments are swapped because the fbranch instructions
5405                          * depend on this for the non-sse case to work.
5406                          */
5407                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5408                         break;
5409                 case OP_RCOMPARE:
5410                         /*
5411                          * FIXME: Get rid of this.
5412                          * The two arguments are swapped because the fbranch instructions
5413                          * depend on this for the non-sse case to work.
5414                          */
5415                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5416                         break;
5417                 case OP_FCNEQ:
5418                 case OP_FCEQ: {
5419                         /* zeroing the register at the start results in
5420                          * shorter and faster code (we can also remove the widening op)
5421                          */
5422                         guchar *unordered_check;
5423
5424                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5425                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5426                         unordered_check = code;
5427                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5428
5429                         if (ins->opcode == OP_FCEQ) {
5430                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5431                                 amd64_patch (unordered_check, code);
5432                         } else {
5433                                 guchar *jump_to_end;
5434                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5435                                 jump_to_end = code;
5436                                 x86_jump8 (code, 0);
5437                                 amd64_patch (unordered_check, code);
5438                                 amd64_inc_reg (code, ins->dreg);
5439                                 amd64_patch (jump_to_end, code);
5440                         }
5441                         break;
5442                 }
5443                 case OP_FCLT:
5444                 case OP_FCLT_UN: {
5445                         /* zeroing the register at the start results in
5446                          * shorter and faster code (we can also remove the widening op)
5447                          */
5448                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5449                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5450                         if (ins->opcode == OP_FCLT_UN) {
5451                                 guchar *unordered_check = code;
5452                                 guchar *jump_to_end;
5453                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5454                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5455                                 jump_to_end = code;
5456                                 x86_jump8 (code, 0);
5457                                 amd64_patch (unordered_check, code);
5458                                 amd64_inc_reg (code, ins->dreg);
5459                                 amd64_patch (jump_to_end, code);
5460                         } else {
5461                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5462                         }
5463                         break;
5464                 }
5465                 case OP_FCLE: {
5466                         guchar *unordered_check;
5467                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5468                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5469                         unordered_check = code;
5470                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5471                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5472                         amd64_patch (unordered_check, code);
5473                         break;
5474                 }
5475                 case OP_FCGT:
5476                 case OP_FCGT_UN: {
5477                         /* zeroing the register at the start results in
5478                          * shorter and faster code (we can also remove the widening op)
5479                          */
5480                         guchar *unordered_check;
5481
5482                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5483                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5484                         if (ins->opcode == OP_FCGT) {
5485                                 unordered_check = code;
5486                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5487                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5488                                 amd64_patch (unordered_check, code);
5489                         } else {
5490                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5491                         }
5492                         break;
5493                 }
5494                 case OP_FCGE: {
5495                         guchar *unordered_check;
5496                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5497                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5498                         unordered_check = code;
5499                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5500                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5501                         amd64_patch (unordered_check, code);
5502                         break;
5503                 }
5504
5505                 case OP_RCEQ:
5506                 case OP_RCGT:
5507                 case OP_RCLT:
5508                 case OP_RCLT_UN:
5509                 case OP_RCGT_UN: {
5510                         int x86_cond;
5511                         gboolean unordered = FALSE;
5512
5513                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5514                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5515
5516                         switch (ins->opcode) {
5517                         case OP_RCEQ:
5518                                 x86_cond = X86_CC_EQ;
5519                                 break;
5520                         case OP_RCGT:
5521                                 x86_cond = X86_CC_LT;
5522                                 break;
5523                         case OP_RCLT:
5524                                 x86_cond = X86_CC_GT;
5525                                 break;
5526                         case OP_RCLT_UN:
5527                                 x86_cond = X86_CC_GT;
5528                                 unordered = TRUE;
5529                                 break;
5530                         case OP_RCGT_UN:
5531                                 x86_cond = X86_CC_LT;
5532                                 unordered = TRUE;
5533                                 break;
5534                         default:
5535                                 g_assert_not_reached ();
5536                                 break;
5537                         }
5538
5539                         if (unordered) {
5540                                 guchar *unordered_check;
5541                                 guchar *jump_to_end;
5542
5543                                 unordered_check = code;
5544                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5545                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5546                                 jump_to_end = code;
5547                                 x86_jump8 (code, 0);
5548                                 amd64_patch (unordered_check, code);
5549                                 amd64_inc_reg (code, ins->dreg);
5550                                 amd64_patch (jump_to_end, code);
5551                         } else {
5552                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5553                         }
5554                         break;
5555                 }
5556                 case OP_FCLT_MEMBASE:
5557                 case OP_FCGT_MEMBASE:
5558                 case OP_FCLT_UN_MEMBASE:
5559                 case OP_FCGT_UN_MEMBASE:
5560                 case OP_FCEQ_MEMBASE: {
5561                         guchar *unordered_check, *jump_to_end;
5562                         int x86_cond;
5563
5564                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5565                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5566
5567                         switch (ins->opcode) {
5568                         case OP_FCEQ_MEMBASE:
5569                                 x86_cond = X86_CC_EQ;
5570                                 break;
5571                         case OP_FCLT_MEMBASE:
5572                         case OP_FCLT_UN_MEMBASE:
5573                                 x86_cond = X86_CC_LT;
5574                                 break;
5575                         case OP_FCGT_MEMBASE:
5576                         case OP_FCGT_UN_MEMBASE:
5577                                 x86_cond = X86_CC_GT;
5578                                 break;
5579                         default:
5580                                 g_assert_not_reached ();
5581                         }
5582
5583                         unordered_check = code;
5584                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5585                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5586
5587                         switch (ins->opcode) {
5588                         case OP_FCEQ_MEMBASE:
5589                         case OP_FCLT_MEMBASE:
5590                         case OP_FCGT_MEMBASE:
5591                                 amd64_patch (unordered_check, code);
5592                                 break;
5593                         case OP_FCLT_UN_MEMBASE:
5594                         case OP_FCGT_UN_MEMBASE:
5595                                 jump_to_end = code;
5596                                 x86_jump8 (code, 0);
5597                                 amd64_patch (unordered_check, code);
5598                                 amd64_inc_reg (code, ins->dreg);
5599                                 amd64_patch (jump_to_end, code);
5600                                 break;
5601                         default:
5602                                 break;
5603                         }
5604                         break;
5605                 }
5606                 case OP_FBEQ: {
5607                         guchar *jump = code;
5608                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5609                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5610                         amd64_patch (jump, code);
5611                         break;
5612                 }
5613                 case OP_FBNE_UN:
5614                         /* Branch if C013 != 100 */
5615                         /* branch if !ZF or (PF|CF) */
5616                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5617                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5618                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5619                         break;
5620                 case OP_FBLT:
5621                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5622                         break;
5623                 case OP_FBLT_UN:
5624                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5625                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5626                         break;
5627                 case OP_FBGT:
5628                 case OP_FBGT_UN:
5629                         if (ins->opcode == OP_FBGT) {
5630                                 guchar *br1;
5631
5632                                 /* skip branch if C1=1 */
5633                                 br1 = code;
5634                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5635                                 /* branch if (C0 | C3) = 1 */
5636                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5637                                 amd64_patch (br1, code);
5638                                 break;
5639                         } else {
5640                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5641                         }
5642                         break;
5643                 case OP_FBGE: {
5644                         /* Branch if C013 == 100 or 001 */
5645                         guchar *br1;
5646
5647                         /* skip branch if C1=1 */
5648                         br1 = code;
5649                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5650                         /* branch if (C0 | C3) = 1 */
5651                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5652                         amd64_patch (br1, code);
5653                         break;
5654                 }
5655                 case OP_FBGE_UN:
5656                         /* Branch if C013 == 000 */
5657                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5658                         break;
5659                 case OP_FBLE: {
5660                         /* Branch if C013=000 or 100 */
5661                         guchar *br1;
5662
5663                         /* skip branch if C1=1 */
5664                         br1 = code;
5665                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5666                         /* branch if C0=0 */
5667                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5668                         amd64_patch (br1, code);
5669                         break;
5670                 }
5671                 case OP_FBLE_UN:
5672                         /* Branch if C013 != 001 */
5673                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5674                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5675                         break;
5676                 case OP_CKFINITE:
5677                         /* Transfer value to the fp stack */
5678                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5679                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5680                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5681
5682                         amd64_push_reg (code, AMD64_RAX);
5683                         amd64_fxam (code);
5684                         amd64_fnstsw (code);
5685                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5686                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5687                         amd64_pop_reg (code, AMD64_RAX);
5688                         amd64_fstp (code, 0);
5689                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5690                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5691                         break;
5692                 case OP_TLS_GET: {
5693                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5694                         break;
5695                 }
5696                 case OP_TLS_GET_REG:
5697                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5698                         break;
5699                 case OP_TLS_SET: {
5700                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5701                         break;
5702                 }
5703                 case OP_TLS_SET_REG: {
5704                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5705                         break;
5706                 }
5707                 case OP_MEMORY_BARRIER: {
5708                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5709                                 x86_mfence (code);
5710                         break;
5711                 }
5712                 case OP_ATOMIC_ADD_I4:
5713                 case OP_ATOMIC_ADD_I8: {
5714                         int dreg = ins->dreg;
5715                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5716
5717                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5718                                 dreg = AMD64_R11;
5719
5720                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5721                         amd64_prefix (code, X86_LOCK_PREFIX);
5722                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5723                         /* dreg contains the old value, add with sreg2 value */
5724                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5725
5726                         if (ins->dreg != dreg)
5727                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5728
5729                         break;
5730                 }
5731                 case OP_ATOMIC_EXCHANGE_I4:
5732                 case OP_ATOMIC_EXCHANGE_I8: {
5733                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5734
5735                         /* LOCK prefix is implied. */
5736                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5737                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5738                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5739                         break;
5740                 }
5741                 case OP_ATOMIC_CAS_I4:
5742                 case OP_ATOMIC_CAS_I8: {
5743                         guint32 size;
5744
5745                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5746                                 size = 8;
5747                         else
5748                                 size = 4;
5749
5750                         /*
5751                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5752                          * an explanation of how this works.
5753                          */
5754                         g_assert (ins->sreg3 == AMD64_RAX);
5755                         g_assert (ins->sreg1 != AMD64_RAX);
5756                         g_assert (ins->sreg1 != ins->sreg2);
5757
5758                         amd64_prefix (code, X86_LOCK_PREFIX);
5759                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5760
5761                         if (ins->dreg != AMD64_RAX)
5762                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5763                         break;
5764                 }
5765                 case OP_ATOMIC_LOAD_I1: {
5766                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5767                         break;
5768                 }
5769                 case OP_ATOMIC_LOAD_U1: {
5770                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5771                         break;
5772                 }
5773                 case OP_ATOMIC_LOAD_I2: {
5774                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5775                         break;
5776                 }
5777                 case OP_ATOMIC_LOAD_U2: {
5778                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5779                         break;
5780                 }
5781                 case OP_ATOMIC_LOAD_I4: {
5782                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5783                         break;
5784                 }
5785                 case OP_ATOMIC_LOAD_U4:
5786                 case OP_ATOMIC_LOAD_I8:
5787                 case OP_ATOMIC_LOAD_U8: {
5788                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5789                         break;
5790                 }
5791                 case OP_ATOMIC_LOAD_R4: {
5792                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5793                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5794                         break;
5795                 }
5796                 case OP_ATOMIC_LOAD_R8: {
5797                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5798                         break;
5799                 }
5800                 case OP_ATOMIC_STORE_I1:
5801                 case OP_ATOMIC_STORE_U1:
5802                 case OP_ATOMIC_STORE_I2:
5803                 case OP_ATOMIC_STORE_U2:
5804                 case OP_ATOMIC_STORE_I4:
5805                 case OP_ATOMIC_STORE_U4:
5806                 case OP_ATOMIC_STORE_I8:
5807                 case OP_ATOMIC_STORE_U8: {
5808                         int size;
5809
5810                         switch (ins->opcode) {
5811                         case OP_ATOMIC_STORE_I1:
5812                         case OP_ATOMIC_STORE_U1:
5813                                 size = 1;
5814                                 break;
5815                         case OP_ATOMIC_STORE_I2:
5816                         case OP_ATOMIC_STORE_U2:
5817                                 size = 2;
5818                                 break;
5819                         case OP_ATOMIC_STORE_I4:
5820                         case OP_ATOMIC_STORE_U4:
5821                                 size = 4;
5822                                 break;
5823                         case OP_ATOMIC_STORE_I8:
5824                         case OP_ATOMIC_STORE_U8:
5825                                 size = 8;
5826                                 break;
5827                         }
5828
5829                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5830
5831                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5832                                 x86_mfence (code);
5833                         break;
5834                 }
5835                 case OP_ATOMIC_STORE_R4: {
5836                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5837                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5838
5839                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5840                                 x86_mfence (code);
5841                         break;
5842                 }
5843                 case OP_ATOMIC_STORE_R8: {
5844                         x86_nop (code);
5845                         x86_nop (code);
5846                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5847                         x86_nop (code);
5848                         x86_nop (code);
5849
5850                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5851                                 x86_mfence (code);
5852                         break;
5853                 }
5854                 case OP_CARD_TABLE_WBARRIER: {
5855                         int ptr = ins->sreg1;
5856                         int value = ins->sreg2;
5857                         guchar *br = 0;
5858                         int nursery_shift, card_table_shift;
5859                         gpointer card_table_mask;
5860                         size_t nursery_size;
5861
5862                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5863                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5864                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5865
5866                         /*If either point to the stack we can simply avoid the WB. This happens due to
5867                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5868                          */
5869                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5870                                 continue;
5871
5872                         /*
5873                          * We need one register we can clobber, we choose EDX and make sreg1
5874                          * fixed EAX to work around limitations in the local register allocator.
5875                          * sreg2 might get allocated to EDX, but that is not a problem since
5876                          * we use it before clobbering EDX.
5877                          */
5878                         g_assert (ins->sreg1 == AMD64_RAX);
5879
5880                         /*
5881                          * This is the code we produce:
5882                          *
5883                          *   edx = value
5884                          *   edx >>= nursery_shift
5885                          *   cmp edx, (nursery_start >> nursery_shift)
5886                          *   jne done
5887                          *   edx = ptr
5888                          *   edx >>= card_table_shift
5889                          *   edx += cardtable
5890                          *   [edx] = 1
5891                          * done:
5892                          */
5893
5894                         if (mono_gc_card_table_nursery_check ()) {
5895                                 if (value != AMD64_RDX)
5896                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5897                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5898                                 if (shifted_nursery_start >> 31) {
5899                                         /*
5900                                          * The value we need to compare against is 64 bits, so we need
5901                                          * another spare register.  We use RBX, which we save and
5902                                          * restore.
5903                                          */
5904                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5905                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5906                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5907                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5908                                 } else {
5909                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5910                                 }
5911                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5912                         }
5913                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5914                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5915                         if (card_table_mask)
5916                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5917
5918                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5919                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5920
5921                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5922
5923                         if (mono_gc_card_table_nursery_check ())
5924                                 x86_patch (br, code);
5925                         break;
5926                 }
5927 #ifdef MONO_ARCH_SIMD_INTRINSICS
5928                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5929                 case OP_ADDPS:
5930                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_DIVPS:
5933                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_MULPS:
5936                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_SUBPS:
5939                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_MAXPS:
5942                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944                 case OP_MINPS:
5945                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_COMPPS:
5948                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5949                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5950                         break;
5951                 case OP_ANDPS:
5952                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_ANDNPS:
5955                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957                 case OP_ORPS:
5958                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_XORPS:
5961                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_SQRTPS:
5964                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5965                         break;
5966                 case OP_RSQRTPS:
5967                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5968                         break;
5969                 case OP_RCPPS:
5970                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5971                         break;
5972                 case OP_ADDSUBPS:
5973                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_HADDPS:
5976                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_HSUBPS:
5979                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_DUPPS_HIGH:
5982                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5983                         break;
5984                 case OP_DUPPS_LOW:
5985                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5986                         break;
5987
5988                 case OP_PSHUFLEW_HIGH:
5989                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5990                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5991                         break;
5992                 case OP_PSHUFLEW_LOW:
5993                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5994                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5995                         break;
5996                 case OP_PSHUFLED:
5997                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5998                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5999                         break;
6000                 case OP_SHUFPS:
6001                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6002                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6003                         break;
6004                 case OP_SHUFPD:
6005                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6006                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6007                         break;
6008
6009                 case OP_ADDPD:
6010                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_DIVPD:
6013                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_MULPD:
6016                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_SUBPD:
6019                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_MAXPD:
6022                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_MINPD:
6025                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_COMPPD:
6028                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6029                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6030                         break;
6031                 case OP_ANDPD:
6032                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_ANDNPD:
6035                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_ORPD:
6038                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_XORPD:
6041                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_SQRTPD:
6044                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6045                         break;
6046                 case OP_ADDSUBPD:
6047                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_HADDPD:
6050                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_HSUBPD:
6053                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_DUPPD:
6056                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6057                         break;
6058
6059                 case OP_EXTRACT_MASK:
6060                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6061                         break;
6062
6063                 case OP_PAND:
6064                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_POR:
6067                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PXOR:
6070                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072
6073                 case OP_PADDB:
6074                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_PADDW:
6077                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PADDD:
6080                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PADDQ:
6083                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085
6086                 case OP_PSUBB:
6087                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PSUBW:
6090                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PSUBD:
6093                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PSUBQ:
6096                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098
6099                 case OP_PMAXB_UN:
6100                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PMAXW_UN:
6103                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMAXD_UN:
6106                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108
6109                 case OP_PMAXB:
6110                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMAXW:
6113                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PMAXD:
6116                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118
6119                 case OP_PAVGB_UN:
6120                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_PAVGW_UN:
6123                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125
6126                 case OP_PMINB_UN:
6127                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PMINW_UN:
6130                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PMIND_UN:
6133                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135
6136                 case OP_PMINB:
6137                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_PMINW:
6140                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_PMIND:
6143                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145
6146                 case OP_PCMPEQB:
6147                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6148                         break;
6149                 case OP_PCMPEQW:
6150                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152                 case OP_PCMPEQD:
6153                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155                 case OP_PCMPEQQ:
6156                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158
6159                 case OP_PCMPGTB:
6160                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_PCMPGTW:
6163                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_PCMPGTD:
6166                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6167                         break;
6168                 case OP_PCMPGTQ:
6169                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171
6172                 case OP_PSUM_ABS_DIFF:
6173                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175
6176                 case OP_UNPACK_LOWB:
6177                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179                 case OP_UNPACK_LOWW:
6180                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6181                         break;
6182                 case OP_UNPACK_LOWD:
6183                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_UNPACK_LOWQ:
6186                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_UNPACK_LOWPS:
6189                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_UNPACK_LOWPD:
6192                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194
6195                 case OP_UNPACK_HIGHB:
6196                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_UNPACK_HIGHW:
6199                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_UNPACK_HIGHD:
6202                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_UNPACK_HIGHQ:
6205                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_UNPACK_HIGHPS:
6208                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_UNPACK_HIGHPD:
6211                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213
6214                 case OP_PACKW:
6215                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_PACKD:
6218                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_PACKW_UN:
6221                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223                 case OP_PACKD_UN:
6224                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226
6227                 case OP_PADDB_SAT_UN:
6228                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6229                         break;
6230                 case OP_PSUBB_SAT_UN:
6231                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_PADDW_SAT_UN:
6234                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PSUBW_SAT_UN:
6237                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239
6240                 case OP_PADDB_SAT:
6241                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6242                         break;
6243                 case OP_PSUBB_SAT:
6244                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6245                         break;
6246                 case OP_PADDW_SAT:
6247                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249                 case OP_PSUBW_SAT:
6250                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6251                         break;
6252
6253                 case OP_PMULW:
6254                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256                 case OP_PMULD:
6257                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6258                         break;
6259                 case OP_PMULQ:
6260                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262                 case OP_PMULW_HIGH_UN:
6263                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6264                         break;
6265                 case OP_PMULW_HIGH:
6266                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6267                         break;
6268
6269                 case OP_PSHRW:
6270                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6271                         break;
6272                 case OP_PSHRW_REG:
6273                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6274                         break;
6275
6276                 case OP_PSARW:
6277                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6278                         break;
6279                 case OP_PSARW_REG:
6280                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6281                         break;
6282
6283                 case OP_PSHLW:
6284                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6285                         break;
6286                 case OP_PSHLW_REG:
6287                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6288                         break;
6289
6290                 case OP_PSHRD:
6291                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6292                         break;
6293                 case OP_PSHRD_REG:
6294                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6295                         break;
6296
6297                 case OP_PSARD:
6298                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6299                         break;
6300                 case OP_PSARD_REG:
6301                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6302                         break;
6303
6304                 case OP_PSHLD:
6305                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6306                         break;
6307                 case OP_PSHLD_REG:
6308                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6309                         break;
6310
6311                 case OP_PSHRQ:
6312                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6313                         break;
6314                 case OP_PSHRQ_REG:
6315                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6316                         break;
6317
6318                 /*TODO: This is appart of the sse spec but not added
6319                 case OP_PSARQ:
6320                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6321                         break;
6322                 case OP_PSARQ_REG:
6323                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6324                         break;
6325                 */
6326
6327                 case OP_PSHLQ:
6328                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6329                         break;
6330                 case OP_PSHLQ_REG:
6331                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6332                         break;
6333                 case OP_CVTDQ2PD:
6334                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6335                         break;
6336                 case OP_CVTDQ2PS:
6337                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6338                         break;
6339                 case OP_CVTPD2DQ:
6340                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6341                         break;
6342                 case OP_CVTPD2PS:
6343                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6344                         break;
6345                 case OP_CVTPS2DQ:
6346                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6347                         break;
6348                 case OP_CVTPS2PD:
6349                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6350                         break;
6351                 case OP_CVTTPD2DQ:
6352                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6353                         break;
6354                 case OP_CVTTPS2DQ:
6355                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6356                         break;
6357
6358                 case OP_ICONV_TO_X:
6359                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6360                         break;
6361                 case OP_EXTRACT_I4:
6362                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6363                         break;
6364                 case OP_EXTRACT_I8:
6365                         if (ins->inst_c0) {
6366                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6367                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6368                         } else {
6369                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6370                         }
6371                         break;
6372                 case OP_EXTRACT_I1:
6373                 case OP_EXTRACT_U1:
6374                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6375                         if (ins->inst_c0)
6376                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6377                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6378                         break;
6379                 case OP_EXTRACT_I2:
6380                 case OP_EXTRACT_U2:
6381                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6382                         if (ins->inst_c0)
6383                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6384                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6385                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6386                         break;
6387                 case OP_EXTRACT_R8:
6388                         if (ins->inst_c0)
6389                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6390                         else
6391                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6392                         break;
6393                 case OP_INSERT_I2:
6394                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6395                         break;
6396                 case OP_EXTRACTX_U2:
6397                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6398                         break;
6399                 case OP_INSERTX_U1_SLOW:
6400                         /*sreg1 is the extracted ireg (scratch)
6401                         /sreg2 is the to be inserted ireg (scratch)
6402                         /dreg is the xreg to receive the value*/
6403
6404                         /*clear the bits from the extracted word*/
6405                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6406                         /*shift the value to insert if needed*/
6407                         if (ins->inst_c0 & 1)
6408                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6409                         /*join them together*/
6410                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6411                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6412                         break;
6413                 case OP_INSERTX_I4_SLOW:
6414                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6415                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6416                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6417                         break;
6418                 case OP_INSERTX_I8_SLOW:
6419                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6420                         if (ins->inst_c0)
6421                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6422                         else
6423                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6424                         break;
6425
6426                 case OP_INSERTX_R4_SLOW:
6427                         switch (ins->inst_c0) {
6428                         case 0:
6429                                 if (cfg->r4fp)
6430                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6431                                 else
6432                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6433                                 break;
6434                         case 1:
6435                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6436                                 if (cfg->r4fp)
6437                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6438                                 else
6439                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6440                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6441                                 break;
6442                         case 2:
6443                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6444                                 if (cfg->r4fp)
6445                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6446                                 else
6447                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6448                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6449                                 break;
6450                         case 3:
6451                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6452                                 if (cfg->r4fp)
6453                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6454                                 else
6455                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6456                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6457                                 break;
6458                         }
6459                         break;
6460                 case OP_INSERTX_R8_SLOW:
6461                         if (ins->inst_c0)
6462                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6463                         else
6464                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6465                         break;
6466                 case OP_STOREX_MEMBASE_REG:
6467                 case OP_STOREX_MEMBASE:
6468                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6469                         break;
6470                 case OP_LOADX_MEMBASE:
6471                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6472                         break;
6473                 case OP_LOADX_ALIGNED_MEMBASE:
6474                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6475                         break;
6476                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6477                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6478                         break;
6479                 case OP_STOREX_NTA_MEMBASE_REG:
6480                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6481                         break;
6482                 case OP_PREFETCH_MEMBASE:
6483                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6484                         break;
6485
6486                 case OP_XMOVE:
6487                         /*FIXME the peephole pass should have killed this*/
6488                         if (ins->dreg != ins->sreg1)
6489                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6490                         break;
6491                 case OP_XZERO:
6492                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6493                         break;
6494                 case OP_ICONV_TO_R4_RAW:
6495                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6496                         break;
6497
6498                 case OP_FCONV_TO_R8_X:
6499                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6500                         break;
6501
6502                 case OP_XCONV_R8_TO_I4:
6503                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6504                         switch (ins->backend.source_opcode) {
6505                         case OP_FCONV_TO_I1:
6506                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6507                                 break;
6508                         case OP_FCONV_TO_U1:
6509                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6510                                 break;
6511                         case OP_FCONV_TO_I2:
6512                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6513                                 break;
6514                         case OP_FCONV_TO_U2:
6515                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6516                                 break;
6517                         }
6518                         break;
6519
6520                 case OP_EXPAND_I2:
6521                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6522                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6523                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6524                         break;
6525                 case OP_EXPAND_I4:
6526                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6527                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6528                         break;
6529                 case OP_EXPAND_I8:
6530                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6531                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6532                         break;
6533                 case OP_EXPAND_R4:
6534                         if (cfg->r4fp) {
6535                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6536                         } else {
6537                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6538                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6539                         }
6540                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6541                         break;
6542                 case OP_EXPAND_R8:
6543                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6544                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6545                         break;
6546 #endif
6547                 case OP_LIVERANGE_START: {
6548                         if (cfg->verbose_level > 1)
6549                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6550                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6551                         break;
6552                 }
6553                 case OP_LIVERANGE_END: {
6554                         if (cfg->verbose_level > 1)
6555                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6556                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6557                         break;
6558                 }
6559                 case OP_GC_SAFE_POINT: {
6560                         gpointer polling_func = NULL;
6561                         int compare_val = 0;
6562                         guint8 *br [1];
6563
6564 #if defined (USE_COOP_GC)
6565                         polling_func = (gpointer)mono_threads_state_poll;
6566                         compare_val = 1;
6567 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6568                         polling_func = (gpointer)mono_nacl_gc;
6569                         compare_val = 0xFFFFFFFF;
6570 #endif
6571                         if (!polling_func)
6572                                 break;
6573
6574                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6575                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6576                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, polling_func, TRUE);
6577                         amd64_patch (br[0], code);
6578                         break;
6579                 }
6580
6581                 case OP_GC_LIVENESS_DEF:
6582                 case OP_GC_LIVENESS_USE:
6583                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6584                         ins->backend.pc_offset = code - cfg->native_code;
6585                         break;
6586                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6587                         ins->backend.pc_offset = code - cfg->native_code;
6588                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6589                         break;
6590                 default:
6591                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6592                         g_assert_not_reached ();
6593                 }
6594
6595                 if ((code - cfg->native_code - offset) > max_len) {
6596 #if !defined(__native_client_codegen__)
6597                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6598                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6599                         g_assert_not_reached ();
6600 #endif
6601                 }
6602         }
6603
6604         cfg->code_len = code - cfg->native_code;
6605 }
6606
6607 #endif /* DISABLE_JIT */
6608
6609 void
6610 mono_arch_register_lowlevel_calls (void)
6611 {
6612         /* The signature doesn't matter */
6613         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6614 }
6615
6616 void
6617 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6618 {
6619         MonoJumpInfo *patch_info;
6620         gboolean compile_aot = !run_cctors;
6621
6622         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6623                 unsigned char *ip = patch_info->ip.i + code;
6624                 unsigned char *target;
6625
6626                 if (compile_aot) {
6627                         switch (patch_info->type) {
6628                         case MONO_PATCH_INFO_BB:
6629                         case MONO_PATCH_INFO_LABEL:
6630                                 break;
6631                         default:
6632                                 /* No need to patch these */
6633                                 continue;
6634                         }
6635                 }
6636
6637                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6638
6639                 switch (patch_info->type) {
6640                 case MONO_PATCH_INFO_NONE:
6641                         continue;
6642                 case MONO_PATCH_INFO_METHOD_REL:
6643                 case MONO_PATCH_INFO_R8:
6644                 case MONO_PATCH_INFO_R4:
6645                         g_assert_not_reached ();
6646                         continue;
6647                 case MONO_PATCH_INFO_BB:
6648                         break;
6649                 default:
6650                         break;
6651                 }
6652
6653                 /*
6654                  * Debug code to help track down problems where the target of a near call is
6655                  * is not valid.
6656                  */
6657                 if (amd64_is_near_call (ip)) {
6658                         gint64 disp = (guint8*)target - (guint8*)ip;
6659
6660                         if (!amd64_is_imm32 (disp)) {
6661                                 printf ("TYPE: %d\n", patch_info->type);
6662                                 switch (patch_info->type) {
6663                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6664                                         printf ("V: %s\n", patch_info->data.name);
6665                                         break;
6666                                 case MONO_PATCH_INFO_METHOD_JUMP:
6667                                 case MONO_PATCH_INFO_METHOD:
6668                                         printf ("V: %s\n", patch_info->data.method->name);
6669                                         break;
6670                                 default:
6671                                         break;
6672                                 }
6673                         }
6674                 }
6675
6676                 amd64_patch (ip, (gpointer)target);
6677         }
6678 }
6679
6680 #ifndef DISABLE_JIT
6681
6682 static int
6683 get_max_epilog_size (MonoCompile *cfg)
6684 {
6685         int max_epilog_size = 16;
6686
6687         if (cfg->method->save_lmf)
6688                 max_epilog_size += 256;
6689
6690         if (mono_jit_trace_calls != NULL)
6691                 max_epilog_size += 50;
6692
6693         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6694                 max_epilog_size += 50;
6695
6696         max_epilog_size += (AMD64_NREG * 2);
6697
6698         return max_epilog_size;
6699 }
6700
6701 /*
6702  * This macro is used for testing whenever the unwinder works correctly at every point
6703  * where an async exception can happen.
6704  */
6705 /* This will generate a SIGSEGV at the given point in the code */
6706 #define async_exc_point(code) do { \
6707     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6708          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6709              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6710          cfg->arch.async_point_count ++; \
6711     } \
6712 } while (0)
6713
6714 guint8 *
6715 mono_arch_emit_prolog (MonoCompile *cfg)
6716 {
6717         MonoMethod *method = cfg->method;
6718         MonoBasicBlock *bb;
6719         MonoMethodSignature *sig;
6720         MonoInst *ins;
6721         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6722         guint8 *code;
6723         CallInfo *cinfo;
6724         MonoInst *lmf_var = cfg->lmf_var;
6725         gboolean args_clobbered = FALSE;
6726         gboolean trace = FALSE;
6727 #ifdef __native_client_codegen__
6728         guint alignment_check;
6729 #endif
6730
6731         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6732
6733 #if defined(__default_codegen__)
6734         code = cfg->native_code = g_malloc (cfg->code_size);
6735 #elif defined(__native_client_codegen__)
6736         /* native_code_alloc is not 32-byte aligned, native_code is. */
6737         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6738
6739         /* Align native_code to next nearest kNaclAlignment byte. */
6740         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6741         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6742
6743         code = cfg->native_code;
6744
6745         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6746         g_assert (alignment_check == 0);
6747 #endif
6748
6749         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6750                 trace = TRUE;
6751
6752         /* Amount of stack space allocated by register saving code */
6753         pos = 0;
6754
6755         /* Offset between RSP and the CFA */
6756         cfa_offset = 0;
6757
6758         /*
6759          * The prolog consists of the following parts:
6760          * FP present:
6761          * - push rbp, mov rbp, rsp
6762          * - save callee saved regs using pushes
6763          * - allocate frame
6764          * - save rgctx if needed
6765          * - save lmf if needed
6766          * FP not present:
6767          * - allocate frame
6768          * - save rgctx if needed
6769          * - save lmf if needed
6770          * - save callee saved regs using moves
6771          */
6772
6773         // CFA = sp + 8
6774         cfa_offset = 8;
6775         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6776         // IP saved at CFA - 8
6777         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6778         async_exc_point (code);
6779         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6780
6781         if (!cfg->arch.omit_fp) {
6782                 amd64_push_reg (code, AMD64_RBP);
6783                 cfa_offset += 8;
6784                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6785                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6786                 async_exc_point (code);
6787 #ifdef TARGET_WIN32
6788                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6789 #endif
6790                 /* These are handled automatically by the stack marking code */
6791                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6792
6793                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6794                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6795                 async_exc_point (code);
6796 #ifdef TARGET_WIN32
6797                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6798 #endif
6799         }
6800
6801         /* The param area is always at offset 0 from sp */
6802         /* This needs to be allocated here, since it has to come after the spill area */
6803         if (cfg->param_area) {
6804                 if (cfg->arch.omit_fp)
6805                         // FIXME:
6806                         g_assert_not_reached ();
6807                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6808         }
6809
6810         if (cfg->arch.omit_fp) {
6811                 /*
6812                  * On enter, the stack is misaligned by the pushing of the return
6813                  * address. It is either made aligned by the pushing of %rbp, or by
6814                  * this.
6815                  */
6816                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6817                 if ((alloc_size % 16) == 0) {
6818                         alloc_size += 8;
6819                         /* Mark the padding slot as NOREF */
6820                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6821                 }
6822         } else {
6823                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6824                 if (cfg->stack_offset != alloc_size) {
6825                         /* Mark the padding slot as NOREF */
6826                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6827                 }
6828                 cfg->arch.sp_fp_offset = alloc_size;
6829                 alloc_size -= pos;
6830         }
6831
6832         cfg->arch.stack_alloc_size = alloc_size;
6833
6834         /* Allocate stack frame */
6835         if (alloc_size) {
6836                 /* See mono_emit_stack_alloc */
6837 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6838                 guint32 remaining_size = alloc_size;
6839                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6840                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6841                 guint32 offset = code - cfg->native_code;
6842                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6843                         while (required_code_size >= (cfg->code_size - offset))
6844                                 cfg->code_size *= 2;
6845                         cfg->native_code = mono_realloc_native_code (cfg);
6846                         code = cfg->native_code + offset;
6847                         cfg->stat_code_reallocs++;
6848                 }
6849
6850                 while (remaining_size >= 0x1000) {
6851                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6852                         if (cfg->arch.omit_fp) {
6853                                 cfa_offset += 0x1000;
6854                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6855                         }
6856                         async_exc_point (code);
6857 #ifdef TARGET_WIN32
6858                         if (cfg->arch.omit_fp)
6859                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6860 #endif
6861
6862                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6863                         remaining_size -= 0x1000;
6864                 }
6865                 if (remaining_size) {
6866                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6867                         if (cfg->arch.omit_fp) {
6868                                 cfa_offset += remaining_size;
6869                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6870                                 async_exc_point (code);
6871                         }
6872 #ifdef TARGET_WIN32
6873                         if (cfg->arch.omit_fp)
6874                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6875 #endif
6876                 }
6877 #else
6878                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6879                 if (cfg->arch.omit_fp) {
6880                         cfa_offset += alloc_size;
6881                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6882                         async_exc_point (code);
6883                 }
6884 #endif
6885         }
6886
6887         /* Stack alignment check */
6888 #if 0
6889         {
6890                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6891                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6892                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6893                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6894                 amd64_breakpoint (code);
6895         }
6896 #endif
6897
6898         if (mini_get_debug_options ()->init_stacks) {
6899                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6900
6901                 /* Save registers to the red zone */
6902                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6903                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6904
6905                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6906                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6907                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6908
6909                 amd64_cld (code);
6910 #if defined(__default_codegen__)
6911                 amd64_prefix (code, X86_REP_PREFIX);
6912                 amd64_stosl (code);
6913 #elif defined(__native_client_codegen__)
6914                 /* NaCl stos pseudo-instruction */
6915                 amd64_codegen_pre (code);
6916                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6917                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6918                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6919                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6920                 amd64_prefix (code, X86_REP_PREFIX);
6921                 amd64_stosl (code);
6922                 amd64_codegen_post (code);
6923 #endif /* __native_client_codegen__ */
6924
6925                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6926                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6927         }
6928
6929         /* Save LMF */
6930         if (method->save_lmf)
6931                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6932
6933         /* Save callee saved registers */
6934         if (cfg->arch.omit_fp) {
6935                 save_area_offset = cfg->arch.reg_save_area_offset;
6936                 /* Save caller saved registers after sp is adjusted */
6937                 /* The registers are saved at the bottom of the frame */
6938                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6939         } else {
6940                 /* The registers are saved just below the saved rbp */
6941                 save_area_offset = cfg->arch.reg_save_area_offset;
6942         }
6943
6944         for (i = 0; i < AMD64_NREG; ++i) {
6945                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6946                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6947
6948                         if (cfg->arch.omit_fp) {
6949                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6950                                 /* These are handled automatically by the stack marking code */
6951                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6952                         } else {
6953                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6954                                 // FIXME: GC
6955                         }
6956
6957                         save_area_offset += 8;
6958                         async_exc_point (code);
6959                 }
6960         }
6961
6962         /* store runtime generic context */
6963         if (cfg->rgctx_var) {
6964                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6965                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6966
6967                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6968
6969                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6970                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6971         }
6972
6973         /* compute max_length in order to use short forward jumps */
6974         max_epilog_size = get_max_epilog_size (cfg);
6975         if (cfg->opt & MONO_OPT_BRANCH) {
6976                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6977                         MonoInst *ins;
6978                         int max_length = 0;
6979
6980                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6981                                 max_length += 6;
6982                         /* max alignment for loops */
6983                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6984                                 max_length += LOOP_ALIGNMENT;
6985 #ifdef __native_client_codegen__
6986                         /* max alignment for native client */
6987                         max_length += kNaClAlignment;
6988 #endif
6989
6990                         MONO_BB_FOR_EACH_INS (bb, ins) {
6991 #ifdef __native_client_codegen__
6992                                 {
6993                                         int space_in_block = kNaClAlignment -
6994                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6995                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6996                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6997                                                 max_length += space_in_block;
6998                                         }
6999                                 }
7000 #endif  /*__native_client_codegen__*/
7001                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7002                         }
7003
7004                         /* Take prolog and epilog instrumentation into account */
7005                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7006                                 max_length += max_epilog_size;
7007
7008                         bb->max_length = max_length;
7009                 }
7010         }
7011
7012         sig = mono_method_signature (method);
7013         pos = 0;
7014
7015         cinfo = cfg->arch.cinfo;
7016
7017         if (sig->ret->type != MONO_TYPE_VOID) {
7018                 /* Save volatile arguments to the stack */
7019                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7020                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7021         }
7022
7023         /* Keep this in sync with emit_load_volatile_arguments */
7024         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7025                 ArgInfo *ainfo = cinfo->args + i;
7026
7027                 ins = cfg->args [i];
7028
7029                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7030                         /* Unused arguments */
7031                         continue;
7032
7033                 if (cfg->globalra) {
7034                         /* All the other moves are done by the register allocator */
7035                         switch (ainfo->storage) {
7036                         case ArgInFloatSSEReg:
7037                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7038                                 break;
7039                         case ArgValuetypeInReg:
7040                                 for (quad = 0; quad < 2; quad ++) {
7041                                         switch (ainfo->pair_storage [quad]) {
7042                                         case ArgInIReg:
7043                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7044                                                 break;
7045                                         case ArgInFloatSSEReg:
7046                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7047                                                 break;
7048                                         case ArgInDoubleSSEReg:
7049                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7050                                                 break;
7051                                         case ArgNone:
7052                                                 break;
7053                                         default:
7054                                                 g_assert_not_reached ();
7055                                         }
7056                                 }
7057                                 break;
7058                         default:
7059                                 break;
7060                         }
7061
7062                         continue;
7063                 }
7064
7065                 /* Save volatile arguments to the stack */
7066                 if (ins->opcode != OP_REGVAR) {
7067                         switch (ainfo->storage) {
7068                         case ArgInIReg: {
7069                                 guint32 size = 8;
7070
7071                                 /* FIXME: I1 etc */
7072                                 /*
7073                                 if (stack_offset & 0x1)
7074                                         size = 1;
7075                                 else if (stack_offset & 0x2)
7076                                         size = 2;
7077                                 else if (stack_offset & 0x4)
7078                                         size = 4;
7079                                 else
7080                                         size = 8;
7081                                 */
7082                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7083
7084                                 /*
7085                                  * Save the original location of 'this',
7086                                  * get_generic_info_from_stack_frame () needs this to properly look up
7087                                  * the argument value during the handling of async exceptions.
7088                                  */
7089                                 if (ins == cfg->args [0]) {
7090                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7091                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7092                                 }
7093                                 break;
7094                         }
7095                         case ArgInFloatSSEReg:
7096                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7097                                 break;
7098                         case ArgInDoubleSSEReg:
7099                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7100                                 break;
7101                         case ArgValuetypeInReg:
7102                                 for (quad = 0; quad < 2; quad ++) {
7103                                         switch (ainfo->pair_storage [quad]) {
7104                                         case ArgInIReg:
7105                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7106                                                 break;
7107                                         case ArgInFloatSSEReg:
7108                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7109                                                 break;
7110                                         case ArgInDoubleSSEReg:
7111                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7112                                                 break;
7113                                         case ArgNone:
7114                                                 break;
7115                                         default:
7116                                                 g_assert_not_reached ();
7117                                         }
7118                                 }
7119                                 break;
7120                         case ArgValuetypeAddrInIReg:
7121                                 if (ainfo->pair_storage [0] == ArgInIReg)
7122                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7123                                 break;
7124                         default:
7125                                 break;
7126                         }
7127                 } else {
7128                         /* Argument allocated to (non-volatile) register */
7129                         switch (ainfo->storage) {
7130                         case ArgInIReg:
7131                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7132                                 break;
7133                         case ArgOnStack:
7134                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7135                                 break;
7136                         default:
7137                                 g_assert_not_reached ();
7138                         }
7139
7140                         if (ins == cfg->args [0]) {
7141                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7142                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7143                         }
7144                 }
7145         }
7146
7147         if (cfg->method->save_lmf)
7148                 args_clobbered = TRUE;
7149
7150         if (trace) {
7151                 args_clobbered = TRUE;
7152                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7153         }
7154
7155         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7156                 args_clobbered = TRUE;
7157
7158         /*
7159          * Optimize the common case of the first bblock making a call with the same
7160          * arguments as the method. This works because the arguments are still in their
7161          * original argument registers.
7162          * FIXME: Generalize this
7163          */
7164         if (!args_clobbered) {
7165                 MonoBasicBlock *first_bb = cfg->bb_entry;
7166                 MonoInst *next;
7167                 int filter = FILTER_IL_SEQ_POINT;
7168
7169                 next = mono_bb_first_inst (first_bb, filter);
7170                 if (!next && first_bb->next_bb) {
7171                         first_bb = first_bb->next_bb;
7172                         next = mono_bb_first_inst (first_bb, filter);
7173                 }
7174
7175                 if (first_bb->in_count > 1)
7176                         next = NULL;
7177
7178                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7179                         ArgInfo *ainfo = cinfo->args + i;
7180                         gboolean match = FALSE;
7181
7182                         ins = cfg->args [i];
7183                         if (ins->opcode != OP_REGVAR) {
7184                                 switch (ainfo->storage) {
7185                                 case ArgInIReg: {
7186                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7187                                                 if (next->dreg == ainfo->reg) {
7188                                                         NULLIFY_INS (next);
7189                                                         match = TRUE;
7190                                                 } else {
7191                                                         next->opcode = OP_MOVE;
7192                                                         next->sreg1 = ainfo->reg;
7193                                                         /* Only continue if the instruction doesn't change argument regs */
7194                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7195                                                                 match = TRUE;
7196                                                 }
7197                                         }
7198                                         break;
7199                                 }
7200                                 default:
7201                                         break;
7202                                 }
7203                         } else {
7204                                 /* Argument allocated to (non-volatile) register */
7205                                 switch (ainfo->storage) {
7206                                 case ArgInIReg:
7207                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7208                                                 NULLIFY_INS (next);
7209                                                 match = TRUE;
7210                                         }
7211                                         break;
7212                                 default:
7213                                         break;
7214                                 }
7215                         }
7216
7217                         if (match) {
7218                                 next = mono_inst_next (next, filter);
7219                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7220                                 if (!next)
7221                                         break;
7222                         }
7223                 }
7224         }
7225
7226         if (cfg->gen_sdb_seq_points) {
7227                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7228
7229                 /* Initialize seq_point_info_var */
7230                 if (cfg->compile_aot) {
7231                         /* Initialize the variable from a GOT slot */
7232                         /* Same as OP_AOTCONST */
7233                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7234                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7235                         g_assert (info_var->opcode == OP_REGOFFSET);
7236                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7237                 }
7238
7239                 if (cfg->compile_aot) {
7240                         /* Initialize ss_tramp_var */
7241                         ins = cfg->arch.ss_tramp_var;
7242                         g_assert (ins->opcode == OP_REGOFFSET);
7243
7244                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7245                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7246                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7247                 } else {
7248                         /* Initialize ss_trigger_page_var */
7249                         ins = cfg->arch.ss_trigger_page_var;
7250
7251                         g_assert (ins->opcode == OP_REGOFFSET);
7252
7253                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7254                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7255                 }
7256         }
7257
7258         cfg->code_len = code - cfg->native_code;
7259
7260         g_assert (cfg->code_len < cfg->code_size);
7261
7262         return code;
7263 }
7264
7265 void
7266 mono_arch_emit_epilog (MonoCompile *cfg)
7267 {
7268         MonoMethod *method = cfg->method;
7269         int quad, i;
7270         guint8 *code;
7271         int max_epilog_size;
7272         CallInfo *cinfo;
7273         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7274         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7275
7276         max_epilog_size = get_max_epilog_size (cfg);
7277
7278         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7279                 cfg->code_size *= 2;
7280                 cfg->native_code = mono_realloc_native_code (cfg);
7281                 cfg->stat_code_reallocs++;
7282         }
7283         code = cfg->native_code + cfg->code_len;
7284
7285         cfg->has_unwind_info_for_epilog = TRUE;
7286
7287         /* Mark the start of the epilog */
7288         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7289
7290         /* Save the uwind state which is needed by the out-of-line code */
7291         mono_emit_unwind_op_remember_state (cfg, code);
7292
7293         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7294                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7295
7296         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7297
7298         if (method->save_lmf) {
7299                 /* check if we need to restore protection of the stack after a stack overflow */
7300                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7301                         guint8 *patch;
7302                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7303                         /* we load the value in a separate instruction: this mechanism may be
7304                          * used later as a safer way to do thread interruption
7305                          */
7306                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7307                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7308                         patch = code;
7309                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7310                         /* note that the call trampoline will preserve eax/edx */
7311                         x86_call_reg (code, X86_ECX);
7312                         x86_patch (patch, code);
7313                 } else {
7314                         /* FIXME: maybe save the jit tls in the prolog */
7315                 }
7316                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7317                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7318                 }
7319         }
7320
7321         /* Restore callee saved regs */
7322         for (i = 0; i < AMD64_NREG; ++i) {
7323                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7324                         /* Restore only used_int_regs, not arch.saved_iregs */
7325                         if (cfg->used_int_regs & (1 << i)) {
7326                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7327                                 mono_emit_unwind_op_same_value (cfg, code, i);
7328                                 async_exc_point (code);
7329                         }
7330                         save_area_offset += 8;
7331                 }
7332         }
7333
7334         /* Load returned vtypes into registers if needed */
7335         cinfo = cfg->arch.cinfo;
7336         if (cinfo->ret.storage == ArgValuetypeInReg) {
7337                 ArgInfo *ainfo = &cinfo->ret;
7338                 MonoInst *inst = cfg->ret;
7339
7340                 for (quad = 0; quad < 2; quad ++) {
7341                         switch (ainfo->pair_storage [quad]) {
7342                         case ArgInIReg:
7343                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7344                                 break;
7345                         case ArgInFloatSSEReg:
7346                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7347                                 break;
7348                         case ArgInDoubleSSEReg:
7349                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7350                                 break;
7351                         case ArgNone:
7352                                 break;
7353                         default:
7354                                 g_assert_not_reached ();
7355                         }
7356                 }
7357         }
7358
7359         if (cfg->arch.omit_fp) {
7360                 if (cfg->arch.stack_alloc_size) {
7361                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7362                 }
7363         } else {
7364                 amd64_leave (code);
7365                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7366         }
7367         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7368         async_exc_point (code);
7369         amd64_ret (code);
7370
7371         /* Restore the unwind state to be the same as before the epilog */
7372         mono_emit_unwind_op_restore_state (cfg, code);
7373
7374         cfg->code_len = code - cfg->native_code;
7375
7376         g_assert (cfg->code_len < cfg->code_size);
7377 }
7378
7379 void
7380 mono_arch_emit_exceptions (MonoCompile *cfg)
7381 {
7382         MonoJumpInfo *patch_info;
7383         int nthrows, i;
7384         guint8 *code;
7385         MonoClass *exc_classes [16];
7386         guint8 *exc_throw_start [16], *exc_throw_end [16];
7387         guint32 code_size = 0;
7388
7389         /* Compute needed space */
7390         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7391                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7392                         code_size += 40;
7393                 if (patch_info->type == MONO_PATCH_INFO_R8)
7394                         code_size += 8 + 15; /* sizeof (double) + alignment */
7395                 if (patch_info->type == MONO_PATCH_INFO_R4)
7396                         code_size += 4 + 15; /* sizeof (float) + alignment */
7397                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7398                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7399         }
7400
7401 #ifdef __native_client_codegen__
7402         /* Give us extra room on Native Client.  This could be   */
7403         /* more carefully calculated, but bundle alignment makes */
7404         /* it much trickier, so *2 like other places is good.    */
7405         code_size *= 2;
7406 #endif
7407
7408         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7409                 cfg->code_size *= 2;
7410                 cfg->native_code = mono_realloc_native_code (cfg);
7411                 cfg->stat_code_reallocs++;
7412         }
7413
7414         code = cfg->native_code + cfg->code_len;
7415
7416         /* add code to raise exceptions */
7417         nthrows = 0;
7418         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7419                 switch (patch_info->type) {
7420                 case MONO_PATCH_INFO_EXC: {
7421                         MonoClass *exc_class;
7422                         guint8 *buf, *buf2;
7423                         guint32 throw_ip;
7424
7425                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7426
7427                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7428                         g_assert (exc_class);
7429                         throw_ip = patch_info->ip.i;
7430
7431                         //x86_breakpoint (code);
7432                         /* Find a throw sequence for the same exception class */
7433                         for (i = 0; i < nthrows; ++i)
7434                                 if (exc_classes [i] == exc_class)
7435                                         break;
7436                         if (i < nthrows) {
7437                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7438                                 x86_jump_code (code, exc_throw_start [i]);
7439                                 patch_info->type = MONO_PATCH_INFO_NONE;
7440                         }
7441                         else {
7442                                 buf = code;
7443                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7444                                 buf2 = code;
7445
7446                                 if (nthrows < 16) {
7447                                         exc_classes [nthrows] = exc_class;
7448                                         exc_throw_start [nthrows] = code;
7449                                 }
7450                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7451
7452                                 patch_info->type = MONO_PATCH_INFO_NONE;
7453
7454                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7455
7456                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7457                                 while (buf < buf2)
7458                                         x86_nop (buf);
7459
7460                                 if (nthrows < 16) {
7461                                         exc_throw_end [nthrows] = code;
7462                                         nthrows ++;
7463                                 }
7464                         }
7465                         break;
7466                 }
7467                 default:
7468                         /* do nothing */
7469                         break;
7470                 }
7471                 g_assert(code < cfg->native_code + cfg->code_size);
7472         }
7473
7474         /* Handle relocations with RIP relative addressing */
7475         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7476                 gboolean remove = FALSE;
7477                 guint8 *orig_code = code;
7478
7479                 switch (patch_info->type) {
7480                 case MONO_PATCH_INFO_R8:
7481                 case MONO_PATCH_INFO_R4: {
7482                         guint8 *pos, *patch_pos;
7483                         guint32 target_pos;
7484
7485                         /* The SSE opcodes require a 16 byte alignment */
7486 #if defined(__default_codegen__)
7487                         code = (guint8*)ALIGN_TO (code, 16);
7488 #elif defined(__native_client_codegen__)
7489                         {
7490                                 /* Pad this out with HLT instructions  */
7491                                 /* or we can get garbage bytes emitted */
7492                                 /* which will fail validation          */
7493                                 guint8 *aligned_code;
7494                                 /* extra align to make room for  */
7495                                 /* mov/push below                      */
7496                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7497                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7498                                 /* The technique of hiding data in an  */
7499                                 /* instruction has a problem here: we  */
7500                                 /* need the data aligned to a 16-byte  */
7501                                 /* boundary but the instruction cannot */
7502                                 /* cross the bundle boundary. so only  */
7503                                 /* odd multiples of 16 can be used     */
7504                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7505                                         aligned_code += 16;
7506                                 }
7507                                 while (code < aligned_code) {
7508                                         *(code++) = 0xf4; /* hlt */
7509                                 }
7510                         }
7511 #endif
7512
7513                         pos = cfg->native_code + patch_info->ip.i;
7514                         if (IS_REX (pos [1])) {
7515                                 patch_pos = pos + 5;
7516                                 target_pos = code - pos - 9;
7517                         }
7518                         else {
7519                                 patch_pos = pos + 4;
7520                                 target_pos = code - pos - 8;
7521                         }
7522
7523                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7524 #ifdef __native_client_codegen__
7525                                 /* Hide 64-bit data in a         */
7526                                 /* "mov imm64, r11" instruction. */
7527                                 /* write it before the start of  */
7528                                 /* the data*/
7529                                 *(code-2) = 0x49; /* prefix      */
7530                                 *(code-1) = 0xbb; /* mov X, %r11 */
7531 #endif
7532                                 *(double*)code = *(double*)patch_info->data.target;
7533                                 code += sizeof (double);
7534                         } else {
7535 #ifdef __native_client_codegen__
7536                                 /* Hide 32-bit data in a        */
7537                                 /* "push imm32" instruction.    */
7538                                 *(code-1) = 0x68; /* push */
7539 #endif
7540                                 *(float*)code = *(float*)patch_info->data.target;
7541                                 code += sizeof (float);
7542                         }
7543
7544                         *(guint32*)(patch_pos) = target_pos;
7545
7546                         remove = TRUE;
7547                         break;
7548                 }
7549                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7550                         guint8 *pos;
7551
7552                         if (cfg->compile_aot)
7553                                 continue;
7554
7555                         /*loading is faster against aligned addresses.*/
7556                         code = (guint8*)ALIGN_TO (code, 8);
7557                         memset (orig_code, 0, code - orig_code);
7558
7559                         pos = cfg->native_code + patch_info->ip.i;
7560
7561                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7562                         if (IS_REX (pos [1]))
7563                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7564                         else
7565                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7566
7567                         *(gpointer*)code = (gpointer)patch_info->data.target;
7568                         code += sizeof (gpointer);
7569
7570                         remove = TRUE;
7571                         break;
7572                 }
7573                 default:
7574                         break;
7575                 }
7576
7577                 if (remove) {
7578                         if (patch_info == cfg->patch_info)
7579                                 cfg->patch_info = patch_info->next;
7580                         else {
7581                                 MonoJumpInfo *tmp;
7582
7583                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7584                                         ;
7585                                 tmp->next = patch_info->next;
7586                         }
7587                 }
7588                 g_assert (code < cfg->native_code + cfg->code_size);
7589         }
7590
7591         cfg->code_len = code - cfg->native_code;
7592
7593         g_assert (cfg->code_len < cfg->code_size);
7594
7595 }
7596
7597 #endif /* DISABLE_JIT */
7598
7599 void*
7600 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7601 {
7602         guchar *code = p;
7603         MonoMethodSignature *sig;
7604         MonoInst *inst;
7605         int i, n, stack_area = 0;
7606
7607         /* Keep this in sync with mono_arch_get_argument_info */
7608
7609         if (enable_arguments) {
7610                 /* Allocate a new area on the stack and save arguments there */
7611                 sig = mono_method_signature (cfg->method);
7612
7613                 n = sig->param_count + sig->hasthis;
7614
7615                 stack_area = ALIGN_TO (n * 8, 16);
7616
7617                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7618
7619                 for (i = 0; i < n; ++i) {
7620                         inst = cfg->args [i];
7621
7622                         if (inst->opcode == OP_REGVAR)
7623                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7624                         else {
7625                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7626                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7627                         }
7628                 }
7629         }
7630
7631         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7632         amd64_set_reg_template (code, AMD64_ARG_REG1);
7633         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7634         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7635
7636         if (enable_arguments)
7637                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7638
7639         return code;
7640 }
7641
7642 enum {
7643         SAVE_NONE,
7644         SAVE_STRUCT,
7645         SAVE_EAX,
7646         SAVE_EAX_EDX,
7647         SAVE_XMM
7648 };
7649
7650 void*
7651 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7652 {
7653         guchar *code = p;
7654         int save_mode = SAVE_NONE;
7655         MonoMethod *method = cfg->method;
7656         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7657         int i;
7658
7659         switch (ret_type->type) {
7660         case MONO_TYPE_VOID:
7661                 /* special case string .ctor icall */
7662                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7663                         save_mode = SAVE_EAX;
7664                 else
7665                         save_mode = SAVE_NONE;
7666                 break;
7667         case MONO_TYPE_I8:
7668         case MONO_TYPE_U8:
7669                 save_mode = SAVE_EAX;
7670                 break;
7671         case MONO_TYPE_R4:
7672         case MONO_TYPE_R8:
7673                 save_mode = SAVE_XMM;
7674                 break;
7675         case MONO_TYPE_GENERICINST:
7676                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7677                         save_mode = SAVE_EAX;
7678                         break;
7679                 }
7680                 /* Fall through */
7681         case MONO_TYPE_VALUETYPE:
7682                 save_mode = SAVE_STRUCT;
7683                 break;
7684         default:
7685                 save_mode = SAVE_EAX;
7686                 break;
7687         }
7688
7689         /* Save the result and copy it into the proper argument register */
7690         switch (save_mode) {
7691         case SAVE_EAX:
7692                 amd64_push_reg (code, AMD64_RAX);
7693                 /* Align stack */
7694                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7695                 if (enable_arguments)
7696                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7697                 break;
7698         case SAVE_STRUCT:
7699                 /* FIXME: */
7700                 if (enable_arguments)
7701                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7702                 break;
7703         case SAVE_XMM:
7704                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7705                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7706                 /* Align stack */
7707                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7708                 /*
7709                  * The result is already in the proper argument register so no copying
7710                  * needed.
7711                  */
7712                 break;
7713         case SAVE_NONE:
7714                 break;
7715         default:
7716                 g_assert_not_reached ();
7717         }
7718
7719         /* Set %al since this is a varargs call */
7720         if (save_mode == SAVE_XMM)
7721                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7722         else
7723                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7724
7725         if (preserve_argument_registers) {
7726                 for (i = 0; i < PARAM_REGS; ++i)
7727                         amd64_push_reg (code, param_regs [i]);
7728         }
7729
7730         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7731         amd64_set_reg_template (code, AMD64_ARG_REG1);
7732         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7733
7734         if (preserve_argument_registers) {
7735                 for (i = PARAM_REGS - 1; i >= 0; --i)
7736                         amd64_pop_reg (code, param_regs [i]);
7737         }
7738
7739         /* Restore result */
7740         switch (save_mode) {
7741         case SAVE_EAX:
7742                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7743                 amd64_pop_reg (code, AMD64_RAX);
7744                 break;
7745         case SAVE_STRUCT:
7746                 /* FIXME: */
7747                 break;
7748         case SAVE_XMM:
7749                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7750                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7751                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7752                 break;
7753         case SAVE_NONE:
7754                 break;
7755         default:
7756                 g_assert_not_reached ();
7757         }
7758
7759         return code;
7760 }
7761
7762 void
7763 mono_arch_flush_icache (guint8 *code, gint size)
7764 {
7765         /* Not needed */
7766 }
7767
7768 void
7769 mono_arch_flush_register_windows (void)
7770 {
7771 }
7772
7773 gboolean
7774 mono_arch_is_inst_imm (gint64 imm)
7775 {
7776         return amd64_is_imm32 (imm);
7777 }
7778
7779 /*
7780  * Determine whenever the trap whose info is in SIGINFO is caused by
7781  * integer overflow.
7782  */
7783 gboolean
7784 mono_arch_is_int_overflow (void *sigctx, void *info)
7785 {
7786         MonoContext ctx;
7787         guint8* rip;
7788         int reg;
7789         gint64 value;
7790
7791         mono_sigctx_to_monoctx (sigctx, &ctx);
7792
7793         rip = (guint8*)ctx.rip;
7794
7795         if (IS_REX (rip [0])) {
7796                 reg = amd64_rex_b (rip [0]);
7797                 rip ++;
7798         }
7799         else
7800                 reg = 0;
7801
7802         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7803                 /* idiv REG */
7804                 reg += x86_modrm_rm (rip [1]);
7805
7806                 switch (reg) {
7807                 case AMD64_RAX:
7808                         value = ctx.rax;
7809                         break;
7810                 case AMD64_RBX:
7811                         value = ctx.rbx;
7812                         break;
7813                 case AMD64_RCX:
7814                         value = ctx.rcx;
7815                         break;
7816                 case AMD64_RDX:
7817                         value = ctx.rdx;
7818                         break;
7819                 case AMD64_RBP:
7820                         value = ctx.rbp;
7821                         break;
7822                 case AMD64_RSP:
7823                         value = ctx.rsp;
7824                         break;
7825                 case AMD64_RSI:
7826                         value = ctx.rsi;
7827                         break;
7828                 case AMD64_RDI:
7829                         value = ctx.rdi;
7830                         break;
7831                 case AMD64_R12:
7832                         value = ctx.r12;
7833                         break;
7834                 case AMD64_R13:
7835                         value = ctx.r13;
7836                         break;
7837                 case AMD64_R14:
7838                         value = ctx.r14;
7839                         break;
7840                 case AMD64_R15:
7841                         value = ctx.r15;
7842                         break;
7843                 default:
7844                         g_assert_not_reached ();
7845                         reg = -1;
7846                 }
7847
7848                 if (value == -1)
7849                         return TRUE;
7850         }
7851
7852         return FALSE;
7853 }
7854
7855 guint32
7856 mono_arch_get_patch_offset (guint8 *code)
7857 {
7858         return 3;
7859 }
7860
7861 /**
7862  * mono_breakpoint_clean_code:
7863  *
7864  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7865  * breakpoints in the original code, they are removed in the copy.
7866  *
7867  * Returns TRUE if no sw breakpoint was present.
7868  */
7869 gboolean
7870 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7871 {
7872         /*
7873          * If method_start is non-NULL we need to perform bound checks, since we access memory
7874          * at code - offset we could go before the start of the method and end up in a different
7875          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7876          * instead.
7877          */
7878         if (!method_start || code - offset >= method_start) {
7879                 memcpy (buf, code - offset, size);
7880         } else {
7881                 int diff = code - method_start;
7882                 memset (buf, 0, size);
7883                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7884         }
7885         return TRUE;
7886 }
7887
7888 #if defined(__native_client_codegen__)
7889 /* For membase calls, we want the base register. for Native Client,  */
7890 /* all indirect calls have the following sequence with the given sizes: */
7891 /* mov %eXX,%eXX                                [2-3]   */
7892 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7893 /* and $0xffffffffffffffe0,%r11d                [4]     */
7894 /* add %r15,%r11                                [3]     */
7895 /* callq *%r11                                  [3]     */
7896
7897
7898 /* Determine if code points to a NaCl call-through-register sequence, */
7899 /* (i.e., the last 3 instructions listed above) */
7900 int
7901 is_nacl_call_reg_sequence(guint8* code)
7902 {
7903         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7904                                "\x4d\x03\xdf"     /* add */
7905                                "\x41\xff\xd3";   /* call */
7906         return memcmp(code, sequence, 10) == 0;
7907 }
7908
7909 /* Determine if code points to the first opcode of the mov membase component */
7910 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7911 /* (there could be a REX prefix before the opcode but it is ignored) */
7912 static int
7913 is_nacl_indirect_call_membase_sequence(guint8* code)
7914 {
7915                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7916         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7917                /* and that src reg = dest reg */
7918                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7919                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7920                IS_REX(code[2]) &&
7921                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7922                /* and has dst of r11 and base of r15 */
7923                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7924                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7925 }
7926 #endif /* __native_client_codegen__ */
7927
7928 int
7929 mono_arch_get_this_arg_reg (guint8 *code)
7930 {
7931         return AMD64_ARG_REG1;
7932 }
7933
7934 gpointer
7935 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7936 {
7937         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7938 }
7939
7940 #define MAX_ARCH_DELEGATE_PARAMS 10
7941
7942 static gpointer
7943 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7944 {
7945         guint8 *code, *start;
7946         int i;
7947
7948         if (has_target) {
7949                 start = code = mono_global_codeman_reserve (64);
7950
7951                 /* Replace the this argument with the target */
7952                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7953                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7954                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7955
7956                 g_assert ((code - start) < 64);
7957         } else {
7958                 start = code = mono_global_codeman_reserve (64);
7959
7960                 if (param_count == 0) {
7961                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7962                 } else {
7963                         /* We have to shift the arguments left */
7964                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7965                         for (i = 0; i < param_count; ++i) {
7966 #ifdef TARGET_WIN32
7967                                 if (i < 3)
7968                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7969                                 else
7970                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7971 #else
7972                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7973 #endif
7974                         }
7975
7976                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7977                 }
7978                 g_assert ((code - start) < 64);
7979         }
7980
7981         nacl_global_codeman_validate (&start, 64, &code);
7982         mono_arch_flush_icache (start, code - start);
7983
7984         if (code_len)
7985                 *code_len = code - start;
7986
7987         if (mono_jit_map_is_enabled ()) {
7988                 char *buff;
7989                 if (has_target)
7990                         buff = (char*)"delegate_invoke_has_target";
7991                 else
7992                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7993                 mono_emit_jit_tramp (start, code - start, buff);
7994                 if (!has_target)
7995                         g_free (buff);
7996         }
7997         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7998
7999         return start;
8000 }
8001
8002 /*
8003  * mono_arch_get_delegate_invoke_impls:
8004  *
8005  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8006  * trampolines.
8007  */
8008 GSList*
8009 mono_arch_get_delegate_invoke_impls (void)
8010 {
8011         GSList *res = NULL;
8012         guint8 *code;
8013         guint32 code_len;
8014         int i;
8015         char *tramp_name;
8016
8017         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8018         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8019
8020         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8021                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8022                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8023                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8024                 g_free (tramp_name);
8025         }
8026
8027         return res;
8028 }
8029
8030 gpointer
8031 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8032 {
8033         guint8 *code, *start;
8034         int i;
8035
8036         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8037                 return NULL;
8038
8039         /* FIXME: Support more cases */
8040         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8041                 return NULL;
8042
8043         if (has_target) {
8044                 static guint8* cached = NULL;
8045
8046                 if (cached)
8047                         return cached;
8048
8049                 if (mono_aot_only)
8050                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8051                 else
8052                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8053
8054                 mono_memory_barrier ();
8055
8056                 cached = start;
8057         } else {
8058                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8059                 for (i = 0; i < sig->param_count; ++i)
8060                         if (!mono_is_regsize_var (sig->params [i]))
8061                                 return NULL;
8062                 if (sig->param_count > 4)
8063                         return NULL;
8064
8065                 code = cache [sig->param_count];
8066                 if (code)
8067                         return code;
8068
8069                 if (mono_aot_only) {
8070                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8071                         start = mono_aot_get_trampoline (name);
8072                         g_free (name);
8073                 } else {
8074                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8075                 }
8076
8077                 mono_memory_barrier ();
8078
8079                 cache [sig->param_count] = start;
8080         }
8081
8082         return start;
8083 }
8084
8085 gpointer
8086 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8087 {
8088         guint8 *code, *start;
8089         int size = 20;
8090
8091         start = code = mono_global_codeman_reserve (size);
8092
8093         /* Replace the this argument with the target */
8094         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8095         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8096
8097         if (load_imt_reg) {
8098                 /* Load the IMT reg */
8099                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8100         }
8101
8102         /* Load the vtable */
8103         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8104         amd64_jump_membase (code, AMD64_RAX, offset);
8105         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8106
8107         return start;
8108 }
8109
8110 void
8111 mono_arch_finish_init (void)
8112 {
8113 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8114         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8115 #endif
8116 }
8117
8118 void
8119 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8120 {
8121 }
8122
8123 #if defined(__default_codegen__)
8124 #define CMP_SIZE (6 + 1)
8125 #define CMP_REG_REG_SIZE (4 + 1)
8126 #define BR_SMALL_SIZE 2
8127 #define BR_LARGE_SIZE 6
8128 #define MOV_REG_IMM_SIZE 10
8129 #define MOV_REG_IMM_32BIT_SIZE 6
8130 #define JUMP_REG_SIZE (2 + 1)
8131 #elif defined(__native_client_codegen__)
8132 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8133 #define CMP_SIZE ((6 + 1) * 2 - 1)
8134 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8135 #define BR_SMALL_SIZE (2 * 2 - 1)
8136 #define BR_LARGE_SIZE (6 * 2 - 1)
8137 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8138 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8139 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8140 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8141 /* Jump membase's size is large and unpredictable    */
8142 /* in native client, just pad it out a whole bundle. */
8143 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8144 #endif
8145
8146 static int
8147 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8148 {
8149         int i, distance = 0;
8150         for (i = start; i < target; ++i)
8151                 distance += imt_entries [i]->chunk_size;
8152         return distance;
8153 }
8154
8155 /*
8156  * LOCKING: called with the domain lock held
8157  */
8158 gpointer
8159 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8160         gpointer fail_tramp)
8161 {
8162         int i;
8163         int size = 0;
8164         guint8 *code, *start;
8165         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8166
8167         for (i = 0; i < count; ++i) {
8168                 MonoIMTCheckItem *item = imt_entries [i];
8169                 if (item->is_equals) {
8170                         if (item->check_target_idx) {
8171                                 if (!item->compare_done) {
8172                                         if (amd64_is_imm32 (item->key))
8173                                                 item->chunk_size += CMP_SIZE;
8174                                         else
8175                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8176                                 }
8177                                 if (item->has_target_code) {
8178                                         item->chunk_size += MOV_REG_IMM_SIZE;
8179                                 } else {
8180                                         if (vtable_is_32bit)
8181                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8182                                         else
8183                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8184 #ifdef __native_client_codegen__
8185                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8186 #endif
8187                                 }
8188                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8189                         } else {
8190                                 if (fail_tramp) {
8191                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8192                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8193                                 } else {
8194                                         if (vtable_is_32bit)
8195                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8196                                         else
8197                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8198                                         item->chunk_size += JUMP_REG_SIZE;
8199                                         /* with assert below:
8200                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8201                                          */
8202 #ifdef __native_client_codegen__
8203                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8204 #endif
8205                                 }
8206                         }
8207                 } else {
8208                         if (amd64_is_imm32 (item->key))
8209                                 item->chunk_size += CMP_SIZE;
8210                         else
8211                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8212                         item->chunk_size += BR_LARGE_SIZE;
8213                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8214                 }
8215                 size += item->chunk_size;
8216         }
8217 #if defined(__native_client__) && defined(__native_client_codegen__)
8218         /* In Native Client, we don't re-use thunks, allocate from the */
8219         /* normal code manager paths. */
8220         code = mono_domain_code_reserve (domain, size);
8221 #else
8222         if (fail_tramp)
8223                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8224         else
8225                 code = mono_domain_code_reserve (domain, size);
8226 #endif
8227         start = code;
8228         for (i = 0; i < count; ++i) {
8229                 MonoIMTCheckItem *item = imt_entries [i];
8230                 item->code_target = code;
8231                 if (item->is_equals) {
8232                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8233
8234                         if (item->check_target_idx || fail_case) {
8235                                 if (!item->compare_done || fail_case) {
8236                                         if (amd64_is_imm32 (item->key))
8237                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8238                                         else {
8239                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8240                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8241                                         }
8242                                 }
8243                                 item->jmp_code = code;
8244                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8245                                 if (item->has_target_code) {
8246                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8247                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8248                                 } else {
8249                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8250                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8251                                 }
8252
8253                                 if (fail_case) {
8254                                         amd64_patch (item->jmp_code, code);
8255                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8256                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8257                                         item->jmp_code = NULL;
8258                                 }
8259                         } else {
8260                                 /* enable the commented code to assert on wrong method */
8261 #if 0
8262                                 if (amd64_is_imm32 (item->key))
8263                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8264                                 else {
8265                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8266                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8267                                 }
8268                                 item->jmp_code = code;
8269                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8270                                 /* See the comment below about R10 */
8271                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8272                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8273                                 amd64_patch (item->jmp_code, code);
8274                                 amd64_breakpoint (code);
8275                                 item->jmp_code = NULL;
8276 #else
8277                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8278                                    needs to be preserved.  R10 needs
8279                                    to be preserved for calls which
8280                                    require a runtime generic context,
8281                                    but interface calls don't. */
8282                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8283                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8284 #endif
8285                         }
8286                 } else {
8287                         if (amd64_is_imm32 (item->key))
8288                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8289                         else {
8290                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8291                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8292                         }
8293                         item->jmp_code = code;
8294                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8295                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8296                         else
8297                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8298                 }
8299                 g_assert (code - item->code_target <= item->chunk_size);
8300         }
8301         /* patch the branches to get to the target items */
8302         for (i = 0; i < count; ++i) {
8303                 MonoIMTCheckItem *item = imt_entries [i];
8304                 if (item->jmp_code) {
8305                         if (item->check_target_idx) {
8306                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8307                         }
8308                 }
8309         }
8310
8311         if (!fail_tramp)
8312                 mono_stats.imt_thunks_size += code - start;
8313         g_assert (code - start <= size);
8314
8315         nacl_domain_code_validate(domain, &start, size, &code);
8316         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8317
8318         return start;
8319 }
8320
8321 MonoMethod*
8322 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8323 {
8324         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8325 }
8326
8327 MonoVTable*
8328 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8329 {
8330         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8331 }
8332
8333 GSList*
8334 mono_arch_get_cie_program (void)
8335 {
8336         GSList *l = NULL;
8337
8338         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8339         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8340
8341         return l;
8342 }
8343
8344 #ifndef DISABLE_JIT
8345
8346 MonoInst*
8347 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8348 {
8349         MonoInst *ins = NULL;
8350         int opcode = 0;
8351
8352         if (cmethod->klass == mono_defaults.math_class) {
8353                 if (strcmp (cmethod->name, "Sin") == 0) {
8354                         opcode = OP_SIN;
8355                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8356                         opcode = OP_COS;
8357                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8358                         opcode = OP_SQRT;
8359                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8360                         opcode = OP_ABS;
8361                 }
8362
8363                 if (opcode && fsig->param_count == 1) {
8364                         MONO_INST_NEW (cfg, ins, opcode);
8365                         ins->type = STACK_R8;
8366                         ins->dreg = mono_alloc_freg (cfg);
8367                         ins->sreg1 = args [0]->dreg;
8368                         MONO_ADD_INS (cfg->cbb, ins);
8369                 }
8370
8371                 opcode = 0;
8372                 if (cfg->opt & MONO_OPT_CMOV) {
8373                         if (strcmp (cmethod->name, "Min") == 0) {
8374                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8375                                         opcode = OP_IMIN;
8376                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8377                                         opcode = OP_IMIN_UN;
8378                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8379                                         opcode = OP_LMIN;
8380                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8381                                         opcode = OP_LMIN_UN;
8382                         } else if (strcmp (cmethod->name, "Max") == 0) {
8383                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8384                                         opcode = OP_IMAX;
8385                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8386                                         opcode = OP_IMAX_UN;
8387                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8388                                         opcode = OP_LMAX;
8389                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8390                                         opcode = OP_LMAX_UN;
8391                         }
8392                 }
8393
8394                 if (opcode && fsig->param_count == 2) {
8395                         MONO_INST_NEW (cfg, ins, opcode);
8396                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8397                         ins->dreg = mono_alloc_ireg (cfg);
8398                         ins->sreg1 = args [0]->dreg;
8399                         ins->sreg2 = args [1]->dreg;
8400                         MONO_ADD_INS (cfg->cbb, ins);
8401                 }
8402
8403 #if 0
8404                 /* OP_FREM is not IEEE compatible */
8405                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8406                         MONO_INST_NEW (cfg, ins, OP_FREM);
8407                         ins->inst_i0 = args [0];
8408                         ins->inst_i1 = args [1];
8409                 }
8410 #endif
8411         }
8412
8413         return ins;
8414 }
8415 #endif
8416
8417 gboolean
8418 mono_arch_print_tree (MonoInst *tree, int arity)
8419 {
8420         return 0;
8421 }
8422
8423 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8424
8425 mgreg_t
8426 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8427 {
8428         switch (reg) {
8429         case AMD64_RCX: return ctx->rcx;
8430         case AMD64_RDX: return ctx->rdx;
8431         case AMD64_RBX: return ctx->rbx;
8432         case AMD64_RBP: return ctx->rbp;
8433         case AMD64_RSP: return ctx->rsp;
8434         default:
8435                 return _CTX_REG (ctx, rax, reg);
8436         }
8437 }
8438
8439 void
8440 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8441 {
8442         switch (reg) {
8443         case AMD64_RCX:
8444                 ctx->rcx = val;
8445                 break;
8446         case AMD64_RDX:
8447                 ctx->rdx = val;
8448                 break;
8449         case AMD64_RBX:
8450                 ctx->rbx = val;
8451                 break;
8452         case AMD64_RBP:
8453                 ctx->rbp = val;
8454                 break;
8455         case AMD64_RSP:
8456                 ctx->rsp = val;
8457                 break;
8458         default:
8459                 _CTX_REG (ctx, rax, reg) = val;
8460         }
8461 }
8462
8463 gpointer
8464 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8465 {
8466         gpointer *sp, old_value;
8467         char *bp;
8468
8469         /*Load the spvar*/
8470         bp = MONO_CONTEXT_GET_BP (ctx);
8471         sp = *(gpointer*)(bp + clause->exvar_offset);
8472
8473         old_value = *sp;
8474         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8475                 return old_value;
8476
8477         *sp = new_value;
8478
8479         return old_value;
8480 }
8481
8482 /*
8483  * mono_arch_emit_load_aotconst:
8484  *
8485  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8486  * TARGET from the mscorlib GOT in full-aot code.
8487  * On AMD64, the result is placed into R11.
8488  */
8489 guint8*
8490 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8491 {
8492         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8493         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8494
8495         return code;
8496 }
8497
8498 /*
8499  * mono_arch_get_trampolines:
8500  *
8501  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8502  * for AOT.
8503  */
8504 GSList *
8505 mono_arch_get_trampolines (gboolean aot)
8506 {
8507         return mono_amd64_get_exception_trampolines (aot);
8508 }
8509
8510 /* Soft Debug support */
8511 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8512
8513 /*
8514  * mono_arch_set_breakpoint:
8515  *
8516  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8517  * The location should contain code emitted by OP_SEQ_POINT.
8518  */
8519 void
8520 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8521 {
8522         guint8 *code = ip;
8523         guint8 *orig_code = code;
8524
8525         if (ji->from_aot) {
8526                 guint32 native_offset = ip - (guint8*)ji->code_start;
8527                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8528
8529                 g_assert (info->bp_addrs [native_offset] == 0);
8530                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8531         } else {
8532                 /*
8533                  * In production, we will use int3 (has to fix the size in the md
8534                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8535                  * instead.
8536                  */
8537                 g_assert (code [0] == 0x90);
8538                 if (breakpoint_size == 8) {
8539                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8540                 } else {
8541                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8542                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8543                 }
8544
8545                 g_assert (code - orig_code == breakpoint_size);
8546         }
8547 }
8548
8549 /*
8550  * mono_arch_clear_breakpoint:
8551  *
8552  *   Clear the breakpoint at IP.
8553  */
8554 void
8555 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8556 {
8557         guint8 *code = ip;
8558         int i;
8559
8560         if (ji->from_aot) {
8561                 guint32 native_offset = ip - (guint8*)ji->code_start;
8562                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8563
8564                 info->bp_addrs [native_offset] = NULL;
8565         } else {
8566                 for (i = 0; i < breakpoint_size; ++i)
8567                         x86_nop (code);
8568         }
8569 }
8570
8571 gboolean
8572 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8573 {
8574 #ifdef HOST_WIN32
8575         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8576         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8577                 return TRUE;
8578         else
8579                 return FALSE;
8580 #else
8581         siginfo_t* sinfo = (siginfo_t*) info;
8582         /* Sometimes the address is off by 4 */
8583         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8584                 return TRUE;
8585         else
8586                 return FALSE;
8587 #endif
8588 }
8589
8590 /*
8591  * mono_arch_skip_breakpoint:
8592  *
8593  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8594  * we resume, the instruction is not executed again.
8595  */
8596 void
8597 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8598 {
8599         if (ji->from_aot) {
8600                 /* The breakpoint instruction is a call */
8601         } else {
8602                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8603         }
8604 }
8605
8606 /*
8607  * mono_arch_start_single_stepping:
8608  *
8609  *   Start single stepping.
8610  */
8611 void
8612 mono_arch_start_single_stepping (void)
8613 {
8614         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8615         ss_trampoline = mini_get_single_step_trampoline ();
8616 }
8617
8618 /*
8619  * mono_arch_stop_single_stepping:
8620  *
8621  *   Stop single stepping.
8622  */
8623 void
8624 mono_arch_stop_single_stepping (void)
8625 {
8626         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8627         ss_trampoline = NULL;
8628 }
8629
8630 /*
8631  * mono_arch_is_single_step_event:
8632  *
8633  *   Return whenever the machine state in SIGCTX corresponds to a single
8634  * step event.
8635  */
8636 gboolean
8637 mono_arch_is_single_step_event (void *info, void *sigctx)
8638 {
8639 #ifdef HOST_WIN32
8640         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8641         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8642                 return TRUE;
8643         else
8644                 return FALSE;
8645 #else
8646         siginfo_t* sinfo = (siginfo_t*) info;
8647         /* Sometimes the address is off by 4 */
8648         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8649                 return TRUE;
8650         else
8651                 return FALSE;
8652 #endif
8653 }
8654
8655 /*
8656  * mono_arch_skip_single_step:
8657  *
8658  *   Modify CTX so the ip is placed after the single step trigger instruction,
8659  * we resume, the instruction is not executed again.
8660  */
8661 void
8662 mono_arch_skip_single_step (MonoContext *ctx)
8663 {
8664         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8665 }
8666
8667 /*
8668  * mono_arch_create_seq_point_info:
8669  *
8670  *   Return a pointer to a data structure which is used by the sequence
8671  * point implementation in AOTed code.
8672  */
8673 gpointer
8674 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8675 {
8676         SeqPointInfo *info;
8677         MonoJitInfo *ji;
8678
8679         // FIXME: Add a free function
8680
8681         mono_domain_lock (domain);
8682         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8683                                                                 code);
8684         mono_domain_unlock (domain);
8685
8686         if (!info) {
8687                 ji = mono_jit_info_table_find (domain, (char*)code);
8688                 g_assert (ji);
8689
8690                 // FIXME: Optimize the size
8691                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8692
8693                 info->ss_tramp_addr = &ss_trampoline;
8694
8695                 mono_domain_lock (domain);
8696                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8697                                                          code, info);
8698                 mono_domain_unlock (domain);
8699         }
8700
8701         return info;
8702 }
8703
8704 void
8705 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8706 {
8707         ext->lmf.previous_lmf = prev_lmf;
8708         /* Mark that this is a MonoLMFExt */
8709         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8710         ext->lmf.rsp = (gssize)ext;
8711 }
8712
8713 #endif
8714
8715 gboolean
8716 mono_arch_opcode_supported (int opcode)
8717 {
8718         switch (opcode) {
8719         case OP_ATOMIC_ADD_I4:
8720         case OP_ATOMIC_ADD_I8:
8721         case OP_ATOMIC_EXCHANGE_I4:
8722         case OP_ATOMIC_EXCHANGE_I8:
8723         case OP_ATOMIC_CAS_I4:
8724         case OP_ATOMIC_CAS_I8:
8725         case OP_ATOMIC_LOAD_I1:
8726         case OP_ATOMIC_LOAD_I2:
8727         case OP_ATOMIC_LOAD_I4:
8728         case OP_ATOMIC_LOAD_I8:
8729         case OP_ATOMIC_LOAD_U1:
8730         case OP_ATOMIC_LOAD_U2:
8731         case OP_ATOMIC_LOAD_U4:
8732         case OP_ATOMIC_LOAD_U8:
8733         case OP_ATOMIC_LOAD_R4:
8734         case OP_ATOMIC_LOAD_R8:
8735         case OP_ATOMIC_STORE_I1:
8736         case OP_ATOMIC_STORE_I2:
8737         case OP_ATOMIC_STORE_I4:
8738         case OP_ATOMIC_STORE_I8:
8739         case OP_ATOMIC_STORE_U1:
8740         case OP_ATOMIC_STORE_U2:
8741         case OP_ATOMIC_STORE_U4:
8742         case OP_ATOMIC_STORE_U8:
8743         case OP_ATOMIC_STORE_R4:
8744         case OP_ATOMIC_STORE_R8:
8745                 return TRUE;
8746         default:
8747                 return FALSE;
8748         }
8749 }