mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011 }
1012
1013 GList *
1014 mono_arch_get_global_int_regs (MonoCompile *cfg)
1015 {
1016         GList *regs = NULL;
1017
1018         mono_arch_compute_omit_fp (cfg);
1019
1020         if (cfg->globalra) {
1021                 if (cfg->arch.omit_fp)
1022                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1023
1024                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1025                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1026                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1027                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1028                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1029
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1034                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1038         } else {
1039                 if (cfg->arch.omit_fp)
1040                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1041
1042                 /* We use the callee saved registers for global allocation */
1043                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1048 #ifdef PLATFORM_WIN32
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1051 #endif
1052         }
1053
1054         return regs;
1055 }
1056
1057 GList*
1058 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1059 {
1060         GList *regs = NULL;
1061         int i;
1062
1063         /* All XMM registers */
1064         for (i = 0; i < 16; ++i)
1065                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1066
1067         return regs;
1068 }
1069
1070 GList*
1071 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1072 {
1073         static GList *r = NULL;
1074
1075         if (r == NULL) {
1076                 GList *regs = NULL;
1077
1078                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1084
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1093
1094                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1095         }
1096
1097         return r;
1098 }
1099
1100 GList*
1101 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1102 {
1103         int i;
1104         static GList *r = NULL;
1105
1106         if (r == NULL) {
1107                 GList *regs = NULL;
1108
1109                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1110                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1111
1112                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1113         }
1114
1115         return r;
1116 }
1117
1118 /*
1119  * mono_arch_regalloc_cost:
1120  *
1121  *  Return the cost, in number of memory references, of the action of
1122  * allocating the variable VMV into a register during global register
1123  * allocation.
1124  */
1125 guint32
1126 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1127 {
1128         MonoInst *ins = cfg->varinfo [vmv->idx];
1129
1130         if (cfg->method->save_lmf)
1131                 /* The register is already saved */
1132                 /* substract 1 for the invisible store in the prolog */
1133                 return (ins->opcode == OP_ARG) ? 0 : 1;
1134         else
1135                 /* push+pop */
1136                 return (ins->opcode == OP_ARG) ? 1 : 2;
1137 }
1138
1139 /*
1140  * mono_arch_fill_argument_info:
1141  *
1142  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1143  * of the method.
1144  */
1145 void
1146 mono_arch_fill_argument_info (MonoCompile *cfg)
1147 {
1148         MonoMethodSignature *sig;
1149         MonoMethodHeader *header;
1150         MonoInst *ins;
1151         int i;
1152         CallInfo *cinfo;
1153
1154         header = mono_method_get_header (cfg->method);
1155
1156         sig = mono_method_signature (cfg->method);
1157
1158         cinfo = cfg->arch.cinfo;
1159
1160         /*
1161          * Contrary to mono_arch_allocate_vars (), the information should describe
1162          * where the arguments are at the beginning of the method, not where they can be
1163          * accessed during the execution of the method. The later makes no sense for the
1164          * global register allocator, since a variable can be in more than one location.
1165          */
1166         if (sig->ret->type != MONO_TYPE_VOID) {
1167                 switch (cinfo->ret.storage) {
1168                 case ArgInIReg:
1169                 case ArgInFloatSSEReg:
1170                 case ArgInDoubleSSEReg:
1171                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1172                                 cfg->vret_addr->opcode = OP_REGVAR;
1173                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1174                         }
1175                         else {
1176                                 cfg->ret->opcode = OP_REGVAR;
1177                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1178                         }
1179                         break;
1180                 case ArgValuetypeInReg:
1181                         cfg->ret->opcode = OP_REGOFFSET;
1182                         cfg->ret->inst_basereg = -1;
1183                         cfg->ret->inst_offset = -1;
1184                         break;
1185                 default:
1186                         g_assert_not_reached ();
1187                 }
1188         }
1189
1190         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1191                 ArgInfo *ainfo = &cinfo->args [i];
1192                 MonoType *arg_type;
1193
1194                 ins = cfg->args [i];
1195
1196                 if (sig->hasthis && (i == 0))
1197                         arg_type = &mono_defaults.object_class->byval_arg;
1198                 else
1199                         arg_type = sig->params [i - sig->hasthis];
1200
1201                 switch (ainfo->storage) {
1202                 case ArgInIReg:
1203                 case ArgInFloatSSEReg:
1204                 case ArgInDoubleSSEReg:
1205                         ins->opcode = OP_REGVAR;
1206                         ins->inst_c0 = ainfo->reg;
1207                         break;
1208                 case ArgOnStack:
1209                         ins->opcode = OP_REGOFFSET;
1210                         ins->inst_basereg = -1;
1211                         ins->inst_offset = -1;
1212                         break;
1213                 case ArgValuetypeInReg:
1214                         /* Dummy */
1215                         ins->opcode = OP_NOP;
1216                         break;
1217                 default:
1218                         g_assert_not_reached ();
1219                 }
1220         }
1221 }
1222
1223 void
1224 mono_arch_allocate_vars (MonoCompile *cfg)
1225 {
1226         MonoMethodSignature *sig;
1227         MonoMethodHeader *header;
1228         MonoInst *ins;
1229         int i, offset;
1230         guint32 locals_stack_size, locals_stack_align;
1231         gint32 *offsets;
1232         CallInfo *cinfo;
1233
1234         header = mono_method_get_header (cfg->method);
1235
1236         sig = mono_method_signature (cfg->method);
1237
1238         cinfo = cfg->arch.cinfo;
1239
1240         mono_arch_compute_omit_fp (cfg);
1241
1242         /*
1243          * We use the ABI calling conventions for managed code as well.
1244          * Exception: valuetypes are never passed or returned in registers.
1245          */
1246
1247         if (cfg->arch.omit_fp) {
1248                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1249                 cfg->frame_reg = AMD64_RSP;
1250                 offset = 0;
1251         } else {
1252                 /* Locals are allocated backwards from %fp */
1253                 cfg->frame_reg = AMD64_RBP;
1254                 offset = 0;
1255         }
1256
1257         if (cfg->method->save_lmf) {
1258                 /* Reserve stack space for saving LMF */
1259                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1260                 g_assert (offset == 0);
1261                 if (cfg->arch.omit_fp) {
1262                         cfg->arch.lmf_offset = offset;
1263                         offset += sizeof (MonoLMF);
1264                 }
1265                 else {
1266                         offset += sizeof (MonoLMF);
1267                         cfg->arch.lmf_offset = -offset;
1268                 }
1269         } else {
1270                 if (cfg->arch.omit_fp)
1271                         cfg->arch.reg_save_area_offset = offset;
1272                 /* Reserve space for caller saved registers */
1273                 for (i = 0; i < AMD64_NREG; ++i)
1274                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1275                                 offset += sizeof (gpointer);
1276                         }
1277         }
1278
1279         if (sig->ret->type != MONO_TYPE_VOID) {
1280                 switch (cinfo->ret.storage) {
1281                 case ArgInIReg:
1282                 case ArgInFloatSSEReg:
1283                 case ArgInDoubleSSEReg:
1284                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1285                                 if (cfg->globalra) {
1286                                         cfg->vret_addr->opcode = OP_REGVAR;
1287                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1288                                 } else {
1289                                         /* The register is volatile */
1290                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1291                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1292                                         if (cfg->arch.omit_fp) {
1293                                                 cfg->vret_addr->inst_offset = offset;
1294                                                 offset += 8;
1295                                         } else {
1296                                                 offset += 8;
1297                                                 cfg->vret_addr->inst_offset = -offset;
1298                                         }
1299                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1300                                                 printf ("vret_addr =");
1301                                                 mono_print_ins (cfg->vret_addr);
1302                                         }
1303                                 }
1304                         }
1305                         else {
1306                                 cfg->ret->opcode = OP_REGVAR;
1307                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1308                         }
1309                         break;
1310                 case ArgValuetypeInReg:
1311                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1312                         cfg->ret->opcode = OP_REGOFFSET;
1313                         cfg->ret->inst_basereg = cfg->frame_reg;
1314                         if (cfg->arch.omit_fp) {
1315                                 cfg->ret->inst_offset = offset;
1316                                 offset += 16;
1317                         } else {
1318                                 offset += 16;
1319                                 cfg->ret->inst_offset = - offset;
1320                         }
1321                         break;
1322                 default:
1323                         g_assert_not_reached ();
1324                 }
1325                 if (!cfg->globalra)
1326                         cfg->ret->dreg = cfg->ret->inst_c0;
1327         }
1328
1329         /* Allocate locals */
1330         if (!cfg->globalra) {
1331                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1332                 if (locals_stack_align) {
1333                         offset += (locals_stack_align - 1);
1334                         offset &= ~(locals_stack_align - 1);
1335                 }
1336                 if (cfg->arch.omit_fp) {
1337                         cfg->locals_min_stack_offset = offset;
1338                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1339                 } else {
1340                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1341                         cfg->locals_max_stack_offset = - offset;
1342                 }
1343
1344                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1345                         if (offsets [i] != -1) {
1346                                 MonoInst *ins = cfg->varinfo [i];
1347                                 ins->opcode = OP_REGOFFSET;
1348                                 ins->inst_basereg = cfg->frame_reg;
1349                                 if (cfg->arch.omit_fp)
1350                                         ins->inst_offset = (offset + offsets [i]);
1351                                 else
1352                                         ins->inst_offset = - (offset + offsets [i]);
1353                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1354                         }
1355                 }
1356                 offset += locals_stack_size;
1357         }
1358
1359         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1360                 g_assert (!cfg->arch.omit_fp);
1361                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1362                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1363         }
1364
1365         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1366                 ins = cfg->args [i];
1367                 if (ins->opcode != OP_REGVAR) {
1368                         ArgInfo *ainfo = &cinfo->args [i];
1369                         gboolean inreg = TRUE;
1370                         MonoType *arg_type;
1371
1372                         if (sig->hasthis && (i == 0))
1373                                 arg_type = &mono_defaults.object_class->byval_arg;
1374                         else
1375                                 arg_type = sig->params [i - sig->hasthis];
1376
1377                         if (cfg->globalra) {
1378                                 /* The new allocator needs info about the original locations of the arguments */
1379                                 switch (ainfo->storage) {
1380                                 case ArgInIReg:
1381                                 case ArgInFloatSSEReg:
1382                                 case ArgInDoubleSSEReg:
1383                                         ins->opcode = OP_REGVAR;
1384                                         ins->inst_c0 = ainfo->reg;
1385                                         break;
1386                                 case ArgOnStack:
1387                                         g_assert (!cfg->arch.omit_fp);
1388                                         ins->opcode = OP_REGOFFSET;
1389                                         ins->inst_basereg = cfg->frame_reg;
1390                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1391                                         break;
1392                                 case ArgValuetypeInReg:
1393                                         ins->opcode = OP_REGOFFSET;
1394                                         ins->inst_basereg = cfg->frame_reg;
1395                                         /* These arguments are saved to the stack in the prolog */
1396                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1397                                         if (cfg->arch.omit_fp) {
1398                                                 ins->inst_offset = offset;
1399                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1400                                         } else {
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                                 ins->inst_offset = - offset;
1403                                         }
1404                                         break;
1405                                 default:
1406                                         g_assert_not_reached ();
1407                                 }
1408
1409                                 continue;
1410                         }
1411
1412                         /* FIXME: Allocate volatile arguments to registers */
1413                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1414                                 inreg = FALSE;
1415
1416                         /*
1417                          * Under AMD64, all registers used to pass arguments to functions
1418                          * are volatile across calls.
1419                          * FIXME: Optimize this.
1420                          */
1421                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1422                                 inreg = FALSE;
1423
1424                         ins->opcode = OP_REGOFFSET;
1425
1426                         switch (ainfo->storage) {
1427                         case ArgInIReg:
1428                         case ArgInFloatSSEReg:
1429                         case ArgInDoubleSSEReg:
1430                                 if (inreg) {
1431                                         ins->opcode = OP_REGVAR;
1432                                         ins->dreg = ainfo->reg;
1433                                 }
1434                                 break;
1435                         case ArgOnStack:
1436                                 g_assert (!cfg->arch.omit_fp);
1437                                 ins->opcode = OP_REGOFFSET;
1438                                 ins->inst_basereg = cfg->frame_reg;
1439                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1440                                 break;
1441                         case ArgValuetypeInReg:
1442                                 break;
1443                         case ArgValuetypeAddrInIReg: {
1444                                 MonoInst *indir;
1445                                 g_assert (!cfg->arch.omit_fp);
1446
1447                                 MONO_INST_NEW (cfg, indir, 0);
1448                                 indir->opcode = OP_REGOFFSET;
1449                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1450                                         indir->inst_basereg = cfg->frame_reg;
1451                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1452                                         offset += (sizeof (gpointer));
1453                                         indir->inst_offset = - offset;
1454                                 }
1455                                 else {
1456                                         indir->inst_basereg = cfg->frame_reg;
1457                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1458                                 }
1459
1460                                 ins->opcode = OP_VTARG_ADDR;
1461                                 ins->inst_left = indir;
1462
1463                                 break;
1464                         }
1465                         default:
1466                                 NOT_IMPLEMENTED;
1467                         }
1468
1469                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1470                                 ins->opcode = OP_REGOFFSET;
1471                                 ins->inst_basereg = cfg->frame_reg;
1472                                 /* These arguments are saved to the stack in the prolog */
1473                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1474                                 if (cfg->arch.omit_fp) {
1475                                         ins->inst_offset = offset;
1476                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1477                                 } else {
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                         ins->inst_offset = - offset;
1480                                 }
1481                         }
1482                 }
1483         }
1484
1485         cfg->stack_offset = offset;
1486 }
1487
1488 void
1489 mono_arch_create_vars (MonoCompile *cfg)
1490 {
1491         MonoMethodSignature *sig;
1492         CallInfo *cinfo;
1493
1494         sig = mono_method_signature (cfg->method);
1495
1496         if (!cfg->arch.cinfo)
1497                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1498         cinfo = cfg->arch.cinfo;
1499
1500         if (cinfo->ret.storage == ArgValuetypeInReg)
1501                 cfg->ret_var_is_local = TRUE;
1502
1503         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1504                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1505                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1506                         printf ("vret_addr = ");
1507                         mono_print_ins (cfg->vret_addr);
1508                 }
1509         }
1510 }
1511
1512 static void
1513 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1514 {
1515         MonoInst *ins;
1516
1517         switch (storage) {
1518         case ArgInIReg:
1519                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1520                 ins->dreg = mono_alloc_ireg (cfg);
1521                 ins->sreg1 = tree->dreg;
1522                 MONO_ADD_INS (cfg->cbb, ins);
1523                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1524                 break;
1525         case ArgInFloatSSEReg:
1526                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1527                 ins->dreg = mono_alloc_freg (cfg);
1528                 ins->sreg1 = tree->dreg;
1529                 MONO_ADD_INS (cfg->cbb, ins);
1530
1531                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1532                 break;
1533         case ArgInDoubleSSEReg:
1534                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1535                 ins->dreg = mono_alloc_freg (cfg);
1536                 ins->sreg1 = tree->dreg;
1537                 MONO_ADD_INS (cfg->cbb, ins);
1538
1539                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1540
1541                 break;
1542         default:
1543                 g_assert_not_reached ();
1544         }
1545 }
1546
1547 static int
1548 arg_storage_to_load_membase (ArgStorage storage)
1549 {
1550         switch (storage) {
1551         case ArgInIReg:
1552                 return OP_LOAD_MEMBASE;
1553         case ArgInDoubleSSEReg:
1554                 return OP_LOADR8_MEMBASE;
1555         case ArgInFloatSSEReg:
1556                 return OP_LOADR4_MEMBASE;
1557         default:
1558                 g_assert_not_reached ();
1559         }
1560
1561         return -1;
1562 }
1563
1564 static void
1565 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1566 {
1567         MonoInst *arg;
1568         MonoMethodSignature *tmp_sig;
1569         MonoInst *sig_arg;
1570
1571         if (call->tail_call)
1572                 NOT_IMPLEMENTED;
1573
1574         /* FIXME: Add support for signature tokens to AOT */
1575         cfg->disable_aot = TRUE;
1576
1577         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1578
1579         /*
1580          * mono_ArgIterator_Setup assumes the signature cookie is
1581          * passed first and all the arguments which were before it are
1582          * passed on the stack after the signature. So compensate by
1583          * passing a different signature.
1584          */
1585         tmp_sig = mono_metadata_signature_dup (call->signature);
1586         tmp_sig->param_count -= call->signature->sentinelpos;
1587         tmp_sig->sentinelpos = 0;
1588         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1589
1590         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1591         sig_arg->dreg = mono_alloc_ireg (cfg);
1592         sig_arg->inst_p0 = tmp_sig;
1593         MONO_ADD_INS (cfg->cbb, sig_arg);
1594
1595         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1596         arg->sreg1 = sig_arg->dreg;
1597         MONO_ADD_INS (cfg->cbb, arg);
1598 }
1599
1600 void
1601 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1602 {
1603         MonoInst *arg, *in;
1604         MonoMethodSignature *sig;
1605         int i, n, stack_size;
1606         CallInfo *cinfo;
1607         ArgInfo *ainfo;
1608
1609         stack_size = 0;
1610
1611         sig = call->signature;
1612         n = sig->param_count + sig->hasthis;
1613
1614         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1615
1616         if (COMPILE_LLVM (cfg)) {
1617                 for (i = 0; i < n; ++i) {
1618                         MonoInst *ins;
1619
1620                         ainfo = cinfo->args + i;
1621
1622                         in = call->args [i];
1623
1624                         /* Simply remember the arguments */
1625                         switch (ainfo->storage) {
1626                         case ArgInIReg:
1627                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1628                                 ins->dreg = mono_alloc_ireg (cfg);
1629                                 ins->sreg1 = in->dreg;
1630                                 break;
1631                         case ArgInDoubleSSEReg:
1632                         case ArgInFloatSSEReg:
1633                                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1634                                 ins->dreg = mono_alloc_freg (cfg);
1635                                 ins->sreg1 = in->dreg;
1636                                 break;
1637                         case ArgOnStack:
1638                                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1639                                         cfg->exception_message = g_strdup ("vtype argument");
1640                                         cfg->disable_llvm = TRUE;
1641                                 } else {
1642                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1643                                         ins->dreg = mono_alloc_ireg (cfg);
1644                                         ins->sreg1 = in->dreg;
1645                                 }
1646                                 break;
1647                         default:
1648                                 cfg->exception_message = g_strdup ("ainfo->storage");
1649                                 cfg->disable_llvm = TRUE;
1650                                 return;
1651                         }
1652
1653                         if (!cfg->disable_llvm) {
1654                                 MONO_ADD_INS (cfg->cbb, ins);
1655                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, 0, FALSE);
1656                         }
1657                 }
1658                 return;
1659         }
1660
1661         if (cinfo->need_stack_align) {
1662                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1663         }
1664
1665         /*
1666          * Emit all parameters passed in registers in non-reverse order for better readability
1667          * and to help the optimization in emit_prolog ().
1668          */
1669         for (i = 0; i < n; ++i) {
1670                 ainfo = cinfo->args + i;
1671
1672                 in = call->args [i];
1673
1674                 if (ainfo->storage == ArgInIReg)
1675                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1676         }
1677
1678         for (i = n - 1; i >= 0; --i) {
1679                 ainfo = cinfo->args + i;
1680
1681                 in = call->args [i];
1682
1683                 switch (ainfo->storage) {
1684                 case ArgInIReg:
1685                         /* Already done */
1686                         break;
1687                 case ArgInFloatSSEReg:
1688                 case ArgInDoubleSSEReg:
1689                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1690                         break;
1691                 case ArgOnStack:
1692                 case ArgValuetypeInReg:
1693                 case ArgValuetypeAddrInIReg:
1694                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1695                                 MonoInst *call_inst = (MonoInst*)call;
1696                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1697                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1698                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1699                                 guint32 align;
1700                                 guint32 size;
1701
1702                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1703                                         size = sizeof (MonoTypedRef);
1704                                         align = sizeof (gpointer);
1705                                 }
1706                                 else {
1707                                         if (sig->pinvoke)
1708                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1709                                         else {
1710                                                 /*
1711                                                  * Other backends use mono_type_stack_size (), but that
1712                                                  * aligns the size to 8, which is larger than the size of
1713                                                  * the source, leading to reads of invalid memory if the
1714                                                  * source is at the end of address space.
1715                                                  */
1716                                                 size = mono_class_value_size (in->klass, &align);
1717                                         }
1718                                 }
1719                                 g_assert (in->klass);
1720
1721                                 if (size > 0) {
1722                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1723                                         arg->sreg1 = in->dreg;
1724                                         arg->klass = in->klass;
1725                                         arg->backend.size = size;
1726                                         arg->inst_p0 = call;
1727                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1728                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1729
1730                                         MONO_ADD_INS (cfg->cbb, arg);
1731                                 }
1732                         } else {
1733                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1734                                 arg->sreg1 = in->dreg;
1735                                 if (!sig->params [i - sig->hasthis]->byref) {
1736                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1737                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1738                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1739                                                 arg->inst_destbasereg = X86_ESP;
1740                                                 arg->inst_offset = 0;
1741                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1742                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1743                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1744                                                 arg->inst_destbasereg = X86_ESP;
1745                                                 arg->inst_offset = 0;
1746                                         }
1747                                 }
1748                                 MONO_ADD_INS (cfg->cbb, arg);
1749                         }
1750                         break;
1751                 default:
1752                         g_assert_not_reached ();
1753                 }
1754
1755                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1756                         /* Emit the signature cookie just before the implicit arguments */
1757                         emit_sig_cookie (cfg, call, cinfo);
1758         }
1759
1760         /* Handle the case where there are no implicit arguments */
1761         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1762                 emit_sig_cookie (cfg, call, cinfo);
1763
1764         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1765                 MonoInst *vtarg;
1766
1767                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1768                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1769                                 /*
1770                                  * Tell the JIT to use a more efficient calling convention: call using
1771                                  * OP_CALL, compute the result location after the call, and save the
1772                                  * result there.
1773                                  */
1774                                 call->vret_in_reg = TRUE;
1775                                 /*
1776                                  * Nullify the instruction computing the vret addr to enable
1777                                  * future optimizations.
1778                                  */
1779                                 if (call->vret_var)
1780                                         NULLIFY_INS (call->vret_var);
1781                         } else {
1782                                 if (call->tail_call)
1783                                         NOT_IMPLEMENTED;
1784                                 /*
1785                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1786                                  * the stack. Push the address here, so the call instruction can
1787                                  * access it.
1788                                  */
1789                                 if (!cfg->arch.vret_addr_loc) {
1790                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1791                                         /* Prevent it from being register allocated or optimized away */
1792                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1793                                 }
1794
1795                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1796                         }
1797                 }
1798                 else {
1799                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1800                         vtarg->sreg1 = call->vret_var->dreg;
1801                         vtarg->dreg = mono_alloc_preg (cfg);
1802                         MONO_ADD_INS (cfg->cbb, vtarg);
1803
1804                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1805                 }
1806         }
1807
1808 #ifdef PLATFORM_WIN32
1809         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1810                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1811         }
1812 #endif
1813
1814         if (cfg->method->save_lmf) {
1815                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1816                 MONO_ADD_INS (cfg->cbb, arg);
1817         }
1818
1819         call->stack_usage = cinfo->stack_usage;
1820 }
1821
1822 void
1823 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1824 {
1825         MonoInst *arg;
1826         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1827         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1828         int size = ins->backend.size;
1829
1830         if (ainfo->storage == ArgValuetypeInReg) {
1831                 MonoInst *load;
1832                 int part;
1833
1834                 for (part = 0; part < 2; ++part) {
1835                         if (ainfo->pair_storage [part] == ArgNone)
1836                                 continue;
1837
1838                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1839                         load->inst_basereg = src->dreg;
1840                         load->inst_offset = part * sizeof (gpointer);
1841
1842                         switch (ainfo->pair_storage [part]) {
1843                         case ArgInIReg:
1844                                 load->dreg = mono_alloc_ireg (cfg);
1845                                 break;
1846                         case ArgInDoubleSSEReg:
1847                         case ArgInFloatSSEReg:
1848                                 load->dreg = mono_alloc_freg (cfg);
1849                                 break;
1850                         default:
1851                                 g_assert_not_reached ();
1852                         }
1853                         MONO_ADD_INS (cfg->cbb, load);
1854
1855                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1856                 }
1857         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1858                 MonoInst *vtaddr, *load;
1859                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1860
1861                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1862                 load->inst_p0 = vtaddr;
1863                 vtaddr->flags |= MONO_INST_INDIRECT;
1864                 load->type = STACK_MP;
1865                 load->klass = vtaddr->klass;
1866                 load->dreg = mono_alloc_ireg (cfg);
1867                 MONO_ADD_INS (cfg->cbb, load);
1868                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1869
1870                 if (ainfo->pair_storage [0] == ArgInIReg) {
1871                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1872                         arg->dreg = mono_alloc_ireg (cfg);
1873                         arg->sreg1 = load->dreg;
1874                         arg->inst_imm = 0;
1875                         MONO_ADD_INS (cfg->cbb, arg);
1876                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1877                 } else {
1878                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1879                         arg->sreg1 = load->dreg;
1880                         MONO_ADD_INS (cfg->cbb, arg);
1881                 }
1882         } else {
1883                 if (size == 8) {
1884                         /* Can't use this for < 8 since it does an 8 byte memory load */
1885                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1886                         arg->inst_basereg = src->dreg;
1887                         arg->inst_offset = 0;
1888                         MONO_ADD_INS (cfg->cbb, arg);
1889                 } else if (size <= 40) {
1890                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1891                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1892                 } else {
1893                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1894                         arg->inst_basereg = src->dreg;
1895                         arg->inst_offset = 0;
1896                         arg->inst_imm = size;
1897                         MONO_ADD_INS (cfg->cbb, arg);
1898                 }
1899         }
1900 }
1901
1902 void
1903 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1904 {
1905         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1906
1907         if (!ret->byref) {
1908                 if (ret->type == MONO_TYPE_R4) {
1909                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1910                         return;
1911                 } else if (ret->type == MONO_TYPE_R8) {
1912                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1913                         return;
1914                 }
1915         }
1916
1917         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1918 }
1919
1920 #define EMIT_COND_BRANCH(ins,cond,sign) \
1921 if (ins->flags & MONO_INST_BRLABEL) { \
1922         if (ins->inst_i0->inst_c0) { \
1923                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1924         } else { \
1925                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1926                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1927                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1928                         x86_branch8 (code, cond, 0, sign); \
1929                 else \
1930                         x86_branch32 (code, cond, 0, sign); \
1931         } \
1932 } else { \
1933         if (ins->inst_true_bb->native_offset) { \
1934                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1935         } else { \
1936                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1937                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1938                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1939                         x86_branch8 (code, cond, 0, sign); \
1940                 else \
1941                         x86_branch32 (code, cond, 0, sign); \
1942         } \
1943 }
1944
1945 /* emit an exception if condition is fail */
1946 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1947         do {                                                        \
1948                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1949                 if (tins == NULL) {                                                                             \
1950                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1951                                         MONO_PATCH_INFO_EXC, exc_name);  \
1952                         x86_branch32 (code, cond, 0, signed);               \
1953                 } else {        \
1954                         EMIT_COND_BRANCH (tins, cond, signed);  \
1955                 }                       \
1956         } while (0);
1957
1958 #define EMIT_FPCOMPARE(code) do { \
1959         amd64_fcompp (code); \
1960         amd64_fnstsw (code); \
1961 } while (0);
1962
1963 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1964     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1965         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1966         amd64_ ##op (code); \
1967         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1968         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1969 } while (0);
1970
1971 static guint8*
1972 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1973 {
1974         gboolean no_patch = FALSE;
1975
1976         /*
1977          * FIXME: Add support for thunks
1978          */
1979         {
1980                 gboolean near_call = FALSE;
1981
1982                 /*
1983                  * Indirect calls are expensive so try to make a near call if possible.
1984                  * The caller memory is allocated by the code manager so it is
1985                  * guaranteed to be at a 32 bit offset.
1986                  */
1987
1988                 if (patch_type != MONO_PATCH_INFO_ABS) {
1989                         /* The target is in memory allocated using the code manager */
1990                         near_call = TRUE;
1991
1992                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1993                                 if (((MonoMethod*)data)->klass->image->aot_module)
1994                                         /* The callee might be an AOT method */
1995                                         near_call = FALSE;
1996                                 if (((MonoMethod*)data)->dynamic)
1997                                         /* The target is in malloc-ed memory */
1998                                         near_call = FALSE;
1999                         }
2000
2001                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2002                                 /*
2003                                  * The call might go directly to a native function without
2004                                  * the wrapper.
2005                                  */
2006                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2007                                 if (mi) {
2008                                         gconstpointer target = mono_icall_get_wrapper (mi);
2009                                         if ((((guint64)target) >> 32) != 0)
2010                                                 near_call = FALSE;
2011                                 }
2012                         }
2013                 }
2014                 else {
2015                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2016                                 /*
2017                                  * This is not really an optimization, but required because the
2018                                  * generic class init trampolines use R11 to pass the vtable.
2019                                  */
2020                                 near_call = TRUE;
2021                         } else {
2022                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2023                                 if (info) {
2024                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2025                                                 strstr (cfg->method->name, info->name)) {
2026                                                 /* A call to the wrapped function */
2027                                                 if ((((guint64)data) >> 32) == 0)
2028                                                         near_call = TRUE;
2029                                                 no_patch = TRUE;
2030                                         }
2031                                         else if (info->func == info->wrapper) {
2032                                                 /* No wrapper */
2033                                                 if ((((guint64)info->func) >> 32) == 0)
2034                                                         near_call = TRUE;
2035                                         }
2036                                         else {
2037                                                 /* See the comment in mono_codegen () */
2038                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2039                                                         near_call = TRUE;
2040                                         }
2041                                 }
2042                                 else if ((((guint64)data) >> 32) == 0) {
2043                                         near_call = TRUE;
2044                                         no_patch = TRUE;
2045                                 }
2046                         }
2047                 }
2048
2049                 if (cfg->method->dynamic)
2050                         /* These methods are allocated using malloc */
2051                         near_call = FALSE;
2052
2053                 if (cfg->compile_aot) {
2054                         near_call = TRUE;
2055                         no_patch = TRUE;
2056                 }
2057
2058 #ifdef MONO_ARCH_NOMAP32BIT
2059                 near_call = FALSE;
2060 #endif
2061
2062                 if (near_call) {
2063                         /*
2064                          * Align the call displacement to an address divisible by 4 so it does
2065                          * not span cache lines. This is required for code patching to work on SMP
2066                          * systems.
2067                          */
2068                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2069                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2070                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2071                         amd64_call_code (code, 0);
2072                 }
2073                 else {
2074                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2075                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2076                         amd64_call_reg (code, GP_SCRATCH_REG);
2077                 }
2078         }
2079
2080         return code;
2081 }
2082
2083 static inline guint8*
2084 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2085 {
2086 #ifdef PLATFORM_WIN32
2087         if (win64_adjust_stack)
2088                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2089 #endif
2090         code = emit_call_body (cfg, code, patch_type, data);
2091 #ifdef PLATFORM_WIN32
2092         if (win64_adjust_stack)
2093                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2094 #endif
2095
2096         return code;
2097 }
2098
2099 static inline int
2100 store_membase_imm_to_store_membase_reg (int opcode)
2101 {
2102         switch (opcode) {
2103         case OP_STORE_MEMBASE_IMM:
2104                 return OP_STORE_MEMBASE_REG;
2105         case OP_STOREI4_MEMBASE_IMM:
2106                 return OP_STOREI4_MEMBASE_REG;
2107         case OP_STOREI8_MEMBASE_IMM:
2108                 return OP_STOREI8_MEMBASE_REG;
2109         }
2110
2111         return -1;
2112 }
2113
2114 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2115
2116 /*
2117  * mono_arch_peephole_pass_1:
2118  *
2119  *   Perform peephole opts which should/can be performed before local regalloc
2120  */
2121 void
2122 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2123 {
2124         MonoInst *ins, *n;
2125
2126         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2127                 MonoInst *last_ins = ins->prev;
2128
2129                 switch (ins->opcode) {
2130                 case OP_ADD_IMM:
2131                 case OP_IADD_IMM:
2132                 case OP_LADD_IMM:
2133                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2134                                 /*
2135                                  * X86_LEA is like ADD, but doesn't have the
2136                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2137                                  * its operand to 64 bit.
2138                                  */
2139                                 ins->opcode = OP_X86_LEA_MEMBASE;
2140                                 ins->inst_basereg = ins->sreg1;
2141                         }
2142                         break;
2143                 case OP_LXOR:
2144                 case OP_IXOR:
2145                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2146                                 MonoInst *ins2;
2147
2148                                 /*
2149                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2150                                  * the latter has length 2-3 instead of 6 (reverse constant
2151                                  * propagation). These instruction sequences are very common
2152                                  * in the initlocals bblock.
2153                                  */
2154                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2155                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2156                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2157                                                 ins2->sreg1 = ins->dreg;
2158                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2159                                                 /* Continue */
2160                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2161                                                 NULLIFY_INS (ins2);
2162                                                 /* Continue */
2163                                         } else {
2164                                                 break;
2165                                         }
2166                                 }
2167                         }
2168                         break;
2169                 case OP_COMPARE_IMM:
2170                 case OP_LCOMPARE_IMM:
2171                         /* OP_COMPARE_IMM (reg, 0)
2172                          * -->
2173                          * OP_AMD64_TEST_NULL (reg)
2174                          */
2175                         if (!ins->inst_imm)
2176                                 ins->opcode = OP_AMD64_TEST_NULL;
2177                         break;
2178                 case OP_ICOMPARE_IMM:
2179                         if (!ins->inst_imm)
2180                                 ins->opcode = OP_X86_TEST_NULL;
2181                         break;
2182                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2183                         /*
2184                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2185                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2186                          * -->
2187                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2188                          * OP_COMPARE_IMM reg, imm
2189                          *
2190                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2191                          */
2192                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2193                             ins->inst_basereg == last_ins->inst_destbasereg &&
2194                             ins->inst_offset == last_ins->inst_offset) {
2195                                         ins->opcode = OP_ICOMPARE_IMM;
2196                                         ins->sreg1 = last_ins->sreg1;
2197
2198                                         /* check if we can remove cmp reg,0 with test null */
2199                                         if (!ins->inst_imm)
2200                                                 ins->opcode = OP_X86_TEST_NULL;
2201                                 }
2202
2203                         break;
2204                 }
2205
2206                 mono_peephole_ins (bb, ins);
2207         }
2208 }
2209
2210 void
2211 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2212 {
2213         MonoInst *ins, *n;
2214
2215         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2216                 switch (ins->opcode) {
2217                 case OP_ICONST:
2218                 case OP_I8CONST: {
2219                         /* reg = 0 -> XOR (reg, reg) */
2220                         /* XOR sets cflags on x86, so we cant do it always */
2221                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2222                                 ins->opcode = OP_LXOR;
2223                                 ins->sreg1 = ins->dreg;
2224                                 ins->sreg2 = ins->dreg;
2225                                 /* Fall through */
2226                         } else {
2227                                 break;
2228                         }
2229                 }
2230                 case OP_LXOR:
2231                         /*
2232                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2233                          * 0 result into 64 bits.
2234                          */
2235                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2236                                 ins->opcode = OP_IXOR;
2237                         }
2238                         /* Fall through */
2239                 case OP_IXOR:
2240                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2241                                 MonoInst *ins2;
2242
2243                                 /*
2244                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2245                                  * the latter has length 2-3 instead of 6 (reverse constant
2246                                  * propagation). These instruction sequences are very common
2247                                  * in the initlocals bblock.
2248                                  */
2249                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2250                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2251                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2252                                                 ins2->sreg1 = ins->dreg;
2253                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2254                                                 /* Continue */
2255                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2256                                                 NULLIFY_INS (ins2);
2257                                                 /* Continue */
2258                                         } else {
2259                                                 break;
2260                                         }
2261                                 }
2262                         }
2263                         break;
2264                 case OP_IADD_IMM:
2265                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2266                                 ins->opcode = OP_X86_INC_REG;
2267                         break;
2268                 case OP_ISUB_IMM:
2269                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2270                                 ins->opcode = OP_X86_DEC_REG;
2271                         break;
2272                 }
2273
2274                 mono_peephole_ins (bb, ins);
2275         }
2276 }
2277
2278 #define NEW_INS(cfg,ins,dest,op) do {   \
2279                 MONO_INST_NEW ((cfg), (dest), (op)); \
2280         (dest)->cil_code = (ins)->cil_code; \
2281         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2282         } while (0)
2283
2284 /*
2285  * mono_arch_lowering_pass:
2286  *
2287  *  Converts complex opcodes into simpler ones so that each IR instruction
2288  * corresponds to one machine instruction.
2289  */
2290 void
2291 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2292 {
2293         MonoInst *ins, *n, *temp;
2294
2295         /*
2296          * FIXME: Need to add more instructions, but the current machine
2297          * description can't model some parts of the composite instructions like
2298          * cdq.
2299          */
2300         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2301                 switch (ins->opcode) {
2302                 case OP_DIV_IMM:
2303                 case OP_REM_IMM:
2304                 case OP_IDIV_IMM:
2305                 case OP_IDIV_UN_IMM:
2306                 case OP_IREM_UN_IMM:
2307                         mono_decompose_op_imm (cfg, bb, ins);
2308                         break;
2309                 case OP_IREM_IMM:
2310                         /* Keep the opcode if we can implement it efficiently */
2311                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2312                                 mono_decompose_op_imm (cfg, bb, ins);
2313                         break;
2314                 case OP_COMPARE_IMM:
2315                 case OP_LCOMPARE_IMM:
2316                         if (!amd64_is_imm32 (ins->inst_imm)) {
2317                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2318                                 temp->inst_c0 = ins->inst_imm;
2319                                 temp->dreg = mono_alloc_ireg (cfg);
2320                                 ins->opcode = OP_COMPARE;
2321                                 ins->sreg2 = temp->dreg;
2322                         }
2323                         break;
2324                 case OP_LOAD_MEMBASE:
2325                 case OP_LOADI8_MEMBASE:
2326                         if (!amd64_is_imm32 (ins->inst_offset)) {
2327                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2328                                 temp->inst_c0 = ins->inst_offset;
2329                                 temp->dreg = mono_alloc_ireg (cfg);
2330                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2331                                 ins->inst_indexreg = temp->dreg;
2332                         }
2333                         break;
2334                 case OP_STORE_MEMBASE_IMM:
2335                 case OP_STOREI8_MEMBASE_IMM:
2336                         if (!amd64_is_imm32 (ins->inst_imm)) {
2337                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2338                                 temp->inst_c0 = ins->inst_imm;
2339                                 temp->dreg = mono_alloc_ireg (cfg);
2340                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2341                                 ins->sreg1 = temp->dreg;
2342                         }
2343                         break;
2344                 default:
2345                         break;
2346                 }
2347         }
2348
2349         bb->max_vreg = cfg->next_vreg;
2350 }
2351
2352 static const int
2353 branch_cc_table [] = {
2354         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2355         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2356         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2357 };
2358
2359 /* Maps CMP_... constants to X86_CC_... constants */
2360 static const int
2361 cc_table [] = {
2362         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2363         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2364 };
2365
2366 static const int
2367 cc_signed_table [] = {
2368         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2369         FALSE, FALSE, FALSE, FALSE
2370 };
2371
2372 /*#include "cprop.c"*/
2373
2374 static unsigned char*
2375 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2376 {
2377         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2378
2379         if (size == 1)
2380                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2381         else if (size == 2)
2382                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2383         return code;
2384 }
2385
2386 static unsigned char*
2387 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2388 {
2389         int sreg = tree->sreg1;
2390         int need_touch = FALSE;
2391
2392 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2393         if (!tree->flags & MONO_INST_INIT)
2394                 need_touch = TRUE;
2395 #endif
2396
2397         if (need_touch) {
2398                 guint8* br[5];
2399
2400                 /*
2401                  * Under Windows:
2402                  * If requested stack size is larger than one page,
2403                  * perform stack-touch operation
2404                  */
2405                 /*
2406                  * Generate stack probe code.
2407                  * Under Windows, it is necessary to allocate one page at a time,
2408                  * "touching" stack after each successful sub-allocation. This is
2409                  * because of the way stack growth is implemented - there is a
2410                  * guard page before the lowest stack page that is currently commited.
2411                  * Stack normally grows sequentially so OS traps access to the
2412                  * guard page and commits more pages when needed.
2413                  */
2414                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2415                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2416
2417                 br[2] = code; /* loop */
2418                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2419                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2420                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2421                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2422                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2423                 amd64_patch (br[3], br[2]);
2424                 amd64_test_reg_reg (code, sreg, sreg);
2425                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2426                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2427
2428                 br[1] = code; x86_jump8 (code, 0);
2429
2430                 amd64_patch (br[0], code);
2431                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2432                 amd64_patch (br[1], code);
2433                 amd64_patch (br[4], code);
2434         }
2435         else
2436                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2437
2438         if (tree->flags & MONO_INST_INIT) {
2439                 int offset = 0;
2440                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2441                         amd64_push_reg (code, AMD64_RAX);
2442                         offset += 8;
2443                 }
2444                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2445                         amd64_push_reg (code, AMD64_RCX);
2446                         offset += 8;
2447                 }
2448                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2449                         amd64_push_reg (code, AMD64_RDI);
2450                         offset += 8;
2451                 }
2452
2453                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2454                 if (sreg != AMD64_RCX)
2455                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2456                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2457
2458                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2459                 amd64_cld (code);
2460                 amd64_prefix (code, X86_REP_PREFIX);
2461                 amd64_stosl (code);
2462
2463                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2464                         amd64_pop_reg (code, AMD64_RDI);
2465                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2466                         amd64_pop_reg (code, AMD64_RCX);
2467                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2468                         amd64_pop_reg (code, AMD64_RAX);
2469         }
2470         return code;
2471 }
2472
2473 static guint8*
2474 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2475 {
2476         CallInfo *cinfo;
2477         guint32 quad;
2478
2479         /* Move return value to the target register */
2480         /* FIXME: do this in the local reg allocator */
2481         switch (ins->opcode) {
2482         case OP_CALL:
2483         case OP_CALL_REG:
2484         case OP_CALL_MEMBASE:
2485         case OP_LCALL:
2486         case OP_LCALL_REG:
2487         case OP_LCALL_MEMBASE:
2488                 g_assert (ins->dreg == AMD64_RAX);
2489                 break;
2490         case OP_FCALL:
2491         case OP_FCALL_REG:
2492         case OP_FCALL_MEMBASE:
2493                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2494                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2495                 }
2496                 else {
2497                         if (ins->dreg != AMD64_XMM0)
2498                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2499                 }
2500                 break;
2501         case OP_VCALL:
2502         case OP_VCALL_REG:
2503         case OP_VCALL_MEMBASE:
2504         case OP_VCALL2:
2505         case OP_VCALL2_REG:
2506         case OP_VCALL2_MEMBASE:
2507                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2508                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2509                         MonoInst *loc = cfg->arch.vret_addr_loc;
2510
2511                         /* Load the destination address */
2512                         g_assert (loc->opcode == OP_REGOFFSET);
2513                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2514
2515                         for (quad = 0; quad < 2; quad ++) {
2516                                 switch (cinfo->ret.pair_storage [quad]) {
2517                                 case ArgInIReg:
2518                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2519                                         break;
2520                                 case ArgInFloatSSEReg:
2521                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2522                                         break;
2523                                 case ArgInDoubleSSEReg:
2524                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2525                                         break;
2526                                 case ArgNone:
2527                                         break;
2528                                 default:
2529                                         NOT_IMPLEMENTED;
2530                                 }
2531                         }
2532                 }
2533                 break;
2534         }
2535
2536         return code;
2537 }
2538
2539 /*
2540  * mono_amd64_emit_tls_get:
2541  * @code: buffer to store code to
2542  * @dreg: hard register where to place the result
2543  * @tls_offset: offset info
2544  *
2545  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2546  * the dreg register the item in the thread local storage identified
2547  * by tls_offset.
2548  *
2549  * Returns: a pointer to the end of the stored code
2550  */
2551 guint8*
2552 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2553 {
2554 #ifdef PLATFORM_WIN32
2555         g_assert (tls_offset < 64);
2556         x86_prefix (code, X86_GS_PREFIX);
2557         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2558 #else
2559         if (optimize_for_xen) {
2560                 x86_prefix (code, X86_FS_PREFIX);
2561                 amd64_mov_reg_mem (code, dreg, 0, 8);
2562                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2563         } else {
2564                 x86_prefix (code, X86_FS_PREFIX);
2565                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2566         }
2567 #endif
2568         return code;
2569 }
2570
2571 #define REAL_PRINT_REG(text,reg) \
2572 mono_assert (reg >= 0); \
2573 amd64_push_reg (code, AMD64_RAX); \
2574 amd64_push_reg (code, AMD64_RDX); \
2575 amd64_push_reg (code, AMD64_RCX); \
2576 amd64_push_reg (code, reg); \
2577 amd64_push_imm (code, reg); \
2578 amd64_push_imm (code, text " %d %p\n"); \
2579 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2580 amd64_call_reg (code, AMD64_RAX); \
2581 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2582 amd64_pop_reg (code, AMD64_RCX); \
2583 amd64_pop_reg (code, AMD64_RDX); \
2584 amd64_pop_reg (code, AMD64_RAX);
2585
2586 /* benchmark and set based on cpu */
2587 #define LOOP_ALIGNMENT 8
2588 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2589
2590 #ifndef DISABLE_JIT
2591
2592 void
2593 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2594 {
2595         MonoInst *ins;
2596         MonoCallInst *call;
2597         guint offset;
2598         guint8 *code = cfg->native_code + cfg->code_len;
2599         MonoInst *last_ins = NULL;
2600         guint last_offset = 0;
2601         int max_len, cpos;
2602
2603         if (cfg->opt & MONO_OPT_LOOP) {
2604                 int pad, align = LOOP_ALIGNMENT;
2605                 /* set alignment depending on cpu */
2606                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2607                         pad = align - pad;
2608                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2609                         amd64_padding (code, pad);
2610                         cfg->code_len += pad;
2611                         bb->native_offset = cfg->code_len;
2612                 }
2613         }
2614
2615         if (cfg->verbose_level > 2)
2616                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2617
2618         cpos = bb->max_offset;
2619
2620         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2621                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2622                 g_assert (!cfg->compile_aot);
2623                 cpos += 6;
2624
2625                 cov->data [bb->dfn].cil_code = bb->cil_code;
2626                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2627                 /* this is not thread save, but good enough */
2628                 amd64_inc_membase (code, AMD64_R11, 0);
2629         }
2630
2631         offset = code - cfg->native_code;
2632
2633         mono_debug_open_block (cfg, bb, offset);
2634
2635     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2636                 x86_breakpoint (code);
2637
2638         MONO_BB_FOR_EACH_INS (bb, ins) {
2639                 offset = code - cfg->native_code;
2640
2641                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2642
2643                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2644                         cfg->code_size *= 2;
2645                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2646                         code = cfg->native_code + offset;
2647                         mono_jit_stats.code_reallocs++;
2648                 }
2649
2650                 if (cfg->debug_info)
2651                         mono_debug_record_line_number (cfg, ins, offset);
2652
2653                 switch (ins->opcode) {
2654                 case OP_BIGMUL:
2655                         amd64_mul_reg (code, ins->sreg2, TRUE);
2656                         break;
2657                 case OP_BIGMUL_UN:
2658                         amd64_mul_reg (code, ins->sreg2, FALSE);
2659                         break;
2660                 case OP_X86_SETEQ_MEMBASE:
2661                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2662                         break;
2663                 case OP_STOREI1_MEMBASE_IMM:
2664                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2665                         break;
2666                 case OP_STOREI2_MEMBASE_IMM:
2667                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2668                         break;
2669                 case OP_STOREI4_MEMBASE_IMM:
2670                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2671                         break;
2672                 case OP_STOREI1_MEMBASE_REG:
2673                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2674                         break;
2675                 case OP_STOREI2_MEMBASE_REG:
2676                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2677                         break;
2678                 case OP_STORE_MEMBASE_REG:
2679                 case OP_STOREI8_MEMBASE_REG:
2680                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2681                         break;
2682                 case OP_STOREI4_MEMBASE_REG:
2683                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2684                         break;
2685                 case OP_STORE_MEMBASE_IMM:
2686                 case OP_STOREI8_MEMBASE_IMM:
2687                         g_assert (amd64_is_imm32 (ins->inst_imm));
2688                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2689                         break;
2690                 case OP_LOAD_MEM:
2691                 case OP_LOADI8_MEM:
2692                         // FIXME: Decompose this earlier
2693                         if (amd64_is_imm32 (ins->inst_imm))
2694                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2695                         else {
2696                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2697                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2698                         }
2699                         break;
2700                 case OP_LOADI4_MEM:
2701                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2702                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2703                         break;
2704                 case OP_LOADU4_MEM:
2705                         // FIXME: Decompose this earlier
2706                         if (amd64_is_imm32 (ins->inst_imm))
2707                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2708                         else {
2709                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2710                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2711                         }
2712                         break;
2713                 case OP_LOADU1_MEM:
2714                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2715                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2716                         break;
2717                 case OP_LOADU2_MEM:
2718                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2719                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2720                         break;
2721                 case OP_LOAD_MEMBASE:
2722                 case OP_LOADI8_MEMBASE:
2723                         g_assert (amd64_is_imm32 (ins->inst_offset));
2724                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2725                         break;
2726                 case OP_LOADI4_MEMBASE:
2727                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2728                         break;
2729                 case OP_LOADU4_MEMBASE:
2730                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2731                         break;
2732                 case OP_LOADU1_MEMBASE:
2733                         /* The cpu zero extends the result into 64 bits */
2734                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2735                         break;
2736                 case OP_LOADI1_MEMBASE:
2737                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2738                         break;
2739                 case OP_LOADU2_MEMBASE:
2740                         /* The cpu zero extends the result into 64 bits */
2741                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2742                         break;
2743                 case OP_LOADI2_MEMBASE:
2744                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2745                         break;
2746                 case OP_AMD64_LOADI8_MEMINDEX:
2747                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2748                         break;
2749                 case OP_LCONV_TO_I1:
2750                 case OP_ICONV_TO_I1:
2751                 case OP_SEXT_I1:
2752                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2753                         break;
2754                 case OP_LCONV_TO_I2:
2755                 case OP_ICONV_TO_I2:
2756                 case OP_SEXT_I2:
2757                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2758                         break;
2759                 case OP_LCONV_TO_U1:
2760                 case OP_ICONV_TO_U1:
2761                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2762                         break;
2763                 case OP_LCONV_TO_U2:
2764                 case OP_ICONV_TO_U2:
2765                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2766                         break;
2767                 case OP_ZEXT_I4:
2768                         /* Clean out the upper word */
2769                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2770                         break;
2771                 case OP_SEXT_I4:
2772                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2773                         break;
2774                 case OP_COMPARE:
2775                 case OP_LCOMPARE:
2776                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2777                         break;
2778                 case OP_COMPARE_IMM:
2779                 case OP_LCOMPARE_IMM:
2780                         g_assert (amd64_is_imm32 (ins->inst_imm));
2781                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2782                         break;
2783                 case OP_X86_COMPARE_REG_MEMBASE:
2784                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2785                         break;
2786                 case OP_X86_TEST_NULL:
2787                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2788                         break;
2789                 case OP_AMD64_TEST_NULL:
2790                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2791                         break;
2792
2793                 case OP_X86_ADD_REG_MEMBASE:
2794                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2795                         break;
2796                 case OP_X86_SUB_REG_MEMBASE:
2797                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2798                         break;
2799                 case OP_X86_AND_REG_MEMBASE:
2800                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2801                         break;
2802                 case OP_X86_OR_REG_MEMBASE:
2803                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2804                         break;
2805                 case OP_X86_XOR_REG_MEMBASE:
2806                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2807                         break;
2808
2809                 case OP_X86_ADD_MEMBASE_IMM:
2810                         /* FIXME: Make a 64 version too */
2811                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2812                         break;
2813                 case OP_X86_SUB_MEMBASE_IMM:
2814                         g_assert (amd64_is_imm32 (ins->inst_imm));
2815                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2816                         break;
2817                 case OP_X86_AND_MEMBASE_IMM:
2818                         g_assert (amd64_is_imm32 (ins->inst_imm));
2819                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2820                         break;
2821                 case OP_X86_OR_MEMBASE_IMM:
2822                         g_assert (amd64_is_imm32 (ins->inst_imm));
2823                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2824                         break;
2825                 case OP_X86_XOR_MEMBASE_IMM:
2826                         g_assert (amd64_is_imm32 (ins->inst_imm));
2827                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2828                         break;
2829                 case OP_X86_ADD_MEMBASE_REG:
2830                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2831                         break;
2832                 case OP_X86_SUB_MEMBASE_REG:
2833                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2834                         break;
2835                 case OP_X86_AND_MEMBASE_REG:
2836                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2837                         break;
2838                 case OP_X86_OR_MEMBASE_REG:
2839                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2840                         break;
2841                 case OP_X86_XOR_MEMBASE_REG:
2842                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2843                         break;
2844                 case OP_X86_INC_MEMBASE:
2845                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2846                         break;
2847                 case OP_X86_INC_REG:
2848                         amd64_inc_reg_size (code, ins->dreg, 4);
2849                         break;
2850                 case OP_X86_DEC_MEMBASE:
2851                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2852                         break;
2853                 case OP_X86_DEC_REG:
2854                         amd64_dec_reg_size (code, ins->dreg, 4);
2855                         break;
2856                 case OP_X86_MUL_REG_MEMBASE:
2857                 case OP_X86_MUL_MEMBASE_REG:
2858                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2859                         break;
2860                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2861                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2862                         break;
2863                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2864                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2865                         break;
2866                 case OP_AMD64_COMPARE_MEMBASE_REG:
2867                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2868                         break;
2869                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2870                         g_assert (amd64_is_imm32 (ins->inst_imm));
2871                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2872                         break;
2873                 case OP_X86_COMPARE_MEMBASE8_IMM:
2874                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2875                         break;
2876                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2877                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2878                         break;
2879                 case OP_AMD64_COMPARE_REG_MEMBASE:
2880                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2881                         break;
2882
2883                 case OP_AMD64_ADD_REG_MEMBASE:
2884                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2885                         break;
2886                 case OP_AMD64_SUB_REG_MEMBASE:
2887                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2888                         break;
2889                 case OP_AMD64_AND_REG_MEMBASE:
2890                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2891                         break;
2892                 case OP_AMD64_OR_REG_MEMBASE:
2893                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2894                         break;
2895                 case OP_AMD64_XOR_REG_MEMBASE:
2896                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2897                         break;
2898
2899                 case OP_AMD64_ADD_MEMBASE_REG:
2900                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2901                         break;
2902                 case OP_AMD64_SUB_MEMBASE_REG:
2903                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2904                         break;
2905                 case OP_AMD64_AND_MEMBASE_REG:
2906                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2907                         break;
2908                 case OP_AMD64_OR_MEMBASE_REG:
2909                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2910                         break;
2911                 case OP_AMD64_XOR_MEMBASE_REG:
2912                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2913                         break;
2914
2915                 case OP_AMD64_ADD_MEMBASE_IMM:
2916                         g_assert (amd64_is_imm32 (ins->inst_imm));
2917                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2918                         break;
2919                 case OP_AMD64_SUB_MEMBASE_IMM:
2920                         g_assert (amd64_is_imm32 (ins->inst_imm));
2921                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2922                         break;
2923                 case OP_AMD64_AND_MEMBASE_IMM:
2924                         g_assert (amd64_is_imm32 (ins->inst_imm));
2925                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2926                         break;
2927                 case OP_AMD64_OR_MEMBASE_IMM:
2928                         g_assert (amd64_is_imm32 (ins->inst_imm));
2929                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2930                         break;
2931                 case OP_AMD64_XOR_MEMBASE_IMM:
2932                         g_assert (amd64_is_imm32 (ins->inst_imm));
2933                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2934                         break;
2935
2936                 case OP_BREAK:
2937                         amd64_breakpoint (code);
2938                         break;
2939                 case OP_RELAXED_NOP:
2940                         x86_prefix (code, X86_REP_PREFIX);
2941                         x86_nop (code);
2942                         break;
2943                 case OP_HARD_NOP:
2944                         x86_nop (code);
2945                         break;
2946                 case OP_NOP:
2947                 case OP_DUMMY_USE:
2948                 case OP_DUMMY_STORE:
2949                 case OP_NOT_REACHED:
2950                 case OP_NOT_NULL:
2951                         break;
2952                 case OP_ADDCC:
2953                 case OP_LADD:
2954                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2955                         break;
2956                 case OP_ADC:
2957                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2958                         break;
2959                 case OP_ADD_IMM:
2960                 case OP_LADD_IMM:
2961                         g_assert (amd64_is_imm32 (ins->inst_imm));
2962                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2963                         break;
2964                 case OP_ADC_IMM:
2965                         g_assert (amd64_is_imm32 (ins->inst_imm));
2966                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2967                         break;
2968                 case OP_SUBCC:
2969                 case OP_LSUB:
2970                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2971                         break;
2972                 case OP_SBB:
2973                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2974                         break;
2975                 case OP_SUB_IMM:
2976                 case OP_LSUB_IMM:
2977                         g_assert (amd64_is_imm32 (ins->inst_imm));
2978                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2979                         break;
2980                 case OP_SBB_IMM:
2981                         g_assert (amd64_is_imm32 (ins->inst_imm));
2982                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2983                         break;
2984                 case OP_LAND:
2985                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2986                         break;
2987                 case OP_AND_IMM:
2988                 case OP_LAND_IMM:
2989                         g_assert (amd64_is_imm32 (ins->inst_imm));
2990                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2991                         break;
2992                 case OP_LMUL:
2993                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2994                         break;
2995                 case OP_MUL_IMM:
2996                 case OP_LMUL_IMM:
2997                 case OP_IMUL_IMM: {
2998                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2999
3000                         switch (ins->inst_imm) {
3001                         case 2:
3002                                 /* MOV r1, r2 */
3003                                 /* ADD r1, r1 */
3004                                 if (ins->dreg != ins->sreg1)
3005                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3006                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3007                                 break;
3008                         case 3:
3009                                 /* LEA r1, [r2 + r2*2] */
3010                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3011                                 break;
3012                         case 5:
3013                                 /* LEA r1, [r2 + r2*4] */
3014                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3015                                 break;
3016                         case 6:
3017                                 /* LEA r1, [r2 + r2*2] */
3018                                 /* ADD r1, r1          */
3019                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3020                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3021                                 break;
3022                         case 9:
3023                                 /* LEA r1, [r2 + r2*8] */
3024                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3025                                 break;
3026                         case 10:
3027                                 /* LEA r1, [r2 + r2*4] */
3028                                 /* ADD r1, r1          */
3029                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3030                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3031                                 break;
3032                         case 12:
3033                                 /* LEA r1, [r2 + r2*2] */
3034                                 /* SHL r1, 2           */
3035                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3036                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3037                                 break;
3038                         case 25:
3039                                 /* LEA r1, [r2 + r2*4] */
3040                                 /* LEA r1, [r1 + r1*4] */
3041                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3042                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3043                                 break;
3044                         case 100:
3045                                 /* LEA r1, [r2 + r2*4] */
3046                                 /* SHL r1, 2           */
3047                                 /* LEA r1, [r1 + r1*4] */
3048                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3049                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3050                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3051                                 break;
3052                         default:
3053                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3054                                 break;
3055                         }
3056                         break;
3057                 }
3058                 case OP_LDIV:
3059                 case OP_LREM:
3060                         /* Regalloc magic makes the div/rem cases the same */
3061                         if (ins->sreg2 == AMD64_RDX) {
3062                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3063                                 amd64_cdq (code);
3064                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3065                         } else {
3066                                 amd64_cdq (code);
3067                                 amd64_div_reg (code, ins->sreg2, TRUE);
3068                         }
3069                         break;
3070                 case OP_LDIV_UN:
3071                 case OP_LREM_UN:
3072                         if (ins->sreg2 == AMD64_RDX) {
3073                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3074                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3075                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3076                         } else {
3077                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3078                                 amd64_div_reg (code, ins->sreg2, FALSE);
3079                         }
3080                         break;
3081                 case OP_IDIV:
3082                 case OP_IREM:
3083                         if (ins->sreg2 == AMD64_RDX) {
3084                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3085                                 amd64_cdq_size (code, 4);
3086                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3087                         } else {
3088                                 amd64_cdq_size (code, 4);
3089                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3090                         }
3091                         break;
3092                 case OP_IDIV_UN:
3093                 case OP_IREM_UN:
3094                         if (ins->sreg2 == AMD64_RDX) {
3095                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3096                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3097                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3098                         } else {
3099                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3100                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3101                         }
3102                         break;
3103                 case OP_IREM_IMM: {
3104                         int power = mono_is_power_of_two (ins->inst_imm);
3105
3106                         g_assert (ins->sreg1 == X86_EAX);
3107                         g_assert (ins->dreg == X86_EAX);
3108                         g_assert (power >= 0);
3109
3110                         if (power == 0) {
3111                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3112                                 break;
3113                         }
3114
3115                         /* Based on gcc code */
3116
3117                         /* Add compensation for negative dividents */
3118                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3119                         if (power > 1)
3120                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3121                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3122                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3123                         /* Compute remainder */
3124                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3125                         /* Remove compensation */
3126                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3127                         break;
3128                 }
3129                 case OP_LMUL_OVF:
3130                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3131                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3132                         break;
3133                 case OP_LOR:
3134                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3135                         break;
3136                 case OP_OR_IMM:
3137                 case OP_LOR_IMM:
3138                         g_assert (amd64_is_imm32 (ins->inst_imm));
3139                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3140                         break;
3141                 case OP_LXOR:
3142                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3143                         break;
3144                 case OP_XOR_IMM:
3145                 case OP_LXOR_IMM:
3146                         g_assert (amd64_is_imm32 (ins->inst_imm));
3147                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3148                         break;
3149                 case OP_LSHL:
3150                         g_assert (ins->sreg2 == AMD64_RCX);
3151                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3152                         break;
3153                 case OP_LSHR:
3154                         g_assert (ins->sreg2 == AMD64_RCX);
3155                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3156                         break;
3157                 case OP_SHR_IMM:
3158                         g_assert (amd64_is_imm32 (ins->inst_imm));
3159                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3160                         break;
3161                 case OP_LSHR_IMM:
3162                         g_assert (amd64_is_imm32 (ins->inst_imm));
3163                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3164                         break;
3165                 case OP_SHR_UN_IMM:
3166                         g_assert (amd64_is_imm32 (ins->inst_imm));
3167                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3168                         break;
3169                 case OP_LSHR_UN_IMM:
3170                         g_assert (amd64_is_imm32 (ins->inst_imm));
3171                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3172                         break;
3173                 case OP_LSHR_UN:
3174                         g_assert (ins->sreg2 == AMD64_RCX);
3175                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3176                         break;
3177                 case OP_SHL_IMM:
3178                         g_assert (amd64_is_imm32 (ins->inst_imm));
3179                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3180                         break;
3181                 case OP_LSHL_IMM:
3182                         g_assert (amd64_is_imm32 (ins->inst_imm));
3183                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3184                         break;
3185
3186                 case OP_IADDCC:
3187                 case OP_IADD:
3188                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3189                         break;
3190                 case OP_IADC:
3191                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3192                         break;
3193                 case OP_IADD_IMM:
3194                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3195                         break;
3196                 case OP_IADC_IMM:
3197                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3198                         break;
3199                 case OP_ISUBCC:
3200                 case OP_ISUB:
3201                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3202                         break;
3203                 case OP_ISBB:
3204                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3205                         break;
3206                 case OP_ISUB_IMM:
3207                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3208                         break;
3209                 case OP_ISBB_IMM:
3210                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3211                         break;
3212                 case OP_IAND:
3213                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3214                         break;
3215                 case OP_IAND_IMM:
3216                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3217                         break;
3218                 case OP_IOR:
3219                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3220                         break;
3221                 case OP_IOR_IMM:
3222                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3223                         break;
3224                 case OP_IXOR:
3225                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3226                         break;
3227                 case OP_IXOR_IMM:
3228                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3229                         break;
3230                 case OP_INEG:
3231                         amd64_neg_reg_size (code, ins->sreg1, 4);
3232                         break;
3233                 case OP_INOT:
3234                         amd64_not_reg_size (code, ins->sreg1, 4);
3235                         break;
3236                 case OP_ISHL:
3237                         g_assert (ins->sreg2 == AMD64_RCX);
3238                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3239                         break;
3240                 case OP_ISHR:
3241                         g_assert (ins->sreg2 == AMD64_RCX);
3242                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3243                         break;
3244                 case OP_ISHR_IMM:
3245                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3246                         break;
3247                 case OP_ISHR_UN_IMM:
3248                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3249                         break;
3250                 case OP_ISHR_UN:
3251                         g_assert (ins->sreg2 == AMD64_RCX);
3252                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3253                         break;
3254                 case OP_ISHL_IMM:
3255                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3256                         break;
3257                 case OP_IMUL:
3258                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3259                         break;
3260                 case OP_IMUL_OVF:
3261                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3262                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3263                         break;
3264                 case OP_IMUL_OVF_UN:
3265                 case OP_LMUL_OVF_UN: {
3266                         /* the mul operation and the exception check should most likely be split */
3267                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3268                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3269                         /*g_assert (ins->sreg2 == X86_EAX);
3270                         g_assert (ins->dreg == X86_EAX);*/
3271                         if (ins->sreg2 == X86_EAX) {
3272                                 non_eax_reg = ins->sreg1;
3273                         } else if (ins->sreg1 == X86_EAX) {
3274                                 non_eax_reg = ins->sreg2;
3275                         } else {
3276                                 /* no need to save since we're going to store to it anyway */
3277                                 if (ins->dreg != X86_EAX) {
3278                                         saved_eax = TRUE;
3279                                         amd64_push_reg (code, X86_EAX);
3280                                 }
3281                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3282                                 non_eax_reg = ins->sreg2;
3283                         }
3284                         if (ins->dreg == X86_EDX) {
3285                                 if (!saved_eax) {
3286                                         saved_eax = TRUE;
3287                                         amd64_push_reg (code, X86_EAX);
3288                                 }
3289                         } else {
3290                                 saved_edx = TRUE;
3291                                 amd64_push_reg (code, X86_EDX);
3292                         }
3293                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3294                         /* save before the check since pop and mov don't change the flags */
3295                         if (ins->dreg != X86_EAX)
3296                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3297                         if (saved_edx)
3298                                 amd64_pop_reg (code, X86_EDX);
3299                         if (saved_eax)
3300                                 amd64_pop_reg (code, X86_EAX);
3301                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3302                         break;
3303                 }
3304                 case OP_ICOMPARE:
3305                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3306                         break;
3307                 case OP_ICOMPARE_IMM:
3308                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3309                         break;
3310                 case OP_IBEQ:
3311                 case OP_IBLT:
3312                 case OP_IBGT:
3313                 case OP_IBGE:
3314                 case OP_IBLE:
3315                 case OP_LBEQ:
3316                 case OP_LBLT:
3317                 case OP_LBGT:
3318                 case OP_LBGE:
3319                 case OP_LBLE:
3320                 case OP_IBNE_UN:
3321                 case OP_IBLT_UN:
3322                 case OP_IBGT_UN:
3323                 case OP_IBGE_UN:
3324                 case OP_IBLE_UN:
3325                 case OP_LBNE_UN:
3326                 case OP_LBLT_UN:
3327                 case OP_LBGT_UN:
3328                 case OP_LBGE_UN:
3329                 case OP_LBLE_UN:
3330                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3331                         break;
3332
3333                 case OP_CMOV_IEQ:
3334                 case OP_CMOV_IGE:
3335                 case OP_CMOV_IGT:
3336                 case OP_CMOV_ILE:
3337                 case OP_CMOV_ILT:
3338                 case OP_CMOV_INE_UN:
3339                 case OP_CMOV_IGE_UN:
3340                 case OP_CMOV_IGT_UN:
3341                 case OP_CMOV_ILE_UN:
3342                 case OP_CMOV_ILT_UN:
3343                 case OP_CMOV_LEQ:
3344                 case OP_CMOV_LGE:
3345                 case OP_CMOV_LGT:
3346                 case OP_CMOV_LLE:
3347                 case OP_CMOV_LLT:
3348                 case OP_CMOV_LNE_UN:
3349                 case OP_CMOV_LGE_UN:
3350                 case OP_CMOV_LGT_UN:
3351                 case OP_CMOV_LLE_UN:
3352                 case OP_CMOV_LLT_UN:
3353                         g_assert (ins->dreg == ins->sreg1);
3354                         /* This needs to operate on 64 bit values */
3355                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3356                         break;
3357
3358                 case OP_LNOT:
3359                         amd64_not_reg (code, ins->sreg1);
3360                         break;
3361                 case OP_LNEG:
3362                         amd64_neg_reg (code, ins->sreg1);
3363                         break;
3364
3365                 case OP_ICONST:
3366                 case OP_I8CONST:
3367                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3368                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3369                         else
3370                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3371                         break;
3372                 case OP_AOTCONST:
3373                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3374                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3375                         break;
3376                 case OP_JUMP_TABLE:
3377                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3378                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3379                         break;
3380                 case OP_MOVE:
3381                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3382                         break;
3383                 case OP_AMD64_SET_XMMREG_R4: {
3384                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3385                         break;
3386                 }
3387                 case OP_AMD64_SET_XMMREG_R8: {
3388                         if (ins->dreg != ins->sreg1)
3389                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3390                         break;
3391                 }
3392                 case OP_TAILCALL: {
3393                         /*
3394                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3395                          * Keep in sync with the code in emit_epilog.
3396                          */
3397                         int pos = 0, i;
3398
3399                         /* FIXME: no tracing support... */
3400                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3401                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3402
3403                         g_assert (!cfg->method->save_lmf);
3404
3405                         if (cfg->arch.omit_fp) {
3406                                 guint32 save_offset = 0;
3407                                 /* Pop callee-saved registers */
3408                                 for (i = 0; i < AMD64_NREG; ++i)
3409                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3410                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3411                                                 save_offset += 8;
3412                                         }
3413                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3414                         }
3415                         else {
3416                                 for (i = 0; i < AMD64_NREG; ++i)
3417                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3418                                                 pos -= sizeof (gpointer);
3419
3420                                 if (pos)
3421                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3422
3423                                 /* Pop registers in reverse order */
3424                                 for (i = AMD64_NREG - 1; i > 0; --i)
3425                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3426                                                 amd64_pop_reg (code, i);
3427                                         }
3428
3429                                 amd64_leave (code);
3430                         }
3431
3432                         offset = code - cfg->native_code;
3433                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3434                         if (cfg->compile_aot)
3435                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3436                         else
3437                                 amd64_set_reg_template (code, AMD64_R11);
3438                         amd64_jump_reg (code, AMD64_R11);
3439                         break;
3440                 }
3441                 case OP_CHECK_THIS:
3442                         /* ensure ins->sreg1 is not NULL */
3443                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3444                         break;
3445                 case OP_ARGLIST: {
3446                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3447                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3448                         break;
3449                 }
3450                 case OP_CALL:
3451                 case OP_FCALL:
3452                 case OP_LCALL:
3453                 case OP_VCALL:
3454                 case OP_VCALL2:
3455                 case OP_VOIDCALL:
3456                         call = (MonoCallInst*)ins;
3457                         /*
3458                          * The AMD64 ABI forces callers to know about varargs.
3459                          */
3460                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3461                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3462                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3463                                 /*
3464                                  * Since the unmanaged calling convention doesn't contain a
3465                                  * 'vararg' entry, we have to treat every pinvoke call as a
3466                                  * potential vararg call.
3467                                  */
3468                                 guint32 nregs, i;
3469                                 nregs = 0;
3470                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3471                                         if (call->used_fregs & (1 << i))
3472                                                 nregs ++;
3473                                 if (!nregs)
3474                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3475                                 else
3476                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3477                         }
3478
3479                         if (ins->flags & MONO_INST_HAS_METHOD)
3480                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3481                         else
3482                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3483                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3484                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3485                         code = emit_move_return_value (cfg, ins, code);
3486                         break;
3487                 case OP_FCALL_REG:
3488                 case OP_LCALL_REG:
3489                 case OP_VCALL_REG:
3490                 case OP_VCALL2_REG:
3491                 case OP_VOIDCALL_REG:
3492                 case OP_CALL_REG:
3493                         call = (MonoCallInst*)ins;
3494
3495                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3496                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3497                                 ins->sreg1 = AMD64_R11;
3498                         }
3499
3500                         /*
3501                          * The AMD64 ABI forces callers to know about varargs.
3502                          */
3503                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3504                                 if (ins->sreg1 == AMD64_RAX) {
3505                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3506                                         ins->sreg1 = AMD64_R11;
3507                                 }
3508                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3509                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3510                                 /*
3511                                  * Since the unmanaged calling convention doesn't contain a
3512                                  * 'vararg' entry, we have to treat every pinvoke call as a
3513                                  * potential vararg call.
3514                                  */
3515                                 guint32 nregs, i;
3516                                 nregs = 0;
3517                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3518                                         if (call->used_fregs & (1 << i))
3519                                                 nregs ++;
3520                                 if (ins->sreg1 == AMD64_RAX) {
3521                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3522                                         ins->sreg1 = AMD64_R11;
3523                                 }
3524                                 if (!nregs)
3525                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3526                                 else
3527                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3528                         }
3529
3530                         amd64_call_reg (code, ins->sreg1);
3531                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3532                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3533                         code = emit_move_return_value (cfg, ins, code);
3534                         break;
3535                 case OP_FCALL_MEMBASE:
3536                 case OP_LCALL_MEMBASE:
3537                 case OP_VCALL_MEMBASE:
3538                 case OP_VCALL2_MEMBASE:
3539                 case OP_VOIDCALL_MEMBASE:
3540                 case OP_CALL_MEMBASE:
3541                         call = (MonoCallInst*)ins;
3542
3543                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3544                                 /*
3545                                  * Can't use R11 because it is clobbered by the trampoline
3546                                  * code, and the reg value is needed by get_vcall_slot_addr.
3547                                  */
3548                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3549                                 ins->sreg1 = AMD64_RAX;
3550                         }
3551
3552                         /*
3553                          * Emit a few nops to simplify get_vcall_slot ().
3554                          */
3555                         amd64_nop (code);
3556                         amd64_nop (code);
3557                         amd64_nop (code);
3558
3559                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3560                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3561                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3562                         code = emit_move_return_value (cfg, ins, code);
3563                         break;
3564                 case OP_AMD64_SAVE_SP_TO_LMF:
3565                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3566                         break;
3567                 case OP_X86_PUSH:
3568                         amd64_push_reg (code, ins->sreg1);
3569                         break;
3570                 case OP_X86_PUSH_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_push_imm (code, ins->inst_imm);
3573                         break;
3574                 case OP_X86_PUSH_MEMBASE:
3575                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3576                         break;
3577                 case OP_X86_PUSH_OBJ: {
3578                         int size = ALIGN_TO (ins->inst_imm, 8);
3579                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3580                         amd64_push_reg (code, AMD64_RDI);
3581                         amd64_push_reg (code, AMD64_RSI);
3582                         amd64_push_reg (code, AMD64_RCX);
3583                         if (ins->inst_offset)
3584                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3585                         else
3586                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3587                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3588                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3589                         amd64_cld (code);
3590                         amd64_prefix (code, X86_REP_PREFIX);
3591                         amd64_movsd (code);
3592                         amd64_pop_reg (code, AMD64_RCX);
3593                         amd64_pop_reg (code, AMD64_RSI);
3594                         amd64_pop_reg (code, AMD64_RDI);
3595                         break;
3596                 }
3597                 case OP_X86_LEA:
3598                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3599                         break;
3600                 case OP_X86_LEA_MEMBASE:
3601                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3602                         break;
3603                 case OP_X86_XCHG:
3604                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3605                         break;
3606                 case OP_LOCALLOC:
3607                         /* keep alignment */
3608                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3609                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3610                         code = mono_emit_stack_alloc (code, ins);
3611                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3612                         break;
3613                 case OP_LOCALLOC_IMM: {
3614                         guint32 size = ins->inst_imm;
3615                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3616
3617                         if (ins->flags & MONO_INST_INIT) {
3618                                 if (size < 64) {
3619                                         int i;
3620
3621                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3622                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3623
3624                                         for (i = 0; i < size; i += 8)
3625                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3626                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3627                                 } else {
3628                                         amd64_mov_reg_imm (code, ins->dreg, size);
3629                                         ins->sreg1 = ins->dreg;
3630
3631                                         code = mono_emit_stack_alloc (code, ins);
3632                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3633                                 }
3634                         } else {
3635                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3636                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3637                         }
3638                         break;
3639                 }
3640                 case OP_THROW: {
3641                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3642                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3643                                              (gpointer)"mono_arch_throw_exception", FALSE);
3644                         break;
3645                 }
3646                 case OP_RETHROW: {
3647                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3648                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3649                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3650                         break;
3651                 }
3652                 case OP_CALL_HANDLER:
3653                         /* Align stack */
3654                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3655                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3656                         amd64_call_imm (code, 0);
3657                         /* Restore stack alignment */
3658                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3659                         break;
3660                 case OP_START_HANDLER: {
3661                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3662                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3663                         break;
3664                 }
3665                 case OP_ENDFINALLY: {
3666                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3667                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3668                         amd64_ret (code);
3669                         break;
3670                 }
3671                 case OP_ENDFILTER: {
3672                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3673                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3674                         /* The local allocator will put the result into RAX */
3675                         amd64_ret (code);
3676                         break;
3677                 }
3678
3679                 case OP_LABEL:
3680                         ins->inst_c0 = code - cfg->native_code;
3681                         break;
3682                 case OP_BR:
3683                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3684                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3685                         //break;
3686                         if (ins->flags & MONO_INST_BRLABEL) {
3687                                 if (ins->inst_i0->inst_c0) {
3688                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3689                                 } else {
3690                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3691                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3692                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3693                                                 x86_jump8 (code, 0);
3694                                         else
3695                                                 x86_jump32 (code, 0);
3696                                 }
3697                         } else {
3698                                 if (ins->inst_target_bb->native_offset) {
3699                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3700                                 } else {
3701                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3702                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3703                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3704                                                 x86_jump8 (code, 0);
3705                                         else
3706                                                 x86_jump32 (code, 0);
3707                                 }
3708                         }
3709                         break;
3710                 case OP_BR_REG:
3711                         amd64_jump_reg (code, ins->sreg1);
3712                         break;
3713                 case OP_CEQ:
3714                 case OP_LCEQ:
3715                 case OP_ICEQ:
3716                 case OP_CLT:
3717                 case OP_LCLT:
3718                 case OP_ICLT:
3719                 case OP_CGT:
3720                 case OP_ICGT:
3721                 case OP_LCGT:
3722                 case OP_CLT_UN:
3723                 case OP_LCLT_UN:
3724                 case OP_ICLT_UN:
3725                 case OP_CGT_UN:
3726                 case OP_LCGT_UN:
3727                 case OP_ICGT_UN:
3728                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3729                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3730                         break;
3731                 case OP_COND_EXC_EQ:
3732                 case OP_COND_EXC_NE_UN:
3733                 case OP_COND_EXC_LT:
3734                 case OP_COND_EXC_LT_UN:
3735                 case OP_COND_EXC_GT:
3736                 case OP_COND_EXC_GT_UN:
3737                 case OP_COND_EXC_GE:
3738                 case OP_COND_EXC_GE_UN:
3739                 case OP_COND_EXC_LE:
3740                 case OP_COND_EXC_LE_UN:
3741                 case OP_COND_EXC_IEQ:
3742                 case OP_COND_EXC_INE_UN:
3743                 case OP_COND_EXC_ILT:
3744                 case OP_COND_EXC_ILT_UN:
3745                 case OP_COND_EXC_IGT:
3746                 case OP_COND_EXC_IGT_UN:
3747                 case OP_COND_EXC_IGE:
3748                 case OP_COND_EXC_IGE_UN:
3749                 case OP_COND_EXC_ILE:
3750                 case OP_COND_EXC_ILE_UN:
3751                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3752                         break;
3753                 case OP_COND_EXC_OV:
3754                 case OP_COND_EXC_NO:
3755                 case OP_COND_EXC_C:
3756                 case OP_COND_EXC_NC:
3757                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3758                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3759                         break;
3760                 case OP_COND_EXC_IOV:
3761                 case OP_COND_EXC_INO:
3762                 case OP_COND_EXC_IC:
3763                 case OP_COND_EXC_INC:
3764                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3765                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3766                         break;
3767
3768                 /* floating point opcodes */
3769                 case OP_R8CONST: {
3770                         double d = *(double *)ins->inst_p0;
3771
3772                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3773                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3774                         }
3775                         else {
3776                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3777                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3778                         }
3779                         break;
3780                 }
3781                 case OP_R4CONST: {
3782                         float f = *(float *)ins->inst_p0;
3783
3784                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3785                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3786                         }
3787                         else {
3788                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3789                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3790                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3791                         }
3792                         break;
3793                 }
3794                 case OP_STORER8_MEMBASE_REG:
3795                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3796                         break;
3797                 case OP_LOADR8_SPILL_MEMBASE:
3798                         g_assert_not_reached ();
3799                         break;
3800                 case OP_LOADR8_MEMBASE:
3801                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3802                         break;
3803                 case OP_STORER4_MEMBASE_REG:
3804                         /* This requires a double->single conversion */
3805                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3806                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3807                         break;
3808                 case OP_LOADR4_MEMBASE:
3809                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3810                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3811                         break;
3812                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3813                 case OP_ICONV_TO_R8:
3814                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3815                         break;
3816                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3817                 case OP_LCONV_TO_R8:
3818                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3819                         break;
3820                 case OP_FCONV_TO_R4:
3821                         /* FIXME: nothing to do ?? */
3822                         break;
3823                 case OP_FCONV_TO_I1:
3824                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3825                         break;
3826                 case OP_FCONV_TO_U1:
3827                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3828                         break;
3829                 case OP_FCONV_TO_I2:
3830                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3831                         break;
3832                 case OP_FCONV_TO_U2:
3833                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3834                         break;
3835                 case OP_FCONV_TO_U4:
3836                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3837                         break;
3838                 case OP_FCONV_TO_I4:
3839                 case OP_FCONV_TO_I:
3840                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3841                         break;
3842                 case OP_FCONV_TO_I8:
3843                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3844                         break;
3845                 case OP_LCONV_TO_R_UN: {
3846                         guint8 *br [2];
3847
3848                         /* Based on gcc code */
3849                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3850                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3851
3852                         /* Positive case */
3853                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3854                         br [1] = code; x86_jump8 (code, 0);
3855                         amd64_patch (br [0], code);
3856
3857                         /* Negative case */
3858                         /* Save to the red zone */
3859                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3860                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3861                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3862                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3863                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3864                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3865                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3866                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3867                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3868                         /* Restore */
3869                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3870                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3871                         amd64_patch (br [1], code);
3872                         break;
3873                 }
3874                 case OP_LCONV_TO_OVF_U4:
3875                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3876                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3877                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3878                         break;
3879                 case OP_LCONV_TO_OVF_I4_UN:
3880                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3881                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3882                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3883                         break;
3884                 case OP_FMOVE:
3885                         if (ins->dreg != ins->sreg1)
3886                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3887                         break;
3888                 case OP_FADD:
3889                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3890                         break;
3891                 case OP_FSUB:
3892                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3893                         break;
3894                 case OP_FMUL:
3895                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3896                         break;
3897                 case OP_FDIV:
3898                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3899                         break;
3900                 case OP_FNEG: {
3901                         static double r8_0 = -0.0;
3902
3903                         g_assert (ins->sreg1 == ins->dreg);
3904
3905                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3906                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3907                         break;
3908                 }
3909                 case OP_SIN:
3910                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3911                         break;
3912                 case OP_COS:
3913                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3914                         break;
3915                 case OP_ABS: {
3916                         static guint64 d = 0x7fffffffffffffffUL;
3917
3918                         g_assert (ins->sreg1 == ins->dreg);
3919
3920                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3921                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3922                         break;
3923                 }
3924                 case OP_SQRT:
3925                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3926                         break;
3927                 case OP_IMIN:
3928                         g_assert (cfg->opt & MONO_OPT_CMOV);
3929                         g_assert (ins->dreg == ins->sreg1);
3930                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3931                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3932                         break;
3933                 case OP_IMIN_UN:
3934                         g_assert (cfg->opt & MONO_OPT_CMOV);
3935                         g_assert (ins->dreg == ins->sreg1);
3936                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3937                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3938                         break;
3939                 case OP_IMAX:
3940                         g_assert (cfg->opt & MONO_OPT_CMOV);
3941                         g_assert (ins->dreg == ins->sreg1);
3942                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3943                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3944                         break;
3945                 case OP_IMAX_UN:
3946                         g_assert (cfg->opt & MONO_OPT_CMOV);
3947                         g_assert (ins->dreg == ins->sreg1);
3948                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3949                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3950                         break;
3951                 case OP_LMIN:
3952                         g_assert (cfg->opt & MONO_OPT_CMOV);
3953                         g_assert (ins->dreg == ins->sreg1);
3954                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3955                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3956                         break;
3957                 case OP_LMIN_UN:
3958                         g_assert (cfg->opt & MONO_OPT_CMOV);
3959                         g_assert (ins->dreg == ins->sreg1);
3960                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3961                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3962                         break;
3963                 case OP_LMAX:
3964                         g_assert (cfg->opt & MONO_OPT_CMOV);
3965                         g_assert (ins->dreg == ins->sreg1);
3966                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3967                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3968                         break;
3969                 case OP_LMAX_UN:
3970                         g_assert (cfg->opt & MONO_OPT_CMOV);
3971                         g_assert (ins->dreg == ins->sreg1);
3972                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3973                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3974                         break;
3975                 case OP_X86_FPOP:
3976                         break;
3977                 case OP_FCOMPARE:
3978                         /*
3979                          * The two arguments are swapped because the fbranch instructions
3980                          * depend on this for the non-sse case to work.
3981                          */
3982                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3983                         break;
3984                 case OP_FCEQ: {
3985                         /* zeroing the register at the start results in
3986                          * shorter and faster code (we can also remove the widening op)
3987                          */
3988                         guchar *unordered_check;
3989                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3990                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3991                         unordered_check = code;
3992                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3993                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3994                         amd64_patch (unordered_check, code);
3995                         break;
3996                 }
3997                 case OP_FCLT:
3998                 case OP_FCLT_UN:
3999                         /* zeroing the register at the start results in
4000                          * shorter and faster code (we can also remove the widening op)
4001                          */
4002                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4003                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4004                         if (ins->opcode == OP_FCLT_UN) {
4005                                 guchar *unordered_check = code;
4006                                 guchar *jump_to_end;
4007                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4008                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4009                                 jump_to_end = code;
4010                                 x86_jump8 (code, 0);
4011                                 amd64_patch (unordered_check, code);
4012                                 amd64_inc_reg (code, ins->dreg);
4013                                 amd64_patch (jump_to_end, code);
4014                         } else {
4015                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4016                         }
4017                         break;
4018                 case OP_FCGT:
4019                 case OP_FCGT_UN: {
4020                         /* zeroing the register at the start results in
4021                          * shorter and faster code (we can also remove the widening op)
4022                          */
4023                         guchar *unordered_check;
4024                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4025                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4026                         if (ins->opcode == OP_FCGT) {
4027                                 unordered_check = code;
4028                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4029                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4030                                 amd64_patch (unordered_check, code);
4031                         } else {
4032                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4033                         }
4034                         break;
4035                 }
4036                 case OP_FCLT_MEMBASE:
4037                 case OP_FCGT_MEMBASE:
4038                 case OP_FCLT_UN_MEMBASE:
4039                 case OP_FCGT_UN_MEMBASE:
4040                 case OP_FCEQ_MEMBASE: {
4041                         guchar *unordered_check, *jump_to_end;
4042                         int x86_cond;
4043
4044                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4045                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4046
4047                         switch (ins->opcode) {
4048                         case OP_FCEQ_MEMBASE:
4049                                 x86_cond = X86_CC_EQ;
4050                                 break;
4051                         case OP_FCLT_MEMBASE:
4052                         case OP_FCLT_UN_MEMBASE:
4053                                 x86_cond = X86_CC_LT;
4054                                 break;
4055                         case OP_FCGT_MEMBASE:
4056                         case OP_FCGT_UN_MEMBASE:
4057                                 x86_cond = X86_CC_GT;
4058                                 break;
4059                         default:
4060                                 g_assert_not_reached ();
4061                         }
4062
4063                         unordered_check = code;
4064                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4065                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4066
4067                         switch (ins->opcode) {
4068                         case OP_FCEQ_MEMBASE:
4069                         case OP_FCLT_MEMBASE:
4070                         case OP_FCGT_MEMBASE:
4071                                 amd64_patch (unordered_check, code);
4072                                 break;
4073                         case OP_FCLT_UN_MEMBASE:
4074                         case OP_FCGT_UN_MEMBASE:
4075                                 jump_to_end = code;
4076                                 x86_jump8 (code, 0);
4077                                 amd64_patch (unordered_check, code);
4078                                 amd64_inc_reg (code, ins->dreg);
4079                                 amd64_patch (jump_to_end, code);
4080                                 break;
4081                         default:
4082                                 break;
4083                         }
4084                         break;
4085                 }
4086                 case OP_FBEQ: {
4087                         guchar *jump = code;
4088                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4089                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4090                         amd64_patch (jump, code);
4091                         break;
4092                 }
4093                 case OP_FBNE_UN:
4094                         /* Branch if C013 != 100 */
4095                         /* branch if !ZF or (PF|CF) */
4096                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4097                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4098                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4099                         break;
4100                 case OP_FBLT:
4101                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4102                         break;
4103                 case OP_FBLT_UN:
4104                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4105                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4106                         break;
4107                 case OP_FBGT:
4108                 case OP_FBGT_UN:
4109                         if (ins->opcode == OP_FBGT) {
4110                                 guchar *br1;
4111
4112                                 /* skip branch if C1=1 */
4113                                 br1 = code;
4114                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4115                                 /* branch if (C0 | C3) = 1 */
4116                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4117                                 amd64_patch (br1, code);
4118                                 break;
4119                         } else {
4120                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4121                         }
4122                         break;
4123                 case OP_FBGE: {
4124                         /* Branch if C013 == 100 or 001 */
4125                         guchar *br1;
4126
4127                         /* skip branch if C1=1 */
4128                         br1 = code;
4129                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4130                         /* branch if (C0 | C3) = 1 */
4131                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4132                         amd64_patch (br1, code);
4133                         break;
4134                 }
4135                 case OP_FBGE_UN:
4136                         /* Branch if C013 == 000 */
4137                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4138                         break;
4139                 case OP_FBLE: {
4140                         /* Branch if C013=000 or 100 */
4141                         guchar *br1;
4142
4143                         /* skip branch if C1=1 */
4144                         br1 = code;
4145                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4146                         /* branch if C0=0 */
4147                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4148                         amd64_patch (br1, code);
4149                         break;
4150                 }
4151                 case OP_FBLE_UN:
4152                         /* Branch if C013 != 001 */
4153                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4154                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4155                         break;
4156                 case OP_CKFINITE:
4157                         /* Transfer value to the fp stack */
4158                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4159                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4160                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4161
4162                         amd64_push_reg (code, AMD64_RAX);
4163                         amd64_fxam (code);
4164                         amd64_fnstsw (code);
4165                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4166                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4167                         amd64_pop_reg (code, AMD64_RAX);
4168                         amd64_fstp (code, 0);
4169                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4170                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4171                         break;
4172                 case OP_TLS_GET: {
4173                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4174                         break;
4175                 }
4176                 case OP_MEMORY_BARRIER: {
4177                         /* Not needed on amd64 */
4178                         break;
4179                 }
4180                 case OP_ATOMIC_ADD_I4:
4181                 case OP_ATOMIC_ADD_I8: {
4182                         int dreg = ins->dreg;
4183                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4184
4185                         if (dreg == ins->inst_basereg)
4186                                 dreg = AMD64_R11;
4187
4188                         if (dreg != ins->sreg2)
4189                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4190
4191                         x86_prefix (code, X86_LOCK_PREFIX);
4192                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4193
4194                         if (dreg != ins->dreg)
4195                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4196
4197                         break;
4198                 }
4199                 case OP_ATOMIC_ADD_NEW_I4:
4200                 case OP_ATOMIC_ADD_NEW_I8: {
4201                         int dreg = ins->dreg;
4202                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4203
4204                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4205                                 dreg = AMD64_R11;
4206
4207                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4208                         amd64_prefix (code, X86_LOCK_PREFIX);
4209                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4210                         /* dreg contains the old value, add with sreg2 value */
4211                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4212
4213                         if (ins->dreg != dreg)
4214                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4215
4216                         break;
4217                 }
4218                 case OP_ATOMIC_EXCHANGE_I4:
4219                 case OP_ATOMIC_EXCHANGE_I8: {
4220                         guchar *br[2];
4221                         int sreg2 = ins->sreg2;
4222                         int breg = ins->inst_basereg;
4223                         guint32 size;
4224                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4225
4226                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4227                                 size = 8;
4228                         else
4229                                 size = 4;
4230
4231                         /*
4232                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4233                          * an explanation of how this works.
4234                          */
4235
4236                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4237                          * hack to overcome limits in x86 reg allocator
4238                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4239                          */
4240                         g_assert (ins->dreg == AMD64_RAX);
4241
4242                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4243                                 /* Highly unlikely, but possible */
4244                                 need_push = TRUE;
4245
4246                         /* The pushes invalidate rsp */
4247                         if ((breg == AMD64_RAX) || need_push) {
4248                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4249                                 breg = AMD64_R11;
4250                         }
4251
4252                         /* We need the EAX reg for the comparand */
4253                         if (ins->sreg2 == AMD64_RAX) {
4254                                 if (breg != AMD64_R11) {
4255                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4256                                         sreg2 = AMD64_R11;
4257                                 } else {
4258                                         g_assert (need_push);
4259                                         amd64_push_reg (code, AMD64_RDX);
4260                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4261                                         sreg2 = AMD64_RDX;
4262                                         rdx_pushed = TRUE;
4263                                 }
4264                         }
4265
4266                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4267
4268                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4269                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4270                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4271                         amd64_patch (br [1], br [0]);
4272
4273                         if (rdx_pushed)
4274                                 amd64_pop_reg (code, AMD64_RDX);
4275
4276                         break;
4277                 }
4278                 case OP_ATOMIC_CAS_I4:
4279                 case OP_ATOMIC_CAS_I8: {
4280                         guint32 size;
4281
4282                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4283                                 size = 8;
4284                         else
4285                                 size = 4;
4286
4287                         /*
4288                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4289                          * an explanation of how this works.
4290                          */
4291                         g_assert (ins->sreg3 == AMD64_RAX);
4292                         g_assert (ins->sreg1 != AMD64_RAX);
4293                         g_assert (ins->sreg1 != ins->sreg2);
4294
4295                         amd64_prefix (code, X86_LOCK_PREFIX);
4296                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4297
4298                         if (ins->dreg != AMD64_RAX)
4299                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4300                         break;
4301                 }
4302                 case OP_LIVERANGE_START: {
4303                         if (cfg->verbose_level > 1)
4304                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4305                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4306                         break;
4307                 }
4308                 case OP_LIVERANGE_END: {
4309                         if (cfg->verbose_level > 1)
4310                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4311                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4312                         break;
4313                 }
4314                 default:
4315                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4316                         g_assert_not_reached ();
4317                 }
4318
4319                 if ((code - cfg->native_code - offset) > max_len) {
4320                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4321                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4322                         g_assert_not_reached ();
4323                 }
4324
4325                 cpos += max_len;
4326
4327                 last_ins = ins;
4328                 last_offset = offset;
4329         }
4330
4331         cfg->code_len = code - cfg->native_code;
4332 }
4333
4334 #endif /* DISABLE_JIT */
4335
4336 void
4337 mono_arch_register_lowlevel_calls (void)
4338 {
4339         /* The signature doesn't matter */
4340         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4341 }
4342
4343 void
4344 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4345 {
4346         MonoJumpInfo *patch_info;
4347         gboolean compile_aot = !run_cctors;
4348
4349         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4350                 unsigned char *ip = patch_info->ip.i + code;
4351                 unsigned char *target;
4352
4353                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4354
4355                 if (compile_aot) {
4356                         switch (patch_info->type) {
4357                         case MONO_PATCH_INFO_BB:
4358                         case MONO_PATCH_INFO_LABEL:
4359                                 break;
4360                         default:
4361                                 /* No need to patch these */
4362                                 continue;
4363                         }
4364                 }
4365
4366                 switch (patch_info->type) {
4367                 case MONO_PATCH_INFO_NONE:
4368                         continue;
4369                 case MONO_PATCH_INFO_METHOD_REL:
4370                 case MONO_PATCH_INFO_R8:
4371                 case MONO_PATCH_INFO_R4:
4372                         g_assert_not_reached ();
4373                         continue;
4374                 case MONO_PATCH_INFO_BB:
4375                         break;
4376                 default:
4377                         break;
4378                 }
4379
4380                 /*
4381                  * Debug code to help track down problems where the target of a near call is
4382                  * is not valid.
4383                  */
4384                 if (amd64_is_near_call (ip)) {
4385                         gint64 disp = (guint8*)target - (guint8*)ip;
4386
4387                         if (!amd64_is_imm32 (disp)) {
4388                                 printf ("TYPE: %d\n", patch_info->type);
4389                                 switch (patch_info->type) {
4390                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4391                                         printf ("V: %s\n", patch_info->data.name);
4392                                         break;
4393                                 case MONO_PATCH_INFO_METHOD_JUMP:
4394                                 case MONO_PATCH_INFO_METHOD:
4395                                         printf ("V: %s\n", patch_info->data.method->name);
4396                                         break;
4397                                 default:
4398                                         break;
4399                                 }
4400                         }
4401                 }
4402
4403                 amd64_patch (ip, (gpointer)target);
4404         }
4405 }
4406
4407 static int
4408 get_max_epilog_size (MonoCompile *cfg)
4409 {
4410         int max_epilog_size = 16;
4411
4412         if (cfg->method->save_lmf)
4413                 max_epilog_size += 256;
4414
4415         if (mono_jit_trace_calls != NULL)
4416                 max_epilog_size += 50;
4417
4418         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4419                 max_epilog_size += 50;
4420
4421         max_epilog_size += (AMD64_NREG * 2);
4422
4423         return max_epilog_size;
4424 }
4425
4426 /*
4427  * This macro is used for testing whenever the unwinder works correctly at every point
4428  * where an async exception can happen.
4429  */
4430 /* This will generate a SIGSEGV at the given point in the code */
4431 #define async_exc_point(code) do { \
4432     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4433          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4434              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4435          cfg->arch.async_point_count ++; \
4436     } \
4437 } while (0)
4438
4439 guint8 *
4440 mono_arch_emit_prolog (MonoCompile *cfg)
4441 {
4442         MonoMethod *method = cfg->method;
4443         MonoBasicBlock *bb;
4444         MonoMethodSignature *sig;
4445         MonoInst *ins;
4446         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4447         guint8 *code;
4448         CallInfo *cinfo;
4449         gint32 lmf_offset = cfg->arch.lmf_offset;
4450         gboolean args_clobbered = FALSE;
4451         gboolean trace = FALSE;
4452
4453         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4454
4455         code = cfg->native_code = g_malloc (cfg->code_size);
4456
4457         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4458                 trace = TRUE;
4459
4460         /* Amount of stack space allocated by register saving code */
4461         pos = 0;
4462
4463         /* Offset between RSP and the CFA */
4464         cfa_offset = 0;
4465
4466         /*
4467          * The prolog consists of the following parts:
4468          * FP present:
4469          * - push rbp, mov rbp, rsp
4470          * - save callee saved regs using pushes
4471          * - allocate frame
4472          * - save rgctx if needed
4473          * - save lmf if needed
4474          * FP not present:
4475          * - allocate frame
4476          * - save rgctx if needed
4477          * - save lmf if needed
4478          * - save callee saved regs using moves
4479          */
4480
4481         // CFA = sp + 8
4482         cfa_offset = 8;
4483         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4484         // IP saved at CFA - 8
4485         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4486         async_exc_point (code);
4487
4488         if (!cfg->arch.omit_fp) {
4489                 amd64_push_reg (code, AMD64_RBP);
4490                 cfa_offset += 8;
4491                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4492                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4493                 async_exc_point (code);
4494 #ifdef PLATFORM_WIN32
4495                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4496 #endif
4497
4498                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4499                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4500                 async_exc_point (code);
4501 #ifdef PLATFORM_WIN32
4502                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4503 #endif
4504         }
4505
4506         /* Save callee saved registers */
4507         if (!cfg->arch.omit_fp && !method->save_lmf) {
4508                 int offset = cfa_offset;
4509
4510                 for (i = 0; i < AMD64_NREG; ++i)
4511                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4512                                 amd64_push_reg (code, i);
4513                                 pos += sizeof (gpointer);
4514                                 offset += 8;
4515                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4516                                 async_exc_point (code);
4517                         }
4518         }
4519
4520         if (cfg->arch.omit_fp) {
4521                 /*
4522                  * On enter, the stack is misaligned by the the pushing of the return
4523                  * address. It is either made aligned by the pushing of %rbp, or by
4524                  * this.
4525                  */
4526                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4527                 if ((alloc_size % 16) == 0)
4528                         alloc_size += 8;
4529         } else {
4530                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4531
4532                 alloc_size -= pos;
4533         }
4534
4535         cfg->arch.stack_alloc_size = alloc_size;
4536
4537         /* Allocate stack frame */
4538         if (alloc_size) {
4539                 /* See mono_emit_stack_alloc */
4540 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4541                 guint32 remaining_size = alloc_size;
4542                 while (remaining_size >= 0x1000) {
4543                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4544                         if (cfg->arch.omit_fp) {
4545                                 cfa_offset += 0x1000;
4546                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4547                         }
4548                         async_exc_point (code);
4549 #ifdef PLATFORM_WIN32
4550                         if (cfg->arch.omit_fp)
4551                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4552 #endif
4553
4554                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4555                         remaining_size -= 0x1000;
4556                 }
4557                 if (remaining_size) {
4558                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4559                         if (cfg->arch.omit_fp) {
4560                                 cfa_offset += remaining_size;
4561                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4562                                 async_exc_point (code);
4563                         }
4564 #ifdef PLATFORM_WIN32
4565                         if (cfg->arch.omit_fp)
4566                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4567 #endif
4568                 }
4569 #else
4570                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4571                 if (cfg->arch.omit_fp) {
4572                         cfa_offset += alloc_size;
4573                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4574                         async_exc_point (code);
4575                 }
4576 #endif
4577         }
4578
4579         /* Stack alignment check */
4580 #if 0
4581         {
4582                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4583                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4584                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4585                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4586                 amd64_breakpoint (code);
4587         }
4588 #endif
4589
4590         /* Save LMF */
4591         if (method->save_lmf) {
4592                 /*
4593                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4594                  */
4595                 /* sp is saved right before calls */
4596                 /* Skip method (only needed for trampoline LMF frames) */
4597                 /* Save callee saved regs */
4598                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4599                         int offset;
4600
4601                         switch (i) {
4602                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4603                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4604                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4605                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4606                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4607                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4608 #ifdef PLATFORM_WIN32
4609                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4610                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4611 #endif
4612                         default:
4613                                 offset = -1;
4614                                 break;
4615                         }
4616
4617                         if (offset != -1) {
4618                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4619                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4620                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4621                         }
4622                 }
4623         }
4624
4625         /* Save callee saved registers */
4626         if (cfg->arch.omit_fp && !method->save_lmf) {
4627                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4628
4629                 /* Save caller saved registers after sp is adjusted */
4630                 /* The registers are saved at the bottom of the frame */
4631                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4632                 for (i = 0; i < AMD64_NREG; ++i)
4633                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4634                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4635                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4636                                 save_area_offset += 8;
4637                                 async_exc_point (code);
4638                         }
4639         }
4640
4641         /* store runtime generic context */
4642         if (cfg->rgctx_var) {
4643                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4644                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4645
4646                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4647         }
4648
4649         /* compute max_offset in order to use short forward jumps */
4650         max_offset = 0;
4651         max_epilog_size = get_max_epilog_size (cfg);
4652         if (cfg->opt & MONO_OPT_BRANCH) {
4653                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4654                         MonoInst *ins;
4655                         bb->max_offset = max_offset;
4656
4657                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4658                                 max_offset += 6;
4659                         /* max alignment for loops */
4660                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4661                                 max_offset += LOOP_ALIGNMENT;
4662
4663                         MONO_BB_FOR_EACH_INS (bb, ins) {
4664                                 if (ins->opcode == OP_LABEL)
4665                                         ins->inst_c1 = max_offset;
4666
4667                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4668                         }
4669
4670                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4671                                 /* The tracing code can be quite large */
4672                                 max_offset += max_epilog_size;
4673                 }
4674         }
4675
4676         sig = mono_method_signature (method);
4677         pos = 0;
4678
4679         cinfo = cfg->arch.cinfo;
4680
4681         if (sig->ret->type != MONO_TYPE_VOID) {
4682                 /* Save volatile arguments to the stack */
4683                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4684                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4685         }
4686
4687         /* Keep this in sync with emit_load_volatile_arguments */
4688         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4689                 ArgInfo *ainfo = cinfo->args + i;
4690                 gint32 stack_offset;
4691                 MonoType *arg_type;
4692
4693                 ins = cfg->args [i];
4694
4695                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4696                         /* Unused arguments */
4697                         continue;
4698
4699                 if (sig->hasthis && (i == 0))
4700                         arg_type = &mono_defaults.object_class->byval_arg;
4701                 else
4702                         arg_type = sig->params [i - sig->hasthis];
4703
4704                 stack_offset = ainfo->offset + ARGS_OFFSET;
4705
4706                 if (cfg->globalra) {
4707                         /* All the other moves are done by the register allocator */
4708                         switch (ainfo->storage) {
4709                         case ArgInFloatSSEReg:
4710                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4711                                 break;
4712                         case ArgValuetypeInReg:
4713                                 for (quad = 0; quad < 2; quad ++) {
4714                                         switch (ainfo->pair_storage [quad]) {
4715                                         case ArgInIReg:
4716                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4717                                                 break;
4718                                         case ArgInFloatSSEReg:
4719                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4720                                                 break;
4721                                         case ArgInDoubleSSEReg:
4722                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4723                                                 break;
4724                                         case ArgNone:
4725                                                 break;
4726                                         default:
4727                                                 g_assert_not_reached ();
4728                                         }
4729                                 }
4730                                 break;
4731                         default:
4732                                 break;
4733                         }
4734
4735                         continue;
4736                 }
4737
4738                 /* Save volatile arguments to the stack */
4739                 if (ins->opcode != OP_REGVAR) {
4740                         switch (ainfo->storage) {
4741                         case ArgInIReg: {
4742                                 guint32 size = 8;
4743
4744                                 /* FIXME: I1 etc */
4745                                 /*
4746                                 if (stack_offset & 0x1)
4747                                         size = 1;
4748                                 else if (stack_offset & 0x2)
4749                                         size = 2;
4750                                 else if (stack_offset & 0x4)
4751                                         size = 4;
4752                                 else
4753                                         size = 8;
4754                                 */
4755                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4756                                 break;
4757                         }
4758                         case ArgInFloatSSEReg:
4759                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4760                                 break;
4761                         case ArgInDoubleSSEReg:
4762                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4763                                 break;
4764                         case ArgValuetypeInReg:
4765                                 for (quad = 0; quad < 2; quad ++) {
4766                                         switch (ainfo->pair_storage [quad]) {
4767                                         case ArgInIReg:
4768                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4769                                                 break;
4770                                         case ArgInFloatSSEReg:
4771                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4772                                                 break;
4773                                         case ArgInDoubleSSEReg:
4774                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4775                                                 break;
4776                                         case ArgNone:
4777                                                 break;
4778                                         default:
4779                                                 g_assert_not_reached ();
4780                                         }
4781                                 }
4782                                 break;
4783                         case ArgValuetypeAddrInIReg:
4784                                 if (ainfo->pair_storage [0] == ArgInIReg)
4785                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4786                                 break;
4787                         default:
4788                                 break;
4789                         }
4790                 } else {
4791                         /* Argument allocated to (non-volatile) register */
4792                         switch (ainfo->storage) {
4793                         case ArgInIReg:
4794                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4795                                 break;
4796                         case ArgOnStack:
4797                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4798                                 break;
4799                         default:
4800                                 g_assert_not_reached ();
4801                         }
4802                 }
4803         }
4804
4805         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4806         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4807                 guint64 domain = (guint64)cfg->domain;
4808
4809                 args_clobbered = TRUE;
4810
4811                 /*
4812                  * The call might clobber argument registers, but they are already
4813                  * saved to the stack/global regs.
4814                  */
4815                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4816                         guint8 *buf, *no_domain_branch;
4817
4818                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4819                         if ((domain >> 32) == 0)
4820                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4821                         else
4822                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4823                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4824                         no_domain_branch = code;
4825                         x86_branch8 (code, X86_CC_NE, 0, 0);
4826                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4827                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4828                         buf = code;
4829                         x86_branch8 (code, X86_CC_NE, 0, 0);
4830                         amd64_patch (no_domain_branch, code);
4831                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4832                                           (gpointer)"mono_jit_thread_attach", TRUE);
4833                         amd64_patch (buf, code);
4834 #ifdef PLATFORM_WIN32
4835                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4836                         /* FIXME: Add a separate key for LMF to avoid this */
4837                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4838 #endif
4839                 } else {
4840                         g_assert (!cfg->compile_aot);
4841                         if ((domain >> 32) == 0)
4842                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4843                         else
4844                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4845                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4846                                           (gpointer)"mono_jit_thread_attach", TRUE);
4847                 }
4848         }
4849
4850         if (method->save_lmf) {
4851                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4852                         /*
4853                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4854                          * through the mono_lmf_addr TLS variable.
4855                          */
4856                         /* %rax = previous_lmf */
4857                         x86_prefix (code, X86_FS_PREFIX);
4858                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4859
4860                         /* Save previous_lmf */
4861                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4862                         /* Set new lmf */
4863                         if (lmf_offset == 0) {
4864                                 x86_prefix (code, X86_FS_PREFIX);
4865                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4866                         } else {
4867                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4868                                 x86_prefix (code, X86_FS_PREFIX);
4869                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4870                         }
4871                 } else {
4872                         if (lmf_addr_tls_offset != -1) {
4873                                 /* Load lmf quicky using the FS register */
4874                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4875 #ifdef PLATFORM_WIN32
4876                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4877                                 /* FIXME: Add a separate key for LMF to avoid this */
4878                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4879 #endif
4880                         }
4881                         else {
4882                                 /*
4883                                  * The call might clobber argument registers, but they are already
4884                                  * saved to the stack/global regs.
4885                                  */
4886                                 args_clobbered = TRUE;
4887                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4888                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4889                         }
4890
4891                         /* Save lmf_addr */
4892                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4893                         /* Save previous_lmf */
4894                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4895                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4896                         /* Set new lmf */
4897                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4898                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4899                 }
4900         }
4901
4902         if (trace) {
4903                 args_clobbered = TRUE;
4904                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4905         }
4906
4907         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4908                 args_clobbered = TRUE;
4909
4910         /*
4911          * Optimize the common case of the first bblock making a call with the same
4912          * arguments as the method. This works because the arguments are still in their
4913          * original argument registers.
4914          * FIXME: Generalize this
4915          */
4916         if (!args_clobbered) {
4917                 MonoBasicBlock *first_bb = cfg->bb_entry;
4918                 MonoInst *next;
4919
4920                 next = mono_bb_first_ins (first_bb);
4921                 if (!next && first_bb->next_bb) {
4922                         first_bb = first_bb->next_bb;
4923                         next = mono_bb_first_ins (first_bb);
4924                 }
4925
4926                 if (first_bb->in_count > 1)
4927                         next = NULL;
4928
4929                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4930                         ArgInfo *ainfo = cinfo->args + i;
4931                         gboolean match = FALSE;
4932
4933                         ins = cfg->args [i];
4934                         if (ins->opcode != OP_REGVAR) {
4935                                 switch (ainfo->storage) {
4936                                 case ArgInIReg: {
4937                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4938                                                 if (next->dreg == ainfo->reg) {
4939                                                         NULLIFY_INS (next);
4940                                                         match = TRUE;
4941                                                 } else {
4942                                                         next->opcode = OP_MOVE;
4943                                                         next->sreg1 = ainfo->reg;
4944                                                         /* Only continue if the instruction doesn't change argument regs */
4945                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4946                                                                 match = TRUE;
4947                                                 }
4948                                         }
4949                                         break;
4950                                 }
4951                                 default:
4952                                         break;
4953                                 }
4954                         } else {
4955                                 /* Argument allocated to (non-volatile) register */
4956                                 switch (ainfo->storage) {
4957                                 case ArgInIReg:
4958                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4959                                                 NULLIFY_INS (next);
4960                                                 match = TRUE;
4961                                         }
4962                                         break;
4963                                 default:
4964                                         break;
4965                                 }
4966                         }
4967
4968                         if (match) {
4969                                 next = next->next;
4970                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4971                                 if (!next)
4972                                         break;
4973                         }
4974                 }
4975         }
4976
4977         cfg->code_len = code - cfg->native_code;
4978
4979         g_assert (cfg->code_len < cfg->code_size);
4980
4981         return code;
4982 }
4983
4984 void
4985 mono_arch_emit_epilog (MonoCompile *cfg)
4986 {
4987         MonoMethod *method = cfg->method;
4988         int quad, pos, i;
4989         guint8 *code;
4990         int max_epilog_size;
4991         CallInfo *cinfo;
4992         gint32 lmf_offset = cfg->arch.lmf_offset;
4993
4994         max_epilog_size = get_max_epilog_size (cfg);
4995
4996         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4997                 cfg->code_size *= 2;
4998                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4999                 mono_jit_stats.code_reallocs++;
5000         }
5001
5002         code = cfg->native_code + cfg->code_len;
5003
5004         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5005                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5006
5007         /* the code restoring the registers must be kept in sync with OP_JMP */
5008         pos = 0;
5009
5010         if (method->save_lmf) {
5011                 /* check if we need to restore protection of the stack after a stack overflow */
5012                 if (mono_get_jit_tls_offset () != -1) {
5013                         guint8 *patch;
5014                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5015                         /* we load the value in a separate instruction: this mechanism may be
5016                          * used later as a safer way to do thread interruption
5017                          */
5018                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5019                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5020                         patch = code;
5021                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5022                         /* note that the call trampoline will preserve eax/edx */
5023                         x86_call_reg (code, X86_ECX);
5024                         x86_patch (patch, code);
5025                 } else {
5026                         /* FIXME: maybe save the jit tls in the prolog */
5027                 }
5028                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5029                         /*
5030                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5031                          * through the mono_lmf_addr TLS variable.
5032                          */
5033                         /* reg = previous_lmf */
5034                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5035                         x86_prefix (code, X86_FS_PREFIX);
5036                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5037                 } else {
5038                         /* Restore previous lmf */
5039                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5040                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5041                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5042                 }
5043
5044                 /* Restore caller saved regs */
5045                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5046                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5047                 }
5048                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5049                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5050                 }
5051                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5052                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5053                 }
5054                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5055                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5056                 }
5057                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5058                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5059                 }
5060                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5061                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5062                 }
5063 #ifdef PLATFORM_WIN32
5064                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5065                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5066                 }
5067                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5068                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5069                 }
5070 #endif
5071         } else {
5072
5073                 if (cfg->arch.omit_fp) {
5074                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5075
5076                         for (i = 0; i < AMD64_NREG; ++i)
5077                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5078                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5079                                         save_area_offset += 8;
5080                                 }
5081                 }
5082                 else {
5083                         for (i = 0; i < AMD64_NREG; ++i)
5084                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5085                                         pos -= sizeof (gpointer);
5086
5087                         if (pos) {
5088                                 if (pos == - sizeof (gpointer)) {
5089                                         /* Only one register, so avoid lea */
5090                                         for (i = AMD64_NREG - 1; i > 0; --i)
5091                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5092                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5093                                                 }
5094                                 }
5095                                 else {
5096                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5097
5098                                         /* Pop registers in reverse order */
5099                                         for (i = AMD64_NREG - 1; i > 0; --i)
5100                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5101                                                         amd64_pop_reg (code, i);
5102                                                 }
5103                                 }
5104                         }
5105                 }
5106         }
5107
5108         /* Load returned vtypes into registers if needed */
5109         cinfo = cfg->arch.cinfo;
5110         if (cinfo->ret.storage == ArgValuetypeInReg) {
5111                 ArgInfo *ainfo = &cinfo->ret;
5112                 MonoInst *inst = cfg->ret;
5113
5114                 for (quad = 0; quad < 2; quad ++) {
5115                         switch (ainfo->pair_storage [quad]) {
5116                         case ArgInIReg:
5117                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5118                                 break;
5119                         case ArgInFloatSSEReg:
5120                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5121                                 break;
5122                         case ArgInDoubleSSEReg:
5123                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5124                                 break;
5125                         case ArgNone:
5126                                 break;
5127                         default:
5128                                 g_assert_not_reached ();
5129                         }
5130                 }
5131         }
5132
5133         if (cfg->arch.omit_fp) {
5134                 if (cfg->arch.stack_alloc_size)
5135                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5136         } else {
5137                 amd64_leave (code);
5138         }
5139         async_exc_point (code);
5140         amd64_ret (code);
5141
5142         cfg->code_len = code - cfg->native_code;
5143
5144         g_assert (cfg->code_len < cfg->code_size);
5145 }
5146
5147 void
5148 mono_arch_emit_exceptions (MonoCompile *cfg)
5149 {
5150         MonoJumpInfo *patch_info;
5151         int nthrows, i;
5152         guint8 *code;
5153         MonoClass *exc_classes [16];
5154         guint8 *exc_throw_start [16], *exc_throw_end [16];
5155         guint32 code_size = 0;
5156
5157         /* Compute needed space */
5158         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5159                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5160                         code_size += 40;
5161                 if (patch_info->type == MONO_PATCH_INFO_R8)
5162                         code_size += 8 + 15; /* sizeof (double) + alignment */
5163                 if (patch_info->type == MONO_PATCH_INFO_R4)
5164                         code_size += 4 + 15; /* sizeof (float) + alignment */
5165         }
5166
5167         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5168                 cfg->code_size *= 2;
5169                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5170                 mono_jit_stats.code_reallocs++;
5171         }
5172
5173         code = cfg->native_code + cfg->code_len;
5174
5175         /* add code to raise exceptions */
5176         nthrows = 0;
5177         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5178                 switch (patch_info->type) {
5179                 case MONO_PATCH_INFO_EXC: {
5180                         MonoClass *exc_class;
5181                         guint8 *buf, *buf2;
5182                         guint32 throw_ip;
5183
5184                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5185
5186                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5187                         g_assert (exc_class);
5188                         throw_ip = patch_info->ip.i;
5189
5190                         //x86_breakpoint (code);
5191                         /* Find a throw sequence for the same exception class */
5192                         for (i = 0; i < nthrows; ++i)
5193                                 if (exc_classes [i] == exc_class)
5194                                         break;
5195                         if (i < nthrows) {
5196                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5197                                 x86_jump_code (code, exc_throw_start [i]);
5198                                 patch_info->type = MONO_PATCH_INFO_NONE;
5199                         }
5200                         else {
5201                                 buf = code;
5202                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5203                                 buf2 = code;
5204
5205                                 if (nthrows < 16) {
5206                                         exc_classes [nthrows] = exc_class;
5207                                         exc_throw_start [nthrows] = code;
5208                                 }
5209                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5210
5211                                 patch_info->type = MONO_PATCH_INFO_NONE;
5212
5213                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5214
5215                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5216                                 while (buf < buf2)
5217                                         x86_nop (buf);
5218
5219                                 if (nthrows < 16) {
5220                                         exc_throw_end [nthrows] = code;
5221                                         nthrows ++;
5222                                 }
5223                         }
5224                         break;
5225                 }
5226                 default:
5227                         /* do nothing */
5228                         break;
5229                 }
5230         }
5231
5232         /* Handle relocations with RIP relative addressing */
5233         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5234                 gboolean remove = FALSE;
5235
5236                 switch (patch_info->type) {
5237                 case MONO_PATCH_INFO_R8:
5238                 case MONO_PATCH_INFO_R4: {
5239                         guint8 *pos;
5240
5241                         /* The SSE opcodes require a 16 byte alignment */
5242                         code = (guint8*)ALIGN_TO (code, 16);
5243
5244                         pos = cfg->native_code + patch_info->ip.i;
5245
5246                         if (IS_REX (pos [1]))
5247                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5248                         else
5249                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5250
5251                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5252                                 *(double*)code = *(double*)patch_info->data.target;
5253                                 code += sizeof (double);
5254                         } else {
5255                                 *(float*)code = *(float*)patch_info->data.target;
5256                                 code += sizeof (float);
5257                         }
5258
5259                         remove = TRUE;
5260                         break;
5261                 }
5262                 default:
5263                         break;
5264                 }
5265
5266                 if (remove) {
5267                         if (patch_info == cfg->patch_info)
5268                                 cfg->patch_info = patch_info->next;
5269                         else {
5270                                 MonoJumpInfo *tmp;
5271
5272                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5273                                         ;
5274                                 tmp->next = patch_info->next;
5275                         }
5276                 }
5277         }
5278
5279         cfg->code_len = code - cfg->native_code;
5280
5281         g_assert (cfg->code_len < cfg->code_size);
5282
5283 }
5284
5285 void*
5286 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5287 {
5288         guchar *code = p;
5289         CallInfo *cinfo = NULL;
5290         MonoMethodSignature *sig;
5291         MonoInst *inst;
5292         int i, n, stack_area = 0;
5293
5294         /* Keep this in sync with mono_arch_get_argument_info */
5295
5296         if (enable_arguments) {
5297                 /* Allocate a new area on the stack and save arguments there */
5298                 sig = mono_method_signature (cfg->method);
5299
5300                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5301
5302                 n = sig->param_count + sig->hasthis;
5303
5304                 stack_area = ALIGN_TO (n * 8, 16);
5305
5306                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5307
5308                 for (i = 0; i < n; ++i) {
5309                         inst = cfg->args [i];
5310
5311                         if (inst->opcode == OP_REGVAR)
5312                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5313                         else {
5314                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5315                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5316                         }
5317                 }
5318         }
5319
5320         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5321         amd64_set_reg_template (code, AMD64_ARG_REG1);
5322         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5323         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5324
5325         if (enable_arguments)
5326                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5327
5328         return code;
5329 }
5330
5331 enum {
5332         SAVE_NONE,
5333         SAVE_STRUCT,
5334         SAVE_EAX,
5335         SAVE_EAX_EDX,
5336         SAVE_XMM
5337 };
5338
5339 void*
5340 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5341 {
5342         guchar *code = p;
5343         int save_mode = SAVE_NONE;
5344         MonoMethod *method = cfg->method;
5345         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5346
5347         switch (rtype) {
5348         case MONO_TYPE_VOID:
5349                 /* special case string .ctor icall */
5350                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5351                         save_mode = SAVE_EAX;
5352                 else
5353                         save_mode = SAVE_NONE;
5354                 break;
5355         case MONO_TYPE_I8:
5356         case MONO_TYPE_U8:
5357                 save_mode = SAVE_EAX;
5358                 break;
5359         case MONO_TYPE_R4:
5360         case MONO_TYPE_R8:
5361                 save_mode = SAVE_XMM;
5362                 break;
5363         case MONO_TYPE_GENERICINST:
5364                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5365                         save_mode = SAVE_EAX;
5366                         break;
5367                 }
5368                 /* Fall through */
5369         case MONO_TYPE_VALUETYPE:
5370                 save_mode = SAVE_STRUCT;
5371                 break;
5372         default:
5373                 save_mode = SAVE_EAX;
5374                 break;
5375         }
5376
5377         /* Save the result and copy it into the proper argument register */
5378         switch (save_mode) {
5379         case SAVE_EAX:
5380                 amd64_push_reg (code, AMD64_RAX);
5381                 /* Align stack */
5382                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5383                 if (enable_arguments)
5384                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5385                 break;
5386         case SAVE_STRUCT:
5387                 /* FIXME: */
5388                 if (enable_arguments)
5389                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5390                 break;
5391         case SAVE_XMM:
5392                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5393                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5394                 /* Align stack */
5395                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5396                 /*
5397                  * The result is already in the proper argument register so no copying
5398                  * needed.
5399                  */
5400                 break;
5401         case SAVE_NONE:
5402                 break;
5403         default:
5404                 g_assert_not_reached ();
5405         }
5406
5407         /* Set %al since this is a varargs call */
5408         if (save_mode == SAVE_XMM)
5409                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5410         else
5411                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5412
5413         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5414         amd64_set_reg_template (code, AMD64_ARG_REG1);
5415         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5416
5417         /* Restore result */
5418         switch (save_mode) {
5419         case SAVE_EAX:
5420                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5421                 amd64_pop_reg (code, AMD64_RAX);
5422                 break;
5423         case SAVE_STRUCT:
5424                 /* FIXME: */
5425                 break;
5426         case SAVE_XMM:
5427                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5428                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5429                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5430                 break;
5431         case SAVE_NONE:
5432                 break;
5433         default:
5434                 g_assert_not_reached ();
5435         }
5436
5437         return code;
5438 }
5439
5440 void
5441 mono_arch_flush_icache (guint8 *code, gint size)
5442 {
5443         /* Not needed */
5444 }
5445
5446 void
5447 mono_arch_flush_register_windows (void)
5448 {
5449 }
5450
5451 gboolean
5452 mono_arch_is_inst_imm (gint64 imm)
5453 {
5454         return amd64_is_imm32 (imm);
5455 }
5456
5457 /*
5458  * Determine whenever the trap whose info is in SIGINFO is caused by
5459  * integer overflow.
5460  */
5461 gboolean
5462 mono_arch_is_int_overflow (void *sigctx, void *info)
5463 {
5464         MonoContext ctx;
5465         guint8* rip;
5466         int reg;
5467         gint64 value;
5468
5469         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5470
5471         rip = (guint8*)ctx.rip;
5472
5473         if (IS_REX (rip [0])) {
5474                 reg = amd64_rex_b (rip [0]);
5475                 rip ++;
5476         }
5477         else
5478                 reg = 0;
5479
5480         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5481                 /* idiv REG */
5482                 reg += x86_modrm_rm (rip [1]);
5483
5484                 switch (reg) {
5485                 case AMD64_RAX:
5486                         value = ctx.rax;
5487                         break;
5488                 case AMD64_RBX:
5489                         value = ctx.rbx;
5490                         break;
5491                 case AMD64_RCX:
5492                         value = ctx.rcx;
5493                         break;
5494                 case AMD64_RDX:
5495                         value = ctx.rdx;
5496                         break;
5497                 case AMD64_RBP:
5498                         value = ctx.rbp;
5499                         break;
5500                 case AMD64_RSP:
5501                         value = ctx.rsp;
5502                         break;
5503                 case AMD64_RSI:
5504                         value = ctx.rsi;
5505                         break;
5506                 case AMD64_RDI:
5507                         value = ctx.rdi;
5508                         break;
5509                 case AMD64_R12:
5510                         value = ctx.r12;
5511                         break;
5512                 case AMD64_R13:
5513                         value = ctx.r13;
5514                         break;
5515                 case AMD64_R14:
5516                         value = ctx.r14;
5517                         break;
5518                 case AMD64_R15:
5519                         value = ctx.r15;
5520                         break;
5521                 default:
5522                         g_assert_not_reached ();
5523                         reg = -1;
5524                 }
5525
5526                 if (value == -1)
5527                         return TRUE;
5528         }
5529
5530         return FALSE;
5531 }
5532
5533 guint32
5534 mono_arch_get_patch_offset (guint8 *code)
5535 {
5536         return 3;
5537 }
5538
5539 /**
5540  * mono_breakpoint_clean_code:
5541  *
5542  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5543  * breakpoints in the original code, they are removed in the copy.
5544  *
5545  * Returns TRUE if no sw breakpoint was present.
5546  */
5547 gboolean
5548 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5549 {
5550         int i;
5551         gboolean can_write = TRUE;
5552         /*
5553          * If method_start is non-NULL we need to perform bound checks, since we access memory
5554          * at code - offset we could go before the start of the method and end up in a different
5555          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5556          * instead.
5557          */
5558         if (!method_start || code - offset >= method_start) {
5559                 memcpy (buf, code - offset, size);
5560         } else {
5561                 int diff = code - method_start;
5562                 memset (buf, 0, size);
5563                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5564         }
5565         code -= offset;
5566         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5567                 int idx = mono_breakpoint_info_index [i];
5568                 guint8 *ptr;
5569                 if (idx < 1)
5570                         continue;
5571                 ptr = mono_breakpoint_info [idx].address;
5572                 if (ptr >= code && ptr < code + size) {
5573                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5574                         can_write = FALSE;
5575                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5576                         buf [ptr - code] = saved_byte;
5577                 }
5578         }
5579         return can_write;
5580 }
5581
5582 gpointer
5583 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5584 {
5585         guint8 buf [10];
5586         guint32 reg;
5587         gint32 disp;
5588         guint8 rex = 0;
5589
5590         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5591         code = buf + 9;
5592
5593         *displacement = 0;
5594
5595         code -= 7;
5596
5597         /*
5598          * A given byte sequence can match more than case here, so we have to be
5599          * really careful about the ordering of the cases. Longer sequences
5600          * come first.
5601          * There are two types of calls:
5602          * - direct calls: 0xff address_byte 8/32 bits displacement
5603          * - indirect calls: nop nop nop <call>
5604          * The nops make sure we don't confuse the instruction preceeding an indirect
5605          * call with a direct call.
5606          */
5607         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5608                 /* call OFFSET(%rip) */
5609                 disp = *(guint32*)(code + 3);
5610                 return (gpointer*)(code + disp + 7);
5611         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
5612                 /* call *[reg+disp32] using indexed addressing */
5613                 /* The LLVM JIT emits this, and we emit it too for %r12 */
5614                 if (IS_REX (code [-1])) {
5615                         rex = code [-1];
5616                         g_assert (amd64_rex_x (rex) == 0);
5617                 }
5618                 reg = amd64_sib_base (code [2]);
5619                 disp = *(gint32*)(code + 3);
5620         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5621                 /* call *[reg+disp32] */
5622                 if (IS_REX (code [0]))
5623                         rex = code [0];
5624                 reg = amd64_modrm_rm (code [2]);
5625                 disp = *(gint32*)(code + 3);
5626                 /* R10 is clobbered by the IMT thunk code */
5627                 g_assert (reg != AMD64_R10);
5628         } else if (code [2] == 0xe8) {
5629                 /* call <ADDR> */
5630                 return NULL;
5631         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
5632                 /* call *[r12+disp8] using indexed addressing */
5633                 if (IS_REX (code [2]))
5634                         rex = code [2];
5635                 reg = amd64_sib_base (code [5]);
5636                 disp = *(gint8*)(code + 6);
5637         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5638                 /* call *%reg */
5639                 return NULL;
5640         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5641                 /* call *[reg+disp8] */
5642                 if (IS_REX (code [3]))
5643                         rex = code [3];
5644                 reg = amd64_modrm_rm (code [5]);
5645                 disp = *(gint8*)(code + 6);
5646                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5647         }
5648         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5649                 /* call *%reg */
5650                 if (IS_REX (code [4]))
5651                         rex = code [4];
5652                 reg = amd64_modrm_rm (code [6]);
5653                 disp = 0;
5654         }
5655         else
5656                 g_assert_not_reached ();
5657
5658         reg += amd64_rex_b (rex);
5659
5660         /* R11 is clobbered by the trampoline code */
5661         g_assert (reg != AMD64_R11);
5662
5663         *displacement = disp;
5664         return regs [reg];
5665 }
5666
5667 int
5668 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5669 {
5670         int this_reg = AMD64_ARG_REG1;
5671
5672         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5673                 CallInfo *cinfo;
5674
5675                 if (!gsctx && code)
5676                         gsctx = mono_get_generic_context_from_code (code);
5677
5678                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5679
5680                 if (cinfo->ret.storage != ArgValuetypeInReg)
5681                         this_reg = AMD64_ARG_REG2;
5682                 g_free (cinfo);
5683         }
5684
5685         return this_reg;
5686 }
5687
5688 gpointer
5689 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5690 {
5691         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5692 }
5693
5694 #define MAX_ARCH_DELEGATE_PARAMS 10
5695
5696 static gpointer
5697 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
5698 {
5699         guint8 *code, *start;
5700         int i;
5701
5702         if (has_target) {
5703                 start = code = mono_global_codeman_reserve (64);
5704
5705                 /* Replace the this argument with the target */
5706                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5707                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5708                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5709
5710                 g_assert ((code - start) < 64);
5711         } else {
5712                 start = code = mono_global_codeman_reserve (64);
5713
5714                 if (param_count == 0) {
5715                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5716                 } else {
5717                         /* We have to shift the arguments left */
5718                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5719                         for (i = 0; i < param_count; ++i) {
5720 #ifdef PLATFORM_WIN32
5721                                 if (i < 3)
5722                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5723                                 else
5724                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5725 #else
5726                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5727 #endif
5728                         }
5729
5730                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5731                 }
5732                 g_assert ((code - start) < 64);
5733         }
5734
5735         mono_debug_add_delegate_trampoline (start, code - start);
5736
5737         if (code_len)
5738                 *code_len = code - start;
5739
5740         return start;
5741 }
5742
5743 /*
5744  * mono_arch_get_delegate_invoke_impls:
5745  *
5746  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
5747  * trampolines.
5748  */
5749 GSList*
5750 mono_arch_get_delegate_invoke_impls (void)
5751 {
5752         GSList *res = NULL;
5753         guint8 *code;
5754         guint32 code_len;
5755         int i;
5756
5757         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
5758         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
5759
5760         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
5761                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
5762                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
5763         }
5764
5765         return res;
5766 }
5767
5768 gpointer
5769 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5770 {
5771         guint8 *code, *start;
5772         int i;
5773
5774         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5775                 return NULL;
5776
5777         /* FIXME: Support more cases */
5778         if (MONO_TYPE_ISSTRUCT (sig->ret))
5779                 return NULL;
5780
5781         if (has_target) {
5782                 static guint8* cached = NULL;
5783
5784                 if (cached)
5785                         return cached;
5786
5787                 if (mono_aot_only)
5788                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
5789                 else
5790                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
5791
5792                 mono_memory_barrier ();
5793
5794                 cached = start;
5795         } else {
5796                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5797                 for (i = 0; i < sig->param_count; ++i)
5798                         if (!mono_is_regsize_var (sig->params [i]))
5799                                 return NULL;
5800                 if (sig->param_count > 4)
5801                         return NULL;
5802
5803                 code = cache [sig->param_count];
5804                 if (code)
5805                         return code;
5806
5807                 if (mono_aot_only) {
5808                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5809                         start = mono_aot_get_named_code (name);
5810                         g_free (name);
5811                 } else {
5812                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
5813                 }
5814
5815                 mono_memory_barrier ();
5816
5817                 cache [sig->param_count] = start;
5818         }
5819
5820         return start;
5821 }
5822
5823 /*
5824  * Support for fast access to the thread-local lmf structure using the GS
5825  * segment register on NPTL + kernel 2.6.x.
5826  */
5827
5828 static gboolean tls_offset_inited = FALSE;
5829
5830 void
5831 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5832 {
5833         if (!tls_offset_inited) {
5834 #ifdef PLATFORM_WIN32
5835                 /*
5836                  * We need to init this multiple times, since when we are first called, the key might not
5837                  * be initialized yet.
5838                  */
5839                 appdomain_tls_offset = mono_domain_get_tls_key ();
5840                 lmf_tls_offset = mono_get_jit_tls_key ();
5841                 thread_tls_offset = mono_thread_get_tls_key ();
5842                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5843
5844                 /* Only 64 tls entries can be accessed using inline code */
5845                 if (appdomain_tls_offset >= 64)
5846                         appdomain_tls_offset = -1;
5847                 if (lmf_tls_offset >= 64)
5848                         lmf_tls_offset = -1;
5849                 if (thread_tls_offset >= 64)
5850                         thread_tls_offset = -1;
5851 #else
5852                 tls_offset_inited = TRUE;
5853 #ifdef MONO_XEN_OPT
5854                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5855 #endif
5856                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5857                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5858                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5859                 thread_tls_offset = mono_thread_get_tls_offset ();
5860 #endif
5861         }
5862 }
5863
5864 void
5865 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5866 {
5867 }
5868
5869 #ifdef MONO_ARCH_HAVE_IMT
5870
5871 #define CMP_SIZE (6 + 1)
5872 #define CMP_REG_REG_SIZE (4 + 1)
5873 #define BR_SMALL_SIZE 2
5874 #define BR_LARGE_SIZE 6
5875 #define MOV_REG_IMM_SIZE 10
5876 #define MOV_REG_IMM_32BIT_SIZE 6
5877 #define JUMP_REG_SIZE (2 + 1)
5878
5879 static int
5880 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5881 {
5882         int i, distance = 0;
5883         for (i = start; i < target; ++i)
5884                 distance += imt_entries [i]->chunk_size;
5885         return distance;
5886 }
5887
5888 /*
5889  * LOCKING: called with the domain lock held
5890  */
5891 gpointer
5892 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5893         gpointer fail_tramp)
5894 {
5895         int i;
5896         int size = 0;
5897         guint8 *code, *start;
5898         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5899
5900         for (i = 0; i < count; ++i) {
5901                 MonoIMTCheckItem *item = imt_entries [i];
5902                 if (item->is_equals) {
5903                         if (item->check_target_idx) {
5904                                 if (!item->compare_done) {
5905                                         if (amd64_is_imm32 (item->key))
5906                                                 item->chunk_size += CMP_SIZE;
5907                                         else
5908                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5909                                 }
5910                                 if (item->has_target_code) {
5911                                         item->chunk_size += MOV_REG_IMM_SIZE;
5912                                 } else {
5913                                         if (vtable_is_32bit)
5914                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5915                                         else
5916                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5917                                 }
5918                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5919                         } else {
5920                                 if (fail_tramp) {
5921                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5922                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5923                                 } else {
5924                                         if (vtable_is_32bit)
5925                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5926                                         else
5927                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5928                                         item->chunk_size += JUMP_REG_SIZE;
5929                                         /* with assert below:
5930                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5931                                          */
5932                                 }
5933                         }
5934                 } else {
5935                         if (amd64_is_imm32 (item->key))
5936                                 item->chunk_size += CMP_SIZE;
5937                         else
5938                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5939                         item->chunk_size += BR_LARGE_SIZE;
5940                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5941                 }
5942                 size += item->chunk_size;
5943         }
5944         if (fail_tramp)
5945                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5946         else
5947                 code = mono_domain_code_reserve (domain, size);
5948         start = code;
5949         for (i = 0; i < count; ++i) {
5950                 MonoIMTCheckItem *item = imt_entries [i];
5951                 item->code_target = code;
5952                 if (item->is_equals) {
5953                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5954
5955                         if (item->check_target_idx || fail_case) {
5956                                 if (!item->compare_done || fail_case) {
5957                                         if (amd64_is_imm32 (item->key))
5958                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5959                                         else {
5960                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5961                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5962                                         }
5963                                 }
5964                                 item->jmp_code = code;
5965                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5966                                 /* See the comment below about R10 */
5967                                 if (item->has_target_code) {
5968                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5969                                         amd64_jump_reg (code, AMD64_R10);
5970                                 } else {
5971                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5972                                         amd64_jump_membase (code, AMD64_R10, 0);
5973                                 }
5974
5975                                 if (fail_case) {
5976                                         amd64_patch (item->jmp_code, code);
5977                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5978                                         amd64_jump_reg (code, AMD64_R10);
5979                                         item->jmp_code = NULL;
5980                                 }
5981                         } else {
5982                                 /* enable the commented code to assert on wrong method */
5983 #if 0
5984                                 if (amd64_is_imm32 (item->key))
5985                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5986                                 else {
5987                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
5988                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5989                                 }
5990                                 item->jmp_code = code;
5991                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5992                                 /* See the comment below about R10 */
5993                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5994                                 amd64_jump_membase (code, AMD64_R10, 0);
5995                                 amd64_patch (item->jmp_code, code);
5996                                 amd64_breakpoint (code);
5997                                 item->jmp_code = NULL;
5998 #else
5999                                 /* We're using R10 here because R11
6000                                    needs to be preserved.  R10 needs
6001                                    to be preserved for calls which
6002                                    require a runtime generic context,
6003                                    but interface calls don't. */
6004                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6005                                 amd64_jump_membase (code, AMD64_R10, 0);
6006 #endif
6007                         }
6008                 } else {
6009                         if (amd64_is_imm32 (item->key))
6010                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6011                         else {
6012                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6013                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6014                         }
6015                         item->jmp_code = code;
6016                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6017                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6018                         else
6019                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6020                 }
6021                 g_assert (code - item->code_target <= item->chunk_size);
6022         }
6023         /* patch the branches to get to the target items */
6024         for (i = 0; i < count; ++i) {
6025                 MonoIMTCheckItem *item = imt_entries [i];
6026                 if (item->jmp_code) {
6027                         if (item->check_target_idx) {
6028                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6029                         }
6030                 }
6031         }
6032
6033         if (!fail_tramp)
6034                 mono_stats.imt_thunks_size += code - start;
6035         g_assert (code - start <= size);
6036
6037         return start;
6038 }
6039
6040 MonoMethod*
6041 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6042 {
6043         return regs [MONO_ARCH_IMT_REG];
6044 }
6045
6046 MonoObject*
6047 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6048 {
6049         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6050 }
6051 #endif
6052
6053 MonoVTable*
6054 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6055 {
6056         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6057 }
6058
6059 MonoInst*
6060 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6061 {
6062         MonoInst *ins = NULL;
6063         int opcode = 0;
6064
6065         if (cmethod->klass == mono_defaults.math_class) {
6066                 if (strcmp (cmethod->name, "Sin") == 0) {
6067                         opcode = OP_SIN;
6068                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6069                         opcode = OP_COS;
6070                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6071                         opcode = OP_SQRT;
6072                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6073                         opcode = OP_ABS;
6074                 }
6075
6076                 if (opcode) {
6077                         MONO_INST_NEW (cfg, ins, opcode);
6078                         ins->type = STACK_R8;
6079                         ins->dreg = mono_alloc_freg (cfg);
6080                         ins->sreg1 = args [0]->dreg;
6081                         MONO_ADD_INS (cfg->cbb, ins);
6082                 }
6083
6084                 opcode = 0;
6085                 if (cfg->opt & MONO_OPT_CMOV) {
6086                         if (strcmp (cmethod->name, "Min") == 0) {
6087                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6088                                         opcode = OP_IMIN;
6089                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6090                                         opcode = OP_IMIN_UN;
6091                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6092                                         opcode = OP_LMIN;
6093                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6094                                         opcode = OP_LMIN_UN;
6095                         } else if (strcmp (cmethod->name, "Max") == 0) {
6096                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6097                                         opcode = OP_IMAX;
6098                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6099                                         opcode = OP_IMAX_UN;
6100                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6101                                         opcode = OP_LMAX;
6102                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6103                                         opcode = OP_LMAX_UN;
6104                         }
6105                 }
6106
6107                 if (opcode) {
6108                         MONO_INST_NEW (cfg, ins, opcode);
6109                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6110                         ins->dreg = mono_alloc_ireg (cfg);
6111                         ins->sreg1 = args [0]->dreg;
6112                         ins->sreg2 = args [1]->dreg;
6113                         MONO_ADD_INS (cfg->cbb, ins);
6114                 }
6115
6116 #if 0
6117                 /* OP_FREM is not IEEE compatible */
6118                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6119                         MONO_INST_NEW (cfg, ins, OP_FREM);
6120                         ins->inst_i0 = args [0];
6121                         ins->inst_i1 = args [1];
6122                 }
6123 #endif
6124         }
6125
6126         /*
6127          * Can't implement CompareExchange methods this way since they have
6128          * three arguments.
6129          */
6130
6131         return ins;
6132 }
6133
6134 gboolean
6135 mono_arch_print_tree (MonoInst *tree, int arity)
6136 {
6137         return 0;
6138 }
6139
6140 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6141 {
6142         MonoInst* ins;
6143
6144         if (appdomain_tls_offset == -1)
6145                 return NULL;
6146
6147         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6148         ins->inst_offset = appdomain_tls_offset;
6149         return ins;
6150 }
6151
6152 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6153 {
6154         MonoInst* ins;
6155
6156         if (thread_tls_offset == -1)
6157                 return NULL;
6158
6159         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6160         ins->inst_offset = thread_tls_offset;
6161         return ins;
6162 }
6163
6164 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6165
6166 gpointer
6167 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6168 {
6169         switch (reg) {
6170         case AMD64_RCX: return (gpointer)ctx->rcx;
6171         case AMD64_RDX: return (gpointer)ctx->rdx;
6172         case AMD64_RBX: return (gpointer)ctx->rbx;
6173         case AMD64_RBP: return (gpointer)ctx->rbp;
6174         case AMD64_RSP: return (gpointer)ctx->rsp;
6175         default:
6176                 if (reg < 8)
6177                         return _CTX_REG (ctx, rax, reg);
6178                 else if (reg >= 12)
6179                         return _CTX_REG (ctx, r12, reg - 12);
6180                 else
6181                         g_assert_not_reached ();
6182         }
6183 }