mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/metadata/gc-internal.h>
  27 #include <mono/utils/mono-math.h>
  28 #include <mono/utils/mono-mmap.h>
  29
  30 #include "trace.h"
  31 #include "ir-emit.h"
  32 #include "mini-amd64.h"
  33 #include "cpu-amd64.h"
  34 #include "debugger-agent.h"
  35
  36 static gint lmf_tls_offset = -1;
  37 static gint lmf_addr_tls_offset = -1;
  38 static gint appdomain_tls_offset = -1;
  39
  40 #ifdef MONO_XEN_OPT
  41 static gboolean optimize_for_xen = TRUE;
  42 #else
  43 #define optimize_for_xen 0
  44 #endif
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  51
  52 #ifdef HOST_WIN32
  53 /* Under windows, the calling convention is never stdcall */
  54 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  55 #else
  56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  57 #endif
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 MonoBreakpointInfo
  65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  66
  67 /*
  68  * The code generated for sequence points reads from this location, which is
  69  * made read-only when single stepping is enabled.
  70  */
  71 static gpointer ss_trigger_page;
  72
  73 /* Enabled breakpoints read from this trigger page */
  74 static gpointer bp_trigger_page;
  75
  76 /* The size of the breakpoint sequence */
  77 static int breakpoint_size;
  78
  79 /* The size of the breakpoint instruction causing the actual fault */
  80 static int breakpoint_fault_size;
  81
  82 /* The size of the single step instruction causing the actual fault */
  83 static int single_step_fault_size;
  84
  85 #ifdef HOST_WIN32
  86 /* On Win64 always reserve first 32 bytes for first four arguments */
  87 #define ARGS_OFFSET 48
  88 #else
  89 #define ARGS_OFFSET 16
  90 #endif
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 G_GNUC_UNUSED static void
 163 break_count (void)
 164 {
 165 }
 166
 167 G_GNUC_UNUSED static gboolean
 168 debug_count (void)
 169 {
 170         static int count = 0;
 171         count ++;
 172
 173         if (!getenv ("COUNT"))
 174                 return TRUE;
 175
 176         if (count == atoi (getenv ("COUNT"))) {
 177                 break_count ();
 178         }
 179
 180         if (count > atoi (getenv ("COUNT"))) {
 181                 return FALSE;
 182         }
 183
 184         return TRUE;
 185 }
 186
 187 static gboolean
 188 debug_omit_fp (void)
 189 {
 190 #if 0
 191         return debug_count ();
 192 #else
 193         return TRUE;
 194 #endif
 195 }
 196
 197 static inline gboolean
 198 amd64_is_near_call (guint8 *code)
 199 {
 200         /* Skip REX */
 201         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 202                 code += 1;
 203
 204         return code [0] == 0xe8;
 205 }
 206
 207 static inline void
 208 amd64_patch (unsigned char* code, gpointer target)
 209 {
 210         guint8 rex = 0;
 211
 212         /* Skip REX */
 213         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 214                 rex = code [0];
 215                 code += 1;
 216         }
 217
 218         if ((code [0] & 0xf8) == 0xb8) {
 219                 /* amd64_set_reg_template */
 220                 *(guint64*)(code + 1) = (guint64)target;
 221         }
 222         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 223                 /* mov 0(%rip), %dreg */
 224                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 225         }
 226         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 227                 /* call *<OFFSET>(%rip) */
 228                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 229         }
 230         else if ((code [0] == 0xe8)) {
 231                 /* call <DISP> */
 232                 gint64 disp = (guint8*)target - (guint8*)code;
 233                 g_assert (amd64_is_imm32 (disp));
 234                 x86_patch (code, (unsigned char*)target);
 235         }
 236         else
 237                 x86_patch (code, (unsigned char*)target);
 238 }
 239
 240 void
 241 mono_amd64_patch (unsigned char* code, gpointer target)
 242 {
 243         amd64_patch (code, target);
 244 }
 245
 246 typedef enum {
 247         ArgInIReg,
 248         ArgInFloatSSEReg,
 249         ArgInDoubleSSEReg,
 250         ArgOnStack,
 251         ArgValuetypeInReg,
 252         ArgValuetypeAddrInIReg,
 253         ArgNone /* only in pair_storage */
 254 } ArgStorage;
 255
 256 typedef struct {
 257         gint16 offset;
 258         gint8  reg;
 259         ArgStorage storage;
 260
 261         /* Only if storage == ArgValuetypeInReg */
 262         ArgStorage pair_storage [2];
 263         gint8 pair_regs [2];
 264 } ArgInfo;
 265
 266 typedef struct {
 267         int nargs;
 268         guint32 stack_usage;
 269         guint32 reg_usage;
 270         guint32 freg_usage;
 271         gboolean need_stack_align;
 272         gboolean vtype_retaddr;
 273         /* The index of the vret arg in the argument list */
 274         int vret_arg_index;
 275         ArgInfo ret;
 276         ArgInfo sig_cookie;
 277         ArgInfo args [1];
 278 } CallInfo;
 279
 280 #define DEBUG(a) if (cfg->verbose_level > 1) a
 281
 282 #ifdef HOST_WIN32
 283 #define PARAM_REGS 4
 284
 285 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 286
 287 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 288 #else
 289 #define PARAM_REGS 6
 290
 291 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 292
 293  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 294 #endif
 295
 296 static void inline
 297 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 ainfo->storage = ArgInIReg;
 307                 ainfo->reg = param_regs [*gr];
 308                 (*gr) ++;
 309     }
 310 }
 311
 312 #ifdef HOST_WIN32
 313 #define FLOAT_PARAM_REGS 4
 314 #else
 315 #define FLOAT_PARAM_REGS 8
 316 #endif
 317
 318 static void inline
 319 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 320 {
 321     ainfo->offset = *stack_size;
 322
 323     if (*gr >= FLOAT_PARAM_REGS) {
 324                 ainfo->storage = ArgOnStack;
 325                 (*stack_size) += sizeof (gpointer);
 326     }
 327     else {
 328                 /* A double register */
 329                 if (is_double)
 330                         ainfo->storage = ArgInDoubleSSEReg;
 331                 else
 332                         ainfo->storage = ArgInFloatSSEReg;
 333                 ainfo->reg = *gr;
 334                 (*gr) += 1;
 335     }
 336 }
 337
 338 typedef enum ArgumentClass {
 339         ARG_CLASS_NO_CLASS,
 340         ARG_CLASS_MEMORY,
 341         ARG_CLASS_INTEGER,
 342         ARG_CLASS_SSE
 343 } ArgumentClass;
 344
 345 static ArgumentClass
 346 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 347 {
 348         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 349         MonoType *ptype;
 350
 351         ptype = mini_type_get_underlying_type (NULL, type);
 352         switch (ptype->type) {
 353         case MONO_TYPE_BOOLEAN:
 354         case MONO_TYPE_CHAR:
 355         case MONO_TYPE_I1:
 356         case MONO_TYPE_U1:
 357         case MONO_TYPE_I2:
 358         case MONO_TYPE_U2:
 359         case MONO_TYPE_I4:
 360         case MONO_TYPE_U4:
 361         case MONO_TYPE_I:
 362         case MONO_TYPE_U:
 363         case MONO_TYPE_STRING:
 364         case MONO_TYPE_OBJECT:
 365         case MONO_TYPE_CLASS:
 366         case MONO_TYPE_SZARRAY:
 367         case MONO_TYPE_PTR:
 368         case MONO_TYPE_FNPTR:
 369         case MONO_TYPE_ARRAY:
 370         case MONO_TYPE_I8:
 371         case MONO_TYPE_U8:
 372                 class2 = ARG_CLASS_INTEGER;
 373                 break;
 374         case MONO_TYPE_R4:
 375         case MONO_TYPE_R8:
 376 #ifdef HOST_WIN32
 377                 class2 = ARG_CLASS_INTEGER;
 378 #else
 379                 class2 = ARG_CLASS_SSE;
 380 #endif
 381                 break;
 382
 383         case MONO_TYPE_TYPEDBYREF:
 384                 g_assert_not_reached ();
 385
 386         case MONO_TYPE_GENERICINST:
 387                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 388                         class2 = ARG_CLASS_INTEGER;
 389                         break;
 390                 }
 391                 /* fall through */
 392         case MONO_TYPE_VALUETYPE: {
 393                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 394                 int i;
 395
 396                 for (i = 0; i < info->num_fields; ++i) {
 397                         class2 = class1;
 398                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 399                 }
 400                 break;
 401         }
 402         default:
 403                 g_assert_not_reached ();
 404         }
 405
 406         /* Merge */
 407         if (class1 == class2)
 408                 ;
 409         else if (class1 == ARG_CLASS_NO_CLASS)
 410                 class1 = class2;
 411         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 412                 class1 = ARG_CLASS_MEMORY;
 413         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 414                 class1 = ARG_CLASS_INTEGER;
 415         else
 416                 class1 = ARG_CLASS_SSE;
 417
 418         return class1;
 419 }
 420
 421 static void
 422 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 423                            gboolean is_return,
 424                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 425 {
 426         guint32 size, quad, nquads, i;
 427         ArgumentClass args [2];
 428         MonoMarshalType *info = NULL;
 429         MonoClass *klass;
 430         MonoGenericSharingContext tmp_gsctx;
 431         gboolean pass_on_stack = FALSE;
 432
 433         /*
 434          * The gsctx currently contains no data, it is only used for checking whenever
 435          * open types are allowed, some callers like mono_arch_get_argument_info ()
 436          * don't pass it to us, so work around that.
 437          */
 438         if (!gsctx)
 439                 gsctx = &tmp_gsctx;
 440
 441         klass = mono_class_from_mono_type (type);
 442         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 443 #ifndef HOST_WIN32
 444         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 445                 /* We pass and return vtypes of size 8 in a register */
 446         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 447                 pass_on_stack = TRUE;
 448         }
 449 #else
 450         if (!sig->pinvoke) {
 451                 pass_on_stack = TRUE;
 452         }
 453 #endif
 454
 455         if (pass_on_stack) {
 456                 /* Allways pass in memory */
 457                 ainfo->offset = *stack_size;
 458                 *stack_size += ALIGN_TO (size, 8);
 459                 ainfo->storage = ArgOnStack;
 460
 461                 return;
 462         }
 463
 464         /* FIXME: Handle structs smaller than 8 bytes */
 465         //if ((size % 8) != 0)
 466         //      NOT_IMPLEMENTED;
 467
 468         if (size > 8)
 469                 nquads = 2;
 470         else
 471                 nquads = 1;
 472
 473         if (!sig->pinvoke) {
 474                 /* Always pass in 1 or 2 integer registers */
 475                 args [0] = ARG_CLASS_INTEGER;
 476                 args [1] = ARG_CLASS_INTEGER;
 477                 /* Only the simplest cases are supported */
 478                 if (is_return && nquads != 1) {
 479                         args [0] = ARG_CLASS_MEMORY;
 480                         args [1] = ARG_CLASS_MEMORY;
 481                 }
 482         } else {
 483                 /*
 484                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 485                  * The X87 and SSEUP stuff is left out since there are no such types in
 486                  * the CLR.
 487                  */
 488                 info = mono_marshal_load_type_info (klass);
 489                 g_assert (info);
 490
 491 #ifndef HOST_WIN32
 492                 if (info->native_size > 16) {
 493                         ainfo->offset = *stack_size;
 494                         *stack_size += ALIGN_TO (info->native_size, 8);
 495                         ainfo->storage = ArgOnStack;
 496
 497                         return;
 498                 }
 499 #else
 500                 switch (info->native_size) {
 501                 case 1: case 2: case 4: case 8:
 502                         break;
 503                 default:
 504                         if (is_return) {
 505                                 ainfo->storage = ArgOnStack;
 506                                 ainfo->offset = *stack_size;
 507                                 *stack_size += ALIGN_TO (info->native_size, 8);
 508                         }
 509                         else {
 510                                 ainfo->storage = ArgValuetypeAddrInIReg;
 511
 512                                 if (*gr < PARAM_REGS) {
 513                                         ainfo->pair_storage [0] = ArgInIReg;
 514                                         ainfo->pair_regs [0] = param_regs [*gr];
 515                                         (*gr) ++;
 516                                 }
 517                                 else {
 518                                         ainfo->pair_storage [0] = ArgOnStack;
 519                                         ainfo->offset = *stack_size;
 520                                         *stack_size += 8;
 521                                 }
 522                         }
 523
 524                         return;
 525                 }
 526 #endif
 527
 528                 args [0] = ARG_CLASS_NO_CLASS;
 529                 args [1] = ARG_CLASS_NO_CLASS;
 530                 for (quad = 0; quad < nquads; ++quad) {
 531                         int size;
 532                         guint32 align;
 533                         ArgumentClass class1;
 534
 535                         if (info->num_fields == 0)
 536                                 class1 = ARG_CLASS_MEMORY;
 537                         else
 538                                 class1 = ARG_CLASS_NO_CLASS;
 539                         for (i = 0; i < info->num_fields; ++i) {
 540                                 size = mono_marshal_type_size (info->fields [i].field->type,
 541                                                                                            info->fields [i].mspec,
 542                                                                                            &align, TRUE, klass->unicode);
 543                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 544                                         /* Unaligned field */
 545                                         NOT_IMPLEMENTED;
 546                                 }
 547
 548                                 /* Skip fields in other quad */
 549                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 550                                         continue;
 551                                 if ((quad == 1) && (info->fields [i].offset < 8))
 552                                         continue;
 553
 554                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 555                         }
 556                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 557                         args [quad] = class1;
 558                 }
 559         }
 560
 561         /* Post merger cleanup */
 562         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 563                 args [0] = args [1] = ARG_CLASS_MEMORY;
 564
 565         /* Allocate registers */
 566         {
 567                 int orig_gr = *gr;
 568                 int orig_fr = *fr;
 569
 570                 ainfo->storage = ArgValuetypeInReg;
 571                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 572                 for (quad = 0; quad < nquads; ++quad) {
 573                         switch (args [quad]) {
 574                         case ARG_CLASS_INTEGER:
 575                                 if (*gr >= PARAM_REGS)
 576                                         args [quad] = ARG_CLASS_MEMORY;
 577                                 else {
 578                                         ainfo->pair_storage [quad] = ArgInIReg;
 579                                         if (is_return)
 580                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 581                                         else
 582                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 583                                         (*gr) ++;
 584                                 }
 585                                 break;
 586                         case ARG_CLASS_SSE:
 587                                 if (*fr >= FLOAT_PARAM_REGS)
 588                                         args [quad] = ARG_CLASS_MEMORY;
 589                                 else {
 590                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 591                                         ainfo->pair_regs [quad] = *fr;
 592                                         (*fr) ++;
 593                                 }
 594                                 break;
 595                         case ARG_CLASS_MEMORY:
 596                                 break;
 597                         default:
 598                                 g_assert_not_reached ();
 599                         }
 600                 }
 601
 602                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 603                         /* Revert possible register assignments */
 604                         *gr = orig_gr;
 605                         *fr = orig_fr;
 606
 607                         ainfo->offset = *stack_size;
 608                         if (sig->pinvoke)
 609                                 *stack_size += ALIGN_TO (info->native_size, 8);
 610                         else
 611                                 *stack_size += nquads * sizeof (gpointer);
 612                         ainfo->storage = ArgOnStack;
 613                 }
 614         }
 615 }
 616
 617 /*
 618  * get_call_info:
 619  *
 620  *  Obtain information about a call according to the calling convention.
 621  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 622  * Draft Version 0.23" document for more information.
 623  */
 624 static CallInfo*
 625 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 626 {
 627         guint32 i, gr, fr, pstart;
 628         MonoType *ret_type;
 629         int n = sig->hasthis + sig->param_count;
 630         guint32 stack_size = 0;
 631         CallInfo *cinfo;
 632
 633         if (mp)
 634                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 635         else
 636                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 637
 638         cinfo->nargs = n;
 639
 640         gr = 0;
 641         fr = 0;
 642
 643         /* return value */
 644         {
 645                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 646                 switch (ret_type->type) {
 647                 case MONO_TYPE_BOOLEAN:
 648                 case MONO_TYPE_I1:
 649                 case MONO_TYPE_U1:
 650                 case MONO_TYPE_I2:
 651                 case MONO_TYPE_U2:
 652                 case MONO_TYPE_CHAR:
 653                 case MONO_TYPE_I4:
 654                 case MONO_TYPE_U4:
 655                 case MONO_TYPE_I:
 656                 case MONO_TYPE_U:
 657                 case MONO_TYPE_PTR:
 658                 case MONO_TYPE_FNPTR:
 659                 case MONO_TYPE_CLASS:
 660                 case MONO_TYPE_OBJECT:
 661                 case MONO_TYPE_SZARRAY:
 662                 case MONO_TYPE_ARRAY:
 663                 case MONO_TYPE_STRING:
 664                         cinfo->ret.storage = ArgInIReg;
 665                         cinfo->ret.reg = AMD64_RAX;
 666                         break;
 667                 case MONO_TYPE_U8:
 668                 case MONO_TYPE_I8:
 669                         cinfo->ret.storage = ArgInIReg;
 670                         cinfo->ret.reg = AMD64_RAX;
 671                         break;
 672                 case MONO_TYPE_R4:
 673                         cinfo->ret.storage = ArgInFloatSSEReg;
 674                         cinfo->ret.reg = AMD64_XMM0;
 675                         break;
 676                 case MONO_TYPE_R8:
 677                         cinfo->ret.storage = ArgInDoubleSSEReg;
 678                         cinfo->ret.reg = AMD64_XMM0;
 679                         break;
 680                 case MONO_TYPE_GENERICINST:
 681                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 682                                 cinfo->ret.storage = ArgInIReg;
 683                                 cinfo->ret.reg = AMD64_RAX;
 684                                 break;
 685                         }
 686                         /* fall through */
 687                 case MONO_TYPE_VALUETYPE: {
 688                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 689
 690                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 691                         if (cinfo->ret.storage == ArgOnStack) {
 692                                 cinfo->vtype_retaddr = TRUE;
 693                                 /* The caller passes the address where the value is stored */
 694                         }
 695                         break;
 696                 }
 697                 case MONO_TYPE_TYPEDBYREF:
 698                         /* Same as a valuetype with size 24 */
 699                         cinfo->vtype_retaddr = TRUE;
 700                         break;
 701                 case MONO_TYPE_VOID:
 702                         break;
 703                 default:
 704                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 705                 }
 706         }
 707
 708         pstart = 0;
 709         /*
 710          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 711          * the first argument, allowing 'this' to be always passed in the first arg reg.
 712          * Also do this if the first argument is a reference type, since virtual calls
 713          * are sometimes made using calli without sig->hasthis set, like in the delegate
 714          * invoke wrappers.
 715          */
 716         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 717                 if (sig->hasthis) {
 718                         add_general (&gr, &stack_size, cinfo->args + 0);
 719                 } else {
 720                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 721                         pstart = 1;
 722                 }
 723                 add_general (&gr, &stack_size, &cinfo->ret);
 724                 cinfo->vret_arg_index = 1;
 725         } else {
 726                 /* this */
 727                 if (sig->hasthis)
 728                         add_general (&gr, &stack_size, cinfo->args + 0);
 729
 730                 if (cinfo->vtype_retaddr)
 731                         add_general (&gr, &stack_size, &cinfo->ret);
 732         }
 733
 734         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 735                 gr = PARAM_REGS;
 736                 fr = FLOAT_PARAM_REGS;
 737
 738                 /* Emit the signature cookie just before the implicit arguments */
 739                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 740         }
 741
 742         for (i = pstart; i < sig->param_count; ++i) {
 743                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 744                 MonoType *ptype;
 745
 746 #ifdef HOST_WIN32
 747                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 748                 if (gr > fr)
 749                         fr = gr;
 750                 else if (fr > gr)
 751                         gr = fr;
 752 #endif
 753
 754                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 755                         /* We allways pass the sig cookie on the stack for simplicity */
 756                         /*
 757                          * Prevent implicit arguments + the sig cookie from being passed
 758                          * in registers.
 759                          */
 760                         gr = PARAM_REGS;
 761                         fr = FLOAT_PARAM_REGS;
 762
 763                         /* Emit the signature cookie just before the implicit arguments */
 764                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 765                 }
 766
 767                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 768                 switch (ptype->type) {
 769                 case MONO_TYPE_BOOLEAN:
 770                 case MONO_TYPE_I1:
 771                 case MONO_TYPE_U1:
 772                         add_general (&gr, &stack_size, ainfo);
 773                         break;
 774                 case MONO_TYPE_I2:
 775                 case MONO_TYPE_U2:
 776                 case MONO_TYPE_CHAR:
 777                         add_general (&gr, &stack_size, ainfo);
 778                         break;
 779                 case MONO_TYPE_I4:
 780                 case MONO_TYPE_U4:
 781                         add_general (&gr, &stack_size, ainfo);
 782                         break;
 783                 case MONO_TYPE_I:
 784                 case MONO_TYPE_U:
 785                 case MONO_TYPE_PTR:
 786                 case MONO_TYPE_FNPTR:
 787                 case MONO_TYPE_CLASS:
 788                 case MONO_TYPE_OBJECT:
 789                 case MONO_TYPE_STRING:
 790                 case MONO_TYPE_SZARRAY:
 791                 case MONO_TYPE_ARRAY:
 792                         add_general (&gr, &stack_size, ainfo);
 793                         break;
 794                 case MONO_TYPE_GENERICINST:
 795                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 796                                 add_general (&gr, &stack_size, ainfo);
 797                                 break;
 798                         }
 799                         /* fall through */
 800                 case MONO_TYPE_VALUETYPE:
 801                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 802                         break;
 803                 case MONO_TYPE_TYPEDBYREF:
 804 #ifdef HOST_WIN32
 805                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 806 #else
 807                         stack_size += sizeof (MonoTypedRef);
 808                         ainfo->storage = ArgOnStack;
 809 #endif
 810                         break;
 811                 case MONO_TYPE_U8:
 812                 case MONO_TYPE_I8:
 813                         add_general (&gr, &stack_size, ainfo);
 814                         break;
 815                 case MONO_TYPE_R4:
 816                         add_float (&fr, &stack_size, ainfo, FALSE);
 817                         break;
 818                 case MONO_TYPE_R8:
 819                         add_float (&fr, &stack_size, ainfo, TRUE);
 820                         break;
 821                 default:
 822                         g_assert_not_reached ();
 823                 }
 824         }
 825
 826         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 827                 gr = PARAM_REGS;
 828                 fr = FLOAT_PARAM_REGS;
 829
 830                 /* Emit the signature cookie just before the implicit arguments */
 831                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 832         }
 833
 834 #ifdef HOST_WIN32
 835         // There always is 32 bytes reserved on the stack when calling on Winx64
 836         stack_size += 0x20;
 837 #endif
 838
 839         if (stack_size & 0x8) {
 840                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 841                 cinfo->need_stack_align = TRUE;
 842                 stack_size += 8;
 843         }
 844
 845         cinfo->stack_usage = stack_size;
 846         cinfo->reg_usage = gr;
 847         cinfo->freg_usage = fr;
 848         return cinfo;
 849 }
 850
 851 /*
 852  * mono_arch_get_argument_info:
 853  * @csig:  a method signature
 854  * @param_count: the number of parameters to consider
 855  * @arg_info: an array to store the result infos
 856  *
 857  * Gathers information on parameters such as size, alignment and
 858  * padding. arg_info should be large enought to hold param_count + 1 entries.
 859  *
 860  * Returns the size of the argument area on the stack.
 861  */
 862 int
 863 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 864 {
 865         int k;
 866         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 867         guint32 args_size = cinfo->stack_usage;
 868
 869         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 870         if (csig->hasthis) {
 871                 arg_info [0].offset = 0;
 872         }
 873
 874         for (k = 0; k < param_count; k++) {
 875                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 876                 /* FIXME: */
 877                 arg_info [k + 1].size = 0;
 878         }
 879
 880         g_free (cinfo);
 881
 882         return args_size;
 883 }
 884
 885 static int
 886 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 887 {
 888 #ifndef _MSC_VER
 889         __asm__ __volatile__ ("cpuid"
 890                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 891                 : "a" (id));
 892 #else
 893         int info[4];
 894         __cpuid(info, id);
 895         *p_eax = info[0];
 896         *p_ebx = info[1];
 897         *p_ecx = info[2];
 898         *p_edx = info[3];
 899 #endif
 900         return 1;
 901 }
 902
 903 /*
 904  * Initialize the cpu to execute managed code.
 905  */
 906 void
 907 mono_arch_cpu_init (void)
 908 {
 909 #ifndef _MSC_VER
 910         guint16 fpcw;
 911
 912         /* spec compliance requires running with double precision */
 913         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 914         fpcw &= ~X86_FPCW_PRECC_MASK;
 915         fpcw |= X86_FPCW_PREC_DOUBLE;
 916         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 917         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 918 #else
 919         /* TODO: This is crashing on Win64 right now.
 920         * _control87 (_PC_53, MCW_PC);
 921         */
 922 #endif
 923 }
 924
 925 /*
 926  * Initialize architecture specific code.
 927  */
 928 void
 929 mono_arch_init (void)
 930 {
 931         int flags;
 932
 933         InitializeCriticalSection (&mini_arch_mutex);
 934
 935 #ifdef MONO_ARCH_NOMAP32BIT
 936         flags = MONO_MMAP_READ;
 937         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 938         breakpoint_size = 13;
 939         breakpoint_fault_size = 3;
 940         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 941         single_step_fault_size = 5;
 942 #else
 943         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 944         /* amd64_mov_reg_mem () */
 945         breakpoint_size = 8;
 946         breakpoint_fault_size = 8;
 947         single_step_fault_size = 8;
 948 #endif
 949
 950         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 951         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 952         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 953
 954         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 955         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 956         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 957 }
 958
 959 /*
 960  * Cleanup architecture specific code.
 961  */
 962 void
 963 mono_arch_cleanup (void)
 964 {
 965         DeleteCriticalSection (&mini_arch_mutex);
 966 }
 967
 968 /*
 969  * This function returns the optimizations supported on this cpu.
 970  */
 971 guint32
 972 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 973 {
 974         int eax, ebx, ecx, edx;
 975         guint32 opts = 0;
 976
 977         *exclude_mask = 0;
 978         /* Feature Flags function, flags returned in EDX. */
 979         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 980                 if (edx & (1 << 15)) {
 981                         opts |= MONO_OPT_CMOV;
 982                         if (edx & 1)
 983                                 opts |= MONO_OPT_FCMOV;
 984                         else
 985                                 *exclude_mask |= MONO_OPT_FCMOV;
 986                 } else
 987                         *exclude_mask |= MONO_OPT_CMOV;
 988         }
 989
 990         return opts;
 991 }
 992
 993 /*
 994  * This function test for all SSE functions supported.
 995  *
 996  * Returns a bitmask corresponding to all supported versions.
 997  *
 998  */
 999 guint32
1000 mono_arch_cpu_enumerate_simd_versions (void)
1001 {
1002         int eax, ebx, ecx, edx;
1003         guint32 sse_opts = 0;
1004
1005         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1006                 if (edx & (1 << 25))
1007                         sse_opts |= SIMD_VERSION_SSE1;
1008                 if (edx & (1 << 26))
1009                         sse_opts |= SIMD_VERSION_SSE2;
1010                 if (ecx & (1 << 0))
1011                         sse_opts |= SIMD_VERSION_SSE3;
1012                 if (ecx & (1 << 9))
1013                         sse_opts |= SIMD_VERSION_SSSE3;
1014                 if (ecx & (1 << 19))
1015                         sse_opts |= SIMD_VERSION_SSE41;
1016                 if (ecx & (1 << 20))
1017                         sse_opts |= SIMD_VERSION_SSE42;
1018         }
1019
1020         /* Yes, all this needs to be done to check for sse4a.
1021            See: "Amd: CPUID Specification"
1022          */
1023         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1024                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1025                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1026                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1027                         if (ecx & (1 << 6))
1028                                 sse_opts |= SIMD_VERSION_SSE4a;
1029                 }
1030         }
1031
1032         return sse_opts;
1033 }
1034
1035 #ifndef DISABLE_JIT
1036
1037 GList *
1038 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1039 {
1040         GList *vars = NULL;
1041         int i;
1042
1043         for (i = 0; i < cfg->num_varinfo; i++) {
1044                 MonoInst *ins = cfg->varinfo [i];
1045                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1046
1047                 /* unused vars */
1048                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1049                         continue;
1050
1051                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1052                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1053                         continue;
1054
1055                 if (mono_is_regsize_var (ins->inst_vtype)) {
1056                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1057                         g_assert (i == vmv->idx);
1058                         vars = g_list_prepend (vars, vmv);
1059                 }
1060         }
1061
1062         vars = mono_varlist_sort (cfg, vars, 0);
1063
1064         return vars;
1065 }
1066
1067 /**
1068  * mono_arch_compute_omit_fp:
1069  *
1070  *   Determine whenever the frame pointer can be eliminated.
1071  */
1072 static void
1073 mono_arch_compute_omit_fp (MonoCompile *cfg)
1074 {
1075         MonoMethodSignature *sig;
1076         MonoMethodHeader *header;
1077         int i, locals_size;
1078         CallInfo *cinfo;
1079
1080         if (cfg->arch.omit_fp_computed)
1081                 return;
1082
1083         header = cfg->header;
1084
1085         sig = mono_method_signature (cfg->method);
1086
1087         if (!cfg->arch.cinfo)
1088                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1089         cinfo = cfg->arch.cinfo;
1090
1091         /*
1092          * FIXME: Remove some of the restrictions.
1093          */
1094         cfg->arch.omit_fp = TRUE;
1095         cfg->arch.omit_fp_computed = TRUE;
1096
1097         if (cfg->disable_omit_fp)
1098                 cfg->arch.omit_fp = FALSE;
1099
1100         if (!debug_omit_fp ())
1101                 cfg->arch.omit_fp = FALSE;
1102         /*
1103         if (cfg->method->save_lmf)
1104                 cfg->arch.omit_fp = FALSE;
1105         */
1106         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1107                 cfg->arch.omit_fp = FALSE;
1108         if (header->num_clauses)
1109                 cfg->arch.omit_fp = FALSE;
1110         if (cfg->param_area)
1111                 cfg->arch.omit_fp = FALSE;
1112         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1113                 cfg->arch.omit_fp = FALSE;
1114         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1115                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1116                 cfg->arch.omit_fp = FALSE;
1117         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [i];
1119
1120                 if (ainfo->storage == ArgOnStack) {
1121                         /*
1122                          * The stack offset can only be determined when the frame
1123                          * size is known.
1124                          */
1125                         cfg->arch.omit_fp = FALSE;
1126                 }
1127         }
1128
1129         locals_size = 0;
1130         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1131                 MonoInst *ins = cfg->varinfo [i];
1132                 int ialign;
1133
1134                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1135         }
1136 }
1137
1138 GList *
1139 mono_arch_get_global_int_regs (MonoCompile *cfg)
1140 {
1141         GList *regs = NULL;
1142
1143         mono_arch_compute_omit_fp (cfg);
1144
1145         if (cfg->globalra) {
1146                 if (cfg->arch.omit_fp)
1147                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1148
1149                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1150                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1151                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1152                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1153                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1154
1155                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1156                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1157                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1158                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1159                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1160                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1161                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1162                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1163         } else {
1164                 if (cfg->arch.omit_fp)
1165                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1166
1167                 /* We use the callee saved registers for global allocation */
1168                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1169                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1173 #ifdef HOST_WIN32
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1176 #endif
1177         }
1178
1179         return regs;
1180 }
1181
1182 GList*
1183 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1184 {
1185         GList *regs = NULL;
1186         int i;
1187
1188         /* All XMM registers */
1189         for (i = 0; i < 16; ++i)
1190                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1191
1192         return regs;
1193 }
1194
1195 GList*
1196 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1197 {
1198         static GList *r = NULL;
1199
1200         if (r == NULL) {
1201                 GList *regs = NULL;
1202
1203                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1204                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1205                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1206                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1207                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1208                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1209
1210                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1211                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1212                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1213                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1214                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1215                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1216                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1217                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1218
1219                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1220         }
1221
1222         return r;
1223 }
1224
1225 GList*
1226 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1227 {
1228         int i;
1229         static GList *r = NULL;
1230
1231         if (r == NULL) {
1232                 GList *regs = NULL;
1233
1234                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1235                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1236
1237                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1238         }
1239
1240         return r;
1241 }
1242
1243 /*
1244  * mono_arch_regalloc_cost:
1245  *
1246  *  Return the cost, in number of memory references, of the action of
1247  * allocating the variable VMV into a register during global register
1248  * allocation.
1249  */
1250 guint32
1251 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1252 {
1253         MonoInst *ins = cfg->varinfo [vmv->idx];
1254
1255         if (cfg->method->save_lmf)
1256                 /* The register is already saved */
1257                 /* substract 1 for the invisible store in the prolog */
1258                 return (ins->opcode == OP_ARG) ? 0 : 1;
1259         else
1260                 /* push+pop */
1261                 return (ins->opcode == OP_ARG) ? 1 : 2;
1262 }
1263
1264 /*
1265  * mono_arch_fill_argument_info:
1266  *
1267  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1268  * of the method.
1269  */
1270 void
1271 mono_arch_fill_argument_info (MonoCompile *cfg)
1272 {
1273         MonoMethodSignature *sig;
1274         MonoMethodHeader *header;
1275         MonoInst *ins;
1276         int i;
1277         CallInfo *cinfo;
1278
1279         header = cfg->header;
1280
1281         sig = mono_method_signature (cfg->method);
1282
1283         cinfo = cfg->arch.cinfo;
1284
1285         /*
1286          * Contrary to mono_arch_allocate_vars (), the information should describe
1287          * where the arguments are at the beginning of the method, not where they can be
1288          * accessed during the execution of the method. The later makes no sense for the
1289          * global register allocator, since a variable can be in more than one location.
1290          */
1291         if (sig->ret->type != MONO_TYPE_VOID) {
1292                 switch (cinfo->ret.storage) {
1293                 case ArgInIReg:
1294                 case ArgInFloatSSEReg:
1295                 case ArgInDoubleSSEReg:
1296                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1297                                 cfg->vret_addr->opcode = OP_REGVAR;
1298                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1299                         }
1300                         else {
1301                                 cfg->ret->opcode = OP_REGVAR;
1302                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1303                         }
1304                         break;
1305                 case ArgValuetypeInReg:
1306                         cfg->ret->opcode = OP_REGOFFSET;
1307                         cfg->ret->inst_basereg = -1;
1308                         cfg->ret->inst_offset = -1;
1309                         break;
1310                 default:
1311                         g_assert_not_reached ();
1312                 }
1313         }
1314
1315         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1316                 ArgInfo *ainfo = &cinfo->args [i];
1317                 MonoType *arg_type;
1318
1319                 ins = cfg->args [i];
1320
1321                 if (sig->hasthis && (i == 0))
1322                         arg_type = &mono_defaults.object_class->byval_arg;
1323                 else
1324                         arg_type = sig->params [i - sig->hasthis];
1325
1326                 switch (ainfo->storage) {
1327                 case ArgInIReg:
1328                 case ArgInFloatSSEReg:
1329                 case ArgInDoubleSSEReg:
1330                         ins->opcode = OP_REGVAR;
1331                         ins->inst_c0 = ainfo->reg;
1332                         break;
1333                 case ArgOnStack:
1334                         ins->opcode = OP_REGOFFSET;
1335                         ins->inst_basereg = -1;
1336                         ins->inst_offset = -1;
1337                         break;
1338                 case ArgValuetypeInReg:
1339                         /* Dummy */
1340                         ins->opcode = OP_NOP;
1341                         break;
1342                 default:
1343                         g_assert_not_reached ();
1344                 }
1345         }
1346 }
1347
1348 void
1349 mono_arch_allocate_vars (MonoCompile *cfg)
1350 {
1351         MonoMethodSignature *sig;
1352         MonoMethodHeader *header;
1353         MonoInst *ins;
1354         int i, offset;
1355         guint32 locals_stack_size, locals_stack_align;
1356         gint32 *offsets;
1357         CallInfo *cinfo;
1358
1359         header = cfg->header;
1360
1361         sig = mono_method_signature (cfg->method);
1362
1363         cinfo = cfg->arch.cinfo;
1364
1365         mono_arch_compute_omit_fp (cfg);
1366
1367         /*
1368          * We use the ABI calling conventions for managed code as well.
1369          * Exception: valuetypes are only sometimes passed or returned in registers.
1370          */
1371
1372         /*
1373          * The stack looks like this:
1374          * <incoming arguments passed on the stack>
1375          * <return value>
1376          * <lmf/caller saved registers>
1377          * <locals>
1378          * <spill area>
1379          * <localloc area>  -> grows dynamically
1380          * <params area>
1381          */
1382
1383         if (cfg->arch.omit_fp) {
1384                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1385                 cfg->frame_reg = AMD64_RSP;
1386                 offset = 0;
1387         } else {
1388                 /* Locals are allocated backwards from %fp */
1389                 cfg->frame_reg = AMD64_RBP;
1390                 offset = 0;
1391         }
1392
1393         if (cfg->method->save_lmf) {
1394                 /* Reserve stack space for saving LMF */
1395                 if (cfg->arch.omit_fp) {
1396                         cfg->arch.lmf_offset = offset;
1397                         offset += sizeof (MonoLMF);
1398                 }
1399                 else {
1400                         offset += sizeof (MonoLMF);
1401                         cfg->arch.lmf_offset = -offset;
1402                 }
1403         } else {
1404                 if (cfg->arch.omit_fp)
1405                         cfg->arch.reg_save_area_offset = offset;
1406                 /* Reserve space for caller saved registers */
1407                 for (i = 0; i < AMD64_NREG; ++i)
1408                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1409                                 offset += sizeof (gpointer);
1410                         }
1411         }
1412
1413         if (sig->ret->type != MONO_TYPE_VOID) {
1414                 switch (cinfo->ret.storage) {
1415                 case ArgInIReg:
1416                 case ArgInFloatSSEReg:
1417                 case ArgInDoubleSSEReg:
1418                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1419                                 if (cfg->globalra) {
1420                                         cfg->vret_addr->opcode = OP_REGVAR;
1421                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1422                                 } else {
1423                                         /* The register is volatile */
1424                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1425                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1426                                         if (cfg->arch.omit_fp) {
1427                                                 cfg->vret_addr->inst_offset = offset;
1428                                                 offset += 8;
1429                                         } else {
1430                                                 offset += 8;
1431                                                 cfg->vret_addr->inst_offset = -offset;
1432                                         }
1433                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1434                                                 printf ("vret_addr =");
1435                                                 mono_print_ins (cfg->vret_addr);
1436                                         }
1437                                 }
1438                         }
1439                         else {
1440                                 cfg->ret->opcode = OP_REGVAR;
1441                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1442                         }
1443                         break;
1444                 case ArgValuetypeInReg:
1445                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1446                         cfg->ret->opcode = OP_REGOFFSET;
1447                         cfg->ret->inst_basereg = cfg->frame_reg;
1448                         if (cfg->arch.omit_fp) {
1449                                 cfg->ret->inst_offset = offset;
1450                                 offset += 16;
1451                         } else {
1452                                 offset += 16;
1453                                 cfg->ret->inst_offset = - offset;
1454                         }
1455                         break;
1456                 default:
1457                         g_assert_not_reached ();
1458                 }
1459                 if (!cfg->globalra)
1460                         cfg->ret->dreg = cfg->ret->inst_c0;
1461         }
1462
1463         /* Allocate locals */
1464         if (!cfg->globalra) {
1465                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1466                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1467                         char *mname = mono_method_full_name (cfg->method, TRUE);
1468                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1469                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1470                         g_free (mname);
1471                         return;
1472                 }
1473
1474                 if (locals_stack_align) {
1475                         offset += (locals_stack_align - 1);
1476                         offset &= ~(locals_stack_align - 1);
1477                 }
1478                 if (cfg->arch.omit_fp) {
1479                         cfg->locals_min_stack_offset = offset;
1480                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1481                 } else {
1482                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1483                         cfg->locals_max_stack_offset = - offset;
1484                 }
1485
1486                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1487                         if (offsets [i] != -1) {
1488                                 MonoInst *ins = cfg->varinfo [i];
1489                                 ins->opcode = OP_REGOFFSET;
1490                                 ins->inst_basereg = cfg->frame_reg;
1491                                 if (cfg->arch.omit_fp)
1492                                         ins->inst_offset = (offset + offsets [i]);
1493                                 else
1494                                         ins->inst_offset = - (offset + offsets [i]);
1495                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1496                         }
1497                 }
1498                 offset += locals_stack_size;
1499         }
1500
1501         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1502                 g_assert (!cfg->arch.omit_fp);
1503                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1504                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1505         }
1506
1507         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1508                 ins = cfg->args [i];
1509                 if (ins->opcode != OP_REGVAR) {
1510                         ArgInfo *ainfo = &cinfo->args [i];
1511                         gboolean inreg = TRUE;
1512                         MonoType *arg_type;
1513
1514                         if (sig->hasthis && (i == 0))
1515                                 arg_type = &mono_defaults.object_class->byval_arg;
1516                         else
1517                                 arg_type = sig->params [i - sig->hasthis];
1518
1519                         if (cfg->globalra) {
1520                                 /* The new allocator needs info about the original locations of the arguments */
1521                                 switch (ainfo->storage) {
1522                                 case ArgInIReg:
1523                                 case ArgInFloatSSEReg:
1524                                 case ArgInDoubleSSEReg:
1525                                         ins->opcode = OP_REGVAR;
1526                                         ins->inst_c0 = ainfo->reg;
1527                                         break;
1528                                 case ArgOnStack:
1529                                         g_assert (!cfg->arch.omit_fp);
1530                                         ins->opcode = OP_REGOFFSET;
1531                                         ins->inst_basereg = cfg->frame_reg;
1532                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1533                                         break;
1534                                 case ArgValuetypeInReg:
1535                                         ins->opcode = OP_REGOFFSET;
1536                                         ins->inst_basereg = cfg->frame_reg;
1537                                         /* These arguments are saved to the stack in the prolog */
1538                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1539                                         if (cfg->arch.omit_fp) {
1540                                                 ins->inst_offset = offset;
1541                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1542                                         } else {
1543                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1544                                                 ins->inst_offset = - offset;
1545                                         }
1546                                         break;
1547                                 default:
1548                                         g_assert_not_reached ();
1549                                 }
1550
1551                                 continue;
1552                         }
1553
1554                         /* FIXME: Allocate volatile arguments to registers */
1555                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1556                                 inreg = FALSE;
1557
1558                         /*
1559                          * Under AMD64, all registers used to pass arguments to functions
1560                          * are volatile across calls.
1561                          * FIXME: Optimize this.
1562                          */
1563                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1564                                 inreg = FALSE;
1565
1566                         ins->opcode = OP_REGOFFSET;
1567
1568                         switch (ainfo->storage) {
1569                         case ArgInIReg:
1570                         case ArgInFloatSSEReg:
1571                         case ArgInDoubleSSEReg:
1572                                 if (inreg) {
1573                                         ins->opcode = OP_REGVAR;
1574                                         ins->dreg = ainfo->reg;
1575                                 }
1576                                 break;
1577                         case ArgOnStack:
1578                                 g_assert (!cfg->arch.omit_fp);
1579                                 ins->opcode = OP_REGOFFSET;
1580                                 ins->inst_basereg = cfg->frame_reg;
1581                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1582                                 break;
1583                         case ArgValuetypeInReg:
1584                                 break;
1585                         case ArgValuetypeAddrInIReg: {
1586                                 MonoInst *indir;
1587                                 g_assert (!cfg->arch.omit_fp);
1588
1589                                 MONO_INST_NEW (cfg, indir, 0);
1590                                 indir->opcode = OP_REGOFFSET;
1591                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1592                                         indir->inst_basereg = cfg->frame_reg;
1593                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1594                                         offset += (sizeof (gpointer));
1595                                         indir->inst_offset = - offset;
1596                                 }
1597                                 else {
1598                                         indir->inst_basereg = cfg->frame_reg;
1599                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1600                                 }
1601
1602                                 ins->opcode = OP_VTARG_ADDR;
1603                                 ins->inst_left = indir;
1604
1605                                 break;
1606                         }
1607                         default:
1608                                 NOT_IMPLEMENTED;
1609                         }
1610
1611                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1612                                 ins->opcode = OP_REGOFFSET;
1613                                 ins->inst_basereg = cfg->frame_reg;
1614                                 /* These arguments are saved to the stack in the prolog */
1615                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1616                                 if (cfg->arch.omit_fp) {
1617                                         ins->inst_offset = offset;
1618                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1619                                         // Arguments are yet supported by the stack map creation code
1620                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1621                                 } else {
1622                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1623                                         ins->inst_offset = - offset;
1624                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1625                                 }
1626                         }
1627                 }
1628         }
1629
1630         cfg->stack_offset = offset;
1631 }
1632
1633 void
1634 mono_arch_create_vars (MonoCompile *cfg)
1635 {
1636         MonoMethodSignature *sig;
1637         CallInfo *cinfo;
1638
1639         sig = mono_method_signature (cfg->method);
1640
1641         if (!cfg->arch.cinfo)
1642                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1643         cinfo = cfg->arch.cinfo;
1644
1645         if (cinfo->ret.storage == ArgValuetypeInReg)
1646                 cfg->ret_var_is_local = TRUE;
1647
1648         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1649                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1650                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1651                         printf ("vret_addr = ");
1652                         mono_print_ins (cfg->vret_addr);
1653                 }
1654         }
1655
1656         if (cfg->gen_seq_points) {
1657                 MonoInst *ins;
1658
1659             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1660                 ins->flags |= MONO_INST_VOLATILE;
1661                 cfg->arch.ss_trigger_page_var = ins;
1662         }
1663
1664 #ifdef MONO_AMD64_NO_PUSHES
1665         /*
1666          * When this is set, we pass arguments on the stack by moves, and by allocating
1667          * a bigger stack frame, instead of pushes.
1668          * Pushes complicate exception handling because the arguments on the stack have
1669          * to be popped each time a frame is unwound. They also make fp elimination
1670          * impossible.
1671          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1672          * on a new frame which doesn't include a param area.
1673          */
1674         cfg->arch.no_pushes = TRUE;
1675 #endif
1676 }
1677
1678 static void
1679 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1680 {
1681         MonoInst *ins;
1682
1683         switch (storage) {
1684         case ArgInIReg:
1685                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1686                 ins->dreg = mono_alloc_ireg (cfg);
1687                 ins->sreg1 = tree->dreg;
1688                 MONO_ADD_INS (cfg->cbb, ins);
1689                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1690                 break;
1691         case ArgInFloatSSEReg:
1692                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1693                 ins->dreg = mono_alloc_freg (cfg);
1694                 ins->sreg1 = tree->dreg;
1695                 MONO_ADD_INS (cfg->cbb, ins);
1696
1697                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1698                 break;
1699         case ArgInDoubleSSEReg:
1700                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1701                 ins->dreg = mono_alloc_freg (cfg);
1702                 ins->sreg1 = tree->dreg;
1703                 MONO_ADD_INS (cfg->cbb, ins);
1704
1705                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1706
1707                 break;
1708         default:
1709                 g_assert_not_reached ();
1710         }
1711 }
1712
1713 static int
1714 arg_storage_to_load_membase (ArgStorage storage)
1715 {
1716         switch (storage) {
1717         case ArgInIReg:
1718                 return OP_LOAD_MEMBASE;
1719         case ArgInDoubleSSEReg:
1720                 return OP_LOADR8_MEMBASE;
1721         case ArgInFloatSSEReg:
1722                 return OP_LOADR4_MEMBASE;
1723         default:
1724                 g_assert_not_reached ();
1725         }
1726
1727         return -1;
1728 }
1729
1730 static void
1731 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1732 {
1733         MonoInst *arg;
1734         MonoMethodSignature *tmp_sig;
1735         MonoInst *sig_arg;
1736
1737         if (call->tail_call)
1738                 NOT_IMPLEMENTED;
1739
1740         /* FIXME: Add support for signature tokens to AOT */
1741         cfg->disable_aot = TRUE;
1742
1743         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1744
1745         /*
1746          * mono_ArgIterator_Setup assumes the signature cookie is
1747          * passed first and all the arguments which were before it are
1748          * passed on the stack after the signature. So compensate by
1749          * passing a different signature.
1750          */
1751         tmp_sig = mono_metadata_signature_dup (call->signature);
1752         tmp_sig->param_count -= call->signature->sentinelpos;
1753         tmp_sig->sentinelpos = 0;
1754         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1755
1756         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1757         sig_arg->dreg = mono_alloc_ireg (cfg);
1758         sig_arg->inst_p0 = tmp_sig;
1759         MONO_ADD_INS (cfg->cbb, sig_arg);
1760
1761         if (cfg->arch.no_pushes) {
1762                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1763         } else {
1764                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1765                 arg->sreg1 = sig_arg->dreg;
1766                 MONO_ADD_INS (cfg->cbb, arg);
1767         }
1768 }
1769
1770 static inline LLVMArgStorage
1771 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1772 {
1773         switch (storage) {
1774         case ArgInIReg:
1775                 return LLVMArgInIReg;
1776         case ArgNone:
1777                 return LLVMArgNone;
1778         default:
1779                 g_assert_not_reached ();
1780                 return LLVMArgNone;
1781         }
1782 }
1783
1784 #ifdef ENABLE_LLVM
1785 LLVMCallInfo*
1786 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1787 {
1788         int i, n;
1789         CallInfo *cinfo;
1790         ArgInfo *ainfo;
1791         int j;
1792         LLVMCallInfo *linfo;
1793         MonoType *t;
1794
1795         n = sig->param_count + sig->hasthis;
1796
1797         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1798
1799         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1800
1801         /*
1802          * LLVM always uses the native ABI while we use our own ABI, the
1803          * only difference is the handling of vtypes:
1804          * - we only pass/receive them in registers in some cases, and only
1805          *   in 1 or 2 integer registers.
1806          */
1807         if (cinfo->ret.storage == ArgValuetypeInReg) {
1808                 if (sig->pinvoke) {
1809                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1810                         cfg->disable_llvm = TRUE;
1811                         return linfo;
1812                 }
1813
1814                 linfo->ret.storage = LLVMArgVtypeInReg;
1815                 for (j = 0; j < 2; ++j)
1816                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1817         }
1818
1819         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1820                 /* Vtype returned using a hidden argument */
1821                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1822                 linfo->vret_arg_index = cinfo->vret_arg_index;
1823         }
1824
1825         for (i = 0; i < n; ++i) {
1826                 ainfo = cinfo->args + i;
1827
1828                 if (i >= sig->hasthis)
1829                         t = sig->params [i - sig->hasthis];
1830                 else
1831                         t = &mono_defaults.int_class->byval_arg;
1832
1833                 linfo->args [i].storage = LLVMArgNone;
1834
1835                 switch (ainfo->storage) {
1836                 case ArgInIReg:
1837                         linfo->args [i].storage = LLVMArgInIReg;
1838                         break;
1839                 case ArgInDoubleSSEReg:
1840                 case ArgInFloatSSEReg:
1841                         linfo->args [i].storage = LLVMArgInFPReg;
1842                         break;
1843                 case ArgOnStack:
1844                         if (MONO_TYPE_ISSTRUCT (t)) {
1845                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1846                         } else {
1847                                 linfo->args [i].storage = LLVMArgInIReg;
1848                                 if (!t->byref) {
1849                                         if (t->type == MONO_TYPE_R4)
1850                                                 linfo->args [i].storage = LLVMArgInFPReg;
1851                                         else if (t->type == MONO_TYPE_R8)
1852                                                 linfo->args [i].storage = LLVMArgInFPReg;
1853                                 }
1854                         }
1855                         break;
1856                 case ArgValuetypeInReg:
1857                         if (sig->pinvoke) {
1858                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1859                                 cfg->disable_llvm = TRUE;
1860                                 return linfo;
1861                         }
1862
1863                         linfo->args [i].storage = LLVMArgVtypeInReg;
1864                         for (j = 0; j < 2; ++j)
1865                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1866                         break;
1867                 default:
1868                         cfg->exception_message = g_strdup ("ainfo->storage");
1869                         cfg->disable_llvm = TRUE;
1870                         break;
1871                 }
1872         }
1873
1874         return linfo;
1875 }
1876 #endif
1877
1878 void
1879 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1880 {
1881         MonoInst *arg, *in;
1882         MonoMethodSignature *sig;
1883         int i, n, stack_size;
1884         CallInfo *cinfo;
1885         ArgInfo *ainfo;
1886
1887         stack_size = 0;
1888
1889         sig = call->signature;
1890         n = sig->param_count + sig->hasthis;
1891
1892         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1893
1894         if (COMPILE_LLVM (cfg)) {
1895                 /* We shouldn't be called in the llvm case */
1896                 cfg->disable_llvm = TRUE;
1897                 return;
1898         }
1899
1900         if (cinfo->need_stack_align) {
1901                 if (!cfg->arch.no_pushes)
1902                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1903         }
1904
1905         /*
1906          * Emit all arguments which are passed on the stack to prevent register
1907          * allocation problems.
1908          */
1909         if (cfg->arch.no_pushes) {
1910                 for (i = 0; i < n; ++i) {
1911                         MonoType *t;
1912                         ainfo = cinfo->args + i;
1913
1914                         in = call->args [i];
1915
1916                         if (sig->hasthis && i == 0)
1917                                 t = &mono_defaults.object_class->byval_arg;
1918                         else
1919                                 t = sig->params [i - sig->hasthis];
1920
1921                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1922                                 if (!t->byref) {
1923                                         if (t->type == MONO_TYPE_R4)
1924                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1925                                         else if (t->type == MONO_TYPE_R8)
1926                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1927                                         else
1928                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1929                                 } else {
1930                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1931                                 }
1932                         }
1933                 }
1934         }
1935
1936         /*
1937          * Emit all parameters passed in registers in non-reverse order for better readability
1938          * and to help the optimization in emit_prolog ().
1939          */
1940         for (i = 0; i < n; ++i) {
1941                 ainfo = cinfo->args + i;
1942
1943                 in = call->args [i];
1944
1945                 if (ainfo->storage == ArgInIReg)
1946                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1947         }
1948
1949         for (i = n - 1; i >= 0; --i) {
1950                 ainfo = cinfo->args + i;
1951
1952                 in = call->args [i];
1953
1954                 switch (ainfo->storage) {
1955                 case ArgInIReg:
1956                         /* Already done */
1957                         break;
1958                 case ArgInFloatSSEReg:
1959                 case ArgInDoubleSSEReg:
1960                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1961                         break;
1962                 case ArgOnStack:
1963                 case ArgValuetypeInReg:
1964                 case ArgValuetypeAddrInIReg:
1965                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1966                                 MonoInst *call_inst = (MonoInst*)call;
1967                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1968                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1969                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1970                                 guint32 align;
1971                                 guint32 size;
1972
1973                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1974                                         size = sizeof (MonoTypedRef);
1975                                         align = sizeof (gpointer);
1976                                 }
1977                                 else {
1978                                         if (sig->pinvoke)
1979                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1980                                         else {
1981                                                 /*
1982                                                  * Other backends use mono_type_stack_size (), but that
1983                                                  * aligns the size to 8, which is larger than the size of
1984                                                  * the source, leading to reads of invalid memory if the
1985                                                  * source is at the end of address space.
1986                                                  */
1987                                                 size = mono_class_value_size (in->klass, &align);
1988                                         }
1989                                 }
1990                                 g_assert (in->klass);
1991
1992                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
1993                                         /* Avoid asserts in emit_memcpy () */
1994                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1995                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
1996                                         /* Continue normally */
1997                                 }
1998
1999                                 if (size > 0) {
2000                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2001                                         arg->sreg1 = in->dreg;
2002                                         arg->klass = in->klass;
2003                                         arg->backend.size = size;
2004                                         arg->inst_p0 = call;
2005                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2006                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2007
2008                                         MONO_ADD_INS (cfg->cbb, arg);
2009                                 }
2010                         } else {
2011                                 if (cfg->arch.no_pushes) {
2012                                         /* Already done */
2013                                 } else {
2014                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2015                                         arg->sreg1 = in->dreg;
2016                                         if (!sig->params [i - sig->hasthis]->byref) {
2017                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2018                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2019                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2020                                                         arg->inst_destbasereg = X86_ESP;
2021                                                         arg->inst_offset = 0;
2022                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2023                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2024                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2025                                                         arg->inst_destbasereg = X86_ESP;
2026                                                         arg->inst_offset = 0;
2027                                                 }
2028                                         }
2029                                         MONO_ADD_INS (cfg->cbb, arg);
2030                                 }
2031                         }
2032                         break;
2033                 default:
2034                         g_assert_not_reached ();
2035                 }
2036
2037                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2038                         /* Emit the signature cookie just before the implicit arguments */
2039                         emit_sig_cookie (cfg, call, cinfo);
2040         }
2041
2042         /* Handle the case where there are no implicit arguments */
2043         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2044                 emit_sig_cookie (cfg, call, cinfo);
2045
2046         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2047                 MonoInst *vtarg;
2048
2049                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2050                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2051                                 /*
2052                                  * Tell the JIT to use a more efficient calling convention: call using
2053                                  * OP_CALL, compute the result location after the call, and save the
2054                                  * result there.
2055                                  */
2056                                 call->vret_in_reg = TRUE;
2057                                 /*
2058                                  * Nullify the instruction computing the vret addr to enable
2059                                  * future optimizations.
2060                                  */
2061                                 if (call->vret_var)
2062                                         NULLIFY_INS (call->vret_var);
2063                         } else {
2064                                 if (call->tail_call)
2065                                         NOT_IMPLEMENTED;
2066                                 /*
2067                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2068                                  * the stack. Push the address here, so the call instruction can
2069                                  * access it.
2070                                  */
2071                                 if (!cfg->arch.vret_addr_loc) {
2072                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2073                                         /* Prevent it from being register allocated or optimized away */
2074                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2075                                 }
2076
2077                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2078                         }
2079                 }
2080                 else {
2081                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2082                         vtarg->sreg1 = call->vret_var->dreg;
2083                         vtarg->dreg = mono_alloc_preg (cfg);
2084                         MONO_ADD_INS (cfg->cbb, vtarg);
2085
2086                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2087                 }
2088         }
2089
2090 #ifdef HOST_WIN32
2091         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2092                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2093         }
2094 #endif
2095
2096         if (cfg->method->save_lmf) {
2097                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2098                 MONO_ADD_INS (cfg->cbb, arg);
2099         }
2100
2101         call->stack_usage = cinfo->stack_usage;
2102 }
2103
2104 void
2105 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2106 {
2107         MonoInst *arg;
2108         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2109         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2110         int size = ins->backend.size;
2111
2112         if (ainfo->storage == ArgValuetypeInReg) {
2113                 MonoInst *load;
2114                 int part;
2115
2116                 for (part = 0; part < 2; ++part) {
2117                         if (ainfo->pair_storage [part] == ArgNone)
2118                                 continue;
2119
2120                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2121                         load->inst_basereg = src->dreg;
2122                         load->inst_offset = part * sizeof (gpointer);
2123
2124                         switch (ainfo->pair_storage [part]) {
2125                         case ArgInIReg:
2126                                 load->dreg = mono_alloc_ireg (cfg);
2127                                 break;
2128                         case ArgInDoubleSSEReg:
2129                         case ArgInFloatSSEReg:
2130                                 load->dreg = mono_alloc_freg (cfg);
2131                                 break;
2132                         default:
2133                                 g_assert_not_reached ();
2134                         }
2135                         MONO_ADD_INS (cfg->cbb, load);
2136
2137                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2138                 }
2139         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2140                 MonoInst *vtaddr, *load;
2141                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2142
2143                 g_assert (!cfg->arch.no_pushes);
2144
2145                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2146                 load->inst_p0 = vtaddr;
2147                 vtaddr->flags |= MONO_INST_INDIRECT;
2148                 load->type = STACK_MP;
2149                 load->klass = vtaddr->klass;
2150                 load->dreg = mono_alloc_ireg (cfg);
2151                 MONO_ADD_INS (cfg->cbb, load);
2152                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2153
2154                 if (ainfo->pair_storage [0] == ArgInIReg) {
2155                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2156                         arg->dreg = mono_alloc_ireg (cfg);
2157                         arg->sreg1 = load->dreg;
2158                         arg->inst_imm = 0;
2159                         MONO_ADD_INS (cfg->cbb, arg);
2160                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2161                 } else {
2162                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2163                         arg->sreg1 = load->dreg;
2164                         MONO_ADD_INS (cfg->cbb, arg);
2165                 }
2166         } else {
2167                 if (size == 8) {
2168                         if (cfg->arch.no_pushes) {
2169                                 int dreg = mono_alloc_ireg (cfg);
2170
2171                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2172                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2173                         } else {
2174                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2175                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2176                                 arg->inst_basereg = src->dreg;
2177                                 arg->inst_offset = 0;
2178                                 MONO_ADD_INS (cfg->cbb, arg);
2179                         }
2180                 } else if (size <= 40) {
2181                         if (cfg->arch.no_pushes) {
2182                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2183                         } else {
2184                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2185                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2186                         }
2187                 } else {
2188                         if (cfg->arch.no_pushes) {
2189                                 // FIXME: Code growth
2190                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2191                         } else {
2192                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2193                                 arg->inst_basereg = src->dreg;
2194                                 arg->inst_offset = 0;
2195                                 arg->inst_imm = size;
2196                                 MONO_ADD_INS (cfg->cbb, arg);
2197                         }
2198                 }
2199         }
2200 }
2201
2202 void
2203 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2204 {
2205         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2206
2207         if (ret->type == MONO_TYPE_R4) {
2208                 if (COMPILE_LLVM (cfg))
2209                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2210                 else
2211                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2212                 return;
2213         } else if (ret->type == MONO_TYPE_R8) {
2214                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2215                 return;
2216         }
2217
2218         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2219 }
2220
2221 #endif /* DISABLE_JIT */
2222
2223 #define EMIT_COND_BRANCH(ins,cond,sign) \
2224         if (ins->inst_true_bb->native_offset) { \
2225                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2226         } else { \
2227                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2228                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2229             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2230                         x86_branch8 (code, cond, 0, sign); \
2231                 else \
2232                         x86_branch32 (code, cond, 0, sign); \
2233 }
2234
2235 typedef struct {
2236         MonoMethodSignature *sig;
2237         CallInfo *cinfo;
2238 } ArchDynCallInfo;
2239
2240 typedef struct {
2241         mgreg_t regs [PARAM_REGS];
2242         mgreg_t res;
2243         guint8 *ret;
2244 } DynCallArgs;
2245
2246 static gboolean
2247 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2248 {
2249         int i;
2250
2251 #ifdef HOST_WIN32
2252         return FALSE;
2253 #endif
2254
2255         switch (cinfo->ret.storage) {
2256         case ArgNone:
2257         case ArgInIReg:
2258                 break;
2259         case ArgValuetypeInReg: {
2260                 ArgInfo *ainfo = &cinfo->ret;
2261
2262                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2263                         return FALSE;
2264                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2265                         return FALSE;
2266                 break;
2267         }
2268         default:
2269                 return FALSE;
2270         }
2271
2272         for (i = 0; i < cinfo->nargs; ++i) {
2273                 ArgInfo *ainfo = &cinfo->args [i];
2274                 switch (ainfo->storage) {
2275                 case ArgInIReg:
2276                         break;
2277                 case ArgValuetypeInReg:
2278                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2279                                 return FALSE;
2280                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2281                                 return FALSE;
2282                         break;
2283                 default:
2284                         return FALSE;
2285                 }
2286         }
2287
2288         return TRUE;
2289 }
2290
2291 /*
2292  * mono_arch_dyn_call_prepare:
2293  *
2294  *   Return a pointer to an arch-specific structure which contains information
2295  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2296  * supported for SIG.
2297  * This function is equivalent to ffi_prep_cif in libffi.
2298  */
2299 MonoDynCallInfo*
2300 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2301 {
2302         ArchDynCallInfo *info;
2303         CallInfo *cinfo;
2304
2305         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2306
2307         if (!dyn_call_supported (sig, cinfo)) {
2308                 g_free (cinfo);
2309                 return NULL;
2310         }
2311
2312         info = g_new0 (ArchDynCallInfo, 1);
2313         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2314         info->sig = sig;
2315         info->cinfo = cinfo;
2316
2317         return (MonoDynCallInfo*)info;
2318 }
2319
2320 /*
2321  * mono_arch_dyn_call_free:
2322  *
2323  *   Free a MonoDynCallInfo structure.
2324  */
2325 void
2326 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2327 {
2328         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2329
2330         g_free (ainfo->cinfo);
2331         g_free (ainfo);
2332 }
2333
2334 /*
2335  * mono_arch_get_start_dyn_call:
2336  *
2337  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2338  * store the result into BUF.
2339  * ARGS should be an array of pointers pointing to the arguments.
2340  * RET should point to a memory buffer large enought to hold the result of the
2341  * call.
2342  * This function should be as fast as possible, any work which does not depend
2343  * on the actual values of the arguments should be done in
2344  * mono_arch_dyn_call_prepare ().
2345  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2346  * libffi.
2347  */
2348 void
2349 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2350 {
2351         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2352         DynCallArgs *p = (DynCallArgs*)buf;
2353         int arg_index, greg, i, pindex;
2354         MonoMethodSignature *sig = dinfo->sig;
2355
2356         g_assert (buf_len >= sizeof (DynCallArgs));
2357
2358         p->res = 0;
2359         p->ret = ret;
2360
2361         arg_index = 0;
2362         greg = 0;
2363         pindex = 0;
2364
2365         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2366                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2367                 if (!sig->hasthis)
2368                         pindex = 1;
2369         }
2370
2371         if (dinfo->cinfo->vtype_retaddr)
2372                 p->regs [greg ++] = (mgreg_t)ret;
2373
2374         for (i = pindex; i < sig->param_count; i++) {
2375                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2376                 gpointer *arg = args [arg_index ++];
2377
2378                 if (t->byref) {
2379                         p->regs [greg ++] = (mgreg_t)*(arg);
2380                         continue;
2381                 }
2382
2383                 switch (t->type) {
2384                 case MONO_TYPE_STRING:
2385                 case MONO_TYPE_CLASS:
2386                 case MONO_TYPE_ARRAY:
2387                 case MONO_TYPE_SZARRAY:
2388                 case MONO_TYPE_OBJECT:
2389                 case MONO_TYPE_PTR:
2390                 case MONO_TYPE_I:
2391                 case MONO_TYPE_U:
2392                 case MONO_TYPE_I8:
2393                 case MONO_TYPE_U8:
2394                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2395                         p->regs [greg ++] = (mgreg_t)*(arg);
2396                         break;
2397                 case MONO_TYPE_BOOLEAN:
2398                 case MONO_TYPE_U1:
2399                         p->regs [greg ++] = *(guint8*)(arg);
2400                         break;
2401                 case MONO_TYPE_I1:
2402                         p->regs [greg ++] = *(gint8*)(arg);
2403                         break;
2404                 case MONO_TYPE_I2:
2405                         p->regs [greg ++] = *(gint16*)(arg);
2406                         break;
2407                 case MONO_TYPE_U2:
2408                 case MONO_TYPE_CHAR:
2409                         p->regs [greg ++] = *(guint16*)(arg);
2410                         break;
2411                 case MONO_TYPE_I4:
2412                         p->regs [greg ++] = *(gint32*)(arg);
2413                         break;
2414                 case MONO_TYPE_U4:
2415                         p->regs [greg ++] = *(guint32*)(arg);
2416                         break;
2417                 case MONO_TYPE_GENERICINST:
2418                     if (MONO_TYPE_IS_REFERENCE (t)) {
2419                                 p->regs [greg ++] = (mgreg_t)*(arg);
2420                                 break;
2421                         } else {
2422                                 /* Fall through */
2423                         }
2424                 case MONO_TYPE_VALUETYPE: {
2425                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2426
2427                         g_assert (ainfo->storage == ArgValuetypeInReg);
2428                         if (ainfo->pair_storage [0] != ArgNone) {
2429                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2430                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2431                         }
2432                         if (ainfo->pair_storage [1] != ArgNone) {
2433                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2434                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2435                         }
2436                         break;
2437                 }
2438                 default:
2439                         g_assert_not_reached ();
2440                 }
2441         }
2442
2443         g_assert (greg <= PARAM_REGS);
2444 }
2445
2446 /*
2447  * mono_arch_finish_dyn_call:
2448  *
2449  *   Store the result of a dyn call into the return value buffer passed to
2450  * start_dyn_call ().
2451  * This function should be as fast as possible, any work which does not depend
2452  * on the actual values of the arguments should be done in
2453  * mono_arch_dyn_call_prepare ().
2454  */
2455 void
2456 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2457 {
2458         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2459         MonoMethodSignature *sig = dinfo->sig;
2460         guint8 *ret = ((DynCallArgs*)buf)->ret;
2461         mgreg_t res = ((DynCallArgs*)buf)->res;
2462
2463         switch (mono_type_get_underlying_type (sig->ret)->type) {
2464         case MONO_TYPE_VOID:
2465                 *(gpointer*)ret = NULL;
2466                 break;
2467         case MONO_TYPE_STRING:
2468         case MONO_TYPE_CLASS:
2469         case MONO_TYPE_ARRAY:
2470         case MONO_TYPE_SZARRAY:
2471         case MONO_TYPE_OBJECT:
2472         case MONO_TYPE_I:
2473         case MONO_TYPE_U:
2474         case MONO_TYPE_PTR:
2475                 *(gpointer*)ret = (gpointer)res;
2476                 break;
2477         case MONO_TYPE_I1:
2478                 *(gint8*)ret = res;
2479                 break;
2480         case MONO_TYPE_U1:
2481         case MONO_TYPE_BOOLEAN:
2482                 *(guint8*)ret = res;
2483                 break;
2484         case MONO_TYPE_I2:
2485                 *(gint16*)ret = res;
2486                 break;
2487         case MONO_TYPE_U2:
2488         case MONO_TYPE_CHAR:
2489                 *(guint16*)ret = res;
2490                 break;
2491         case MONO_TYPE_I4:
2492                 *(gint32*)ret = res;
2493                 break;
2494         case MONO_TYPE_U4:
2495                 *(guint32*)ret = res;
2496                 break;
2497         case MONO_TYPE_I8:
2498                 *(gint64*)ret = res;
2499                 break;
2500         case MONO_TYPE_U8:
2501                 *(guint64*)ret = res;
2502                 break;
2503         case MONO_TYPE_GENERICINST:
2504                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2505                         *(gpointer*)ret = (gpointer)res;
2506                         break;
2507                 } else {
2508                         /* Fall through */
2509                 }
2510         case MONO_TYPE_VALUETYPE:
2511                 if (dinfo->cinfo->vtype_retaddr) {
2512                         /* Nothing to do */
2513                 } else {
2514                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2515
2516                         g_assert (ainfo->storage == ArgValuetypeInReg);
2517
2518                         if (ainfo->pair_storage [0] != ArgNone) {
2519                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2520                                 ((mgreg_t*)ret)[0] = res;
2521                         }
2522
2523                         g_assert (ainfo->pair_storage [1] == ArgNone);
2524                 }
2525                 break;
2526         default:
2527                 g_assert_not_reached ();
2528         }
2529 }
2530
2531 /* emit an exception if condition is fail */
2532 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2533         do {                                                        \
2534                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2535                 if (tins == NULL) {                                                                             \
2536                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2537                                         MONO_PATCH_INFO_EXC, exc_name);  \
2538                         x86_branch32 (code, cond, 0, signed);               \
2539                 } else {        \
2540                         EMIT_COND_BRANCH (tins, cond, signed);  \
2541                 }                       \
2542         } while (0);
2543
2544 #define EMIT_FPCOMPARE(code) do { \
2545         amd64_fcompp (code); \
2546         amd64_fnstsw (code); \
2547 } while (0);
2548
2549 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2550     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2551         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2552         amd64_ ##op (code); \
2553         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2554         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2555 } while (0);
2556
2557 static guint8*
2558 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2559 {
2560         gboolean no_patch = FALSE;
2561
2562         /*
2563          * FIXME: Add support for thunks
2564          */
2565         {
2566                 gboolean near_call = FALSE;
2567
2568                 /*
2569                  * Indirect calls are expensive so try to make a near call if possible.
2570                  * The caller memory is allocated by the code manager so it is
2571                  * guaranteed to be at a 32 bit offset.
2572                  */
2573
2574                 if (patch_type != MONO_PATCH_INFO_ABS) {
2575                         /* The target is in memory allocated using the code manager */
2576                         near_call = TRUE;
2577
2578                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2579                                 if (((MonoMethod*)data)->klass->image->aot_module)
2580                                         /* The callee might be an AOT method */
2581                                         near_call = FALSE;
2582                                 if (((MonoMethod*)data)->dynamic)
2583                                         /* The target is in malloc-ed memory */
2584                                         near_call = FALSE;
2585                         }
2586
2587                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2588                                 /*
2589                                  * The call might go directly to a native function without
2590                                  * the wrapper.
2591                                  */
2592                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2593                                 if (mi) {
2594                                         gconstpointer target = mono_icall_get_wrapper (mi);
2595                                         if ((((guint64)target) >> 32) != 0)
2596                                                 near_call = FALSE;
2597                                 }
2598                         }
2599                 }
2600                 else {
2601                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2602                                 /*
2603                                  * This is not really an optimization, but required because the
2604                                  * generic class init trampolines use R11 to pass the vtable.
2605                                  */
2606                                 near_call = TRUE;
2607                         } else {
2608                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2609                                 if (info) {
2610                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2611                                                 strstr (cfg->method->name, info->name)) {
2612                                                 /* A call to the wrapped function */
2613                                                 if ((((guint64)data) >> 32) == 0)
2614                                                         near_call = TRUE;
2615                                                 no_patch = TRUE;
2616                                         }
2617                                         else if (info->func == info->wrapper) {
2618                                                 /* No wrapper */
2619                                                 if ((((guint64)info->func) >> 32) == 0)
2620                                                         near_call = TRUE;
2621                                         }
2622                                         else {
2623                                                 /* See the comment in mono_codegen () */
2624                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2625                                                         near_call = TRUE;
2626                                         }
2627                                 }
2628                                 else if ((((guint64)data) >> 32) == 0) {
2629                                         near_call = TRUE;
2630                                         no_patch = TRUE;
2631                                 }
2632                         }
2633                 }
2634
2635                 if (cfg->method->dynamic)
2636                         /* These methods are allocated using malloc */
2637                         near_call = FALSE;
2638
2639 #ifdef MONO_ARCH_NOMAP32BIT
2640                 near_call = FALSE;
2641 #endif
2642
2643                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2644                 if (optimize_for_xen)
2645                         near_call = FALSE;
2646
2647                 if (cfg->compile_aot) {
2648                         near_call = TRUE;
2649                         no_patch = TRUE;
2650                 }
2651
2652                 if (near_call) {
2653                         /*
2654                          * Align the call displacement to an address divisible by 4 so it does
2655                          * not span cache lines. This is required for code patching to work on SMP
2656                          * systems.
2657                          */
2658                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2659                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2660                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2661                         amd64_call_code (code, 0);
2662                 }
2663                 else {
2664                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2665                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2666                         amd64_call_reg (code, GP_SCRATCH_REG);
2667                 }
2668         }
2669
2670         return code;
2671 }
2672
2673 static inline guint8*
2674 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2675 {
2676 #ifdef HOST_WIN32
2677         if (win64_adjust_stack)
2678                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2679 #endif
2680         code = emit_call_body (cfg, code, patch_type, data);
2681 #ifdef HOST_WIN32
2682         if (win64_adjust_stack)
2683                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2684 #endif
2685
2686         return code;
2687 }
2688
2689 static inline int
2690 store_membase_imm_to_store_membase_reg (int opcode)
2691 {
2692         switch (opcode) {
2693         case OP_STORE_MEMBASE_IMM:
2694                 return OP_STORE_MEMBASE_REG;
2695         case OP_STOREI4_MEMBASE_IMM:
2696                 return OP_STOREI4_MEMBASE_REG;
2697         case OP_STOREI8_MEMBASE_IMM:
2698                 return OP_STOREI8_MEMBASE_REG;
2699         }
2700
2701         return -1;
2702 }
2703
2704 #ifndef DISABLE_JIT
2705
2706 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2707
2708 /*
2709  * mono_arch_peephole_pass_1:
2710  *
2711  *   Perform peephole opts which should/can be performed before local regalloc
2712  */
2713 void
2714 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2715 {
2716         MonoInst *ins, *n;
2717
2718         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2719                 MonoInst *last_ins = ins->prev;
2720
2721                 switch (ins->opcode) {
2722                 case OP_ADD_IMM:
2723                 case OP_IADD_IMM:
2724                 case OP_LADD_IMM:
2725                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2726                                 /*
2727                                  * X86_LEA is like ADD, but doesn't have the
2728                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2729                                  * its operand to 64 bit.
2730                                  */
2731                                 ins->opcode = OP_X86_LEA_MEMBASE;
2732                                 ins->inst_basereg = ins->sreg1;
2733                         }
2734                         break;
2735                 case OP_LXOR:
2736                 case OP_IXOR:
2737                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2738                                 MonoInst *ins2;
2739
2740                                 /*
2741                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2742                                  * the latter has length 2-3 instead of 6 (reverse constant
2743                                  * propagation). These instruction sequences are very common
2744                                  * in the initlocals bblock.
2745                                  */
2746                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2747                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2748                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2749                                                 ins2->sreg1 = ins->dreg;
2750                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2751                                                 /* Continue */
2752                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2753                                                 NULLIFY_INS (ins2);
2754                                                 /* Continue */
2755                                         } else {
2756                                                 break;
2757                                         }
2758                                 }
2759                         }
2760                         break;
2761                 case OP_COMPARE_IMM:
2762                 case OP_LCOMPARE_IMM:
2763                         /* OP_COMPARE_IMM (reg, 0)
2764                          * -->
2765                          * OP_AMD64_TEST_NULL (reg)
2766                          */
2767                         if (!ins->inst_imm)
2768                                 ins->opcode = OP_AMD64_TEST_NULL;
2769                         break;
2770                 case OP_ICOMPARE_IMM:
2771                         if (!ins->inst_imm)
2772                                 ins->opcode = OP_X86_TEST_NULL;
2773                         break;
2774                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2775                         /*
2776                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2777                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2778                          * -->
2779                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2780                          * OP_COMPARE_IMM reg, imm
2781                          *
2782                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2783                          */
2784                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2785                             ins->inst_basereg == last_ins->inst_destbasereg &&
2786                             ins->inst_offset == last_ins->inst_offset) {
2787                                         ins->opcode = OP_ICOMPARE_IMM;
2788                                         ins->sreg1 = last_ins->sreg1;
2789
2790                                         /* check if we can remove cmp reg,0 with test null */
2791                                         if (!ins->inst_imm)
2792                                                 ins->opcode = OP_X86_TEST_NULL;
2793                                 }
2794
2795                         break;
2796                 }
2797
2798                 mono_peephole_ins (bb, ins);
2799         }
2800 }
2801
2802 void
2803 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2804 {
2805         MonoInst *ins, *n;
2806
2807         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2808                 switch (ins->opcode) {
2809                 case OP_ICONST:
2810                 case OP_I8CONST: {
2811                         /* reg = 0 -> XOR (reg, reg) */
2812                         /* XOR sets cflags on x86, so we cant do it always */
2813                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2814                                 ins->opcode = OP_LXOR;
2815                                 ins->sreg1 = ins->dreg;
2816                                 ins->sreg2 = ins->dreg;
2817                                 /* Fall through */
2818                         } else {
2819                                 break;
2820                         }
2821                 }
2822                 case OP_LXOR:
2823                         /*
2824                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2825                          * 0 result into 64 bits.
2826                          */
2827                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2828                                 ins->opcode = OP_IXOR;
2829                         }
2830                         /* Fall through */
2831                 case OP_IXOR:
2832                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2833                                 MonoInst *ins2;
2834
2835                                 /*
2836                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2837                                  * the latter has length 2-3 instead of 6 (reverse constant
2838                                  * propagation). These instruction sequences are very common
2839                                  * in the initlocals bblock.
2840                                  */
2841                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2842                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2843                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2844                                                 ins2->sreg1 = ins->dreg;
2845                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2846                                                 /* Continue */
2847                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2848                                                 NULLIFY_INS (ins2);
2849                                                 /* Continue */
2850                                         } else {
2851                                                 break;
2852                                         }
2853                                 }
2854                         }
2855                         break;
2856                 case OP_IADD_IMM:
2857                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2858                                 ins->opcode = OP_X86_INC_REG;
2859                         break;
2860                 case OP_ISUB_IMM:
2861                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2862                                 ins->opcode = OP_X86_DEC_REG;
2863                         break;
2864                 }
2865
2866                 mono_peephole_ins (bb, ins);
2867         }
2868 }
2869
2870 #define NEW_INS(cfg,ins,dest,op) do {   \
2871                 MONO_INST_NEW ((cfg), (dest), (op)); \
2872         (dest)->cil_code = (ins)->cil_code; \
2873         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2874         } while (0)
2875
2876 /*
2877  * mono_arch_lowering_pass:
2878  *
2879  *  Converts complex opcodes into simpler ones so that each IR instruction
2880  * corresponds to one machine instruction.
2881  */
2882 void
2883 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2884 {
2885         MonoInst *ins, *n, *temp;
2886
2887         /*
2888          * FIXME: Need to add more instructions, but the current machine
2889          * description can't model some parts of the composite instructions like
2890          * cdq.
2891          */
2892         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2893                 switch (ins->opcode) {
2894                 case OP_DIV_IMM:
2895                 case OP_REM_IMM:
2896                 case OP_IDIV_IMM:
2897                 case OP_IDIV_UN_IMM:
2898                 case OP_IREM_UN_IMM:
2899                         mono_decompose_op_imm (cfg, bb, ins);
2900                         break;
2901                 case OP_IREM_IMM:
2902                         /* Keep the opcode if we can implement it efficiently */
2903                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2904                                 mono_decompose_op_imm (cfg, bb, ins);
2905                         break;
2906                 case OP_COMPARE_IMM:
2907                 case OP_LCOMPARE_IMM:
2908                         if (!amd64_is_imm32 (ins->inst_imm)) {
2909                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2910                                 temp->inst_c0 = ins->inst_imm;
2911                                 temp->dreg = mono_alloc_ireg (cfg);
2912                                 ins->opcode = OP_COMPARE;
2913                                 ins->sreg2 = temp->dreg;
2914                         }
2915                         break;
2916                 case OP_LOAD_MEMBASE:
2917                 case OP_LOADI8_MEMBASE:
2918                         if (!amd64_is_imm32 (ins->inst_offset)) {
2919                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2920                                 temp->inst_c0 = ins->inst_offset;
2921                                 temp->dreg = mono_alloc_ireg (cfg);
2922                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2923                                 ins->inst_indexreg = temp->dreg;
2924                         }
2925                         break;
2926                 case OP_STORE_MEMBASE_IMM:
2927                 case OP_STOREI8_MEMBASE_IMM:
2928                         if (!amd64_is_imm32 (ins->inst_imm)) {
2929                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2930                                 temp->inst_c0 = ins->inst_imm;
2931                                 temp->dreg = mono_alloc_ireg (cfg);
2932                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2933                                 ins->sreg1 = temp->dreg;
2934                         }
2935                         break;
2936 #ifdef MONO_ARCH_SIMD_INTRINSICS
2937                 case OP_EXPAND_I1: {
2938                                 int temp_reg1 = mono_alloc_ireg (cfg);
2939                                 int temp_reg2 = mono_alloc_ireg (cfg);
2940                                 int original_reg = ins->sreg1;
2941
2942                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2943                                 temp->sreg1 = original_reg;
2944                                 temp->dreg = temp_reg1;
2945
2946                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2947                                 temp->sreg1 = temp_reg1;
2948                                 temp->dreg = temp_reg2;
2949                                 temp->inst_imm = 8;
2950
2951                                 NEW_INS (cfg, ins, temp, OP_LOR);
2952                                 temp->sreg1 = temp->dreg = temp_reg2;
2953                                 temp->sreg2 = temp_reg1;
2954
2955                                 ins->opcode = OP_EXPAND_I2;
2956                                 ins->sreg1 = temp_reg2;
2957                         }
2958                         break;
2959 #endif
2960                 default:
2961                         break;
2962                 }
2963         }
2964
2965         bb->max_vreg = cfg->next_vreg;
2966 }
2967
2968 static const int
2969 branch_cc_table [] = {
2970         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2971         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2972         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2973 };
2974
2975 /* Maps CMP_... constants to X86_CC_... constants */
2976 static const int
2977 cc_table [] = {
2978         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2979         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2980 };
2981
2982 static const int
2983 cc_signed_table [] = {
2984         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2985         FALSE, FALSE, FALSE, FALSE
2986 };
2987
2988 /*#include "cprop.c"*/
2989
2990 static unsigned char*
2991 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2992 {
2993         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2994
2995         if (size == 1)
2996                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2997         else if (size == 2)
2998                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2999         return code;
3000 }
3001
3002 static unsigned char*
3003 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3004 {
3005         int sreg = tree->sreg1;
3006         int need_touch = FALSE;
3007
3008 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3009         if (!tree->flags & MONO_INST_INIT)
3010                 need_touch = TRUE;
3011 #endif
3012
3013         if (need_touch) {
3014                 guint8* br[5];
3015
3016                 /*
3017                  * Under Windows:
3018                  * If requested stack size is larger than one page,
3019                  * perform stack-touch operation
3020                  */
3021                 /*
3022                  * Generate stack probe code.
3023                  * Under Windows, it is necessary to allocate one page at a time,
3024                  * "touching" stack after each successful sub-allocation. This is
3025                  * because of the way stack growth is implemented - there is a
3026                  * guard page before the lowest stack page that is currently commited.
3027                  * Stack normally grows sequentially so OS traps access to the
3028                  * guard page and commits more pages when needed.
3029                  */
3030                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3031                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3032
3033                 br[2] = code; /* loop */
3034                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3035                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3036                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3037                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3038                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3039                 amd64_patch (br[3], br[2]);
3040                 amd64_test_reg_reg (code, sreg, sreg);
3041                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3042                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3043
3044                 br[1] = code; x86_jump8 (code, 0);
3045
3046                 amd64_patch (br[0], code);
3047                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3048                 amd64_patch (br[1], code);
3049                 amd64_patch (br[4], code);
3050         }
3051         else
3052                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3053
3054         if (tree->flags & MONO_INST_INIT) {
3055                 int offset = 0;
3056                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3057                         amd64_push_reg (code, AMD64_RAX);
3058                         offset += 8;
3059                 }
3060                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3061                         amd64_push_reg (code, AMD64_RCX);
3062                         offset += 8;
3063                 }
3064                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3065                         amd64_push_reg (code, AMD64_RDI);
3066                         offset += 8;
3067                 }
3068
3069                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3070                 if (sreg != AMD64_RCX)
3071                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3072                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3073
3074                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3075                 if (cfg->param_area && cfg->arch.no_pushes)
3076                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3077                 amd64_cld (code);
3078                 amd64_prefix (code, X86_REP_PREFIX);
3079                 amd64_stosl (code);
3080
3081                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3082                         amd64_pop_reg (code, AMD64_RDI);
3083                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3084                         amd64_pop_reg (code, AMD64_RCX);
3085                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3086                         amd64_pop_reg (code, AMD64_RAX);
3087         }
3088         return code;
3089 }
3090
3091 static guint8*
3092 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3093 {
3094         CallInfo *cinfo;
3095         guint32 quad;
3096
3097         /* Move return value to the target register */
3098         /* FIXME: do this in the local reg allocator */
3099         switch (ins->opcode) {
3100         case OP_CALL:
3101         case OP_CALL_REG:
3102         case OP_CALL_MEMBASE:
3103         case OP_LCALL:
3104         case OP_LCALL_REG:
3105         case OP_LCALL_MEMBASE:
3106                 g_assert (ins->dreg == AMD64_RAX);
3107                 break;
3108         case OP_FCALL:
3109         case OP_FCALL_REG:
3110         case OP_FCALL_MEMBASE:
3111                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3112                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3113                 }
3114                 else {
3115                         if (ins->dreg != AMD64_XMM0)
3116                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3117                 }
3118                 break;
3119         case OP_VCALL:
3120         case OP_VCALL_REG:
3121         case OP_VCALL_MEMBASE:
3122         case OP_VCALL2:
3123         case OP_VCALL2_REG:
3124         case OP_VCALL2_MEMBASE:
3125                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3126                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3127                         MonoInst *loc = cfg->arch.vret_addr_loc;
3128
3129                         /* Load the destination address */
3130                         g_assert (loc->opcode == OP_REGOFFSET);
3131                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3132
3133                         for (quad = 0; quad < 2; quad ++) {
3134                                 switch (cinfo->ret.pair_storage [quad]) {
3135                                 case ArgInIReg:
3136                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3137                                         break;
3138                                 case ArgInFloatSSEReg:
3139                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3140                                         break;
3141                                 case ArgInDoubleSSEReg:
3142                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3143                                         break;
3144                                 case ArgNone:
3145                                         break;
3146                                 default:
3147                                         NOT_IMPLEMENTED;
3148                                 }
3149                         }
3150                 }
3151                 break;
3152         }
3153
3154         return code;
3155 }
3156
3157 #endif /* DISABLE_JIT */
3158
3159 /*
3160  * mono_amd64_emit_tls_get:
3161  * @code: buffer to store code to
3162  * @dreg: hard register where to place the result
3163  * @tls_offset: offset info
3164  *
3165  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3166  * the dreg register the item in the thread local storage identified
3167  * by tls_offset.
3168  *
3169  * Returns: a pointer to the end of the stored code
3170  */
3171 guint8*
3172 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3173 {
3174 #ifdef HOST_WIN32
3175         g_assert (tls_offset < 64);
3176         x86_prefix (code, X86_GS_PREFIX);
3177         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3178 #else
3179         if (optimize_for_xen) {
3180                 x86_prefix (code, X86_FS_PREFIX);
3181                 amd64_mov_reg_mem (code, dreg, 0, 8);
3182                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3183         } else {
3184                 x86_prefix (code, X86_FS_PREFIX);
3185                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3186         }
3187 #endif
3188         return code;
3189 }
3190
3191 #define REAL_PRINT_REG(text,reg) \
3192 mono_assert (reg >= 0); \
3193 amd64_push_reg (code, AMD64_RAX); \
3194 amd64_push_reg (code, AMD64_RDX); \
3195 amd64_push_reg (code, AMD64_RCX); \
3196 amd64_push_reg (code, reg); \
3197 amd64_push_imm (code, reg); \
3198 amd64_push_imm (code, text " %d %p\n"); \
3199 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3200 amd64_call_reg (code, AMD64_RAX); \
3201 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3202 amd64_pop_reg (code, AMD64_RCX); \
3203 amd64_pop_reg (code, AMD64_RDX); \
3204 amd64_pop_reg (code, AMD64_RAX);
3205
3206 /* benchmark and set based on cpu */
3207 #define LOOP_ALIGNMENT 8
3208 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3209
3210 #ifndef DISABLE_JIT
3211
3212 void
3213 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3214 {
3215         MonoInst *ins;
3216         MonoCallInst *call;
3217         guint offset;
3218         guint8 *code = cfg->native_code + cfg->code_len;
3219         MonoInst *last_ins = NULL;
3220         guint last_offset = 0;
3221         int max_len;
3222
3223         /* Fix max_offset estimate for each successor bb */
3224         if (cfg->opt & MONO_OPT_BRANCH) {
3225                 int current_offset = cfg->code_len;
3226                 MonoBasicBlock *current_bb;
3227                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3228                         current_bb->max_offset = current_offset;
3229                         current_offset += current_bb->max_length;
3230                 }
3231         }
3232
3233         if (cfg->opt & MONO_OPT_LOOP) {
3234                 int pad, align = LOOP_ALIGNMENT;
3235                 /* set alignment depending on cpu */
3236                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3237                         pad = align - pad;
3238                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3239                         amd64_padding (code, pad);
3240                         cfg->code_len += pad;
3241                         bb->native_offset = cfg->code_len;
3242                 }
3243         }
3244
3245         if (cfg->verbose_level > 2)
3246                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3247
3248         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3249                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3250                 g_assert (!cfg->compile_aot);
3251
3252                 cov->data [bb->dfn].cil_code = bb->cil_code;
3253                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3254                 /* this is not thread save, but good enough */
3255                 amd64_inc_membase (code, AMD64_R11, 0);
3256         }
3257
3258         offset = code - cfg->native_code;
3259
3260         mono_debug_open_block (cfg, bb, offset);
3261
3262     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3263                 x86_breakpoint (code);
3264
3265         MONO_BB_FOR_EACH_INS (bb, ins) {
3266                 offset = code - cfg->native_code;
3267
3268                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3269
3270                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3271                         cfg->code_size *= 2;
3272                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3273                         code = cfg->native_code + offset;
3274                         mono_jit_stats.code_reallocs++;
3275                 }
3276
3277                 if (cfg->debug_info)
3278                         mono_debug_record_line_number (cfg, ins, offset);
3279
3280                 switch (ins->opcode) {
3281                 case OP_BIGMUL:
3282                         amd64_mul_reg (code, ins->sreg2, TRUE);
3283                         break;
3284                 case OP_BIGMUL_UN:
3285                         amd64_mul_reg (code, ins->sreg2, FALSE);
3286                         break;
3287                 case OP_X86_SETEQ_MEMBASE:
3288                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3289                         break;
3290                 case OP_STOREI1_MEMBASE_IMM:
3291                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3292                         break;
3293                 case OP_STOREI2_MEMBASE_IMM:
3294                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3295                         break;
3296                 case OP_STOREI4_MEMBASE_IMM:
3297                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3298                         break;
3299                 case OP_STOREI1_MEMBASE_REG:
3300                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3301                         break;
3302                 case OP_STOREI2_MEMBASE_REG:
3303                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3304                         break;
3305                 case OP_STORE_MEMBASE_REG:
3306                 case OP_STOREI8_MEMBASE_REG:
3307                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3308                         break;
3309                 case OP_STOREI4_MEMBASE_REG:
3310                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3311                         break;
3312                 case OP_STORE_MEMBASE_IMM:
3313                 case OP_STOREI8_MEMBASE_IMM:
3314                         g_assert (amd64_is_imm32 (ins->inst_imm));
3315                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3316                         break;
3317                 case OP_LOAD_MEM:
3318                 case OP_LOADI8_MEM:
3319                         // FIXME: Decompose this earlier
3320                         if (amd64_is_imm32 (ins->inst_imm))
3321                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3322                         else {
3323                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3324                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3325                         }
3326                         break;
3327                 case OP_LOADI4_MEM:
3328                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3329                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3330                         break;
3331                 case OP_LOADU4_MEM:
3332                         // FIXME: Decompose this earlier
3333                         if (amd64_is_imm32 (ins->inst_imm))
3334                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3335                         else {
3336                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3337                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3338                         }
3339                         break;
3340                 case OP_LOADU1_MEM:
3341                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3342                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3343                         break;
3344                 case OP_LOADU2_MEM:
3345                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3346                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3347                         break;
3348                 case OP_LOAD_MEMBASE:
3349                 case OP_LOADI8_MEMBASE:
3350                         g_assert (amd64_is_imm32 (ins->inst_offset));
3351                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3352                         break;
3353                 case OP_LOADI4_MEMBASE:
3354                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3355                         break;
3356                 case OP_LOADU4_MEMBASE:
3357                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3358                         break;
3359                 case OP_LOADU1_MEMBASE:
3360                         /* The cpu zero extends the result into 64 bits */
3361                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3362                         break;
3363                 case OP_LOADI1_MEMBASE:
3364                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3365                         break;
3366                 case OP_LOADU2_MEMBASE:
3367                         /* The cpu zero extends the result into 64 bits */
3368                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3369                         break;
3370                 case OP_LOADI2_MEMBASE:
3371                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3372                         break;
3373                 case OP_AMD64_LOADI8_MEMINDEX:
3374                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3375                         break;
3376                 case OP_LCONV_TO_I1:
3377                 case OP_ICONV_TO_I1:
3378                 case OP_SEXT_I1:
3379                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3380                         break;
3381                 case OP_LCONV_TO_I2:
3382                 case OP_ICONV_TO_I2:
3383                 case OP_SEXT_I2:
3384                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3385                         break;
3386                 case OP_LCONV_TO_U1:
3387                 case OP_ICONV_TO_U1:
3388                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3389                         break;
3390                 case OP_LCONV_TO_U2:
3391                 case OP_ICONV_TO_U2:
3392                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3393                         break;
3394                 case OP_ZEXT_I4:
3395                         /* Clean out the upper word */
3396                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3397                         break;
3398                 case OP_SEXT_I4:
3399                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3400                         break;
3401                 case OP_COMPARE:
3402                 case OP_LCOMPARE:
3403                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3404                         break;
3405                 case OP_COMPARE_IMM:
3406                 case OP_LCOMPARE_IMM:
3407                         g_assert (amd64_is_imm32 (ins->inst_imm));
3408                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3409                         break;
3410                 case OP_X86_COMPARE_REG_MEMBASE:
3411                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3412                         break;
3413                 case OP_X86_TEST_NULL:
3414                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3415                         break;
3416                 case OP_AMD64_TEST_NULL:
3417                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3418                         break;
3419
3420                 case OP_X86_ADD_REG_MEMBASE:
3421                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3422                         break;
3423                 case OP_X86_SUB_REG_MEMBASE:
3424                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3425                         break;
3426                 case OP_X86_AND_REG_MEMBASE:
3427                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3428                         break;
3429                 case OP_X86_OR_REG_MEMBASE:
3430                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3431                         break;
3432                 case OP_X86_XOR_REG_MEMBASE:
3433                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3434                         break;
3435
3436                 case OP_X86_ADD_MEMBASE_IMM:
3437                         /* FIXME: Make a 64 version too */
3438                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3439                         break;
3440                 case OP_X86_SUB_MEMBASE_IMM:
3441                         g_assert (amd64_is_imm32 (ins->inst_imm));
3442                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3443                         break;
3444                 case OP_X86_AND_MEMBASE_IMM:
3445                         g_assert (amd64_is_imm32 (ins->inst_imm));
3446                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3447                         break;
3448                 case OP_X86_OR_MEMBASE_IMM:
3449                         g_assert (amd64_is_imm32 (ins->inst_imm));
3450                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3451                         break;
3452                 case OP_X86_XOR_MEMBASE_IMM:
3453                         g_assert (amd64_is_imm32 (ins->inst_imm));
3454                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3455                         break;
3456                 case OP_X86_ADD_MEMBASE_REG:
3457                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3458                         break;
3459                 case OP_X86_SUB_MEMBASE_REG:
3460                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3461                         break;
3462                 case OP_X86_AND_MEMBASE_REG:
3463                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3464                         break;
3465                 case OP_X86_OR_MEMBASE_REG:
3466                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3467                         break;
3468                 case OP_X86_XOR_MEMBASE_REG:
3469                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3470                         break;
3471                 case OP_X86_INC_MEMBASE:
3472                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3473                         break;
3474                 case OP_X86_INC_REG:
3475                         amd64_inc_reg_size (code, ins->dreg, 4);
3476                         break;
3477                 case OP_X86_DEC_MEMBASE:
3478                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3479                         break;
3480                 case OP_X86_DEC_REG:
3481                         amd64_dec_reg_size (code, ins->dreg, 4);
3482                         break;
3483                 case OP_X86_MUL_REG_MEMBASE:
3484                 case OP_X86_MUL_MEMBASE_REG:
3485                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3486                         break;
3487                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3488                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3489                         break;
3490                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3491                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3492                         break;
3493                 case OP_AMD64_COMPARE_MEMBASE_REG:
3494                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3495                         break;
3496                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3497                         g_assert (amd64_is_imm32 (ins->inst_imm));
3498                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3499                         break;
3500                 case OP_X86_COMPARE_MEMBASE8_IMM:
3501                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3502                         break;
3503                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3504                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3505                         break;
3506                 case OP_AMD64_COMPARE_REG_MEMBASE:
3507                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3508                         break;
3509
3510                 case OP_AMD64_ADD_REG_MEMBASE:
3511                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3512                         break;
3513                 case OP_AMD64_SUB_REG_MEMBASE:
3514                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3515                         break;
3516                 case OP_AMD64_AND_REG_MEMBASE:
3517                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3518                         break;
3519                 case OP_AMD64_OR_REG_MEMBASE:
3520                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3521                         break;
3522                 case OP_AMD64_XOR_REG_MEMBASE:
3523                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3524                         break;
3525
3526                 case OP_AMD64_ADD_MEMBASE_REG:
3527                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3528                         break;
3529                 case OP_AMD64_SUB_MEMBASE_REG:
3530                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3531                         break;
3532                 case OP_AMD64_AND_MEMBASE_REG:
3533                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3534                         break;
3535                 case OP_AMD64_OR_MEMBASE_REG:
3536                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3537                         break;
3538                 case OP_AMD64_XOR_MEMBASE_REG:
3539                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3540                         break;
3541
3542                 case OP_AMD64_ADD_MEMBASE_IMM:
3543                         g_assert (amd64_is_imm32 (ins->inst_imm));
3544                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3545                         break;
3546                 case OP_AMD64_SUB_MEMBASE_IMM:
3547                         g_assert (amd64_is_imm32 (ins->inst_imm));
3548                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3549                         break;
3550                 case OP_AMD64_AND_MEMBASE_IMM:
3551                         g_assert (amd64_is_imm32 (ins->inst_imm));
3552                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3553                         break;
3554                 case OP_AMD64_OR_MEMBASE_IMM:
3555                         g_assert (amd64_is_imm32 (ins->inst_imm));
3556                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3557                         break;
3558                 case OP_AMD64_XOR_MEMBASE_IMM:
3559                         g_assert (amd64_is_imm32 (ins->inst_imm));
3560                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3561                         break;
3562
3563                 case OP_BREAK:
3564                         amd64_breakpoint (code);
3565                         break;
3566                 case OP_RELAXED_NOP:
3567                         x86_prefix (code, X86_REP_PREFIX);
3568                         x86_nop (code);
3569                         break;
3570                 case OP_HARD_NOP:
3571                         x86_nop (code);
3572                         break;
3573                 case OP_NOP:
3574                 case OP_DUMMY_USE:
3575                 case OP_DUMMY_STORE:
3576                 case OP_NOT_REACHED:
3577                 case OP_NOT_NULL:
3578                         break;
3579                 case OP_SEQ_POINT: {
3580                         int i;
3581
3582                         if (cfg->compile_aot)
3583                                 NOT_IMPLEMENTED;
3584
3585                         /*
3586                          * Read from the single stepping trigger page. This will cause a
3587                          * SIGSEGV when single stepping is enabled.
3588                          * We do this _before_ the breakpoint, so single stepping after
3589                          * a breakpoint is hit will step to the next IL offset.
3590                          */
3591                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3592                                 if (((guint64)ss_trigger_page >> 32) == 0)
3593                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3594                                 else {
3595                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3596
3597                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3598                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3599                                 }
3600                         }
3601
3602                         /*
3603                          * This is the address which is saved in seq points,
3604                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3605                          * from the address of the instruction causing the fault.
3606                          */
3607                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3608
3609                         /*
3610                          * A placeholder for a possible breakpoint inserted by
3611                          * mono_arch_set_breakpoint ().
3612                          */
3613                         for (i = 0; i < breakpoint_size; ++i)
3614                                 x86_nop (code);
3615                         break;
3616                 }
3617                 case OP_ADDCC:
3618                 case OP_LADD:
3619                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3620                         break;
3621                 case OP_ADC:
3622                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3623                         break;
3624                 case OP_ADD_IMM:
3625                 case OP_LADD_IMM:
3626                         g_assert (amd64_is_imm32 (ins->inst_imm));
3627                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3628                         break;
3629                 case OP_ADC_IMM:
3630                         g_assert (amd64_is_imm32 (ins->inst_imm));
3631                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3632                         break;
3633                 case OP_SUBCC:
3634                 case OP_LSUB:
3635                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3636                         break;
3637                 case OP_SBB:
3638                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3639                         break;
3640                 case OP_SUB_IMM:
3641                 case OP_LSUB_IMM:
3642                         g_assert (amd64_is_imm32 (ins->inst_imm));
3643                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3644                         break;
3645                 case OP_SBB_IMM:
3646                         g_assert (amd64_is_imm32 (ins->inst_imm));
3647                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3648                         break;
3649                 case OP_LAND:
3650                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3651                         break;
3652                 case OP_AND_IMM:
3653                 case OP_LAND_IMM:
3654                         g_assert (amd64_is_imm32 (ins->inst_imm));
3655                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3656                         break;
3657                 case OP_LMUL:
3658                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3659                         break;
3660                 case OP_MUL_IMM:
3661                 case OP_LMUL_IMM:
3662                 case OP_IMUL_IMM: {
3663                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3664
3665                         switch (ins->inst_imm) {
3666                         case 2:
3667                                 /* MOV r1, r2 */
3668                                 /* ADD r1, r1 */
3669                                 if (ins->dreg != ins->sreg1)
3670                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3671                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3672                                 break;
3673                         case 3:
3674                                 /* LEA r1, [r2 + r2*2] */
3675                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3676                                 break;
3677                         case 5:
3678                                 /* LEA r1, [r2 + r2*4] */
3679                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3680                                 break;
3681                         case 6:
3682                                 /* LEA r1, [r2 + r2*2] */
3683                                 /* ADD r1, r1          */
3684                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3685                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3686                                 break;
3687                         case 9:
3688                                 /* LEA r1, [r2 + r2*8] */
3689                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3690                                 break;
3691                         case 10:
3692                                 /* LEA r1, [r2 + r2*4] */
3693                                 /* ADD r1, r1          */
3694                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3695                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3696                                 break;
3697                         case 12:
3698                                 /* LEA r1, [r2 + r2*2] */
3699                                 /* SHL r1, 2           */
3700                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3701                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3702                                 break;
3703                         case 25:
3704                                 /* LEA r1, [r2 + r2*4] */
3705                                 /* LEA r1, [r1 + r1*4] */
3706                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3707                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3708                                 break;
3709                         case 100:
3710                                 /* LEA r1, [r2 + r2*4] */
3711                                 /* SHL r1, 2           */
3712                                 /* LEA r1, [r1 + r1*4] */
3713                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3714                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3715                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3716                                 break;
3717                         default:
3718                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3719                                 break;
3720                         }
3721                         break;
3722                 }
3723                 case OP_LDIV:
3724                 case OP_LREM:
3725                         /* Regalloc magic makes the div/rem cases the same */
3726                         if (ins->sreg2 == AMD64_RDX) {
3727                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3728                                 amd64_cdq (code);
3729                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3730                         } else {
3731                                 amd64_cdq (code);
3732                                 amd64_div_reg (code, ins->sreg2, TRUE);
3733                         }
3734                         break;
3735                 case OP_LDIV_UN:
3736                 case OP_LREM_UN:
3737                         if (ins->sreg2 == AMD64_RDX) {
3738                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3739                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3740                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3741                         } else {
3742                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3743                                 amd64_div_reg (code, ins->sreg2, FALSE);
3744                         }
3745                         break;
3746                 case OP_IDIV:
3747                 case OP_IREM:
3748                         if (ins->sreg2 == AMD64_RDX) {
3749                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3750                                 amd64_cdq_size (code, 4);
3751                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3752                         } else {
3753                                 amd64_cdq_size (code, 4);
3754                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3755                         }
3756                         break;
3757                 case OP_IDIV_UN:
3758                 case OP_IREM_UN:
3759                         if (ins->sreg2 == AMD64_RDX) {
3760                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3761                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3762                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3763                         } else {
3764                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3765                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3766                         }
3767                         break;
3768                 case OP_IREM_IMM: {
3769                         int power = mono_is_power_of_two (ins->inst_imm);
3770
3771                         g_assert (ins->sreg1 == X86_EAX);
3772                         g_assert (ins->dreg == X86_EAX);
3773                         g_assert (power >= 0);
3774
3775                         if (power == 0) {
3776                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3777                                 break;
3778                         }
3779
3780                         /* Based on gcc code */
3781
3782                         /* Add compensation for negative dividents */
3783                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3784                         if (power > 1)
3785                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3786                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3787                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3788                         /* Compute remainder */
3789                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3790                         /* Remove compensation */
3791                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3792                         break;
3793                 }
3794                 case OP_LMUL_OVF:
3795                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3796                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3797                         break;
3798                 case OP_LOR:
3799                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3800                         break;
3801                 case OP_OR_IMM:
3802                 case OP_LOR_IMM:
3803                         g_assert (amd64_is_imm32 (ins->inst_imm));
3804                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3805                         break;
3806                 case OP_LXOR:
3807                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3808                         break;
3809                 case OP_XOR_IMM:
3810                 case OP_LXOR_IMM:
3811                         g_assert (amd64_is_imm32 (ins->inst_imm));
3812                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3813                         break;
3814                 case OP_LSHL:
3815                         g_assert (ins->sreg2 == AMD64_RCX);
3816                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3817                         break;
3818                 case OP_LSHR:
3819                         g_assert (ins->sreg2 == AMD64_RCX);
3820                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3821                         break;
3822                 case OP_SHR_IMM:
3823                         g_assert (amd64_is_imm32 (ins->inst_imm));
3824                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3825                         break;
3826                 case OP_LSHR_IMM:
3827                         g_assert (amd64_is_imm32 (ins->inst_imm));
3828                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3829                         break;
3830                 case OP_SHR_UN_IMM:
3831                         g_assert (amd64_is_imm32 (ins->inst_imm));
3832                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3833                         break;
3834                 case OP_LSHR_UN_IMM:
3835                         g_assert (amd64_is_imm32 (ins->inst_imm));
3836                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3837                         break;
3838                 case OP_LSHR_UN:
3839                         g_assert (ins->sreg2 == AMD64_RCX);
3840                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3841                         break;
3842                 case OP_SHL_IMM:
3843                         g_assert (amd64_is_imm32 (ins->inst_imm));
3844                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3845                         break;
3846                 case OP_LSHL_IMM:
3847                         g_assert (amd64_is_imm32 (ins->inst_imm));
3848                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3849                         break;
3850
3851                 case OP_IADDCC:
3852                 case OP_IADD:
3853                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3854                         break;
3855                 case OP_IADC:
3856                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3857                         break;
3858                 case OP_IADD_IMM:
3859                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3860                         break;
3861                 case OP_IADC_IMM:
3862                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3863                         break;
3864                 case OP_ISUBCC:
3865                 case OP_ISUB:
3866                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3867                         break;
3868                 case OP_ISBB:
3869                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3870                         break;
3871                 case OP_ISUB_IMM:
3872                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3873                         break;
3874                 case OP_ISBB_IMM:
3875                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3876                         break;
3877                 case OP_IAND:
3878                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3879                         break;
3880                 case OP_IAND_IMM:
3881                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3882                         break;
3883                 case OP_IOR:
3884                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3885                         break;
3886                 case OP_IOR_IMM:
3887                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3888                         break;
3889                 case OP_IXOR:
3890                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3891                         break;
3892                 case OP_IXOR_IMM:
3893                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3894                         break;
3895                 case OP_INEG:
3896                         amd64_neg_reg_size (code, ins->sreg1, 4);
3897                         break;
3898                 case OP_INOT:
3899                         amd64_not_reg_size (code, ins->sreg1, 4);
3900                         break;
3901                 case OP_ISHL:
3902                         g_assert (ins->sreg2 == AMD64_RCX);
3903                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3904                         break;
3905                 case OP_ISHR:
3906                         g_assert (ins->sreg2 == AMD64_RCX);
3907                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3908                         break;
3909                 case OP_ISHR_IMM:
3910                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3911                         break;
3912                 case OP_ISHR_UN_IMM:
3913                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3914                         break;
3915                 case OP_ISHR_UN:
3916                         g_assert (ins->sreg2 == AMD64_RCX);
3917                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3918                         break;
3919                 case OP_ISHL_IMM:
3920                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3921                         break;
3922                 case OP_IMUL:
3923                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3924                         break;
3925                 case OP_IMUL_OVF:
3926                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3927                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3928                         break;
3929                 case OP_IMUL_OVF_UN:
3930                 case OP_LMUL_OVF_UN: {
3931                         /* the mul operation and the exception check should most likely be split */
3932                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3933                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3934                         /*g_assert (ins->sreg2 == X86_EAX);
3935                         g_assert (ins->dreg == X86_EAX);*/
3936                         if (ins->sreg2 == X86_EAX) {
3937                                 non_eax_reg = ins->sreg1;
3938                         } else if (ins->sreg1 == X86_EAX) {
3939                                 non_eax_reg = ins->sreg2;
3940                         } else {
3941                                 /* no need to save since we're going to store to it anyway */
3942                                 if (ins->dreg != X86_EAX) {
3943                                         saved_eax = TRUE;
3944                                         amd64_push_reg (code, X86_EAX);
3945                                 }
3946                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3947                                 non_eax_reg = ins->sreg2;
3948                         }
3949                         if (ins->dreg == X86_EDX) {
3950                                 if (!saved_eax) {
3951                                         saved_eax = TRUE;
3952                                         amd64_push_reg (code, X86_EAX);
3953                                 }
3954                         } else {
3955                                 saved_edx = TRUE;
3956                                 amd64_push_reg (code, X86_EDX);
3957                         }
3958                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3959                         /* save before the check since pop and mov don't change the flags */
3960                         if (ins->dreg != X86_EAX)
3961                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3962                         if (saved_edx)
3963                                 amd64_pop_reg (code, X86_EDX);
3964                         if (saved_eax)
3965                                 amd64_pop_reg (code, X86_EAX);
3966                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3967                         break;
3968                 }
3969                 case OP_ICOMPARE:
3970                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3971                         break;
3972                 case OP_ICOMPARE_IMM:
3973                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3974                         break;
3975                 case OP_IBEQ:
3976                 case OP_IBLT:
3977                 case OP_IBGT:
3978                 case OP_IBGE:
3979                 case OP_IBLE:
3980                 case OP_LBEQ:
3981                 case OP_LBLT:
3982                 case OP_LBGT:
3983                 case OP_LBGE:
3984                 case OP_LBLE:
3985                 case OP_IBNE_UN:
3986                 case OP_IBLT_UN:
3987                 case OP_IBGT_UN:
3988                 case OP_IBGE_UN:
3989                 case OP_IBLE_UN:
3990                 case OP_LBNE_UN:
3991                 case OP_LBLT_UN:
3992                 case OP_LBGT_UN:
3993                 case OP_LBGE_UN:
3994                 case OP_LBLE_UN:
3995                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3996                         break;
3997
3998                 case OP_CMOV_IEQ:
3999                 case OP_CMOV_IGE:
4000                 case OP_CMOV_IGT:
4001                 case OP_CMOV_ILE:
4002                 case OP_CMOV_ILT:
4003                 case OP_CMOV_INE_UN:
4004                 case OP_CMOV_IGE_UN:
4005                 case OP_CMOV_IGT_UN:
4006                 case OP_CMOV_ILE_UN:
4007                 case OP_CMOV_ILT_UN:
4008                 case OP_CMOV_LEQ:
4009                 case OP_CMOV_LGE:
4010                 case OP_CMOV_LGT:
4011                 case OP_CMOV_LLE:
4012                 case OP_CMOV_LLT:
4013                 case OP_CMOV_LNE_UN:
4014                 case OP_CMOV_LGE_UN:
4015                 case OP_CMOV_LGT_UN:
4016                 case OP_CMOV_LLE_UN:
4017                 case OP_CMOV_LLT_UN:
4018                         g_assert (ins->dreg == ins->sreg1);
4019                         /* This needs to operate on 64 bit values */
4020                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4021                         break;
4022
4023                 case OP_LNOT:
4024                         amd64_not_reg (code, ins->sreg1);
4025                         break;
4026                 case OP_LNEG:
4027                         amd64_neg_reg (code, ins->sreg1);
4028                         break;
4029
4030                 case OP_ICONST:
4031                 case OP_I8CONST:
4032                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4033                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4034                         else
4035                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4036                         break;
4037                 case OP_AOTCONST:
4038                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4039                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4040                         break;
4041                 case OP_JUMP_TABLE:
4042                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4043                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4044                         break;
4045                 case OP_MOVE:
4046                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4047                         break;
4048                 case OP_AMD64_SET_XMMREG_R4: {
4049                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4050                         break;
4051                 }
4052                 case OP_AMD64_SET_XMMREG_R8: {
4053                         if (ins->dreg != ins->sreg1)
4054                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4055                         break;
4056                 }
4057                 case OP_TAILCALL: {
4058                         /*
4059                          * Note: this 'frame destruction' logic is useful for tail calls, too.
4060                          * Keep in sync with the code in emit_epilog.
4061                          */
4062                         int pos = 0, i;
4063
4064                         /* FIXME: no tracing support... */
4065                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4066                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4067
4068                         g_assert (!cfg->method->save_lmf);
4069
4070                         if (cfg->arch.omit_fp) {
4071                                 guint32 save_offset = 0;
4072                                 /* Pop callee-saved registers */
4073                                 for (i = 0; i < AMD64_NREG; ++i)
4074                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4075                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4076                                                 save_offset += 8;
4077                                         }
4078                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4079                         }
4080                         else {
4081                                 for (i = 0; i < AMD64_NREG; ++i)
4082                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4083                                                 pos -= sizeof (gpointer);
4084
4085                                 if (pos)
4086                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4087
4088                                 /* Pop registers in reverse order */
4089                                 for (i = AMD64_NREG - 1; i > 0; --i)
4090                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4091                                                 amd64_pop_reg (code, i);
4092                                         }
4093
4094                                 amd64_leave (code);
4095                         }
4096
4097                         offset = code - cfg->native_code;
4098                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4099                         if (cfg->compile_aot)
4100                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4101                         else
4102                                 amd64_set_reg_template (code, AMD64_R11);
4103                         amd64_jump_reg (code, AMD64_R11);
4104                         break;
4105                 }
4106                 case OP_CHECK_THIS:
4107                         /* ensure ins->sreg1 is not NULL */
4108                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4109                         break;
4110                 case OP_ARGLIST: {
4111                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4112                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4113                         break;
4114                 }
4115                 case OP_CALL:
4116                 case OP_FCALL:
4117                 case OP_LCALL:
4118                 case OP_VCALL:
4119                 case OP_VCALL2:
4120                 case OP_VOIDCALL:
4121                         call = (MonoCallInst*)ins;
4122                         /*
4123                          * The AMD64 ABI forces callers to know about varargs.
4124                          */
4125                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4126                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4127                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4128                                 /*
4129                                  * Since the unmanaged calling convention doesn't contain a
4130                                  * 'vararg' entry, we have to treat every pinvoke call as a
4131                                  * potential vararg call.
4132                                  */
4133                                 guint32 nregs, i;
4134                                 nregs = 0;
4135                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4136                                         if (call->used_fregs & (1 << i))
4137                                                 nregs ++;
4138                                 if (!nregs)
4139                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4140                                 else
4141                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4142                         }
4143
4144                         if (ins->flags & MONO_INST_HAS_METHOD)
4145                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4146                         else
4147                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4148                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4149                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4150                         code = emit_move_return_value (cfg, ins, code);
4151                         break;
4152                 case OP_FCALL_REG:
4153                 case OP_LCALL_REG:
4154                 case OP_VCALL_REG:
4155                 case OP_VCALL2_REG:
4156                 case OP_VOIDCALL_REG:
4157                 case OP_CALL_REG:
4158                         call = (MonoCallInst*)ins;
4159
4160                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4161                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4162                                 ins->sreg1 = AMD64_R11;
4163                         }
4164
4165                         /*
4166                          * The AMD64 ABI forces callers to know about varargs.
4167                          */
4168                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4169                                 if (ins->sreg1 == AMD64_RAX) {
4170                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4171                                         ins->sreg1 = AMD64_R11;
4172                                 }
4173                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4174                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4175                                 /*
4176                                  * Since the unmanaged calling convention doesn't contain a
4177                                  * 'vararg' entry, we have to treat every pinvoke call as a
4178                                  * potential vararg call.
4179                                  */
4180                                 guint32 nregs, i;
4181                                 nregs = 0;
4182                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4183                                         if (call->used_fregs & (1 << i))
4184                                                 nregs ++;
4185                                 if (ins->sreg1 == AMD64_RAX) {
4186                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4187                                         ins->sreg1 = AMD64_R11;
4188                                 }
4189                                 if (!nregs)
4190                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4191                                 else
4192                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4193                         }
4194
4195                         amd64_call_reg (code, ins->sreg1);
4196                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4197                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4198                         code = emit_move_return_value (cfg, ins, code);
4199                         break;
4200                 case OP_FCALL_MEMBASE:
4201                 case OP_LCALL_MEMBASE:
4202                 case OP_VCALL_MEMBASE:
4203                 case OP_VCALL2_MEMBASE:
4204                 case OP_VOIDCALL_MEMBASE:
4205                 case OP_CALL_MEMBASE:
4206                         call = (MonoCallInst*)ins;
4207
4208                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4209                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4210                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4211                         code = emit_move_return_value (cfg, ins, code);
4212                         break;
4213                 case OP_DYN_CALL: {
4214                         int i;
4215                         MonoInst *var = cfg->dyn_call_var;
4216
4217                         g_assert (var->opcode == OP_REGOFFSET);
4218
4219                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4220                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4221                         /* r10 = ftn */
4222                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4223
4224                         /* Save args buffer */
4225                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4226
4227                         /* Set argument registers */
4228                         for (i = 0; i < PARAM_REGS; ++i)
4229                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4230
4231                         /* Make the call */
4232                         amd64_call_reg (code, AMD64_R10);
4233
4234                         /* Save result */
4235                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4236                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4237                         break;
4238                 }
4239                 case OP_AMD64_SAVE_SP_TO_LMF:
4240                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4241                         break;
4242                 case OP_X86_PUSH:
4243                         g_assert (!cfg->arch.no_pushes);
4244                         amd64_push_reg (code, ins->sreg1);
4245                         break;
4246                 case OP_X86_PUSH_IMM:
4247                         g_assert (!cfg->arch.no_pushes);
4248                         g_assert (amd64_is_imm32 (ins->inst_imm));
4249                         amd64_push_imm (code, ins->inst_imm);
4250                         break;
4251                 case OP_X86_PUSH_MEMBASE:
4252                         g_assert (!cfg->arch.no_pushes);
4253                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4254                         break;
4255                 case OP_X86_PUSH_OBJ: {
4256                         int size = ALIGN_TO (ins->inst_imm, 8);
4257
4258                         g_assert (!cfg->arch.no_pushes);
4259
4260                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4261                         amd64_push_reg (code, AMD64_RDI);
4262                         amd64_push_reg (code, AMD64_RSI);
4263                         amd64_push_reg (code, AMD64_RCX);
4264                         if (ins->inst_offset)
4265                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4266                         else
4267                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4268                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4269                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4270                         amd64_cld (code);
4271                         amd64_prefix (code, X86_REP_PREFIX);
4272                         amd64_movsd (code);
4273                         amd64_pop_reg (code, AMD64_RCX);
4274                         amd64_pop_reg (code, AMD64_RSI);
4275                         amd64_pop_reg (code, AMD64_RDI);
4276                         break;
4277                 }
4278                 case OP_X86_LEA:
4279                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4280                         break;
4281                 case OP_X86_LEA_MEMBASE:
4282                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4283                         break;
4284                 case OP_X86_XCHG:
4285                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4286                         break;
4287                 case OP_LOCALLOC:
4288                         /* keep alignment */
4289                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4290                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4291                         code = mono_emit_stack_alloc (cfg, code, ins);
4292                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4293                         if (cfg->param_area && cfg->arch.no_pushes)
4294                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4295                         break;
4296                 case OP_LOCALLOC_IMM: {
4297                         guint32 size = ins->inst_imm;
4298                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4299
4300                         if (ins->flags & MONO_INST_INIT) {
4301                                 if (size < 64) {
4302                                         int i;
4303
4304                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4305                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4306
4307                                         for (i = 0; i < size; i += 8)
4308                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4309                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4310                                 } else {
4311                                         amd64_mov_reg_imm (code, ins->dreg, size);
4312                                         ins->sreg1 = ins->dreg;
4313
4314                                         code = mono_emit_stack_alloc (cfg, code, ins);
4315                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4316                                 }
4317                         } else {
4318                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4319                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4320                         }
4321                         if (cfg->param_area && cfg->arch.no_pushes)
4322                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4323                         break;
4324                 }
4325                 case OP_THROW: {
4326                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4327                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4328                                              (gpointer)"mono_arch_throw_exception", FALSE);
4329                         break;
4330                 }
4331                 case OP_RETHROW: {
4332                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4333                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4334                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4335                         break;
4336                 }
4337                 case OP_CALL_HANDLER:
4338                         /* Align stack */
4339                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4340                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4341                         amd64_call_imm (code, 0);
4342                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4343                         /* Restore stack alignment */
4344                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4345                         break;
4346                 case OP_START_HANDLER: {
4347                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4348                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4349
4350                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4351                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4352                                 cfg->param_area && cfg->arch.no_pushes) {
4353                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4354                         }
4355                         break;
4356                 }
4357                 case OP_ENDFINALLY: {
4358                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4359                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4360                         amd64_ret (code);
4361                         break;
4362                 }
4363                 case OP_ENDFILTER: {
4364                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4365                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4366                         /* The local allocator will put the result into RAX */
4367                         amd64_ret (code);
4368                         break;
4369                 }
4370
4371                 case OP_LABEL:
4372                         ins->inst_c0 = code - cfg->native_code;
4373                         break;
4374                 case OP_BR:
4375                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4376                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4377                         //break;
4378                                 if (ins->inst_target_bb->native_offset) {
4379                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4380                                 } else {
4381                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4382                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4383                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4384                                                 x86_jump8 (code, 0);
4385                                         else
4386                                                 x86_jump32 (code, 0);
4387                         }
4388                         break;
4389                 case OP_BR_REG:
4390                         amd64_jump_reg (code, ins->sreg1);
4391                         break;
4392                 case OP_CEQ:
4393                 case OP_LCEQ:
4394                 case OP_ICEQ:
4395                 case OP_CLT:
4396                 case OP_LCLT:
4397                 case OP_ICLT:
4398                 case OP_CGT:
4399                 case OP_ICGT:
4400                 case OP_LCGT:
4401                 case OP_CLT_UN:
4402                 case OP_LCLT_UN:
4403                 case OP_ICLT_UN:
4404                 case OP_CGT_UN:
4405                 case OP_LCGT_UN:
4406                 case OP_ICGT_UN:
4407                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4408                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4409                         break;
4410                 case OP_COND_EXC_EQ:
4411                 case OP_COND_EXC_NE_UN:
4412                 case OP_COND_EXC_LT:
4413                 case OP_COND_EXC_LT_UN:
4414                 case OP_COND_EXC_GT:
4415                 case OP_COND_EXC_GT_UN:
4416                 case OP_COND_EXC_GE:
4417                 case OP_COND_EXC_GE_UN:
4418                 case OP_COND_EXC_LE:
4419                 case OP_COND_EXC_LE_UN:
4420                 case OP_COND_EXC_IEQ:
4421                 case OP_COND_EXC_INE_UN:
4422                 case OP_COND_EXC_ILT:
4423                 case OP_COND_EXC_ILT_UN:
4424                 case OP_COND_EXC_IGT:
4425                 case OP_COND_EXC_IGT_UN:
4426                 case OP_COND_EXC_IGE:
4427                 case OP_COND_EXC_IGE_UN:
4428                 case OP_COND_EXC_ILE:
4429                 case OP_COND_EXC_ILE_UN:
4430                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4431                         break;
4432                 case OP_COND_EXC_OV:
4433                 case OP_COND_EXC_NO:
4434                 case OP_COND_EXC_C:
4435                 case OP_COND_EXC_NC:
4436                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4437                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4438                         break;
4439                 case OP_COND_EXC_IOV:
4440                 case OP_COND_EXC_INO:
4441                 case OP_COND_EXC_IC:
4442                 case OP_COND_EXC_INC:
4443                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4444                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4445                         break;
4446
4447                 /* floating point opcodes */
4448                 case OP_R8CONST: {
4449                         double d = *(double *)ins->inst_p0;
4450
4451                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4452                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4453                         }
4454                         else {
4455                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4456                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4457                         }
4458                         break;
4459                 }
4460                 case OP_R4CONST: {
4461                         float f = *(float *)ins->inst_p0;
4462
4463                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4464                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4465                         }
4466                         else {
4467                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4468                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4469                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4470                         }
4471                         break;
4472                 }
4473                 case OP_STORER8_MEMBASE_REG:
4474                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4475                         break;
4476                 case OP_LOADR8_MEMBASE:
4477                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4478                         break;
4479                 case OP_STORER4_MEMBASE_REG:
4480                         /* This requires a double->single conversion */
4481                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4482                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4483                         break;
4484                 case OP_LOADR4_MEMBASE:
4485                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4486                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4487                         break;
4488                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4489                 case OP_ICONV_TO_R8:
4490                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4491                         break;
4492                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4493                 case OP_LCONV_TO_R8:
4494                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4495                         break;
4496                 case OP_FCONV_TO_R4:
4497                         /* FIXME: nothing to do ?? */
4498                         break;
4499                 case OP_FCONV_TO_I1:
4500                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4501                         break;
4502                 case OP_FCONV_TO_U1:
4503                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4504                         break;
4505                 case OP_FCONV_TO_I2:
4506                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4507                         break;
4508                 case OP_FCONV_TO_U2:
4509                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4510                         break;
4511                 case OP_FCONV_TO_U4:
4512                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4513                         break;
4514                 case OP_FCONV_TO_I4:
4515                 case OP_FCONV_TO_I:
4516                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4517                         break;
4518                 case OP_FCONV_TO_I8:
4519                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4520                         break;
4521                 case OP_LCONV_TO_R_UN: {
4522                         guint8 *br [2];
4523
4524                         /* Based on gcc code */
4525                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4526                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4527
4528                         /* Positive case */
4529                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4530                         br [1] = code; x86_jump8 (code, 0);
4531                         amd64_patch (br [0], code);
4532
4533                         /* Negative case */
4534                         /* Save to the red zone */
4535                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4536                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4537                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4538                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4539                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4540                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4541                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4542                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4543                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4544                         /* Restore */
4545                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4546                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4547                         amd64_patch (br [1], code);
4548                         break;
4549                 }
4550                 case OP_LCONV_TO_OVF_U4:
4551                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4552                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4553                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4554                         break;
4555                 case OP_LCONV_TO_OVF_I4_UN:
4556                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4557                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4558                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4559                         break;
4560                 case OP_FMOVE:
4561                         if (ins->dreg != ins->sreg1)
4562                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4563                         break;
4564                 case OP_FADD:
4565                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4566                         break;
4567                 case OP_FSUB:
4568                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4569                         break;
4570                 case OP_FMUL:
4571                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4572                         break;
4573                 case OP_FDIV:
4574                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4575                         break;
4576                 case OP_FNEG: {
4577                         static double r8_0 = -0.0;
4578
4579                         g_assert (ins->sreg1 == ins->dreg);
4580
4581                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4582                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4583                         break;
4584                 }
4585                 case OP_SIN:
4586                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4587                         break;
4588                 case OP_COS:
4589                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4590                         break;
4591                 case OP_ABS: {
4592                         static guint64 d = 0x7fffffffffffffffUL;
4593
4594                         g_assert (ins->sreg1 == ins->dreg);
4595
4596                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4597                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4598                         break;
4599                 }
4600                 case OP_SQRT:
4601                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4602                         break;
4603                 case OP_IMIN:
4604                         g_assert (cfg->opt & MONO_OPT_CMOV);
4605                         g_assert (ins->dreg == ins->sreg1);
4606                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4607                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4608                         break;
4609                 case OP_IMIN_UN:
4610                         g_assert (cfg->opt & MONO_OPT_CMOV);
4611                         g_assert (ins->dreg == ins->sreg1);
4612                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4613                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4614                         break;
4615                 case OP_IMAX:
4616                         g_assert (cfg->opt & MONO_OPT_CMOV);
4617                         g_assert (ins->dreg == ins->sreg1);
4618                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4619                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4620                         break;
4621                 case OP_IMAX_UN:
4622                         g_assert (cfg->opt & MONO_OPT_CMOV);
4623                         g_assert (ins->dreg == ins->sreg1);
4624                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4625                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4626                         break;
4627                 case OP_LMIN:
4628                         g_assert (cfg->opt & MONO_OPT_CMOV);
4629                         g_assert (ins->dreg == ins->sreg1);
4630                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4631                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4632                         break;
4633                 case OP_LMIN_UN:
4634                         g_assert (cfg->opt & MONO_OPT_CMOV);
4635                         g_assert (ins->dreg == ins->sreg1);
4636                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4637                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4638                         break;
4639                 case OP_LMAX:
4640                         g_assert (cfg->opt & MONO_OPT_CMOV);
4641                         g_assert (ins->dreg == ins->sreg1);
4642                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4643                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4644                         break;
4645                 case OP_LMAX_UN:
4646                         g_assert (cfg->opt & MONO_OPT_CMOV);
4647                         g_assert (ins->dreg == ins->sreg1);
4648                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4649                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4650                         break;
4651                 case OP_X86_FPOP:
4652                         break;
4653                 case OP_FCOMPARE:
4654                         /*
4655                          * The two arguments are swapped because the fbranch instructions
4656                          * depend on this for the non-sse case to work.
4657                          */
4658                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4659                         break;
4660                 case OP_FCEQ: {
4661                         /* zeroing the register at the start results in
4662                          * shorter and faster code (we can also remove the widening op)
4663                          */
4664                         guchar *unordered_check;
4665                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4666                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4667                         unordered_check = code;
4668                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4669                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4670                         amd64_patch (unordered_check, code);
4671                         break;
4672                 }
4673                 case OP_FCLT:
4674                 case OP_FCLT_UN:
4675                         /* zeroing the register at the start results in
4676                          * shorter and faster code (we can also remove the widening op)
4677                          */
4678                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4679                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4680                         if (ins->opcode == OP_FCLT_UN) {
4681                                 guchar *unordered_check = code;
4682                                 guchar *jump_to_end;
4683                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4684                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4685                                 jump_to_end = code;
4686                                 x86_jump8 (code, 0);
4687                                 amd64_patch (unordered_check, code);
4688                                 amd64_inc_reg (code, ins->dreg);
4689                                 amd64_patch (jump_to_end, code);
4690                         } else {
4691                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4692                         }
4693                         break;
4694                 case OP_FCGT:
4695                 case OP_FCGT_UN: {
4696                         /* zeroing the register at the start results in
4697                          * shorter and faster code (we can also remove the widening op)
4698                          */
4699                         guchar *unordered_check;
4700                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4701                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4702                         if (ins->opcode == OP_FCGT) {
4703                                 unordered_check = code;
4704                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4705                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4706                                 amd64_patch (unordered_check, code);
4707                         } else {
4708                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4709                         }
4710                         break;
4711                 }
4712                 case OP_FCLT_MEMBASE:
4713                 case OP_FCGT_MEMBASE:
4714                 case OP_FCLT_UN_MEMBASE:
4715                 case OP_FCGT_UN_MEMBASE:
4716                 case OP_FCEQ_MEMBASE: {
4717                         guchar *unordered_check, *jump_to_end;
4718                         int x86_cond;
4719
4720                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4721                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4722
4723                         switch (ins->opcode) {
4724                         case OP_FCEQ_MEMBASE:
4725                                 x86_cond = X86_CC_EQ;
4726                                 break;
4727                         case OP_FCLT_MEMBASE:
4728                         case OP_FCLT_UN_MEMBASE:
4729                                 x86_cond = X86_CC_LT;
4730                                 break;
4731                         case OP_FCGT_MEMBASE:
4732                         case OP_FCGT_UN_MEMBASE:
4733                                 x86_cond = X86_CC_GT;
4734                                 break;
4735                         default:
4736                                 g_assert_not_reached ();
4737                         }
4738
4739                         unordered_check = code;
4740                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4741                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4742
4743                         switch (ins->opcode) {
4744                         case OP_FCEQ_MEMBASE:
4745                         case OP_FCLT_MEMBASE:
4746                         case OP_FCGT_MEMBASE:
4747                                 amd64_patch (unordered_check, code);
4748                                 break;
4749                         case OP_FCLT_UN_MEMBASE:
4750                         case OP_FCGT_UN_MEMBASE:
4751                                 jump_to_end = code;
4752                                 x86_jump8 (code, 0);
4753                                 amd64_patch (unordered_check, code);
4754                                 amd64_inc_reg (code, ins->dreg);
4755                                 amd64_patch (jump_to_end, code);
4756                                 break;
4757                         default:
4758                                 break;
4759                         }
4760                         break;
4761                 }
4762                 case OP_FBEQ: {
4763                         guchar *jump = code;
4764                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4765                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4766                         amd64_patch (jump, code);
4767                         break;
4768                 }
4769                 case OP_FBNE_UN:
4770                         /* Branch if C013 != 100 */
4771                         /* branch if !ZF or (PF|CF) */
4772                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4773                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4774                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4775                         break;
4776                 case OP_FBLT:
4777                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4778                         break;
4779                 case OP_FBLT_UN:
4780                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4781                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4782                         break;
4783                 case OP_FBGT:
4784                 case OP_FBGT_UN:
4785                         if (ins->opcode == OP_FBGT) {
4786                                 guchar *br1;
4787
4788                                 /* skip branch if C1=1 */
4789                                 br1 = code;
4790                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4791                                 /* branch if (C0 | C3) = 1 */
4792                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4793                                 amd64_patch (br1, code);
4794                                 break;
4795                         } else {
4796                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4797                         }
4798                         break;
4799                 case OP_FBGE: {
4800                         /* Branch if C013 == 100 or 001 */
4801                         guchar *br1;
4802
4803                         /* skip branch if C1=1 */
4804                         br1 = code;
4805                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4806                         /* branch if (C0 | C3) = 1 */
4807                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4808                         amd64_patch (br1, code);
4809                         break;
4810                 }
4811                 case OP_FBGE_UN:
4812                         /* Branch if C013 == 000 */
4813                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4814                         break;
4815                 case OP_FBLE: {
4816                         /* Branch if C013=000 or 100 */
4817                         guchar *br1;
4818
4819                         /* skip branch if C1=1 */
4820                         br1 = code;
4821                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4822                         /* branch if C0=0 */
4823                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4824                         amd64_patch (br1, code);
4825                         break;
4826                 }
4827                 case OP_FBLE_UN:
4828                         /* Branch if C013 != 001 */
4829                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4830                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4831                         break;
4832                 case OP_CKFINITE:
4833                         /* Transfer value to the fp stack */
4834                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4835                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4836                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4837
4838                         amd64_push_reg (code, AMD64_RAX);
4839                         amd64_fxam (code);
4840                         amd64_fnstsw (code);
4841                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4842                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4843                         amd64_pop_reg (code, AMD64_RAX);
4844                         amd64_fstp (code, 0);
4845                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4846                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4847                         break;
4848                 case OP_TLS_GET: {
4849                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4850                         break;
4851                 }
4852                 case OP_MEMORY_BARRIER: {
4853                         /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4854                         x86_prefix (code, X86_LOCK_PREFIX);
4855                         amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
4856                         break;
4857                 }
4858                 case OP_ATOMIC_ADD_I4:
4859                 case OP_ATOMIC_ADD_I8: {
4860                         int dreg = ins->dreg;
4861                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4862
4863                         if (dreg == ins->inst_basereg)
4864                                 dreg = AMD64_R11;
4865
4866                         if (dreg != ins->sreg2)
4867                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4868
4869                         x86_prefix (code, X86_LOCK_PREFIX);
4870                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4871
4872                         if (dreg != ins->dreg)
4873                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4874
4875                         break;
4876                 }
4877                 case OP_ATOMIC_ADD_NEW_I4:
4878                 case OP_ATOMIC_ADD_NEW_I8: {
4879                         int dreg = ins->dreg;
4880                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4881
4882                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4883                                 dreg = AMD64_R11;
4884
4885                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4886                         amd64_prefix (code, X86_LOCK_PREFIX);
4887                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4888                         /* dreg contains the old value, add with sreg2 value */
4889                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4890
4891                         if (ins->dreg != dreg)
4892                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4893
4894                         break;
4895                 }
4896                 case OP_ATOMIC_EXCHANGE_I4:
4897                 case OP_ATOMIC_EXCHANGE_I8: {
4898                         guchar *br[2];
4899                         int sreg2 = ins->sreg2;
4900                         int breg = ins->inst_basereg;
4901                         guint32 size;
4902                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4903
4904                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4905                                 size = 8;
4906                         else
4907                                 size = 4;
4908
4909                         /*
4910                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4911                          * an explanation of how this works.
4912                          */
4913
4914                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4915                          * hack to overcome limits in x86 reg allocator
4916                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4917                          */
4918                         g_assert (ins->dreg == AMD64_RAX);
4919
4920                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4921                                 /* Highly unlikely, but possible */
4922                                 need_push = TRUE;
4923
4924                         /* The pushes invalidate rsp */
4925                         if ((breg == AMD64_RAX) || need_push) {
4926                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4927                                 breg = AMD64_R11;
4928                         }
4929
4930                         /* We need the EAX reg for the comparand */
4931                         if (ins->sreg2 == AMD64_RAX) {
4932                                 if (breg != AMD64_R11) {
4933                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4934                                         sreg2 = AMD64_R11;
4935                                 } else {
4936                                         g_assert (need_push);
4937                                         amd64_push_reg (code, AMD64_RDX);
4938                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4939                                         sreg2 = AMD64_RDX;
4940                                         rdx_pushed = TRUE;
4941                                 }
4942                         }
4943
4944                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4945
4946                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4947                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4948                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4949                         amd64_patch (br [1], br [0]);
4950
4951                         if (rdx_pushed)
4952                                 amd64_pop_reg (code, AMD64_RDX);
4953
4954                         break;
4955                 }
4956                 case OP_ATOMIC_CAS_I4:
4957                 case OP_ATOMIC_CAS_I8: {
4958                         guint32 size;
4959
4960                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4961                                 size = 8;
4962                         else
4963                                 size = 4;
4964
4965                         /*
4966                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4967                          * an explanation of how this works.
4968                          */
4969                         g_assert (ins->sreg3 == AMD64_RAX);
4970                         g_assert (ins->sreg1 != AMD64_RAX);
4971                         g_assert (ins->sreg1 != ins->sreg2);
4972
4973                         amd64_prefix (code, X86_LOCK_PREFIX);
4974                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4975
4976                         if (ins->dreg != AMD64_RAX)
4977                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4978                         break;
4979                 }
4980                 case OP_CARD_TABLE_WBARRIER: {
4981                         int ptr = ins->sreg1;
4982                         int value = ins->sreg2;
4983                         guchar *br;
4984                         int nursery_shift, card_table_shift;
4985                         gpointer card_table_mask;
4986                         size_t nursery_size;
4987
4988                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4989                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4990
4991                         /*If either point to the stack we can simply avoid the WB. This happens due to
4992                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
4993                          */
4994                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
4995                                 continue;
4996
4997                         /*
4998                          * We need one register we can clobber, we choose EDX and make sreg1
4999                          * fixed EAX to work around limitations in the local register allocator.
5000                          * sreg2 might get allocated to EDX, but that is not a problem since
5001                          * we use it before clobbering EDX.
5002                          */
5003                         g_assert (ins->sreg1 == AMD64_RAX);
5004
5005                         /*
5006                          * This is the code we produce:
5007                          *
5008                          *   edx = value
5009                          *   edx >>= nursery_shift
5010                          *   cmp edx, (nursery_start >> nursery_shift)
5011                          *   jne done
5012                          *   edx = ptr
5013                          *   edx >>= card_table_shift
5014                          *   edx += cardtable
5015                          *   [edx] = 1
5016                          * done:
5017                          */
5018
5019                         if (value != AMD64_RDX)
5020                                 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5021                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5022                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5023                         br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5024                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5025                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5026                         if (card_table_mask)
5027                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5028
5029                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5030                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5031
5032                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5033                         x86_patch (br, code);
5034                         break;
5035                 }
5036 #ifdef MONO_ARCH_SIMD_INTRINSICS
5037                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5038                 case OP_ADDPS:
5039                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5040                         break;
5041                 case OP_DIVPS:
5042                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5043                         break;
5044                 case OP_MULPS:
5045                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5046                         break;
5047                 case OP_SUBPS:
5048                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5049                         break;
5050                 case OP_MAXPS:
5051                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5052                         break;
5053                 case OP_MINPS:
5054                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5055                         break;
5056                 case OP_COMPPS:
5057                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5058                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5059                         break;
5060                 case OP_ANDPS:
5061                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5062                         break;
5063                 case OP_ANDNPS:
5064                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5065                         break;
5066                 case OP_ORPS:
5067                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5068                         break;
5069                 case OP_XORPS:
5070                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_SQRTPS:
5073                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5074                         break;
5075                 case OP_RSQRTPS:
5076                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5077                         break;
5078                 case OP_RCPPS:
5079                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5080                         break;
5081                 case OP_ADDSUBPS:
5082                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5083                         break;
5084                 case OP_HADDPS:
5085                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5086                         break;
5087                 case OP_HSUBPS:
5088                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5089                         break;
5090                 case OP_DUPPS_HIGH:
5091                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5092                         break;
5093                 case OP_DUPPS_LOW:
5094                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5095                         break;
5096
5097                 case OP_PSHUFLEW_HIGH:
5098                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5099                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5100                         break;
5101                 case OP_PSHUFLEW_LOW:
5102                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5103                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5104                         break;
5105                 case OP_PSHUFLED:
5106                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5107                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5108                         break;
5109
5110                 case OP_ADDPD:
5111                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5112                         break;
5113                 case OP_DIVPD:
5114                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5115                         break;
5116                 case OP_MULPD:
5117                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5118                         break;
5119                 case OP_SUBPD:
5120                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5121                         break;
5122                 case OP_MAXPD:
5123                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5124                         break;
5125                 case OP_MINPD:
5126                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5127                         break;
5128                 case OP_COMPPD:
5129                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5130                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5131                         break;
5132                 case OP_ANDPD:
5133                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5134                         break;
5135                 case OP_ANDNPD:
5136                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5137                         break;
5138                 case OP_ORPD:
5139                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5140                         break;
5141                 case OP_XORPD:
5142                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5143                         break;
5144                 case OP_SQRTPD:
5145                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5146                         break;
5147                 case OP_ADDSUBPD:
5148                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         break;
5150                 case OP_HADDPD:
5151                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5152                         break;
5153                 case OP_HSUBPD:
5154                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5155                         break;
5156                 case OP_DUPPD:
5157                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5158                         break;
5159
5160                 case OP_EXTRACT_MASK:
5161                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5162                         break;
5163
5164                 case OP_PAND:
5165                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5166                         break;
5167                 case OP_POR:
5168                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5169                         break;
5170                 case OP_PXOR:
5171                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5172                         break;
5173
5174                 case OP_PADDB:
5175                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5176                         break;
5177                 case OP_PADDW:
5178                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5179                         break;
5180                 case OP_PADDD:
5181                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5182                         break;
5183                 case OP_PADDQ:
5184                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5185                         break;
5186
5187                 case OP_PSUBB:
5188                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5189                         break;
5190                 case OP_PSUBW:
5191                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5192                         break;
5193                 case OP_PSUBD:
5194                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5195                         break;
5196                 case OP_PSUBQ:
5197                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5198                         break;
5199
5200                 case OP_PMAXB_UN:
5201                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5202                         break;
5203                 case OP_PMAXW_UN:
5204                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5205                         break;
5206                 case OP_PMAXD_UN:
5207                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5208                         break;
5209
5210                 case OP_PMAXB:
5211                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5212                         break;
5213                 case OP_PMAXW:
5214                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5215                         break;
5216                 case OP_PMAXD:
5217                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5218                         break;
5219
5220                 case OP_PAVGB_UN:
5221                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5222                         break;
5223                 case OP_PAVGW_UN:
5224                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5225                         break;
5226
5227                 case OP_PMINB_UN:
5228                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5229                         break;
5230                 case OP_PMINW_UN:
5231                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5232                         break;
5233                 case OP_PMIND_UN:
5234                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5235                         break;
5236
5237                 case OP_PMINB:
5238                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5239                         break;
5240                 case OP_PMINW:
5241                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5242                         break;
5243                 case OP_PMIND:
5244                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5245                         break;
5246
5247                 case OP_PCMPEQB:
5248                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5249                         break;
5250                 case OP_PCMPEQW:
5251                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5252                         break;
5253                 case OP_PCMPEQD:
5254                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5255                         break;
5256                 case OP_PCMPEQQ:
5257                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5258                         break;
5259
5260                 case OP_PCMPGTB:
5261                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5262                         break;
5263                 case OP_PCMPGTW:
5264                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5265                         break;
5266                 case OP_PCMPGTD:
5267                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5268                         break;
5269                 case OP_PCMPGTQ:
5270                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5271                         break;
5272
5273                 case OP_PSUM_ABS_DIFF:
5274                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5275                         break;
5276
5277                 case OP_UNPACK_LOWB:
5278                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5279                         break;
5280                 case OP_UNPACK_LOWW:
5281                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5282                         break;
5283                 case OP_UNPACK_LOWD:
5284                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5285                         break;
5286                 case OP_UNPACK_LOWQ:
5287                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5288                         break;
5289                 case OP_UNPACK_LOWPS:
5290                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5291                         break;
5292                 case OP_UNPACK_LOWPD:
5293                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5294                         break;
5295
5296                 case OP_UNPACK_HIGHB:
5297                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5298                         break;
5299                 case OP_UNPACK_HIGHW:
5300                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5301                         break;
5302                 case OP_UNPACK_HIGHD:
5303                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5304                         break;
5305                 case OP_UNPACK_HIGHQ:
5306                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5307                         break;
5308                 case OP_UNPACK_HIGHPS:
5309                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5310                         break;
5311                 case OP_UNPACK_HIGHPD:
5312                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5313                         break;
5314
5315                 case OP_PACKW:
5316                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5317                         break;
5318                 case OP_PACKD:
5319                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5320                         break;
5321                 case OP_PACKW_UN:
5322                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5323                         break;
5324                 case OP_PACKD_UN:
5325                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5326                         break;
5327
5328                 case OP_PADDB_SAT_UN:
5329                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5330                         break;
5331                 case OP_PSUBB_SAT_UN:
5332                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5333                         break;
5334                 case OP_PADDW_SAT_UN:
5335                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5336                         break;
5337                 case OP_PSUBW_SAT_UN:
5338                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5339                         break;
5340
5341                 case OP_PADDB_SAT:
5342                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5343                         break;
5344                 case OP_PSUBB_SAT:
5345                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5346                         break;
5347                 case OP_PADDW_SAT:
5348                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5349                         break;
5350                 case OP_PSUBW_SAT:
5351                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5352                         break;
5353
5354                 case OP_PMULW:
5355                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5356                         break;
5357                 case OP_PMULD:
5358                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5359                         break;
5360                 case OP_PMULQ:
5361                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5362                         break;
5363                 case OP_PMULW_HIGH_UN:
5364                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5365                         break;
5366                 case OP_PMULW_HIGH:
5367                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5368                         break;
5369
5370                 case OP_PSHRW:
5371                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5372                         break;
5373                 case OP_PSHRW_REG:
5374                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5375                         break;
5376
5377                 case OP_PSARW:
5378                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5379                         break;
5380                 case OP_PSARW_REG:
5381                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5382                         break;
5383
5384                 case OP_PSHLW:
5385                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5386                         break;
5387                 case OP_PSHLW_REG:
5388                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5389                         break;
5390
5391                 case OP_PSHRD:
5392                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5393                         break;
5394                 case OP_PSHRD_REG:
5395                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5396                         break;
5397
5398                 case OP_PSARD:
5399                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5400                         break;
5401                 case OP_PSARD_REG:
5402                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5403                         break;
5404
5405                 case OP_PSHLD:
5406                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5407                         break;
5408                 case OP_PSHLD_REG:
5409                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5410                         break;
5411
5412                 case OP_PSHRQ:
5413                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5414                         break;
5415                 case OP_PSHRQ_REG:
5416                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5417                         break;
5418
5419                 /*TODO: This is appart of the sse spec but not added
5420                 case OP_PSARQ:
5421                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5422                         break;
5423                 case OP_PSARQ_REG:
5424                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5425                         break;
5426                 */
5427
5428                 case OP_PSHLQ:
5429                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5430                         break;
5431                 case OP_PSHLQ_REG:
5432                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5433                         break;
5434
5435                 case OP_ICONV_TO_X:
5436                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5437                         break;
5438                 case OP_EXTRACT_I4:
5439                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5440                         break;
5441                 case OP_EXTRACT_I8:
5442                         if (ins->inst_c0) {
5443                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5444                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5445                         } else {
5446                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5447                         }
5448                         break;
5449                 case OP_EXTRACT_I1:
5450                 case OP_EXTRACT_U1:
5451                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5452                         if (ins->inst_c0)
5453                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5454                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5455                         break;
5456                 case OP_EXTRACT_I2:
5457                 case OP_EXTRACT_U2:
5458                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5459                         if (ins->inst_c0)
5460                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5461                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5462                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5463                         break;
5464                 case OP_EXTRACT_R8:
5465                         if (ins->inst_c0)
5466                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5467                         else
5468                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5469                         break;
5470                 case OP_INSERT_I2:
5471                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5472                         break;
5473                 case OP_EXTRACTX_U2:
5474                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5475                         break;
5476                 case OP_INSERTX_U1_SLOW:
5477                         /*sreg1 is the extracted ireg (scratch)
5478                         /sreg2 is the to be inserted ireg (scratch)
5479                         /dreg is the xreg to receive the value*/
5480
5481                         /*clear the bits from the extracted word*/
5482                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5483                         /*shift the value to insert if needed*/
5484                         if (ins->inst_c0 & 1)
5485                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5486                         /*join them together*/
5487                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5488                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5489                         break;
5490                 case OP_INSERTX_I4_SLOW:
5491                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5492                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5493                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5494                         break;
5495                 case OP_INSERTX_I8_SLOW:
5496                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5497                         if (ins->inst_c0)
5498                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5499                         else
5500                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5501                         break;
5502
5503                 case OP_INSERTX_R4_SLOW:
5504                         switch (ins->inst_c0) {
5505                         case 0:
5506                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5507                                 break;
5508                         case 1:
5509                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5510                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5511                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5512                                 break;
5513                         case 2:
5514                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5515                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5516                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5517                                 break;
5518                         case 3:
5519                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5520                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5521                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5522                                 break;
5523                         }
5524                         break;
5525                 case OP_INSERTX_R8_SLOW:
5526                         if (ins->inst_c0)
5527                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5528                         else
5529                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5530                         break;
5531                 case OP_STOREX_MEMBASE_REG:
5532                 case OP_STOREX_MEMBASE:
5533                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5534                         break;
5535                 case OP_LOADX_MEMBASE:
5536                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5537                         break;
5538                 case OP_LOADX_ALIGNED_MEMBASE:
5539                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5540                         break;
5541                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5542                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5543                         break;
5544                 case OP_STOREX_NTA_MEMBASE_REG:
5545                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5546                         break;
5547                 case OP_PREFETCH_MEMBASE:
5548                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5549                         break;
5550
5551                 case OP_XMOVE:
5552                         /*FIXME the peephole pass should have killed this*/
5553                         if (ins->dreg != ins->sreg1)
5554                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5555                         break;
5556                 case OP_XZERO:
5557                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5558                         break;
5559                 case OP_ICONV_TO_R8_RAW:
5560                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5561                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5562                         break;
5563
5564                 case OP_FCONV_TO_R8_X:
5565                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5566                         break;
5567
5568                 case OP_XCONV_R8_TO_I4:
5569                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5570                         switch (ins->backend.source_opcode) {
5571                         case OP_FCONV_TO_I1:
5572                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5573                                 break;
5574                         case OP_FCONV_TO_U1:
5575                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5576                                 break;
5577                         case OP_FCONV_TO_I2:
5578                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5579                                 break;
5580                         case OP_FCONV_TO_U2:
5581                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5582                                 break;
5583                         }
5584                         break;
5585
5586                 case OP_EXPAND_I2:
5587                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5588                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5589                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5590                         break;
5591                 case OP_EXPAND_I4:
5592                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5593                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5594                         break;
5595                 case OP_EXPAND_I8:
5596                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5597                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5598                         break;
5599                 case OP_EXPAND_R4:
5600                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5601                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5602                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5603                         break;
5604                 case OP_EXPAND_R8:
5605                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5606                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5607                         break;
5608 #endif
5609                 case OP_LIVERANGE_START: {
5610                         if (cfg->verbose_level > 1)
5611                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5612                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5613                         break;
5614                 }
5615                 case OP_LIVERANGE_END: {
5616                         if (cfg->verbose_level > 1)
5617                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5618                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5619                         break;
5620                 }
5621                 default:
5622                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5623                         g_assert_not_reached ();
5624                 }
5625
5626                 if ((code - cfg->native_code - offset) > max_len) {
5627                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5628                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5629                         g_assert_not_reached ();
5630                 }
5631
5632                 last_ins = ins;
5633                 last_offset = offset;
5634         }
5635
5636         cfg->code_len = code - cfg->native_code;
5637 }
5638
5639 #endif /* DISABLE_JIT */
5640
5641 void
5642 mono_arch_register_lowlevel_calls (void)
5643 {
5644         /* The signature doesn't matter */
5645         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5646 }
5647
5648 void
5649 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5650 {
5651         MonoJumpInfo *patch_info;
5652         gboolean compile_aot = !run_cctors;
5653
5654         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5655                 unsigned char *ip = patch_info->ip.i + code;
5656                 unsigned char *target;
5657
5658                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5659
5660                 if (compile_aot) {
5661                         switch (patch_info->type) {
5662                         case MONO_PATCH_INFO_BB:
5663                         case MONO_PATCH_INFO_LABEL:
5664                                 break;
5665                         default:
5666                                 /* No need to patch these */
5667                                 continue;
5668                         }
5669                 }
5670
5671                 switch (patch_info->type) {
5672                 case MONO_PATCH_INFO_NONE:
5673                         continue;
5674                 case MONO_PATCH_INFO_METHOD_REL:
5675                 case MONO_PATCH_INFO_R8:
5676                 case MONO_PATCH_INFO_R4:
5677                         g_assert_not_reached ();
5678                         continue;
5679                 case MONO_PATCH_INFO_BB:
5680                         break;
5681                 default:
5682                         break;
5683                 }
5684
5685                 /*
5686                  * Debug code to help track down problems where the target of a near call is
5687                  * is not valid.
5688                  */
5689                 if (amd64_is_near_call (ip)) {
5690                         gint64 disp = (guint8*)target - (guint8*)ip;
5691
5692                         if (!amd64_is_imm32 (disp)) {
5693                                 printf ("TYPE: %d\n", patch_info->type);
5694                                 switch (patch_info->type) {
5695                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5696                                         printf ("V: %s\n", patch_info->data.name);
5697                                         break;
5698                                 case MONO_PATCH_INFO_METHOD_JUMP:
5699                                 case MONO_PATCH_INFO_METHOD:
5700                                         printf ("V: %s\n", patch_info->data.method->name);
5701                                         break;
5702                                 default:
5703                                         break;
5704                                 }
5705                         }
5706                 }
5707
5708                 amd64_patch (ip, (gpointer)target);
5709         }
5710 }
5711
5712 #ifndef DISABLE_JIT
5713
5714 static int
5715 get_max_epilog_size (MonoCompile *cfg)
5716 {
5717         int max_epilog_size = 16;
5718
5719         if (cfg->method->save_lmf)
5720                 max_epilog_size += 256;
5721
5722         if (mono_jit_trace_calls != NULL)
5723                 max_epilog_size += 50;
5724
5725         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5726                 max_epilog_size += 50;
5727
5728         max_epilog_size += (AMD64_NREG * 2);
5729
5730         return max_epilog_size;
5731 }
5732
5733 /*
5734  * This macro is used for testing whenever the unwinder works correctly at every point
5735  * where an async exception can happen.
5736  */
5737 /* This will generate a SIGSEGV at the given point in the code */
5738 #define async_exc_point(code) do { \
5739     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5740          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5741              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5742          cfg->arch.async_point_count ++; \
5743     } \
5744 } while (0)
5745
5746 guint8 *
5747 mono_arch_emit_prolog (MonoCompile *cfg)
5748 {
5749         MonoMethod *method = cfg->method;
5750         MonoBasicBlock *bb;
5751         MonoMethodSignature *sig;
5752         MonoInst *ins;
5753         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5754         guint8 *code;
5755         CallInfo *cinfo;
5756         gint32 lmf_offset = cfg->arch.lmf_offset;
5757         gboolean args_clobbered = FALSE;
5758         gboolean trace = FALSE;
5759
5760         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5761
5762         code = cfg->native_code = g_malloc (cfg->code_size);
5763
5764         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5765                 trace = TRUE;
5766
5767         /* Amount of stack space allocated by register saving code */
5768         pos = 0;
5769
5770         /* Offset between RSP and the CFA */
5771         cfa_offset = 0;
5772
5773         /*
5774          * The prolog consists of the following parts:
5775          * FP present:
5776          * - push rbp, mov rbp, rsp
5777          * - save callee saved regs using pushes
5778          * - allocate frame
5779          * - save rgctx if needed
5780          * - save lmf if needed
5781          * FP not present:
5782          * - allocate frame
5783          * - save rgctx if needed
5784          * - save lmf if needed
5785          * - save callee saved regs using moves
5786          */
5787
5788         // CFA = sp + 8
5789         cfa_offset = 8;
5790         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5791         // IP saved at CFA - 8
5792         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5793         async_exc_point (code);
5794
5795         if (!cfg->arch.omit_fp) {
5796                 amd64_push_reg (code, AMD64_RBP);
5797                 cfa_offset += 8;
5798                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5799                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5800                 async_exc_point (code);
5801 #ifdef HOST_WIN32
5802                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5803 #endif
5804
5805                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5806                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5807                 async_exc_point (code);
5808 #ifdef HOST_WIN32
5809                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5810 #endif
5811         }
5812
5813         /* Save callee saved registers */
5814         if (!cfg->arch.omit_fp && !method->save_lmf) {
5815                 int offset = cfa_offset;
5816
5817                 for (i = 0; i < AMD64_NREG; ++i)
5818                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5819                                 amd64_push_reg (code, i);
5820                                 pos += sizeof (gpointer);
5821                                 offset += 8;
5822                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5823                                 async_exc_point (code);
5824                         }
5825         }
5826
5827         /* The param area is always at offset 0 from sp */
5828         /* This needs to be allocated here, since it has to come after the spill area */
5829         if (cfg->arch.no_pushes && cfg->param_area) {
5830                 if (cfg->arch.omit_fp)
5831                         // FIXME:
5832                         g_assert_not_reached ();
5833                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5834         }
5835
5836         if (cfg->arch.omit_fp) {
5837                 /*
5838                  * On enter, the stack is misaligned by the the pushing of the return
5839                  * address. It is either made aligned by the pushing of %rbp, or by
5840                  * this.
5841                  */
5842                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5843                 if ((alloc_size % 16) == 0)
5844                         alloc_size += 8;
5845         } else {
5846                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5847
5848                 alloc_size -= pos;
5849         }
5850
5851         cfg->arch.stack_alloc_size = alloc_size;
5852
5853         /* Allocate stack frame */
5854         if (alloc_size) {
5855                 /* See mono_emit_stack_alloc */
5856 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5857                 guint32 remaining_size = alloc_size;
5858                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5859                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5860                 guint32 offset = code - cfg->native_code;
5861                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5862                         while (required_code_size >= (cfg->code_size - offset))
5863                                 cfg->code_size *= 2;
5864                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5865                         code = cfg->native_code + offset;
5866                         mono_jit_stats.code_reallocs++;
5867                 }
5868
5869                 while (remaining_size >= 0x1000) {
5870                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5871                         if (cfg->arch.omit_fp) {
5872                                 cfa_offset += 0x1000;
5873                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5874                         }
5875                         async_exc_point (code);
5876 #ifdef HOST_WIN32
5877                         if (cfg->arch.omit_fp)
5878                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5879 #endif
5880
5881                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5882                         remaining_size -= 0x1000;
5883                 }
5884                 if (remaining_size) {
5885                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5886                         if (cfg->arch.omit_fp) {
5887                                 cfa_offset += remaining_size;
5888                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5889                                 async_exc_point (code);
5890                         }
5891 #ifdef HOST_WIN32
5892                         if (cfg->arch.omit_fp)
5893                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5894 #endif
5895                 }
5896 #else
5897                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5898                 if (cfg->arch.omit_fp) {
5899                         cfa_offset += alloc_size;
5900                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5901                         async_exc_point (code);
5902                 }
5903 #endif
5904         }
5905
5906         /* Stack alignment check */
5907 #if 0
5908         {
5909                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5910                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5911                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5912                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5913                 amd64_breakpoint (code);
5914         }
5915 #endif
5916
5917 #ifndef TARGET_WIN32
5918         if (mini_get_debug_options ()->init_stacks) {
5919                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5920
5921                 /* Save registers to the red zone */
5922                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5923                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5924
5925                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5926                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5927                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5928
5929                 amd64_cld (code);
5930                 amd64_prefix (code, X86_REP_PREFIX);
5931                 amd64_stosl (code);
5932
5933                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5934                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5935         }
5936 #endif
5937
5938         /* Save LMF */
5939         if (method->save_lmf) {
5940                 /*
5941                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5942                  */
5943                 /*
5944                  * sp is saved right before calls but we need to save it here too so
5945                  * async stack walks would work.
5946                  */
5947                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5948                 /* Skip method (only needed for trampoline LMF frames) */
5949                 /* Save callee saved regs */
5950                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5951                         int offset;
5952
5953                         switch (i) {
5954                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5955                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5956                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5957                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5958                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5959                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5960 #ifdef HOST_WIN32
5961                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5962                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5963 #endif
5964                         default:
5965                                 offset = -1;
5966                                 break;
5967                         }
5968
5969                         if (offset != -1) {
5970                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5971                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5972                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5973                         }
5974                 }
5975         }
5976
5977         /* Save callee saved registers */
5978         if (cfg->arch.omit_fp && !method->save_lmf) {
5979                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5980
5981                 /* Save caller saved registers after sp is adjusted */
5982                 /* The registers are saved at the bottom of the frame */
5983                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5984                 for (i = 0; i < AMD64_NREG; ++i)
5985                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5986                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5987                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5988                                 save_area_offset += 8;
5989                                 async_exc_point (code);
5990                         }
5991         }
5992
5993         /* store runtime generic context */
5994         if (cfg->rgctx_var) {
5995                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5996                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5997
5998                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5999         }
6000
6001         /* compute max_length in order to use short forward jumps */
6002         max_epilog_size = get_max_epilog_size (cfg);
6003         if (cfg->opt & MONO_OPT_BRANCH) {
6004                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6005                         MonoInst *ins;
6006                         int max_length = 0;
6007
6008                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6009                                 max_length += 6;
6010                         /* max alignment for loops */
6011                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6012                                 max_length += LOOP_ALIGNMENT;
6013
6014                         MONO_BB_FOR_EACH_INS (bb, ins) {
6015                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6016                         }
6017
6018                         /* Take prolog and epilog instrumentation into account */
6019                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6020                                 max_length += max_epilog_size;
6021
6022                         bb->max_length = max_length;
6023                 }
6024         }
6025
6026         sig = mono_method_signature (method);
6027         pos = 0;
6028
6029         cinfo = cfg->arch.cinfo;
6030
6031         if (sig->ret->type != MONO_TYPE_VOID) {
6032                 /* Save volatile arguments to the stack */
6033                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6034                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6035         }
6036
6037         /* Keep this in sync with emit_load_volatile_arguments */
6038         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6039                 ArgInfo *ainfo = cinfo->args + i;
6040                 gint32 stack_offset;
6041                 MonoType *arg_type;
6042
6043                 ins = cfg->args [i];
6044
6045                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6046                         /* Unused arguments */
6047                         continue;
6048
6049                 if (sig->hasthis && (i == 0))
6050                         arg_type = &mono_defaults.object_class->byval_arg;
6051                 else
6052                         arg_type = sig->params [i - sig->hasthis];
6053
6054                 stack_offset = ainfo->offset + ARGS_OFFSET;
6055
6056                 if (cfg->globalra) {
6057                         /* All the other moves are done by the register allocator */
6058                         switch (ainfo->storage) {
6059                         case ArgInFloatSSEReg:
6060                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6061                                 break;
6062                         case ArgValuetypeInReg:
6063                                 for (quad = 0; quad < 2; quad ++) {
6064                                         switch (ainfo->pair_storage [quad]) {
6065                                         case ArgInIReg:
6066                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6067                                                 break;
6068                                         case ArgInFloatSSEReg:
6069                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6070                                                 break;
6071                                         case ArgInDoubleSSEReg:
6072                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6073                                                 break;
6074                                         case ArgNone:
6075                                                 break;
6076                                         default:
6077                                                 g_assert_not_reached ();
6078                                         }
6079                                 }
6080                                 break;
6081                         default:
6082                                 break;
6083                         }
6084
6085                         continue;
6086                 }
6087
6088                 /* Save volatile arguments to the stack */
6089                 if (ins->opcode != OP_REGVAR) {
6090                         switch (ainfo->storage) {
6091                         case ArgInIReg: {
6092                                 guint32 size = 8;
6093
6094                                 /* FIXME: I1 etc */
6095                                 /*
6096                                 if (stack_offset & 0x1)
6097                                         size = 1;
6098                                 else if (stack_offset & 0x2)
6099                                         size = 2;
6100                                 else if (stack_offset & 0x4)
6101                                         size = 4;
6102                                 else
6103                                         size = 8;
6104                                 */
6105                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6106                                 break;
6107                         }
6108                         case ArgInFloatSSEReg:
6109                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6110                                 break;
6111                         case ArgInDoubleSSEReg:
6112                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6113                                 break;
6114                         case ArgValuetypeInReg:
6115                                 for (quad = 0; quad < 2; quad ++) {
6116                                         switch (ainfo->pair_storage [quad]) {
6117                                         case ArgInIReg:
6118                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6119                                                 break;
6120                                         case ArgInFloatSSEReg:
6121                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6122                                                 break;
6123                                         case ArgInDoubleSSEReg:
6124                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6125                                                 break;
6126                                         case ArgNone:
6127                                                 break;
6128                                         default:
6129                                                 g_assert_not_reached ();
6130                                         }
6131                                 }
6132                                 break;
6133                         case ArgValuetypeAddrInIReg:
6134                                 if (ainfo->pair_storage [0] == ArgInIReg)
6135                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6136                                 break;
6137                         default:
6138                                 break;
6139                         }
6140                 } else {
6141                         /* Argument allocated to (non-volatile) register */
6142                         switch (ainfo->storage) {
6143                         case ArgInIReg:
6144                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6145                                 break;
6146                         case ArgOnStack:
6147                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6148                                 break;
6149                         default:
6150                                 g_assert_not_reached ();
6151                         }
6152                 }
6153         }
6154
6155         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6156         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6157                 guint64 domain = (guint64)cfg->domain;
6158
6159                 args_clobbered = TRUE;
6160
6161                 /*
6162                  * The call might clobber argument registers, but they are already
6163                  * saved to the stack/global regs.
6164                  */
6165                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6166                         guint8 *buf, *no_domain_branch;
6167
6168                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6169                         if (cfg->compile_aot) {
6170                                 /* AOT code is only used in the root domain */
6171                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6172                         } else {
6173                                 if ((domain >> 32) == 0)
6174                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6175                                 else
6176                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6177                         }
6178                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6179                         no_domain_branch = code;
6180                         x86_branch8 (code, X86_CC_NE, 0, 0);
6181                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6182                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6183                         buf = code;
6184                         x86_branch8 (code, X86_CC_NE, 0, 0);
6185                         amd64_patch (no_domain_branch, code);
6186                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6187                                           (gpointer)"mono_jit_thread_attach", TRUE);
6188                         amd64_patch (buf, code);
6189 #ifdef HOST_WIN32
6190                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6191                         /* FIXME: Add a separate key for LMF to avoid this */
6192                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6193 #endif
6194                 } else {
6195                         g_assert (!cfg->compile_aot);
6196                         if (cfg->compile_aot) {
6197                                 /* AOT code is only used in the root domain */
6198                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6199                         } else {
6200                                 if ((domain >> 32) == 0)
6201                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6202                                 else
6203                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6204                         }
6205                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6206                                           (gpointer)"mono_jit_thread_attach", TRUE);
6207                 }
6208         }
6209
6210         if (method->save_lmf) {
6211                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6212                         /*
6213                          * Optimized version which uses the mono_lmf TLS variable instead of
6214                          * indirection through the mono_lmf_addr TLS variable.
6215                          */
6216                         /* %rax = previous_lmf */
6217                         x86_prefix (code, X86_FS_PREFIX);
6218                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6219
6220                         /* Save previous_lmf */
6221                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6222                         /* Set new lmf */
6223                         if (lmf_offset == 0) {
6224                                 x86_prefix (code, X86_FS_PREFIX);
6225                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6226                         } else {
6227                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6228                                 x86_prefix (code, X86_FS_PREFIX);
6229                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6230                         }
6231                 } else {
6232                         if (lmf_addr_tls_offset != -1) {
6233                                 /* Load lmf quicky using the FS register */
6234                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6235 #ifdef HOST_WIN32
6236                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6237                                 /* FIXME: Add a separate key for LMF to avoid this */
6238                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6239 #endif
6240                         }
6241                         else {
6242                                 /*
6243                                  * The call might clobber argument registers, but they are already
6244                                  * saved to the stack/global regs.
6245                                  */
6246                                 args_clobbered = TRUE;
6247                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6248                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6249                         }
6250
6251                         /* Save lmf_addr */
6252                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6253                         /* Save previous_lmf */
6254                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6255                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6256                         /* Set new lmf */
6257                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6258                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6259                 }
6260         }
6261
6262         if (trace) {
6263                 args_clobbered = TRUE;
6264                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6265         }
6266
6267         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6268                 args_clobbered = TRUE;
6269
6270         /*
6271          * Optimize the common case of the first bblock making a call with the same
6272          * arguments as the method. This works because the arguments are still in their
6273          * original argument registers.
6274          * FIXME: Generalize this
6275          */
6276         if (!args_clobbered) {
6277                 MonoBasicBlock *first_bb = cfg->bb_entry;
6278                 MonoInst *next;
6279
6280                 next = mono_bb_first_ins (first_bb);
6281                 if (!next && first_bb->next_bb) {
6282                         first_bb = first_bb->next_bb;
6283                         next = mono_bb_first_ins (first_bb);
6284                 }
6285
6286                 if (first_bb->in_count > 1)
6287                         next = NULL;
6288
6289                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6290                         ArgInfo *ainfo = cinfo->args + i;
6291                         gboolean match = FALSE;
6292
6293                         ins = cfg->args [i];
6294                         if (ins->opcode != OP_REGVAR) {
6295                                 switch (ainfo->storage) {
6296                                 case ArgInIReg: {
6297                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6298                                                 if (next->dreg == ainfo->reg) {
6299                                                         NULLIFY_INS (next);
6300                                                         match = TRUE;
6301                                                 } else {
6302                                                         next->opcode = OP_MOVE;
6303                                                         next->sreg1 = ainfo->reg;
6304                                                         /* Only continue if the instruction doesn't change argument regs */
6305                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6306                                                                 match = TRUE;
6307                                                 }
6308                                         }
6309                                         break;
6310                                 }
6311                                 default:
6312                                         break;
6313                                 }
6314                         } else {
6315                                 /* Argument allocated to (non-volatile) register */
6316                                 switch (ainfo->storage) {
6317                                 case ArgInIReg:
6318                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6319                                                 NULLIFY_INS (next);
6320                                                 match = TRUE;
6321                                         }
6322                                         break;
6323                                 default:
6324                                         break;
6325                                 }
6326                         }
6327
6328                         if (match) {
6329                                 next = next->next;
6330                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6331                                 if (!next)
6332                                         break;
6333                         }
6334                 }
6335         }
6336
6337         /* Initialize ss_trigger_page_var */
6338         if (cfg->arch.ss_trigger_page_var) {
6339                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6340
6341                 g_assert (!cfg->compile_aot);
6342                 g_assert (var->opcode == OP_REGOFFSET);
6343
6344                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6345                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6346         }
6347
6348         cfg->code_len = code - cfg->native_code;
6349
6350         g_assert (cfg->code_len < cfg->code_size);
6351
6352         return code;
6353 }
6354
6355 void
6356 mono_arch_emit_epilog (MonoCompile *cfg)
6357 {
6358         MonoMethod *method = cfg->method;
6359         int quad, pos, i;
6360         guint8 *code;
6361         int max_epilog_size;
6362         CallInfo *cinfo;
6363         gint32 lmf_offset = cfg->arch.lmf_offset;
6364
6365         max_epilog_size = get_max_epilog_size (cfg);
6366
6367         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6368                 cfg->code_size *= 2;
6369                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6370                 mono_jit_stats.code_reallocs++;
6371         }
6372
6373         code = cfg->native_code + cfg->code_len;
6374
6375         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6376                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6377
6378         /* the code restoring the registers must be kept in sync with OP_JMP */
6379         pos = 0;
6380
6381         if (method->save_lmf) {
6382                 /* check if we need to restore protection of the stack after a stack overflow */
6383                 if (mono_get_jit_tls_offset () != -1) {
6384                         guint8 *patch;
6385                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6386                         /* we load the value in a separate instruction: this mechanism may be
6387                          * used later as a safer way to do thread interruption
6388                          */
6389                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6390                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6391                         patch = code;
6392                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6393                         /* note that the call trampoline will preserve eax/edx */
6394                         x86_call_reg (code, X86_ECX);
6395                         x86_patch (patch, code);
6396                 } else {
6397                         /* FIXME: maybe save the jit tls in the prolog */
6398                 }
6399                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6400                         /*
6401                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6402                          * through the mono_lmf_addr TLS variable.
6403                          */
6404                         /* reg = previous_lmf */
6405                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6406                         x86_prefix (code, X86_FS_PREFIX);
6407                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6408                 } else {
6409                         /* Restore previous lmf */
6410                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6411                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6412                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6413                 }
6414
6415                 /* Restore caller saved regs */
6416                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6417                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6418                 }
6419                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6420                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6421                 }
6422                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6423                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6424                 }
6425                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6426                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6427                 }
6428                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6429                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6430                 }
6431                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6432                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6433                 }
6434 #ifdef HOST_WIN32
6435                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6436                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6437                 }
6438                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6439                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6440                 }
6441 #endif
6442         } else {
6443
6444                 if (cfg->arch.omit_fp) {
6445                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6446
6447                         for (i = 0; i < AMD64_NREG; ++i)
6448                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6449                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6450                                         save_area_offset += 8;
6451                                 }
6452                 }
6453                 else {
6454                         for (i = 0; i < AMD64_NREG; ++i)
6455                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6456                                         pos -= sizeof (gpointer);
6457
6458                         if (pos) {
6459                                 if (pos == - sizeof (gpointer)) {
6460                                         /* Only one register, so avoid lea */
6461                                         for (i = AMD64_NREG - 1; i > 0; --i)
6462                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6463                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6464                                                 }
6465                                 }
6466                                 else {
6467                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6468
6469                                         /* Pop registers in reverse order */
6470                                         for (i = AMD64_NREG - 1; i > 0; --i)
6471                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6472                                                         amd64_pop_reg (code, i);
6473                                                 }
6474                                 }
6475                         }
6476                 }
6477         }
6478
6479         /* Load returned vtypes into registers if needed */
6480         cinfo = cfg->arch.cinfo;
6481         if (cinfo->ret.storage == ArgValuetypeInReg) {
6482                 ArgInfo *ainfo = &cinfo->ret;
6483                 MonoInst *inst = cfg->ret;
6484
6485                 for (quad = 0; quad < 2; quad ++) {
6486                         switch (ainfo->pair_storage [quad]) {
6487                         case ArgInIReg:
6488                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6489                                 break;
6490                         case ArgInFloatSSEReg:
6491                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6492                                 break;
6493                         case ArgInDoubleSSEReg:
6494                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6495                                 break;
6496                         case ArgNone:
6497                                 break;
6498                         default:
6499                                 g_assert_not_reached ();
6500                         }
6501                 }
6502         }
6503
6504         if (cfg->arch.omit_fp) {
6505                 if (cfg->arch.stack_alloc_size)
6506                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6507         } else {
6508                 amd64_leave (code);
6509         }
6510         async_exc_point (code);
6511         amd64_ret (code);
6512
6513         cfg->code_len = code - cfg->native_code;
6514
6515         g_assert (cfg->code_len < cfg->code_size);
6516 }
6517
6518 void
6519 mono_arch_emit_exceptions (MonoCompile *cfg)
6520 {
6521         MonoJumpInfo *patch_info;
6522         int nthrows, i;
6523         guint8 *code;
6524         MonoClass *exc_classes [16];
6525         guint8 *exc_throw_start [16], *exc_throw_end [16];
6526         guint32 code_size = 0;
6527
6528         /* Compute needed space */
6529         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6530                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6531                         code_size += 40;
6532                 if (patch_info->type == MONO_PATCH_INFO_R8)
6533                         code_size += 8 + 15; /* sizeof (double) + alignment */
6534                 if (patch_info->type == MONO_PATCH_INFO_R4)
6535                         code_size += 4 + 15; /* sizeof (float) + alignment */
6536                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
6537                         code_size += 8 + 7; /*sizeof (void*) + alignment */
6538         }
6539
6540         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6541                 cfg->code_size *= 2;
6542                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6543                 mono_jit_stats.code_reallocs++;
6544         }
6545
6546         code = cfg->native_code + cfg->code_len;
6547
6548         /* add code to raise exceptions */
6549         nthrows = 0;
6550         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6551                 switch (patch_info->type) {
6552                 case MONO_PATCH_INFO_EXC: {
6553                         MonoClass *exc_class;
6554                         guint8 *buf, *buf2;
6555                         guint32 throw_ip;
6556
6557                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6558
6559                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6560                         g_assert (exc_class);
6561                         throw_ip = patch_info->ip.i;
6562
6563                         //x86_breakpoint (code);
6564                         /* Find a throw sequence for the same exception class */
6565                         for (i = 0; i < nthrows; ++i)
6566                                 if (exc_classes [i] == exc_class)
6567                                         break;
6568                         if (i < nthrows) {
6569                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6570                                 x86_jump_code (code, exc_throw_start [i]);
6571                                 patch_info->type = MONO_PATCH_INFO_NONE;
6572                         }
6573                         else {
6574                                 buf = code;
6575                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6576                                 buf2 = code;
6577
6578                                 if (nthrows < 16) {
6579                                         exc_classes [nthrows] = exc_class;
6580                                         exc_throw_start [nthrows] = code;
6581                                 }
6582                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6583
6584                                 patch_info->type = MONO_PATCH_INFO_NONE;
6585
6586                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6587
6588                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6589                                 while (buf < buf2)
6590                                         x86_nop (buf);
6591
6592                                 if (nthrows < 16) {
6593                                         exc_throw_end [nthrows] = code;
6594                                         nthrows ++;
6595                                 }
6596                         }
6597                         break;
6598                 }
6599                 default:
6600                         /* do nothing */
6601                         break;
6602                 }
6603         }
6604
6605         /* Handle relocations with RIP relative addressing */
6606         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6607                 gboolean remove = FALSE;
6608
6609                 switch (patch_info->type) {
6610                 case MONO_PATCH_INFO_R8:
6611                 case MONO_PATCH_INFO_R4: {
6612                         guint8 *pos;
6613
6614                         /* The SSE opcodes require a 16 byte alignment */
6615                         code = (guint8*)ALIGN_TO (code, 16);
6616
6617                         pos = cfg->native_code + patch_info->ip.i;
6618
6619                         if (IS_REX (pos [1]))
6620                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6621                         else
6622                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6623
6624                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6625                                 *(double*)code = *(double*)patch_info->data.target;
6626                                 code += sizeof (double);
6627                         } else {
6628                                 *(float*)code = *(float*)patch_info->data.target;
6629                                 code += sizeof (float);
6630                         }
6631
6632                         remove = TRUE;
6633                         break;
6634                 }
6635                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
6636                         guint8 *pos;
6637
6638                         if (cfg->compile_aot)
6639                                 continue;
6640
6641                         /*loading is faster against aligned addresses.*/
6642                         code = (guint8*)ALIGN_TO (code, 8);
6643
6644                         pos = cfg->native_code + patch_info->ip.i;
6645
6646                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
6647                         if (IS_REX (pos [1]))
6648                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6649                         else
6650                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
6651
6652                         *(gpointer*)code = (gpointer)patch_info->data.target;
6653                         code += sizeof (gpointer);
6654
6655                         remove = TRUE;
6656                         break;
6657                 }
6658                 default:
6659                         break;
6660                 }
6661
6662                 if (remove) {
6663                         if (patch_info == cfg->patch_info)
6664                                 cfg->patch_info = patch_info->next;
6665                         else {
6666                                 MonoJumpInfo *tmp;
6667
6668                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6669                                         ;
6670                                 tmp->next = patch_info->next;
6671                         }
6672                 }
6673         }
6674
6675         cfg->code_len = code - cfg->native_code;
6676
6677         g_assert (cfg->code_len < cfg->code_size);
6678
6679 }
6680
6681 #endif /* DISABLE_JIT */
6682
6683 void*
6684 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6685 {
6686         guchar *code = p;
6687         CallInfo *cinfo = NULL;
6688         MonoMethodSignature *sig;
6689         MonoInst *inst;
6690         int i, n, stack_area = 0;
6691
6692         /* Keep this in sync with mono_arch_get_argument_info */
6693
6694         if (enable_arguments) {
6695                 /* Allocate a new area on the stack and save arguments there */
6696                 sig = mono_method_signature (cfg->method);
6697
6698                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6699
6700                 n = sig->param_count + sig->hasthis;
6701
6702                 stack_area = ALIGN_TO (n * 8, 16);
6703
6704                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6705
6706                 for (i = 0; i < n; ++i) {
6707                         inst = cfg->args [i];
6708
6709                         if (inst->opcode == OP_REGVAR)
6710                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6711                         else {
6712                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6713                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6714                         }
6715                 }
6716         }
6717
6718         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6719         amd64_set_reg_template (code, AMD64_ARG_REG1);
6720         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6721         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6722
6723         if (enable_arguments)
6724                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6725
6726         return code;
6727 }
6728
6729 enum {
6730         SAVE_NONE,
6731         SAVE_STRUCT,
6732         SAVE_EAX,
6733         SAVE_EAX_EDX,
6734         SAVE_XMM
6735 };
6736
6737 void*
6738 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6739 {
6740         guchar *code = p;
6741         int save_mode = SAVE_NONE;
6742         MonoMethod *method = cfg->method;
6743         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6744
6745         switch (ret_type->type) {
6746         case MONO_TYPE_VOID:
6747                 /* special case string .ctor icall */
6748                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6749                         save_mode = SAVE_EAX;
6750                 else
6751                         save_mode = SAVE_NONE;
6752                 break;
6753         case MONO_TYPE_I8:
6754         case MONO_TYPE_U8:
6755                 save_mode = SAVE_EAX;
6756                 break;
6757         case MONO_TYPE_R4:
6758         case MONO_TYPE_R8:
6759                 save_mode = SAVE_XMM;
6760                 break;
6761         case MONO_TYPE_GENERICINST:
6762                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6763                         save_mode = SAVE_EAX;
6764                         break;
6765                 }
6766                 /* Fall through */
6767         case MONO_TYPE_VALUETYPE:
6768                 save_mode = SAVE_STRUCT;
6769                 break;
6770         default:
6771                 save_mode = SAVE_EAX;
6772                 break;
6773         }
6774
6775         /* Save the result and copy it into the proper argument register */
6776         switch (save_mode) {
6777         case SAVE_EAX:
6778                 amd64_push_reg (code, AMD64_RAX);
6779                 /* Align stack */
6780                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6781                 if (enable_arguments)
6782                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6783                 break;
6784         case SAVE_STRUCT:
6785                 /* FIXME: */
6786                 if (enable_arguments)
6787                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6788                 break;
6789         case SAVE_XMM:
6790                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6791                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6792                 /* Align stack */
6793                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6794                 /*
6795                  * The result is already in the proper argument register so no copying
6796                  * needed.
6797                  */
6798                 break;
6799         case SAVE_NONE:
6800                 break;
6801         default:
6802                 g_assert_not_reached ();
6803         }
6804
6805         /* Set %al since this is a varargs call */
6806         if (save_mode == SAVE_XMM)
6807                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6808         else
6809                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6810
6811         if (preserve_argument_registers) {
6812                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6813                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6814         }
6815
6816         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6817         amd64_set_reg_template (code, AMD64_ARG_REG1);
6818         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6819
6820         if (preserve_argument_registers) {
6821                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6822                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6823         }
6824
6825         /* Restore result */
6826         switch (save_mode) {
6827         case SAVE_EAX:
6828                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6829                 amd64_pop_reg (code, AMD64_RAX);
6830                 break;
6831         case SAVE_STRUCT:
6832                 /* FIXME: */
6833                 break;
6834         case SAVE_XMM:
6835                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6836                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6837                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6838                 break;
6839         case SAVE_NONE:
6840                 break;
6841         default:
6842                 g_assert_not_reached ();
6843         }
6844
6845         return code;
6846 }
6847
6848 void
6849 mono_arch_flush_icache (guint8 *code, gint size)
6850 {
6851         /* Not needed */
6852 }
6853
6854 void
6855 mono_arch_flush_register_windows (void)
6856 {
6857 }
6858
6859 gboolean
6860 mono_arch_is_inst_imm (gint64 imm)
6861 {
6862         return amd64_is_imm32 (imm);
6863 }
6864
6865 /*
6866  * Determine whenever the trap whose info is in SIGINFO is caused by
6867  * integer overflow.
6868  */
6869 gboolean
6870 mono_arch_is_int_overflow (void *sigctx, void *info)
6871 {
6872         MonoContext ctx;
6873         guint8* rip;
6874         int reg;
6875         gint64 value;
6876
6877         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6878
6879         rip = (guint8*)ctx.rip;
6880
6881         if (IS_REX (rip [0])) {
6882                 reg = amd64_rex_b (rip [0]);
6883                 rip ++;
6884         }
6885         else
6886                 reg = 0;
6887
6888         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6889                 /* idiv REG */
6890                 reg += x86_modrm_rm (rip [1]);
6891
6892                 switch (reg) {
6893                 case AMD64_RAX:
6894                         value = ctx.rax;
6895                         break;
6896                 case AMD64_RBX:
6897                         value = ctx.rbx;
6898                         break;
6899                 case AMD64_RCX:
6900                         value = ctx.rcx;
6901                         break;
6902                 case AMD64_RDX:
6903                         value = ctx.rdx;
6904                         break;
6905                 case AMD64_RBP:
6906                         value = ctx.rbp;
6907                         break;
6908                 case AMD64_RSP:
6909                         value = ctx.rsp;
6910                         break;
6911                 case AMD64_RSI:
6912                         value = ctx.rsi;
6913                         break;
6914                 case AMD64_RDI:
6915                         value = ctx.rdi;
6916                         break;
6917                 case AMD64_R12:
6918                         value = ctx.r12;
6919                         break;
6920                 case AMD64_R13:
6921                         value = ctx.r13;
6922                         break;
6923                 case AMD64_R14:
6924                         value = ctx.r14;
6925                         break;
6926                 case AMD64_R15:
6927                         value = ctx.r15;
6928                         break;
6929                 default:
6930                         g_assert_not_reached ();
6931                         reg = -1;
6932                 }
6933
6934                 if (value == -1)
6935                         return TRUE;
6936         }
6937
6938         return FALSE;
6939 }
6940
6941 guint32
6942 mono_arch_get_patch_offset (guint8 *code)
6943 {
6944         return 3;
6945 }
6946
6947 /**
6948  * mono_breakpoint_clean_code:
6949  *
6950  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6951  * breakpoints in the original code, they are removed in the copy.
6952  *
6953  * Returns TRUE if no sw breakpoint was present.
6954  */
6955 gboolean
6956 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6957 {
6958         int i;
6959         gboolean can_write = TRUE;
6960         /*
6961          * If method_start is non-NULL we need to perform bound checks, since we access memory
6962          * at code - offset we could go before the start of the method and end up in a different
6963          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6964          * instead.
6965          */
6966         if (!method_start || code - offset >= method_start) {
6967                 memcpy (buf, code - offset, size);
6968         } else {
6969                 int diff = code - method_start;
6970                 memset (buf, 0, size);
6971                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6972         }
6973         code -= offset;
6974         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6975                 int idx = mono_breakpoint_info_index [i];
6976                 guint8 *ptr;
6977                 if (idx < 1)
6978                         continue;
6979                 ptr = mono_breakpoint_info [idx].address;
6980                 if (ptr >= code && ptr < code + size) {
6981                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6982                         can_write = FALSE;
6983                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6984                         buf [ptr - code] = saved_byte;
6985                 }
6986         }
6987         return can_write;
6988 }
6989
6990 int
6991 mono_arch_get_this_arg_reg (guint8 *code)
6992 {
6993         return AMD64_ARG_REG1;
6994 }
6995
6996 gpointer
6997 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6998 {
6999         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7000 }
7001
7002 #define MAX_ARCH_DELEGATE_PARAMS 10
7003
7004 static gpointer
7005 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7006 {
7007         guint8 *code, *start;
7008         int i;
7009
7010         if (has_target) {
7011                 start = code = mono_global_codeman_reserve (64);
7012
7013                 /* Replace the this argument with the target */
7014                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7015                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7016                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7017
7018                 g_assert ((code - start) < 64);
7019         } else {
7020                 start = code = mono_global_codeman_reserve (64);
7021
7022                 if (param_count == 0) {
7023                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7024                 } else {
7025                         /* We have to shift the arguments left */
7026                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7027                         for (i = 0; i < param_count; ++i) {
7028 #ifdef HOST_WIN32
7029                                 if (i < 3)
7030                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7031                                 else
7032                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7033 #else
7034                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7035 #endif
7036                         }
7037
7038                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7039                 }
7040                 g_assert ((code - start) < 64);
7041         }
7042
7043         mono_debug_add_delegate_trampoline (start, code - start);
7044
7045         if (code_len)
7046                 *code_len = code - start;
7047
7048
7049         if (mono_jit_map_is_enabled ()) {
7050                 char *buff;
7051                 if (has_target)
7052                         buff = (char*)"delegate_invoke_has_target";
7053                 else
7054                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7055                 mono_emit_jit_tramp (start, code - start, buff);
7056                 if (!has_target)
7057                         g_free (buff);
7058         }
7059
7060         return start;
7061 }
7062
7063 /*
7064  * mono_arch_get_delegate_invoke_impls:
7065  *
7066  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7067  * trampolines.
7068  */
7069 GSList*
7070 mono_arch_get_delegate_invoke_impls (void)
7071 {
7072         GSList *res = NULL;
7073         guint8 *code;
7074         guint32 code_len;
7075         int i;
7076
7077         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7078         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7079
7080         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7081                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7082                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7083         }
7084
7085         return res;
7086 }
7087
7088 gpointer
7089 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7090 {
7091         guint8 *code, *start;
7092         int i;
7093
7094         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7095                 return NULL;
7096
7097         /* FIXME: Support more cases */
7098         if (MONO_TYPE_ISSTRUCT (sig->ret))
7099                 return NULL;
7100
7101         if (has_target) {
7102                 static guint8* cached = NULL;
7103
7104                 if (cached)
7105                         return cached;
7106
7107                 if (mono_aot_only)
7108                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7109                 else
7110                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7111
7112                 mono_memory_barrier ();
7113
7114                 cached = start;
7115         } else {
7116                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7117                 for (i = 0; i < sig->param_count; ++i)
7118                         if (!mono_is_regsize_var (sig->params [i]))
7119                                 return NULL;
7120                 if (sig->param_count > 4)
7121                         return NULL;
7122
7123                 code = cache [sig->param_count];
7124                 if (code)
7125                         return code;
7126
7127                 if (mono_aot_only) {
7128                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7129                         start = mono_aot_get_trampoline (name);
7130                         g_free (name);
7131                 } else {
7132                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7133                 }
7134
7135                 mono_memory_barrier ();
7136
7137                 cache [sig->param_count] = start;
7138         }
7139
7140         return start;
7141 }
7142
7143 /*
7144  * Support for fast access to the thread-local lmf structure using the GS
7145  * segment register on NPTL + kernel 2.6.x.
7146  */
7147
7148 static gboolean tls_offset_inited = FALSE;
7149
7150 void
7151 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7152 {
7153         if (!tls_offset_inited) {
7154 #ifdef HOST_WIN32
7155                 /*
7156                  * We need to init this multiple times, since when we are first called, the key might not
7157                  * be initialized yet.
7158                  */
7159                 appdomain_tls_offset = mono_domain_get_tls_key ();
7160                 lmf_tls_offset = mono_get_jit_tls_key ();
7161                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7162
7163                 /* Only 64 tls entries can be accessed using inline code */
7164                 if (appdomain_tls_offset >= 64)
7165                         appdomain_tls_offset = -1;
7166                 if (lmf_tls_offset >= 64)
7167                         lmf_tls_offset = -1;
7168 #else
7169                 tls_offset_inited = TRUE;
7170 #ifdef MONO_XEN_OPT
7171                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7172 #endif
7173                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7174                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7175                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7176 #endif
7177         }
7178 }
7179
7180 void
7181 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7182 {
7183 }
7184
7185 #ifdef MONO_ARCH_HAVE_IMT
7186
7187 #define CMP_SIZE (6 + 1)
7188 #define CMP_REG_REG_SIZE (4 + 1)
7189 #define BR_SMALL_SIZE 2
7190 #define BR_LARGE_SIZE 6
7191 #define MOV_REG_IMM_SIZE 10
7192 #define MOV_REG_IMM_32BIT_SIZE 6
7193 #define JUMP_REG_SIZE (2 + 1)
7194
7195 static int
7196 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7197 {
7198         int i, distance = 0;
7199         for (i = start; i < target; ++i)
7200                 distance += imt_entries [i]->chunk_size;
7201         return distance;
7202 }
7203
7204 /*
7205  * LOCKING: called with the domain lock held
7206  */
7207 gpointer
7208 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7209         gpointer fail_tramp)
7210 {
7211         int i;
7212         int size = 0;
7213         guint8 *code, *start;
7214         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7215
7216         for (i = 0; i < count; ++i) {
7217                 MonoIMTCheckItem *item = imt_entries [i];
7218                 if (item->is_equals) {
7219                         if (item->check_target_idx) {
7220                                 if (!item->compare_done) {
7221                                         if (amd64_is_imm32 (item->key))
7222                                                 item->chunk_size += CMP_SIZE;
7223                                         else
7224                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7225                                 }
7226                                 if (item->has_target_code) {
7227                                         item->chunk_size += MOV_REG_IMM_SIZE;
7228                                 } else {
7229                                         if (vtable_is_32bit)
7230                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7231                                         else
7232                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7233                                 }
7234                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7235                         } else {
7236                                 if (fail_tramp) {
7237                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7238                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7239                                 } else {
7240                                         if (vtable_is_32bit)
7241                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7242                                         else
7243                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7244                                         item->chunk_size += JUMP_REG_SIZE;
7245                                         /* with assert below:
7246                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7247                                          */
7248                                 }
7249                         }
7250                 } else {
7251                         if (amd64_is_imm32 (item->key))
7252                                 item->chunk_size += CMP_SIZE;
7253                         else
7254                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7255                         item->chunk_size += BR_LARGE_SIZE;
7256                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7257                 }
7258                 size += item->chunk_size;
7259         }
7260         if (fail_tramp)
7261                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7262         else
7263                 code = mono_domain_code_reserve (domain, size);
7264         start = code;
7265         for (i = 0; i < count; ++i) {
7266                 MonoIMTCheckItem *item = imt_entries [i];
7267                 item->code_target = code;
7268                 if (item->is_equals) {
7269                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7270
7271                         if (item->check_target_idx || fail_case) {
7272                                 if (!item->compare_done || fail_case) {
7273                                         if (amd64_is_imm32 (item->key))
7274                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7275                                         else {
7276                                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7277                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7278                                         }
7279                                 }
7280                                 item->jmp_code = code;
7281                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7282                                 if (item->has_target_code) {
7283                                         amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7284                                         amd64_jump_reg (code, AMD64_R11);
7285                                 } else {
7286                                         amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7287                                         amd64_jump_membase (code, AMD64_R11, 0);
7288                                 }
7289
7290                                 if (fail_case) {
7291                                         amd64_patch (item->jmp_code, code);
7292                                         amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7293                                         amd64_jump_reg (code, AMD64_R11);
7294                                         item->jmp_code = NULL;
7295                                 }
7296                         } else {
7297                                 /* enable the commented code to assert on wrong method */
7298 #if 0
7299                                 if (amd64_is_imm32 (item->key))
7300                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7301                                 else {
7302                                         amd64_mov_reg_imm (code, AMD64_R11, item->key);
7303                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7304                                 }
7305                                 item->jmp_code = code;
7306                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7307                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7308                                 amd64_jump_membase (code, AMD64_R11, 0);
7309                                 amd64_patch (item->jmp_code, code);
7310                                 amd64_breakpoint (code);
7311                                 item->jmp_code = NULL;
7312 #else
7313                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7314                                 amd64_jump_membase (code, AMD64_R11, 0);
7315 #endif
7316                         }
7317                 } else {
7318                         if (amd64_is_imm32 (item->key))
7319                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7320                         else {
7321                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7322                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7323                         }
7324                         item->jmp_code = code;
7325                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7326                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7327                         else
7328                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7329                 }
7330                 g_assert (code - item->code_target <= item->chunk_size);
7331         }
7332         /* patch the branches to get to the target items */
7333         for (i = 0; i < count; ++i) {
7334                 MonoIMTCheckItem *item = imt_entries [i];
7335                 if (item->jmp_code) {
7336                         if (item->check_target_idx) {
7337                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7338                         }
7339                 }
7340         }
7341
7342         if (!fail_tramp)
7343                 mono_stats.imt_thunks_size += code - start;
7344         g_assert (code - start <= size);
7345
7346         return start;
7347 }
7348
7349 MonoMethod*
7350 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7351 {
7352         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7353 }
7354 #endif
7355
7356 MonoVTable*
7357 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7358 {
7359         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7360 }
7361
7362 GSList*
7363 mono_arch_get_cie_program (void)
7364 {
7365         GSList *l = NULL;
7366
7367         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7368         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7369
7370         return l;
7371 }
7372
7373 MonoInst*
7374 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7375 {
7376         MonoInst *ins = NULL;
7377         int opcode = 0;
7378
7379         if (cmethod->klass == mono_defaults.math_class) {
7380                 if (strcmp (cmethod->name, "Sin") == 0) {
7381                         opcode = OP_SIN;
7382                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7383                         opcode = OP_COS;
7384                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7385                         opcode = OP_SQRT;
7386                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7387                         opcode = OP_ABS;
7388                 }
7389
7390                 if (opcode) {
7391                         MONO_INST_NEW (cfg, ins, opcode);
7392                         ins->type = STACK_R8;
7393                         ins->dreg = mono_alloc_freg (cfg);
7394                         ins->sreg1 = args [0]->dreg;
7395                         MONO_ADD_INS (cfg->cbb, ins);
7396                 }
7397
7398                 opcode = 0;
7399                 if (cfg->opt & MONO_OPT_CMOV) {
7400                         if (strcmp (cmethod->name, "Min") == 0) {
7401                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7402                                         opcode = OP_IMIN;
7403                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7404                                         opcode = OP_IMIN_UN;
7405                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7406                                         opcode = OP_LMIN;
7407                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7408                                         opcode = OP_LMIN_UN;
7409                         } else if (strcmp (cmethod->name, "Max") == 0) {
7410                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7411                                         opcode = OP_IMAX;
7412                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7413                                         opcode = OP_IMAX_UN;
7414                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7415                                         opcode = OP_LMAX;
7416                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7417                                         opcode = OP_LMAX_UN;
7418                         }
7419                 }
7420
7421                 if (opcode) {
7422                         MONO_INST_NEW (cfg, ins, opcode);
7423                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7424                         ins->dreg = mono_alloc_ireg (cfg);
7425                         ins->sreg1 = args [0]->dreg;
7426                         ins->sreg2 = args [1]->dreg;
7427                         MONO_ADD_INS (cfg->cbb, ins);
7428                 }
7429
7430 #if 0
7431                 /* OP_FREM is not IEEE compatible */
7432                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7433                         MONO_INST_NEW (cfg, ins, OP_FREM);
7434                         ins->inst_i0 = args [0];
7435                         ins->inst_i1 = args [1];
7436                 }
7437 #endif
7438         }
7439
7440         /*
7441          * Can't implement CompareExchange methods this way since they have
7442          * three arguments.
7443          */
7444
7445         return ins;
7446 }
7447
7448 gboolean
7449 mono_arch_print_tree (MonoInst *tree, int arity)
7450 {
7451         return 0;
7452 }
7453
7454 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7455 {
7456         MonoInst* ins;
7457
7458         if (appdomain_tls_offset == -1)
7459                 return NULL;
7460
7461         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7462         ins->inst_offset = appdomain_tls_offset;
7463         return ins;
7464 }
7465
7466 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7467
7468 gpointer
7469 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7470 {
7471         switch (reg) {
7472         case AMD64_RCX: return (gpointer)ctx->rcx;
7473         case AMD64_RDX: return (gpointer)ctx->rdx;
7474         case AMD64_RBX: return (gpointer)ctx->rbx;
7475         case AMD64_RBP: return (gpointer)ctx->rbp;
7476         case AMD64_RSP: return (gpointer)ctx->rsp;
7477         default:
7478                 if (reg < 8)
7479                         return _CTX_REG (ctx, rax, reg);
7480                 else if (reg >= 12)
7481                         return _CTX_REG (ctx, r12, reg - 12);
7482                 else
7483                         g_assert_not_reached ();
7484         }
7485 }
7486
7487 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
7488 gpointer
7489 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7490 {
7491         int offset;
7492         gpointer *sp, old_value;
7493         char *bp;
7494         const unsigned char *handler;
7495
7496         /*Decode the first instruction to figure out where did we store the spvar*/
7497         /*Our jit MUST generate the following:
7498          mov    %rsp, ?(%rbp)
7499
7500          Which is encoded as: REX.W 0x89 mod_rm
7501          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
7502                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
7503                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
7504
7505         FIXME can we generate frameless methods on this case?
7506
7507         */
7508         handler = clause->handler_start;
7509
7510         /*REX.W*/
7511         if (*handler != 0x48)
7512                 return NULL;
7513         ++handler;
7514
7515         /*mov r, r/m */
7516         if (*handler != 0x89)
7517                 return NULL;
7518         ++handler;
7519
7520         if (*handler == 0x65)
7521                 offset = *(signed char*)(handler + 1);
7522         else if (*handler == 0xA5)
7523                 offset = *(int*)(handler + 1);
7524         else
7525                 return NULL;
7526
7527         /*Load the spvar*/
7528         bp = MONO_CONTEXT_GET_BP (ctx);
7529         sp = *(gpointer*)(bp + offset);
7530
7531         old_value = *sp;
7532         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7533                 return old_value;
7534
7535         *sp = new_value;
7536
7537         return old_value;
7538 }
7539
7540 /*
7541  * mono_arch_emit_load_aotconst:
7542  *
7543  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7544  * TARGET from the mscorlib GOT in full-aot code.
7545  * On AMD64, the result is placed into R11.
7546  */
7547 guint8*
7548 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7549 {
7550         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7551         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7552
7553         return code;
7554 }
7555
7556 /*
7557  * mono_arch_get_trampolines:
7558  *
7559  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
7560  * for AOT.
7561  */
7562 GSList *
7563 mono_arch_get_trampolines (gboolean aot)
7564 {
7565         MonoTrampInfo *info;
7566         GSList *tramps = NULL;
7567
7568         mono_arch_get_throw_pending_exception (&info, aot);
7569
7570         tramps = g_slist_append (tramps, info);
7571
7572         return tramps;
7573 }
7574
7575 /* Soft Debug support */
7576 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7577
7578 /*
7579  * mono_arch_set_breakpoint:
7580  *
7581  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7582  * The location should contain code emitted by OP_SEQ_POINT.
7583  */
7584 void
7585 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7586 {
7587         guint8 *code = ip;
7588         guint8 *orig_code = code;
7589
7590         /*
7591          * In production, we will use int3 (has to fix the size in the md
7592          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7593          * instead.
7594          */
7595         g_assert (code [0] == 0x90);
7596         if (breakpoint_size == 8) {
7597                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7598         } else {
7599                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7600                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7601         }
7602
7603         g_assert (code - orig_code == breakpoint_size);
7604 }
7605
7606 /*
7607  * mono_arch_clear_breakpoint:
7608  *
7609  *   Clear the breakpoint at IP.
7610  */
7611 void
7612 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7613 {
7614         guint8 *code = ip;
7615         int i;
7616
7617         for (i = 0; i < breakpoint_size; ++i)
7618                 x86_nop (code);
7619 }
7620
7621 gboolean
7622 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7623 {
7624 #ifdef HOST_WIN32
7625         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7626         return FALSE;
7627 #else
7628         siginfo_t* sinfo = (siginfo_t*) info;
7629         /* Sometimes the address is off by 4 */
7630         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7631                 return TRUE;
7632         else
7633                 return FALSE;
7634 #endif
7635 }
7636
7637 /*
7638  * mono_arch_get_ip_for_breakpoint:
7639  *
7640  *   Convert the ip in CTX to the address where a breakpoint was placed.
7641  */
7642 guint8*
7643 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7644 {
7645         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7646
7647         /* ip points to the instruction causing the fault */
7648         ip -= (breakpoint_size - breakpoint_fault_size);
7649
7650         return ip;
7651 }
7652
7653 /*
7654  * mono_arch_skip_breakpoint:
7655  *
7656  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7657  * we resume, the instruction is not executed again.
7658  */
7659 void
7660 mono_arch_skip_breakpoint (MonoContext *ctx)
7661 {
7662         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7663 }
7664
7665 /*
7666  * mono_arch_start_single_stepping:
7667  *
7668  *   Start single stepping.
7669  */
7670 void
7671 mono_arch_start_single_stepping (void)
7672 {
7673         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7674 }
7675
7676 /*
7677  * mono_arch_stop_single_stepping:
7678  *
7679  *   Stop single stepping.
7680  */
7681 void
7682 mono_arch_stop_single_stepping (void)
7683 {
7684         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7685 }
7686
7687 /*
7688  * mono_arch_is_single_step_event:
7689  *
7690  *   Return whenever the machine state in SIGCTX corresponds to a single
7691  * step event.
7692  */
7693 gboolean
7694 mono_arch_is_single_step_event (void *info, void *sigctx)
7695 {
7696 #ifdef HOST_WIN32
7697         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7698         return FALSE;
7699 #else
7700         siginfo_t* sinfo = (siginfo_t*) info;
7701         /* Sometimes the address is off by 4 */
7702         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7703                 return TRUE;
7704         else
7705                 return FALSE;
7706 #endif
7707 }
7708
7709 /*
7710  * mono_arch_get_ip_for_single_step:
7711  *
7712  *   Convert the ip in CTX to the address stored in seq_points.
7713  */
7714 guint8*
7715 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7716 {
7717         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7718
7719         ip += single_step_fault_size;
7720
7721         return ip;
7722 }
7723
7724 /*
7725  * mono_arch_skip_single_step:
7726  *
7727  *   Modify CTX so the ip is placed after the single step trigger instruction,
7728  * we resume, the instruction is not executed again.
7729  */
7730 void
7731 mono_arch_skip_single_step (MonoContext *ctx)
7732 {
7733         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7734 }
7735
7736 /*
7737  * mono_arch_create_seq_point_info:
7738  *
7739  *   Return a pointer to a data structure which is used by the sequence
7740  * point implementation in AOTed code.
7741  */
7742 gpointer
7743 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7744 {
7745         NOT_IMPLEMENTED;
7746         return NULL;
7747 }
7748
7749 #endif