mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011 }
1012
1013 GList *
1014 mono_arch_get_global_int_regs (MonoCompile *cfg)
1015 {
1016         GList *regs = NULL;
1017
1018         mono_arch_compute_omit_fp (cfg);
1019
1020         if (cfg->globalra) {
1021                 if (cfg->arch.omit_fp)
1022                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1023
1024                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1025                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1026                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1027                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1028                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1029
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1034                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1038         } else {
1039                 if (cfg->arch.omit_fp)
1040                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1041
1042                 /* We use the callee saved registers for global allocation */
1043                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1048 #ifdef PLATFORM_WIN32
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1051 #endif
1052         }
1053
1054         return regs;
1055 }
1056
1057 GList*
1058 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1059 {
1060         GList *regs = NULL;
1061         int i;
1062
1063         /* All XMM registers */
1064         for (i = 0; i < 16; ++i)
1065                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1066
1067         return regs;
1068 }
1069
1070 GList*
1071 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1072 {
1073         static GList *r = NULL;
1074
1075         if (r == NULL) {
1076                 GList *regs = NULL;
1077
1078                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1084
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1093
1094                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1095         }
1096
1097         return r;
1098 }
1099
1100 GList*
1101 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1102 {
1103         int i;
1104         static GList *r = NULL;
1105
1106         if (r == NULL) {
1107                 GList *regs = NULL;
1108
1109                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1110                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1111
1112                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1113         }
1114
1115         return r;
1116 }
1117
1118 /*
1119  * mono_arch_regalloc_cost:
1120  *
1121  *  Return the cost, in number of memory references, of the action of
1122  * allocating the variable VMV into a register during global register
1123  * allocation.
1124  */
1125 guint32
1126 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1127 {
1128         MonoInst *ins = cfg->varinfo [vmv->idx];
1129
1130         if (cfg->method->save_lmf)
1131                 /* The register is already saved */
1132                 /* substract 1 for the invisible store in the prolog */
1133                 return (ins->opcode == OP_ARG) ? 0 : 1;
1134         else
1135                 /* push+pop */
1136                 return (ins->opcode == OP_ARG) ? 1 : 2;
1137 }
1138
1139 /*
1140  * mono_arch_fill_argument_info:
1141  *
1142  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1143  * of the method.
1144  */
1145 void
1146 mono_arch_fill_argument_info (MonoCompile *cfg)
1147 {
1148         MonoMethodSignature *sig;
1149         MonoMethodHeader *header;
1150         MonoInst *ins;
1151         int i;
1152         CallInfo *cinfo;
1153
1154         header = mono_method_get_header (cfg->method);
1155
1156         sig = mono_method_signature (cfg->method);
1157
1158         cinfo = cfg->arch.cinfo;
1159
1160         /*
1161          * Contrary to mono_arch_allocate_vars (), the information should describe
1162          * where the arguments are at the beginning of the method, not where they can be
1163          * accessed during the execution of the method. The later makes no sense for the
1164          * global register allocator, since a variable can be in more than one location.
1165          */
1166         if (sig->ret->type != MONO_TYPE_VOID) {
1167                 switch (cinfo->ret.storage) {
1168                 case ArgInIReg:
1169                 case ArgInFloatSSEReg:
1170                 case ArgInDoubleSSEReg:
1171                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1172                                 cfg->vret_addr->opcode = OP_REGVAR;
1173                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1174                         }
1175                         else {
1176                                 cfg->ret->opcode = OP_REGVAR;
1177                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1178                         }
1179                         break;
1180                 case ArgValuetypeInReg:
1181                         cfg->ret->opcode = OP_REGOFFSET;
1182                         cfg->ret->inst_basereg = -1;
1183                         cfg->ret->inst_offset = -1;
1184                         break;
1185                 default:
1186                         g_assert_not_reached ();
1187                 }
1188         }
1189
1190         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1191                 ArgInfo *ainfo = &cinfo->args [i];
1192                 MonoType *arg_type;
1193
1194                 ins = cfg->args [i];
1195
1196                 if (sig->hasthis && (i == 0))
1197                         arg_type = &mono_defaults.object_class->byval_arg;
1198                 else
1199                         arg_type = sig->params [i - sig->hasthis];
1200
1201                 switch (ainfo->storage) {
1202                 case ArgInIReg:
1203                 case ArgInFloatSSEReg:
1204                 case ArgInDoubleSSEReg:
1205                         ins->opcode = OP_REGVAR;
1206                         ins->inst_c0 = ainfo->reg;
1207                         break;
1208                 case ArgOnStack:
1209                         ins->opcode = OP_REGOFFSET;
1210                         ins->inst_basereg = -1;
1211                         ins->inst_offset = -1;
1212                         break;
1213                 case ArgValuetypeInReg:
1214                         /* Dummy */
1215                         ins->opcode = OP_NOP;
1216                         break;
1217                 default:
1218                         g_assert_not_reached ();
1219                 }
1220         }
1221 }
1222
1223 void
1224 mono_arch_allocate_vars (MonoCompile *cfg)
1225 {
1226         MonoMethodSignature *sig;
1227         MonoMethodHeader *header;
1228         MonoInst *ins;
1229         int i, offset;
1230         guint32 locals_stack_size, locals_stack_align;
1231         gint32 *offsets;
1232         CallInfo *cinfo;
1233
1234         header = mono_method_get_header (cfg->method);
1235
1236         sig = mono_method_signature (cfg->method);
1237
1238         cinfo = cfg->arch.cinfo;
1239
1240         mono_arch_compute_omit_fp (cfg);
1241
1242         /*
1243          * We use the ABI calling conventions for managed code as well.
1244          * Exception: valuetypes are never passed or returned in registers.
1245          */
1246
1247         if (cfg->arch.omit_fp) {
1248                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1249                 cfg->frame_reg = AMD64_RSP;
1250                 offset = 0;
1251         } else {
1252                 /* Locals are allocated backwards from %fp */
1253                 cfg->frame_reg = AMD64_RBP;
1254                 offset = 0;
1255         }
1256
1257         if (cfg->method->save_lmf) {
1258                 /* Reserve stack space for saving LMF */
1259                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1260                 g_assert (offset == 0);
1261                 if (cfg->arch.omit_fp) {
1262                         cfg->arch.lmf_offset = offset;
1263                         offset += sizeof (MonoLMF);
1264                 }
1265                 else {
1266                         offset += sizeof (MonoLMF);
1267                         cfg->arch.lmf_offset = -offset;
1268                 }
1269         } else {
1270                 if (cfg->arch.omit_fp)
1271                         cfg->arch.reg_save_area_offset = offset;
1272                 /* Reserve space for caller saved registers */
1273                 for (i = 0; i < AMD64_NREG; ++i)
1274                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1275                                 offset += sizeof (gpointer);
1276                         }
1277         }
1278
1279         if (sig->ret->type != MONO_TYPE_VOID) {
1280                 switch (cinfo->ret.storage) {
1281                 case ArgInIReg:
1282                 case ArgInFloatSSEReg:
1283                 case ArgInDoubleSSEReg:
1284                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1285                                 if (cfg->globalra) {
1286                                         cfg->vret_addr->opcode = OP_REGVAR;
1287                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1288                                 } else {
1289                                         /* The register is volatile */
1290                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1291                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1292                                         if (cfg->arch.omit_fp) {
1293                                                 cfg->vret_addr->inst_offset = offset;
1294                                                 offset += 8;
1295                                         } else {
1296                                                 offset += 8;
1297                                                 cfg->vret_addr->inst_offset = -offset;
1298                                         }
1299                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1300                                                 printf ("vret_addr =");
1301                                                 mono_print_ins (cfg->vret_addr);
1302                                         }
1303                                 }
1304                         }
1305                         else {
1306                                 cfg->ret->opcode = OP_REGVAR;
1307                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1308                         }
1309                         break;
1310                 case ArgValuetypeInReg:
1311                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1312                         cfg->ret->opcode = OP_REGOFFSET;
1313                         cfg->ret->inst_basereg = cfg->frame_reg;
1314                         if (cfg->arch.omit_fp) {
1315                                 cfg->ret->inst_offset = offset;
1316                                 offset += 16;
1317                         } else {
1318                                 offset += 16;
1319                                 cfg->ret->inst_offset = - offset;
1320                         }
1321                         break;
1322                 default:
1323                         g_assert_not_reached ();
1324                 }
1325                 if (!cfg->globalra)
1326                         cfg->ret->dreg = cfg->ret->inst_c0;
1327         }
1328
1329         /* Allocate locals */
1330         if (!cfg->globalra) {
1331                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1332                 if (locals_stack_align) {
1333                         offset += (locals_stack_align - 1);
1334                         offset &= ~(locals_stack_align - 1);
1335                 }
1336                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1337                         if (offsets [i] != -1) {
1338                                 MonoInst *ins = cfg->varinfo [i];
1339                                 ins->opcode = OP_REGOFFSET;
1340                                 ins->inst_basereg = cfg->frame_reg;
1341                                 if (cfg->arch.omit_fp)
1342                                         ins->inst_offset = (offset + offsets [i]);
1343                                 else
1344                                         ins->inst_offset = - (offset + offsets [i]);
1345                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1346                         }
1347                 }
1348                 offset += locals_stack_size;
1349         }
1350
1351         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1352                 g_assert (!cfg->arch.omit_fp);
1353                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1354                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1355         }
1356
1357         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1358                 ins = cfg->args [i];
1359                 if (ins->opcode != OP_REGVAR) {
1360                         ArgInfo *ainfo = &cinfo->args [i];
1361                         gboolean inreg = TRUE;
1362                         MonoType *arg_type;
1363
1364                         if (sig->hasthis && (i == 0))
1365                                 arg_type = &mono_defaults.object_class->byval_arg;
1366                         else
1367                                 arg_type = sig->params [i - sig->hasthis];
1368
1369                         if (cfg->globalra) {
1370                                 /* The new allocator needs info about the original locations of the arguments */
1371                                 switch (ainfo->storage) {
1372                                 case ArgInIReg:
1373                                 case ArgInFloatSSEReg:
1374                                 case ArgInDoubleSSEReg:
1375                                         ins->opcode = OP_REGVAR;
1376                                         ins->inst_c0 = ainfo->reg;
1377                                         break;
1378                                 case ArgOnStack:
1379                                         g_assert (!cfg->arch.omit_fp);
1380                                         ins->opcode = OP_REGOFFSET;
1381                                         ins->inst_basereg = cfg->frame_reg;
1382                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1383                                         break;
1384                                 case ArgValuetypeInReg:
1385                                         ins->opcode = OP_REGOFFSET;
1386                                         ins->inst_basereg = cfg->frame_reg;
1387                                         /* These arguments are saved to the stack in the prolog */
1388                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1389                                         if (cfg->arch.omit_fp) {
1390                                                 ins->inst_offset = offset;
1391                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1392                                         } else {
1393                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1394                                                 ins->inst_offset = - offset;
1395                                         }
1396                                         break;
1397                                 default:
1398                                         g_assert_not_reached ();
1399                                 }
1400
1401                                 continue;
1402                         }
1403
1404                         /* FIXME: Allocate volatile arguments to registers */
1405                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1406                                 inreg = FALSE;
1407
1408                         /*
1409                          * Under AMD64, all registers used to pass arguments to functions
1410                          * are volatile across calls.
1411                          * FIXME: Optimize this.
1412                          */
1413                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1414                                 inreg = FALSE;
1415
1416                         ins->opcode = OP_REGOFFSET;
1417
1418                         switch (ainfo->storage) {
1419                         case ArgInIReg:
1420                         case ArgInFloatSSEReg:
1421                         case ArgInDoubleSSEReg:
1422                                 if (inreg) {
1423                                         ins->opcode = OP_REGVAR;
1424                                         ins->dreg = ainfo->reg;
1425                                 }
1426                                 break;
1427                         case ArgOnStack:
1428                                 g_assert (!cfg->arch.omit_fp);
1429                                 ins->opcode = OP_REGOFFSET;
1430                                 ins->inst_basereg = cfg->frame_reg;
1431                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1432                                 break;
1433                         case ArgValuetypeInReg:
1434                                 break;
1435                         case ArgValuetypeAddrInIReg: {
1436                                 MonoInst *indir;
1437                                 g_assert (!cfg->arch.omit_fp);
1438
1439                                 MONO_INST_NEW (cfg, indir, 0);
1440                                 indir->opcode = OP_REGOFFSET;
1441                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1442                                         indir->inst_basereg = cfg->frame_reg;
1443                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1444                                         offset += (sizeof (gpointer));
1445                                         indir->inst_offset = - offset;
1446                                 }
1447                                 else {
1448                                         indir->inst_basereg = cfg->frame_reg;
1449                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1450                                 }
1451
1452                                 ins->opcode = OP_VTARG_ADDR;
1453                                 ins->inst_left = indir;
1454
1455                                 break;
1456                         }
1457                         default:
1458                                 NOT_IMPLEMENTED;
1459                         }
1460
1461                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1462                                 ins->opcode = OP_REGOFFSET;
1463                                 ins->inst_basereg = cfg->frame_reg;
1464                                 /* These arguments are saved to the stack in the prolog */
1465                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1466                                 if (cfg->arch.omit_fp) {
1467                                         ins->inst_offset = offset;
1468                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1469                                 } else {
1470                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1471                                         ins->inst_offset = - offset;
1472                                 }
1473                         }
1474                 }
1475         }
1476
1477         cfg->stack_offset = offset;
1478 }
1479
1480 void
1481 mono_arch_create_vars (MonoCompile *cfg)
1482 {
1483         MonoMethodSignature *sig;
1484         CallInfo *cinfo;
1485
1486         sig = mono_method_signature (cfg->method);
1487
1488         if (!cfg->arch.cinfo)
1489                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1490         cinfo = cfg->arch.cinfo;
1491
1492         if (cinfo->ret.storage == ArgValuetypeInReg)
1493                 cfg->ret_var_is_local = TRUE;
1494
1495         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1496                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1497                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1498                         printf ("vret_addr = ");
1499                         mono_print_ins (cfg->vret_addr);
1500                 }
1501         }
1502 }
1503
1504 static void
1505 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1506 {
1507         MonoInst *ins;
1508
1509         switch (storage) {
1510         case ArgInIReg:
1511                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1512                 ins->dreg = mono_alloc_ireg (cfg);
1513                 ins->sreg1 = tree->dreg;
1514                 MONO_ADD_INS (cfg->cbb, ins);
1515                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1516                 break;
1517         case ArgInFloatSSEReg:
1518                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1519                 ins->dreg = mono_alloc_freg (cfg);
1520                 ins->sreg1 = tree->dreg;
1521                 MONO_ADD_INS (cfg->cbb, ins);
1522
1523                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1524                 break;
1525         case ArgInDoubleSSEReg:
1526                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1527                 ins->dreg = mono_alloc_freg (cfg);
1528                 ins->sreg1 = tree->dreg;
1529                 MONO_ADD_INS (cfg->cbb, ins);
1530
1531                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1532
1533                 break;
1534         default:
1535                 g_assert_not_reached ();
1536         }
1537 }
1538
1539 static int
1540 arg_storage_to_load_membase (ArgStorage storage)
1541 {
1542         switch (storage) {
1543         case ArgInIReg:
1544                 return OP_LOAD_MEMBASE;
1545         case ArgInDoubleSSEReg:
1546                 return OP_LOADR8_MEMBASE;
1547         case ArgInFloatSSEReg:
1548                 return OP_LOADR4_MEMBASE;
1549         default:
1550                 g_assert_not_reached ();
1551         }
1552
1553         return -1;
1554 }
1555
1556 static void
1557 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1558 {
1559         MonoInst *arg;
1560         MonoMethodSignature *tmp_sig;
1561         MonoInst *sig_arg;
1562
1563         if (call->tail_call)
1564                 NOT_IMPLEMENTED;
1565
1566         /* FIXME: Add support for signature tokens to AOT */
1567         cfg->disable_aot = TRUE;
1568
1569         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1570
1571         /*
1572          * mono_ArgIterator_Setup assumes the signature cookie is
1573          * passed first and all the arguments which were before it are
1574          * passed on the stack after the signature. So compensate by
1575          * passing a different signature.
1576          */
1577         tmp_sig = mono_metadata_signature_dup (call->signature);
1578         tmp_sig->param_count -= call->signature->sentinelpos;
1579         tmp_sig->sentinelpos = 0;
1580         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1581
1582         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1583         sig_arg->dreg = mono_alloc_ireg (cfg);
1584         sig_arg->inst_p0 = tmp_sig;
1585         MONO_ADD_INS (cfg->cbb, sig_arg);
1586
1587         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1588         arg->sreg1 = sig_arg->dreg;
1589         MONO_ADD_INS (cfg->cbb, arg);
1590 }
1591
1592 void
1593 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1594 {
1595         MonoInst *arg, *in;
1596         MonoMethodSignature *sig;
1597         int i, n, stack_size;
1598         CallInfo *cinfo;
1599         ArgInfo *ainfo;
1600
1601         stack_size = 0;
1602
1603         sig = call->signature;
1604         n = sig->param_count + sig->hasthis;
1605
1606         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1607
1608         if (COMPILE_LLVM (cfg)) {
1609                 for (i = 0; i < n; ++i) {
1610                         MonoInst *ins;
1611
1612                         ainfo = cinfo->args + i;
1613
1614                         in = call->args [i];
1615
1616                         /* Simply remember the arguments */
1617                         switch (ainfo->storage) {
1618                         case ArgInIReg:
1619                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1620                                 ins->dreg = mono_alloc_ireg (cfg);
1621                                 ins->sreg1 = in->dreg;
1622                                 break;
1623                         case ArgInDoubleSSEReg:
1624                         case ArgInFloatSSEReg:
1625                                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1626                                 ins->dreg = mono_alloc_freg (cfg);
1627                                 ins->sreg1 = in->dreg;
1628                                 break;
1629                         case ArgOnStack:
1630                                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1631                                         cfg->exception_message = g_strdup ("vtype argument");
1632                                         cfg->disable_llvm = TRUE;
1633                                 } else {
1634                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1635                                         ins->dreg = mono_alloc_ireg (cfg);
1636                                         ins->sreg1 = in->dreg;
1637                                 }
1638                                 break;
1639                         default:
1640                                 cfg->exception_message = g_strdup ("ainfo->storage");
1641                                 cfg->disable_llvm = TRUE;
1642                                 return;
1643                         }
1644
1645                         if (!cfg->disable_llvm) {
1646                                 MONO_ADD_INS (cfg->cbb, ins);
1647                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, 0, FALSE);
1648                         }
1649                 }
1650                 return;
1651         }
1652
1653         if (cinfo->need_stack_align) {
1654                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1655         }
1656
1657         /*
1658          * Emit all parameters passed in registers in non-reverse order for better readability
1659          * and to help the optimization in emit_prolog ().
1660          */
1661         for (i = 0; i < n; ++i) {
1662                 ainfo = cinfo->args + i;
1663
1664                 in = call->args [i];
1665
1666                 if (ainfo->storage == ArgInIReg)
1667                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1668         }
1669
1670         for (i = n - 1; i >= 0; --i) {
1671                 ainfo = cinfo->args + i;
1672
1673                 in = call->args [i];
1674
1675                 switch (ainfo->storage) {
1676                 case ArgInIReg:
1677                         /* Already done */
1678                         break;
1679                 case ArgInFloatSSEReg:
1680                 case ArgInDoubleSSEReg:
1681                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1682                         break;
1683                 case ArgOnStack:
1684                 case ArgValuetypeInReg:
1685                 case ArgValuetypeAddrInIReg:
1686                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1687                                 MonoInst *call_inst = (MonoInst*)call;
1688                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1689                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1690                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1691                                 guint32 align;
1692                                 guint32 size;
1693
1694                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1695                                         size = sizeof (MonoTypedRef);
1696                                         align = sizeof (gpointer);
1697                                 }
1698                                 else {
1699                                         if (sig->pinvoke)
1700                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1701                                         else {
1702                                                 /*
1703                                                  * Other backends use mono_type_stack_size (), but that
1704                                                  * aligns the size to 8, which is larger than the size of
1705                                                  * the source, leading to reads of invalid memory if the
1706                                                  * source is at the end of address space.
1707                                                  */
1708                                                 size = mono_class_value_size (in->klass, &align);
1709                                         }
1710                                 }
1711                                 g_assert (in->klass);
1712
1713                                 if (size > 0) {
1714                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1715                                         arg->sreg1 = in->dreg;
1716                                         arg->klass = in->klass;
1717                                         arg->backend.size = size;
1718                                         arg->inst_p0 = call;
1719                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1720                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1721
1722                                         MONO_ADD_INS (cfg->cbb, arg);
1723                                 }
1724                         } else {
1725                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1726                                 arg->sreg1 = in->dreg;
1727                                 if (!sig->params [i - sig->hasthis]->byref) {
1728                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1729                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1730                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1731                                                 arg->inst_destbasereg = X86_ESP;
1732                                                 arg->inst_offset = 0;
1733                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1734                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1735                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1736                                                 arg->inst_destbasereg = X86_ESP;
1737                                                 arg->inst_offset = 0;
1738                                         }
1739                                 }
1740                                 MONO_ADD_INS (cfg->cbb, arg);
1741                         }
1742                         break;
1743                 default:
1744                         g_assert_not_reached ();
1745                 }
1746
1747                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1748                         /* Emit the signature cookie just before the implicit arguments */
1749                         emit_sig_cookie (cfg, call, cinfo);
1750         }
1751
1752         /* Handle the case where there are no implicit arguments */
1753         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1754                 emit_sig_cookie (cfg, call, cinfo);
1755
1756         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1757                 MonoInst *vtarg;
1758
1759                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1760                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1761                                 /*
1762                                  * Tell the JIT to use a more efficient calling convention: call using
1763                                  * OP_CALL, compute the result location after the call, and save the
1764                                  * result there.
1765                                  */
1766                                 call->vret_in_reg = TRUE;
1767                                 /*
1768                                  * Nullify the instruction computing the vret addr to enable
1769                                  * future optimizations.
1770                                  */
1771                                 if (call->vret_var)
1772                                         NULLIFY_INS (call->vret_var);
1773                         } else {
1774                                 if (call->tail_call)
1775                                         NOT_IMPLEMENTED;
1776                                 /*
1777                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1778                                  * the stack. Push the address here, so the call instruction can
1779                                  * access it.
1780                                  */
1781                                 if (!cfg->arch.vret_addr_loc) {
1782                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1783                                         /* Prevent it from being register allocated or optimized away */
1784                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1785                                 }
1786
1787                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1788                         }
1789                 }
1790                 else {
1791                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1792                         vtarg->sreg1 = call->vret_var->dreg;
1793                         vtarg->dreg = mono_alloc_preg (cfg);
1794                         MONO_ADD_INS (cfg->cbb, vtarg);
1795
1796                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1797                 }
1798         }
1799
1800 #ifdef PLATFORM_WIN32
1801         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1802                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1803         }
1804 #endif
1805
1806         if (cfg->method->save_lmf) {
1807                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1808                 MONO_ADD_INS (cfg->cbb, arg);
1809         }
1810
1811         call->stack_usage = cinfo->stack_usage;
1812 }
1813
1814 void
1815 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1816 {
1817         MonoInst *arg;
1818         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1819         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1820         int size = ins->backend.size;
1821
1822         if (ainfo->storage == ArgValuetypeInReg) {
1823                 MonoInst *load;
1824                 int part;
1825
1826                 for (part = 0; part < 2; ++part) {
1827                         if (ainfo->pair_storage [part] == ArgNone)
1828                                 continue;
1829
1830                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1831                         load->inst_basereg = src->dreg;
1832                         load->inst_offset = part * sizeof (gpointer);
1833
1834                         switch (ainfo->pair_storage [part]) {
1835                         case ArgInIReg:
1836                                 load->dreg = mono_alloc_ireg (cfg);
1837                                 break;
1838                         case ArgInDoubleSSEReg:
1839                         case ArgInFloatSSEReg:
1840                                 load->dreg = mono_alloc_freg (cfg);
1841                                 break;
1842                         default:
1843                                 g_assert_not_reached ();
1844                         }
1845                         MONO_ADD_INS (cfg->cbb, load);
1846
1847                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1848                 }
1849         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1850                 MonoInst *vtaddr, *load;
1851                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1852
1853                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1854                 load->inst_p0 = vtaddr;
1855                 vtaddr->flags |= MONO_INST_INDIRECT;
1856                 load->type = STACK_MP;
1857                 load->klass = vtaddr->klass;
1858                 load->dreg = mono_alloc_ireg (cfg);
1859                 MONO_ADD_INS (cfg->cbb, load);
1860                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1861
1862                 if (ainfo->pair_storage [0] == ArgInIReg) {
1863                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1864                         arg->dreg = mono_alloc_ireg (cfg);
1865                         arg->sreg1 = load->dreg;
1866                         arg->inst_imm = 0;
1867                         MONO_ADD_INS (cfg->cbb, arg);
1868                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1869                 } else {
1870                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1871                         arg->sreg1 = load->dreg;
1872                         MONO_ADD_INS (cfg->cbb, arg);
1873                 }
1874         } else {
1875                 if (size == 8) {
1876                         /* Can't use this for < 8 since it does an 8 byte memory load */
1877                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1878                         arg->inst_basereg = src->dreg;
1879                         arg->inst_offset = 0;
1880                         MONO_ADD_INS (cfg->cbb, arg);
1881                 } else if (size <= 40) {
1882                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1883                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1884                 } else {
1885                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1886                         arg->inst_basereg = src->dreg;
1887                         arg->inst_offset = 0;
1888                         arg->inst_imm = size;
1889                         MONO_ADD_INS (cfg->cbb, arg);
1890                 }
1891         }
1892 }
1893
1894 void
1895 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1896 {
1897         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1898
1899         if (!ret->byref) {
1900                 if (ret->type == MONO_TYPE_R4) {
1901                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1902                         return;
1903                 } else if (ret->type == MONO_TYPE_R8) {
1904                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1905                         return;
1906                 }
1907         }
1908
1909         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1910 }
1911
1912 #define EMIT_COND_BRANCH(ins,cond,sign) \
1913 if (ins->flags & MONO_INST_BRLABEL) { \
1914         if (ins->inst_i0->inst_c0) { \
1915                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1916         } else { \
1917                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1918                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1919                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1920                         x86_branch8 (code, cond, 0, sign); \
1921                 else \
1922                         x86_branch32 (code, cond, 0, sign); \
1923         } \
1924 } else { \
1925         if (ins->inst_true_bb->native_offset) { \
1926                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1927         } else { \
1928                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1929                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1930                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1931                         x86_branch8 (code, cond, 0, sign); \
1932                 else \
1933                         x86_branch32 (code, cond, 0, sign); \
1934         } \
1935 }
1936
1937 /* emit an exception if condition is fail */
1938 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1939         do {                                                        \
1940                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1941                 if (tins == NULL) {                                                                             \
1942                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1943                                         MONO_PATCH_INFO_EXC, exc_name);  \
1944                         x86_branch32 (code, cond, 0, signed);               \
1945                 } else {        \
1946                         EMIT_COND_BRANCH (tins, cond, signed);  \
1947                 }                       \
1948         } while (0);
1949
1950 #define EMIT_FPCOMPARE(code) do { \
1951         amd64_fcompp (code); \
1952         amd64_fnstsw (code); \
1953 } while (0);
1954
1955 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1956     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1957         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1958         amd64_ ##op (code); \
1959         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1960         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1961 } while (0);
1962
1963 static guint8*
1964 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1965 {
1966         gboolean no_patch = FALSE;
1967
1968         /*
1969          * FIXME: Add support for thunks
1970          */
1971         {
1972                 gboolean near_call = FALSE;
1973
1974                 /*
1975                  * Indirect calls are expensive so try to make a near call if possible.
1976                  * The caller memory is allocated by the code manager so it is
1977                  * guaranteed to be at a 32 bit offset.
1978                  */
1979
1980                 if (patch_type != MONO_PATCH_INFO_ABS) {
1981                         /* The target is in memory allocated using the code manager */
1982                         near_call = TRUE;
1983
1984                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1985                                 if (((MonoMethod*)data)->klass->image->aot_module)
1986                                         /* The callee might be an AOT method */
1987                                         near_call = FALSE;
1988                                 if (((MonoMethod*)data)->dynamic)
1989                                         /* The target is in malloc-ed memory */
1990                                         near_call = FALSE;
1991                         }
1992
1993                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1994                                 /*
1995                                  * The call might go directly to a native function without
1996                                  * the wrapper.
1997                                  */
1998                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1999                                 if (mi) {
2000                                         gconstpointer target = mono_icall_get_wrapper (mi);
2001                                         if ((((guint64)target) >> 32) != 0)
2002                                                 near_call = FALSE;
2003                                 }
2004                         }
2005                 }
2006                 else {
2007                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2008                                 /*
2009                                  * This is not really an optimization, but required because the
2010                                  * generic class init trampolines use R11 to pass the vtable.
2011                                  */
2012                                 near_call = TRUE;
2013                         } else {
2014                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2015                                 if (info) {
2016                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2017                                                 strstr (cfg->method->name, info->name)) {
2018                                                 /* A call to the wrapped function */
2019                                                 if ((((guint64)data) >> 32) == 0)
2020                                                         near_call = TRUE;
2021                                                 no_patch = TRUE;
2022                                         }
2023                                         else if (info->func == info->wrapper) {
2024                                                 /* No wrapper */
2025                                                 if ((((guint64)info->func) >> 32) == 0)
2026                                                         near_call = TRUE;
2027                                         }
2028                                         else {
2029                                                 /* See the comment in mono_codegen () */
2030                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2031                                                         near_call = TRUE;
2032                                         }
2033                                 }
2034                                 else if ((((guint64)data) >> 32) == 0) {
2035                                         near_call = TRUE;
2036                                         no_patch = TRUE;
2037                                 }
2038                         }
2039                 }
2040
2041                 if (cfg->method->dynamic)
2042                         /* These methods are allocated using malloc */
2043                         near_call = FALSE;
2044
2045                 if (cfg->compile_aot) {
2046                         near_call = TRUE;
2047                         no_patch = TRUE;
2048                 }
2049
2050 #ifdef MONO_ARCH_NOMAP32BIT
2051                 near_call = FALSE;
2052 #endif
2053
2054                 if (near_call) {
2055                         /*
2056                          * Align the call displacement to an address divisible by 4 so it does
2057                          * not span cache lines. This is required for code patching to work on SMP
2058                          * systems.
2059                          */
2060                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2061                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2062                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2063                         amd64_call_code (code, 0);
2064                 }
2065                 else {
2066                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2067                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2068                         amd64_call_reg (code, GP_SCRATCH_REG);
2069                 }
2070         }
2071
2072         return code;
2073 }
2074
2075 static inline guint8*
2076 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2077 {
2078 #ifdef PLATFORM_WIN32
2079         if (win64_adjust_stack)
2080                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2081 #endif
2082         code = emit_call_body (cfg, code, patch_type, data);
2083 #ifdef PLATFORM_WIN32
2084         if (win64_adjust_stack)
2085                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2086 #endif
2087
2088         return code;
2089 }
2090
2091 static inline int
2092 store_membase_imm_to_store_membase_reg (int opcode)
2093 {
2094         switch (opcode) {
2095         case OP_STORE_MEMBASE_IMM:
2096                 return OP_STORE_MEMBASE_REG;
2097         case OP_STOREI4_MEMBASE_IMM:
2098                 return OP_STOREI4_MEMBASE_REG;
2099         case OP_STOREI8_MEMBASE_IMM:
2100                 return OP_STOREI8_MEMBASE_REG;
2101         }
2102
2103         return -1;
2104 }
2105
2106 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2107
2108 /*
2109  * mono_arch_peephole_pass_1:
2110  *
2111  *   Perform peephole opts which should/can be performed before local regalloc
2112  */
2113 void
2114 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2115 {
2116         MonoInst *ins, *n;
2117
2118         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2119                 MonoInst *last_ins = ins->prev;
2120
2121                 switch (ins->opcode) {
2122                 case OP_ADD_IMM:
2123                 case OP_IADD_IMM:
2124                 case OP_LADD_IMM:
2125                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2126                                 /*
2127                                  * X86_LEA is like ADD, but doesn't have the
2128                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2129                                  * its operand to 64 bit.
2130                                  */
2131                                 ins->opcode = OP_X86_LEA_MEMBASE;
2132                                 ins->inst_basereg = ins->sreg1;
2133                         }
2134                         break;
2135                 case OP_LXOR:
2136                 case OP_IXOR:
2137                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2138                                 MonoInst *ins2;
2139
2140                                 /*
2141                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2142                                  * the latter has length 2-3 instead of 6 (reverse constant
2143                                  * propagation). These instruction sequences are very common
2144                                  * in the initlocals bblock.
2145                                  */
2146                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2147                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2148                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2149                                                 ins2->sreg1 = ins->dreg;
2150                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2151                                                 /* Continue */
2152                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2153                                                 NULLIFY_INS (ins2);
2154                                                 /* Continue */
2155                                         } else {
2156                                                 break;
2157                                         }
2158                                 }
2159                         }
2160                         break;
2161                 case OP_COMPARE_IMM:
2162                 case OP_LCOMPARE_IMM:
2163                         /* OP_COMPARE_IMM (reg, 0)
2164                          * -->
2165                          * OP_AMD64_TEST_NULL (reg)
2166                          */
2167                         if (!ins->inst_imm)
2168                                 ins->opcode = OP_AMD64_TEST_NULL;
2169                         break;
2170                 case OP_ICOMPARE_IMM:
2171                         if (!ins->inst_imm)
2172                                 ins->opcode = OP_X86_TEST_NULL;
2173                         break;
2174                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2175                         /*
2176                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2177                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2178                          * -->
2179                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2180                          * OP_COMPARE_IMM reg, imm
2181                          *
2182                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2183                          */
2184                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2185                             ins->inst_basereg == last_ins->inst_destbasereg &&
2186                             ins->inst_offset == last_ins->inst_offset) {
2187                                         ins->opcode = OP_ICOMPARE_IMM;
2188                                         ins->sreg1 = last_ins->sreg1;
2189
2190                                         /* check if we can remove cmp reg,0 with test null */
2191                                         if (!ins->inst_imm)
2192                                                 ins->opcode = OP_X86_TEST_NULL;
2193                                 }
2194
2195                         break;
2196                 }
2197
2198                 mono_peephole_ins (bb, ins);
2199         }
2200 }
2201
2202 void
2203 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2204 {
2205         MonoInst *ins, *n;
2206
2207         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2208                 switch (ins->opcode) {
2209                 case OP_ICONST:
2210                 case OP_I8CONST: {
2211                         /* reg = 0 -> XOR (reg, reg) */
2212                         /* XOR sets cflags on x86, so we cant do it always */
2213                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2214                                 ins->opcode = OP_LXOR;
2215                                 ins->sreg1 = ins->dreg;
2216                                 ins->sreg2 = ins->dreg;
2217                                 /* Fall through */
2218                         } else {
2219                                 break;
2220                         }
2221                 }
2222                 case OP_LXOR:
2223                         /*
2224                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2225                          * 0 result into 64 bits.
2226                          */
2227                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2228                                 ins->opcode = OP_IXOR;
2229                         }
2230                         /* Fall through */
2231                 case OP_IXOR:
2232                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2233                                 MonoInst *ins2;
2234
2235                                 /*
2236                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2237                                  * the latter has length 2-3 instead of 6 (reverse constant
2238                                  * propagation). These instruction sequences are very common
2239                                  * in the initlocals bblock.
2240                                  */
2241                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2242                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2243                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2244                                                 ins2->sreg1 = ins->dreg;
2245                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2246                                                 /* Continue */
2247                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2248                                                 NULLIFY_INS (ins2);
2249                                                 /* Continue */
2250                                         } else {
2251                                                 break;
2252                                         }
2253                                 }
2254                         }
2255                         break;
2256                 case OP_IADD_IMM:
2257                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2258                                 ins->opcode = OP_X86_INC_REG;
2259                         break;
2260                 case OP_ISUB_IMM:
2261                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2262                                 ins->opcode = OP_X86_DEC_REG;
2263                         break;
2264                 }
2265
2266                 mono_peephole_ins (bb, ins);
2267         }
2268 }
2269
2270 #define NEW_INS(cfg,ins,dest,op) do {   \
2271                 MONO_INST_NEW ((cfg), (dest), (op)); \
2272         (dest)->cil_code = (ins)->cil_code; \
2273         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2274         } while (0)
2275
2276 /*
2277  * mono_arch_lowering_pass:
2278  *
2279  *  Converts complex opcodes into simpler ones so that each IR instruction
2280  * corresponds to one machine instruction.
2281  */
2282 void
2283 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2284 {
2285         MonoInst *ins, *n, *temp;
2286
2287         /*
2288          * FIXME: Need to add more instructions, but the current machine
2289          * description can't model some parts of the composite instructions like
2290          * cdq.
2291          */
2292         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2293                 switch (ins->opcode) {
2294                 case OP_DIV_IMM:
2295                 case OP_REM_IMM:
2296                 case OP_IDIV_IMM:
2297                 case OP_IDIV_UN_IMM:
2298                 case OP_IREM_UN_IMM:
2299                         mono_decompose_op_imm (cfg, bb, ins);
2300                         break;
2301                 case OP_IREM_IMM:
2302                         /* Keep the opcode if we can implement it efficiently */
2303                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2304                                 mono_decompose_op_imm (cfg, bb, ins);
2305                         break;
2306                 case OP_COMPARE_IMM:
2307                 case OP_LCOMPARE_IMM:
2308                         if (!amd64_is_imm32 (ins->inst_imm)) {
2309                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2310                                 temp->inst_c0 = ins->inst_imm;
2311                                 temp->dreg = mono_alloc_ireg (cfg);
2312                                 ins->opcode = OP_COMPARE;
2313                                 ins->sreg2 = temp->dreg;
2314                         }
2315                         break;
2316                 case OP_LOAD_MEMBASE:
2317                 case OP_LOADI8_MEMBASE:
2318                         if (!amd64_is_imm32 (ins->inst_offset)) {
2319                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2320                                 temp->inst_c0 = ins->inst_offset;
2321                                 temp->dreg = mono_alloc_ireg (cfg);
2322                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2323                                 ins->inst_indexreg = temp->dreg;
2324                         }
2325                         break;
2326                 case OP_STORE_MEMBASE_IMM:
2327                 case OP_STOREI8_MEMBASE_IMM:
2328                         if (!amd64_is_imm32 (ins->inst_imm)) {
2329                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2330                                 temp->inst_c0 = ins->inst_imm;
2331                                 temp->dreg = mono_alloc_ireg (cfg);
2332                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2333                                 ins->sreg1 = temp->dreg;
2334                         }
2335                         break;
2336                 default:
2337                         break;
2338                 }
2339         }
2340
2341         bb->max_vreg = cfg->next_vreg;
2342 }
2343
2344 static const int
2345 branch_cc_table [] = {
2346         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2347         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2348         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2349 };
2350
2351 /* Maps CMP_... constants to X86_CC_... constants */
2352 static const int
2353 cc_table [] = {
2354         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2355         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2356 };
2357
2358 static const int
2359 cc_signed_table [] = {
2360         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2361         FALSE, FALSE, FALSE, FALSE
2362 };
2363
2364 /*#include "cprop.c"*/
2365
2366 static unsigned char*
2367 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2368 {
2369         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2370
2371         if (size == 1)
2372                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2373         else if (size == 2)
2374                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2375         return code;
2376 }
2377
2378 static unsigned char*
2379 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2380 {
2381         int sreg = tree->sreg1;
2382         int need_touch = FALSE;
2383
2384 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2385         if (!tree->flags & MONO_INST_INIT)
2386                 need_touch = TRUE;
2387 #endif
2388
2389         if (need_touch) {
2390                 guint8* br[5];
2391
2392                 /*
2393                  * Under Windows:
2394                  * If requested stack size is larger than one page,
2395                  * perform stack-touch operation
2396                  */
2397                 /*
2398                  * Generate stack probe code.
2399                  * Under Windows, it is necessary to allocate one page at a time,
2400                  * "touching" stack after each successful sub-allocation. This is
2401                  * because of the way stack growth is implemented - there is a
2402                  * guard page before the lowest stack page that is currently commited.
2403                  * Stack normally grows sequentially so OS traps access to the
2404                  * guard page and commits more pages when needed.
2405                  */
2406                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2407                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2408
2409                 br[2] = code; /* loop */
2410                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2411                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2412                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2413                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2414                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2415                 amd64_patch (br[3], br[2]);
2416                 amd64_test_reg_reg (code, sreg, sreg);
2417                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2418                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2419
2420                 br[1] = code; x86_jump8 (code, 0);
2421
2422                 amd64_patch (br[0], code);
2423                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2424                 amd64_patch (br[1], code);
2425                 amd64_patch (br[4], code);
2426         }
2427         else
2428                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2429
2430         if (tree->flags & MONO_INST_INIT) {
2431                 int offset = 0;
2432                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2433                         amd64_push_reg (code, AMD64_RAX);
2434                         offset += 8;
2435                 }
2436                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2437                         amd64_push_reg (code, AMD64_RCX);
2438                         offset += 8;
2439                 }
2440                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2441                         amd64_push_reg (code, AMD64_RDI);
2442                         offset += 8;
2443                 }
2444
2445                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2446                 if (sreg != AMD64_RCX)
2447                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2448                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2449
2450                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2451                 amd64_cld (code);
2452                 amd64_prefix (code, X86_REP_PREFIX);
2453                 amd64_stosl (code);
2454
2455                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2456                         amd64_pop_reg (code, AMD64_RDI);
2457                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2458                         amd64_pop_reg (code, AMD64_RCX);
2459                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2460                         amd64_pop_reg (code, AMD64_RAX);
2461         }
2462         return code;
2463 }
2464
2465 static guint8*
2466 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2467 {
2468         CallInfo *cinfo;
2469         guint32 quad;
2470
2471         /* Move return value to the target register */
2472         /* FIXME: do this in the local reg allocator */
2473         switch (ins->opcode) {
2474         case OP_CALL:
2475         case OP_CALL_REG:
2476         case OP_CALL_MEMBASE:
2477         case OP_LCALL:
2478         case OP_LCALL_REG:
2479         case OP_LCALL_MEMBASE:
2480                 g_assert (ins->dreg == AMD64_RAX);
2481                 break;
2482         case OP_FCALL:
2483         case OP_FCALL_REG:
2484         case OP_FCALL_MEMBASE:
2485                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2486                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2487                 }
2488                 else {
2489                         if (ins->dreg != AMD64_XMM0)
2490                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2491                 }
2492                 break;
2493         case OP_VCALL:
2494         case OP_VCALL_REG:
2495         case OP_VCALL_MEMBASE:
2496         case OP_VCALL2:
2497         case OP_VCALL2_REG:
2498         case OP_VCALL2_MEMBASE:
2499                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2500                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2501                         MonoInst *loc = cfg->arch.vret_addr_loc;
2502
2503                         /* Load the destination address */
2504                         g_assert (loc->opcode == OP_REGOFFSET);
2505                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2506
2507                         for (quad = 0; quad < 2; quad ++) {
2508                                 switch (cinfo->ret.pair_storage [quad]) {
2509                                 case ArgInIReg:
2510                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2511                                         break;
2512                                 case ArgInFloatSSEReg:
2513                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2514                                         break;
2515                                 case ArgInDoubleSSEReg:
2516                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2517                                         break;
2518                                 case ArgNone:
2519                                         break;
2520                                 default:
2521                                         NOT_IMPLEMENTED;
2522                                 }
2523                         }
2524                 }
2525                 break;
2526         }
2527
2528         return code;
2529 }
2530
2531 /*
2532  * mono_amd64_emit_tls_get:
2533  * @code: buffer to store code to
2534  * @dreg: hard register where to place the result
2535  * @tls_offset: offset info
2536  *
2537  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2538  * the dreg register the item in the thread local storage identified
2539  * by tls_offset.
2540  *
2541  * Returns: a pointer to the end of the stored code
2542  */
2543 guint8*
2544 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2545 {
2546 #ifdef PLATFORM_WIN32
2547         g_assert (tls_offset < 64);
2548         x86_prefix (code, X86_GS_PREFIX);
2549         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2550 #else
2551         if (optimize_for_xen) {
2552                 x86_prefix (code, X86_FS_PREFIX);
2553                 amd64_mov_reg_mem (code, dreg, 0, 8);
2554                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2555         } else {
2556                 x86_prefix (code, X86_FS_PREFIX);
2557                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2558         }
2559 #endif
2560         return code;
2561 }
2562
2563 #define REAL_PRINT_REG(text,reg) \
2564 mono_assert (reg >= 0); \
2565 amd64_push_reg (code, AMD64_RAX); \
2566 amd64_push_reg (code, AMD64_RDX); \
2567 amd64_push_reg (code, AMD64_RCX); \
2568 amd64_push_reg (code, reg); \
2569 amd64_push_imm (code, reg); \
2570 amd64_push_imm (code, text " %d %p\n"); \
2571 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2572 amd64_call_reg (code, AMD64_RAX); \
2573 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2574 amd64_pop_reg (code, AMD64_RCX); \
2575 amd64_pop_reg (code, AMD64_RDX); \
2576 amd64_pop_reg (code, AMD64_RAX);
2577
2578 /* benchmark and set based on cpu */
2579 #define LOOP_ALIGNMENT 8
2580 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2581
2582 #ifndef DISABLE_JIT
2583
2584 void
2585 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2586 {
2587         MonoInst *ins;
2588         MonoCallInst *call;
2589         guint offset;
2590         guint8 *code = cfg->native_code + cfg->code_len;
2591         MonoInst *last_ins = NULL;
2592         guint last_offset = 0;
2593         int max_len, cpos;
2594
2595         if (cfg->opt & MONO_OPT_LOOP) {
2596                 int pad, align = LOOP_ALIGNMENT;
2597                 /* set alignment depending on cpu */
2598                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2599                         pad = align - pad;
2600                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2601                         amd64_padding (code, pad);
2602                         cfg->code_len += pad;
2603                         bb->native_offset = cfg->code_len;
2604                 }
2605         }
2606
2607         if (cfg->verbose_level > 2)
2608                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2609
2610         cpos = bb->max_offset;
2611
2612         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2613                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2614                 g_assert (!cfg->compile_aot);
2615                 cpos += 6;
2616
2617                 cov->data [bb->dfn].cil_code = bb->cil_code;
2618                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2619                 /* this is not thread save, but good enough */
2620                 amd64_inc_membase (code, AMD64_R11, 0);
2621         }
2622
2623         offset = code - cfg->native_code;
2624
2625         mono_debug_open_block (cfg, bb, offset);
2626
2627     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2628                 x86_breakpoint (code);
2629
2630         MONO_BB_FOR_EACH_INS (bb, ins) {
2631                 offset = code - cfg->native_code;
2632
2633                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2634
2635                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2636                         cfg->code_size *= 2;
2637                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2638                         code = cfg->native_code + offset;
2639                         mono_jit_stats.code_reallocs++;
2640                 }
2641
2642                 if (cfg->debug_info)
2643                         mono_debug_record_line_number (cfg, ins, offset);
2644
2645                 switch (ins->opcode) {
2646                 case OP_BIGMUL:
2647                         amd64_mul_reg (code, ins->sreg2, TRUE);
2648                         break;
2649                 case OP_BIGMUL_UN:
2650                         amd64_mul_reg (code, ins->sreg2, FALSE);
2651                         break;
2652                 case OP_X86_SETEQ_MEMBASE:
2653                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2654                         break;
2655                 case OP_STOREI1_MEMBASE_IMM:
2656                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2657                         break;
2658                 case OP_STOREI2_MEMBASE_IMM:
2659                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2660                         break;
2661                 case OP_STOREI4_MEMBASE_IMM:
2662                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2663                         break;
2664                 case OP_STOREI1_MEMBASE_REG:
2665                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2666                         break;
2667                 case OP_STOREI2_MEMBASE_REG:
2668                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2669                         break;
2670                 case OP_STORE_MEMBASE_REG:
2671                 case OP_STOREI8_MEMBASE_REG:
2672                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2673                         break;
2674                 case OP_STOREI4_MEMBASE_REG:
2675                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2676                         break;
2677                 case OP_STORE_MEMBASE_IMM:
2678                 case OP_STOREI8_MEMBASE_IMM:
2679                         g_assert (amd64_is_imm32 (ins->inst_imm));
2680                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2681                         break;
2682                 case OP_LOAD_MEM:
2683                 case OP_LOADI8_MEM:
2684                         // FIXME: Decompose this earlier
2685                         if (amd64_is_imm32 (ins->inst_imm))
2686                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2687                         else {
2688                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2689                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2690                         }
2691                         break;
2692                 case OP_LOADI4_MEM:
2693                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2694                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2695                         break;
2696                 case OP_LOADU4_MEM:
2697                         // FIXME: Decompose this earlier
2698                         if (amd64_is_imm32 (ins->inst_imm))
2699                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2700                         else {
2701                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2702                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2703                         }
2704                         break;
2705                 case OP_LOADU1_MEM:
2706                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2707                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2708                         break;
2709                 case OP_LOADU2_MEM:
2710                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2711                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2712                         break;
2713                 case OP_LOAD_MEMBASE:
2714                 case OP_LOADI8_MEMBASE:
2715                         g_assert (amd64_is_imm32 (ins->inst_offset));
2716                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2717                         break;
2718                 case OP_LOADI4_MEMBASE:
2719                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2720                         break;
2721                 case OP_LOADU4_MEMBASE:
2722                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2723                         break;
2724                 case OP_LOADU1_MEMBASE:
2725                         /* The cpu zero extends the result into 64 bits */
2726                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2727                         break;
2728                 case OP_LOADI1_MEMBASE:
2729                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2730                         break;
2731                 case OP_LOADU2_MEMBASE:
2732                         /* The cpu zero extends the result into 64 bits */
2733                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2734                         break;
2735                 case OP_LOADI2_MEMBASE:
2736                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2737                         break;
2738                 case OP_AMD64_LOADI8_MEMINDEX:
2739                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2740                         break;
2741                 case OP_LCONV_TO_I1:
2742                 case OP_ICONV_TO_I1:
2743                 case OP_SEXT_I1:
2744                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2745                         break;
2746                 case OP_LCONV_TO_I2:
2747                 case OP_ICONV_TO_I2:
2748                 case OP_SEXT_I2:
2749                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2750                         break;
2751                 case OP_LCONV_TO_U1:
2752                 case OP_ICONV_TO_U1:
2753                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2754                         break;
2755                 case OP_LCONV_TO_U2:
2756                 case OP_ICONV_TO_U2:
2757                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2758                         break;
2759                 case OP_ZEXT_I4:
2760                         /* Clean out the upper word */
2761                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2762                         break;
2763                 case OP_SEXT_I4:
2764                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2765                         break;
2766                 case OP_COMPARE:
2767                 case OP_LCOMPARE:
2768                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2769                         break;
2770                 case OP_COMPARE_IMM:
2771                 case OP_LCOMPARE_IMM:
2772                         g_assert (amd64_is_imm32 (ins->inst_imm));
2773                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2774                         break;
2775                 case OP_X86_COMPARE_REG_MEMBASE:
2776                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2777                         break;
2778                 case OP_X86_TEST_NULL:
2779                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2780                         break;
2781                 case OP_AMD64_TEST_NULL:
2782                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2783                         break;
2784
2785                 case OP_X86_ADD_REG_MEMBASE:
2786                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2787                         break;
2788                 case OP_X86_SUB_REG_MEMBASE:
2789                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2790                         break;
2791                 case OP_X86_AND_REG_MEMBASE:
2792                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2793                         break;
2794                 case OP_X86_OR_REG_MEMBASE:
2795                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2796                         break;
2797                 case OP_X86_XOR_REG_MEMBASE:
2798                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2799                         break;
2800
2801                 case OP_X86_ADD_MEMBASE_IMM:
2802                         /* FIXME: Make a 64 version too */
2803                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2804                         break;
2805                 case OP_X86_SUB_MEMBASE_IMM:
2806                         g_assert (amd64_is_imm32 (ins->inst_imm));
2807                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2808                         break;
2809                 case OP_X86_AND_MEMBASE_IMM:
2810                         g_assert (amd64_is_imm32 (ins->inst_imm));
2811                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2812                         break;
2813                 case OP_X86_OR_MEMBASE_IMM:
2814                         g_assert (amd64_is_imm32 (ins->inst_imm));
2815                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2816                         break;
2817                 case OP_X86_XOR_MEMBASE_IMM:
2818                         g_assert (amd64_is_imm32 (ins->inst_imm));
2819                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2820                         break;
2821                 case OP_X86_ADD_MEMBASE_REG:
2822                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2823                         break;
2824                 case OP_X86_SUB_MEMBASE_REG:
2825                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2826                         break;
2827                 case OP_X86_AND_MEMBASE_REG:
2828                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2829                         break;
2830                 case OP_X86_OR_MEMBASE_REG:
2831                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2832                         break;
2833                 case OP_X86_XOR_MEMBASE_REG:
2834                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2835                         break;
2836                 case OP_X86_INC_MEMBASE:
2837                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2838                         break;
2839                 case OP_X86_INC_REG:
2840                         amd64_inc_reg_size (code, ins->dreg, 4);
2841                         break;
2842                 case OP_X86_DEC_MEMBASE:
2843                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2844                         break;
2845                 case OP_X86_DEC_REG:
2846                         amd64_dec_reg_size (code, ins->dreg, 4);
2847                         break;
2848                 case OP_X86_MUL_REG_MEMBASE:
2849                 case OP_X86_MUL_MEMBASE_REG:
2850                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2851                         break;
2852                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2853                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2854                         break;
2855                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2856                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2857                         break;
2858                 case OP_AMD64_COMPARE_MEMBASE_REG:
2859                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2860                         break;
2861                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2862                         g_assert (amd64_is_imm32 (ins->inst_imm));
2863                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2864                         break;
2865                 case OP_X86_COMPARE_MEMBASE8_IMM:
2866                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2867                         break;
2868                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2869                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2870                         break;
2871                 case OP_AMD64_COMPARE_REG_MEMBASE:
2872                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2873                         break;
2874
2875                 case OP_AMD64_ADD_REG_MEMBASE:
2876                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2877                         break;
2878                 case OP_AMD64_SUB_REG_MEMBASE:
2879                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2880                         break;
2881                 case OP_AMD64_AND_REG_MEMBASE:
2882                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2883                         break;
2884                 case OP_AMD64_OR_REG_MEMBASE:
2885                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2886                         break;
2887                 case OP_AMD64_XOR_REG_MEMBASE:
2888                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2889                         break;
2890
2891                 case OP_AMD64_ADD_MEMBASE_REG:
2892                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2893                         break;
2894                 case OP_AMD64_SUB_MEMBASE_REG:
2895                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2896                         break;
2897                 case OP_AMD64_AND_MEMBASE_REG:
2898                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2899                         break;
2900                 case OP_AMD64_OR_MEMBASE_REG:
2901                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2902                         break;
2903                 case OP_AMD64_XOR_MEMBASE_REG:
2904                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2905                         break;
2906
2907                 case OP_AMD64_ADD_MEMBASE_IMM:
2908                         g_assert (amd64_is_imm32 (ins->inst_imm));
2909                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2910                         break;
2911                 case OP_AMD64_SUB_MEMBASE_IMM:
2912                         g_assert (amd64_is_imm32 (ins->inst_imm));
2913                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2914                         break;
2915                 case OP_AMD64_AND_MEMBASE_IMM:
2916                         g_assert (amd64_is_imm32 (ins->inst_imm));
2917                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2918                         break;
2919                 case OP_AMD64_OR_MEMBASE_IMM:
2920                         g_assert (amd64_is_imm32 (ins->inst_imm));
2921                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2922                         break;
2923                 case OP_AMD64_XOR_MEMBASE_IMM:
2924                         g_assert (amd64_is_imm32 (ins->inst_imm));
2925                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2926                         break;
2927
2928                 case OP_BREAK:
2929                         amd64_breakpoint (code);
2930                         break;
2931                 case OP_RELAXED_NOP:
2932                         x86_prefix (code, X86_REP_PREFIX);
2933                         x86_nop (code);
2934                         break;
2935                 case OP_HARD_NOP:
2936                         x86_nop (code);
2937                         break;
2938                 case OP_NOP:
2939                 case OP_DUMMY_USE:
2940                 case OP_DUMMY_STORE:
2941                 case OP_NOT_REACHED:
2942                 case OP_NOT_NULL:
2943                         break;
2944                 case OP_ADDCC:
2945                 case OP_LADD:
2946                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2947                         break;
2948                 case OP_ADC:
2949                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2950                         break;
2951                 case OP_ADD_IMM:
2952                 case OP_LADD_IMM:
2953                         g_assert (amd64_is_imm32 (ins->inst_imm));
2954                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2955                         break;
2956                 case OP_ADC_IMM:
2957                         g_assert (amd64_is_imm32 (ins->inst_imm));
2958                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2959                         break;
2960                 case OP_SUBCC:
2961                 case OP_LSUB:
2962                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2963                         break;
2964                 case OP_SBB:
2965                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2966                         break;
2967                 case OP_SUB_IMM:
2968                 case OP_LSUB_IMM:
2969                         g_assert (amd64_is_imm32 (ins->inst_imm));
2970                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2971                         break;
2972                 case OP_SBB_IMM:
2973                         g_assert (amd64_is_imm32 (ins->inst_imm));
2974                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2975                         break;
2976                 case OP_LAND:
2977                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2978                         break;
2979                 case OP_AND_IMM:
2980                 case OP_LAND_IMM:
2981                         g_assert (amd64_is_imm32 (ins->inst_imm));
2982                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2983                         break;
2984                 case OP_LMUL:
2985                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2986                         break;
2987                 case OP_MUL_IMM:
2988                 case OP_LMUL_IMM:
2989                 case OP_IMUL_IMM: {
2990                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2991
2992                         switch (ins->inst_imm) {
2993                         case 2:
2994                                 /* MOV r1, r2 */
2995                                 /* ADD r1, r1 */
2996                                 if (ins->dreg != ins->sreg1)
2997                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2998                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2999                                 break;
3000                         case 3:
3001                                 /* LEA r1, [r2 + r2*2] */
3002                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3003                                 break;
3004                         case 5:
3005                                 /* LEA r1, [r2 + r2*4] */
3006                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3007                                 break;
3008                         case 6:
3009                                 /* LEA r1, [r2 + r2*2] */
3010                                 /* ADD r1, r1          */
3011                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3012                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3013                                 break;
3014                         case 9:
3015                                 /* LEA r1, [r2 + r2*8] */
3016                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3017                                 break;
3018                         case 10:
3019                                 /* LEA r1, [r2 + r2*4] */
3020                                 /* ADD r1, r1          */
3021                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3022                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3023                                 break;
3024                         case 12:
3025                                 /* LEA r1, [r2 + r2*2] */
3026                                 /* SHL r1, 2           */
3027                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3028                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3029                                 break;
3030                         case 25:
3031                                 /* LEA r1, [r2 + r2*4] */
3032                                 /* LEA r1, [r1 + r1*4] */
3033                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3034                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3035                                 break;
3036                         case 100:
3037                                 /* LEA r1, [r2 + r2*4] */
3038                                 /* SHL r1, 2           */
3039                                 /* LEA r1, [r1 + r1*4] */
3040                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3041                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3042                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3043                                 break;
3044                         default:
3045                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3046                                 break;
3047                         }
3048                         break;
3049                 }
3050                 case OP_LDIV:
3051                 case OP_LREM:
3052                         /* Regalloc magic makes the div/rem cases the same */
3053                         if (ins->sreg2 == AMD64_RDX) {
3054                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3055                                 amd64_cdq (code);
3056                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3057                         } else {
3058                                 amd64_cdq (code);
3059                                 amd64_div_reg (code, ins->sreg2, TRUE);
3060                         }
3061                         break;
3062                 case OP_LDIV_UN:
3063                 case OP_LREM_UN:
3064                         if (ins->sreg2 == AMD64_RDX) {
3065                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3066                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3067                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3068                         } else {
3069                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3070                                 amd64_div_reg (code, ins->sreg2, FALSE);
3071                         }
3072                         break;
3073                 case OP_IDIV:
3074                 case OP_IREM:
3075                         if (ins->sreg2 == AMD64_RDX) {
3076                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3077                                 amd64_cdq_size (code, 4);
3078                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3079                         } else {
3080                                 amd64_cdq_size (code, 4);
3081                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3082                         }
3083                         break;
3084                 case OP_IDIV_UN:
3085                 case OP_IREM_UN:
3086                         if (ins->sreg2 == AMD64_RDX) {
3087                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3088                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3089                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3090                         } else {
3091                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3092                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3093                         }
3094                         break;
3095                 case OP_IREM_IMM: {
3096                         int power = mono_is_power_of_two (ins->inst_imm);
3097
3098                         g_assert (ins->sreg1 == X86_EAX);
3099                         g_assert (ins->dreg == X86_EAX);
3100                         g_assert (power >= 0);
3101
3102                         if (power == 0) {
3103                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3104                                 break;
3105                         }
3106
3107                         /* Based on gcc code */
3108
3109                         /* Add compensation for negative dividents */
3110                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3111                         if (power > 1)
3112                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3113                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3114                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3115                         /* Compute remainder */
3116                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3117                         /* Remove compensation */
3118                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3119                         break;
3120                 }
3121                 case OP_LMUL_OVF:
3122                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3123                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3124                         break;
3125                 case OP_LOR:
3126                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3127                         break;
3128                 case OP_OR_IMM:
3129                 case OP_LOR_IMM:
3130                         g_assert (amd64_is_imm32 (ins->inst_imm));
3131                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3132                         break;
3133                 case OP_LXOR:
3134                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3135                         break;
3136                 case OP_XOR_IMM:
3137                 case OP_LXOR_IMM:
3138                         g_assert (amd64_is_imm32 (ins->inst_imm));
3139                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3140                         break;
3141                 case OP_LSHL:
3142                         g_assert (ins->sreg2 == AMD64_RCX);
3143                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3144                         break;
3145                 case OP_LSHR:
3146                         g_assert (ins->sreg2 == AMD64_RCX);
3147                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3148                         break;
3149                 case OP_SHR_IMM:
3150                         g_assert (amd64_is_imm32 (ins->inst_imm));
3151                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3152                         break;
3153                 case OP_LSHR_IMM:
3154                         g_assert (amd64_is_imm32 (ins->inst_imm));
3155                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3156                         break;
3157                 case OP_SHR_UN_IMM:
3158                         g_assert (amd64_is_imm32 (ins->inst_imm));
3159                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3160                         break;
3161                 case OP_LSHR_UN_IMM:
3162                         g_assert (amd64_is_imm32 (ins->inst_imm));
3163                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3164                         break;
3165                 case OP_LSHR_UN:
3166                         g_assert (ins->sreg2 == AMD64_RCX);
3167                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3168                         break;
3169                 case OP_SHL_IMM:
3170                         g_assert (amd64_is_imm32 (ins->inst_imm));
3171                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3172                         break;
3173                 case OP_LSHL_IMM:
3174                         g_assert (amd64_is_imm32 (ins->inst_imm));
3175                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3176                         break;
3177
3178                 case OP_IADDCC:
3179                 case OP_IADD:
3180                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3181                         break;
3182                 case OP_IADC:
3183                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3184                         break;
3185                 case OP_IADD_IMM:
3186                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3187                         break;
3188                 case OP_IADC_IMM:
3189                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3190                         break;
3191                 case OP_ISUBCC:
3192                 case OP_ISUB:
3193                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3194                         break;
3195                 case OP_ISBB:
3196                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3197                         break;
3198                 case OP_ISUB_IMM:
3199                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3200                         break;
3201                 case OP_ISBB_IMM:
3202                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3203                         break;
3204                 case OP_IAND:
3205                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3206                         break;
3207                 case OP_IAND_IMM:
3208                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3209                         break;
3210                 case OP_IOR:
3211                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3212                         break;
3213                 case OP_IOR_IMM:
3214                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3215                         break;
3216                 case OP_IXOR:
3217                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3218                         break;
3219                 case OP_IXOR_IMM:
3220                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3221                         break;
3222                 case OP_INEG:
3223                         amd64_neg_reg_size (code, ins->sreg1, 4);
3224                         break;
3225                 case OP_INOT:
3226                         amd64_not_reg_size (code, ins->sreg1, 4);
3227                         break;
3228                 case OP_ISHL:
3229                         g_assert (ins->sreg2 == AMD64_RCX);
3230                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3231                         break;
3232                 case OP_ISHR:
3233                         g_assert (ins->sreg2 == AMD64_RCX);
3234                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3235                         break;
3236                 case OP_ISHR_IMM:
3237                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3238                         break;
3239                 case OP_ISHR_UN_IMM:
3240                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3241                         break;
3242                 case OP_ISHR_UN:
3243                         g_assert (ins->sreg2 == AMD64_RCX);
3244                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3245                         break;
3246                 case OP_ISHL_IMM:
3247                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3248                         break;
3249                 case OP_IMUL:
3250                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3251                         break;
3252                 case OP_IMUL_OVF:
3253                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3254                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3255                         break;
3256                 case OP_IMUL_OVF_UN:
3257                 case OP_LMUL_OVF_UN: {
3258                         /* the mul operation and the exception check should most likely be split */
3259                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3260                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3261                         /*g_assert (ins->sreg2 == X86_EAX);
3262                         g_assert (ins->dreg == X86_EAX);*/
3263                         if (ins->sreg2 == X86_EAX) {
3264                                 non_eax_reg = ins->sreg1;
3265                         } else if (ins->sreg1 == X86_EAX) {
3266                                 non_eax_reg = ins->sreg2;
3267                         } else {
3268                                 /* no need to save since we're going to store to it anyway */
3269                                 if (ins->dreg != X86_EAX) {
3270                                         saved_eax = TRUE;
3271                                         amd64_push_reg (code, X86_EAX);
3272                                 }
3273                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3274                                 non_eax_reg = ins->sreg2;
3275                         }
3276                         if (ins->dreg == X86_EDX) {
3277                                 if (!saved_eax) {
3278                                         saved_eax = TRUE;
3279                                         amd64_push_reg (code, X86_EAX);
3280                                 }
3281                         } else {
3282                                 saved_edx = TRUE;
3283                                 amd64_push_reg (code, X86_EDX);
3284                         }
3285                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3286                         /* save before the check since pop and mov don't change the flags */
3287                         if (ins->dreg != X86_EAX)
3288                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3289                         if (saved_edx)
3290                                 amd64_pop_reg (code, X86_EDX);
3291                         if (saved_eax)
3292                                 amd64_pop_reg (code, X86_EAX);
3293                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3294                         break;
3295                 }
3296                 case OP_ICOMPARE:
3297                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3298                         break;
3299                 case OP_ICOMPARE_IMM:
3300                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3301                         break;
3302                 case OP_IBEQ:
3303                 case OP_IBLT:
3304                 case OP_IBGT:
3305                 case OP_IBGE:
3306                 case OP_IBLE:
3307                 case OP_LBEQ:
3308                 case OP_LBLT:
3309                 case OP_LBGT:
3310                 case OP_LBGE:
3311                 case OP_LBLE:
3312                 case OP_IBNE_UN:
3313                 case OP_IBLT_UN:
3314                 case OP_IBGT_UN:
3315                 case OP_IBGE_UN:
3316                 case OP_IBLE_UN:
3317                 case OP_LBNE_UN:
3318                 case OP_LBLT_UN:
3319                 case OP_LBGT_UN:
3320                 case OP_LBGE_UN:
3321                 case OP_LBLE_UN:
3322                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3323                         break;
3324
3325                 case OP_CMOV_IEQ:
3326                 case OP_CMOV_IGE:
3327                 case OP_CMOV_IGT:
3328                 case OP_CMOV_ILE:
3329                 case OP_CMOV_ILT:
3330                 case OP_CMOV_INE_UN:
3331                 case OP_CMOV_IGE_UN:
3332                 case OP_CMOV_IGT_UN:
3333                 case OP_CMOV_ILE_UN:
3334                 case OP_CMOV_ILT_UN:
3335                 case OP_CMOV_LEQ:
3336                 case OP_CMOV_LGE:
3337                 case OP_CMOV_LGT:
3338                 case OP_CMOV_LLE:
3339                 case OP_CMOV_LLT:
3340                 case OP_CMOV_LNE_UN:
3341                 case OP_CMOV_LGE_UN:
3342                 case OP_CMOV_LGT_UN:
3343                 case OP_CMOV_LLE_UN:
3344                 case OP_CMOV_LLT_UN:
3345                         g_assert (ins->dreg == ins->sreg1);
3346                         /* This needs to operate on 64 bit values */
3347                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3348                         break;
3349
3350                 case OP_LNOT:
3351                         amd64_not_reg (code, ins->sreg1);
3352                         break;
3353                 case OP_LNEG:
3354                         amd64_neg_reg (code, ins->sreg1);
3355                         break;
3356
3357                 case OP_ICONST:
3358                 case OP_I8CONST:
3359                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3360                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3361                         else
3362                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3363                         break;
3364                 case OP_AOTCONST:
3365                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3366                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3367                         break;
3368                 case OP_JUMP_TABLE:
3369                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3370                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3371                         break;
3372                 case OP_MOVE:
3373                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3374                         break;
3375                 case OP_AMD64_SET_XMMREG_R4: {
3376                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3377                         break;
3378                 }
3379                 case OP_AMD64_SET_XMMREG_R8: {
3380                         if (ins->dreg != ins->sreg1)
3381                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3382                         break;
3383                 }
3384                 case OP_TAILCALL: {
3385                         /*
3386                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3387                          * Keep in sync with the code in emit_epilog.
3388                          */
3389                         int pos = 0, i;
3390
3391                         /* FIXME: no tracing support... */
3392                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3393                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3394
3395                         g_assert (!cfg->method->save_lmf);
3396
3397                         if (cfg->arch.omit_fp) {
3398                                 guint32 save_offset = 0;
3399                                 /* Pop callee-saved registers */
3400                                 for (i = 0; i < AMD64_NREG; ++i)
3401                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3402                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3403                                                 save_offset += 8;
3404                                         }
3405                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3406                         }
3407                         else {
3408                                 for (i = 0; i < AMD64_NREG; ++i)
3409                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3410                                                 pos -= sizeof (gpointer);
3411
3412                                 if (pos)
3413                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3414
3415                                 /* Pop registers in reverse order */
3416                                 for (i = AMD64_NREG - 1; i > 0; --i)
3417                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3418                                                 amd64_pop_reg (code, i);
3419                                         }
3420
3421                                 amd64_leave (code);
3422                         }
3423
3424                         offset = code - cfg->native_code;
3425                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3426                         if (cfg->compile_aot)
3427                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3428                         else
3429                                 amd64_set_reg_template (code, AMD64_R11);
3430                         amd64_jump_reg (code, AMD64_R11);
3431                         break;
3432                 }
3433                 case OP_CHECK_THIS:
3434                         /* ensure ins->sreg1 is not NULL */
3435                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3436                         break;
3437                 case OP_ARGLIST: {
3438                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3439                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3440                         break;
3441                 }
3442                 case OP_CALL:
3443                 case OP_FCALL:
3444                 case OP_LCALL:
3445                 case OP_VCALL:
3446                 case OP_VCALL2:
3447                 case OP_VOIDCALL:
3448                         call = (MonoCallInst*)ins;
3449                         /*
3450                          * The AMD64 ABI forces callers to know about varargs.
3451                          */
3452                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3453                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3454                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3455                                 /*
3456                                  * Since the unmanaged calling convention doesn't contain a
3457                                  * 'vararg' entry, we have to treat every pinvoke call as a
3458                                  * potential vararg call.
3459                                  */
3460                                 guint32 nregs, i;
3461                                 nregs = 0;
3462                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3463                                         if (call->used_fregs & (1 << i))
3464                                                 nregs ++;
3465                                 if (!nregs)
3466                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3467                                 else
3468                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3469                         }
3470
3471                         if (ins->flags & MONO_INST_HAS_METHOD)
3472                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3473                         else
3474                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3475                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3476                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3477                         code = emit_move_return_value (cfg, ins, code);
3478                         break;
3479                 case OP_FCALL_REG:
3480                 case OP_LCALL_REG:
3481                 case OP_VCALL_REG:
3482                 case OP_VCALL2_REG:
3483                 case OP_VOIDCALL_REG:
3484                 case OP_CALL_REG:
3485                         call = (MonoCallInst*)ins;
3486
3487                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3488                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3489                                 ins->sreg1 = AMD64_R11;
3490                         }
3491
3492                         /*
3493                          * The AMD64 ABI forces callers to know about varargs.
3494                          */
3495                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3496                                 if (ins->sreg1 == AMD64_RAX) {
3497                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3498                                         ins->sreg1 = AMD64_R11;
3499                                 }
3500                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3501                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3502                                 /*
3503                                  * Since the unmanaged calling convention doesn't contain a
3504                                  * 'vararg' entry, we have to treat every pinvoke call as a
3505                                  * potential vararg call.
3506                                  */
3507                                 guint32 nregs, i;
3508                                 nregs = 0;
3509                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3510                                         if (call->used_fregs & (1 << i))
3511                                                 nregs ++;
3512                                 if (ins->sreg1 == AMD64_RAX) {
3513                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3514                                         ins->sreg1 = AMD64_R11;
3515                                 }
3516                                 if (!nregs)
3517                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3518                                 else
3519                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3520                         }
3521
3522                         amd64_call_reg (code, ins->sreg1);
3523                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3524                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3525                         code = emit_move_return_value (cfg, ins, code);
3526                         break;
3527                 case OP_FCALL_MEMBASE:
3528                 case OP_LCALL_MEMBASE:
3529                 case OP_VCALL_MEMBASE:
3530                 case OP_VCALL2_MEMBASE:
3531                 case OP_VOIDCALL_MEMBASE:
3532                 case OP_CALL_MEMBASE:
3533                         call = (MonoCallInst*)ins;
3534
3535                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3536                                 /*
3537                                  * Can't use R11 because it is clobbered by the trampoline
3538                                  * code, and the reg value is needed by get_vcall_slot_addr.
3539                                  */
3540                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3541                                 ins->sreg1 = AMD64_RAX;
3542                         }
3543
3544                         /*
3545                          * Emit a few nops to simplify get_vcall_slot ().
3546                          */
3547                         amd64_nop (code);
3548                         amd64_nop (code);
3549                         amd64_nop (code);
3550
3551                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3552                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3553                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3554                         code = emit_move_return_value (cfg, ins, code);
3555                         break;
3556                 case OP_AMD64_SAVE_SP_TO_LMF:
3557                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3558                         break;
3559                 case OP_X86_PUSH:
3560                         amd64_push_reg (code, ins->sreg1);
3561                         break;
3562                 case OP_X86_PUSH_IMM:
3563                         g_assert (amd64_is_imm32 (ins->inst_imm));
3564                         amd64_push_imm (code, ins->inst_imm);
3565                         break;
3566                 case OP_X86_PUSH_MEMBASE:
3567                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3568                         break;
3569                 case OP_X86_PUSH_OBJ: {
3570                         int size = ALIGN_TO (ins->inst_imm, 8);
3571                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3572                         amd64_push_reg (code, AMD64_RDI);
3573                         amd64_push_reg (code, AMD64_RSI);
3574                         amd64_push_reg (code, AMD64_RCX);
3575                         if (ins->inst_offset)
3576                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3577                         else
3578                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3579                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3580                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3581                         amd64_cld (code);
3582                         amd64_prefix (code, X86_REP_PREFIX);
3583                         amd64_movsd (code);
3584                         amd64_pop_reg (code, AMD64_RCX);
3585                         amd64_pop_reg (code, AMD64_RSI);
3586                         amd64_pop_reg (code, AMD64_RDI);
3587                         break;
3588                 }
3589                 case OP_X86_LEA:
3590                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3591                         break;
3592                 case OP_X86_LEA_MEMBASE:
3593                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3594                         break;
3595                 case OP_X86_XCHG:
3596                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3597                         break;
3598                 case OP_LOCALLOC:
3599                         /* keep alignment */
3600                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3601                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3602                         code = mono_emit_stack_alloc (code, ins);
3603                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3604                         break;
3605                 case OP_LOCALLOC_IMM: {
3606                         guint32 size = ins->inst_imm;
3607                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3608
3609                         if (ins->flags & MONO_INST_INIT) {
3610                                 if (size < 64) {
3611                                         int i;
3612
3613                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3614                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3615
3616                                         for (i = 0; i < size; i += 8)
3617                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3618                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3619                                 } else {
3620                                         amd64_mov_reg_imm (code, ins->dreg, size);
3621                                         ins->sreg1 = ins->dreg;
3622
3623                                         code = mono_emit_stack_alloc (code, ins);
3624                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3625                                 }
3626                         } else {
3627                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3628                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3629                         }
3630                         break;
3631                 }
3632                 case OP_THROW: {
3633                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3634                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3635                                              (gpointer)"mono_arch_throw_exception", FALSE);
3636                         break;
3637                 }
3638                 case OP_RETHROW: {
3639                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3640                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3641                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3642                         break;
3643                 }
3644                 case OP_CALL_HANDLER:
3645                         /* Align stack */
3646                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3647                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3648                         amd64_call_imm (code, 0);
3649                         /* Restore stack alignment */
3650                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3651                         break;
3652                 case OP_START_HANDLER: {
3653                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3654                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3655                         break;
3656                 }
3657                 case OP_ENDFINALLY: {
3658                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3659                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3660                         amd64_ret (code);
3661                         break;
3662                 }
3663                 case OP_ENDFILTER: {
3664                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3665                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3666                         /* The local allocator will put the result into RAX */
3667                         amd64_ret (code);
3668                         break;
3669                 }
3670
3671                 case OP_LABEL:
3672                         ins->inst_c0 = code - cfg->native_code;
3673                         break;
3674                 case OP_BR:
3675                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3676                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3677                         //break;
3678                         if (ins->flags & MONO_INST_BRLABEL) {
3679                                 if (ins->inst_i0->inst_c0) {
3680                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3681                                 } else {
3682                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3683                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3684                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3685                                                 x86_jump8 (code, 0);
3686                                         else
3687                                                 x86_jump32 (code, 0);
3688                                 }
3689                         } else {
3690                                 if (ins->inst_target_bb->native_offset) {
3691                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3692                                 } else {
3693                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3694                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3695                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3696                                                 x86_jump8 (code, 0);
3697                                         else
3698                                                 x86_jump32 (code, 0);
3699                                 }
3700                         }
3701                         break;
3702                 case OP_BR_REG:
3703                         amd64_jump_reg (code, ins->sreg1);
3704                         break;
3705                 case OP_CEQ:
3706                 case OP_LCEQ:
3707                 case OP_ICEQ:
3708                 case OP_CLT:
3709                 case OP_LCLT:
3710                 case OP_ICLT:
3711                 case OP_CGT:
3712                 case OP_ICGT:
3713                 case OP_LCGT:
3714                 case OP_CLT_UN:
3715                 case OP_LCLT_UN:
3716                 case OP_ICLT_UN:
3717                 case OP_CGT_UN:
3718                 case OP_LCGT_UN:
3719                 case OP_ICGT_UN:
3720                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3721                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3722                         break;
3723                 case OP_COND_EXC_EQ:
3724                 case OP_COND_EXC_NE_UN:
3725                 case OP_COND_EXC_LT:
3726                 case OP_COND_EXC_LT_UN:
3727                 case OP_COND_EXC_GT:
3728                 case OP_COND_EXC_GT_UN:
3729                 case OP_COND_EXC_GE:
3730                 case OP_COND_EXC_GE_UN:
3731                 case OP_COND_EXC_LE:
3732                 case OP_COND_EXC_LE_UN:
3733                 case OP_COND_EXC_IEQ:
3734                 case OP_COND_EXC_INE_UN:
3735                 case OP_COND_EXC_ILT:
3736                 case OP_COND_EXC_ILT_UN:
3737                 case OP_COND_EXC_IGT:
3738                 case OP_COND_EXC_IGT_UN:
3739                 case OP_COND_EXC_IGE:
3740                 case OP_COND_EXC_IGE_UN:
3741                 case OP_COND_EXC_ILE:
3742                 case OP_COND_EXC_ILE_UN:
3743                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3744                         break;
3745                 case OP_COND_EXC_OV:
3746                 case OP_COND_EXC_NO:
3747                 case OP_COND_EXC_C:
3748                 case OP_COND_EXC_NC:
3749                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3750                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3751                         break;
3752                 case OP_COND_EXC_IOV:
3753                 case OP_COND_EXC_INO:
3754                 case OP_COND_EXC_IC:
3755                 case OP_COND_EXC_INC:
3756                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3757                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3758                         break;
3759
3760                 /* floating point opcodes */
3761                 case OP_R8CONST: {
3762                         double d = *(double *)ins->inst_p0;
3763
3764                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3765                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3766                         }
3767                         else {
3768                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3769                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3770                         }
3771                         break;
3772                 }
3773                 case OP_R4CONST: {
3774                         float f = *(float *)ins->inst_p0;
3775
3776                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3777                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3778                         }
3779                         else {
3780                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3781                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3782                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3783                         }
3784                         break;
3785                 }
3786                 case OP_STORER8_MEMBASE_REG:
3787                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3788                         break;
3789                 case OP_LOADR8_SPILL_MEMBASE:
3790                         g_assert_not_reached ();
3791                         break;
3792                 case OP_LOADR8_MEMBASE:
3793                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3794                         break;
3795                 case OP_STORER4_MEMBASE_REG:
3796                         /* This requires a double->single conversion */
3797                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3798                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3799                         break;
3800                 case OP_LOADR4_MEMBASE:
3801                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3802                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3803                         break;
3804                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3805                 case OP_ICONV_TO_R8:
3806                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3807                         break;
3808                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3809                 case OP_LCONV_TO_R8:
3810                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3811                         break;
3812                 case OP_FCONV_TO_R4:
3813                         /* FIXME: nothing to do ?? */
3814                         break;
3815                 case OP_FCONV_TO_I1:
3816                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3817                         break;
3818                 case OP_FCONV_TO_U1:
3819                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3820                         break;
3821                 case OP_FCONV_TO_I2:
3822                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3823                         break;
3824                 case OP_FCONV_TO_U2:
3825                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3826                         break;
3827                 case OP_FCONV_TO_U4:
3828                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3829                         break;
3830                 case OP_FCONV_TO_I4:
3831                 case OP_FCONV_TO_I:
3832                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3833                         break;
3834                 case OP_FCONV_TO_I8:
3835                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3836                         break;
3837                 case OP_LCONV_TO_R_UN: {
3838                         guint8 *br [2];
3839
3840                         /* Based on gcc code */
3841                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3842                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3843
3844                         /* Positive case */
3845                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3846                         br [1] = code; x86_jump8 (code, 0);
3847                         amd64_patch (br [0], code);
3848
3849                         /* Negative case */
3850                         /* Save to the red zone */
3851                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3852                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3853                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3854                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3855                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3856                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3857                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3858                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3859                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3860                         /* Restore */
3861                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3862                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3863                         amd64_patch (br [1], code);
3864                         break;
3865                 }
3866                 case OP_LCONV_TO_OVF_U4:
3867                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3868                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3869                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3870                         break;
3871                 case OP_LCONV_TO_OVF_I4_UN:
3872                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3873                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3874                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3875                         break;
3876                 case OP_FMOVE:
3877                         if (ins->dreg != ins->sreg1)
3878                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3879                         break;
3880                 case OP_FADD:
3881                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3882                         break;
3883                 case OP_FSUB:
3884                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3885                         break;
3886                 case OP_FMUL:
3887                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3888                         break;
3889                 case OP_FDIV:
3890                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3891                         break;
3892                 case OP_FNEG: {
3893                         static double r8_0 = -0.0;
3894
3895                         g_assert (ins->sreg1 == ins->dreg);
3896
3897                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3898                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3899                         break;
3900                 }
3901                 case OP_SIN:
3902                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3903                         break;
3904                 case OP_COS:
3905                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3906                         break;
3907                 case OP_ABS: {
3908                         static guint64 d = 0x7fffffffffffffffUL;
3909
3910                         g_assert (ins->sreg1 == ins->dreg);
3911
3912                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3913                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3914                         break;
3915                 }
3916                 case OP_SQRT:
3917                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3918                         break;
3919                 case OP_IMIN:
3920                         g_assert (cfg->opt & MONO_OPT_CMOV);
3921                         g_assert (ins->dreg == ins->sreg1);
3922                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3923                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3924                         break;
3925                 case OP_IMIN_UN:
3926                         g_assert (cfg->opt & MONO_OPT_CMOV);
3927                         g_assert (ins->dreg == ins->sreg1);
3928                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3929                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3930                         break;
3931                 case OP_IMAX:
3932                         g_assert (cfg->opt & MONO_OPT_CMOV);
3933                         g_assert (ins->dreg == ins->sreg1);
3934                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3935                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3936                         break;
3937                 case OP_IMAX_UN:
3938                         g_assert (cfg->opt & MONO_OPT_CMOV);
3939                         g_assert (ins->dreg == ins->sreg1);
3940                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3941                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3942                         break;
3943                 case OP_LMIN:
3944                         g_assert (cfg->opt & MONO_OPT_CMOV);
3945                         g_assert (ins->dreg == ins->sreg1);
3946                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3947                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3948                         break;
3949                 case OP_LMIN_UN:
3950                         g_assert (cfg->opt & MONO_OPT_CMOV);
3951                         g_assert (ins->dreg == ins->sreg1);
3952                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3953                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3954                         break;
3955                 case OP_LMAX:
3956                         g_assert (cfg->opt & MONO_OPT_CMOV);
3957                         g_assert (ins->dreg == ins->sreg1);
3958                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3959                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3960                         break;
3961                 case OP_LMAX_UN:
3962                         g_assert (cfg->opt & MONO_OPT_CMOV);
3963                         g_assert (ins->dreg == ins->sreg1);
3964                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3965                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3966                         break;
3967                 case OP_X86_FPOP:
3968                         break;
3969                 case OP_FCOMPARE:
3970                         /*
3971                          * The two arguments are swapped because the fbranch instructions
3972                          * depend on this for the non-sse case to work.
3973                          */
3974                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3975                         break;
3976                 case OP_FCEQ: {
3977                         /* zeroing the register at the start results in
3978                          * shorter and faster code (we can also remove the widening op)
3979                          */
3980                         guchar *unordered_check;
3981                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3982                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3983                         unordered_check = code;
3984                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3985                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3986                         amd64_patch (unordered_check, code);
3987                         break;
3988                 }
3989                 case OP_FCLT:
3990                 case OP_FCLT_UN:
3991                         /* zeroing the register at the start results in
3992                          * shorter and faster code (we can also remove the widening op)
3993                          */
3994                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3995                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3996                         if (ins->opcode == OP_FCLT_UN) {
3997                                 guchar *unordered_check = code;
3998                                 guchar *jump_to_end;
3999                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4000                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4001                                 jump_to_end = code;
4002                                 x86_jump8 (code, 0);
4003                                 amd64_patch (unordered_check, code);
4004                                 amd64_inc_reg (code, ins->dreg);
4005                                 amd64_patch (jump_to_end, code);
4006                         } else {
4007                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4008                         }
4009                         break;
4010                 case OP_FCGT:
4011                 case OP_FCGT_UN: {
4012                         /* zeroing the register at the start results in
4013                          * shorter and faster code (we can also remove the widening op)
4014                          */
4015                         guchar *unordered_check;
4016                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4017                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4018                         if (ins->opcode == OP_FCGT) {
4019                                 unordered_check = code;
4020                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4021                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4022                                 amd64_patch (unordered_check, code);
4023                         } else {
4024                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4025                         }
4026                         break;
4027                 }
4028                 case OP_FCLT_MEMBASE:
4029                 case OP_FCGT_MEMBASE:
4030                 case OP_FCLT_UN_MEMBASE:
4031                 case OP_FCGT_UN_MEMBASE:
4032                 case OP_FCEQ_MEMBASE: {
4033                         guchar *unordered_check, *jump_to_end;
4034                         int x86_cond;
4035
4036                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4037                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4038
4039                         switch (ins->opcode) {
4040                         case OP_FCEQ_MEMBASE:
4041                                 x86_cond = X86_CC_EQ;
4042                                 break;
4043                         case OP_FCLT_MEMBASE:
4044                         case OP_FCLT_UN_MEMBASE:
4045                                 x86_cond = X86_CC_LT;
4046                                 break;
4047                         case OP_FCGT_MEMBASE:
4048                         case OP_FCGT_UN_MEMBASE:
4049                                 x86_cond = X86_CC_GT;
4050                                 break;
4051                         default:
4052                                 g_assert_not_reached ();
4053                         }
4054
4055                         unordered_check = code;
4056                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4057                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4058
4059                         switch (ins->opcode) {
4060                         case OP_FCEQ_MEMBASE:
4061                         case OP_FCLT_MEMBASE:
4062                         case OP_FCGT_MEMBASE:
4063                                 amd64_patch (unordered_check, code);
4064                                 break;
4065                         case OP_FCLT_UN_MEMBASE:
4066                         case OP_FCGT_UN_MEMBASE:
4067                                 jump_to_end = code;
4068                                 x86_jump8 (code, 0);
4069                                 amd64_patch (unordered_check, code);
4070                                 amd64_inc_reg (code, ins->dreg);
4071                                 amd64_patch (jump_to_end, code);
4072                                 break;
4073                         default:
4074                                 break;
4075                         }
4076                         break;
4077                 }
4078                 case OP_FBEQ: {
4079                         guchar *jump = code;
4080                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4081                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4082                         amd64_patch (jump, code);
4083                         break;
4084                 }
4085                 case OP_FBNE_UN:
4086                         /* Branch if C013 != 100 */
4087                         /* branch if !ZF or (PF|CF) */
4088                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4089                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4090                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4091                         break;
4092                 case OP_FBLT:
4093                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4094                         break;
4095                 case OP_FBLT_UN:
4096                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4097                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4098                         break;
4099                 case OP_FBGT:
4100                 case OP_FBGT_UN:
4101                         if (ins->opcode == OP_FBGT) {
4102                                 guchar *br1;
4103
4104                                 /* skip branch if C1=1 */
4105                                 br1 = code;
4106                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4107                                 /* branch if (C0 | C3) = 1 */
4108                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4109                                 amd64_patch (br1, code);
4110                                 break;
4111                         } else {
4112                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4113                         }
4114                         break;
4115                 case OP_FBGE: {
4116                         /* Branch if C013 == 100 or 001 */
4117                         guchar *br1;
4118
4119                         /* skip branch if C1=1 */
4120                         br1 = code;
4121                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4122                         /* branch if (C0 | C3) = 1 */
4123                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4124                         amd64_patch (br1, code);
4125                         break;
4126                 }
4127                 case OP_FBGE_UN:
4128                         /* Branch if C013 == 000 */
4129                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4130                         break;
4131                 case OP_FBLE: {
4132                         /* Branch if C013=000 or 100 */
4133                         guchar *br1;
4134
4135                         /* skip branch if C1=1 */
4136                         br1 = code;
4137                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4138                         /* branch if C0=0 */
4139                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4140                         amd64_patch (br1, code);
4141                         break;
4142                 }
4143                 case OP_FBLE_UN:
4144                         /* Branch if C013 != 001 */
4145                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4146                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4147                         break;
4148                 case OP_CKFINITE:
4149                         /* Transfer value to the fp stack */
4150                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4151                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4152                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4153
4154                         amd64_push_reg (code, AMD64_RAX);
4155                         amd64_fxam (code);
4156                         amd64_fnstsw (code);
4157                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4158                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4159                         amd64_pop_reg (code, AMD64_RAX);
4160                         amd64_fstp (code, 0);
4161                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4162                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4163                         break;
4164                 case OP_TLS_GET: {
4165                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4166                         break;
4167                 }
4168                 case OP_MEMORY_BARRIER: {
4169                         /* Not needed on amd64 */
4170                         break;
4171                 }
4172                 case OP_ATOMIC_ADD_I4:
4173                 case OP_ATOMIC_ADD_I8: {
4174                         int dreg = ins->dreg;
4175                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4176
4177                         if (dreg == ins->inst_basereg)
4178                                 dreg = AMD64_R11;
4179
4180                         if (dreg != ins->sreg2)
4181                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4182
4183                         x86_prefix (code, X86_LOCK_PREFIX);
4184                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4185
4186                         if (dreg != ins->dreg)
4187                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4188
4189                         break;
4190                 }
4191                 case OP_ATOMIC_ADD_NEW_I4:
4192                 case OP_ATOMIC_ADD_NEW_I8: {
4193                         int dreg = ins->dreg;
4194                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4195
4196                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4197                                 dreg = AMD64_R11;
4198
4199                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4200                         amd64_prefix (code, X86_LOCK_PREFIX);
4201                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4202                         /* dreg contains the old value, add with sreg2 value */
4203                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4204
4205                         if (ins->dreg != dreg)
4206                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4207
4208                         break;
4209                 }
4210                 case OP_ATOMIC_EXCHANGE_I4:
4211                 case OP_ATOMIC_EXCHANGE_I8: {
4212                         guchar *br[2];
4213                         int sreg2 = ins->sreg2;
4214                         int breg = ins->inst_basereg;
4215                         guint32 size;
4216                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4217
4218                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4219                                 size = 8;
4220                         else
4221                                 size = 4;
4222
4223                         /*
4224                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4225                          * an explanation of how this works.
4226                          */
4227
4228                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4229                          * hack to overcome limits in x86 reg allocator
4230                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4231                          */
4232                         g_assert (ins->dreg == AMD64_RAX);
4233
4234                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4235                                 /* Highly unlikely, but possible */
4236                                 need_push = TRUE;
4237
4238                         /* The pushes invalidate rsp */
4239                         if ((breg == AMD64_RAX) || need_push) {
4240                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4241                                 breg = AMD64_R11;
4242                         }
4243
4244                         /* We need the EAX reg for the comparand */
4245                         if (ins->sreg2 == AMD64_RAX) {
4246                                 if (breg != AMD64_R11) {
4247                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4248                                         sreg2 = AMD64_R11;
4249                                 } else {
4250                                         g_assert (need_push);
4251                                         amd64_push_reg (code, AMD64_RDX);
4252                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4253                                         sreg2 = AMD64_RDX;
4254                                         rdx_pushed = TRUE;
4255                                 }
4256                         }
4257
4258                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4259
4260                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4261                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4262                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4263                         amd64_patch (br [1], br [0]);
4264
4265                         if (rdx_pushed)
4266                                 amd64_pop_reg (code, AMD64_RDX);
4267
4268                         break;
4269                 }
4270                 case OP_ATOMIC_CAS_I4:
4271                 case OP_ATOMIC_CAS_I8: {
4272                         guint32 size;
4273
4274                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4275                                 size = 8;
4276                         else
4277                                 size = 4;
4278
4279                         /*
4280                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4281                          * an explanation of how this works.
4282                          */
4283                         g_assert (ins->sreg3 == AMD64_RAX);
4284                         g_assert (ins->sreg1 != AMD64_RAX);
4285                         g_assert (ins->sreg1 != ins->sreg2);
4286
4287                         amd64_prefix (code, X86_LOCK_PREFIX);
4288                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4289
4290                         if (ins->dreg != AMD64_RAX)
4291                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4292                         break;
4293                 }
4294                 case OP_LIVERANGE_START: {
4295                         if (cfg->verbose_level > 1)
4296                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4297                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4298                         break;
4299                 }
4300                 case OP_LIVERANGE_END: {
4301                         if (cfg->verbose_level > 1)
4302                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4303                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4304                         break;
4305                 }
4306                 default:
4307                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4308                         g_assert_not_reached ();
4309                 }
4310
4311                 if ((code - cfg->native_code - offset) > max_len) {
4312                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4313                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4314                         g_assert_not_reached ();
4315                 }
4316
4317                 cpos += max_len;
4318
4319                 last_ins = ins;
4320                 last_offset = offset;
4321         }
4322
4323         cfg->code_len = code - cfg->native_code;
4324 }
4325
4326 #endif /* DISABLE_JIT */
4327
4328 void
4329 mono_arch_register_lowlevel_calls (void)
4330 {
4331         /* The signature doesn't matter */
4332         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4333 }
4334
4335 void
4336 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4337 {
4338         MonoJumpInfo *patch_info;
4339         gboolean compile_aot = !run_cctors;
4340
4341         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4342                 unsigned char *ip = patch_info->ip.i + code;
4343                 unsigned char *target;
4344
4345                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4346
4347                 if (compile_aot) {
4348                         switch (patch_info->type) {
4349                         case MONO_PATCH_INFO_BB:
4350                         case MONO_PATCH_INFO_LABEL:
4351                                 break;
4352                         default:
4353                                 /* No need to patch these */
4354                                 continue;
4355                         }
4356                 }
4357
4358                 switch (patch_info->type) {
4359                 case MONO_PATCH_INFO_NONE:
4360                         continue;
4361                 case MONO_PATCH_INFO_METHOD_REL:
4362                 case MONO_PATCH_INFO_R8:
4363                 case MONO_PATCH_INFO_R4:
4364                         g_assert_not_reached ();
4365                         continue;
4366                 case MONO_PATCH_INFO_BB:
4367                         break;
4368                 default:
4369                         break;
4370                 }
4371
4372                 /*
4373                  * Debug code to help track down problems where the target of a near call is
4374                  * is not valid.
4375                  */
4376                 if (amd64_is_near_call (ip)) {
4377                         gint64 disp = (guint8*)target - (guint8*)ip;
4378
4379                         if (!amd64_is_imm32 (disp)) {
4380                                 printf ("TYPE: %d\n", patch_info->type);
4381                                 switch (patch_info->type) {
4382                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4383                                         printf ("V: %s\n", patch_info->data.name);
4384                                         break;
4385                                 case MONO_PATCH_INFO_METHOD_JUMP:
4386                                 case MONO_PATCH_INFO_METHOD:
4387                                         printf ("V: %s\n", patch_info->data.method->name);
4388                                         break;
4389                                 default:
4390                                         break;
4391                                 }
4392                         }
4393                 }
4394
4395                 amd64_patch (ip, (gpointer)target);
4396         }
4397 }
4398
4399 static int
4400 get_max_epilog_size (MonoCompile *cfg)
4401 {
4402         int max_epilog_size = 16;
4403
4404         if (cfg->method->save_lmf)
4405                 max_epilog_size += 256;
4406
4407         if (mono_jit_trace_calls != NULL)
4408                 max_epilog_size += 50;
4409
4410         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4411                 max_epilog_size += 50;
4412
4413         max_epilog_size += (AMD64_NREG * 2);
4414
4415         return max_epilog_size;
4416 }
4417
4418 /*
4419  * This macro is used for testing whenever the unwinder works correctly at every point
4420  * where an async exception can happen.
4421  */
4422 /* This will generate a SIGSEGV at the given point in the code */
4423 #define async_exc_point(code) do { \
4424     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4425          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4426              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4427          cfg->arch.async_point_count ++; \
4428     } \
4429 } while (0)
4430
4431 guint8 *
4432 mono_arch_emit_prolog (MonoCompile *cfg)
4433 {
4434         MonoMethod *method = cfg->method;
4435         MonoBasicBlock *bb;
4436         MonoMethodSignature *sig;
4437         MonoInst *ins;
4438         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4439         guint8 *code;
4440         CallInfo *cinfo;
4441         gint32 lmf_offset = cfg->arch.lmf_offset;
4442         gboolean args_clobbered = FALSE;
4443         gboolean trace = FALSE;
4444
4445         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4446
4447         code = cfg->native_code = g_malloc (cfg->code_size);
4448
4449         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4450                 trace = TRUE;
4451
4452         /* Amount of stack space allocated by register saving code */
4453         pos = 0;
4454
4455         /* Offset between RSP and the CFA */
4456         cfa_offset = 0;
4457
4458         /*
4459          * The prolog consists of the following parts:
4460          * FP present:
4461          * - push rbp, mov rbp, rsp
4462          * - save callee saved regs using pushes
4463          * - allocate frame
4464          * - save rgctx if needed
4465          * - save lmf if needed
4466          * FP not present:
4467          * - allocate frame
4468          * - save rgctx if needed
4469          * - save lmf if needed
4470          * - save callee saved regs using moves
4471          */
4472
4473         // CFA = sp + 8
4474         cfa_offset = 8;
4475         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4476         // IP saved at CFA - 8
4477         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4478         async_exc_point (code);
4479
4480         if (!cfg->arch.omit_fp) {
4481                 amd64_push_reg (code, AMD64_RBP);
4482                 cfa_offset += 8;
4483                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4484                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4485                 async_exc_point (code);
4486 #ifdef PLATFORM_WIN32
4487                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4488 #endif
4489
4490                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4491                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4492                 async_exc_point (code);
4493 #ifdef PLATFORM_WIN32
4494                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4495 #endif
4496         }
4497
4498         /* Save callee saved registers */
4499         if (!cfg->arch.omit_fp && !method->save_lmf) {
4500                 int offset = cfa_offset;
4501
4502                 for (i = 0; i < AMD64_NREG; ++i)
4503                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4504                                 amd64_push_reg (code, i);
4505                                 pos += sizeof (gpointer);
4506                                 offset += 8;
4507                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4508                                 async_exc_point (code);
4509                         }
4510         }
4511
4512         if (cfg->arch.omit_fp) {
4513                 /*
4514                  * On enter, the stack is misaligned by the the pushing of the return
4515                  * address. It is either made aligned by the pushing of %rbp, or by
4516                  * this.
4517                  */
4518                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4519                 if ((alloc_size % 16) == 0)
4520                         alloc_size += 8;
4521         } else {
4522                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4523
4524                 alloc_size -= pos;
4525         }
4526
4527         cfg->arch.stack_alloc_size = alloc_size;
4528
4529         /* Allocate stack frame */
4530         if (alloc_size) {
4531                 /* See mono_emit_stack_alloc */
4532 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4533                 guint32 remaining_size = alloc_size;
4534                 while (remaining_size >= 0x1000) {
4535                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4536                         if (cfg->arch.omit_fp) {
4537                                 cfa_offset += 0x1000;
4538                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4539                         }
4540                         async_exc_point (code);
4541 #ifdef PLATFORM_WIN32
4542                         if (cfg->arch.omit_fp)
4543                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4544 #endif
4545
4546                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4547                         remaining_size -= 0x1000;
4548                 }
4549                 if (remaining_size) {
4550                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4551                         if (cfg->arch.omit_fp) {
4552                                 cfa_offset += remaining_size;
4553                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4554                                 async_exc_point (code);
4555                         }
4556 #ifdef PLATFORM_WIN32
4557                         if (cfg->arch.omit_fp)
4558                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4559 #endif
4560                 }
4561 #else
4562                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4563                 if (cfg->arch.omit_fp) {
4564                         cfa_offset += alloc_size;
4565                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4566                         async_exc_point (code);
4567                 }
4568 #endif
4569         }
4570
4571         /* Stack alignment check */
4572 #if 0
4573         {
4574                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4575                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4576                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4577                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4578                 amd64_breakpoint (code);
4579         }
4580 #endif
4581
4582         /* Save LMF */
4583         if (method->save_lmf) {
4584                 /*
4585                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4586                  */
4587                 /* sp is saved right before calls */
4588                 /* Skip method (only needed for trampoline LMF frames) */
4589                 /* Save callee saved regs */
4590                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4591                         int offset;
4592
4593                         switch (i) {
4594                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4595                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4596                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4597                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4598                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4599                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4600 #ifdef PLATFORM_WIN32
4601                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4602                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4603 #endif
4604                         default:
4605                                 offset = -1;
4606                                 break;
4607                         }
4608
4609                         if (offset != -1) {
4610                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4611                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4612                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4613                         }
4614                 }
4615         }
4616
4617         /* Save callee saved registers */
4618         if (cfg->arch.omit_fp && !method->save_lmf) {
4619                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4620
4621                 /* Save caller saved registers after sp is adjusted */
4622                 /* The registers are saved at the bottom of the frame */
4623                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4624                 for (i = 0; i < AMD64_NREG; ++i)
4625                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4626                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4627                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4628                                 save_area_offset += 8;
4629                                 async_exc_point (code);
4630                         }
4631         }
4632
4633         /* store runtime generic context */
4634         if (cfg->rgctx_var) {
4635                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4636                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4637
4638                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4639         }
4640
4641         /* compute max_offset in order to use short forward jumps */
4642         max_offset = 0;
4643         max_epilog_size = get_max_epilog_size (cfg);
4644         if (cfg->opt & MONO_OPT_BRANCH) {
4645                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4646                         MonoInst *ins;
4647                         bb->max_offset = max_offset;
4648
4649                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4650                                 max_offset += 6;
4651                         /* max alignment for loops */
4652                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4653                                 max_offset += LOOP_ALIGNMENT;
4654
4655                         MONO_BB_FOR_EACH_INS (bb, ins) {
4656                                 if (ins->opcode == OP_LABEL)
4657                                         ins->inst_c1 = max_offset;
4658
4659                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4660                         }
4661
4662                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4663                                 /* The tracing code can be quite large */
4664                                 max_offset += max_epilog_size;
4665                 }
4666         }
4667
4668         sig = mono_method_signature (method);
4669         pos = 0;
4670
4671         cinfo = cfg->arch.cinfo;
4672
4673         if (sig->ret->type != MONO_TYPE_VOID) {
4674                 /* Save volatile arguments to the stack */
4675                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4676                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4677         }
4678
4679         /* Keep this in sync with emit_load_volatile_arguments */
4680         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4681                 ArgInfo *ainfo = cinfo->args + i;
4682                 gint32 stack_offset;
4683                 MonoType *arg_type;
4684
4685                 ins = cfg->args [i];
4686
4687                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4688                         /* Unused arguments */
4689                         continue;
4690
4691                 if (sig->hasthis && (i == 0))
4692                         arg_type = &mono_defaults.object_class->byval_arg;
4693                 else
4694                         arg_type = sig->params [i - sig->hasthis];
4695
4696                 stack_offset = ainfo->offset + ARGS_OFFSET;
4697
4698                 if (cfg->globalra) {
4699                         /* All the other moves are done by the register allocator */
4700                         switch (ainfo->storage) {
4701                         case ArgInFloatSSEReg:
4702                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4703                                 break;
4704                         case ArgValuetypeInReg:
4705                                 for (quad = 0; quad < 2; quad ++) {
4706                                         switch (ainfo->pair_storage [quad]) {
4707                                         case ArgInIReg:
4708                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4709                                                 break;
4710                                         case ArgInFloatSSEReg:
4711                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4712                                                 break;
4713                                         case ArgInDoubleSSEReg:
4714                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4715                                                 break;
4716                                         case ArgNone:
4717                                                 break;
4718                                         default:
4719                                                 g_assert_not_reached ();
4720                                         }
4721                                 }
4722                                 break;
4723                         default:
4724                                 break;
4725                         }
4726
4727                         continue;
4728                 }
4729
4730                 /* Save volatile arguments to the stack */
4731                 if (ins->opcode != OP_REGVAR) {
4732                         switch (ainfo->storage) {
4733                         case ArgInIReg: {
4734                                 guint32 size = 8;
4735
4736                                 /* FIXME: I1 etc */
4737                                 /*
4738                                 if (stack_offset & 0x1)
4739                                         size = 1;
4740                                 else if (stack_offset & 0x2)
4741                                         size = 2;
4742                                 else if (stack_offset & 0x4)
4743                                         size = 4;
4744                                 else
4745                                         size = 8;
4746                                 */
4747                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4748                                 break;
4749                         }
4750                         case ArgInFloatSSEReg:
4751                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4752                                 break;
4753                         case ArgInDoubleSSEReg:
4754                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4755                                 break;
4756                         case ArgValuetypeInReg:
4757                                 for (quad = 0; quad < 2; quad ++) {
4758                                         switch (ainfo->pair_storage [quad]) {
4759                                         case ArgInIReg:
4760                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4761                                                 break;
4762                                         case ArgInFloatSSEReg:
4763                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4764                                                 break;
4765                                         case ArgInDoubleSSEReg:
4766                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4767                                                 break;
4768                                         case ArgNone:
4769                                                 break;
4770                                         default:
4771                                                 g_assert_not_reached ();
4772                                         }
4773                                 }
4774                                 break;
4775                         case ArgValuetypeAddrInIReg:
4776                                 if (ainfo->pair_storage [0] == ArgInIReg)
4777                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4778                                 break;
4779                         default:
4780                                 break;
4781                         }
4782                 } else {
4783                         /* Argument allocated to (non-volatile) register */
4784                         switch (ainfo->storage) {
4785                         case ArgInIReg:
4786                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4787                                 break;
4788                         case ArgOnStack:
4789                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4790                                 break;
4791                         default:
4792                                 g_assert_not_reached ();
4793                         }
4794                 }
4795         }
4796
4797         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4798         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4799                 guint64 domain = (guint64)cfg->domain;
4800
4801                 args_clobbered = TRUE;
4802
4803                 /*
4804                  * The call might clobber argument registers, but they are already
4805                  * saved to the stack/global regs.
4806                  */
4807                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4808                         guint8 *buf, *no_domain_branch;
4809
4810                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4811                         if ((domain >> 32) == 0)
4812                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4813                         else
4814                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4815                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4816                         no_domain_branch = code;
4817                         x86_branch8 (code, X86_CC_NE, 0, 0);
4818                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4819                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4820                         buf = code;
4821                         x86_branch8 (code, X86_CC_NE, 0, 0);
4822                         amd64_patch (no_domain_branch, code);
4823                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4824                                           (gpointer)"mono_jit_thread_attach", TRUE);
4825                         amd64_patch (buf, code);
4826 #ifdef PLATFORM_WIN32
4827                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4828                         /* FIXME: Add a separate key for LMF to avoid this */
4829                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4830 #endif
4831                 } else {
4832                         g_assert (!cfg->compile_aot);
4833                         if ((domain >> 32) == 0)
4834                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4835                         else
4836                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4837                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4838                                           (gpointer)"mono_jit_thread_attach", TRUE);
4839                 }
4840         }
4841
4842         if (method->save_lmf) {
4843                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4844                         /*
4845                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4846                          * through the mono_lmf_addr TLS variable.
4847                          */
4848                         /* %rax = previous_lmf */
4849                         x86_prefix (code, X86_FS_PREFIX);
4850                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4851
4852                         /* Save previous_lmf */
4853                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4854                         /* Set new lmf */
4855                         if (lmf_offset == 0) {
4856                                 x86_prefix (code, X86_FS_PREFIX);
4857                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4858                         } else {
4859                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4860                                 x86_prefix (code, X86_FS_PREFIX);
4861                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4862                         }
4863                 } else {
4864                         if (lmf_addr_tls_offset != -1) {
4865                                 /* Load lmf quicky using the FS register */
4866                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4867 #ifdef PLATFORM_WIN32
4868                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4869                                 /* FIXME: Add a separate key for LMF to avoid this */
4870                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4871 #endif
4872                         }
4873                         else {
4874                                 /*
4875                                  * The call might clobber argument registers, but they are already
4876                                  * saved to the stack/global regs.
4877                                  */
4878                                 args_clobbered = TRUE;
4879                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4880                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4881                         }
4882
4883                         /* Save lmf_addr */
4884                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4885                         /* Save previous_lmf */
4886                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4887                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4888                         /* Set new lmf */
4889                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4890                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4891                 }
4892         }
4893
4894         if (trace) {
4895                 args_clobbered = TRUE;
4896                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4897         }
4898
4899         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4900                 args_clobbered = TRUE;
4901
4902         /*
4903          * Optimize the common case of the first bblock making a call with the same
4904          * arguments as the method. This works because the arguments are still in their
4905          * original argument registers.
4906          * FIXME: Generalize this
4907          */
4908         if (!args_clobbered) {
4909                 MonoBasicBlock *first_bb = cfg->bb_entry;
4910                 MonoInst *next;
4911
4912                 next = mono_bb_first_ins (first_bb);
4913                 if (!next && first_bb->next_bb) {
4914                         first_bb = first_bb->next_bb;
4915                         next = mono_bb_first_ins (first_bb);
4916                 }
4917
4918                 if (first_bb->in_count > 1)
4919                         next = NULL;
4920
4921                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4922                         ArgInfo *ainfo = cinfo->args + i;
4923                         gboolean match = FALSE;
4924
4925                         ins = cfg->args [i];
4926                         if (ins->opcode != OP_REGVAR) {
4927                                 switch (ainfo->storage) {
4928                                 case ArgInIReg: {
4929                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4930                                                 if (next->dreg == ainfo->reg) {
4931                                                         NULLIFY_INS (next);
4932                                                         match = TRUE;
4933                                                 } else {
4934                                                         next->opcode = OP_MOVE;
4935                                                         next->sreg1 = ainfo->reg;
4936                                                         /* Only continue if the instruction doesn't change argument regs */
4937                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4938                                                                 match = TRUE;
4939                                                 }
4940                                         }
4941                                         break;
4942                                 }
4943                                 default:
4944                                         break;
4945                                 }
4946                         } else {
4947                                 /* Argument allocated to (non-volatile) register */
4948                                 switch (ainfo->storage) {
4949                                 case ArgInIReg:
4950                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4951                                                 NULLIFY_INS (next);
4952                                                 match = TRUE;
4953                                         }
4954                                         break;
4955                                 default:
4956                                         break;
4957                                 }
4958                         }
4959
4960                         if (match) {
4961                                 next = next->next;
4962                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4963                                 if (!next)
4964                                         break;
4965                         }
4966                 }
4967         }
4968
4969         cfg->code_len = code - cfg->native_code;
4970
4971         g_assert (cfg->code_len < cfg->code_size);
4972
4973         return code;
4974 }
4975
4976 void
4977 mono_arch_emit_epilog (MonoCompile *cfg)
4978 {
4979         MonoMethod *method = cfg->method;
4980         int quad, pos, i;
4981         guint8 *code;
4982         int max_epilog_size;
4983         CallInfo *cinfo;
4984         gint32 lmf_offset = cfg->arch.lmf_offset;
4985
4986         max_epilog_size = get_max_epilog_size (cfg);
4987
4988         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4989                 cfg->code_size *= 2;
4990                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4991                 mono_jit_stats.code_reallocs++;
4992         }
4993
4994         code = cfg->native_code + cfg->code_len;
4995
4996         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4997                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4998
4999         /* the code restoring the registers must be kept in sync with OP_JMP */
5000         pos = 0;
5001
5002         if (method->save_lmf) {
5003                 /* check if we need to restore protection of the stack after a stack overflow */
5004                 if (mono_get_jit_tls_offset () != -1) {
5005                         guint8 *patch;
5006                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5007                         /* we load the value in a separate instruction: this mechanism may be
5008                          * used later as a safer way to do thread interruption
5009                          */
5010                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5011                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5012                         patch = code;
5013                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5014                         /* note that the call trampoline will preserve eax/edx */
5015                         x86_call_reg (code, X86_ECX);
5016                         x86_patch (patch, code);
5017                 } else {
5018                         /* FIXME: maybe save the jit tls in the prolog */
5019                 }
5020                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5021                         /*
5022                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5023                          * through the mono_lmf_addr TLS variable.
5024                          */
5025                         /* reg = previous_lmf */
5026                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5027                         x86_prefix (code, X86_FS_PREFIX);
5028                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5029                 } else {
5030                         /* Restore previous lmf */
5031                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5032                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5033                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5034                 }
5035
5036                 /* Restore caller saved regs */
5037                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5038                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5039                 }
5040                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5041                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5042                 }
5043                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5044                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5045                 }
5046                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5047                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5048                 }
5049                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5050                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5051                 }
5052                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5053                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5054                 }
5055 #ifdef PLATFORM_WIN32
5056                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5057                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5058                 }
5059                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5060                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5061                 }
5062 #endif
5063         } else {
5064
5065                 if (cfg->arch.omit_fp) {
5066                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5067
5068                         for (i = 0; i < AMD64_NREG; ++i)
5069                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5070                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5071                                         save_area_offset += 8;
5072                                 }
5073                 }
5074                 else {
5075                         for (i = 0; i < AMD64_NREG; ++i)
5076                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5077                                         pos -= sizeof (gpointer);
5078
5079                         if (pos) {
5080                                 if (pos == - sizeof (gpointer)) {
5081                                         /* Only one register, so avoid lea */
5082                                         for (i = AMD64_NREG - 1; i > 0; --i)
5083                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5084                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5085                                                 }
5086                                 }
5087                                 else {
5088                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5089
5090                                         /* Pop registers in reverse order */
5091                                         for (i = AMD64_NREG - 1; i > 0; --i)
5092                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5093                                                         amd64_pop_reg (code, i);
5094                                                 }
5095                                 }
5096                         }
5097                 }
5098         }
5099
5100         /* Load returned vtypes into registers if needed */
5101         cinfo = cfg->arch.cinfo;
5102         if (cinfo->ret.storage == ArgValuetypeInReg) {
5103                 ArgInfo *ainfo = &cinfo->ret;
5104                 MonoInst *inst = cfg->ret;
5105
5106                 for (quad = 0; quad < 2; quad ++) {
5107                         switch (ainfo->pair_storage [quad]) {
5108                         case ArgInIReg:
5109                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5110                                 break;
5111                         case ArgInFloatSSEReg:
5112                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5113                                 break;
5114                         case ArgInDoubleSSEReg:
5115                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5116                                 break;
5117                         case ArgNone:
5118                                 break;
5119                         default:
5120                                 g_assert_not_reached ();
5121                         }
5122                 }
5123         }
5124
5125         if (cfg->arch.omit_fp) {
5126                 if (cfg->arch.stack_alloc_size)
5127                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5128         } else {
5129                 amd64_leave (code);
5130         }
5131         async_exc_point (code);
5132         amd64_ret (code);
5133
5134         cfg->code_len = code - cfg->native_code;
5135
5136         g_assert (cfg->code_len < cfg->code_size);
5137 }
5138
5139 void
5140 mono_arch_emit_exceptions (MonoCompile *cfg)
5141 {
5142         MonoJumpInfo *patch_info;
5143         int nthrows, i;
5144         guint8 *code;
5145         MonoClass *exc_classes [16];
5146         guint8 *exc_throw_start [16], *exc_throw_end [16];
5147         guint32 code_size = 0;
5148
5149         /* Compute needed space */
5150         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5151                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5152                         code_size += 40;
5153                 if (patch_info->type == MONO_PATCH_INFO_R8)
5154                         code_size += 8 + 15; /* sizeof (double) + alignment */
5155                 if (patch_info->type == MONO_PATCH_INFO_R4)
5156                         code_size += 4 + 15; /* sizeof (float) + alignment */
5157         }
5158
5159         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5160                 cfg->code_size *= 2;
5161                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5162                 mono_jit_stats.code_reallocs++;
5163         }
5164
5165         code = cfg->native_code + cfg->code_len;
5166
5167         /* add code to raise exceptions */
5168         nthrows = 0;
5169         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5170                 switch (patch_info->type) {
5171                 case MONO_PATCH_INFO_EXC: {
5172                         MonoClass *exc_class;
5173                         guint8 *buf, *buf2;
5174                         guint32 throw_ip;
5175
5176                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5177
5178                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5179                         g_assert (exc_class);
5180                         throw_ip = patch_info->ip.i;
5181
5182                         //x86_breakpoint (code);
5183                         /* Find a throw sequence for the same exception class */
5184                         for (i = 0; i < nthrows; ++i)
5185                                 if (exc_classes [i] == exc_class)
5186                                         break;
5187                         if (i < nthrows) {
5188                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5189                                 x86_jump_code (code, exc_throw_start [i]);
5190                                 patch_info->type = MONO_PATCH_INFO_NONE;
5191                         }
5192                         else {
5193                                 buf = code;
5194                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5195                                 buf2 = code;
5196
5197                                 if (nthrows < 16) {
5198                                         exc_classes [nthrows] = exc_class;
5199                                         exc_throw_start [nthrows] = code;
5200                                 }
5201                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5202
5203                                 patch_info->type = MONO_PATCH_INFO_NONE;
5204
5205                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5206
5207                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5208                                 while (buf < buf2)
5209                                         x86_nop (buf);
5210
5211                                 if (nthrows < 16) {
5212                                         exc_throw_end [nthrows] = code;
5213                                         nthrows ++;
5214                                 }
5215                         }
5216                         break;
5217                 }
5218                 default:
5219                         /* do nothing */
5220                         break;
5221                 }
5222         }
5223
5224         /* Handle relocations with RIP relative addressing */
5225         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5226                 gboolean remove = FALSE;
5227
5228                 switch (patch_info->type) {
5229                 case MONO_PATCH_INFO_R8:
5230                 case MONO_PATCH_INFO_R4: {
5231                         guint8 *pos;
5232
5233                         /* The SSE opcodes require a 16 byte alignment */
5234                         code = (guint8*)ALIGN_TO (code, 16);
5235
5236                         pos = cfg->native_code + patch_info->ip.i;
5237
5238                         if (IS_REX (pos [1]))
5239                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5240                         else
5241                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5242
5243                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5244                                 *(double*)code = *(double*)patch_info->data.target;
5245                                 code += sizeof (double);
5246                         } else {
5247                                 *(float*)code = *(float*)patch_info->data.target;
5248                                 code += sizeof (float);
5249                         }
5250
5251                         remove = TRUE;
5252                         break;
5253                 }
5254                 default:
5255                         break;
5256                 }
5257
5258                 if (remove) {
5259                         if (patch_info == cfg->patch_info)
5260                                 cfg->patch_info = patch_info->next;
5261                         else {
5262                                 MonoJumpInfo *tmp;
5263
5264                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5265                                         ;
5266                                 tmp->next = patch_info->next;
5267                         }
5268                 }
5269         }
5270
5271         cfg->code_len = code - cfg->native_code;
5272
5273         g_assert (cfg->code_len < cfg->code_size);
5274
5275 }
5276
5277 void*
5278 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5279 {
5280         guchar *code = p;
5281         CallInfo *cinfo = NULL;
5282         MonoMethodSignature *sig;
5283         MonoInst *inst;
5284         int i, n, stack_area = 0;
5285
5286         /* Keep this in sync with mono_arch_get_argument_info */
5287
5288         if (enable_arguments) {
5289                 /* Allocate a new area on the stack and save arguments there */
5290                 sig = mono_method_signature (cfg->method);
5291
5292                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5293
5294                 n = sig->param_count + sig->hasthis;
5295
5296                 stack_area = ALIGN_TO (n * 8, 16);
5297
5298                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5299
5300                 for (i = 0; i < n; ++i) {
5301                         inst = cfg->args [i];
5302
5303                         if (inst->opcode == OP_REGVAR)
5304                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5305                         else {
5306                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5307                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5308                         }
5309                 }
5310         }
5311
5312         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5313         amd64_set_reg_template (code, AMD64_ARG_REG1);
5314         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5315         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5316
5317         if (enable_arguments)
5318                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5319
5320         return code;
5321 }
5322
5323 enum {
5324         SAVE_NONE,
5325         SAVE_STRUCT,
5326         SAVE_EAX,
5327         SAVE_EAX_EDX,
5328         SAVE_XMM
5329 };
5330
5331 void*
5332 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5333 {
5334         guchar *code = p;
5335         int save_mode = SAVE_NONE;
5336         MonoMethod *method = cfg->method;
5337         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5338
5339         switch (rtype) {
5340         case MONO_TYPE_VOID:
5341                 /* special case string .ctor icall */
5342                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5343                         save_mode = SAVE_EAX;
5344                 else
5345                         save_mode = SAVE_NONE;
5346                 break;
5347         case MONO_TYPE_I8:
5348         case MONO_TYPE_U8:
5349                 save_mode = SAVE_EAX;
5350                 break;
5351         case MONO_TYPE_R4:
5352         case MONO_TYPE_R8:
5353                 save_mode = SAVE_XMM;
5354                 break;
5355         case MONO_TYPE_GENERICINST:
5356                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5357                         save_mode = SAVE_EAX;
5358                         break;
5359                 }
5360                 /* Fall through */
5361         case MONO_TYPE_VALUETYPE:
5362                 save_mode = SAVE_STRUCT;
5363                 break;
5364         default:
5365                 save_mode = SAVE_EAX;
5366                 break;
5367         }
5368
5369         /* Save the result and copy it into the proper argument register */
5370         switch (save_mode) {
5371         case SAVE_EAX:
5372                 amd64_push_reg (code, AMD64_RAX);
5373                 /* Align stack */
5374                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5375                 if (enable_arguments)
5376                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5377                 break;
5378         case SAVE_STRUCT:
5379                 /* FIXME: */
5380                 if (enable_arguments)
5381                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5382                 break;
5383         case SAVE_XMM:
5384                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5385                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5386                 /* Align stack */
5387                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5388                 /*
5389                  * The result is already in the proper argument register so no copying
5390                  * needed.
5391                  */
5392                 break;
5393         case SAVE_NONE:
5394                 break;
5395         default:
5396                 g_assert_not_reached ();
5397         }
5398
5399         /* Set %al since this is a varargs call */
5400         if (save_mode == SAVE_XMM)
5401                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5402         else
5403                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5404
5405         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5406         amd64_set_reg_template (code, AMD64_ARG_REG1);
5407         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5408
5409         /* Restore result */
5410         switch (save_mode) {
5411         case SAVE_EAX:
5412                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5413                 amd64_pop_reg (code, AMD64_RAX);
5414                 break;
5415         case SAVE_STRUCT:
5416                 /* FIXME: */
5417                 break;
5418         case SAVE_XMM:
5419                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5420                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5421                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5422                 break;
5423         case SAVE_NONE:
5424                 break;
5425         default:
5426                 g_assert_not_reached ();
5427         }
5428
5429         return code;
5430 }
5431
5432 void
5433 mono_arch_flush_icache (guint8 *code, gint size)
5434 {
5435         /* Not needed */
5436 }
5437
5438 void
5439 mono_arch_flush_register_windows (void)
5440 {
5441 }
5442
5443 gboolean
5444 mono_arch_is_inst_imm (gint64 imm)
5445 {
5446         return amd64_is_imm32 (imm);
5447 }
5448
5449 /*
5450  * Determine whenever the trap whose info is in SIGINFO is caused by
5451  * integer overflow.
5452  */
5453 gboolean
5454 mono_arch_is_int_overflow (void *sigctx, void *info)
5455 {
5456         MonoContext ctx;
5457         guint8* rip;
5458         int reg;
5459         gint64 value;
5460
5461         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5462
5463         rip = (guint8*)ctx.rip;
5464
5465         if (IS_REX (rip [0])) {
5466                 reg = amd64_rex_b (rip [0]);
5467                 rip ++;
5468         }
5469         else
5470                 reg = 0;
5471
5472         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5473                 /* idiv REG */
5474                 reg += x86_modrm_rm (rip [1]);
5475
5476                 switch (reg) {
5477                 case AMD64_RAX:
5478                         value = ctx.rax;
5479                         break;
5480                 case AMD64_RBX:
5481                         value = ctx.rbx;
5482                         break;
5483                 case AMD64_RCX:
5484                         value = ctx.rcx;
5485                         break;
5486                 case AMD64_RDX:
5487                         value = ctx.rdx;
5488                         break;
5489                 case AMD64_RBP:
5490                         value = ctx.rbp;
5491                         break;
5492                 case AMD64_RSP:
5493                         value = ctx.rsp;
5494                         break;
5495                 case AMD64_RSI:
5496                         value = ctx.rsi;
5497                         break;
5498                 case AMD64_RDI:
5499                         value = ctx.rdi;
5500                         break;
5501                 case AMD64_R12:
5502                         value = ctx.r12;
5503                         break;
5504                 case AMD64_R13:
5505                         value = ctx.r13;
5506                         break;
5507                 case AMD64_R14:
5508                         value = ctx.r14;
5509                         break;
5510                 case AMD64_R15:
5511                         value = ctx.r15;
5512                         break;
5513                 default:
5514                         g_assert_not_reached ();
5515                         reg = -1;
5516                 }
5517
5518                 if (value == -1)
5519                         return TRUE;
5520         }
5521
5522         return FALSE;
5523 }
5524
5525 guint32
5526 mono_arch_get_patch_offset (guint8 *code)
5527 {
5528         return 3;
5529 }
5530
5531 /**
5532  * mono_breakpoint_clean_code:
5533  *
5534  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5535  * breakpoints in the original code, they are removed in the copy.
5536  *
5537  * Returns TRUE if no sw breakpoint was present.
5538  */
5539 gboolean
5540 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5541 {
5542         int i;
5543         gboolean can_write = TRUE;
5544         /*
5545          * If method_start is non-NULL we need to perform bound checks, since we access memory
5546          * at code - offset we could go before the start of the method and end up in a different
5547          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5548          * instead.
5549          */
5550         if (!method_start || code - offset >= method_start) {
5551                 memcpy (buf, code - offset, size);
5552         } else {
5553                 int diff = code - method_start;
5554                 memset (buf, 0, size);
5555                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5556         }
5557         code -= offset;
5558         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5559                 int idx = mono_breakpoint_info_index [i];
5560                 guint8 *ptr;
5561                 if (idx < 1)
5562                         continue;
5563                 ptr = mono_breakpoint_info [idx].address;
5564                 if (ptr >= code && ptr < code + size) {
5565                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5566                         can_write = FALSE;
5567                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5568                         buf [ptr - code] = saved_byte;
5569                 }
5570         }
5571         return can_write;
5572 }
5573
5574 gpointer
5575 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5576 {
5577         guint8 buf [10];
5578         guint32 reg;
5579         gint32 disp;
5580         guint8 rex = 0;
5581
5582         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5583         code = buf + 9;
5584
5585         *displacement = 0;
5586
5587         code -= 7;
5588
5589         /*
5590          * A given byte sequence can match more than case here, so we have to be
5591          * really careful about the ordering of the cases. Longer sequences
5592          * come first.
5593          * There are two types of calls:
5594          * - direct calls: 0xff address_byte 8/32 bits displacement
5595          * - indirect calls: nop nop nop <call>
5596          * The nops make sure we don't confuse the instruction preceeding an indirect
5597          * call with a direct call.
5598          */
5599         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5600                 /* call OFFSET(%rip) */
5601                 disp = *(guint32*)(code + 3);
5602                 return (gpointer*)(code + disp + 7);
5603         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
5604                 /* call *[reg+disp32] using indexed addressing */
5605                 /* The LLVM JIT emits this, and we emit it too for %r12 */
5606                 if (IS_REX (code [-1])) {
5607                         rex = code [-1];
5608                         g_assert (amd64_rex_x (rex) == 0);
5609                 }
5610                 reg = amd64_sib_base (code [2]);
5611                 disp = *(gint32*)(code + 3);
5612         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5613                 /* call *[reg+disp32] */
5614                 if (IS_REX (code [0]))
5615                         rex = code [0];
5616                 reg = amd64_modrm_rm (code [2]);
5617                 disp = *(gint32*)(code + 3);
5618                 /* R10 is clobbered by the IMT thunk code */
5619                 g_assert (reg != AMD64_R10);
5620         } else if (code [2] == 0xe8) {
5621                 /* call <ADDR> */
5622                 return NULL;
5623         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
5624                 /* call *[r12+disp8] using indexed addressing */
5625                 if (IS_REX (code [2]))
5626                         rex = code [2];
5627                 reg = amd64_sib_base (code [5]);
5628                 disp = *(gint8*)(code + 6);
5629         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5630                 /* call *%reg */
5631                 return NULL;
5632         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5633                 /* call *[reg+disp8] */
5634                 if (IS_REX (code [3]))
5635                         rex = code [3];
5636                 reg = amd64_modrm_rm (code [5]);
5637                 disp = *(gint8*)(code + 6);
5638                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5639         }
5640         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5641                 /* call *%reg */
5642                 if (IS_REX (code [4]))
5643                         rex = code [4];
5644                 reg = amd64_modrm_rm (code [6]);
5645                 disp = 0;
5646         }
5647         else
5648                 g_assert_not_reached ();
5649
5650         reg += amd64_rex_b (rex);
5651
5652         /* R11 is clobbered by the trampoline code */
5653         g_assert (reg != AMD64_R11);
5654
5655         *displacement = disp;
5656         return regs [reg];
5657 }
5658
5659 gpointer*
5660 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5661 {
5662         gpointer vt;
5663         int displacement;
5664         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5665         if (!vt)
5666                 return NULL;
5667         return (gpointer*)((char*)vt + displacement);
5668 }
5669
5670 int
5671 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5672 {
5673         int this_reg = AMD64_ARG_REG1;
5674
5675         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5676                 CallInfo *cinfo;
5677
5678                 if (!gsctx && code)
5679                         gsctx = mono_get_generic_context_from_code (code);
5680
5681                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5682
5683                 if (cinfo->ret.storage != ArgValuetypeInReg)
5684                         this_reg = AMD64_ARG_REG2;
5685                 g_free (cinfo);
5686         }
5687
5688         return this_reg;
5689 }
5690
5691 gpointer
5692 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5693 {
5694         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5695 }
5696
5697 #define MAX_ARCH_DELEGATE_PARAMS 10
5698
5699 gpointer
5700 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5701 {
5702         guint8 *code, *start;
5703         int i;
5704
5705         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5706                 return NULL;
5707
5708         /* FIXME: Support more cases */
5709         if (MONO_TYPE_ISSTRUCT (sig->ret))
5710                 return NULL;
5711
5712         if (has_target) {
5713                 static guint8* cached = NULL;
5714
5715                 if (cached)
5716                         return cached;
5717
5718                 start = code = mono_global_codeman_reserve (64);
5719
5720                 /* Replace the this argument with the target */
5721                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5722                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5723                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5724
5725                 g_assert ((code - start) < 64);
5726
5727                 mono_debug_add_delegate_trampoline (start, code - start);
5728
5729                 mono_memory_barrier ();
5730
5731                 cached = start;
5732         } else {
5733                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5734                 for (i = 0; i < sig->param_count; ++i)
5735                         if (!mono_is_regsize_var (sig->params [i]))
5736                                 return NULL;
5737                 if (sig->param_count > 4)
5738                         return NULL;
5739
5740                 code = cache [sig->param_count];
5741                 if (code)
5742                         return code;
5743
5744                 start = code = mono_global_codeman_reserve (64);
5745
5746                 if (sig->param_count == 0) {
5747                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5748                 } else {
5749                         /* We have to shift the arguments left */
5750                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5751                         for (i = 0; i < sig->param_count; ++i) {
5752 #ifdef PLATFORM_WIN32
5753                                 if (i < 3)
5754                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5755                                 else
5756                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5757 #else
5758                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5759 #endif
5760                         }
5761
5762                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5763                 }
5764                 g_assert ((code - start) < 64);
5765
5766                 mono_debug_add_delegate_trampoline (start, code - start);
5767
5768                 mono_memory_barrier ();
5769
5770                 cache [sig->param_count] = start;
5771         }
5772
5773         return start;
5774 }
5775
5776 /*
5777  * Support for fast access to the thread-local lmf structure using the GS
5778  * segment register on NPTL + kernel 2.6.x.
5779  */
5780
5781 static gboolean tls_offset_inited = FALSE;
5782
5783 void
5784 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5785 {
5786         if (!tls_offset_inited) {
5787 #ifdef PLATFORM_WIN32
5788                 /*
5789                  * We need to init this multiple times, since when we are first called, the key might not
5790                  * be initialized yet.
5791                  */
5792                 appdomain_tls_offset = mono_domain_get_tls_key ();
5793                 lmf_tls_offset = mono_get_jit_tls_key ();
5794                 thread_tls_offset = mono_thread_get_tls_key ();
5795                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5796
5797                 /* Only 64 tls entries can be accessed using inline code */
5798                 if (appdomain_tls_offset >= 64)
5799                         appdomain_tls_offset = -1;
5800                 if (lmf_tls_offset >= 64)
5801                         lmf_tls_offset = -1;
5802                 if (thread_tls_offset >= 64)
5803                         thread_tls_offset = -1;
5804 #else
5805                 tls_offset_inited = TRUE;
5806 #ifdef MONO_XEN_OPT
5807                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5808 #endif
5809                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5810                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5811                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5812                 thread_tls_offset = mono_thread_get_tls_offset ();
5813 #endif
5814         }
5815 }
5816
5817 void
5818 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5819 {
5820 }
5821
5822 #ifdef MONO_ARCH_HAVE_IMT
5823
5824 #define CMP_SIZE (6 + 1)
5825 #define CMP_REG_REG_SIZE (4 + 1)
5826 #define BR_SMALL_SIZE 2
5827 #define BR_LARGE_SIZE 6
5828 #define MOV_REG_IMM_SIZE 10
5829 #define MOV_REG_IMM_32BIT_SIZE 6
5830 #define JUMP_REG_SIZE (2 + 1)
5831
5832 static int
5833 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5834 {
5835         int i, distance = 0;
5836         for (i = start; i < target; ++i)
5837                 distance += imt_entries [i]->chunk_size;
5838         return distance;
5839 }
5840
5841 /*
5842  * LOCKING: called with the domain lock held
5843  */
5844 gpointer
5845 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5846         gpointer fail_tramp)
5847 {
5848         int i;
5849         int size = 0;
5850         guint8 *code, *start;
5851         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5852
5853         for (i = 0; i < count; ++i) {
5854                 MonoIMTCheckItem *item = imt_entries [i];
5855                 if (item->is_equals) {
5856                         if (item->check_target_idx) {
5857                                 if (!item->compare_done) {
5858                                         if (amd64_is_imm32 (item->key))
5859                                                 item->chunk_size += CMP_SIZE;
5860                                         else
5861                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5862                                 }
5863                                 if (item->has_target_code) {
5864                                         item->chunk_size += MOV_REG_IMM_SIZE;
5865                                 } else {
5866                                         if (vtable_is_32bit)
5867                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5868                                         else
5869                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5870                                 }
5871                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5872                         } else {
5873                                 if (fail_tramp) {
5874                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5875                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5876                                 } else {
5877                                         if (vtable_is_32bit)
5878                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5879                                         else
5880                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5881                                         item->chunk_size += JUMP_REG_SIZE;
5882                                         /* with assert below:
5883                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5884                                          */
5885                                 }
5886                         }
5887                 } else {
5888                         if (amd64_is_imm32 (item->key))
5889                                 item->chunk_size += CMP_SIZE;
5890                         else
5891                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5892                         item->chunk_size += BR_LARGE_SIZE;
5893                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5894                 }
5895                 size += item->chunk_size;
5896         }
5897         if (fail_tramp)
5898                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5899         else
5900                 code = mono_domain_code_reserve (domain, size);
5901         start = code;
5902         for (i = 0; i < count; ++i) {
5903                 MonoIMTCheckItem *item = imt_entries [i];
5904                 item->code_target = code;
5905                 if (item->is_equals) {
5906                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5907
5908                         if (item->check_target_idx || fail_case) {
5909                                 if (!item->compare_done || fail_case) {
5910                                         if (amd64_is_imm32 (item->key))
5911                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5912                                         else {
5913                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5914                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5915                                         }
5916                                 }
5917                                 item->jmp_code = code;
5918                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5919                                 /* See the comment below about R10 */
5920                                 if (item->has_target_code) {
5921                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5922                                         amd64_jump_reg (code, AMD64_R10);
5923                                 } else {
5924                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5925                                         amd64_jump_membase (code, AMD64_R10, 0);
5926                                 }
5927
5928                                 if (fail_case) {
5929                                         amd64_patch (item->jmp_code, code);
5930                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5931                                         amd64_jump_reg (code, AMD64_R10);
5932                                         item->jmp_code = NULL;
5933                                 }
5934                         } else {
5935                                 /* enable the commented code to assert on wrong method */
5936 #if 0
5937                                 if (amd64_is_imm32 (item->key))
5938                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5939                                 else {
5940                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
5941                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5942                                 }
5943                                 item->jmp_code = code;
5944                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5945                                 /* See the comment below about R10 */
5946                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5947                                 amd64_jump_membase (code, AMD64_R10, 0);
5948                                 amd64_patch (item->jmp_code, code);
5949                                 amd64_breakpoint (code);
5950                                 item->jmp_code = NULL;
5951 #else
5952                                 /* We're using R10 here because R11
5953                                    needs to be preserved.  R10 needs
5954                                    to be preserved for calls which
5955                                    require a runtime generic context,
5956                                    but interface calls don't. */
5957                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5958                                 amd64_jump_membase (code, AMD64_R10, 0);
5959 #endif
5960                         }
5961                 } else {
5962                         if (amd64_is_imm32 (item->key))
5963                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5964                         else {
5965                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5966                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5967                         }
5968                         item->jmp_code = code;
5969                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5970                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5971                         else
5972                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5973                 }
5974                 g_assert (code - item->code_target <= item->chunk_size);
5975         }
5976         /* patch the branches to get to the target items */
5977         for (i = 0; i < count; ++i) {
5978                 MonoIMTCheckItem *item = imt_entries [i];
5979                 if (item->jmp_code) {
5980                         if (item->check_target_idx) {
5981                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5982                         }
5983                 }
5984         }
5985
5986         if (!fail_tramp)
5987                 mono_stats.imt_thunks_size += code - start;
5988         g_assert (code - start <= size);
5989
5990         return start;
5991 }
5992
5993 MonoMethod*
5994 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5995 {
5996         return regs [MONO_ARCH_IMT_REG];
5997 }
5998
5999 MonoObject*
6000 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6001 {
6002         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6003 }
6004 #endif
6005
6006 MonoVTable*
6007 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6008 {
6009         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6010 }
6011
6012 MonoInst*
6013 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6014 {
6015         MonoInst *ins = NULL;
6016         int opcode = 0;
6017
6018         if (cmethod->klass == mono_defaults.math_class) {
6019                 if (strcmp (cmethod->name, "Sin") == 0) {
6020                         opcode = OP_SIN;
6021                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6022                         opcode = OP_COS;
6023                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6024                         opcode = OP_SQRT;
6025                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6026                         opcode = OP_ABS;
6027                 }
6028
6029                 if (opcode) {
6030                         MONO_INST_NEW (cfg, ins, opcode);
6031                         ins->type = STACK_R8;
6032                         ins->dreg = mono_alloc_freg (cfg);
6033                         ins->sreg1 = args [0]->dreg;
6034                         MONO_ADD_INS (cfg->cbb, ins);
6035                 }
6036
6037                 opcode = 0;
6038                 if (cfg->opt & MONO_OPT_CMOV) {
6039                         if (strcmp (cmethod->name, "Min") == 0) {
6040                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6041                                         opcode = OP_IMIN;
6042                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6043                                         opcode = OP_IMIN_UN;
6044                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6045                                         opcode = OP_LMIN;
6046                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6047                                         opcode = OP_LMIN_UN;
6048                         } else if (strcmp (cmethod->name, "Max") == 0) {
6049                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6050                                         opcode = OP_IMAX;
6051                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6052                                         opcode = OP_IMAX_UN;
6053                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6054                                         opcode = OP_LMAX;
6055                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6056                                         opcode = OP_LMAX_UN;
6057                         }
6058                 }
6059
6060                 if (opcode) {
6061                         MONO_INST_NEW (cfg, ins, opcode);
6062                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6063                         ins->dreg = mono_alloc_ireg (cfg);
6064                         ins->sreg1 = args [0]->dreg;
6065                         ins->sreg2 = args [1]->dreg;
6066                         MONO_ADD_INS (cfg->cbb, ins);
6067                 }
6068
6069 #if 0
6070                 /* OP_FREM is not IEEE compatible */
6071                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6072                         MONO_INST_NEW (cfg, ins, OP_FREM);
6073                         ins->inst_i0 = args [0];
6074                         ins->inst_i1 = args [1];
6075                 }
6076 #endif
6077         }
6078
6079         /*
6080          * Can't implement CompareExchange methods this way since they have
6081          * three arguments.
6082          */
6083
6084         return ins;
6085 }
6086
6087 gboolean
6088 mono_arch_print_tree (MonoInst *tree, int arity)
6089 {
6090         return 0;
6091 }
6092
6093 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6094 {
6095         MonoInst* ins;
6096
6097         if (appdomain_tls_offset == -1)
6098                 return NULL;
6099
6100         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6101         ins->inst_offset = appdomain_tls_offset;
6102         return ins;
6103 }
6104
6105 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6106 {
6107         MonoInst* ins;
6108
6109         if (thread_tls_offset == -1)
6110                 return NULL;
6111
6112         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6113         ins->inst_offset = thread_tls_offset;
6114         return ins;
6115 }
6116
6117 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6118
6119 gpointer
6120 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6121 {
6122         switch (reg) {
6123         case AMD64_RCX: return (gpointer)ctx->rcx;
6124         case AMD64_RDX: return (gpointer)ctx->rdx;
6125         case AMD64_RBX: return (gpointer)ctx->rbx;
6126         case AMD64_RBP: return (gpointer)ctx->rbp;
6127         case AMD64_RSP: return (gpointer)ctx->rsp;
6128         default:
6129                 if (reg < 8)
6130                         return _CTX_REG (ctx, rax, reg);
6131                 else if (reg >= 12)
6132                         return _CTX_REG (ctx, r12, reg - 12);
6133                 else
6134                         g_assert_not_reached ();
6135         }
6136 }