mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mini_type_get_underlying_type (NULL, type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info = NULL;
 407         MonoClass *klass;
 408         MonoGenericSharingContext tmp_gsctx;
 409
 410         /*
 411          * The gsctx currently contains no data, it is only used for checking whenever
 412          * open types are allowed, some callers like mono_arch_get_argument_info ()
 413          * don't pass it to us, so work around that.
 414          */
 415         if (!gsctx)
 416                 gsctx = &tmp_gsctx;
 417
 418         klass = mono_class_from_mono_type (type);
 419         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 420 #ifndef PLATFORM_WIN32
 421         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 422                 /* We pass and return vtypes of size 8 in a register */
 423         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 424 #else
 425         if (!sig->pinvoke) {
 426 #endif
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = ArgOnStack;
 431
 432                 return;
 433         }
 434
 435         /* FIXME: Handle structs smaller than 8 bytes */
 436         //if ((size % 8) != 0)
 437         //      NOT_IMPLEMENTED;
 438
 439         if (size > 8)
 440                 nquads = 2;
 441         else
 442                 nquads = 1;
 443
 444         if (!sig->pinvoke) {
 445                 /* Always pass in 1 or 2 integer registers */
 446                 args [0] = ARG_CLASS_INTEGER;
 447                 args [1] = ARG_CLASS_INTEGER;
 448                 /* Only the simplest cases are supported */
 449                 if (is_return && nquads != 1) {
 450                         args [0] = ARG_CLASS_MEMORY;
 451                         args [1] = ARG_CLASS_MEMORY;
 452                 }
 453         } else {
 454                 /*
 455                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 456                  * The X87 and SSEUP stuff is left out since there are no such types in
 457                  * the CLR.
 458                  */
 459                 info = mono_marshal_load_type_info (klass);
 460                 g_assert (info);
 461
 462 #ifndef PLATFORM_WIN32
 463                 if (info->native_size > 16) {
 464                         ainfo->offset = *stack_size;
 465                         *stack_size += ALIGN_TO (info->native_size, 8);
 466                         ainfo->storage = ArgOnStack;
 467
 468                         return;
 469                 }
 470 #else
 471                 switch (info->native_size) {
 472                 case 1: case 2: case 4: case 8:
 473                         break;
 474                 default:
 475                         if (is_return) {
 476                                 ainfo->storage = ArgOnStack;
 477                                 ainfo->offset = *stack_size;
 478                                 *stack_size += ALIGN_TO (info->native_size, 8);
 479                         }
 480                         else {
 481                                 ainfo->storage = ArgValuetypeAddrInIReg;
 482
 483                                 if (*gr < PARAM_REGS) {
 484                                         ainfo->pair_storage [0] = ArgInIReg;
 485                                         ainfo->pair_regs [0] = param_regs [*gr];
 486                                         (*gr) ++;
 487                                 }
 488                                 else {
 489                                         ainfo->pair_storage [0] = ArgOnStack;
 490                                         ainfo->offset = *stack_size;
 491                                         *stack_size += 8;
 492                                 }
 493                         }
 494
 495                         return;
 496                 }
 497 #endif
 498
 499                 args [0] = ARG_CLASS_NO_CLASS;
 500                 args [1] = ARG_CLASS_NO_CLASS;
 501                 for (quad = 0; quad < nquads; ++quad) {
 502                         int size;
 503                         guint32 align;
 504                         ArgumentClass class1;
 505
 506                         if (info->num_fields == 0)
 507                                 class1 = ARG_CLASS_MEMORY;
 508                         else
 509                                 class1 = ARG_CLASS_NO_CLASS;
 510                         for (i = 0; i < info->num_fields; ++i) {
 511                                 size = mono_marshal_type_size (info->fields [i].field->type,
 512                                                                                            info->fields [i].mspec,
 513                                                                                            &align, TRUE, klass->unicode);
 514                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 515                                         /* Unaligned field */
 516                                         NOT_IMPLEMENTED;
 517                                 }
 518
 519                                 /* Skip fields in other quad */
 520                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 521                                         continue;
 522                                 if ((quad == 1) && (info->fields [i].offset < 8))
 523                                         continue;
 524
 525                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 526                         }
 527                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 528                         args [quad] = class1;
 529                 }
 530         }
 531
 532         /* Post merger cleanup */
 533         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 534                 args [0] = args [1] = ARG_CLASS_MEMORY;
 535
 536         /* Allocate registers */
 537         {
 538                 int orig_gr = *gr;
 539                 int orig_fr = *fr;
 540
 541                 ainfo->storage = ArgValuetypeInReg;
 542                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 543                 for (quad = 0; quad < nquads; ++quad) {
 544                         switch (args [quad]) {
 545                         case ARG_CLASS_INTEGER:
 546                                 if (*gr >= PARAM_REGS)
 547                                         args [quad] = ARG_CLASS_MEMORY;
 548                                 else {
 549                                         ainfo->pair_storage [quad] = ArgInIReg;
 550                                         if (is_return)
 551                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 552                                         else
 553                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 554                                         (*gr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_SSE:
 558                                 if (*fr >= FLOAT_PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 562                                         ainfo->pair_regs [quad] = *fr;
 563                                         (*fr) ++;
 564                                 }
 565                                 break;
 566                         case ARG_CLASS_MEMORY:
 567                                 break;
 568                         default:
 569                                 g_assert_not_reached ();
 570                         }
 571                 }
 572
 573                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         if (sig->pinvoke)
 580                                 *stack_size += ALIGN_TO (info->native_size, 8);
 581                         else
 582                                 *stack_size += nquads * sizeof (gpointer);
 583                         ainfo->storage = ArgOnStack;
 584                 }
 585         }
 586 }
 587
 588 /*
 589  * get_call_info:
 590  *
 591  *  Obtain information about a call according to the calling convention.
 592  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 593  * Draft Version 0.23" document for more information.
 594  */
 595 static CallInfo*
 596 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 597 {
 598         guint32 i, gr, fr;
 599         MonoType *ret_type;
 600         int n = sig->hasthis + sig->param_count;
 601         guint32 stack_size = 0;
 602         CallInfo *cinfo;
 603
 604         if (mp)
 605                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606         else
 607                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 608
 609         gr = 0;
 610         fr = 0;
 611
 612         /* return value */
 613         {
 614                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 615                 switch (ret_type->type) {
 616                 case MONO_TYPE_BOOLEAN:
 617                 case MONO_TYPE_I1:
 618                 case MONO_TYPE_U1:
 619                 case MONO_TYPE_I2:
 620                 case MONO_TYPE_U2:
 621                 case MONO_TYPE_CHAR:
 622                 case MONO_TYPE_I4:
 623                 case MONO_TYPE_U4:
 624                 case MONO_TYPE_I:
 625                 case MONO_TYPE_U:
 626                 case MONO_TYPE_PTR:
 627                 case MONO_TYPE_FNPTR:
 628                 case MONO_TYPE_CLASS:
 629                 case MONO_TYPE_OBJECT:
 630                 case MONO_TYPE_SZARRAY:
 631                 case MONO_TYPE_ARRAY:
 632                 case MONO_TYPE_STRING:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_U8:
 637                 case MONO_TYPE_I8:
 638                         cinfo->ret.storage = ArgInIReg;
 639                         cinfo->ret.reg = AMD64_RAX;
 640                         break;
 641                 case MONO_TYPE_R4:
 642                         cinfo->ret.storage = ArgInFloatSSEReg;
 643                         cinfo->ret.reg = AMD64_XMM0;
 644                         break;
 645                 case MONO_TYPE_R8:
 646                         cinfo->ret.storage = ArgInDoubleSSEReg;
 647                         cinfo->ret.reg = AMD64_XMM0;
 648                         break;
 649                 case MONO_TYPE_GENERICINST:
 650                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 651                                 cinfo->ret.storage = ArgInIReg;
 652                                 cinfo->ret.reg = AMD64_RAX;
 653                                 break;
 654                         }
 655                         /* fall through */
 656                 case MONO_TYPE_VALUETYPE: {
 657                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 658
 659                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 660                         if (cinfo->ret.storage == ArgOnStack)
 661                                 /* The caller passes the address where the value is stored */
 662                                 add_general (&gr, &stack_size, &cinfo->ret);
 663                         break;
 664                 }
 665                 case MONO_TYPE_TYPEDBYREF:
 666                         /* Same as a valuetype with size 24 */
 667                         add_general (&gr, &stack_size, &cinfo->ret);
 668                         ;
 669                         break;
 670                 case MONO_TYPE_VOID:
 671                         break;
 672                 default:
 673                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 674                 }
 675         }
 676
 677         /* this */
 678         if (sig->hasthis)
 679                 add_general (&gr, &stack_size, cinfo->args + 0);
 680
 681         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 682                 gr = PARAM_REGS;
 683                 fr = FLOAT_PARAM_REGS;
 684
 685                 /* Emit the signature cookie just before the implicit arguments */
 686                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 687         }
 688
 689         for (i = 0; i < sig->param_count; ++i) {
 690                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 691                 MonoType *ptype;
 692
 693 #ifdef PLATFORM_WIN32
 694                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 695                 if (gr > fr)
 696                         fr = gr;
 697                 else if (fr > gr)
 698                         gr = fr;
 699 #endif
 700
 701                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 702                         /* We allways pass the sig cookie on the stack for simplicity */
 703                         /*
 704                          * Prevent implicit arguments + the sig cookie from being passed
 705                          * in registers.
 706                          */
 707                         gr = PARAM_REGS;
 708                         fr = FLOAT_PARAM_REGS;
 709
 710                         /* Emit the signature cookie just before the implicit arguments */
 711                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 712                 }
 713
 714                 if (sig->params [i]->byref) {
 715                         add_general (&gr, &stack_size, ainfo);
 716                         continue;
 717                 }
 718                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 719                 switch (ptype->type) {
 720                 case MONO_TYPE_BOOLEAN:
 721                 case MONO_TYPE_I1:
 722                 case MONO_TYPE_U1:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I2:
 726                 case MONO_TYPE_U2:
 727                 case MONO_TYPE_CHAR:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I4:
 731                 case MONO_TYPE_U4:
 732                         add_general (&gr, &stack_size, ainfo);
 733                         break;
 734                 case MONO_TYPE_I:
 735                 case MONO_TYPE_U:
 736                 case MONO_TYPE_PTR:
 737                 case MONO_TYPE_FNPTR:
 738                 case MONO_TYPE_CLASS:
 739                 case MONO_TYPE_OBJECT:
 740                 case MONO_TYPE_STRING:
 741                 case MONO_TYPE_SZARRAY:
 742                 case MONO_TYPE_ARRAY:
 743                         add_general (&gr, &stack_size, ainfo);
 744                         break;
 745                 case MONO_TYPE_GENERICINST:
 746                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 747                                 add_general (&gr, &stack_size, ainfo);
 748                                 break;
 749                         }
 750                         /* fall through */
 751                 case MONO_TYPE_VALUETYPE:
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753                         break;
 754                 case MONO_TYPE_TYPEDBYREF:
 755 #ifdef PLATFORM_WIN32
 756                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 757 #else
 758                         stack_size += sizeof (MonoTypedRef);
 759                         ainfo->storage = ArgOnStack;
 760 #endif
 761                         break;
 762                 case MONO_TYPE_U8:
 763                 case MONO_TYPE_I8:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_R4:
 767                         add_float (&fr, &stack_size, ainfo, FALSE);
 768                         break;
 769                 case MONO_TYPE_R8:
 770                         add_float (&fr, &stack_size, ainfo, TRUE);
 771                         break;
 772                 default:
 773                         g_assert_not_reached ();
 774                 }
 775         }
 776
 777         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 778                 gr = PARAM_REGS;
 779                 fr = FLOAT_PARAM_REGS;
 780
 781                 /* Emit the signature cookie just before the implicit arguments */
 782                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 783         }
 784
 785 #ifdef PLATFORM_WIN32
 786         // There always is 32 bytes reserved on the stack when calling on Winx64
 787         stack_size += 0x20;
 788 #endif
 789
 790         if (stack_size & 0x8) {
 791                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 792                 cinfo->need_stack_align = TRUE;
 793                 stack_size += 8;
 794         }
 795
 796         cinfo->stack_usage = stack_size;
 797         cinfo->reg_usage = gr;
 798         cinfo->freg_usage = fr;
 799         return cinfo;
 800 }
 801
 802 /*
 803  * mono_arch_get_argument_info:
 804  * @csig:  a method signature
 805  * @param_count: the number of parameters to consider
 806  * @arg_info: an array to store the result infos
 807  *
 808  * Gathers information on parameters such as size, alignment and
 809  * padding. arg_info should be large enought to hold param_count + 1 entries.
 810  *
 811  * Returns the size of the argument area on the stack.
 812  */
 813 int
 814 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 815 {
 816         int k;
 817         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 818         guint32 args_size = cinfo->stack_usage;
 819
 820         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 821         if (csig->hasthis) {
 822                 arg_info [0].offset = 0;
 823         }
 824
 825         for (k = 0; k < param_count; k++) {
 826                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 827                 /* FIXME: */
 828                 arg_info [k + 1].size = 0;
 829         }
 830
 831         g_free (cinfo);
 832
 833         return args_size;
 834 }
 835
 836 static int
 837 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 838 {
 839 #ifndef _MSC_VER
 840         __asm__ __volatile__ ("cpuid"
 841                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 842                 : "a" (id));
 843 #else
 844         int info[4];
 845         __cpuid(info, id);
 846         *p_eax = info[0];
 847         *p_ebx = info[1];
 848         *p_ecx = info[2];
 849         *p_edx = info[3];
 850 #endif
 851         return 1;
 852 }
 853
 854 /*
 855  * Initialize the cpu to execute managed code.
 856  */
 857 void
 858 mono_arch_cpu_init (void)
 859 {
 860 #ifndef _MSC_VER
 861         guint16 fpcw;
 862
 863         /* spec compliance requires running with double precision */
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865         fpcw &= ~X86_FPCW_PRECC_MASK;
 866         fpcw |= X86_FPCW_PREC_DOUBLE;
 867         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 868         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 869 #else
 870         /* TODO: This is crashing on Win64 right now.
 871         * _control87 (_PC_53, MCW_PC);
 872         */
 873 #endif
 874 }
 875
 876 /*
 877  * Initialize architecture specific code.
 878  */
 879 void
 880 mono_arch_init (void)
 881 {
 882         InitializeCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * Cleanup architecture specific code.
 887  */
 888 void
 889 mono_arch_cleanup (void)
 890 {
 891         DeleteCriticalSection (&mini_arch_mutex);
 892 }
 893
 894 /*
 895  * This function returns the optimizations supported on this cpu.
 896  */
 897 guint32
 898 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 899 {
 900         int eax, ebx, ecx, edx;
 901         guint32 opts = 0;
 902
 903         /* FIXME: AMD64 */
 904
 905         *exclude_mask = 0;
 906         /* Feature Flags function, flags returned in EDX. */
 907         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 908                 if (edx & (1 << 15)) {
 909                         opts |= MONO_OPT_CMOV;
 910                         if (edx & 1)
 911                                 opts |= MONO_OPT_FCMOV;
 912                         else
 913                                 *exclude_mask |= MONO_OPT_FCMOV;
 914                 } else
 915                         *exclude_mask |= MONO_OPT_CMOV;
 916         }
 917
 918         return opts;
 919 }
 920
 921 GList *
 922 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 923 {
 924         GList *vars = NULL;
 925         int i;
 926
 927         for (i = 0; i < cfg->num_varinfo; i++) {
 928                 MonoInst *ins = cfg->varinfo [i];
 929                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 930
 931                 /* unused vars */
 932                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 933                         continue;
 934
 935                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 936                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 937                         continue;
 938
 939                 if (mono_is_regsize_var (ins->inst_vtype)) {
 940                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 941                         g_assert (i == vmv->idx);
 942                         vars = g_list_prepend (vars, vmv);
 943                 }
 944         }
 945
 946         vars = mono_varlist_sort (cfg, vars, 0);
 947
 948         return vars;
 949 }
 950
 951 /**
 952  * mono_arch_compute_omit_fp:
 953  *
 954  *   Determine whenever the frame pointer can be eliminated.
 955  */
 956 static void
 957 mono_arch_compute_omit_fp (MonoCompile *cfg)
 958 {
 959         MonoMethodSignature *sig;
 960         MonoMethodHeader *header;
 961         int i, locals_size;
 962         CallInfo *cinfo;
 963
 964         if (cfg->arch.omit_fp_computed)
 965                 return;
 966
 967         header = mono_method_get_header (cfg->method);
 968
 969         sig = mono_method_signature (cfg->method);
 970
 971         if (!cfg->arch.cinfo)
 972                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 973         cinfo = cfg->arch.cinfo;
 974
 975         /*
 976          * FIXME: Remove some of the restrictions.
 977          */
 978         cfg->arch.omit_fp = TRUE;
 979         cfg->arch.omit_fp_computed = TRUE;
 980
 981         if (cfg->disable_omit_fp)
 982                 cfg->arch.omit_fp = FALSE;
 983
 984         if (!debug_omit_fp ())
 985                 cfg->arch.omit_fp = FALSE;
 986         /*
 987         if (cfg->method->save_lmf)
 988                 cfg->arch.omit_fp = FALSE;
 989         */
 990         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 991                 cfg->arch.omit_fp = FALSE;
 992         if (header->num_clauses)
 993                 cfg->arch.omit_fp = FALSE;
 994         if (cfg->param_area)
 995                 cfg->arch.omit_fp = FALSE;
 996         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 997                 cfg->arch.omit_fp = FALSE;
 998         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 999                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1000                 cfg->arch.omit_fp = FALSE;
1001         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1002                 ArgInfo *ainfo = &cinfo->args [i];
1003
1004                 if (ainfo->storage == ArgOnStack) {
1005                         /*
1006                          * The stack offset can only be determined when the frame
1007                          * size is known.
1008                          */
1009                         cfg->arch.omit_fp = FALSE;
1010                 }
1011         }
1012
1013         locals_size = 0;
1014         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015                 MonoInst *ins = cfg->varinfo [i];
1016                 int ialign;
1017
1018                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1019         }
1020
1021         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1022                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1023                 cfg->arch.omit_fp = FALSE;
1024         }
1025 }
1026
1027 GList *
1028 mono_arch_get_global_int_regs (MonoCompile *cfg)
1029 {
1030         GList *regs = NULL;
1031
1032         mono_arch_compute_omit_fp (cfg);
1033
1034         if (cfg->globalra) {
1035                 if (cfg->arch.omit_fp)
1036                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1037
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1043
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1052         } else {
1053                 if (cfg->arch.omit_fp)
1054                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1055
1056                 /* We use the callee saved registers for global allocation */
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1061                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1062         }
1063
1064         return regs;
1065 }
1066
1067 GList*
1068 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1069 {
1070         GList *regs = NULL;
1071         int i;
1072
1073         /* All XMM registers */
1074         for (i = 0; i < 16; ++i)
1075                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1076
1077         return regs;
1078 }
1079
1080 GList*
1081 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1082 {
1083         static GList *r = NULL;
1084
1085         if (r == NULL) {
1086                 GList *regs = NULL;
1087
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1094
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1102                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1103
1104                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1105         }
1106
1107         return r;
1108 }
1109
1110 GList*
1111 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1112 {
1113         int i;
1114         static GList *r = NULL;
1115
1116         if (r == NULL) {
1117                 GList *regs = NULL;
1118
1119                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1120                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1121
1122                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1123         }
1124
1125         return r;
1126 }
1127
1128 /*
1129  * mono_arch_regalloc_cost:
1130  *
1131  *  Return the cost, in number of memory references, of the action of
1132  * allocating the variable VMV into a register during global register
1133  * allocation.
1134  */
1135 guint32
1136 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1137 {
1138         MonoInst *ins = cfg->varinfo [vmv->idx];
1139
1140         if (cfg->method->save_lmf)
1141                 /* The register is already saved */
1142                 /* substract 1 for the invisible store in the prolog */
1143                 return (ins->opcode == OP_ARG) ? 0 : 1;
1144         else
1145                 /* push+pop */
1146                 return (ins->opcode == OP_ARG) ? 1 : 2;
1147 }
1148
1149 /*
1150  * mono_arch_fill_argument_info:
1151  *
1152  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1153  * of the method.
1154  */
1155 void
1156 mono_arch_fill_argument_info (MonoCompile *cfg)
1157 {
1158         MonoMethodSignature *sig;
1159         MonoMethodHeader *header;
1160         MonoInst *ins;
1161         int i;
1162         CallInfo *cinfo;
1163
1164         header = mono_method_get_header (cfg->method);
1165
1166         sig = mono_method_signature (cfg->method);
1167
1168         cinfo = cfg->arch.cinfo;
1169
1170         /*
1171          * Contrary to mono_arch_allocate_vars (), the information should describe
1172          * where the arguments are at the beginning of the method, not where they can be
1173          * accessed during the execution of the method. The later makes no sense for the
1174          * global register allocator, since a variable can be in more than one location.
1175          */
1176         if (sig->ret->type != MONO_TYPE_VOID) {
1177                 switch (cinfo->ret.storage) {
1178                 case ArgInIReg:
1179                 case ArgInFloatSSEReg:
1180                 case ArgInDoubleSSEReg:
1181                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1182                                 cfg->vret_addr->opcode = OP_REGVAR;
1183                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1184                         }
1185                         else {
1186                                 cfg->ret->opcode = OP_REGVAR;
1187                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1188                         }
1189                         break;
1190                 case ArgValuetypeInReg:
1191                         cfg->ret->opcode = OP_REGOFFSET;
1192                         cfg->ret->inst_basereg = -1;
1193                         cfg->ret->inst_offset = -1;
1194                         break;
1195                 default:
1196                         g_assert_not_reached ();
1197                 }
1198         }
1199
1200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1201                 ArgInfo *ainfo = &cinfo->args [i];
1202                 MonoType *arg_type;
1203
1204                 ins = cfg->args [i];
1205
1206                 if (sig->hasthis && (i == 0))
1207                         arg_type = &mono_defaults.object_class->byval_arg;
1208                 else
1209                         arg_type = sig->params [i - sig->hasthis];
1210
1211                 switch (ainfo->storage) {
1212                 case ArgInIReg:
1213                 case ArgInFloatSSEReg:
1214                 case ArgInDoubleSSEReg:
1215                         ins->opcode = OP_REGVAR;
1216                         ins->inst_c0 = ainfo->reg;
1217                         break;
1218                 case ArgOnStack:
1219                         ins->opcode = OP_REGOFFSET;
1220                         ins->inst_basereg = -1;
1221                         ins->inst_offset = -1;
1222                         break;
1223                 case ArgValuetypeInReg:
1224                         /* Dummy */
1225                         ins->opcode = OP_NOP;
1226                         break;
1227                 default:
1228                         g_assert_not_reached ();
1229                 }
1230         }
1231 }
1232
1233 void
1234 mono_arch_allocate_vars (MonoCompile *cfg)
1235 {
1236         MonoMethodSignature *sig;
1237         MonoMethodHeader *header;
1238         MonoInst *ins;
1239         int i, offset;
1240         guint32 locals_stack_size, locals_stack_align;
1241         gint32 *offsets;
1242         CallInfo *cinfo;
1243
1244         header = mono_method_get_header (cfg->method);
1245
1246         sig = mono_method_signature (cfg->method);
1247
1248         cinfo = cfg->arch.cinfo;
1249
1250         mono_arch_compute_omit_fp (cfg);
1251
1252         /*
1253          * We use the ABI calling conventions for managed code as well.
1254          * Exception: valuetypes are never passed or returned in registers.
1255          */
1256
1257         if (cfg->arch.omit_fp) {
1258                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1259                 cfg->frame_reg = AMD64_RSP;
1260                 offset = 0;
1261         } else {
1262                 /* Locals are allocated backwards from %fp */
1263                 cfg->frame_reg = AMD64_RBP;
1264                 offset = 0;
1265         }
1266
1267         if (cfg->method->save_lmf) {
1268                 /* Reserve stack space for saving LMF */
1269                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1270                 g_assert (offset == 0);
1271                 if (cfg->arch.omit_fp) {
1272                         cfg->arch.lmf_offset = offset;
1273                         offset += sizeof (MonoLMF);
1274                 }
1275                 else {
1276                         offset += sizeof (MonoLMF);
1277                         cfg->arch.lmf_offset = -offset;
1278                 }
1279         } else {
1280                 if (cfg->arch.omit_fp)
1281                         cfg->arch.reg_save_area_offset = offset;
1282                 /* Reserve space for caller saved registers */
1283                 for (i = 0; i < AMD64_NREG; ++i)
1284                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1285                                 offset += sizeof (gpointer);
1286                         }
1287         }
1288
1289         if (sig->ret->type != MONO_TYPE_VOID) {
1290                 switch (cinfo->ret.storage) {
1291                 case ArgInIReg:
1292                 case ArgInFloatSSEReg:
1293                 case ArgInDoubleSSEReg:
1294                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1295                                 if (cfg->globalra) {
1296                                         cfg->vret_addr->opcode = OP_REGVAR;
1297                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1298                                 } else {
1299                                         /* The register is volatile */
1300                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1301                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1302                                         if (cfg->arch.omit_fp) {
1303                                                 cfg->vret_addr->inst_offset = offset;
1304                                                 offset += 8;
1305                                         } else {
1306                                                 offset += 8;
1307                                                 cfg->vret_addr->inst_offset = -offset;
1308                                         }
1309                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1310                                                 printf ("vret_addr =");
1311                                                 mono_print_ins (cfg->vret_addr);
1312                                         }
1313                                 }
1314                         }
1315                         else {
1316                                 cfg->ret->opcode = OP_REGVAR;
1317                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1318                         }
1319                         break;
1320                 case ArgValuetypeInReg:
1321                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1322                         cfg->ret->opcode = OP_REGOFFSET;
1323                         cfg->ret->inst_basereg = cfg->frame_reg;
1324                         if (cfg->arch.omit_fp) {
1325                                 cfg->ret->inst_offset = offset;
1326                                 offset += 16;
1327                         } else {
1328                                 offset += 16;
1329                                 cfg->ret->inst_offset = - offset;
1330                         }
1331                         break;
1332                 default:
1333                         g_assert_not_reached ();
1334                 }
1335                 if (!cfg->globalra)
1336                         cfg->ret->dreg = cfg->ret->inst_c0;
1337         }
1338
1339         /* Allocate locals */
1340         if (!cfg->globalra) {
1341                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1342                 if (locals_stack_align) {
1343                         offset += (locals_stack_align - 1);
1344                         offset &= ~(locals_stack_align - 1);
1345                 }
1346                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1347                         if (offsets [i] != -1) {
1348                                 MonoInst *ins = cfg->varinfo [i];
1349                                 ins->opcode = OP_REGOFFSET;
1350                                 ins->inst_basereg = cfg->frame_reg;
1351                                 if (cfg->arch.omit_fp)
1352                                         ins->inst_offset = (offset + offsets [i]);
1353                                 else
1354                                         ins->inst_offset = - (offset + offsets [i]);
1355                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1356                         }
1357                 }
1358                 offset += locals_stack_size;
1359         }
1360
1361         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1362                 g_assert (!cfg->arch.omit_fp);
1363                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1364                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1365         }
1366
1367         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1368                 ins = cfg->args [i];
1369                 if (ins->opcode != OP_REGVAR) {
1370                         ArgInfo *ainfo = &cinfo->args [i];
1371                         gboolean inreg = TRUE;
1372                         MonoType *arg_type;
1373
1374                         if (sig->hasthis && (i == 0))
1375                                 arg_type = &mono_defaults.object_class->byval_arg;
1376                         else
1377                                 arg_type = sig->params [i - sig->hasthis];
1378
1379                         if (cfg->globalra) {
1380                                 /* The new allocator needs info about the original locations of the arguments */
1381                                 switch (ainfo->storage) {
1382                                 case ArgInIReg:
1383                                 case ArgInFloatSSEReg:
1384                                 case ArgInDoubleSSEReg:
1385                                         ins->opcode = OP_REGVAR;
1386                                         ins->inst_c0 = ainfo->reg;
1387                                         break;
1388                                 case ArgOnStack:
1389                                         g_assert (!cfg->arch.omit_fp);
1390                                         ins->opcode = OP_REGOFFSET;
1391                                         ins->inst_basereg = cfg->frame_reg;
1392                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1393                                         break;
1394                                 case ArgValuetypeInReg:
1395                                         ins->opcode = OP_REGOFFSET;
1396                                         ins->inst_basereg = cfg->frame_reg;
1397                                         /* These arguments are saved to the stack in the prolog */
1398                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1399                                         if (cfg->arch.omit_fp) {
1400                                                 ins->inst_offset = offset;
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                         } else {
1403                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1404                                                 ins->inst_offset = - offset;
1405                                         }
1406                                         break;
1407                                 default:
1408                                         g_assert_not_reached ();
1409                                 }
1410
1411                                 continue;
1412                         }
1413
1414                         /* FIXME: Allocate volatile arguments to registers */
1415                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1416                                 inreg = FALSE;
1417
1418                         /*
1419                          * Under AMD64, all registers used to pass arguments to functions
1420                          * are volatile across calls.
1421                          * FIXME: Optimize this.
1422                          */
1423                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1424                                 inreg = FALSE;
1425
1426                         ins->opcode = OP_REGOFFSET;
1427
1428                         switch (ainfo->storage) {
1429                         case ArgInIReg:
1430                         case ArgInFloatSSEReg:
1431                         case ArgInDoubleSSEReg:
1432                                 if (inreg) {
1433                                         ins->opcode = OP_REGVAR;
1434                                         ins->dreg = ainfo->reg;
1435                                 }
1436                                 break;
1437                         case ArgOnStack:
1438                                 g_assert (!cfg->arch.omit_fp);
1439                                 ins->opcode = OP_REGOFFSET;
1440                                 ins->inst_basereg = cfg->frame_reg;
1441                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1442                                 break;
1443                         case ArgValuetypeInReg:
1444                                 break;
1445                         case ArgValuetypeAddrInIReg: {
1446                                 MonoInst *indir;
1447                                 g_assert (!cfg->arch.omit_fp);
1448
1449                                 MONO_INST_NEW (cfg, indir, 0);
1450                                 indir->opcode = OP_REGOFFSET;
1451                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1452                                         indir->inst_basereg = cfg->frame_reg;
1453                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1454                                         offset += (sizeof (gpointer));
1455                                         indir->inst_offset = - offset;
1456                                 }
1457                                 else {
1458                                         indir->inst_basereg = cfg->frame_reg;
1459                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1460                                 }
1461
1462                                 ins->opcode = OP_VTARG_ADDR;
1463                                 ins->inst_left = indir;
1464
1465                                 break;
1466                         }
1467                         default:
1468                                 NOT_IMPLEMENTED;
1469                         }
1470
1471                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1472                                 ins->opcode = OP_REGOFFSET;
1473                                 ins->inst_basereg = cfg->frame_reg;
1474                                 /* These arguments are saved to the stack in the prolog */
1475                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1476                                 if (cfg->arch.omit_fp) {
1477                                         ins->inst_offset = offset;
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                 } else {
1480                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1481                                         ins->inst_offset = - offset;
1482                                 }
1483                         }
1484                 }
1485         }
1486
1487         cfg->stack_offset = offset;
1488 }
1489
1490 void
1491 mono_arch_create_vars (MonoCompile *cfg)
1492 {
1493         MonoMethodSignature *sig;
1494         CallInfo *cinfo;
1495
1496         sig = mono_method_signature (cfg->method);
1497
1498         if (!cfg->arch.cinfo)
1499                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1500         cinfo = cfg->arch.cinfo;
1501
1502         if (cinfo->ret.storage == ArgValuetypeInReg)
1503                 cfg->ret_var_is_local = TRUE;
1504
1505         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1506                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1507                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1508                         printf ("vret_addr = ");
1509                         mono_print_ins (cfg->vret_addr);
1510                 }
1511         }
1512 }
1513
1514 static void
1515 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1516 {
1517         switch (storage) {
1518         case ArgInIReg:
1519                 arg->opcode = OP_OUTARG_REG;
1520                 arg->inst_left = tree;
1521                 arg->inst_call = call;
1522                 arg->backend.reg3 = reg;
1523                 break;
1524         case ArgInFloatSSEReg:
1525                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1526                 arg->inst_left = tree;
1527                 arg->inst_call = call;
1528                 arg->backend.reg3 = reg;
1529                 break;
1530         case ArgInDoubleSSEReg:
1531                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1532                 arg->inst_left = tree;
1533                 arg->inst_call = call;
1534                 arg->backend.reg3 = reg;
1535                 break;
1536         default:
1537                 g_assert_not_reached ();
1538         }
1539 }
1540
1541 static void
1542 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1543 {
1544         MonoInst *ins;
1545
1546         switch (storage) {
1547         case ArgInIReg:
1548                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1549                 ins->dreg = mono_alloc_ireg (cfg);
1550                 ins->sreg1 = tree->dreg;
1551                 MONO_ADD_INS (cfg->cbb, ins);
1552                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1553                 break;
1554         case ArgInFloatSSEReg:
1555                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1556                 ins->dreg = mono_alloc_freg (cfg);
1557                 ins->sreg1 = tree->dreg;
1558                 MONO_ADD_INS (cfg->cbb, ins);
1559
1560                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1561                 break;
1562         case ArgInDoubleSSEReg:
1563                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1564                 ins->dreg = mono_alloc_freg (cfg);
1565                 ins->sreg1 = tree->dreg;
1566                 MONO_ADD_INS (cfg->cbb, ins);
1567
1568                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1569
1570                 break;
1571         default:
1572                 g_assert_not_reached ();
1573         }
1574 }
1575
1576 static int
1577 arg_storage_to_ldind (ArgStorage storage)
1578 {
1579         switch (storage) {
1580         case ArgInIReg:
1581                 return CEE_LDIND_I;
1582         case ArgInDoubleSSEReg:
1583                 return CEE_LDIND_R8;
1584         case ArgInFloatSSEReg:
1585                 return CEE_LDIND_R4;
1586         default:
1587                 g_assert_not_reached ();
1588         }
1589
1590         return -1;
1591 }
1592
1593 static int
1594 arg_storage_to_load_membase (ArgStorage storage)
1595 {
1596         switch (storage) {
1597         case ArgInIReg:
1598                 return OP_LOAD_MEMBASE;
1599         case ArgInDoubleSSEReg:
1600                 return OP_LOADR8_MEMBASE;
1601         case ArgInFloatSSEReg:
1602                 return OP_LOADR4_MEMBASE;
1603         default:
1604                 g_assert_not_reached ();
1605         }
1606
1607         return -1;
1608 }
1609
1610 static void
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1612 {
1613         MonoInst *arg;
1614         MonoMethodSignature *tmp_sig;
1615         MonoInst *sig_arg;
1616
1617         /* FIXME: Add support for signature tokens to AOT */
1618         cfg->disable_aot = TRUE;
1619
1620         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1621
1622         /*
1623          * mono_ArgIterator_Setup assumes the signature cookie is
1624          * passed first and all the arguments which were before it are
1625          * passed on the stack after the signature. So compensate by
1626          * passing a different signature.
1627          */
1628         tmp_sig = mono_metadata_signature_dup (call->signature);
1629         tmp_sig->param_count -= call->signature->sentinelpos;
1630         tmp_sig->sentinelpos = 0;
1631         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1632
1633         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1634         sig_arg->inst_p0 = tmp_sig;
1635
1636         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1637         arg->inst_left = sig_arg;
1638         arg->type = STACK_PTR;
1639
1640         /* prepend, so they get reversed */
1641         arg->next = call->out_args;
1642         call->out_args = arg;
1643 }
1644
1645 /*
1646  * take the arguments and generate the arch-specific
1647  * instructions to properly call the function in call.
1648  * This includes pushing, moving arguments to the right register
1649  * etc.
1650  */
1651 MonoCallInst*
1652 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1653         MonoInst *arg, *in;
1654         MonoMethodSignature *sig;
1655         int i, n, stack_size;
1656         CallInfo *cinfo;
1657         ArgInfo *ainfo;
1658
1659         stack_size = 0;
1660
1661         sig = call->signature;
1662         n = sig->param_count + sig->hasthis;
1663
1664         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1665
1666         if (cfg->method->save_lmf) {
1667                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1668                 arg->next = call->out_args;
1669                 call->out_args = arg;
1670         }
1671
1672         for (i = 0; i < n; ++i) {
1673                 ainfo = cinfo->args + i;
1674
1675                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1676                         /* Emit the signature cookie just before the implicit arguments */
1677                         emit_sig_cookie (cfg, call, cinfo);
1678                 }
1679
1680                 if (is_virtual && i == 0) {
1681                         /* the argument will be attached to the call instruction */
1682                         in = call->args [i];
1683                 } else {
1684                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1685                         in = call->args [i];
1686                         arg->cil_code = in->cil_code;
1687                         arg->inst_left = in;
1688                         arg->type = in->type;
1689                         /* prepend, so they get reversed */
1690                         arg->next = call->out_args;
1691                         call->out_args = arg;
1692 #if 0
1693                         if (!cinfo->stack_usage)
1694                                 /* Keep the assignments to the arg registers in order if possible */
1695                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1696                         else
1697                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1698 #endif
1699
1700                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1701                                 guint32 align;
1702                                 guint32 size;
1703
1704                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1705                                         size = sizeof (MonoTypedRef);
1706                                         align = sizeof (gpointer);
1707                                 }
1708                                 else
1709                                 if (sig->pinvoke)
1710                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1711                                 else {
1712                                         /*
1713                                          * Other backends use mini_type_stack_size (), but that
1714                                          * aligns the size to 8, which is larger than the size of
1715                                          * the source, leading to reads of invalid memory if the
1716                                          * source is at the end of address space.
1717                                          */
1718                                         size = mono_class_value_size (in->klass, &align);
1719                                 }
1720                                 if (ainfo->storage == ArgValuetypeInReg) {
1721                                         if (ainfo->pair_storage [1] == ArgNone) {
1722                                                 MonoInst *load;
1723
1724                                                 /* Simpler case */
1725
1726                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1727                                                 load->inst_left = in;
1728
1729                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1730                                         }
1731                                         else {
1732                                                 /* Trees can't be shared so make a copy */
1733                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1734                                                 MonoInst *load, *load2, *offset_ins;
1735
1736                                                 /* Reg1 */
1737                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1738                                                 load->ssa_op = MONO_SSA_LOAD;
1739                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1740
1741                                                 NEW_ICONST (cfg, offset_ins, 0);
1742                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1743                                                 load2->inst_left = load;
1744                                                 load2->inst_right = offset_ins;
1745
1746                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1747                                                 load->inst_left = load2;
1748
1749                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1750
1751                                                 /* Reg2 */
1752                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1753                                                 load->ssa_op = MONO_SSA_LOAD;
1754                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1755
1756                                                 NEW_ICONST (cfg, offset_ins, 8);
1757                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1758                                                 load2->inst_left = load;
1759                                                 load2->inst_right = offset_ins;
1760
1761                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1762                                                 load->inst_left = load2;
1763
1764                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1765                                                 arg->cil_code = in->cil_code;
1766                                                 arg->type = in->type;
1767                                                 /* prepend, so they get reversed */
1768                                                 arg->next = call->out_args;
1769                                                 call->out_args = arg;
1770
1771                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1772
1773                                                 /* Prepend a copy inst */
1774                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1775                                                 arg->cil_code = in->cil_code;
1776                                                 arg->ssa_op = MONO_SSA_STORE;
1777                                                 arg->inst_left = vtaddr;
1778                                                 arg->inst_right = in;
1779                                                 arg->type = in->type;
1780
1781                                                 /* prepend, so they get reversed */
1782                                                 arg->next = call->out_args;
1783                                                 call->out_args = arg;
1784                                         }
1785                                 }
1786                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1787
1788                                         /* Add a temp variable to the method*/
1789                                         MonoInst *load;
1790                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1791
1792                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1793                                         load->ssa_op = MONO_SSA_LOAD;
1794                                         load->inst_left = vtaddr;
1795
1796                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1797                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1798                                                 arg->opcode = OP_OUTARG_REG;
1799                                                 arg->inst_left = load;
1800                                                 arg->inst_call = call;
1801                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1802                                         }
1803                                         else {
1804                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1805                                                 arg->opcode = OP_OUTARG_VT;
1806                                                 arg->inst_left = load;
1807                                                 arg->type = STACK_PTR;
1808                                                 arg->klass = mono_defaults.int_class;
1809                                                 arg->backend.is_pinvoke = sig->pinvoke;
1810                                                 arg->inst_imm = size;
1811                                         }
1812
1813                                         /*Copy the argument to the temp variable.*/
1814                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1815                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1816                                         load->backend.memcpy_args->size = size;
1817                                         load->backend.memcpy_args->align = align;
1818                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1819                                         load->inst_right = in->inst_i0;
1820
1821                                         // FIXME:
1822                                         g_assert_not_reached ();
1823                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1824                                 }
1825                                 else {
1826                                         arg->opcode = OP_OUTARG_VT;
1827                                         arg->klass = in->klass;
1828                                         arg->backend.is_pinvoke = sig->pinvoke;
1829                                         arg->inst_imm = size;
1830                                 }
1831                         }
1832                         else {
1833                                 switch (ainfo->storage) {
1834                                 case ArgInIReg:
1835                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1836                                         break;
1837                                 case ArgInFloatSSEReg:
1838                                 case ArgInDoubleSSEReg:
1839                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1840                                         break;
1841                                 case ArgOnStack:
1842                                         arg->opcode = OP_OUTARG;
1843                                         if (!sig->params [i - sig->hasthis]->byref) {
1844                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1845                                                         arg->opcode = OP_OUTARG_R4;
1846                                                 else
1847                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1848                                                                 arg->opcode = OP_OUTARG_R8;
1849                                         }
1850                                         break;
1851                                 default:
1852                                         g_assert_not_reached ();
1853                                 }
1854                         }
1855                 }
1856         }
1857
1858         /* Handle the case where there are no implicit arguments */
1859         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1860                 emit_sig_cookie (cfg, call, cinfo);
1861         }
1862
1863         if (cinfo->ret.storage == ArgValuetypeInReg) {
1864                 /* This is needed by mono_arch_emit_this_vret_args () */
1865                 if (!cfg->arch.vret_addr_loc) {
1866                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867                         /* Prevent it from being register allocated or optimized away */
1868                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1869                 }
1870         }
1871
1872         if (cinfo->need_stack_align) {
1873                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1874                 arg->inst_c0 = 8;
1875                 /* prepend, so they get reversed */
1876                 arg->next = call->out_args;
1877                 call->out_args = arg;
1878         }
1879
1880 #ifdef PLATFORM_WIN32
1881         /* Always reserve 32 bytes of stack space on Win64 */
1882         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1883         arg->inst_c0 = 32;
1884         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1885         NOT_IMPLEMENTED;
1886 #endif
1887
1888 #if 0
1889         if (cfg->method->save_lmf) {
1890                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1891                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1892         }
1893 #endif
1894
1895         call->stack_usage = cinfo->stack_usage;
1896         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1897         cfg->flags |= MONO_CFG_HAS_CALLS;
1898
1899         return call;
1900 }
1901
1902 static void
1903 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1904 {
1905         MonoInst *arg;
1906         MonoMethodSignature *tmp_sig;
1907         MonoInst *sig_arg;
1908
1909         if (call->tail_call)
1910                 NOT_IMPLEMENTED;
1911
1912         /* FIXME: Add support for signature tokens to AOT */
1913         cfg->disable_aot = TRUE;
1914
1915         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1916
1917         /*
1918          * mono_ArgIterator_Setup assumes the signature cookie is
1919          * passed first and all the arguments which were before it are
1920          * passed on the stack after the signature. So compensate by
1921          * passing a different signature.
1922          */
1923         tmp_sig = mono_metadata_signature_dup (call->signature);
1924         tmp_sig->param_count -= call->signature->sentinelpos;
1925         tmp_sig->sentinelpos = 0;
1926         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1927
1928         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1929         sig_arg->dreg = mono_alloc_ireg (cfg);
1930         sig_arg->inst_p0 = tmp_sig;
1931         MONO_ADD_INS (cfg->cbb, sig_arg);
1932
1933         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1934         arg->sreg1 = sig_arg->dreg;
1935         MONO_ADD_INS (cfg->cbb, arg);
1936 }
1937
1938 #define NEW_VARSTORE(cfg,dest,var,vartype,inst) do {    \
1939         MONO_INST_NEW ((cfg), (dest), OP_MOVE); \
1940                 (dest)->opcode = mono_type_to_regmove ((cfg), (vartype));    \
1941                 (dest)->klass = (var)->klass;   \
1942         (dest)->sreg1 = (inst)->dreg; \
1943                 (dest)->dreg = (var)->dreg;   \
1944         if ((dest)->opcode == OP_VMOVE) (dest)->klass = mono_class_from_mono_type ((vartype)); \
1945         } while (0)
1946
1947 #define NEW_ARGSTORE(cfg,dest,num,inst) NEW_VARSTORE ((cfg), (dest), cfg->args [(num)], cfg->arg_types [(num)], (inst))
1948
1949 #define EMIT_NEW_ARGSTORE(cfg,dest,num,inst) do { NEW_ARGSTORE ((cfg), (dest), (num), (inst)); MONO_ADD_INS ((cfg)->cbb, (dest)); } while (0)
1950
1951 void
1952 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1953 {
1954         MonoInst *arg, *in;
1955         MonoMethodSignature *sig;
1956         int i, n, stack_size;
1957         CallInfo *cinfo;
1958         ArgInfo *ainfo;
1959
1960         stack_size = 0;
1961
1962         sig = call->signature;
1963         n = sig->param_count + sig->hasthis;
1964
1965         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1966
1967         if (cinfo->need_stack_align) {
1968                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1969         }
1970
1971         /*
1972          * Emit all parameters passed in registers in non-reverse order for better readability
1973          * and to help the optimization in emit_prolog ().
1974          */
1975         for (i = 0; i < n; ++i) {
1976                 ainfo = cinfo->args + i;
1977
1978                 in = call->args [i];
1979
1980                 if (ainfo->storage == ArgInIReg)
1981                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1982         }
1983
1984         for (i = n - 1; i >= 0; --i) {
1985                 ainfo = cinfo->args + i;
1986
1987                 in = call->args [i];
1988
1989                 switch (ainfo->storage) {
1990                 case ArgInIReg:
1991                         /* Already done */
1992                         break;
1993                 case ArgInFloatSSEReg:
1994                 case ArgInDoubleSSEReg:
1995                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1996                         break;
1997                 case ArgOnStack:
1998                 case ArgValuetypeInReg:
1999                 case ArgValuetypeAddrInIReg:
2000                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2001                                 MonoInst *call_inst = (MonoInst*)call;
2002                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2003                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2004                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2005                                 guint32 align;
2006                                 guint32 size;
2007
2008                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2009                                         size = sizeof (MonoTypedRef);
2010                                         align = sizeof (gpointer);
2011                                 }
2012                                 else {
2013                                         if (sig->pinvoke)
2014                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2015                                         else {
2016                                                 /*
2017                                                  * Other backends use mono_type_stack_size (), but that
2018                                                  * aligns the size to 8, which is larger than the size of
2019                                                  * the source, leading to reads of invalid memory if the
2020                                                  * source is at the end of address space.
2021                                                  */
2022                                                 size = mono_class_value_size (in->klass, &align);
2023                                         }
2024                                 }
2025                                 g_assert (in->klass);
2026
2027                                 if (size > 0) {
2028                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2029                                         arg->sreg1 = in->dreg;
2030                                         arg->klass = in->klass;
2031                                         arg->backend.size = size;
2032                                         arg->inst_p0 = call;
2033                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2034                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2035
2036                                         MONO_ADD_INS (cfg->cbb, arg);
2037                                 }
2038                         } else {
2039                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2040                                 arg->sreg1 = in->dreg;
2041                                 if (!sig->params [i - sig->hasthis]->byref) {
2042                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2043                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2044                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2045                                                 arg->inst_destbasereg = X86_ESP;
2046                                                 arg->inst_offset = 0;
2047                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2048                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2049                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2050                                                 arg->inst_destbasereg = X86_ESP;
2051                                                 arg->inst_offset = 0;
2052                                         }
2053                                 }
2054                                 MONO_ADD_INS (cfg->cbb, arg);
2055                         }
2056                         break;
2057                 default:
2058                         g_assert_not_reached ();
2059                 }
2060
2061                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2062                         /* Emit the signature cookie just before the implicit arguments */
2063                         emit_sig_cookie2 (cfg, call, cinfo);
2064                 }
2065         }
2066
2067         /* Handle the case where there are no implicit arguments */
2068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2069                 emit_sig_cookie2 (cfg, call, cinfo);
2070         }
2071
2072         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2073                 MonoInst *vtarg;
2074
2075                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2076                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2077                                 /*
2078                                  * Tell the JIT to use a more efficient calling convention: call using
2079                                  * OP_CALL, compute the result location after the call, and save the
2080                                  * result there.
2081                                  */
2082                                 call->vret_in_reg = TRUE;
2083                                 /*
2084                                  * Nullify the instruction computing the vret addr to enable
2085                                  * future optimizations.
2086                                  */
2087                                 if (call->vret_var)
2088                                         NULLIFY_INS (call->vret_var);
2089                         } else {
2090                                 if (call->tail_call)
2091                                         NOT_IMPLEMENTED;
2092                                 /*
2093                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2094                                  * the stack. Push the address here, so the call instruction can
2095                                  * access it.
2096                                  */
2097                                 if (!cfg->arch.vret_addr_loc) {
2098                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2099                                         /* Prevent it from being register allocated or optimized away */
2100                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2101                                 }
2102
2103                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2104                         }
2105                 }
2106                 else {
2107                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2108                         vtarg->sreg1 = call->vret_var->dreg;
2109                         vtarg->dreg = mono_alloc_preg (cfg);
2110                         MONO_ADD_INS (cfg->cbb, vtarg);
2111
2112                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2113                 }
2114         }
2115
2116 #ifdef PLATFORM_WIN32
2117         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2118                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2119         }
2120 #endif
2121
2122         if (cfg->method->save_lmf) {
2123                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2124                 MONO_ADD_INS (cfg->cbb, arg);
2125         }
2126
2127         call->stack_usage = cinfo->stack_usage;
2128 }
2129
2130 void
2131 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2132 {
2133         MonoInst *arg;
2134         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2135         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2136         int size = ins->backend.size;
2137
2138         if (ainfo->storage == ArgValuetypeInReg) {
2139                 MonoInst *load;
2140                 int part;
2141
2142                 for (part = 0; part < 2; ++part) {
2143                         if (ainfo->pair_storage [part] == ArgNone)
2144                                 continue;
2145
2146                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2147                         load->inst_basereg = src->dreg;
2148                         load->inst_offset = part * sizeof (gpointer);
2149
2150                         switch (ainfo->pair_storage [part]) {
2151                         case ArgInIReg:
2152                                 load->dreg = mono_alloc_ireg (cfg);
2153                                 break;
2154                         case ArgInDoubleSSEReg:
2155                         case ArgInFloatSSEReg:
2156                                 load->dreg = mono_alloc_freg (cfg);
2157                                 break;
2158                         default:
2159                                 g_assert_not_reached ();
2160                         }
2161                         MONO_ADD_INS (cfg->cbb, load);
2162
2163                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2164                 }
2165         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2166                 MonoInst *vtaddr, *load;
2167                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2168
2169                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2170                 load->inst_p0 = vtaddr;
2171                 vtaddr->flags |= MONO_INST_INDIRECT;
2172                 load->type = STACK_MP;
2173                 load->klass = vtaddr->klass;
2174                 load->dreg = mono_alloc_ireg (cfg);
2175                 MONO_ADD_INS (cfg->cbb, load);
2176                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2177
2178                 if (ainfo->pair_storage [0] == ArgInIReg) {
2179                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2180                         arg->dreg = mono_alloc_ireg (cfg);
2181                         arg->sreg1 = load->dreg;
2182                         arg->inst_imm = 0;
2183                         MONO_ADD_INS (cfg->cbb, arg);
2184                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2185                 } else {
2186                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2187                         arg->sreg1 = load->dreg;
2188                         MONO_ADD_INS (cfg->cbb, arg);
2189                 }
2190         } else {
2191                 if (size == 8) {
2192                         /* Can't use this for < 8 since it does an 8 byte memory load */
2193                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2194                         arg->inst_basereg = src->dreg;
2195                         arg->inst_offset = 0;
2196                         MONO_ADD_INS (cfg->cbb, arg);
2197                 } else if (size <= 40) {
2198                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2199                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2200                 } else {
2201                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2202                         arg->inst_basereg = src->dreg;
2203                         arg->inst_offset = 0;
2204                         arg->inst_imm = size;
2205                         MONO_ADD_INS (cfg->cbb, arg);
2206                 }
2207         }
2208 }
2209
2210 void
2211 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2212 {
2213         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2214
2215         if (!ret->byref) {
2216                 if (ret->type == MONO_TYPE_R4) {
2217                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2218                         return;
2219                 } else if (ret->type == MONO_TYPE_R8) {
2220                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2221                         return;
2222                 }
2223         }
2224
2225         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2226 }
2227
2228 #define EMIT_COND_BRANCH(ins,cond,sign) \
2229 if (ins->flags & MONO_INST_BRLABEL) { \
2230         if (ins->inst_i0->inst_c0) { \
2231                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2232         } else { \
2233                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2234                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2235                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2236                         x86_branch8 (code, cond, 0, sign); \
2237                 else \
2238                         x86_branch32 (code, cond, 0, sign); \
2239         } \
2240 } else { \
2241         if (ins->inst_true_bb->native_offset) { \
2242                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2243         } else { \
2244                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2245                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2246                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2247                         x86_branch8 (code, cond, 0, sign); \
2248                 else \
2249                         x86_branch32 (code, cond, 0, sign); \
2250         } \
2251 }
2252
2253 /* emit an exception if condition is fail */
2254 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2255         do {                                                        \
2256                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2257                 if (tins == NULL) {                                                                             \
2258                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2259                                         MONO_PATCH_INFO_EXC, exc_name);  \
2260                         x86_branch32 (code, cond, 0, signed);               \
2261                 } else {        \
2262                         EMIT_COND_BRANCH (tins, cond, signed);  \
2263                 }                       \
2264         } while (0);
2265
2266 #define EMIT_FPCOMPARE(code) do { \
2267         amd64_fcompp (code); \
2268         amd64_fnstsw (code); \
2269 } while (0);
2270
2271 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2272     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2273         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2274         amd64_ ##op (code); \
2275         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2276         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2277 } while (0);
2278
2279 static guint8*
2280 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2281 {
2282         gboolean no_patch = FALSE;
2283
2284         /*
2285          * FIXME: Add support for thunks
2286          */
2287         {
2288                 gboolean near_call = FALSE;
2289
2290                 /*
2291                  * Indirect calls are expensive so try to make a near call if possible.
2292                  * The caller memory is allocated by the code manager so it is
2293                  * guaranteed to be at a 32 bit offset.
2294                  */
2295
2296                 if (patch_type != MONO_PATCH_INFO_ABS) {
2297                         /* The target is in memory allocated using the code manager */
2298                         near_call = TRUE;
2299
2300                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2301                                 if (((MonoMethod*)data)->klass->image->aot_module)
2302                                         /* The callee might be an AOT method */
2303                                         near_call = FALSE;
2304                                 if (((MonoMethod*)data)->dynamic)
2305                                         /* The target is in malloc-ed memory */
2306                                         near_call = FALSE;
2307                         }
2308
2309                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2310                                 /*
2311                                  * The call might go directly to a native function without
2312                                  * the wrapper.
2313                                  */
2314                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2315                                 if (mi) {
2316                                         gconstpointer target = mono_icall_get_wrapper (mi);
2317                                         if ((((guint64)target) >> 32) != 0)
2318                                                 near_call = FALSE;
2319                                 }
2320                         }
2321                 }
2322                 else {
2323                         if (!cfg->new_ir && mono_find_class_init_trampoline_by_addr (data))
2324                                 near_call = TRUE;
2325                         else if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2326                                 /*
2327                                  * This is not really an optimization, but required because the
2328                                  * generic class init trampolines use R11 to pass the vtable.
2329                                  */
2330                                 near_call = TRUE;
2331                         } else {
2332                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2333                                 if (info) {
2334                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2335                                                 strstr (cfg->method->name, info->name)) {
2336                                                 /* A call to the wrapped function */
2337                                                 if ((((guint64)data) >> 32) == 0)
2338                                                         near_call = TRUE;
2339                                                 no_patch = TRUE;
2340                                         }
2341                                         else if (info->func == info->wrapper) {
2342                                                 /* No wrapper */
2343                                                 if ((((guint64)info->func) >> 32) == 0)
2344                                                         near_call = TRUE;
2345                                         }
2346                                         else {
2347                                                 /* See the comment in mono_codegen () */
2348                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2349                                                         near_call = TRUE;
2350                                         }
2351                                 }
2352                                 else if ((((guint64)data) >> 32) == 0) {
2353                                         near_call = TRUE;
2354                                         no_patch = TRUE;
2355                                 }
2356                         }
2357                 }
2358
2359                 if (cfg->method->dynamic)
2360                         /* These methods are allocated using malloc */
2361                         near_call = FALSE;
2362
2363                 if (cfg->compile_aot) {
2364                         near_call = TRUE;
2365                         no_patch = TRUE;
2366                 }
2367
2368 #ifdef MONO_ARCH_NOMAP32BIT
2369                 near_call = FALSE;
2370 #endif
2371
2372                 if (near_call) {
2373                         /*
2374                          * Align the call displacement to an address divisible by 4 so it does
2375                          * not span cache lines. This is required for code patching to work on SMP
2376                          * systems.
2377                          */
2378                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2379                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2380                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2381                         amd64_call_code (code, 0);
2382                 }
2383                 else {
2384                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2385                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2386                         amd64_call_reg (code, GP_SCRATCH_REG);
2387                 }
2388         }
2389
2390         return code;
2391 }
2392
2393 static inline guint8*
2394 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2395 {
2396 #ifdef PLATFORM_WIN32
2397         if (win64_adjust_stack)
2398                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2399 #endif
2400         code = emit_call_body (cfg, code, patch_type, data);
2401 #ifdef PLATFORM_WIN32
2402         if (win64_adjust_stack)
2403                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2404 #endif
2405
2406         return code;
2407 }
2408
2409 static inline int
2410 store_membase_imm_to_store_membase_reg (int opcode)
2411 {
2412         switch (opcode) {
2413         case OP_STORE_MEMBASE_IMM:
2414                 return OP_STORE_MEMBASE_REG;
2415         case OP_STOREI4_MEMBASE_IMM:
2416                 return OP_STOREI4_MEMBASE_REG;
2417         case OP_STOREI8_MEMBASE_IMM:
2418                 return OP_STOREI8_MEMBASE_REG;
2419         }
2420
2421         return -1;
2422 }
2423
2424 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2425
2426 /*
2427  * mono_arch_peephole_pass_1:
2428  *
2429  *   Perform peephole opts which should/can be performed before local regalloc
2430  */
2431 void
2432 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2433 {
2434         MonoInst *ins, *n;
2435
2436         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2437                 MonoInst *last_ins = ins->prev;
2438
2439                 switch (ins->opcode) {
2440                 case OP_ADD_IMM:
2441                 case OP_IADD_IMM:
2442                 case OP_LADD_IMM:
2443                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2444                                 /*
2445                                  * X86_LEA is like ADD, but doesn't have the
2446                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2447                                  * its operand to 64 bit.
2448                                  */
2449                                 ins->opcode = OP_X86_LEA_MEMBASE;
2450                                 ins->inst_basereg = ins->sreg1;
2451                         }
2452                         break;
2453                 case OP_LXOR:
2454                 case OP_IXOR:
2455                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2456                                 MonoInst *ins2;
2457
2458                                 /*
2459                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2460                                  * the latter has length 2-3 instead of 6 (reverse constant
2461                                  * propagation). These instruction sequences are very common
2462                                  * in the initlocals bblock.
2463                                  */
2464                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2465                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2466                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2467                                                 ins2->sreg1 = ins->dreg;
2468                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2469                                                 /* Continue */
2470                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2471                                                 NULLIFY_INS (ins2);
2472                                                 /* Continue */
2473                                         } else {
2474                                                 break;
2475                                         }
2476                                 }
2477                         }
2478                         break;
2479                 case OP_COMPARE_IMM:
2480                 case OP_LCOMPARE_IMM:
2481                         /* OP_COMPARE_IMM (reg, 0)
2482                          * -->
2483                          * OP_AMD64_TEST_NULL (reg)
2484                          */
2485                         if (!ins->inst_imm)
2486                                 ins->opcode = OP_AMD64_TEST_NULL;
2487                         break;
2488                 case OP_ICOMPARE_IMM:
2489                         if (!ins->inst_imm)
2490                                 ins->opcode = OP_X86_TEST_NULL;
2491                         break;
2492                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2493                         /*
2494                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2495                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2496                          * -->
2497                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2498                          * OP_COMPARE_IMM reg, imm
2499                          *
2500                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2501                          */
2502                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2503                             ins->inst_basereg == last_ins->inst_destbasereg &&
2504                             ins->inst_offset == last_ins->inst_offset) {
2505                                         ins->opcode = OP_ICOMPARE_IMM;
2506                                         ins->sreg1 = last_ins->sreg1;
2507
2508                                         /* check if we can remove cmp reg,0 with test null */
2509                                         if (!ins->inst_imm)
2510                                                 ins->opcode = OP_X86_TEST_NULL;
2511                                 }
2512
2513                         break;
2514                 }
2515
2516                 mono_peephole_ins (bb, ins);
2517         }
2518 }
2519
2520 void
2521 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2522 {
2523         MonoInst *ins, *n;
2524
2525         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2526                 switch (ins->opcode) {
2527                 case OP_ICONST:
2528                 case OP_I8CONST: {
2529                         /* reg = 0 -> XOR (reg, reg) */
2530                         /* XOR sets cflags on x86, so we cant do it always */
2531                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2532                                 ins->opcode = OP_LXOR;
2533                                 ins->sreg1 = ins->dreg;
2534                                 ins->sreg2 = ins->dreg;
2535                                 /* Fall through */
2536                         } else {
2537                                 break;
2538                         }
2539                 }
2540                 case OP_LXOR:
2541                         /*
2542                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2543                          * 0 result into 64 bits.
2544                          */
2545                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2546                                 ins->opcode = OP_IXOR;
2547                         }
2548                         /* Fall through */
2549                 case OP_IXOR:
2550                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2551                                 MonoInst *ins2;
2552
2553                                 /*
2554                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2555                                  * the latter has length 2-3 instead of 6 (reverse constant
2556                                  * propagation). These instruction sequences are very common
2557                                  * in the initlocals bblock.
2558                                  */
2559                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2560                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2561                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2562                                                 ins2->sreg1 = ins->dreg;
2563                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2564                                                 /* Continue */
2565                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2566                                                 NULLIFY_INS (ins2);
2567                                                 /* Continue */
2568                                         } else {
2569                                                 break;
2570                                         }
2571                                 }
2572                         }
2573                         break;
2574                 case OP_IADD_IMM:
2575                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2576                                 ins->opcode = OP_X86_INC_REG;
2577                         break;
2578                 case OP_ISUB_IMM:
2579                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2580                                 ins->opcode = OP_X86_DEC_REG;
2581                         break;
2582                 }
2583
2584                 mono_peephole_ins (bb, ins);
2585         }
2586 }
2587
2588 #define NEW_INS(cfg,ins,dest,op) do {   \
2589                 MONO_INST_NEW ((cfg), (dest), (op)); \
2590         (dest)->cil_code = (ins)->cil_code; \
2591         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2592         } while (0)
2593
2594 /*
2595  * mono_arch_lowering_pass:
2596  *
2597  *  Converts complex opcodes into simpler ones so that each IR instruction
2598  * corresponds to one machine instruction.
2599  */
2600 void
2601 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2602 {
2603         MonoInst *ins, *n, *temp;
2604
2605         if (bb->max_vreg > cfg->rs->next_vreg)
2606                 cfg->rs->next_vreg = bb->max_vreg;
2607
2608         /*
2609          * FIXME: Need to add more instructions, but the current machine
2610          * description can't model some parts of the composite instructions like
2611          * cdq.
2612          */
2613         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2614                 switch (ins->opcode) {
2615                 case OP_DIV_IMM:
2616                 case OP_REM_IMM:
2617                 case OP_IDIV_IMM:
2618                 case OP_IDIV_UN_IMM:
2619                 case OP_IREM_UN_IMM:
2620                         mono_decompose_op_imm (cfg, bb, ins);
2621                         break;
2622                 case OP_IREM_IMM:
2623                         /* Keep the opcode if we can implement it efficiently */
2624                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2625                                 mono_decompose_op_imm (cfg, bb, ins);
2626                         break;
2627                 case OP_COMPARE_IMM:
2628                 case OP_LCOMPARE_IMM:
2629                         if (!amd64_is_imm32 (ins->inst_imm)) {
2630                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2631                                 temp->inst_c0 = ins->inst_imm;
2632                                 if (cfg->globalra)
2633                                         temp->dreg = mono_alloc_ireg (cfg);
2634                                 else
2635                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2636                                 ins->opcode = OP_COMPARE;
2637                                 ins->sreg2 = temp->dreg;
2638                         }
2639                         break;
2640                 case OP_LOAD_MEMBASE:
2641                 case OP_LOADI8_MEMBASE:
2642                         if (!amd64_is_imm32 (ins->inst_offset)) {
2643                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2644                                 temp->inst_c0 = ins->inst_offset;
2645                                 if (cfg->globalra)
2646                                         temp->dreg = mono_alloc_ireg (cfg);
2647                                 else
2648                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2649                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2650                                 ins->inst_indexreg = temp->dreg;
2651                         }
2652                         break;
2653                 case OP_STORE_MEMBASE_IMM:
2654                 case OP_STOREI8_MEMBASE_IMM:
2655                         if (!amd64_is_imm32 (ins->inst_imm)) {
2656                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2657                                 temp->inst_c0 = ins->inst_imm;
2658                                 if (cfg->globalra)
2659                                         temp->dreg = mono_alloc_ireg (cfg);
2660                                 else
2661                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2662                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2663                                 ins->sreg1 = temp->dreg;
2664                         }
2665                         break;
2666                 default:
2667                         break;
2668                 }
2669         }
2670
2671         bb->max_vreg = cfg->rs->next_vreg;
2672 }
2673
2674 static const int
2675 branch_cc_table [] = {
2676         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2677         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2678         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2679 };
2680
2681 /* Maps CMP_... constants to X86_CC_... constants */
2682 static const int
2683 cc_table [] = {
2684         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2685         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2686 };
2687
2688 static const int
2689 cc_signed_table [] = {
2690         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2691         FALSE, FALSE, FALSE, FALSE
2692 };
2693
2694 /*#include "cprop.c"*/
2695
2696 static unsigned char*
2697 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2698 {
2699         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2700
2701         if (size == 1)
2702                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2703         else if (size == 2)
2704                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2705         return code;
2706 }
2707
2708 static unsigned char*
2709 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2710 {
2711         int sreg = tree->sreg1;
2712         int need_touch = FALSE;
2713
2714 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2715         if (!tree->flags & MONO_INST_INIT)
2716                 need_touch = TRUE;
2717 #endif
2718
2719         if (need_touch) {
2720                 guint8* br[5];
2721
2722                 /*
2723                  * Under Windows:
2724                  * If requested stack size is larger than one page,
2725                  * perform stack-touch operation
2726                  */
2727                 /*
2728                  * Generate stack probe code.
2729                  * Under Windows, it is necessary to allocate one page at a time,
2730                  * "touching" stack after each successful sub-allocation. This is
2731                  * because of the way stack growth is implemented - there is a
2732                  * guard page before the lowest stack page that is currently commited.
2733                  * Stack normally grows sequentially so OS traps access to the
2734                  * guard page and commits more pages when needed.
2735                  */
2736                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2737                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2738
2739                 br[2] = code; /* loop */
2740                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2741                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2742                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2743                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2744                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2745                 amd64_patch (br[3], br[2]);
2746                 amd64_test_reg_reg (code, sreg, sreg);
2747                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2748                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2749
2750                 br[1] = code; x86_jump8 (code, 0);
2751
2752                 amd64_patch (br[0], code);
2753                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2754                 amd64_patch (br[1], code);
2755                 amd64_patch (br[4], code);
2756         }
2757         else
2758                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2759
2760         if (tree->flags & MONO_INST_INIT) {
2761                 int offset = 0;
2762                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2763                         amd64_push_reg (code, AMD64_RAX);
2764                         offset += 8;
2765                 }
2766                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2767                         amd64_push_reg (code, AMD64_RCX);
2768                         offset += 8;
2769                 }
2770                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2771                         amd64_push_reg (code, AMD64_RDI);
2772                         offset += 8;
2773                 }
2774
2775                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2776                 if (sreg != AMD64_RCX)
2777                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2778                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2779
2780                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2781                 amd64_cld (code);
2782                 amd64_prefix (code, X86_REP_PREFIX);
2783                 amd64_stosl (code);
2784
2785                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2786                         amd64_pop_reg (code, AMD64_RDI);
2787                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2788                         amd64_pop_reg (code, AMD64_RCX);
2789                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2790                         amd64_pop_reg (code, AMD64_RAX);
2791         }
2792         return code;
2793 }
2794
2795 static guint8*
2796 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2797 {
2798         CallInfo *cinfo;
2799         guint32 quad;
2800
2801         /* Move return value to the target register */
2802         /* FIXME: do this in the local reg allocator */
2803         switch (ins->opcode) {
2804         case OP_CALL:
2805         case OP_CALL_REG:
2806         case OP_CALL_MEMBASE:
2807         case OP_LCALL:
2808         case OP_LCALL_REG:
2809         case OP_LCALL_MEMBASE:
2810                 g_assert (ins->dreg == AMD64_RAX);
2811                 break;
2812         case OP_FCALL:
2813         case OP_FCALL_REG:
2814         case OP_FCALL_MEMBASE:
2815                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2816                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2817                 }
2818                 else {
2819                         if (ins->dreg != AMD64_XMM0)
2820                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2821                 }
2822                 break;
2823         case OP_VCALL:
2824         case OP_VCALL_REG:
2825         case OP_VCALL_MEMBASE:
2826         case OP_VCALL2:
2827         case OP_VCALL2_REG:
2828         case OP_VCALL2_MEMBASE:
2829                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2830                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2831                         MonoInst *loc = cfg->arch.vret_addr_loc;
2832
2833                         /* Load the destination address */
2834                         g_assert (loc->opcode == OP_REGOFFSET);
2835                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2836
2837                         for (quad = 0; quad < 2; quad ++) {
2838                                 switch (cinfo->ret.pair_storage [quad]) {
2839                                 case ArgInIReg:
2840                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2841                                         break;
2842                                 case ArgInFloatSSEReg:
2843                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2844                                         break;
2845                                 case ArgInDoubleSSEReg:
2846                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2847                                         break;
2848                                 case ArgNone:
2849                                         break;
2850                                 default:
2851                                         NOT_IMPLEMENTED;
2852                                 }
2853                         }
2854                 }
2855                 break;
2856         }
2857
2858         return code;
2859 }
2860
2861 /*
2862  * mono_amd64_emit_tls_get:
2863  * @code: buffer to store code to
2864  * @dreg: hard register where to place the result
2865  * @tls_offset: offset info
2866  *
2867  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2868  * the dreg register the item in the thread local storage identified
2869  * by tls_offset.
2870  *
2871  * Returns: a pointer to the end of the stored code
2872  */
2873 guint8*
2874 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2875 {
2876 #ifdef PLATFORM_WIN32
2877         g_assert (tls_offset < 64);
2878         x86_prefix (code, X86_GS_PREFIX);
2879         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2880 #else
2881         if (optimize_for_xen) {
2882                 x86_prefix (code, X86_FS_PREFIX);
2883                 amd64_mov_reg_mem (code, dreg, 0, 8);
2884                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2885         } else {
2886                 x86_prefix (code, X86_FS_PREFIX);
2887                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2888         }
2889 #endif
2890         return code;
2891 }
2892
2893 /*
2894  * emit_load_volatile_arguments:
2895  *
2896  *  Load volatile arguments from the stack to the original input registers.
2897  * Required before a tail call.
2898  */
2899 static guint8*
2900 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2901 {
2902         MonoMethod *method = cfg->method;
2903         MonoMethodSignature *sig;
2904         MonoInst *ins;
2905         CallInfo *cinfo;
2906         guint32 i, quad;
2907
2908         /* FIXME: Generate intermediate code instead */
2909
2910         sig = mono_method_signature (method);
2911
2912         cinfo = cfg->arch.cinfo;
2913
2914         /* This is the opposite of the code in emit_prolog */
2915         if (sig->ret->type != MONO_TYPE_VOID) {
2916                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2917                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2918         }
2919
2920         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2921                 ArgInfo *ainfo = cinfo->args + i;
2922                 MonoType *arg_type;
2923                 ins = cfg->args [i];
2924
2925                 if (sig->hasthis && (i == 0))
2926                         arg_type = &mono_defaults.object_class->byval_arg;
2927                 else
2928                         arg_type = sig->params [i - sig->hasthis];
2929
2930                 if (ins->opcode != OP_REGVAR) {
2931                         switch (ainfo->storage) {
2932                         case ArgInIReg: {
2933                                 guint32 size = 8;
2934
2935                                 /* FIXME: I1 etc */
2936                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2937                                 break;
2938                         }
2939                         case ArgInFloatSSEReg:
2940                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2941                                 break;
2942                         case ArgInDoubleSSEReg:
2943                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2944                                 break;
2945                         case ArgValuetypeInReg:
2946                                 for (quad = 0; quad < 2; quad ++) {
2947                                         switch (ainfo->pair_storage [quad]) {
2948                                         case ArgInIReg:
2949                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2950                                                 break;
2951                                         case ArgInFloatSSEReg:
2952                                         case ArgInDoubleSSEReg:
2953                                                 g_assert_not_reached ();
2954                                                 break;
2955                                         case ArgNone:
2956                                                 break;
2957                                         default:
2958                                                 g_assert_not_reached ();
2959                                         }
2960                                 }
2961                                 break;
2962                         case ArgValuetypeAddrInIReg:
2963                                 if (ainfo->pair_storage [0] == ArgInIReg)
2964                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2965                                 break;
2966                         default:
2967                                 break;
2968                         }
2969                 }
2970                 else {
2971                         g_assert (ainfo->storage == ArgInIReg);
2972
2973                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2974                 }
2975         }
2976
2977         return code;
2978 }
2979
2980 #define REAL_PRINT_REG(text,reg) \
2981 mono_assert (reg >= 0); \
2982 amd64_push_reg (code, AMD64_RAX); \
2983 amd64_push_reg (code, AMD64_RDX); \
2984 amd64_push_reg (code, AMD64_RCX); \
2985 amd64_push_reg (code, reg); \
2986 amd64_push_imm (code, reg); \
2987 amd64_push_imm (code, text " %d %p\n"); \
2988 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2989 amd64_call_reg (code, AMD64_RAX); \
2990 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2991 amd64_pop_reg (code, AMD64_RCX); \
2992 amd64_pop_reg (code, AMD64_RDX); \
2993 amd64_pop_reg (code, AMD64_RAX);
2994
2995 /* benchmark and set based on cpu */
2996 #define LOOP_ALIGNMENT 8
2997 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2998
2999 #ifndef DISABLE_JIT
3000
3001 void
3002 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3003 {
3004         MonoInst *ins;
3005         MonoCallInst *call;
3006         guint offset;
3007         guint8 *code = cfg->native_code + cfg->code_len;
3008         MonoInst *last_ins = NULL;
3009         guint last_offset = 0;
3010         int max_len, cpos;
3011
3012         if (cfg->opt & MONO_OPT_LOOP) {
3013                 int pad, align = LOOP_ALIGNMENT;
3014                 /* set alignment depending on cpu */
3015                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3016                         pad = align - pad;
3017                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3018                         amd64_padding (code, pad);
3019                         cfg->code_len += pad;
3020                         bb->native_offset = cfg->code_len;
3021                 }
3022         }
3023
3024         if (cfg->verbose_level > 2)
3025                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3026
3027         cpos = bb->max_offset;
3028
3029         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3030                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3031                 g_assert (!cfg->compile_aot);
3032                 cpos += 6;
3033
3034                 cov->data [bb->dfn].cil_code = bb->cil_code;
3035                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3036                 /* this is not thread save, but good enough */
3037                 amd64_inc_membase (code, AMD64_R11, 0);
3038         }
3039
3040         offset = code - cfg->native_code;
3041
3042         mono_debug_open_block (cfg, bb, offset);
3043
3044     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3045                 x86_breakpoint (code);
3046
3047         MONO_BB_FOR_EACH_INS (bb, ins) {
3048                 offset = code - cfg->native_code;
3049
3050                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3051
3052                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3053                         cfg->code_size *= 2;
3054                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3055                         code = cfg->native_code + offset;
3056                         mono_jit_stats.code_reallocs++;
3057                 }
3058
3059                 if (cfg->debug_info)
3060                         mono_debug_record_line_number (cfg, ins, offset);
3061
3062                 switch (ins->opcode) {
3063                 case OP_BIGMUL:
3064                         amd64_mul_reg (code, ins->sreg2, TRUE);
3065                         break;
3066                 case OP_BIGMUL_UN:
3067                         amd64_mul_reg (code, ins->sreg2, FALSE);
3068                         break;
3069                 case OP_X86_SETEQ_MEMBASE:
3070                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3071                         break;
3072                 case OP_STOREI1_MEMBASE_IMM:
3073                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3074                         break;
3075                 case OP_STOREI2_MEMBASE_IMM:
3076                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3077                         break;
3078                 case OP_STOREI4_MEMBASE_IMM:
3079                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3080                         break;
3081                 case OP_STOREI1_MEMBASE_REG:
3082                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3083                         break;
3084                 case OP_STOREI2_MEMBASE_REG:
3085                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3086                         break;
3087                 case OP_STORE_MEMBASE_REG:
3088                 case OP_STOREI8_MEMBASE_REG:
3089                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3090                         break;
3091                 case OP_STOREI4_MEMBASE_REG:
3092                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3093                         break;
3094                 case OP_STORE_MEMBASE_IMM:
3095                 case OP_STOREI8_MEMBASE_IMM:
3096                         g_assert (amd64_is_imm32 (ins->inst_imm));
3097                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3098                         break;
3099                 case OP_LOAD_MEM:
3100                 case OP_LOADI8_MEM:
3101                         // FIXME: Decompose this earlier
3102                         if (amd64_is_imm32 (ins->inst_imm))
3103                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3104                         else {
3105                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3106                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3107                         }
3108                         break;
3109                 case OP_LOADI4_MEM:
3110                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3111                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3112                         break;
3113                 case OP_LOADU4_MEM:
3114                         // FIXME: Decompose this earlier
3115                         if (cfg->new_ir) {
3116                                 if (amd64_is_imm32 (ins->inst_imm))
3117                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3118                                 else {
3119                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3120                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3121                                 }
3122                         } else {
3123                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3124                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3125                         }
3126                         break;
3127                 case OP_LOADU1_MEM:
3128                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3129                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3130                         break;
3131                 case OP_LOADU2_MEM:
3132                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3133                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3134                         break;
3135                 case OP_LOAD_MEMBASE:
3136                 case OP_LOADI8_MEMBASE:
3137                         g_assert (amd64_is_imm32 (ins->inst_offset));
3138                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3139                         break;
3140                 case OP_LOADI4_MEMBASE:
3141                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3142                         break;
3143                 case OP_LOADU4_MEMBASE:
3144                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3145                         break;
3146                 case OP_LOADU1_MEMBASE:
3147                         /* The cpu zero extends the result into 64 bits */
3148                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3149                         break;
3150                 case OP_LOADI1_MEMBASE:
3151                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3152                         break;
3153                 case OP_LOADU2_MEMBASE:
3154                         /* The cpu zero extends the result into 64 bits */
3155                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3156                         break;
3157                 case OP_LOADI2_MEMBASE:
3158                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3159                         break;
3160                 case OP_AMD64_LOADI8_MEMINDEX:
3161                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3162                         break;
3163                 case OP_LCONV_TO_I1:
3164                 case OP_ICONV_TO_I1:
3165                 case OP_SEXT_I1:
3166                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3167                         break;
3168                 case OP_LCONV_TO_I2:
3169                 case OP_ICONV_TO_I2:
3170                 case OP_SEXT_I2:
3171                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3172                         break;
3173                 case OP_LCONV_TO_U1:
3174                 case OP_ICONV_TO_U1:
3175                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3176                         break;
3177                 case OP_LCONV_TO_U2:
3178                 case OP_ICONV_TO_U2:
3179                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3180                         break;
3181                 case OP_ZEXT_I4:
3182                         /* Clean out the upper word */
3183                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3184                         break;
3185                 case OP_SEXT_I4:
3186                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3187                         break;
3188                 case OP_COMPARE:
3189                 case OP_LCOMPARE:
3190                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3191                         break;
3192                 case OP_COMPARE_IMM:
3193                 case OP_LCOMPARE_IMM:
3194                         g_assert (amd64_is_imm32 (ins->inst_imm));
3195                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3196                         break;
3197                 case OP_X86_COMPARE_REG_MEMBASE:
3198                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3199                         break;
3200                 case OP_X86_TEST_NULL:
3201                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3202                         break;
3203                 case OP_AMD64_TEST_NULL:
3204                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3205                         break;
3206
3207                 case OP_X86_ADD_REG_MEMBASE:
3208                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3209                         break;
3210                 case OP_X86_SUB_REG_MEMBASE:
3211                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3212                         break;
3213                 case OP_X86_AND_REG_MEMBASE:
3214                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3215                         break;
3216                 case OP_X86_OR_REG_MEMBASE:
3217                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3218                         break;
3219                 case OP_X86_XOR_REG_MEMBASE:
3220                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3221                         break;
3222
3223                 case OP_X86_ADD_MEMBASE_IMM:
3224                         /* FIXME: Make a 64 version too */
3225                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3226                         break;
3227                 case OP_X86_SUB_MEMBASE_IMM:
3228                         g_assert (amd64_is_imm32 (ins->inst_imm));
3229                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3230                         break;
3231                 case OP_X86_AND_MEMBASE_IMM:
3232                         g_assert (amd64_is_imm32 (ins->inst_imm));
3233                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3234                         break;
3235                 case OP_X86_OR_MEMBASE_IMM:
3236                         g_assert (amd64_is_imm32 (ins->inst_imm));
3237                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3238                         break;
3239                 case OP_X86_XOR_MEMBASE_IMM:
3240                         g_assert (amd64_is_imm32 (ins->inst_imm));
3241                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3242                         break;
3243                 case OP_X86_ADD_MEMBASE_REG:
3244                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3245                         break;
3246                 case OP_X86_SUB_MEMBASE_REG:
3247                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3248                         break;
3249                 case OP_X86_AND_MEMBASE_REG:
3250                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3251                         break;
3252                 case OP_X86_OR_MEMBASE_REG:
3253                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3254                         break;
3255                 case OP_X86_XOR_MEMBASE_REG:
3256                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3257                         break;
3258                 case OP_X86_INC_MEMBASE:
3259                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3260                         break;
3261                 case OP_X86_INC_REG:
3262                         amd64_inc_reg_size (code, ins->dreg, 4);
3263                         break;
3264                 case OP_X86_DEC_MEMBASE:
3265                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3266                         break;
3267                 case OP_X86_DEC_REG:
3268                         amd64_dec_reg_size (code, ins->dreg, 4);
3269                         break;
3270                 case OP_X86_MUL_REG_MEMBASE:
3271                 case OP_X86_MUL_MEMBASE_REG:
3272                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3273                         break;
3274                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3275                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3276                         break;
3277                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3278                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3279                         break;
3280                 case OP_AMD64_COMPARE_MEMBASE_REG:
3281                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3282                         break;
3283                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3284                         g_assert (amd64_is_imm32 (ins->inst_imm));
3285                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3286                         break;
3287                 case OP_X86_COMPARE_MEMBASE8_IMM:
3288                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3289                         break;
3290                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3291                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3292                         break;
3293                 case OP_AMD64_COMPARE_REG_MEMBASE:
3294                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3295                         break;
3296
3297                 case OP_AMD64_ADD_REG_MEMBASE:
3298                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3299                         break;
3300                 case OP_AMD64_SUB_REG_MEMBASE:
3301                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3302                         break;
3303                 case OP_AMD64_AND_REG_MEMBASE:
3304                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3305                         break;
3306                 case OP_AMD64_OR_REG_MEMBASE:
3307                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3308                         break;
3309                 case OP_AMD64_XOR_REG_MEMBASE:
3310                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3311                         break;
3312
3313                 case OP_AMD64_ADD_MEMBASE_REG:
3314                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3315                         break;
3316                 case OP_AMD64_SUB_MEMBASE_REG:
3317                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3318                         break;
3319                 case OP_AMD64_AND_MEMBASE_REG:
3320                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3321                         break;
3322                 case OP_AMD64_OR_MEMBASE_REG:
3323                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3324                         break;
3325                 case OP_AMD64_XOR_MEMBASE_REG:
3326                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3327                         break;
3328
3329                 case OP_AMD64_ADD_MEMBASE_IMM:
3330                         g_assert (amd64_is_imm32 (ins->inst_imm));
3331                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3332                         break;
3333                 case OP_AMD64_SUB_MEMBASE_IMM:
3334                         g_assert (amd64_is_imm32 (ins->inst_imm));
3335                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3336                         break;
3337                 case OP_AMD64_AND_MEMBASE_IMM:
3338                         g_assert (amd64_is_imm32 (ins->inst_imm));
3339                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3340                         break;
3341                 case OP_AMD64_OR_MEMBASE_IMM:
3342                         g_assert (amd64_is_imm32 (ins->inst_imm));
3343                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3344                         break;
3345                 case OP_AMD64_XOR_MEMBASE_IMM:
3346                         g_assert (amd64_is_imm32 (ins->inst_imm));
3347                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3348                         break;
3349
3350                 case OP_BREAK:
3351                         amd64_breakpoint (code);
3352                         break;
3353                 case OP_RELAXED_NOP:
3354                         x86_prefix (code, X86_REP_PREFIX);
3355                         x86_nop (code);
3356                         break;
3357                 case OP_HARD_NOP:
3358                         x86_nop (code);
3359                         break;
3360                 case OP_NOP:
3361                 case OP_DUMMY_USE:
3362                 case OP_DUMMY_STORE:
3363                 case OP_NOT_REACHED:
3364                 case OP_NOT_NULL:
3365                         break;
3366                 case OP_ADDCC:
3367                 case OP_LADD:
3368                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3369                         break;
3370                 case OP_ADC:
3371                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3372                         break;
3373                 case OP_ADD_IMM:
3374                 case OP_LADD_IMM:
3375                         g_assert (amd64_is_imm32 (ins->inst_imm));
3376                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3377                         break;
3378                 case OP_ADC_IMM:
3379                         g_assert (amd64_is_imm32 (ins->inst_imm));
3380                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3381                         break;
3382                 case OP_SUBCC:
3383                 case OP_LSUB:
3384                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3385                         break;
3386                 case OP_SBB:
3387                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3388                         break;
3389                 case OP_SUB_IMM:
3390                 case OP_LSUB_IMM:
3391                         g_assert (amd64_is_imm32 (ins->inst_imm));
3392                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3393                         break;
3394                 case OP_SBB_IMM:
3395                         g_assert (amd64_is_imm32 (ins->inst_imm));
3396                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3397                         break;
3398                 case OP_LAND:
3399                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3400                         break;
3401                 case OP_AND_IMM:
3402                 case OP_LAND_IMM:
3403                         g_assert (amd64_is_imm32 (ins->inst_imm));
3404                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3405                         break;
3406                 case OP_LMUL:
3407                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3408                         break;
3409                 case OP_MUL_IMM:
3410                 case OP_LMUL_IMM:
3411                 case OP_IMUL_IMM: {
3412                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3413
3414                         switch (ins->inst_imm) {
3415                         case 2:
3416                                 /* MOV r1, r2 */
3417                                 /* ADD r1, r1 */
3418                                 if (ins->dreg != ins->sreg1)
3419                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3420                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3421                                 break;
3422                         case 3:
3423                                 /* LEA r1, [r2 + r2*2] */
3424                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3425                                 break;
3426                         case 5:
3427                                 /* LEA r1, [r2 + r2*4] */
3428                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3429                                 break;
3430                         case 6:
3431                                 /* LEA r1, [r2 + r2*2] */
3432                                 /* ADD r1, r1          */
3433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3434                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3435                                 break;
3436                         case 9:
3437                                 /* LEA r1, [r2 + r2*8] */
3438                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3439                                 break;
3440                         case 10:
3441                                 /* LEA r1, [r2 + r2*4] */
3442                                 /* ADD r1, r1          */
3443                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3444                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3445                                 break;
3446                         case 12:
3447                                 /* LEA r1, [r2 + r2*2] */
3448                                 /* SHL r1, 2           */
3449                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3450                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3451                                 break;
3452                         case 25:
3453                                 /* LEA r1, [r2 + r2*4] */
3454                                 /* LEA r1, [r1 + r1*4] */
3455                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3456                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3457                                 break;
3458                         case 100:
3459                                 /* LEA r1, [r2 + r2*4] */
3460                                 /* SHL r1, 2           */
3461                                 /* LEA r1, [r1 + r1*4] */
3462                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3463                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3464                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3465                                 break;
3466                         default:
3467                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3468                                 break;
3469                         }
3470                         break;
3471                 }
3472                 case OP_LDIV:
3473                 case OP_LREM:
3474                         /* Regalloc magic makes the div/rem cases the same */
3475                         if (ins->sreg2 == AMD64_RDX) {
3476                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3477                                 amd64_cdq (code);
3478                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3479                         } else {
3480                                 amd64_cdq (code);
3481                                 amd64_div_reg (code, ins->sreg2, TRUE);
3482                         }
3483                         break;
3484                 case OP_LDIV_UN:
3485                 case OP_LREM_UN:
3486                         if (ins->sreg2 == AMD64_RDX) {
3487                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3488                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3489                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3490                         } else {
3491                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3492                                 amd64_div_reg (code, ins->sreg2, FALSE);
3493                         }
3494                         break;
3495                 case OP_IDIV:
3496                 case OP_IREM:
3497                         if (ins->sreg2 == AMD64_RDX) {
3498                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3499                                 amd64_cdq_size (code, 4);
3500                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3501                         } else {
3502                                 amd64_cdq_size (code, 4);
3503                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3504                         }
3505                         break;
3506                 case OP_IDIV_UN:
3507                 case OP_IREM_UN:
3508                         if (ins->sreg2 == AMD64_RDX) {
3509                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3510                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3511                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3512                         } else {
3513                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3514                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3515                         }
3516                         break;
3517                 case OP_IREM_IMM: {
3518                         int power = mono_is_power_of_two (ins->inst_imm);
3519
3520                         g_assert (ins->sreg1 == X86_EAX);
3521                         g_assert (ins->dreg == X86_EAX);
3522                         g_assert (power >= 0);
3523
3524                         /* Based on gcc code */
3525
3526                         /* Add compensation for negative dividents */
3527                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3528                         if (power > 1)
3529                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3530                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3531                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3532                         /* Compute remainder */
3533                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3534                         /* Remove compensation */
3535                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3536                         break;
3537                 }
3538                 case OP_LMUL_OVF:
3539                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3540                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3541                         break;
3542                 case OP_LOR:
3543                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3544                         break;
3545                 case OP_OR_IMM:
3546                 case OP_LOR_IMM:
3547                         g_assert (amd64_is_imm32 (ins->inst_imm));
3548                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3549                         break;
3550                 case OP_LXOR:
3551                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3552                         break;
3553                 case OP_XOR_IMM:
3554                 case OP_LXOR_IMM:
3555                         g_assert (amd64_is_imm32 (ins->inst_imm));
3556                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3557                         break;
3558                 case OP_LSHL:
3559                         g_assert (ins->sreg2 == AMD64_RCX);
3560                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3561                         break;
3562                 case OP_LSHR:
3563                         g_assert (ins->sreg2 == AMD64_RCX);
3564                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3565                         break;
3566                 case OP_SHR_IMM:
3567                         g_assert (amd64_is_imm32 (ins->inst_imm));
3568                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3569                         break;
3570                 case OP_LSHR_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3573                         break;
3574                 case OP_SHR_UN_IMM:
3575                         g_assert (amd64_is_imm32 (ins->inst_imm));
3576                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3577                         break;
3578                 case OP_LSHR_UN_IMM:
3579                         g_assert (amd64_is_imm32 (ins->inst_imm));
3580                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3581                         break;
3582                 case OP_LSHR_UN:
3583                         g_assert (ins->sreg2 == AMD64_RCX);
3584                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3585                         break;
3586                 case OP_SHL_IMM:
3587                         g_assert (amd64_is_imm32 (ins->inst_imm));
3588                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3589                         break;
3590                 case OP_LSHL_IMM:
3591                         g_assert (amd64_is_imm32 (ins->inst_imm));
3592                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3593                         break;
3594
3595                 case OP_IADDCC:
3596                 case OP_IADD:
3597                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3598                         break;
3599                 case OP_IADC:
3600                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3601                         break;
3602                 case OP_IADD_IMM:
3603                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3604                         break;
3605                 case OP_IADC_IMM:
3606                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3607                         break;
3608                 case OP_ISUBCC:
3609                 case OP_ISUB:
3610                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3611                         break;
3612                 case OP_ISBB:
3613                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3614                         break;
3615                 case OP_ISUB_IMM:
3616                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3617                         break;
3618                 case OP_ISBB_IMM:
3619                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3620                         break;
3621                 case OP_IAND:
3622                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3623                         break;
3624                 case OP_IAND_IMM:
3625                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3626                         break;
3627                 case OP_IOR:
3628                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3629                         break;
3630                 case OP_IOR_IMM:
3631                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3632                         break;
3633                 case OP_IXOR:
3634                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3635                         break;
3636                 case OP_IXOR_IMM:
3637                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3638                         break;
3639                 case OP_INEG:
3640                         amd64_neg_reg_size (code, ins->sreg1, 4);
3641                         break;
3642                 case OP_INOT:
3643                         amd64_not_reg_size (code, ins->sreg1, 4);
3644                         break;
3645                 case OP_ISHL:
3646                         g_assert (ins->sreg2 == AMD64_RCX);
3647                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3648                         break;
3649                 case OP_ISHR:
3650                         g_assert (ins->sreg2 == AMD64_RCX);
3651                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3652                         break;
3653                 case OP_ISHR_IMM:
3654                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3655                         break;
3656                 case OP_ISHR_UN_IMM:
3657                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3658                         break;
3659                 case OP_ISHR_UN:
3660                         g_assert (ins->sreg2 == AMD64_RCX);
3661                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3662                         break;
3663                 case OP_ISHL_IMM:
3664                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3665                         break;
3666                 case OP_IMUL:
3667                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3668                         break;
3669                 case OP_IMUL_OVF:
3670                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3671                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3672                         break;
3673                 case OP_IMUL_OVF_UN:
3674                 case OP_LMUL_OVF_UN: {
3675                         /* the mul operation and the exception check should most likely be split */
3676                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3677                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3678                         /*g_assert (ins->sreg2 == X86_EAX);
3679                         g_assert (ins->dreg == X86_EAX);*/
3680                         if (ins->sreg2 == X86_EAX) {
3681                                 non_eax_reg = ins->sreg1;
3682                         } else if (ins->sreg1 == X86_EAX) {
3683                                 non_eax_reg = ins->sreg2;
3684                         } else {
3685                                 /* no need to save since we're going to store to it anyway */
3686                                 if (ins->dreg != X86_EAX) {
3687                                         saved_eax = TRUE;
3688                                         amd64_push_reg (code, X86_EAX);
3689                                 }
3690                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3691                                 non_eax_reg = ins->sreg2;
3692                         }
3693                         if (ins->dreg == X86_EDX) {
3694                                 if (!saved_eax) {
3695                                         saved_eax = TRUE;
3696                                         amd64_push_reg (code, X86_EAX);
3697                                 }
3698                         } else {
3699                                 saved_edx = TRUE;
3700                                 amd64_push_reg (code, X86_EDX);
3701                         }
3702                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3703                         /* save before the check since pop and mov don't change the flags */
3704                         if (ins->dreg != X86_EAX)
3705                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3706                         if (saved_edx)
3707                                 amd64_pop_reg (code, X86_EDX);
3708                         if (saved_eax)
3709                                 amd64_pop_reg (code, X86_EAX);
3710                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3711                         break;
3712                 }
3713                 case OP_ICOMPARE:
3714                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3715                         break;
3716                 case OP_ICOMPARE_IMM:
3717                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3718                         break;
3719                 case OP_IBEQ:
3720                 case OP_IBLT:
3721                 case OP_IBGT:
3722                 case OP_IBGE:
3723                 case OP_IBLE:
3724                 case OP_LBEQ:
3725                 case OP_LBLT:
3726                 case OP_LBGT:
3727                 case OP_LBGE:
3728                 case OP_LBLE:
3729                 case OP_IBNE_UN:
3730                 case OP_IBLT_UN:
3731                 case OP_IBGT_UN:
3732                 case OP_IBGE_UN:
3733                 case OP_IBLE_UN:
3734                 case OP_LBNE_UN:
3735                 case OP_LBLT_UN:
3736                 case OP_LBGT_UN:
3737                 case OP_LBGE_UN:
3738                 case OP_LBLE_UN:
3739                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3740                         break;
3741
3742                 case OP_CMOV_IEQ:
3743                 case OP_CMOV_IGE:
3744                 case OP_CMOV_IGT:
3745                 case OP_CMOV_ILE:
3746                 case OP_CMOV_ILT:
3747                 case OP_CMOV_INE_UN:
3748                 case OP_CMOV_IGE_UN:
3749                 case OP_CMOV_IGT_UN:
3750                 case OP_CMOV_ILE_UN:
3751                 case OP_CMOV_ILT_UN:
3752                 case OP_CMOV_LEQ:
3753                 case OP_CMOV_LGE:
3754                 case OP_CMOV_LGT:
3755                 case OP_CMOV_LLE:
3756                 case OP_CMOV_LLT:
3757                 case OP_CMOV_LNE_UN:
3758                 case OP_CMOV_LGE_UN:
3759                 case OP_CMOV_LGT_UN:
3760                 case OP_CMOV_LLE_UN:
3761                 case OP_CMOV_LLT_UN:
3762                         g_assert (ins->dreg == ins->sreg1);
3763                         /* This needs to operate on 64 bit values */
3764                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3765                         break;
3766
3767                 case OP_LNOT:
3768                         amd64_not_reg (code, ins->sreg1);
3769                         break;
3770                 case OP_LNEG:
3771                         amd64_neg_reg (code, ins->sreg1);
3772                         break;
3773
3774                 case OP_ICONST:
3775                 case OP_I8CONST:
3776                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3777                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3778                         else
3779                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3780                         break;
3781                 case OP_AOTCONST:
3782                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3783                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3784                         break;
3785                 case OP_JUMP_TABLE:
3786                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3787                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3788                         break;
3789                 case OP_MOVE:
3790                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3791                         break;
3792                 case OP_AMD64_SET_XMMREG_R4: {
3793                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3794                         break;
3795                 }
3796                 case OP_AMD64_SET_XMMREG_R8: {
3797                         if (ins->dreg != ins->sreg1)
3798                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3799                         break;
3800                 }
3801                 case OP_JMP:
3802                 case OP_TAILCALL: {
3803                         /*
3804                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3805                          * Keep in sync with the code in emit_epilog.
3806                          */
3807                         int pos = 0, i;
3808
3809                         /* FIXME: no tracing support... */
3810                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3811                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3812
3813                         g_assert (!cfg->method->save_lmf);
3814
3815                         if (ins->opcode == OP_JMP)
3816                                 code = emit_load_volatile_arguments (cfg, code);
3817
3818                         if (cfg->arch.omit_fp) {
3819                                 guint32 save_offset = 0;
3820                                 /* Pop callee-saved registers */
3821                                 for (i = 0; i < AMD64_NREG; ++i)
3822                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3823                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3824                                                 save_offset += 8;
3825                                         }
3826                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3827                         }
3828                         else {
3829                                 for (i = 0; i < AMD64_NREG; ++i)
3830                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3831                                                 pos -= sizeof (gpointer);
3832
3833                                 if (pos)
3834                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3835
3836                                 /* Pop registers in reverse order */
3837                                 for (i = AMD64_NREG - 1; i > 0; --i)
3838                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3839                                                 amd64_pop_reg (code, i);
3840                                         }
3841
3842                                 amd64_leave (code);
3843                         }
3844
3845                         offset = code - cfg->native_code;
3846                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3847                         if (cfg->compile_aot)
3848                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3849                         else
3850                                 amd64_set_reg_template (code, AMD64_R11);
3851                         amd64_jump_reg (code, AMD64_R11);
3852                         break;
3853                 }
3854                 case OP_CHECK_THIS:
3855                         /* ensure ins->sreg1 is not NULL */
3856                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3857                         break;
3858                 case OP_ARGLIST: {
3859                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3860                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3861                         break;
3862                 }
3863                 case OP_CALL:
3864                 case OP_FCALL:
3865                 case OP_LCALL:
3866                 case OP_VCALL:
3867                 case OP_VCALL2:
3868                 case OP_VOIDCALL:
3869                         call = (MonoCallInst*)ins;
3870                         /*
3871                          * The AMD64 ABI forces callers to know about varargs.
3872                          */
3873                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3874                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3875                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3876                                 /*
3877                                  * Since the unmanaged calling convention doesn't contain a
3878                                  * 'vararg' entry, we have to treat every pinvoke call as a
3879                                  * potential vararg call.
3880                                  */
3881                                 guint32 nregs, i;
3882                                 nregs = 0;
3883                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3884                                         if (call->used_fregs & (1 << i))
3885                                                 nregs ++;
3886                                 if (!nregs)
3887                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3888                                 else
3889                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3890                         }
3891
3892                         if (ins->flags & MONO_INST_HAS_METHOD)
3893                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3894                         else
3895                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3896                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3897                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3898                         code = emit_move_return_value (cfg, ins, code);
3899                         break;
3900                 case OP_FCALL_REG:
3901                 case OP_LCALL_REG:
3902                 case OP_VCALL_REG:
3903                 case OP_VCALL2_REG:
3904                 case OP_VOIDCALL_REG:
3905                 case OP_CALL_REG:
3906                         call = (MonoCallInst*)ins;
3907
3908                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3909                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3910                                 ins->sreg1 = AMD64_R11;
3911                         }
3912
3913                         /*
3914                          * The AMD64 ABI forces callers to know about varargs.
3915                          */
3916                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3917                                 if (ins->sreg1 == AMD64_RAX) {
3918                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3919                                         ins->sreg1 = AMD64_R11;
3920                                 }
3921                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3922                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3923                                 /*
3924                                  * Since the unmanaged calling convention doesn't contain a
3925                                  * 'vararg' entry, we have to treat every pinvoke call as a
3926                                  * potential vararg call.
3927                                  */
3928                                 guint32 nregs, i;
3929                                 nregs = 0;
3930                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3931                                         if (call->used_fregs & (1 << i))
3932                                                 nregs ++;
3933                                 if (ins->sreg1 == AMD64_RAX) {
3934                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3935                                         ins->sreg1 = AMD64_R11;
3936                                 }
3937                                 if (!nregs)
3938                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3939                                 else
3940                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3941                         }
3942
3943                         amd64_call_reg (code, ins->sreg1);
3944                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3945                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3946                         code = emit_move_return_value (cfg, ins, code);
3947                         break;
3948                 case OP_FCALL_MEMBASE:
3949                 case OP_LCALL_MEMBASE:
3950                 case OP_VCALL_MEMBASE:
3951                 case OP_VCALL2_MEMBASE:
3952                 case OP_VOIDCALL_MEMBASE:
3953                 case OP_CALL_MEMBASE:
3954                         call = (MonoCallInst*)ins;
3955
3956                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3957                                 /*
3958                                  * Can't use R11 because it is clobbered by the trampoline
3959                                  * code, and the reg value is needed by get_vcall_slot_addr.
3960                                  */
3961                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3962                                 ins->sreg1 = AMD64_RAX;
3963                         }
3964
3965                         if (call->method && ins->inst_offset < 0) {
3966                                 gssize val;
3967
3968                                 /*
3969                                  * This is a possible IMT call so save the IMT method in the proper
3970                                  * register. We don't use the generic code in method-to-ir.c, because
3971                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3972                                  * maintain control over the layout of the code.
3973                                  * Also put the base reg in %rax to simplify find_imt_method ().
3974                                  */
3975                                 if (ins->sreg1 != AMD64_RAX) {
3976                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3977                                         ins->sreg1 = AMD64_RAX;
3978                                 }
3979                                 val = (gssize)(gpointer)call->method;
3980
3981                                 // FIXME: Generics sharing
3982 #if 0
3983                                 if ((((guint64)val) >> 32) == 0)
3984                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3985                                 else
3986                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3987 #endif
3988                         }
3989
3990                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3991                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3992                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3993                         code = emit_move_return_value (cfg, ins, code);
3994                         break;
3995                 case OP_AMD64_SAVE_SP_TO_LMF:
3996                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3997                         break;
3998                 case OP_OUTARG:
3999                 case OP_X86_PUSH:
4000                         amd64_push_reg (code, ins->sreg1);
4001                         break;
4002                 case OP_X86_PUSH_IMM:
4003                         g_assert (amd64_is_imm32 (ins->inst_imm));
4004                         amd64_push_imm (code, ins->inst_imm);
4005                         break;
4006                 case OP_X86_PUSH_MEMBASE:
4007                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4008                         break;
4009                 case OP_X86_PUSH_OBJ: {
4010                         int size = ALIGN_TO (ins->inst_imm, 8);
4011                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4012                         amd64_push_reg (code, AMD64_RDI);
4013                         amd64_push_reg (code, AMD64_RSI);
4014                         amd64_push_reg (code, AMD64_RCX);
4015                         if (ins->inst_offset)
4016                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4017                         else
4018                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4019                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4020                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4021                         amd64_cld (code);
4022                         amd64_prefix (code, X86_REP_PREFIX);
4023                         amd64_movsd (code);
4024                         amd64_pop_reg (code, AMD64_RCX);
4025                         amd64_pop_reg (code, AMD64_RSI);
4026                         amd64_pop_reg (code, AMD64_RDI);
4027                         break;
4028                 }
4029                 case OP_X86_LEA:
4030                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4031                         break;
4032                 case OP_X86_LEA_MEMBASE:
4033                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4034                         break;
4035                 case OP_X86_XCHG:
4036                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4037                         break;
4038                 case OP_LOCALLOC:
4039                         /* keep alignment */
4040                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4041                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4042                         code = mono_emit_stack_alloc (code, ins);
4043                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4044                         break;
4045                 case OP_LOCALLOC_IMM: {
4046                         guint32 size = ins->inst_imm;
4047                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4048
4049                         if (ins->flags & MONO_INST_INIT) {
4050                                 if (size < 64) {
4051                                         int i;
4052
4053                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4054                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4055
4056                                         for (i = 0; i < size; i += 8)
4057                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4058                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4059                                 } else {
4060                                         amd64_mov_reg_imm (code, ins->dreg, size);
4061                                         ins->sreg1 = ins->dreg;
4062
4063                                         code = mono_emit_stack_alloc (code, ins);
4064                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4065                                 }
4066                         } else {
4067                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4068                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4069                         }
4070                         break;
4071                 }
4072                 case OP_THROW: {
4073                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4074                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4075                                              (gpointer)"mono_arch_throw_exception", FALSE);
4076                         break;
4077                 }
4078                 case OP_RETHROW: {
4079                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4080                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4081                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4082                         break;
4083                 }
4084                 case OP_CALL_HANDLER:
4085                         /* Align stack */
4086                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4087                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4088                         amd64_call_imm (code, 0);
4089                         /* Restore stack alignment */
4090                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4091                         break;
4092                 case OP_START_HANDLER: {
4093                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4094                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4095                         break;
4096                 }
4097                 case OP_ENDFINALLY: {
4098                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4099                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4100                         amd64_ret (code);
4101                         break;
4102                 }
4103                 case OP_ENDFILTER: {
4104                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4105                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4106                         /* The local allocator will put the result into RAX */
4107                         amd64_ret (code);
4108                         break;
4109                 }
4110
4111                 case OP_LABEL:
4112                         ins->inst_c0 = code - cfg->native_code;
4113                         break;
4114                 case OP_BR:
4115                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4116                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4117                         //break;
4118                         if (ins->flags & MONO_INST_BRLABEL) {
4119                                 if (ins->inst_i0->inst_c0) {
4120                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4121                                 } else {
4122                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4123                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4124                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4125                                                 x86_jump8 (code, 0);
4126                                         else
4127                                                 x86_jump32 (code, 0);
4128                                 }
4129                         } else {
4130                                 if (ins->inst_target_bb->native_offset) {
4131                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4132                                 } else {
4133                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4134                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4135                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4136                                                 x86_jump8 (code, 0);
4137                                         else
4138                                                 x86_jump32 (code, 0);
4139                                 }
4140                         }
4141                         break;
4142                 case OP_BR_REG:
4143                         amd64_jump_reg (code, ins->sreg1);
4144                         break;
4145                 case OP_CEQ:
4146                 case OP_LCEQ:
4147                 case OP_ICEQ:
4148                 case OP_CLT:
4149                 case OP_LCLT:
4150                 case OP_ICLT:
4151                 case OP_CGT:
4152                 case OP_ICGT:
4153                 case OP_LCGT:
4154                 case OP_CLT_UN:
4155                 case OP_LCLT_UN:
4156                 case OP_ICLT_UN:
4157                 case OP_CGT_UN:
4158                 case OP_LCGT_UN:
4159                 case OP_ICGT_UN:
4160                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4161                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4162                         break;
4163                 case OP_COND_EXC_EQ:
4164                 case OP_COND_EXC_NE_UN:
4165                 case OP_COND_EXC_LT:
4166                 case OP_COND_EXC_LT_UN:
4167                 case OP_COND_EXC_GT:
4168                 case OP_COND_EXC_GT_UN:
4169                 case OP_COND_EXC_GE:
4170                 case OP_COND_EXC_GE_UN:
4171                 case OP_COND_EXC_LE:
4172                 case OP_COND_EXC_LE_UN:
4173                 case OP_COND_EXC_IEQ:
4174                 case OP_COND_EXC_INE_UN:
4175                 case OP_COND_EXC_ILT:
4176                 case OP_COND_EXC_ILT_UN:
4177                 case OP_COND_EXC_IGT:
4178                 case OP_COND_EXC_IGT_UN:
4179                 case OP_COND_EXC_IGE:
4180                 case OP_COND_EXC_IGE_UN:
4181                 case OP_COND_EXC_ILE:
4182                 case OP_COND_EXC_ILE_UN:
4183                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4184                         break;
4185                 case OP_COND_EXC_OV:
4186                 case OP_COND_EXC_NO:
4187                 case OP_COND_EXC_C:
4188                 case OP_COND_EXC_NC:
4189                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4190                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4191                         break;
4192                 case OP_COND_EXC_IOV:
4193                 case OP_COND_EXC_INO:
4194                 case OP_COND_EXC_IC:
4195                 case OP_COND_EXC_INC:
4196                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4197                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4198                         break;
4199
4200                 /* floating point opcodes */
4201                 case OP_R8CONST: {
4202                         double d = *(double *)ins->inst_p0;
4203
4204                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4205                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4206                         }
4207                         else {
4208                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4209                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4210                         }
4211                         break;
4212                 }
4213                 case OP_R4CONST: {
4214                         float f = *(float *)ins->inst_p0;
4215
4216                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4217                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4218                         }
4219                         else {
4220                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4221                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4222                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4223                         }
4224                         break;
4225                 }
4226                 case OP_STORER8_MEMBASE_REG:
4227                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4228                         break;
4229                 case OP_LOADR8_SPILL_MEMBASE:
4230                         g_assert_not_reached ();
4231                         break;
4232                 case OP_LOADR8_MEMBASE:
4233                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4234                         break;
4235                 case OP_STORER4_MEMBASE_REG:
4236                         /* This requires a double->single conversion */
4237                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4238                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4239                         break;
4240                 case OP_LOADR4_MEMBASE:
4241                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4242                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4243                         break;
4244                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4245                 case OP_ICONV_TO_R8:
4246                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4247                         break;
4248                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4249                 case OP_LCONV_TO_R8:
4250                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4251                         break;
4252                 case OP_FCONV_TO_R4:
4253                         /* FIXME: nothing to do ?? */
4254                         break;
4255                 case OP_FCONV_TO_I1:
4256                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4257                         break;
4258                 case OP_FCONV_TO_U1:
4259                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4260                         break;
4261                 case OP_FCONV_TO_I2:
4262                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4263                         break;
4264                 case OP_FCONV_TO_U2:
4265                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4266                         break;
4267                 case OP_FCONV_TO_U4:
4268                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4269                         break;
4270                 case OP_FCONV_TO_I4:
4271                 case OP_FCONV_TO_I:
4272                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4273                         break;
4274                 case OP_FCONV_TO_I8:
4275                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4276                         break;
4277                 case OP_LCONV_TO_R_UN: {
4278                         guint8 *br [2];
4279
4280                         /* Based on gcc code */
4281                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4282                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4283
4284                         /* Positive case */
4285                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4286                         br [1] = code; x86_jump8 (code, 0);
4287                         amd64_patch (br [0], code);
4288
4289                         /* Negative case */
4290                         /* Save to the red zone */
4291                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4292                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4293                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4294                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4295                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4296                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4297                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4298                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4299                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4300                         /* Restore */
4301                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4302                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4303                         amd64_patch (br [1], code);
4304                         break;
4305                 }
4306                 case OP_LCONV_TO_OVF_U4:
4307                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4308                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4309                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4310                         break;
4311                 case OP_LCONV_TO_OVF_I4_UN:
4312                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4313                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4314                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4315                         break;
4316                 case OP_FMOVE:
4317                         if (ins->dreg != ins->sreg1)
4318                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4319                         break;
4320                 case OP_FADD:
4321                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4322                         break;
4323                 case OP_FSUB:
4324                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4325                         break;
4326                 case OP_FMUL:
4327                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4328                         break;
4329                 case OP_FDIV:
4330                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4331                         break;
4332                 case OP_FNEG: {
4333                         static double r8_0 = -0.0;
4334
4335                         g_assert (ins->sreg1 == ins->dreg);
4336
4337                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4338                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4339                         break;
4340                 }
4341                 case OP_SIN:
4342                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4343                         break;
4344                 case OP_COS:
4345                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4346                         break;
4347                 case OP_ABS: {
4348                         static guint64 d = 0x7fffffffffffffffUL;
4349
4350                         g_assert (ins->sreg1 == ins->dreg);
4351
4352                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4353                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4354                         break;
4355                 }
4356                 case OP_SQRT:
4357                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4358                         break;
4359                 case OP_IMIN:
4360                         g_assert (cfg->opt & MONO_OPT_CMOV);
4361                         g_assert (ins->dreg == ins->sreg1);
4362                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4363                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4364                         break;
4365                 case OP_IMIN_UN:
4366                         g_assert (cfg->opt & MONO_OPT_CMOV);
4367                         g_assert (ins->dreg == ins->sreg1);
4368                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4369                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4370                         break;
4371                 case OP_IMAX:
4372                         g_assert (cfg->opt & MONO_OPT_CMOV);
4373                         g_assert (ins->dreg == ins->sreg1);
4374                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4375                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4376                         break;
4377                 case OP_IMAX_UN:
4378                         g_assert (cfg->opt & MONO_OPT_CMOV);
4379                         g_assert (ins->dreg == ins->sreg1);
4380                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4381                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4382                         break;
4383                 case OP_LMIN:
4384                         g_assert (cfg->opt & MONO_OPT_CMOV);
4385                         g_assert (ins->dreg == ins->sreg1);
4386                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4387                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4388                         break;
4389                 case OP_LMIN_UN:
4390                         g_assert (cfg->opt & MONO_OPT_CMOV);
4391                         g_assert (ins->dreg == ins->sreg1);
4392                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4393                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4394                         break;
4395                 case OP_LMAX:
4396                         g_assert (cfg->opt & MONO_OPT_CMOV);
4397                         g_assert (ins->dreg == ins->sreg1);
4398                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4399                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4400                         break;
4401                 case OP_LMAX_UN:
4402                         g_assert (cfg->opt & MONO_OPT_CMOV);
4403                         g_assert (ins->dreg == ins->sreg1);
4404                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4405                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4406                         break;
4407                 case OP_X86_FPOP:
4408                         break;
4409                 case OP_FCOMPARE:
4410                         /*
4411                          * The two arguments are swapped because the fbranch instructions
4412                          * depend on this for the non-sse case to work.
4413                          */
4414                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4415                         break;
4416                 case OP_FCEQ: {
4417                         /* zeroing the register at the start results in
4418                          * shorter and faster code (we can also remove the widening op)
4419                          */
4420                         guchar *unordered_check;
4421                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4422                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4423                         unordered_check = code;
4424                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4425                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4426                         amd64_patch (unordered_check, code);
4427                         break;
4428                 }
4429                 case OP_FCLT:
4430                 case OP_FCLT_UN:
4431                         /* zeroing the register at the start results in
4432                          * shorter and faster code (we can also remove the widening op)
4433                          */
4434                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4435                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4436                         if (ins->opcode == OP_FCLT_UN) {
4437                                 guchar *unordered_check = code;
4438                                 guchar *jump_to_end;
4439                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4440                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4441                                 jump_to_end = code;
4442                                 x86_jump8 (code, 0);
4443                                 amd64_patch (unordered_check, code);
4444                                 amd64_inc_reg (code, ins->dreg);
4445                                 amd64_patch (jump_to_end, code);
4446                         } else {
4447                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4448                         }
4449                         break;
4450                 case OP_FCGT:
4451                 case OP_FCGT_UN: {
4452                         /* zeroing the register at the start results in
4453                          * shorter and faster code (we can also remove the widening op)
4454                          */
4455                         guchar *unordered_check;
4456                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4457                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4458                         if (ins->opcode == OP_FCGT) {
4459                                 unordered_check = code;
4460                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4461                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4462                                 amd64_patch (unordered_check, code);
4463                         } else {
4464                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4465                         }
4466                         break;
4467                 }
4468                 case OP_FCLT_MEMBASE:
4469                 case OP_FCGT_MEMBASE:
4470                 case OP_FCLT_UN_MEMBASE:
4471                 case OP_FCGT_UN_MEMBASE:
4472                 case OP_FCEQ_MEMBASE: {
4473                         guchar *unordered_check, *jump_to_end;
4474                         int x86_cond;
4475
4476                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4477                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4478
4479                         switch (ins->opcode) {
4480                         case OP_FCEQ_MEMBASE:
4481                                 x86_cond = X86_CC_EQ;
4482                                 break;
4483                         case OP_FCLT_MEMBASE:
4484                         case OP_FCLT_UN_MEMBASE:
4485                                 x86_cond = X86_CC_LT;
4486                                 break;
4487                         case OP_FCGT_MEMBASE:
4488                         case OP_FCGT_UN_MEMBASE:
4489                                 x86_cond = X86_CC_GT;
4490                                 break;
4491                         default:
4492                                 g_assert_not_reached ();
4493                         }
4494
4495                         unordered_check = code;
4496                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4497                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4498
4499                         switch (ins->opcode) {
4500                         case OP_FCEQ_MEMBASE:
4501                         case OP_FCLT_MEMBASE:
4502                         case OP_FCGT_MEMBASE:
4503                                 amd64_patch (unordered_check, code);
4504                                 break;
4505                         case OP_FCLT_UN_MEMBASE:
4506                         case OP_FCGT_UN_MEMBASE:
4507                                 jump_to_end = code;
4508                                 x86_jump8 (code, 0);
4509                                 amd64_patch (unordered_check, code);
4510                                 amd64_inc_reg (code, ins->dreg);
4511                                 amd64_patch (jump_to_end, code);
4512                                 break;
4513                         default:
4514                                 break;
4515                         }
4516                         break;
4517                 }
4518                 case OP_FBEQ: {
4519                         guchar *jump = code;
4520                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4521                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4522                         amd64_patch (jump, code);
4523                         break;
4524                 }
4525                 case OP_FBNE_UN:
4526                         /* Branch if C013 != 100 */
4527                         /* branch if !ZF or (PF|CF) */
4528                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4529                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4530                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4531                         break;
4532                 case OP_FBLT:
4533                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4534                         break;
4535                 case OP_FBLT_UN:
4536                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4537                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4538                         break;
4539                 case OP_FBGT:
4540                 case OP_FBGT_UN:
4541                         if (ins->opcode == OP_FBGT) {
4542                                 guchar *br1;
4543
4544                                 /* skip branch if C1=1 */
4545                                 br1 = code;
4546                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4547                                 /* branch if (C0 | C3) = 1 */
4548                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4549                                 amd64_patch (br1, code);
4550                                 break;
4551                         } else {
4552                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4553                         }
4554                         break;
4555                 case OP_FBGE: {
4556                         /* Branch if C013 == 100 or 001 */
4557                         guchar *br1;
4558
4559                         /* skip branch if C1=1 */
4560                         br1 = code;
4561                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4562                         /* branch if (C0 | C3) = 1 */
4563                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4564                         amd64_patch (br1, code);
4565                         break;
4566                 }
4567                 case OP_FBGE_UN:
4568                         /* Branch if C013 == 000 */
4569                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4570                         break;
4571                 case OP_FBLE: {
4572                         /* Branch if C013=000 or 100 */
4573                         guchar *br1;
4574
4575                         /* skip branch if C1=1 */
4576                         br1 = code;
4577                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4578                         /* branch if C0=0 */
4579                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4580                         amd64_patch (br1, code);
4581                         break;
4582                 }
4583                 case OP_FBLE_UN:
4584                         /* Branch if C013 != 001 */
4585                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4586                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4587                         break;
4588                 case OP_CKFINITE:
4589                         /* Transfer value to the fp stack */
4590                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4591                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4592                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4593
4594                         amd64_push_reg (code, AMD64_RAX);
4595                         amd64_fxam (code);
4596                         amd64_fnstsw (code);
4597                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4598                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4599                         amd64_pop_reg (code, AMD64_RAX);
4600                         amd64_fstp (code, 0);
4601                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4602                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4603                         break;
4604                 case OP_TLS_GET: {
4605                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4606                         break;
4607                 }
4608                 case OP_MEMORY_BARRIER: {
4609                         /* Not needed on amd64 */
4610                         break;
4611                 }
4612                 case OP_ATOMIC_ADD_I4:
4613                 case OP_ATOMIC_ADD_I8: {
4614                         int dreg = ins->dreg;
4615                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4616
4617                         if (dreg == ins->inst_basereg)
4618                                 dreg = AMD64_R11;
4619
4620                         if (dreg != ins->sreg2)
4621                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4622
4623                         x86_prefix (code, X86_LOCK_PREFIX);
4624                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4625
4626                         if (dreg != ins->dreg)
4627                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4628
4629                         break;
4630                 }
4631                 case OP_ATOMIC_ADD_NEW_I4:
4632                 case OP_ATOMIC_ADD_NEW_I8: {
4633                         int dreg = ins->dreg;
4634                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4635
4636                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4637                                 dreg = AMD64_R11;
4638
4639                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4640                         amd64_prefix (code, X86_LOCK_PREFIX);
4641                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4642                         /* dreg contains the old value, add with sreg2 value */
4643                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4644
4645                         if (ins->dreg != dreg)
4646                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4647
4648                         break;
4649                 }
4650                 case OP_ATOMIC_EXCHANGE_I4:
4651                 case OP_ATOMIC_EXCHANGE_I8:
4652                 case OP_ATOMIC_CAS_IMM_I4: {
4653                         guchar *br[2];
4654                         int sreg2 = ins->sreg2;
4655                         int breg = ins->inst_basereg;
4656                         guint32 size;
4657                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4658
4659                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4660                                 size = 8;
4661                         else
4662                                 size = 4;
4663
4664                         /*
4665                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4666                          * an explanation of how this works.
4667                          */
4668
4669                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4670                          * hack to overcome limits in x86 reg allocator
4671                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4672                          */
4673                         g_assert (ins->dreg == AMD64_RAX);
4674
4675                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4676                                 /* Highly unlikely, but possible */
4677                                 need_push = TRUE;
4678
4679                         /* The pushes invalidate rsp */
4680                         if ((breg == AMD64_RAX) || need_push) {
4681                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4682                                 breg = AMD64_R11;
4683                         }
4684
4685                         /* We need the EAX reg for the comparand */
4686                         if (ins->sreg2 == AMD64_RAX) {
4687                                 if (breg != AMD64_R11) {
4688                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4689                                         sreg2 = AMD64_R11;
4690                                 } else {
4691                                         g_assert (need_push);
4692                                         amd64_push_reg (code, AMD64_RDX);
4693                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4694                                         sreg2 = AMD64_RDX;
4695                                         rdx_pushed = TRUE;
4696                                 }
4697                         }
4698
4699                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4700                                 if (ins->backend.data == NULL)
4701                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4702                                 else
4703                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4704
4705                                 amd64_prefix (code, X86_LOCK_PREFIX);
4706                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4707                         } else {
4708                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4709
4710                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4711                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4712                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4713                                 amd64_patch (br [1], br [0]);
4714                         }
4715
4716                         if (rdx_pushed)
4717                                 amd64_pop_reg (code, AMD64_RDX);
4718
4719                         break;
4720                 }
4721                 default:
4722                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4723                         g_assert_not_reached ();
4724                 }
4725
4726                 if ((code - cfg->native_code - offset) > max_len) {
4727                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4728                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4729                         g_assert_not_reached ();
4730                 }
4731
4732                 cpos += max_len;
4733
4734                 last_ins = ins;
4735                 last_offset = offset;
4736         }
4737
4738         cfg->code_len = code - cfg->native_code;
4739 }
4740
4741 #endif /* DISABLE_JIT */
4742
4743 void
4744 mono_arch_register_lowlevel_calls (void)
4745 {
4746         /* The signature doesn't matter */
4747         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4748 }
4749
4750 void
4751 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4752 {
4753         MonoJumpInfo *patch_info;
4754         gboolean compile_aot = !run_cctors;
4755
4756         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4757                 unsigned char *ip = patch_info->ip.i + code;
4758                 unsigned char *target;
4759
4760                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4761
4762                 if (compile_aot) {
4763                         switch (patch_info->type) {
4764                         case MONO_PATCH_INFO_BB:
4765                         case MONO_PATCH_INFO_LABEL:
4766                                 break;
4767                         default:
4768                                 /* No need to patch these */
4769                                 continue;
4770                         }
4771                 }
4772
4773                 switch (patch_info->type) {
4774                 case MONO_PATCH_INFO_NONE:
4775                         continue;
4776                 case MONO_PATCH_INFO_METHOD_REL:
4777                 case MONO_PATCH_INFO_R8:
4778                 case MONO_PATCH_INFO_R4:
4779                         g_assert_not_reached ();
4780                         continue;
4781                 case MONO_PATCH_INFO_BB:
4782                         break;
4783                 default:
4784                         break;
4785                 }
4786
4787                 /*
4788                  * Debug code to help track down problems where the target of a near call is
4789                  * is not valid.
4790                  */
4791                 if (amd64_is_near_call (ip)) {
4792                         gint64 disp = (guint8*)target - (guint8*)ip;
4793
4794                         if (!amd64_is_imm32 (disp)) {
4795                                 printf ("TYPE: %d\n", patch_info->type);
4796                                 switch (patch_info->type) {
4797                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4798                                         printf ("V: %s\n", patch_info->data.name);
4799                                         break;
4800                                 case MONO_PATCH_INFO_METHOD_JUMP:
4801                                 case MONO_PATCH_INFO_METHOD:
4802                                         printf ("V: %s\n", patch_info->data.method->name);
4803                                         break;
4804                                 default:
4805                                         break;
4806                                 }
4807                         }
4808                 }
4809
4810                 amd64_patch (ip, (gpointer)target);
4811         }
4812 }
4813
4814 static int
4815 get_max_epilog_size (MonoCompile *cfg)
4816 {
4817         int max_epilog_size = 16;
4818
4819         if (cfg->method->save_lmf)
4820                 max_epilog_size += 256;
4821
4822         if (mono_jit_trace_calls != NULL)
4823                 max_epilog_size += 50;
4824
4825         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4826                 max_epilog_size += 50;
4827
4828         max_epilog_size += (AMD64_NREG * 2);
4829
4830         return max_epilog_size;
4831 }
4832
4833 /*
4834  * This macro is used for testing whenever the unwinder works correctly at every point
4835  * where an async exception can happen.
4836  */
4837 /* This will generate a SIGSEGV at the given point in the code */
4838 #define async_exc_point(code) do { \
4839     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4840          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4841              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4842          cfg->arch.async_point_count ++; \
4843     } \
4844 } while (0)
4845
4846 guint8 *
4847 mono_arch_emit_prolog (MonoCompile *cfg)
4848 {
4849         MonoMethod *method = cfg->method;
4850         MonoBasicBlock *bb;
4851         MonoMethodSignature *sig;
4852         MonoInst *ins;
4853         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4854         guint8 *code;
4855         CallInfo *cinfo;
4856         gint32 lmf_offset = cfg->arch.lmf_offset;
4857         gboolean args_clobbered = FALSE;
4858         gboolean trace = FALSE;
4859
4860         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4861
4862         code = cfg->native_code = g_malloc (cfg->code_size);
4863
4864         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4865                 trace = TRUE;
4866
4867         /* Amount of stack space allocated by register saving code */
4868         pos = 0;
4869
4870         /* Offset between RSP and the CFA */
4871         cfa_offset = 0;
4872
4873         /*
4874          * The prolog consists of the following parts:
4875          * FP present:
4876          * - push rbp, mov rbp, rsp
4877          * - save callee saved regs using pushes
4878          * - allocate frame
4879          * - save rgctx if needed
4880          * - save lmf if needed
4881          * FP not present:
4882          * - allocate frame
4883          * - save rgctx if needed
4884          * - save lmf if needed
4885          * - save callee saved regs using moves
4886          */
4887
4888         // CFA = sp + 8
4889         cfa_offset = 8;
4890         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4891         // IP saved at CFA - 8
4892         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4893         async_exc_point (code);
4894
4895         if (!cfg->arch.omit_fp) {
4896                 amd64_push_reg (code, AMD64_RBP);
4897                 cfa_offset += 8;
4898                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4899                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4900                 async_exc_point (code);
4901 #ifdef PLATFORM_WIN32
4902                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4903 #endif
4904
4905                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4906                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4907                 async_exc_point (code);
4908 #ifdef PLATFORM_WIN32
4909                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4910 #endif
4911         }
4912
4913         /* Save callee saved registers */
4914         if (!cfg->arch.omit_fp && !method->save_lmf) {
4915                 int offset = cfa_offset;
4916
4917                 for (i = 0; i < AMD64_NREG; ++i)
4918                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4919                                 amd64_push_reg (code, i);
4920                                 pos += sizeof (gpointer);
4921                                 offset += 8;
4922                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4923                                 async_exc_point (code);
4924                         }
4925         }
4926
4927         if (cfg->arch.omit_fp) {
4928                 /*
4929                  * On enter, the stack is misaligned by the the pushing of the return
4930                  * address. It is either made aligned by the pushing of %rbp, or by
4931                  * this.
4932                  */
4933                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4934                 if ((alloc_size % 16) == 0)
4935                         alloc_size += 8;
4936         } else {
4937                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4938
4939                 alloc_size -= pos;
4940         }
4941
4942         cfg->arch.stack_alloc_size = alloc_size;
4943
4944         /* Allocate stack frame */
4945         if (alloc_size) {
4946                 /* See mono_emit_stack_alloc */
4947 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4948                 guint32 remaining_size = alloc_size;
4949                 while (remaining_size >= 0x1000) {
4950                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4951                         if (cfg->arch.omit_fp) {
4952                                 cfa_offset += 0x1000;
4953                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4954                         }
4955                         async_exc_point (code);
4956 #ifdef PLATFORM_WIN32
4957                         if (cfg->arch.omit_fp)
4958                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4959 #endif
4960
4961                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4962                         remaining_size -= 0x1000;
4963                 }
4964                 if (remaining_size) {
4965                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4966                         if (cfg->arch.omit_fp) {
4967                                 cfa_offset += remaining_size;
4968                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4969                                 async_exc_point (code);
4970                         }
4971 #ifdef PLATFORM_WIN32
4972                         if (cfg->arch.omit_fp)
4973                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4974 #endif
4975                 }
4976 #else
4977                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4978                 if (cfg->arch.omit_fp) {
4979                         cfa_offset += alloc_size;
4980                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4981                         async_exc_point (code);
4982                 }
4983 #endif
4984         }
4985
4986         /* Stack alignment check */
4987 #if 0
4988         {
4989                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4990                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4991                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4992                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4993                 amd64_breakpoint (code);
4994         }
4995 #endif
4996
4997         /* Save LMF */
4998         if (method->save_lmf) {
4999                 /*
5000                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5001                  */
5002                 /* sp is saved right before calls */
5003                 /* Skip method (only needed for trampoline LMF frames) */
5004                 /* Save callee saved regs */
5005                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
5006                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
5007                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
5008                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
5009                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
5010                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
5011         }
5012
5013         /* Save callee saved registers */
5014         if (cfg->arch.omit_fp && !method->save_lmf) {
5015                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5016
5017                 /* Save caller saved registers after sp is adjusted */
5018                 /* The registers are saved at the bottom of the frame */
5019                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5020                 for (i = 0; i < AMD64_NREG; ++i)
5021                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5022                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5023                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5024                                 save_area_offset += 8;
5025                                 async_exc_point (code);
5026                         }
5027         }
5028
5029         /* store runtime generic context */
5030         if (cfg->rgctx_var) {
5031                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5032                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5033
5034                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5035         }
5036
5037         /* compute max_offset in order to use short forward jumps */
5038         max_offset = 0;
5039         max_epilog_size = get_max_epilog_size (cfg);
5040         if (cfg->opt & MONO_OPT_BRANCH) {
5041                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5042                         MonoInst *ins;
5043                         bb->max_offset = max_offset;
5044
5045                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5046                                 max_offset += 6;
5047                         /* max alignment for loops */
5048                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5049                                 max_offset += LOOP_ALIGNMENT;
5050
5051                         MONO_BB_FOR_EACH_INS (bb, ins) {
5052                                 if (ins->opcode == OP_LABEL)
5053                                         ins->inst_c1 = max_offset;
5054
5055                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5056                         }
5057
5058                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
5059                                 /* The tracing code can be quite large */
5060                                 max_offset += max_epilog_size;
5061                 }
5062         }
5063
5064         sig = mono_method_signature (method);
5065         pos = 0;
5066
5067         cinfo = cfg->arch.cinfo;
5068
5069         if (sig->ret->type != MONO_TYPE_VOID) {
5070                 /* Save volatile arguments to the stack */
5071                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5072                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5073         }
5074
5075         /* Keep this in sync with emit_load_volatile_arguments */
5076         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5077                 ArgInfo *ainfo = cinfo->args + i;
5078                 gint32 stack_offset;
5079                 MonoType *arg_type;
5080
5081                 ins = cfg->args [i];
5082
5083                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5084                         /* Unused arguments */
5085                         continue;
5086
5087                 if (sig->hasthis && (i == 0))
5088                         arg_type = &mono_defaults.object_class->byval_arg;
5089                 else
5090                         arg_type = sig->params [i - sig->hasthis];
5091
5092                 stack_offset = ainfo->offset + ARGS_OFFSET;
5093
5094                 if (cfg->globalra) {
5095                         /* All the other moves are done by the register allocator */
5096                         switch (ainfo->storage) {
5097                         case ArgInFloatSSEReg:
5098                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5099                                 break;
5100                         case ArgValuetypeInReg:
5101                                 for (quad = 0; quad < 2; quad ++) {
5102                                         switch (ainfo->pair_storage [quad]) {
5103                                         case ArgInIReg:
5104                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5105                                                 break;
5106                                         case ArgInFloatSSEReg:
5107                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5108                                                 break;
5109                                         case ArgInDoubleSSEReg:
5110                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5111                                                 break;
5112                                         case ArgNone:
5113                                                 break;
5114                                         default:
5115                                                 g_assert_not_reached ();
5116                                         }
5117                                 }
5118                                 break;
5119                         default:
5120                                 break;
5121                         }
5122
5123                         continue;
5124                 }
5125
5126                 /* Save volatile arguments to the stack */
5127                 if (ins->opcode != OP_REGVAR) {
5128                         switch (ainfo->storage) {
5129                         case ArgInIReg: {
5130                                 guint32 size = 8;
5131
5132                                 /* FIXME: I1 etc */
5133                                 /*
5134                                 if (stack_offset & 0x1)
5135                                         size = 1;
5136                                 else if (stack_offset & 0x2)
5137                                         size = 2;
5138                                 else if (stack_offset & 0x4)
5139                                         size = 4;
5140                                 else
5141                                         size = 8;
5142                                 */
5143                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5144                                 break;
5145                         }
5146                         case ArgInFloatSSEReg:
5147                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5148                                 break;
5149                         case ArgInDoubleSSEReg:
5150                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5151                                 break;
5152                         case ArgValuetypeInReg:
5153                                 for (quad = 0; quad < 2; quad ++) {
5154                                         switch (ainfo->pair_storage [quad]) {
5155                                         case ArgInIReg:
5156                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5157                                                 break;
5158                                         case ArgInFloatSSEReg:
5159                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5160                                                 break;
5161                                         case ArgInDoubleSSEReg:
5162                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5163                                                 break;
5164                                         case ArgNone:
5165                                                 break;
5166                                         default:
5167                                                 g_assert_not_reached ();
5168                                         }
5169                                 }
5170                                 break;
5171                         case ArgValuetypeAddrInIReg:
5172                                 if (ainfo->pair_storage [0] == ArgInIReg)
5173                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5174                                 break;
5175                         default:
5176                                 break;
5177                         }
5178                 } else {
5179                         /* Argument allocated to (non-volatile) register */
5180                         switch (ainfo->storage) {
5181                         case ArgInIReg:
5182                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5183                                 break;
5184                         case ArgOnStack:
5185                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5186                                 break;
5187                         default:
5188                                 g_assert_not_reached ();
5189                         }
5190                 }
5191         }
5192
5193         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5194         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5195                 guint64 domain = (guint64)cfg->domain;
5196
5197                 args_clobbered = TRUE;
5198
5199                 /*
5200                  * The call might clobber argument registers, but they are already
5201                  * saved to the stack/global regs.
5202                  */
5203                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5204                         guint8 *buf, *no_domain_branch;
5205
5206                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5207                         if ((domain >> 32) == 0)
5208                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5209                         else
5210                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5211                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5212                         no_domain_branch = code;
5213                         x86_branch8 (code, X86_CC_NE, 0, 0);
5214                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5215                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5216                         buf = code;
5217                         x86_branch8 (code, X86_CC_NE, 0, 0);
5218                         amd64_patch (no_domain_branch, code);
5219                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5220                                           (gpointer)"mono_jit_thread_attach", TRUE);
5221                         amd64_patch (buf, code);
5222 #ifdef PLATFORM_WIN32
5223                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5224                         /* FIXME: Add a separate key for LMF to avoid this */
5225                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5226 #endif
5227                 } else {
5228                         g_assert (!cfg->compile_aot);
5229                         if ((domain >> 32) == 0)
5230                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5231                         else
5232                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5233                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5234                                           (gpointer)"mono_jit_thread_attach", TRUE);
5235                 }
5236         }
5237
5238         if (method->save_lmf) {
5239                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5240                         /*
5241                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5242                          * through the mono_lmf_addr TLS variable.
5243                          */
5244                         /* %rax = previous_lmf */
5245                         x86_prefix (code, X86_FS_PREFIX);
5246                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5247
5248                         /* Save previous_lmf */
5249                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5250                         /* Set new lmf */
5251                         if (lmf_offset == 0) {
5252                                 x86_prefix (code, X86_FS_PREFIX);
5253                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5254                         } else {
5255                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5256                                 x86_prefix (code, X86_FS_PREFIX);
5257                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5258                         }
5259                 } else {
5260                         if (lmf_addr_tls_offset != -1) {
5261                                 /* Load lmf quicky using the FS register */
5262                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5263 #ifdef PLATFORM_WIN32
5264                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5265                                 /* FIXME: Add a separate key for LMF to avoid this */
5266                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5267 #endif
5268                         }
5269                         else {
5270                                 /*
5271                                  * The call might clobber argument registers, but they are already
5272                                  * saved to the stack/global regs.
5273                                  */
5274                                 args_clobbered = TRUE;
5275                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5276                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5277                         }
5278
5279                         /* Save lmf_addr */
5280                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5281                         /* Save previous_lmf */
5282                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5283                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5284                         /* Set new lmf */
5285                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5286                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5287                 }
5288         }
5289
5290         if (trace) {
5291                 args_clobbered = TRUE;
5292                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5293         }
5294
5295         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5296                 args_clobbered = TRUE;
5297
5298         /*
5299          * Optimize the common case of the first bblock making a call with the same
5300          * arguments as the method. This works because the arguments are still in their
5301          * original argument registers.
5302          * FIXME: Generalize this
5303          */
5304         if (!args_clobbered) {
5305                 MonoBasicBlock *first_bb = cfg->bb_entry;
5306                 MonoInst *next;
5307
5308                 next = mono_bb_first_ins (first_bb);
5309                 if (!next && first_bb->next_bb) {
5310                         first_bb = first_bb->next_bb;
5311                         next = mono_bb_first_ins (first_bb);
5312                 }
5313
5314                 if (first_bb->in_count > 1)
5315                         next = NULL;
5316
5317                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5318                         ArgInfo *ainfo = cinfo->args + i;
5319                         gboolean match = FALSE;
5320
5321                         ins = cfg->args [i];
5322                         if (ins->opcode != OP_REGVAR) {
5323                                 switch (ainfo->storage) {
5324                                 case ArgInIReg: {
5325                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5326                                                 if (next->dreg == ainfo->reg) {
5327                                                         NULLIFY_INS (next);
5328                                                         match = TRUE;
5329                                                 } else {
5330                                                         next->opcode = OP_MOVE;
5331                                                         next->sreg1 = ainfo->reg;
5332                                                         /* Only continue if the instruction doesn't change argument regs */
5333                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5334                                                                 match = TRUE;
5335                                                 }
5336                                         }
5337                                         break;
5338                                 }
5339                                 default:
5340                                         break;
5341                                 }
5342                         } else {
5343                                 /* Argument allocated to (non-volatile) register */
5344                                 switch (ainfo->storage) {
5345                                 case ArgInIReg:
5346                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5347                                                 NULLIFY_INS (next);
5348                                                 match = TRUE;
5349                                         }
5350                                         break;
5351                                 default:
5352                                         break;
5353                                 }
5354                         }
5355
5356                         if (match) {
5357                                 next = next->next;
5358                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5359                                 if (!next)
5360                                         break;
5361                         }
5362                 }
5363         }
5364
5365         cfg->code_len = code - cfg->native_code;
5366
5367         g_assert (cfg->code_len < cfg->code_size);
5368
5369         return code;
5370 }
5371
5372 void
5373 mono_arch_emit_epilog (MonoCompile *cfg)
5374 {
5375         MonoMethod *method = cfg->method;
5376         int quad, pos, i;
5377         guint8 *code;
5378         int max_epilog_size;
5379         CallInfo *cinfo;
5380         gint32 lmf_offset = cfg->arch.lmf_offset;
5381
5382         max_epilog_size = get_max_epilog_size (cfg);
5383
5384         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5385                 cfg->code_size *= 2;
5386                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5387                 mono_jit_stats.code_reallocs++;
5388         }
5389
5390         code = cfg->native_code + cfg->code_len;
5391
5392         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5393                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5394
5395         /* the code restoring the registers must be kept in sync with OP_JMP */
5396         pos = 0;
5397
5398         if (method->save_lmf) {
5399                 /* check if we need to restore protection of the stack after a stack overflow */
5400                 if (mono_get_jit_tls_offset () != -1) {
5401                         guint8 *patch;
5402                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5403                         /* we load the value in a separate instruction: this mechanism may be
5404                          * used later as a safer way to do thread interruption
5405                          */
5406                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5407                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5408                         patch = code;
5409                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5410                         /* note that the call trampoline will preserve eax/edx */
5411                         x86_call_reg (code, X86_ECX);
5412                         x86_patch (patch, code);
5413                 } else {
5414                         /* FIXME: maybe save the jit tls in the prolog */
5415                 }
5416                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5417                         /*
5418                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5419                          * through the mono_lmf_addr TLS variable.
5420                          */
5421                         /* reg = previous_lmf */
5422                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5423                         x86_prefix (code, X86_FS_PREFIX);
5424                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5425                 } else {
5426                         /* Restore previous lmf */
5427                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5428                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5429                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5430                 }
5431
5432                 /* Restore caller saved regs */
5433                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5434                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5435                 }
5436                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5437                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5438                 }
5439                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5440                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5441                 }
5442                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5443                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5444                 }
5445                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5446                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5447                 }
5448                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5449                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5450                 }
5451         } else {
5452
5453                 if (cfg->arch.omit_fp) {
5454                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5455
5456                         for (i = 0; i < AMD64_NREG; ++i)
5457                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5458                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5459                                         save_area_offset += 8;
5460                                 }
5461                 }
5462                 else {
5463                         for (i = 0; i < AMD64_NREG; ++i)
5464                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5465                                         pos -= sizeof (gpointer);
5466
5467                         if (pos) {
5468                                 if (pos == - sizeof (gpointer)) {
5469                                         /* Only one register, so avoid lea */
5470                                         for (i = AMD64_NREG - 1; i > 0; --i)
5471                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5472                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5473                                                 }
5474                                 }
5475                                 else {
5476                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5477
5478                                         /* Pop registers in reverse order */
5479                                         for (i = AMD64_NREG - 1; i > 0; --i)
5480                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5481                                                         amd64_pop_reg (code, i);
5482                                                 }
5483                                 }
5484                         }
5485                 }
5486         }
5487
5488         /* Load returned vtypes into registers if needed */
5489         cinfo = cfg->arch.cinfo;
5490         if (cinfo->ret.storage == ArgValuetypeInReg) {
5491                 ArgInfo *ainfo = &cinfo->ret;
5492                 MonoInst *inst = cfg->ret;
5493
5494                 for (quad = 0; quad < 2; quad ++) {
5495                         switch (ainfo->pair_storage [quad]) {
5496                         case ArgInIReg:
5497                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5498                                 break;
5499                         case ArgInFloatSSEReg:
5500                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5501                                 break;
5502                         case ArgInDoubleSSEReg:
5503                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5504                                 break;
5505                         case ArgNone:
5506                                 break;
5507                         default:
5508                                 g_assert_not_reached ();
5509                         }
5510                 }
5511         }
5512
5513         if (cfg->arch.omit_fp) {
5514                 if (cfg->arch.stack_alloc_size)
5515                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5516         } else {
5517                 amd64_leave (code);
5518         }
5519         async_exc_point (code);
5520         amd64_ret (code);
5521
5522         cfg->code_len = code - cfg->native_code;
5523
5524         g_assert (cfg->code_len < cfg->code_size);
5525
5526         if (cfg->arch.omit_fp) {
5527                 /*
5528                  * Encode the stack size into used_int_regs so the exception handler
5529                  * can access it.
5530                  */
5531                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5532                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5533         }
5534 }
5535
5536 void
5537 mono_arch_emit_exceptions (MonoCompile *cfg)
5538 {
5539         MonoJumpInfo *patch_info;
5540         int nthrows, i;
5541         guint8 *code;
5542         MonoClass *exc_classes [16];
5543         guint8 *exc_throw_start [16], *exc_throw_end [16];
5544         guint32 code_size = 0;
5545
5546         /* Compute needed space */
5547         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5548                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5549                         code_size += 40;
5550                 if (patch_info->type == MONO_PATCH_INFO_R8)
5551                         code_size += 8 + 15; /* sizeof (double) + alignment */
5552                 if (patch_info->type == MONO_PATCH_INFO_R4)
5553                         code_size += 4 + 15; /* sizeof (float) + alignment */
5554         }
5555
5556         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5557                 cfg->code_size *= 2;
5558                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5559                 mono_jit_stats.code_reallocs++;
5560         }
5561
5562         code = cfg->native_code + cfg->code_len;
5563
5564         /* add code to raise exceptions */
5565         nthrows = 0;
5566         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5567                 switch (patch_info->type) {
5568                 case MONO_PATCH_INFO_EXC: {
5569                         MonoClass *exc_class;
5570                         guint8 *buf, *buf2;
5571                         guint32 throw_ip;
5572
5573                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5574
5575                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5576                         g_assert (exc_class);
5577                         throw_ip = patch_info->ip.i;
5578
5579                         //x86_breakpoint (code);
5580                         /* Find a throw sequence for the same exception class */
5581                         for (i = 0; i < nthrows; ++i)
5582                                 if (exc_classes [i] == exc_class)
5583                                         break;
5584                         if (i < nthrows) {
5585                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5586                                 x86_jump_code (code, exc_throw_start [i]);
5587                                 patch_info->type = MONO_PATCH_INFO_NONE;
5588                         }
5589                         else {
5590                                 buf = code;
5591                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5592                                 buf2 = code;
5593
5594                                 if (nthrows < 16) {
5595                                         exc_classes [nthrows] = exc_class;
5596                                         exc_throw_start [nthrows] = code;
5597                                 }
5598                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5599
5600                                 patch_info->type = MONO_PATCH_INFO_NONE;
5601
5602                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5603
5604                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5605                                 while (buf < buf2)
5606                                         x86_nop (buf);
5607
5608                                 if (nthrows < 16) {
5609                                         exc_throw_end [nthrows] = code;
5610                                         nthrows ++;
5611                                 }
5612                         }
5613                         break;
5614                 }
5615                 default:
5616                         /* do nothing */
5617                         break;
5618                 }
5619         }
5620
5621         /* Handle relocations with RIP relative addressing */
5622         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5623                 gboolean remove = FALSE;
5624
5625                 switch (patch_info->type) {
5626                 case MONO_PATCH_INFO_R8:
5627                 case MONO_PATCH_INFO_R4: {
5628                         guint8 *pos;
5629
5630                         /* The SSE opcodes require a 16 byte alignment */
5631                         code = (guint8*)ALIGN_TO (code, 16);
5632
5633                         pos = cfg->native_code + patch_info->ip.i;
5634
5635                         if (IS_REX (pos [1]))
5636                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5637                         else
5638                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5639
5640                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5641                                 *(double*)code = *(double*)patch_info->data.target;
5642                                 code += sizeof (double);
5643                         } else {
5644                                 *(float*)code = *(float*)patch_info->data.target;
5645                                 code += sizeof (float);
5646                         }
5647
5648                         remove = TRUE;
5649                         break;
5650                 }
5651                 default:
5652                         break;
5653                 }
5654
5655                 if (remove) {
5656                         if (patch_info == cfg->patch_info)
5657                                 cfg->patch_info = patch_info->next;
5658                         else {
5659                                 MonoJumpInfo *tmp;
5660
5661                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5662                                         ;
5663                                 tmp->next = patch_info->next;
5664                         }
5665                 }
5666         }
5667
5668         cfg->code_len = code - cfg->native_code;
5669
5670         g_assert (cfg->code_len < cfg->code_size);
5671
5672 }
5673
5674 void*
5675 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5676 {
5677         guchar *code = p;
5678         CallInfo *cinfo = NULL;
5679         MonoMethodSignature *sig;
5680         MonoInst *inst;
5681         int i, n, stack_area = 0;
5682
5683         /* Keep this in sync with mono_arch_get_argument_info */
5684
5685         if (enable_arguments) {
5686                 /* Allocate a new area on the stack and save arguments there */
5687                 sig = mono_method_signature (cfg->method);
5688
5689                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5690
5691                 n = sig->param_count + sig->hasthis;
5692
5693                 stack_area = ALIGN_TO (n * 8, 16);
5694
5695                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5696
5697                 for (i = 0; i < n; ++i) {
5698                         inst = cfg->args [i];
5699
5700                         if (inst->opcode == OP_REGVAR)
5701                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5702                         else {
5703                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5704                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5705                         }
5706                 }
5707         }
5708
5709         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5710         amd64_set_reg_template (code, AMD64_ARG_REG1);
5711         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5712         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5713
5714         if (enable_arguments)
5715                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5716
5717         return code;
5718 }
5719
5720 enum {
5721         SAVE_NONE,
5722         SAVE_STRUCT,
5723         SAVE_EAX,
5724         SAVE_EAX_EDX,
5725         SAVE_XMM
5726 };
5727
5728 void*
5729 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5730 {
5731         guchar *code = p;
5732         int save_mode = SAVE_NONE;
5733         MonoMethod *method = cfg->method;
5734         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5735
5736         switch (rtype) {
5737         case MONO_TYPE_VOID:
5738                 /* special case string .ctor icall */
5739                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5740                         save_mode = SAVE_EAX;
5741                 else
5742                         save_mode = SAVE_NONE;
5743                 break;
5744         case MONO_TYPE_I8:
5745         case MONO_TYPE_U8:
5746                 save_mode = SAVE_EAX;
5747                 break;
5748         case MONO_TYPE_R4:
5749         case MONO_TYPE_R8:
5750                 save_mode = SAVE_XMM;
5751                 break;
5752         case MONO_TYPE_GENERICINST:
5753                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5754                         save_mode = SAVE_EAX;
5755                         break;
5756                 }
5757                 /* Fall through */
5758         case MONO_TYPE_VALUETYPE:
5759                 save_mode = SAVE_STRUCT;
5760                 break;
5761         default:
5762                 save_mode = SAVE_EAX;
5763                 break;
5764         }
5765
5766         /* Save the result and copy it into the proper argument register */
5767         switch (save_mode) {
5768         case SAVE_EAX:
5769                 amd64_push_reg (code, AMD64_RAX);
5770                 /* Align stack */
5771                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5772                 if (enable_arguments)
5773                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5774                 break;
5775         case SAVE_STRUCT:
5776                 /* FIXME: */
5777                 if (enable_arguments)
5778                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5779                 break;
5780         case SAVE_XMM:
5781                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5782                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5783                 /* Align stack */
5784                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5785                 /*
5786                  * The result is already in the proper argument register so no copying
5787                  * needed.
5788                  */
5789                 break;
5790         case SAVE_NONE:
5791                 break;
5792         default:
5793                 g_assert_not_reached ();
5794         }
5795
5796         /* Set %al since this is a varargs call */
5797         if (save_mode == SAVE_XMM)
5798                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5799         else
5800                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5801
5802         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5803         amd64_set_reg_template (code, AMD64_ARG_REG1);
5804         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5805
5806         /* Restore result */
5807         switch (save_mode) {
5808         case SAVE_EAX:
5809                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5810                 amd64_pop_reg (code, AMD64_RAX);
5811                 break;
5812         case SAVE_STRUCT:
5813                 /* FIXME: */
5814                 break;
5815         case SAVE_XMM:
5816                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5817                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5818                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5819                 break;
5820         case SAVE_NONE:
5821                 break;
5822         default:
5823                 g_assert_not_reached ();
5824         }
5825
5826         return code;
5827 }
5828
5829 void
5830 mono_arch_flush_icache (guint8 *code, gint size)
5831 {
5832         /* Not needed */
5833 }
5834
5835 void
5836 mono_arch_flush_register_windows (void)
5837 {
5838 }
5839
5840 gboolean
5841 mono_arch_is_inst_imm (gint64 imm)
5842 {
5843         return amd64_is_imm32 (imm);
5844 }
5845
5846 /*
5847  * Determine whenever the trap whose info is in SIGINFO is caused by
5848  * integer overflow.
5849  */
5850 gboolean
5851 mono_arch_is_int_overflow (void *sigctx, void *info)
5852 {
5853         MonoContext ctx;
5854         guint8* rip;
5855         int reg;
5856         gint64 value;
5857
5858         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5859
5860         rip = (guint8*)ctx.rip;
5861
5862         if (IS_REX (rip [0])) {
5863                 reg = amd64_rex_b (rip [0]);
5864                 rip ++;
5865         }
5866         else
5867                 reg = 0;
5868
5869         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5870                 /* idiv REG */
5871                 reg += x86_modrm_rm (rip [1]);
5872
5873                 switch (reg) {
5874                 case AMD64_RAX:
5875                         value = ctx.rax;
5876                         break;
5877                 case AMD64_RBX:
5878                         value = ctx.rbx;
5879                         break;
5880                 case AMD64_RCX:
5881                         value = ctx.rcx;
5882                         break;
5883                 case AMD64_RDX:
5884                         value = ctx.rdx;
5885                         break;
5886                 case AMD64_RBP:
5887                         value = ctx.rbp;
5888                         break;
5889                 case AMD64_RSP:
5890                         value = ctx.rsp;
5891                         break;
5892                 case AMD64_RSI:
5893                         value = ctx.rsi;
5894                         break;
5895                 case AMD64_RDI:
5896                         value = ctx.rdi;
5897                         break;
5898                 case AMD64_R12:
5899                         value = ctx.r12;
5900                         break;
5901                 case AMD64_R13:
5902                         value = ctx.r13;
5903                         break;
5904                 case AMD64_R14:
5905                         value = ctx.r14;
5906                         break;
5907                 case AMD64_R15:
5908                         value = ctx.r15;
5909                         break;
5910                 default:
5911                         g_assert_not_reached ();
5912                         reg = -1;
5913                 }
5914
5915                 if (value == -1)
5916                         return TRUE;
5917         }
5918
5919         return FALSE;
5920 }
5921
5922 guint32
5923 mono_arch_get_patch_offset (guint8 *code)
5924 {
5925         return 3;
5926 }
5927
5928 /**
5929  * mono_breakpoint_clean_code:
5930  *
5931  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5932  * breakpoints in the original code, they are removed in the copy.
5933  *
5934  * Returns TRUE if no sw breakpoint was present.
5935  */
5936 gboolean
5937 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5938 {
5939         int i;
5940         gboolean can_write = TRUE;
5941         /*
5942          * If method_start is non-NULL we need to perform bound checks, since we access memory
5943          * at code - offset we could go before the start of the method and end up in a different
5944          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5945          * instead.
5946          */
5947         if (!method_start || code - offset >= method_start) {
5948                 memcpy (buf, code - offset, size);
5949         } else {
5950                 int diff = code - method_start;
5951                 memset (buf, 0, size);
5952                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5953         }
5954         code -= offset;
5955         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5956                 int idx = mono_breakpoint_info_index [i];
5957                 guint8 *ptr;
5958                 if (idx < 1)
5959                         continue;
5960                 ptr = mono_breakpoint_info [idx].address;
5961                 if (ptr >= code && ptr < code + size) {
5962                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5963                         can_write = FALSE;
5964                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5965                         buf [ptr - code] = saved_byte;
5966                 }
5967         }
5968         return can_write;
5969 }
5970
5971 gpointer
5972 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5973 {
5974         guint8 buf [10];
5975         guint32 reg;
5976         gint32 disp;
5977         guint8 rex = 0;
5978
5979         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5980         code = buf + 9;
5981
5982         *displacement = 0;
5983
5984         /* go to the start of the call instruction
5985          *
5986          * address_byte = (m << 6) | (o << 3) | reg
5987          * call opcode: 0xff address_byte displacement
5988          * 0xff m=1,o=2 imm8
5989          * 0xff m=2,o=2 imm32
5990          */
5991         code -= 7;
5992
5993         /*
5994          * A given byte sequence can match more than case here, so we have to be
5995          * really careful about the ordering of the cases. Longer sequences
5996          * come first.
5997          */
5998 #ifdef MONO_ARCH_HAVE_IMT
5999         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
6000                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
6001                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
6002                  * ff 50 fc                call   *0xfffffffc(%rax)
6003                  */
6004                 reg = amd64_modrm_rm (code [5]);
6005                 disp = (signed char)code [6];
6006                 /* R10 is clobbered by the IMT thunk code */
6007                 g_assert (reg != AMD64_R10);
6008         }
6009 #else
6010         if (0) {
6011         }
6012 #endif
6013         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6014                         /*
6015                          * This is a interface call
6016                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
6017                          * ff 10                  callq  *(%rax)
6018                          */
6019                 if (IS_REX (code [4]))
6020                         rex = code [4];
6021                 reg = amd64_modrm_rm (code [6]);
6022                 disp = 0;
6023                 /* R10 is clobbered by the IMT thunk code */
6024                 g_assert (reg != AMD64_R10);
6025         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6026                 /* call OFFSET(%rip) */
6027                 disp = *(guint32*)(code + 3);
6028                 return (gpointer*)(code + disp + 7);
6029         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
6030                 /* call *[r12+disp32] */
6031                 if (IS_REX (code [-1]))
6032                         rex = code [-1];
6033                 reg = AMD64_RSP;
6034                 disp = *(gint32*)(code + 3);
6035         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6036                 /* call *[reg+disp32] */
6037                 if (IS_REX (code [0]))
6038                         rex = code [0];
6039                 reg = amd64_modrm_rm (code [2]);
6040                 disp = *(gint32*)(code + 3);
6041                 /* R10 is clobbered by the IMT thunk code */
6042                 g_assert (reg != AMD64_R10);
6043         } else if (code [2] == 0xe8) {
6044                 /* call <ADDR> */
6045                 return NULL;
6046         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
6047                 /* call *[r12+disp32] */
6048                 if (IS_REX (code [2]))
6049                         rex = code [2];
6050                 reg = AMD64_RSP;
6051                 disp = *(gint8*)(code + 6);
6052         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6053                 /* call *%reg */
6054                 return NULL;
6055         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6056                 /* call *[reg+disp8] */
6057                 if (IS_REX (code [3]))
6058                         rex = code [3];
6059                 reg = amd64_modrm_rm (code [5]);
6060                 disp = *(gint8*)(code + 6);
6061                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6062         }
6063         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6064                         /*
6065                          * This is a interface call: should check the above code can't catch it earlier
6066                          * 8b 40 30   mov    0x30(%eax),%eax
6067                          * ff 10      call   *(%eax)
6068                          */
6069                 if (IS_REX (code [4]))
6070                         rex = code [4];
6071                 reg = amd64_modrm_rm (code [6]);
6072                 disp = 0;
6073         }
6074         else
6075                 g_assert_not_reached ();
6076
6077         reg += amd64_rex_b (rex);
6078
6079         /* R11 is clobbered by the trampoline code */
6080         g_assert (reg != AMD64_R11);
6081
6082         *displacement = disp;
6083         return regs [reg];
6084 }
6085
6086 gpointer*
6087 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
6088 {
6089         gpointer vt;
6090         int displacement;
6091         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
6092         if (!vt)
6093                 return NULL;
6094         return (gpointer*)((char*)vt + displacement);
6095 }
6096
6097 int
6098 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6099 {
6100         int this_reg = AMD64_ARG_REG1;
6101
6102         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6103                 CallInfo *cinfo;
6104
6105                 if (!gsctx && code)
6106                         gsctx = mono_get_generic_context_from_code (code);
6107
6108                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6109
6110                 if (cinfo->ret.storage != ArgValuetypeInReg)
6111                         this_reg = AMD64_ARG_REG2;
6112                 g_free (cinfo);
6113         }
6114
6115         return this_reg;
6116 }
6117
6118 gpointer
6119 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6120 {
6121         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6122 }
6123
6124 #define MAX_ARCH_DELEGATE_PARAMS 10
6125
6126 gpointer
6127 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6128 {
6129         guint8 *code, *start;
6130         int i;
6131
6132         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6133                 return NULL;
6134
6135         /* FIXME: Support more cases */
6136         if (MONO_TYPE_ISSTRUCT (sig->ret))
6137                 return NULL;
6138
6139         if (has_target) {
6140                 static guint8* cached = NULL;
6141
6142                 if (cached)
6143                         return cached;
6144
6145                 start = code = mono_global_codeman_reserve (64);
6146
6147                 /* Replace the this argument with the target */
6148                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6149                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6150                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6151
6152                 g_assert ((code - start) < 64);
6153
6154                 mono_debug_add_delegate_trampoline (start, code - start);
6155
6156                 mono_memory_barrier ();
6157
6158                 cached = start;
6159         } else {
6160                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6161                 for (i = 0; i < sig->param_count; ++i)
6162                         if (!mono_is_regsize_var (sig->params [i]))
6163                                 return NULL;
6164                 if (sig->param_count > 4)
6165                         return NULL;
6166
6167                 code = cache [sig->param_count];
6168                 if (code)
6169                         return code;
6170
6171                 start = code = mono_global_codeman_reserve (64);
6172
6173                 if (sig->param_count == 0) {
6174                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6175                 } else {
6176                         /* We have to shift the arguments left */
6177                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6178                         for (i = 0; i < sig->param_count; ++i) {
6179 #ifdef PLATFORM_WIN32
6180                                 if (i < 3)
6181                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6182                                 else
6183                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6184 #else
6185                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6186 #endif
6187                         }
6188
6189                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6190                 }
6191                 g_assert ((code - start) < 64);
6192
6193                 mono_debug_add_delegate_trampoline (start, code - start);
6194
6195                 mono_memory_barrier ();
6196
6197                 cache [sig->param_count] = start;
6198         }
6199
6200         return start;
6201 }
6202
6203 /*
6204  * Support for fast access to the thread-local lmf structure using the GS
6205  * segment register on NPTL + kernel 2.6.x.
6206  */
6207
6208 static gboolean tls_offset_inited = FALSE;
6209
6210 void
6211 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6212 {
6213         if (!tls_offset_inited) {
6214 #ifdef PLATFORM_WIN32
6215                 /*
6216                  * We need to init this multiple times, since when we are first called, the key might not
6217                  * be initialized yet.
6218                  */
6219                 appdomain_tls_offset = mono_domain_get_tls_key ();
6220                 lmf_tls_offset = mono_get_jit_tls_key ();
6221                 thread_tls_offset = mono_thread_get_tls_key ();
6222                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6223
6224                 /* Only 64 tls entries can be accessed using inline code */
6225                 if (appdomain_tls_offset >= 64)
6226                         appdomain_tls_offset = -1;
6227                 if (lmf_tls_offset >= 64)
6228                         lmf_tls_offset = -1;
6229                 if (thread_tls_offset >= 64)
6230                         thread_tls_offset = -1;
6231 #else
6232                 tls_offset_inited = TRUE;
6233 #ifdef MONO_XEN_OPT
6234                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6235 #endif
6236                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6237                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6238                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6239                 thread_tls_offset = mono_thread_get_tls_offset ();
6240 #endif
6241         }
6242 }
6243
6244 void
6245 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6246 {
6247 }
6248
6249 void
6250 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6251 {
6252         MonoCallInst *call = (MonoCallInst*)inst;
6253         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6254
6255         if (vt_reg != -1) {
6256                 MonoInst *vtarg;
6257
6258                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6259                         /*
6260                          * The valuetype is in RAX:RDX after the call, need to be copied to
6261                          * the stack. Save the address here, so the call instruction can
6262                          * access it.
6263                          */
6264                         MonoInst *loc = cfg->arch.vret_addr_loc;
6265
6266                         g_assert (loc);
6267                         g_assert (loc->opcode == OP_REGOFFSET);
6268
6269                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6270                 } else {
6271                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6272                         vtarg->sreg1 = vt_reg;
6273                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6274                         mono_bblock_add_inst (cfg->cbb, vtarg);
6275
6276                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6277                 }
6278         }
6279
6280         /* add the this argument */
6281         if (this_reg != -1) {
6282                 MonoInst *this;
6283                 MONO_INST_NEW (cfg, this, OP_MOVE);
6284                 this->type = this_type;
6285                 this->sreg1 = this_reg;
6286                 this->dreg = mono_regstate_next_int (cfg->rs);
6287                 mono_bblock_add_inst (cfg->cbb, this);
6288
6289                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6290         }
6291 }
6292
6293 #ifdef MONO_ARCH_HAVE_IMT
6294
6295 #define CMP_SIZE (6 + 1)
6296 #define CMP_REG_REG_SIZE (4 + 1)
6297 #define BR_SMALL_SIZE 2
6298 #define BR_LARGE_SIZE 6
6299 #define MOV_REG_IMM_SIZE 10
6300 #define MOV_REG_IMM_32BIT_SIZE 6
6301 #define JUMP_REG_SIZE (2 + 1)
6302
6303 static int
6304 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6305 {
6306         int i, distance = 0;
6307         for (i = start; i < target; ++i)
6308                 distance += imt_entries [i]->chunk_size;
6309         return distance;
6310 }
6311
6312 /*
6313  * LOCKING: called with the domain lock held
6314  */
6315 gpointer
6316 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6317         gpointer fail_tramp)
6318 {
6319         int i;
6320         int size = 0;
6321         guint8 *code, *start;
6322         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6323
6324         for (i = 0; i < count; ++i) {
6325                 MonoIMTCheckItem *item = imt_entries [i];
6326                 if (item->is_equals) {
6327                         if (item->check_target_idx) {
6328                                 if (!item->compare_done) {
6329                                         if (amd64_is_imm32 (item->key))
6330                                                 item->chunk_size += CMP_SIZE;
6331                                         else
6332                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6333                                 }
6334                                 if (vtable_is_32bit)
6335                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6336                                 else
6337                                         item->chunk_size += MOV_REG_IMM_SIZE;
6338                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6339                         } else {
6340                                 if (fail_tramp) {
6341                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
6342                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
6343                                 } else {
6344                                         if (vtable_is_32bit)
6345                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6346                                         else
6347                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6348                                         item->chunk_size += JUMP_REG_SIZE;
6349                                         /* with assert below:
6350                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6351                                          */
6352                                 }
6353                         }
6354                 } else {
6355                         if (amd64_is_imm32 (item->key))
6356                                 item->chunk_size += CMP_SIZE;
6357                         else
6358                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6359                         item->chunk_size += BR_LARGE_SIZE;
6360                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6361                 }
6362                 size += item->chunk_size;
6363         }
6364         if (fail_tramp)
6365                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6366         else
6367                 code = mono_code_manager_reserve (domain->code_mp, size);
6368         start = code;
6369         for (i = 0; i < count; ++i) {
6370                 MonoIMTCheckItem *item = imt_entries [i];
6371                 item->code_target = code;
6372                 if (item->is_equals) {
6373                         if (item->check_target_idx) {
6374                                 if (!item->compare_done) {
6375                                         if (amd64_is_imm32 (item->key))
6376                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6377                                         else {
6378                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6379                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6380                                         }
6381                                 }
6382                                 item->jmp_code = code;
6383                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6384                                 /* See the comment below about R10 */
6385                                 if (fail_tramp) {
6386                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6387                                         amd64_jump_reg (code, AMD64_R10);
6388                                 } else {
6389                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6390                                         amd64_jump_membase (code, AMD64_R10, 0);
6391                                 }
6392                         } else {
6393                                 if (fail_tramp) {
6394                                         if (amd64_is_imm32 (item->key))
6395                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6396                                         else {
6397                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6398                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6399                                         }
6400                                         item->jmp_code = code;
6401                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6402                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6403                                         amd64_jump_reg (code, AMD64_R10);
6404                                         amd64_patch (item->jmp_code, code);
6405                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
6406                                         amd64_jump_reg (code, AMD64_R10);
6407                                         item->jmp_code = NULL;
6408
6409                                 } else {
6410                                         /* enable the commented code to assert on wrong method */
6411 #if 0
6412                                         if (amd64_is_imm32 (item->key))
6413                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6414                                         else {
6415                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6416                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6417                                         }
6418                                         item->jmp_code = code;
6419                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6420                                         /* See the comment below about R10 */
6421                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6422                                         amd64_jump_membase (code, AMD64_R10, 0);
6423                                         amd64_patch (item->jmp_code, code);
6424                                         amd64_breakpoint (code);
6425                                         item->jmp_code = NULL;
6426 #else
6427                                         /* We're using R10 here because R11
6428                                            needs to be preserved.  R10 needs
6429                                            to be preserved for calls which
6430                                            require a runtime generic context,
6431                                            but interface calls don't. */
6432                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6433                                         amd64_jump_membase (code, AMD64_R10, 0);
6434 #endif
6435                                 }
6436                         }
6437                 } else {
6438                         if (amd64_is_imm32 (item->key))
6439                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6440                         else {
6441                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6442                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6443                         }
6444                         item->jmp_code = code;
6445                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6446                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6447                         else
6448                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6449                 }
6450                 g_assert (code - item->code_target <= item->chunk_size);
6451         }
6452         /* patch the branches to get to the target items */
6453         for (i = 0; i < count; ++i) {
6454                 MonoIMTCheckItem *item = imt_entries [i];
6455                 if (item->jmp_code) {
6456                         if (item->check_target_idx) {
6457                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6458                         }
6459                 }
6460         }
6461
6462         if (!fail_tramp)
6463                 mono_stats.imt_thunks_size += code - start;
6464         g_assert (code - start <= size);
6465
6466         return start;
6467 }
6468
6469 MonoMethod*
6470 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6471 {
6472         return regs [MONO_ARCH_IMT_REG];
6473 }
6474
6475 MonoObject*
6476 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6477 {
6478         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6479 }
6480
6481 void
6482 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6483 {
6484         /* Done by the implementation of the CALL_MEMBASE opcodes */
6485 }
6486 #endif
6487
6488 MonoVTable*
6489 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6490 {
6491         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6492 }
6493
6494 MonoInst*
6495 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6496 {
6497         MonoInst *ins = NULL;
6498
6499         if (cmethod->klass == mono_defaults.math_class) {
6500                 if (strcmp (cmethod->name, "Sin") == 0) {
6501                         MONO_INST_NEW (cfg, ins, OP_SIN);
6502                         ins->inst_i0 = args [0];
6503                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6504                         MONO_INST_NEW (cfg, ins, OP_COS);
6505                         ins->inst_i0 = args [0];
6506                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6507                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6508                         ins->inst_i0 = args [0];
6509                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6510                         MONO_INST_NEW (cfg, ins, OP_ABS);
6511                         ins->inst_i0 = args [0];
6512                 }
6513
6514                 if (cfg->opt & MONO_OPT_CMOV) {
6515                         int opcode = 0;
6516
6517                         if (strcmp (cmethod->name, "Min") == 0) {
6518                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6519                                         opcode = OP_IMIN;
6520                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6521                                         opcode = OP_IMIN_UN;
6522                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6523                                         opcode = OP_LMIN;
6524                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6525                                         opcode = OP_LMIN_UN;
6526                         } else if (strcmp (cmethod->name, "Max") == 0) {
6527                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6528                                         opcode = OP_IMAX;
6529                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6530                                         opcode = OP_IMAX_UN;
6531                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6532                                         opcode = OP_LMAX;
6533                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6534                                         opcode = OP_LMAX_UN;
6535                         }
6536
6537                         if (opcode) {
6538                                 MONO_INST_NEW (cfg, ins, opcode);
6539                                 ins->inst_i0 = args [0];
6540                                 ins->inst_i1 = args [1];
6541                         }
6542                 }
6543
6544 #if 0
6545                 /* OP_FREM is not IEEE compatible */
6546                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6547                         MONO_INST_NEW (cfg, ins, OP_FREM);
6548                         ins->inst_i0 = args [0];
6549                         ins->inst_i1 = args [1];
6550                 }
6551 #endif
6552         }
6553
6554         return ins;
6555 }
6556
6557 MonoInst*
6558 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6559 {
6560         MonoInst *ins = NULL;
6561         int opcode = 0;
6562
6563         if (cmethod->klass == mono_defaults.math_class) {
6564                 if (strcmp (cmethod->name, "Sin") == 0) {
6565                         opcode = OP_SIN;
6566                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6567                         opcode = OP_COS;
6568                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6569                         opcode = OP_SQRT;
6570                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6571                         opcode = OP_ABS;
6572                 }
6573
6574                 if (opcode) {
6575                         MONO_INST_NEW (cfg, ins, opcode);
6576                         ins->type = STACK_R8;
6577                         ins->dreg = mono_alloc_freg (cfg);
6578                         ins->sreg1 = args [0]->dreg;
6579                         MONO_ADD_INS (cfg->cbb, ins);
6580                 }
6581
6582                 opcode = 0;
6583                 if (cfg->opt & MONO_OPT_CMOV) {
6584                         if (strcmp (cmethod->name, "Min") == 0) {
6585                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6586                                         opcode = OP_IMIN;
6587                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6588                                         opcode = OP_IMIN_UN;
6589                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6590                                         opcode = OP_LMIN;
6591                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6592                                         opcode = OP_LMIN_UN;
6593                         } else if (strcmp (cmethod->name, "Max") == 0) {
6594                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6595                                         opcode = OP_IMAX;
6596                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6597                                         opcode = OP_IMAX_UN;
6598                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6599                                         opcode = OP_LMAX;
6600                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6601                                         opcode = OP_LMAX_UN;
6602                         }
6603                 }
6604
6605                 if (opcode) {
6606                         MONO_INST_NEW (cfg, ins, opcode);
6607                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6608                         ins->dreg = mono_alloc_ireg (cfg);
6609                         ins->sreg1 = args [0]->dreg;
6610                         ins->sreg2 = args [1]->dreg;
6611                         MONO_ADD_INS (cfg->cbb, ins);
6612                 }
6613
6614 #if 0
6615                 /* OP_FREM is not IEEE compatible */
6616                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6617                         MONO_INST_NEW (cfg, ins, OP_FREM);
6618                         ins->inst_i0 = args [0];
6619                         ins->inst_i1 = args [1];
6620                 }
6621 #endif
6622         }
6623
6624         /*
6625          * Can't implement CompareExchange methods this way since they have
6626          * three arguments.
6627          */
6628
6629         return ins;
6630 }
6631
6632 gboolean
6633 mono_arch_print_tree (MonoInst *tree, int arity)
6634 {
6635         return 0;
6636 }
6637
6638 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6639 {
6640         MonoInst* ins;
6641
6642         if (appdomain_tls_offset == -1)
6643                 return NULL;
6644
6645         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6646         ins->inst_offset = appdomain_tls_offset;
6647         return ins;
6648 }
6649
6650 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6651 {
6652         MonoInst* ins;
6653
6654         if (thread_tls_offset == -1)
6655                 return NULL;
6656
6657         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6658         ins->inst_offset = thread_tls_offset;
6659         return ins;
6660 }
6661
6662 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6663
6664 gpointer
6665 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6666 {
6667         switch (reg) {
6668         case AMD64_RCX: return (gpointer)ctx->rcx;
6669         case AMD64_RDX: return (gpointer)ctx->rdx;
6670         case AMD64_RBX: return (gpointer)ctx->rbx;
6671         case AMD64_RBP: return (gpointer)ctx->rbp;
6672         case AMD64_RSP: return (gpointer)ctx->rsp;
6673         default:
6674                 if (reg < 8)
6675                         return _CTX_REG (ctx, rax, reg);
6676                 else if (reg >= 12)
6677                         return _CTX_REG (ctx, r12, reg - 12);
6678                 else
6679                         g_assert_not_reached ();
6680         }
6681 }