mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 static void
 178 amd64_patch (unsigned char* code, gpointer target)
 179 {
 180         guint8 rex = 0;
 181
 182         /* Skip REX */
 183         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 184                 rex = code [0];
 185                 code += 1;
 186         }
 187
 188         if ((code [0] & 0xf8) == 0xb8) {
 189                 /* amd64_set_reg_template */
 190                 *(guint64*)(code + 1) = (guint64)target;
 191         }
 192         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 193                 /* mov 0(%rip), %dreg */
 194                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 195         }
 196         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 197                 /* call *<OFFSET>(%rip) */
 198                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 199         }
 200         else if (code [0] == 0xe8) {
 201                 /* call <DISP> */
 202                 gint64 disp = (guint8*)target - (guint8*)code;
 203                 g_assert (amd64_is_imm32 (disp));
 204                 x86_patch (code, (unsigned char*)target);
 205         }
 206         else
 207                 x86_patch (code, (unsigned char*)target);
 208 }
 209
 210 void
 211 mono_amd64_patch (unsigned char* code, gpointer target)
 212 {
 213         amd64_patch (code, target);
 214 }
 215
 216 #define DEBUG(a) if (cfg->verbose_level > 1) a
 217
 218 static void inline
 219 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 ainfo->arg_size = sizeof (mgreg_t);
 226                 /* Since the same stack slot size is used for all arg */
 227                 /*  types, it needs to be big enough to hold them all */
 228                 (*stack_size) += sizeof(mgreg_t);
 229     }
 230     else {
 231                 ainfo->storage = ArgInIReg;
 232                 ainfo->reg = param_regs [*gr];
 233                 (*gr) ++;
 234     }
 235 }
 236
 237 static void inline
 238 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 239 {
 240     ainfo->offset = *stack_size;
 241
 242     if (*gr >= FLOAT_PARAM_REGS) {
 243                 ainfo->storage = ArgOnStack;
 244                 ainfo->arg_size = sizeof (mgreg_t);
 245                 /* Since the same stack slot size is used for both float */
 246                 /*  types, it needs to be big enough to hold them both */
 247                 (*stack_size) += sizeof(mgreg_t);
 248     }
 249     else {
 250                 /* A double register */
 251                 if (is_double)
 252                         ainfo->storage = ArgInDoubleSSEReg;
 253                 else
 254                         ainfo->storage = ArgInFloatSSEReg;
 255                 ainfo->reg = *gr;
 256                 (*gr) += 1;
 257     }
 258 }
 259
 260 typedef enum ArgumentClass {
 261         ARG_CLASS_NO_CLASS,
 262         ARG_CLASS_MEMORY,
 263         ARG_CLASS_INTEGER,
 264         ARG_CLASS_SSE
 265 } ArgumentClass;
 266
 267 static ArgumentClass
 268 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 269 {
 270         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 271         MonoType *ptype;
 272
 273         ptype = mini_get_underlying_type (type);
 274         switch (ptype->type) {
 275         case MONO_TYPE_I1:
 276         case MONO_TYPE_U1:
 277         case MONO_TYPE_I2:
 278         case MONO_TYPE_U2:
 279         case MONO_TYPE_I4:
 280         case MONO_TYPE_U4:
 281         case MONO_TYPE_I:
 282         case MONO_TYPE_U:
 283         case MONO_TYPE_STRING:
 284         case MONO_TYPE_OBJECT:
 285         case MONO_TYPE_CLASS:
 286         case MONO_TYPE_SZARRAY:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_ARRAY:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 static int
 342 count_fields_nested (MonoClass *klass)
 343 {
 344         MonoMarshalType *info;
 345         int i, count;
 346
 347         info = mono_marshal_load_type_info (klass);
 348         g_assert(info);
 349         count = 0;
 350         for (i = 0; i < info->num_fields; ++i) {
 351                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 352                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 353                 else
 354                         count ++;
 355         }
 356         return count;
 357 }
 358
 359 static int
 360 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 361 {
 362         MonoMarshalType *info;
 363         int i;
 364
 365         info = mono_marshal_load_type_info (klass);
 366         g_assert(info);
 367         for (i = 0; i < info->num_fields; ++i) {
 368                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 369                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 370                 } else {
 371                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 372                         fields [index].offset += offset;
 373                         index ++;
 374                 }
 375         }
 376         return index;
 377 }
 378
 379 #ifdef TARGET_WIN32
 380 static void
 381 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 382                                          gboolean is_return,
 383                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 384 {
 385         guint32 size, i, nfields;
 386         guint32 argsize = 8;
 387         ArgumentClass arg_class;
 388         MonoMarshalType *info = NULL;
 389         MonoMarshalField *fields = NULL;
 390         MonoClass *klass;
 391         gboolean pass_on_stack = FALSE;
 392
 393         klass = mono_class_from_mono_type (type);
 394         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 395         if (!sig->pinvoke)
 396                 pass_on_stack = TRUE;
 397
 398         /* If this struct can't be split up naturally into 8-byte */
 399         /* chunks (registers), pass it on the stack.              */
 400         if (sig->pinvoke && !pass_on_stack) {
 401                 guint32 align;
 402                 guint32 field_size;
 403
 404                 info = mono_marshal_load_type_info (klass);
 405                 g_assert (info);
 406
 407                 /*
 408                  * Collect field information recursively to be able to
 409                  * handle nested structures.
 410                  */
 411                 nfields = count_fields_nested (klass);
 412                 fields = g_new0 (MonoMarshalField, nfields);
 413                 collect_field_info_nested (klass, fields, 0, 0);
 414
 415                 for (i = 0; i < nfields; ++i) {
 416                         field_size = mono_marshal_type_size (fields [i].field->type,
 417                                                            fields [i].mspec,
 418                                                            &align, TRUE, klass->unicode);
 419                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 420                                 pass_on_stack = TRUE;
 421                                 break;
 422                         }
 423                 }
 424         }
 425
 426         if (pass_on_stack) {
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 431                 if (!is_return)
 432                         ainfo->arg_size = ALIGN_TO (size, 8);
 433
 434                 g_free (fields);
 435                 return;
 436         }
 437
 438         if (!sig->pinvoke) {
 439                 int n = mono_class_value_size (klass, NULL);
 440
 441                 argsize = n;
 442
 443                 if (n > 8)
 444                         arg_class = ARG_CLASS_MEMORY;
 445                 else
 446                         /* Always pass in 1 integer register */
 447                         arg_class = ARG_CLASS_INTEGER;
 448         } else {
 449                 g_assert (info);
 450
 451                 if (!fields) {
 452                         ainfo->storage = ArgValuetypeInReg;
 453                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 454                         return;
 455                 }
 456
 457                 switch (info->native_size) {
 458                 case 1: case 2: case 4: case 8:
 459                         break;
 460                 default:
 461                         if (is_return) {
 462                                 ainfo->storage = ArgValuetypeAddrInIReg;
 463                                 ainfo->offset = *stack_size;
 464                                 *stack_size += ALIGN_TO (info->native_size, 8);
 465                         }
 466                         else {
 467                                 ainfo->storage = ArgValuetypeAddrInIReg;
 468
 469                                 if (*gr < PARAM_REGS) {
 470                                         ainfo->pair_storage [0] = ArgInIReg;
 471                                         ainfo->pair_regs [0] = param_regs [*gr];
 472                                         (*gr) ++;
 473                                 }
 474                                 else {
 475                                         ainfo->pair_storage [0] = ArgOnStack;
 476                                         ainfo->offset = *stack_size;
 477                                         ainfo->arg_size = sizeof (mgreg_t);
 478                                         *stack_size += 8;
 479                                 }
 480                         }
 481
 482                         g_free (fields);
 483                         return;
 484                 }
 485
 486                 int size;
 487                 guint32 align;
 488                 ArgumentClass class1;
 489
 490                 if (nfields == 0)
 491                         class1 = ARG_CLASS_MEMORY;
 492                 else
 493                         class1 = ARG_CLASS_NO_CLASS;
 494                 for (i = 0; i < nfields; ++i) {
 495                         size = mono_marshal_type_size (fields [i].field->type,
 496                                                                                    fields [i].mspec,
 497                                                                                    &align, TRUE, klass->unicode);
 498                         /* How far into this quad this data extends.*/
 499                         /* (8 is size of quad) */
 500                         argsize = fields [i].offset + size;
 501
 502                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 503                 }
 504                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 505                 arg_class = class1;
 506         }
 507
 508         g_free (fields);
 509
 510         /* Allocate registers */
 511         {
 512                 int orig_gr = *gr;
 513                 int orig_fr = *fr;
 514
 515                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 516                         argsize ++;
 517
 518                 ainfo->storage = ArgValuetypeInReg;
 519                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 520                 ainfo->pair_size [0] = argsize;
 521                 ainfo->pair_size [1] = 0;
 522                 ainfo->nregs = 1;
 523                 switch (arg_class) {
 524                 case ARG_CLASS_INTEGER:
 525                         if (*gr >= PARAM_REGS)
 526                                 arg_class = ARG_CLASS_MEMORY;
 527                         else {
 528                                 ainfo->pair_storage [0] = ArgInIReg;
 529                                 if (is_return)
 530                                         ainfo->pair_regs [0] = return_regs [*gr];
 531                                 else
 532                                         ainfo->pair_regs [0] = param_regs [*gr];
 533                                 (*gr) ++;
 534                         }
 535                         break;
 536                 case ARG_CLASS_SSE:
 537                         if (*fr >= FLOAT_PARAM_REGS)
 538                                 arg_class = ARG_CLASS_MEMORY;
 539                         else {
 540                                 if (argsize <= 4)
 541                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 542                                 else
 543                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 544                                 ainfo->pair_regs [0] = *fr;
 545                                 (*fr) ++;
 546                         }
 547                         break;
 548                 case ARG_CLASS_MEMORY:
 549                         break;
 550                 default:
 551                         g_assert_not_reached ();
 552                 }
 553
 554                 if (arg_class == ARG_CLASS_MEMORY) {
 555                         /* Revert possible register assignments */
 556                         *gr = orig_gr;
 557                         *fr = orig_fr;
 558
 559                         ainfo->offset = *stack_size;
 560                         *stack_size += sizeof (mgreg_t);
 561                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 562                         if (!is_return)
 563                                 ainfo->arg_size = sizeof (mgreg_t);
 564                 }
 565         }
 566 }
 567 #endif /* TARGET_WIN32 */
 568
 569 static void
 570 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 571                            gboolean is_return,
 572                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 573 {
 574 #ifdef TARGET_WIN32
 575         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 576 #else
 577         guint32 size, quad, nquads, i, nfields;
 578         /* Keep track of the size used in each quad so we can */
 579         /* use the right size when copying args/return vars.  */
 580         guint32 quadsize [2] = {8, 8};
 581         ArgumentClass args [2];
 582         MonoMarshalType *info = NULL;
 583         MonoMarshalField *fields = NULL;
 584         MonoClass *klass;
 585         gboolean pass_on_stack = FALSE;
 586
 587         klass = mono_class_from_mono_type (type);
 588         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 589         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 590                 /* We pass and return vtypes of size 8 in a register */
 591         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 592                 pass_on_stack = TRUE;
 593         }
 594
 595         /* If this struct can't be split up naturally into 8-byte */
 596         /* chunks (registers), pass it on the stack.              */
 597         if (sig->pinvoke && !pass_on_stack) {
 598                 guint32 align;
 599                 guint32 field_size;
 600
 601                 info = mono_marshal_load_type_info (klass);
 602                 g_assert (info);
 603
 604                 /*
 605                  * Collect field information recursively to be able to
 606                  * handle nested structures.
 607                  */
 608                 nfields = count_fields_nested (klass);
 609                 fields = g_new0 (MonoMarshalField, nfields);
 610                 collect_field_info_nested (klass, fields, 0, 0);
 611
 612                 for (i = 0; i < nfields; ++i) {
 613                         field_size = mono_marshal_type_size (fields [i].field->type,
 614                                                            fields [i].mspec,
 615                                                            &align, TRUE, klass->unicode);
 616                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 617                                 pass_on_stack = TRUE;
 618                                 break;
 619                         }
 620                 }
 621         }
 622
 623         if (size == 0) {
 624                 ainfo->storage = ArgValuetypeInReg;
 625                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 626                 return;
 627         }
 628
 629         if (pass_on_stack) {
 630                 /* Allways pass in memory */
 631                 ainfo->offset = *stack_size;
 632                 *stack_size += ALIGN_TO (size, 8);
 633                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 634                 if (!is_return)
 635                         ainfo->arg_size = ALIGN_TO (size, 8);
 636
 637                 g_free (fields);
 638                 return;
 639         }
 640
 641         if (size > 8)
 642                 nquads = 2;
 643         else
 644                 nquads = 1;
 645
 646         if (!sig->pinvoke) {
 647                 int n = mono_class_value_size (klass, NULL);
 648
 649                 quadsize [0] = n >= 8 ? 8 : n;
 650                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 651
 652                 /* Always pass in 1 or 2 integer registers */
 653                 args [0] = ARG_CLASS_INTEGER;
 654                 args [1] = ARG_CLASS_INTEGER;
 655                 /* Only the simplest cases are supported */
 656                 if (is_return && nquads != 1) {
 657                         args [0] = ARG_CLASS_MEMORY;
 658                         args [1] = ARG_CLASS_MEMORY;
 659                 }
 660         } else {
 661                 /*
 662                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 663                  * The X87 and SSEUP stuff is left out since there are no such types in
 664                  * the CLR.
 665                  */
 666                 g_assert (info);
 667
 668                 if (!fields) {
 669                         ainfo->storage = ArgValuetypeInReg;
 670                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 671                         return;
 672                 }
 673
 674                 if (info->native_size > 16) {
 675                         ainfo->offset = *stack_size;
 676                         *stack_size += ALIGN_TO (info->native_size, 8);
 677                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 678                         if (!is_return)
 679                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 680
 681                         g_free (fields);
 682                         return;
 683                 }
 684
 685                 args [0] = ARG_CLASS_NO_CLASS;
 686                 args [1] = ARG_CLASS_NO_CLASS;
 687                 for (quad = 0; quad < nquads; ++quad) {
 688                         int size;
 689                         guint32 align;
 690                         ArgumentClass class1;
 691
 692                         if (nfields == 0)
 693                                 class1 = ARG_CLASS_MEMORY;
 694                         else
 695                                 class1 = ARG_CLASS_NO_CLASS;
 696                         for (i = 0; i < nfields; ++i) {
 697                                 size = mono_marshal_type_size (fields [i].field->type,
 698                                                                                            fields [i].mspec,
 699                                                                                            &align, TRUE, klass->unicode);
 700                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 701                                         /* Unaligned field */
 702                                         NOT_IMPLEMENTED;
 703                                 }
 704
 705                                 /* Skip fields in other quad */
 706                                 if ((quad == 0) && (fields [i].offset >= 8))
 707                                         continue;
 708                                 if ((quad == 1) && (fields [i].offset < 8))
 709                                         continue;
 710
 711                                 /* How far into this quad this data extends.*/
 712                                 /* (8 is size of quad) */
 713                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 714
 715                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 716                         }
 717                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 718                         args [quad] = class1;
 719                 }
 720         }
 721
 722         g_free (fields);
 723
 724         /* Post merger cleanup */
 725         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 726                 args [0] = args [1] = ARG_CLASS_MEMORY;
 727
 728         /* Allocate registers */
 729         {
 730                 int orig_gr = *gr;
 731                 int orig_fr = *fr;
 732
 733                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 734                         quadsize [0] ++;
 735                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 736                         quadsize [1] ++;
 737
 738                 ainfo->storage = ArgValuetypeInReg;
 739                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 740                 g_assert (quadsize [0] <= 8);
 741                 g_assert (quadsize [1] <= 8);
 742                 ainfo->pair_size [0] = quadsize [0];
 743                 ainfo->pair_size [1] = quadsize [1];
 744                 ainfo->nregs = nquads;
 745                 for (quad = 0; quad < nquads; ++quad) {
 746                         switch (args [quad]) {
 747                         case ARG_CLASS_INTEGER:
 748                                 if (*gr >= PARAM_REGS)
 749                                         args [quad] = ARG_CLASS_MEMORY;
 750                                 else {
 751                                         ainfo->pair_storage [quad] = ArgInIReg;
 752                                         if (is_return)
 753                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 754                                         else
 755                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 756                                         (*gr) ++;
 757                                 }
 758                                 break;
 759                         case ARG_CLASS_SSE:
 760                                 if (*fr >= FLOAT_PARAM_REGS)
 761                                         args [quad] = ARG_CLASS_MEMORY;
 762                                 else {
 763                                         if (quadsize[quad] <= 4)
 764                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 765                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 766                                         ainfo->pair_regs [quad] = *fr;
 767                                         (*fr) ++;
 768                                 }
 769                                 break;
 770                         case ARG_CLASS_MEMORY:
 771                                 break;
 772                         default:
 773                                 g_assert_not_reached ();
 774                         }
 775                 }
 776
 777                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 778                         int arg_size;
 779                         /* Revert possible register assignments */
 780                         *gr = orig_gr;
 781                         *fr = orig_fr;
 782
 783                         ainfo->offset = *stack_size;
 784                         if (sig->pinvoke)
 785                                 arg_size = ALIGN_TO (info->native_size, 8);
 786                         else
 787                                 arg_size = nquads * sizeof(mgreg_t);
 788                         *stack_size += arg_size;
 789                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 790                         if (!is_return)
 791                                 ainfo->arg_size = arg_size;
 792                 }
 793         }
 794 #endif /* !TARGET_WIN32 */
 795 }
 796
 797 /*
 798  * get_call_info:
 799  *
 800  * Obtain information about a call according to the calling convention.
 801  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 802  * Draft Version 0.23" document for more information.
 803  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 804  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 805  */
 806 static CallInfo*
 807 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 808 {
 809         guint32 i, gr, fr, pstart;
 810         MonoType *ret_type;
 811         int n = sig->hasthis + sig->param_count;
 812         guint32 stack_size = 0;
 813         CallInfo *cinfo;
 814         gboolean is_pinvoke = sig->pinvoke;
 815
 816         if (mp)
 817                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 818         else
 819                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 820
 821         cinfo->nargs = n;
 822         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 823
 824         gr = 0;
 825         fr = 0;
 826
 827 #ifdef TARGET_WIN32
 828         /* Reserve space where the callee can save the argument registers */
 829         stack_size = 4 * sizeof (mgreg_t);
 830 #endif
 831
 832         /* return value */
 833         ret_type = mini_get_underlying_type (sig->ret);
 834         switch (ret_type->type) {
 835         case MONO_TYPE_I1:
 836         case MONO_TYPE_U1:
 837         case MONO_TYPE_I2:
 838         case MONO_TYPE_U2:
 839         case MONO_TYPE_I4:
 840         case MONO_TYPE_U4:
 841         case MONO_TYPE_I:
 842         case MONO_TYPE_U:
 843         case MONO_TYPE_PTR:
 844         case MONO_TYPE_FNPTR:
 845         case MONO_TYPE_CLASS:
 846         case MONO_TYPE_OBJECT:
 847         case MONO_TYPE_SZARRAY:
 848         case MONO_TYPE_ARRAY:
 849         case MONO_TYPE_STRING:
 850                 cinfo->ret.storage = ArgInIReg;
 851                 cinfo->ret.reg = AMD64_RAX;
 852                 break;
 853         case MONO_TYPE_U8:
 854         case MONO_TYPE_I8:
 855                 cinfo->ret.storage = ArgInIReg;
 856                 cinfo->ret.reg = AMD64_RAX;
 857                 break;
 858         case MONO_TYPE_R4:
 859                 cinfo->ret.storage = ArgInFloatSSEReg;
 860                 cinfo->ret.reg = AMD64_XMM0;
 861                 break;
 862         case MONO_TYPE_R8:
 863                 cinfo->ret.storage = ArgInDoubleSSEReg;
 864                 cinfo->ret.reg = AMD64_XMM0;
 865                 break;
 866         case MONO_TYPE_GENERICINST:
 867                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 868                         cinfo->ret.storage = ArgInIReg;
 869                         cinfo->ret.reg = AMD64_RAX;
 870                         break;
 871                 }
 872                 if (mini_is_gsharedvt_type (ret_type)) {
 873                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 874                         break;
 875                 }
 876                 /* fall through */
 877         case MONO_TYPE_VALUETYPE:
 878         case MONO_TYPE_TYPEDBYREF: {
 879                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 880
 881                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 882                 g_assert (cinfo->ret.storage != ArgInIReg);
 883                 break;
 884         }
 885         case MONO_TYPE_VAR:
 886         case MONO_TYPE_MVAR:
 887                 g_assert (mini_is_gsharedvt_type (ret_type));
 888                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 889                 break;
 890         case MONO_TYPE_VOID:
 891                 break;
 892         default:
 893                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 894         }
 895
 896         pstart = 0;
 897         /*
 898          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 899          * the first argument, allowing 'this' to be always passed in the first arg reg.
 900          * Also do this if the first argument is a reference type, since virtual calls
 901          * are sometimes made using calli without sig->hasthis set, like in the delegate
 902          * invoke wrappers.
 903          */
 904         ArgStorage ret_storage = cinfo->ret.storage;
 905         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 906                 if (sig->hasthis) {
 907                         add_general (&gr, &stack_size, cinfo->args + 0);
 908                 } else {
 909                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 910                         pstart = 1;
 911                 }
 912                 add_general (&gr, &stack_size, &cinfo->ret);
 913                 cinfo->ret.storage = ret_storage;
 914                 cinfo->vret_arg_index = 1;
 915         } else {
 916                 /* this */
 917                 if (sig->hasthis)
 918                         add_general (&gr, &stack_size, cinfo->args + 0);
 919
 920                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 921                         add_general (&gr, &stack_size, &cinfo->ret);
 922                         cinfo->ret.storage = ret_storage;
 923                 }
 924         }
 925
 926         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 927                 gr = PARAM_REGS;
 928                 fr = FLOAT_PARAM_REGS;
 929
 930                 /* Emit the signature cookie just before the implicit arguments */
 931                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 932         }
 933
 934         for (i = pstart; i < sig->param_count; ++i) {
 935                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 936                 MonoType *ptype;
 937
 938 #ifdef TARGET_WIN32
 939                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 940                 if (gr > fr)
 941                         fr = gr;
 942                 else if (fr > gr)
 943                         gr = fr;
 944 #endif
 945
 946                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 947                         /* We allways pass the sig cookie on the stack for simplicity */
 948                         /*
 949                          * Prevent implicit arguments + the sig cookie from being passed
 950                          * in registers.
 951                          */
 952                         gr = PARAM_REGS;
 953                         fr = FLOAT_PARAM_REGS;
 954
 955                         /* Emit the signature cookie just before the implicit arguments */
 956                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 957                 }
 958
 959                 ptype = mini_get_underlying_type (sig->params [i]);
 960                 switch (ptype->type) {
 961                 case MONO_TYPE_I1:
 962                 case MONO_TYPE_U1:
 963                         add_general (&gr, &stack_size, ainfo);
 964                         break;
 965                 case MONO_TYPE_I2:
 966                 case MONO_TYPE_U2:
 967                         add_general (&gr, &stack_size, ainfo);
 968                         break;
 969                 case MONO_TYPE_I4:
 970                 case MONO_TYPE_U4:
 971                         add_general (&gr, &stack_size, ainfo);
 972                         break;
 973                 case MONO_TYPE_I:
 974                 case MONO_TYPE_U:
 975                 case MONO_TYPE_PTR:
 976                 case MONO_TYPE_FNPTR:
 977                 case MONO_TYPE_CLASS:
 978                 case MONO_TYPE_OBJECT:
 979                 case MONO_TYPE_STRING:
 980                 case MONO_TYPE_SZARRAY:
 981                 case MONO_TYPE_ARRAY:
 982                         add_general (&gr, &stack_size, ainfo);
 983                         break;
 984                 case MONO_TYPE_GENERICINST:
 985                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 986                                 add_general (&gr, &stack_size, ainfo);
 987                                 break;
 988                         }
 989                         if (mini_is_gsharedvt_variable_type (ptype)) {
 990                                 /* gsharedvt arguments are passed by ref */
 991                                 add_general (&gr, &stack_size, ainfo);
 992                                 if (ainfo->storage == ArgInIReg)
 993                                         ainfo->storage = ArgGSharedVtInReg;
 994                                 else
 995                                         ainfo->storage = ArgGSharedVtOnStack;
 996                                 break;
 997                         }
 998                         /* fall through */
 999                 case MONO_TYPE_VALUETYPE:
1000                 case MONO_TYPE_TYPEDBYREF:
1001                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1002                         break;
1003                 case MONO_TYPE_U8:
1004
1005                 case MONO_TYPE_I8:
1006                         add_general (&gr, &stack_size, ainfo);
1007                         break;
1008                 case MONO_TYPE_R4:
1009                         add_float (&fr, &stack_size, ainfo, FALSE);
1010                         break;
1011                 case MONO_TYPE_R8:
1012                         add_float (&fr, &stack_size, ainfo, TRUE);
1013                         break;
1014                 case MONO_TYPE_VAR:
1015                 case MONO_TYPE_MVAR:
1016                         /* gsharedvt arguments are passed by ref */
1017                         g_assert (mini_is_gsharedvt_type (ptype));
1018                         add_general (&gr, &stack_size, ainfo);
1019                         if (ainfo->storage == ArgInIReg)
1020                                 ainfo->storage = ArgGSharedVtInReg;
1021                         else
1022                                 ainfo->storage = ArgGSharedVtOnStack;
1023                         break;
1024                 default:
1025                         g_assert_not_reached ();
1026                 }
1027         }
1028
1029         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1030                 gr = PARAM_REGS;
1031                 fr = FLOAT_PARAM_REGS;
1032
1033                 /* Emit the signature cookie just before the implicit arguments */
1034                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1035         }
1036
1037         cinfo->stack_usage = stack_size;
1038         cinfo->reg_usage = gr;
1039         cinfo->freg_usage = fr;
1040         return cinfo;
1041 }
1042
1043 /*
1044  * mono_arch_get_argument_info:
1045  * @csig:  a method signature
1046  * @param_count: the number of parameters to consider
1047  * @arg_info: an array to store the result infos
1048  *
1049  * Gathers information on parameters such as size, alignment and
1050  * padding. arg_info should be large enought to hold param_count + 1 entries.
1051  *
1052  * Returns the size of the argument area on the stack.
1053  */
1054 int
1055 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1056 {
1057         int k;
1058         CallInfo *cinfo = get_call_info (NULL, csig);
1059         guint32 args_size = cinfo->stack_usage;
1060
1061         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1062         if (csig->hasthis) {
1063                 arg_info [0].offset = 0;
1064         }
1065
1066         for (k = 0; k < param_count; k++) {
1067                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1068                 /* FIXME: */
1069                 arg_info [k + 1].size = 0;
1070         }
1071
1072         g_free (cinfo);
1073
1074         return args_size;
1075 }
1076
1077 gboolean
1078 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1079 {
1080         CallInfo *c1, *c2;
1081         gboolean res;
1082         MonoType *callee_ret;
1083
1084         c1 = get_call_info (NULL, caller_sig);
1085         c2 = get_call_info (NULL, callee_sig);
1086         res = c1->stack_usage >= c2->stack_usage;
1087         callee_ret = mini_get_underlying_type (callee_sig->ret);
1088         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1089                 /* An address on the callee's stack is passed as the first argument */
1090                 res = FALSE;
1091
1092         g_free (c1);
1093         g_free (c2);
1094
1095         return res;
1096 }
1097
1098 /*
1099  * Initialize the cpu to execute managed code.
1100  */
1101 void
1102 mono_arch_cpu_init (void)
1103 {
1104 #ifndef _MSC_VER
1105         guint16 fpcw;
1106
1107         /* spec compliance requires running with double precision */
1108         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1109         fpcw &= ~X86_FPCW_PRECC_MASK;
1110         fpcw |= X86_FPCW_PREC_DOUBLE;
1111         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1112         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1113 #else
1114         /* TODO: This is crashing on Win64 right now.
1115         * _control87 (_PC_53, MCW_PC);
1116         */
1117 #endif
1118 }
1119
1120 /*
1121  * Initialize architecture specific code.
1122  */
1123 void
1124 mono_arch_init (void)
1125 {
1126         mono_os_mutex_init_recursive (&mini_arch_mutex);
1127
1128         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1129         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1130         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1131         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1132 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1133         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1134 #endif
1135
1136         if (!mono_aot_only)
1137                 bp_trampoline = mini_get_breakpoint_trampoline ();
1138 }
1139
1140 /*
1141  * Cleanup architecture specific code.
1142  */
1143 void
1144 mono_arch_cleanup (void)
1145 {
1146         mono_os_mutex_destroy (&mini_arch_mutex);
1147 }
1148
1149 /*
1150  * This function returns the optimizations supported on this cpu.
1151  */
1152 guint32
1153 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1154 {
1155         guint32 opts = 0;
1156
1157         *exclude_mask = 0;
1158
1159         if (mono_hwcap_x86_has_cmov) {
1160                 opts |= MONO_OPT_CMOV;
1161
1162                 if (mono_hwcap_x86_has_fcmov)
1163                         opts |= MONO_OPT_FCMOV;
1164                 else
1165                         *exclude_mask |= MONO_OPT_FCMOV;
1166         } else {
1167                 *exclude_mask |= MONO_OPT_CMOV;
1168         }
1169
1170         return opts;
1171 }
1172
1173 /*
1174  * This function test for all SSE functions supported.
1175  *
1176  * Returns a bitmask corresponding to all supported versions.
1177  *
1178  */
1179 guint32
1180 mono_arch_cpu_enumerate_simd_versions (void)
1181 {
1182         guint32 sse_opts = 0;
1183
1184         if (mono_hwcap_x86_has_sse1)
1185                 sse_opts |= SIMD_VERSION_SSE1;
1186
1187         if (mono_hwcap_x86_has_sse2)
1188                 sse_opts |= SIMD_VERSION_SSE2;
1189
1190         if (mono_hwcap_x86_has_sse3)
1191                 sse_opts |= SIMD_VERSION_SSE3;
1192
1193         if (mono_hwcap_x86_has_ssse3)
1194                 sse_opts |= SIMD_VERSION_SSSE3;
1195
1196         if (mono_hwcap_x86_has_sse41)
1197                 sse_opts |= SIMD_VERSION_SSE41;
1198
1199         if (mono_hwcap_x86_has_sse42)
1200                 sse_opts |= SIMD_VERSION_SSE42;
1201
1202         if (mono_hwcap_x86_has_sse4a)
1203                 sse_opts |= SIMD_VERSION_SSE4a;
1204
1205         return sse_opts;
1206 }
1207
1208 #ifndef DISABLE_JIT
1209
1210 GList *
1211 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1212 {
1213         GList *vars = NULL;
1214         int i;
1215
1216         for (i = 0; i < cfg->num_varinfo; i++) {
1217                 MonoInst *ins = cfg->varinfo [i];
1218                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1219
1220                 /* unused vars */
1221                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1222                         continue;
1223
1224                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1225                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1226                         continue;
1227
1228                 if (mono_is_regsize_var (ins->inst_vtype)) {
1229                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1230                         g_assert (i == vmv->idx);
1231                         vars = g_list_prepend (vars, vmv);
1232                 }
1233         }
1234
1235         vars = mono_varlist_sort (cfg, vars, 0);
1236
1237         return vars;
1238 }
1239
1240 /**
1241  * mono_arch_compute_omit_fp:
1242  *
1243  *   Determine whenever the frame pointer can be eliminated.
1244  */
1245 static void
1246 mono_arch_compute_omit_fp (MonoCompile *cfg)
1247 {
1248         MonoMethodSignature *sig;
1249         MonoMethodHeader *header;
1250         int i, locals_size;
1251         CallInfo *cinfo;
1252
1253         if (cfg->arch.omit_fp_computed)
1254                 return;
1255
1256         header = cfg->header;
1257
1258         sig = mono_method_signature (cfg->method);
1259
1260         if (!cfg->arch.cinfo)
1261                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1262         cinfo = (CallInfo *)cfg->arch.cinfo;
1263
1264         /*
1265          * FIXME: Remove some of the restrictions.
1266          */
1267         cfg->arch.omit_fp = TRUE;
1268         cfg->arch.omit_fp_computed = TRUE;
1269
1270         if (cfg->disable_omit_fp)
1271                 cfg->arch.omit_fp = FALSE;
1272
1273         if (!debug_omit_fp ())
1274                 cfg->arch.omit_fp = FALSE;
1275         /*
1276         if (cfg->method->save_lmf)
1277                 cfg->arch.omit_fp = FALSE;
1278         */
1279         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1280                 cfg->arch.omit_fp = FALSE;
1281         if (header->num_clauses)
1282                 cfg->arch.omit_fp = FALSE;
1283         if (cfg->param_area)
1284                 cfg->arch.omit_fp = FALSE;
1285         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1286                 cfg->arch.omit_fp = FALSE;
1287         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1288                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1289                 cfg->arch.omit_fp = FALSE;
1290         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1291                 ArgInfo *ainfo = &cinfo->args [i];
1292
1293                 if (ainfo->storage == ArgOnStack) {
1294                         /*
1295                          * The stack offset can only be determined when the frame
1296                          * size is known.
1297                          */
1298                         cfg->arch.omit_fp = FALSE;
1299                 }
1300         }
1301
1302         locals_size = 0;
1303         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1304                 MonoInst *ins = cfg->varinfo [i];
1305                 int ialign;
1306
1307                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1308         }
1309 }
1310
1311 GList *
1312 mono_arch_get_global_int_regs (MonoCompile *cfg)
1313 {
1314         GList *regs = NULL;
1315
1316         mono_arch_compute_omit_fp (cfg);
1317
1318         if (cfg->arch.omit_fp)
1319                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1320
1321         /* We use the callee saved registers for global allocation */
1322         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1323         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1324         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1325         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1326         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1327 #ifdef TARGET_WIN32
1328         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1329         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1330 #endif
1331
1332         return regs;
1333 }
1334
1335 GList*
1336 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1337 {
1338         GList *regs = NULL;
1339         int i;
1340
1341         /* All XMM registers */
1342         for (i = 0; i < 16; ++i)
1343                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1344
1345         return regs;
1346 }
1347
1348 GList*
1349 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1350 {
1351         static GList *r = NULL;
1352
1353         if (r == NULL) {
1354                 GList *regs = NULL;
1355
1356                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1357                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1358                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1359                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1360                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1361                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1362
1363                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1364                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1365                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1366                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1367                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1368                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1369                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1370                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1371
1372                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1373         }
1374
1375         return r;
1376 }
1377
1378 GList*
1379 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1380 {
1381         int i;
1382         static GList *r = NULL;
1383
1384         if (r == NULL) {
1385                 GList *regs = NULL;
1386
1387                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1388                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1389
1390                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1391         }
1392
1393         return r;
1394 }
1395
1396 /*
1397  * mono_arch_regalloc_cost:
1398  *
1399  *  Return the cost, in number of memory references, of the action of
1400  * allocating the variable VMV into a register during global register
1401  * allocation.
1402  */
1403 guint32
1404 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1405 {
1406         MonoInst *ins = cfg->varinfo [vmv->idx];
1407
1408         if (cfg->method->save_lmf)
1409                 /* The register is already saved */
1410                 /* substract 1 for the invisible store in the prolog */
1411                 return (ins->opcode == OP_ARG) ? 0 : 1;
1412         else
1413                 /* push+pop */
1414                 return (ins->opcode == OP_ARG) ? 1 : 2;
1415 }
1416
1417 /*
1418  * mono_arch_fill_argument_info:
1419  *
1420  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1421  * of the method.
1422  */
1423 void
1424 mono_arch_fill_argument_info (MonoCompile *cfg)
1425 {
1426         MonoType *sig_ret;
1427         MonoMethodSignature *sig;
1428         MonoInst *ins;
1429         int i;
1430         CallInfo *cinfo;
1431
1432         sig = mono_method_signature (cfg->method);
1433
1434         cinfo = (CallInfo *)cfg->arch.cinfo;
1435         sig_ret = mini_get_underlying_type (sig->ret);
1436
1437         /*
1438          * Contrary to mono_arch_allocate_vars (), the information should describe
1439          * where the arguments are at the beginning of the method, not where they can be
1440          * accessed during the execution of the method. The later makes no sense for the
1441          * global register allocator, since a variable can be in more than one location.
1442          */
1443         switch (cinfo->ret.storage) {
1444         case ArgInIReg:
1445         case ArgInFloatSSEReg:
1446         case ArgInDoubleSSEReg:
1447                 cfg->ret->opcode = OP_REGVAR;
1448                 cfg->ret->inst_c0 = cinfo->ret.reg;
1449                 break;
1450         case ArgValuetypeInReg:
1451                 cfg->ret->opcode = OP_REGOFFSET;
1452                 cfg->ret->inst_basereg = -1;
1453                 cfg->ret->inst_offset = -1;
1454                 break;
1455         case ArgNone:
1456                 break;
1457         default:
1458                 g_assert_not_reached ();
1459         }
1460
1461         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1462                 ArgInfo *ainfo = &cinfo->args [i];
1463
1464                 ins = cfg->args [i];
1465
1466                 switch (ainfo->storage) {
1467                 case ArgInIReg:
1468                 case ArgInFloatSSEReg:
1469                 case ArgInDoubleSSEReg:
1470                         ins->opcode = OP_REGVAR;
1471                         ins->inst_c0 = ainfo->reg;
1472                         break;
1473                 case ArgOnStack:
1474                         ins->opcode = OP_REGOFFSET;
1475                         ins->inst_basereg = -1;
1476                         ins->inst_offset = -1;
1477                         break;
1478                 case ArgValuetypeInReg:
1479                         /* Dummy */
1480                         ins->opcode = OP_NOP;
1481                         break;
1482                 default:
1483                         g_assert_not_reached ();
1484                 }
1485         }
1486 }
1487
1488 void
1489 mono_arch_allocate_vars (MonoCompile *cfg)
1490 {
1491         MonoType *sig_ret;
1492         MonoMethodSignature *sig;
1493         MonoInst *ins;
1494         int i, offset;
1495         guint32 locals_stack_size, locals_stack_align;
1496         gint32 *offsets;
1497         CallInfo *cinfo;
1498
1499         sig = mono_method_signature (cfg->method);
1500
1501         cinfo = (CallInfo *)cfg->arch.cinfo;
1502         sig_ret = mini_get_underlying_type (sig->ret);
1503
1504         mono_arch_compute_omit_fp (cfg);
1505
1506         /*
1507          * We use the ABI calling conventions for managed code as well.
1508          * Exception: valuetypes are only sometimes passed or returned in registers.
1509          */
1510
1511         /*
1512          * The stack looks like this:
1513          * <incoming arguments passed on the stack>
1514          * <return value>
1515          * <lmf/caller saved registers>
1516          * <locals>
1517          * <spill area>
1518          * <localloc area>  -> grows dynamically
1519          * <params area>
1520          */
1521
1522         if (cfg->arch.omit_fp) {
1523                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1524                 cfg->frame_reg = AMD64_RSP;
1525                 offset = 0;
1526         } else {
1527                 /* Locals are allocated backwards from %fp */
1528                 cfg->frame_reg = AMD64_RBP;
1529                 offset = 0;
1530         }
1531
1532         cfg->arch.saved_iregs = cfg->used_int_regs;
1533         if (cfg->method->save_lmf)
1534                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1535                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1536
1537         if (cfg->arch.omit_fp)
1538                 cfg->arch.reg_save_area_offset = offset;
1539         /* Reserve space for callee saved registers */
1540         for (i = 0; i < AMD64_NREG; ++i)
1541                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1542                         offset += sizeof(mgreg_t);
1543                 }
1544         if (!cfg->arch.omit_fp)
1545                 cfg->arch.reg_save_area_offset = -offset;
1546
1547         if (sig_ret->type != MONO_TYPE_VOID) {
1548                 switch (cinfo->ret.storage) {
1549                 case ArgInIReg:
1550                 case ArgInFloatSSEReg:
1551                 case ArgInDoubleSSEReg:
1552                         cfg->ret->opcode = OP_REGVAR;
1553                         cfg->ret->inst_c0 = cinfo->ret.reg;
1554                         cfg->ret->dreg = cinfo->ret.reg;
1555                         break;
1556                 case ArgValuetypeAddrInIReg:
1557                 case ArgGsharedvtVariableInReg:
1558                         /* The register is volatile */
1559                         cfg->vret_addr->opcode = OP_REGOFFSET;
1560                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1561                         if (cfg->arch.omit_fp) {
1562                                 cfg->vret_addr->inst_offset = offset;
1563                                 offset += 8;
1564                         } else {
1565                                 offset += 8;
1566                                 cfg->vret_addr->inst_offset = -offset;
1567                         }
1568                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1569                                 printf ("vret_addr =");
1570                                 mono_print_ins (cfg->vret_addr);
1571                         }
1572                         break;
1573                 case ArgValuetypeInReg:
1574                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1575                         cfg->ret->opcode = OP_REGOFFSET;
1576                         cfg->ret->inst_basereg = cfg->frame_reg;
1577                         if (cfg->arch.omit_fp) {
1578                                 cfg->ret->inst_offset = offset;
1579                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1580                         } else {
1581                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1582                                 cfg->ret->inst_offset = - offset;
1583                         }
1584                         break;
1585                 default:
1586                         g_assert_not_reached ();
1587                 }
1588         }
1589
1590         /* Allocate locals */
1591         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1592         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1593                 char *mname = mono_method_full_name (cfg->method, TRUE);
1594                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1595                 g_free (mname);
1596                 return;
1597         }
1598
1599         if (locals_stack_align) {
1600                 offset += (locals_stack_align - 1);
1601                 offset &= ~(locals_stack_align - 1);
1602         }
1603         if (cfg->arch.omit_fp) {
1604                 cfg->locals_min_stack_offset = offset;
1605                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1606         } else {
1607                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1608                 cfg->locals_max_stack_offset = - offset;
1609         }
1610
1611         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1612                 if (offsets [i] != -1) {
1613                         MonoInst *ins = cfg->varinfo [i];
1614                         ins->opcode = OP_REGOFFSET;
1615                         ins->inst_basereg = cfg->frame_reg;
1616                         if (cfg->arch.omit_fp)
1617                                 ins->inst_offset = (offset + offsets [i]);
1618                         else
1619                                 ins->inst_offset = - (offset + offsets [i]);
1620                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1621                 }
1622         }
1623         offset += locals_stack_size;
1624
1625         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1626                 g_assert (!cfg->arch.omit_fp);
1627                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1628                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1629         }
1630
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ins = cfg->args [i];
1633                 if (ins->opcode != OP_REGVAR) {
1634                         ArgInfo *ainfo = &cinfo->args [i];
1635                         gboolean inreg = TRUE;
1636
1637                         /* FIXME: Allocate volatile arguments to registers */
1638                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1639                                 inreg = FALSE;
1640
1641                         /*
1642                          * Under AMD64, all registers used to pass arguments to functions
1643                          * are volatile across calls.
1644                          * FIXME: Optimize this.
1645                          */
1646                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1647                                 inreg = FALSE;
1648
1649                         ins->opcode = OP_REGOFFSET;
1650
1651                         switch (ainfo->storage) {
1652                         case ArgInIReg:
1653                         case ArgInFloatSSEReg:
1654                         case ArgInDoubleSSEReg:
1655                         case ArgGSharedVtInReg:
1656                                 if (inreg) {
1657                                         ins->opcode = OP_REGVAR;
1658                                         ins->dreg = ainfo->reg;
1659                                 }
1660                                 break;
1661                         case ArgOnStack:
1662                         case ArgGSharedVtOnStack:
1663                                 g_assert (!cfg->arch.omit_fp);
1664                                 ins->opcode = OP_REGOFFSET;
1665                                 ins->inst_basereg = cfg->frame_reg;
1666                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1667                                 break;
1668                         case ArgValuetypeInReg:
1669                                 break;
1670                         case ArgValuetypeAddrInIReg: {
1671                                 MonoInst *indir;
1672                                 g_assert (!cfg->arch.omit_fp);
1673
1674                                 MONO_INST_NEW (cfg, indir, 0);
1675                                 indir->opcode = OP_REGOFFSET;
1676                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1677                                         indir->inst_basereg = cfg->frame_reg;
1678                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1679                                         offset += (sizeof (gpointer));
1680                                         indir->inst_offset = - offset;
1681                                 }
1682                                 else {
1683                                         indir->inst_basereg = cfg->frame_reg;
1684                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1685                                 }
1686
1687                                 ins->opcode = OP_VTARG_ADDR;
1688                                 ins->inst_left = indir;
1689
1690                                 break;
1691                         }
1692                         default:
1693                                 NOT_IMPLEMENTED;
1694                         }
1695
1696                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
1697                                 ins->opcode = OP_REGOFFSET;
1698                                 ins->inst_basereg = cfg->frame_reg;
1699                                 /* These arguments are saved to the stack in the prolog */
1700                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1701                                 if (cfg->arch.omit_fp) {
1702                                         ins->inst_offset = offset;
1703                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1704                                         // Arguments are yet supported by the stack map creation code
1705                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1706                                 } else {
1707                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1708                                         ins->inst_offset = - offset;
1709                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1710                                 }
1711                         }
1712                 }
1713         }
1714
1715         cfg->stack_offset = offset;
1716 }
1717
1718 void
1719 mono_arch_create_vars (MonoCompile *cfg)
1720 {
1721         MonoMethodSignature *sig;
1722         CallInfo *cinfo;
1723         MonoType *sig_ret;
1724
1725         sig = mono_method_signature (cfg->method);
1726
1727         if (!cfg->arch.cinfo)
1728                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1729         cinfo = (CallInfo *)cfg->arch.cinfo;
1730
1731         if (cinfo->ret.storage == ArgValuetypeInReg)
1732                 cfg->ret_var_is_local = TRUE;
1733
1734         sig_ret = mini_get_underlying_type (sig->ret);
1735         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1736                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1737                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1738                         printf ("vret_addr = ");
1739                         mono_print_ins (cfg->vret_addr);
1740                 }
1741         }
1742
1743         if (cfg->gen_sdb_seq_points) {
1744                 MonoInst *ins;
1745
1746                 if (cfg->compile_aot) {
1747                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1748                         ins->flags |= MONO_INST_VOLATILE;
1749                         cfg->arch.seq_point_info_var = ins;
1750                 }
1751                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1752                 ins->flags |= MONO_INST_VOLATILE;
1753                 cfg->arch.ss_tramp_var = ins;
1754
1755                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1756                 ins->flags |= MONO_INST_VOLATILE;
1757                 cfg->arch.bp_tramp_var = ins;
1758         }
1759
1760         if (cfg->method->save_lmf)
1761                 cfg->create_lmf_var = TRUE;
1762
1763         if (cfg->method->save_lmf) {
1764                 cfg->lmf_ir = TRUE;
1765 #if !defined(TARGET_WIN32)
1766                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1767                         cfg->lmf_ir_mono_lmf = TRUE;
1768 #endif
1769         }
1770 }
1771
1772 static void
1773 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1774 {
1775         MonoInst *ins;
1776
1777         switch (storage) {
1778         case ArgInIReg:
1779                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1780                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1781                 ins->sreg1 = tree->dreg;
1782                 MONO_ADD_INS (cfg->cbb, ins);
1783                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1784                 break;
1785         case ArgInFloatSSEReg:
1786                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1787                 ins->dreg = mono_alloc_freg (cfg);
1788                 ins->sreg1 = tree->dreg;
1789                 MONO_ADD_INS (cfg->cbb, ins);
1790
1791                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1792                 break;
1793         case ArgInDoubleSSEReg:
1794                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1795                 ins->dreg = mono_alloc_freg (cfg);
1796                 ins->sreg1 = tree->dreg;
1797                 MONO_ADD_INS (cfg->cbb, ins);
1798
1799                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1800
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805 }
1806
1807 static int
1808 arg_storage_to_load_membase (ArgStorage storage)
1809 {
1810         switch (storage) {
1811         case ArgInIReg:
1812 #if defined(__mono_ilp32__)
1813                 return OP_LOADI8_MEMBASE;
1814 #else
1815                 return OP_LOAD_MEMBASE;
1816 #endif
1817         case ArgInDoubleSSEReg:
1818                 return OP_LOADR8_MEMBASE;
1819         case ArgInFloatSSEReg:
1820                 return OP_LOADR4_MEMBASE;
1821         default:
1822                 g_assert_not_reached ();
1823         }
1824
1825         return -1;
1826 }
1827
1828 static void
1829 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1830 {
1831         MonoMethodSignature *tmp_sig;
1832         int sig_reg;
1833
1834         if (call->tail_call)
1835                 NOT_IMPLEMENTED;
1836
1837         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1838
1839         /*
1840          * mono_ArgIterator_Setup assumes the signature cookie is
1841          * passed first and all the arguments which were before it are
1842          * passed on the stack after the signature. So compensate by
1843          * passing a different signature.
1844          */
1845         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1846         tmp_sig->param_count -= call->signature->sentinelpos;
1847         tmp_sig->sentinelpos = 0;
1848         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1849
1850         sig_reg = mono_alloc_ireg (cfg);
1851         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1852
1853         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1854 }
1855
1856 #ifdef ENABLE_LLVM
1857 static inline LLVMArgStorage
1858 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1859 {
1860         switch (storage) {
1861         case ArgInIReg:
1862                 return LLVMArgInIReg;
1863         case ArgNone:
1864                 return LLVMArgNone;
1865         case ArgGSharedVtInReg:
1866         case ArgGSharedVtOnStack:
1867                 return LLVMArgGSharedVt;
1868         default:
1869                 g_assert_not_reached ();
1870                 return LLVMArgNone;
1871         }
1872 }
1873
1874 LLVMCallInfo*
1875 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1876 {
1877         int i, n;
1878         CallInfo *cinfo;
1879         ArgInfo *ainfo;
1880         int j;
1881         LLVMCallInfo *linfo;
1882         MonoType *t, *sig_ret;
1883
1884         n = sig->param_count + sig->hasthis;
1885         sig_ret = mini_get_underlying_type (sig->ret);
1886
1887         cinfo = get_call_info (cfg->mempool, sig);
1888
1889         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1890
1891         /*
1892          * LLVM always uses the native ABI while we use our own ABI, the
1893          * only difference is the handling of vtypes:
1894          * - we only pass/receive them in registers in some cases, and only
1895          *   in 1 or 2 integer registers.
1896          */
1897         switch (cinfo->ret.storage) {
1898         case ArgNone:
1899                 linfo->ret.storage = LLVMArgNone;
1900                 break;
1901         case ArgInIReg:
1902         case ArgInFloatSSEReg:
1903         case ArgInDoubleSSEReg:
1904                 linfo->ret.storage = LLVMArgNormal;
1905                 break;
1906         case ArgValuetypeInReg: {
1907                 ainfo = &cinfo->ret;
1908
1909                 if (sig->pinvoke &&
1910                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1911                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1912                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1913                         cfg->disable_llvm = TRUE;
1914                         return linfo;
1915                 }
1916
1917                 linfo->ret.storage = LLVMArgVtypeInReg;
1918                 for (j = 0; j < 2; ++j)
1919                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1920                 break;
1921         }
1922         case ArgValuetypeAddrInIReg:
1923         case ArgGsharedvtVariableInReg:
1924                 /* Vtype returned using a hidden argument */
1925                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1926                 linfo->vret_arg_index = cinfo->vret_arg_index;
1927                 break;
1928         default:
1929                 g_assert_not_reached ();
1930                 break;
1931         }
1932
1933         for (i = 0; i < n; ++i) {
1934                 ainfo = cinfo->args + i;
1935
1936                 if (i >= sig->hasthis)
1937                         t = sig->params [i - sig->hasthis];
1938                 else
1939                         t = &mono_defaults.int_class->byval_arg;
1940
1941                 linfo->args [i].storage = LLVMArgNone;
1942
1943                 switch (ainfo->storage) {
1944                 case ArgInIReg:
1945                         linfo->args [i].storage = LLVMArgNormal;
1946                         break;
1947                 case ArgInDoubleSSEReg:
1948                 case ArgInFloatSSEReg:
1949                         linfo->args [i].storage = LLVMArgNormal;
1950                         break;
1951                 case ArgOnStack:
1952                         if (MONO_TYPE_ISSTRUCT (t))
1953                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1954                         else
1955                                 linfo->args [i].storage = LLVMArgNormal;
1956                         break;
1957                 case ArgValuetypeInReg:
1958                         if (sig->pinvoke &&
1959                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1960                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1961                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1962                                 cfg->disable_llvm = TRUE;
1963                                 return linfo;
1964                         }
1965
1966                         linfo->args [i].storage = LLVMArgVtypeInReg;
1967                         for (j = 0; j < 2; ++j)
1968                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1969                         break;
1970                 case ArgGSharedVtInReg:
1971                 case ArgGSharedVtOnStack:
1972                         linfo->args [i].storage = LLVMArgGSharedVt;
1973                         break;
1974                 default:
1975                         cfg->exception_message = g_strdup ("ainfo->storage");
1976                         cfg->disable_llvm = TRUE;
1977                         break;
1978                 }
1979         }
1980
1981         return linfo;
1982 }
1983 #endif
1984
1985 void
1986 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1987 {
1988         MonoInst *arg, *in;
1989         MonoMethodSignature *sig;
1990         MonoType *sig_ret;
1991         int i, n;
1992         CallInfo *cinfo;
1993         ArgInfo *ainfo;
1994
1995         sig = call->signature;
1996         n = sig->param_count + sig->hasthis;
1997
1998         cinfo = get_call_info (cfg->mempool, sig);
1999
2000         sig_ret = sig->ret;
2001
2002         if (COMPILE_LLVM (cfg)) {
2003                 /* We shouldn't be called in the llvm case */
2004                 cfg->disable_llvm = TRUE;
2005                 return;
2006         }
2007
2008         /*
2009          * Emit all arguments which are passed on the stack to prevent register
2010          * allocation problems.
2011          */
2012         for (i = 0; i < n; ++i) {
2013                 MonoType *t;
2014                 ainfo = cinfo->args + i;
2015
2016                 in = call->args [i];
2017
2018                 if (sig->hasthis && i == 0)
2019                         t = &mono_defaults.object_class->byval_arg;
2020                 else
2021                         t = sig->params [i - sig->hasthis];
2022
2023                 t = mini_get_underlying_type (t);
2024                 //XXX what about ArgGSharedVtOnStack here?
2025                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2026                         if (!t->byref) {
2027                                 if (t->type == MONO_TYPE_R4)
2028                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2029                                 else if (t->type == MONO_TYPE_R8)
2030                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2031                                 else
2032                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2033                         } else {
2034                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2035                         }
2036                         if (cfg->compute_gc_maps) {
2037                                 MonoInst *def;
2038
2039                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2040                         }
2041                 }
2042         }
2043
2044         /*
2045          * Emit all parameters passed in registers in non-reverse order for better readability
2046          * and to help the optimization in emit_prolog ().
2047          */
2048         for (i = 0; i < n; ++i) {
2049                 ainfo = cinfo->args + i;
2050
2051                 in = call->args [i];
2052
2053                 if (ainfo->storage == ArgInIReg)
2054                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2055         }
2056
2057         for (i = n - 1; i >= 0; --i) {
2058                 MonoType *t;
2059
2060                 ainfo = cinfo->args + i;
2061
2062                 in = call->args [i];
2063
2064                 if (sig->hasthis && i == 0)
2065                         t = &mono_defaults.object_class->byval_arg;
2066                 else
2067                         t = sig->params [i - sig->hasthis];
2068                 t = mini_get_underlying_type (t);
2069
2070                 switch (ainfo->storage) {
2071                 case ArgInIReg:
2072                         /* Already done */
2073                         break;
2074                 case ArgInFloatSSEReg:
2075                 case ArgInDoubleSSEReg:
2076                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2077                         break;
2078                 case ArgOnStack:
2079                 case ArgValuetypeInReg:
2080                 case ArgValuetypeAddrInIReg:
2081                 case ArgGSharedVtInReg:
2082                 case ArgGSharedVtOnStack: {
2083                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2084                                 /* Already emitted above */
2085                                 break;
2086                         //FIXME what about ArgGSharedVtOnStack ?
2087                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2088                                 MonoInst *call_inst = (MonoInst*)call;
2089                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2090                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2091                                 break;
2092                         }
2093
2094                         guint32 align;
2095                         guint32 size;
2096
2097                         if (sig->pinvoke)
2098                                 size = mono_type_native_stack_size (t, &align);
2099                         else {
2100                                 /*
2101                                  * Other backends use mono_type_stack_size (), but that
2102                                  * aligns the size to 8, which is larger than the size of
2103                                  * the source, leading to reads of invalid memory if the
2104                                  * source is at the end of address space.
2105                                  */
2106                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2107                         }
2108
2109                         if (size >= 10000) {
2110                                 /* Avoid asserts in emit_memcpy () */
2111                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2112                                 /* Continue normally */
2113                         }
2114
2115                         if (size > 0) {
2116                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2117                                 arg->sreg1 = in->dreg;
2118                                 arg->klass = mono_class_from_mono_type (t);
2119                                 arg->backend.size = size;
2120                                 arg->inst_p0 = call;
2121                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2122                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2123
2124                                 MONO_ADD_INS (cfg->cbb, arg);
2125                         }
2126                         break;
2127                 }
2128                 default:
2129                         g_assert_not_reached ();
2130                 }
2131
2132                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2133                         /* Emit the signature cookie just before the implicit arguments */
2134                         emit_sig_cookie (cfg, call, cinfo);
2135         }
2136
2137         /* Handle the case where there are no implicit arguments */
2138         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2139                 emit_sig_cookie (cfg, call, cinfo);
2140
2141         switch (cinfo->ret.storage) {
2142         case ArgValuetypeInReg:
2143                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2144                         /*
2145                          * Tell the JIT to use a more efficient calling convention: call using
2146                          * OP_CALL, compute the result location after the call, and save the
2147                          * result there.
2148                          */
2149                         call->vret_in_reg = TRUE;
2150                         /*
2151                          * Nullify the instruction computing the vret addr to enable
2152                          * future optimizations.
2153                          */
2154                         if (call->vret_var)
2155                                 NULLIFY_INS (call->vret_var);
2156                 } else {
2157                         if (call->tail_call)
2158                                 NOT_IMPLEMENTED;
2159                         /*
2160                          * The valuetype is in RAX:RDX after the call, need to be copied to
2161                          * the stack. Push the address here, so the call instruction can
2162                          * access it.
2163                          */
2164                         if (!cfg->arch.vret_addr_loc) {
2165                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2166                                 /* Prevent it from being register allocated or optimized away */
2167                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2168                         }
2169
2170                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2171                 }
2172                 break;
2173         case ArgValuetypeAddrInIReg:
2174         case ArgGsharedvtVariableInReg: {
2175                 MonoInst *vtarg;
2176                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2177                 vtarg->sreg1 = call->vret_var->dreg;
2178                 vtarg->dreg = mono_alloc_preg (cfg);
2179                 MONO_ADD_INS (cfg->cbb, vtarg);
2180
2181                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2182                 break;
2183         }
2184         default:
2185                 break;
2186         }
2187
2188         if (cfg->method->save_lmf) {
2189                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2190                 MONO_ADD_INS (cfg->cbb, arg);
2191         }
2192
2193         call->stack_usage = cinfo->stack_usage;
2194 }
2195
2196 void
2197 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2198 {
2199         MonoInst *arg;
2200         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2201         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2202         int size = ins->backend.size;
2203
2204         switch (ainfo->storage) {
2205         case ArgValuetypeInReg: {
2206                 MonoInst *load;
2207                 int part;
2208
2209                 for (part = 0; part < 2; ++part) {
2210                         if (ainfo->pair_storage [part] == ArgNone)
2211                                 continue;
2212
2213                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2214                         load->inst_basereg = src->dreg;
2215                         load->inst_offset = part * sizeof(mgreg_t);
2216
2217                         switch (ainfo->pair_storage [part]) {
2218                         case ArgInIReg:
2219                                 load->dreg = mono_alloc_ireg (cfg);
2220                                 break;
2221                         case ArgInDoubleSSEReg:
2222                         case ArgInFloatSSEReg:
2223                                 load->dreg = mono_alloc_freg (cfg);
2224                                 break;
2225                         default:
2226                                 g_assert_not_reached ();
2227                         }
2228                         MONO_ADD_INS (cfg->cbb, load);
2229
2230                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2231                 }
2232                 break;
2233         }
2234         case ArgValuetypeAddrInIReg: {
2235                 MonoInst *vtaddr, *load;
2236                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2237
2238                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2239                 cfg->has_indirection = TRUE;
2240                 load->inst_p0 = vtaddr;
2241                 vtaddr->flags |= MONO_INST_INDIRECT;
2242                 load->type = STACK_MP;
2243                 load->klass = vtaddr->klass;
2244                 load->dreg = mono_alloc_ireg (cfg);
2245                 MONO_ADD_INS (cfg->cbb, load);
2246                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2247
2248                 if (ainfo->pair_storage [0] == ArgInIReg) {
2249                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2250                         arg->dreg = mono_alloc_ireg (cfg);
2251                         arg->sreg1 = load->dreg;
2252                         arg->inst_imm = 0;
2253                         MONO_ADD_INS (cfg->cbb, arg);
2254                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2255                 } else {
2256                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2257                 }
2258                 break;
2259         }
2260         case ArgGSharedVtInReg:
2261                 /* Pass by addr */
2262                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2263                 break;
2264         case ArgGSharedVtOnStack:
2265                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2266                 break;
2267         default:
2268                 if (size == 8) {
2269                         int dreg = mono_alloc_ireg (cfg);
2270
2271                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2272                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2273                 } else if (size <= 40) {
2274                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2275                 } else {
2276                         // FIXME: Code growth
2277                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2278                 }
2279
2280                 if (cfg->compute_gc_maps) {
2281                         MonoInst *def;
2282                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2283                 }
2284         }
2285 }
2286
2287 void
2288 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2289 {
2290         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2291
2292         if (ret->type == MONO_TYPE_R4) {
2293                 if (COMPILE_LLVM (cfg))
2294                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2295                 else
2296                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2297                 return;
2298         } else if (ret->type == MONO_TYPE_R8) {
2299                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2300                 return;
2301         }
2302
2303         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2304 }
2305
2306 #endif /* DISABLE_JIT */
2307
2308 #define EMIT_COND_BRANCH(ins,cond,sign) \
2309         if (ins->inst_true_bb->native_offset) { \
2310                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2311         } else { \
2312                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2313                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2314             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2315                         x86_branch8 (code, cond, 0, sign); \
2316                 else \
2317                         x86_branch32 (code, cond, 0, sign); \
2318 }
2319
2320 typedef struct {
2321         MonoMethodSignature *sig;
2322         CallInfo *cinfo;
2323 } ArchDynCallInfo;
2324
2325 static gboolean
2326 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2327 {
2328         int i;
2329
2330         switch (cinfo->ret.storage) {
2331         case ArgNone:
2332         case ArgInIReg:
2333         case ArgInFloatSSEReg:
2334         case ArgInDoubleSSEReg:
2335         case ArgValuetypeAddrInIReg:
2336                 break;
2337         case ArgValuetypeInReg: {
2338                 ArgInfo *ainfo = &cinfo->ret;
2339
2340                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2341                         return FALSE;
2342                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2343                         return FALSE;
2344                 break;
2345         }
2346         default:
2347                 return FALSE;
2348         }
2349
2350         for (i = 0; i < cinfo->nargs; ++i) {
2351                 ArgInfo *ainfo = &cinfo->args [i];
2352                 switch (ainfo->storage) {
2353                 case ArgInIReg:
2354                 case ArgInFloatSSEReg:
2355                 case ArgInDoubleSSEReg:
2356                         break;
2357                 case ArgValuetypeInReg:
2358                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2359                                 return FALSE;
2360                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2361                                 return FALSE;
2362                         break;
2363                 case ArgOnStack:
2364                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2365                                 return FALSE;
2366                         break;
2367                 default:
2368                         return FALSE;
2369                 }
2370         }
2371
2372         return TRUE;
2373 }
2374
2375 /*
2376  * mono_arch_dyn_call_prepare:
2377  *
2378  *   Return a pointer to an arch-specific structure which contains information
2379  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2380  * supported for SIG.
2381  * This function is equivalent to ffi_prep_cif in libffi.
2382  */
2383 MonoDynCallInfo*
2384 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2385 {
2386         ArchDynCallInfo *info;
2387         CallInfo *cinfo;
2388
2389         cinfo = get_call_info (NULL, sig);
2390
2391         if (!dyn_call_supported (sig, cinfo)) {
2392                 g_free (cinfo);
2393                 return NULL;
2394         }
2395
2396         info = g_new0 (ArchDynCallInfo, 1);
2397         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2398         info->sig = sig;
2399         info->cinfo = cinfo;
2400
2401         return (MonoDynCallInfo*)info;
2402 }
2403
2404 /*
2405  * mono_arch_dyn_call_free:
2406  *
2407  *   Free a MonoDynCallInfo structure.
2408  */
2409 void
2410 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2411 {
2412         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2413
2414         g_free (ainfo->cinfo);
2415         g_free (ainfo);
2416 }
2417
2418 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2419 #define GREG_TO_PTR(greg) (gpointer)(greg)
2420
2421 /*
2422  * mono_arch_get_start_dyn_call:
2423  *
2424  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2425  * store the result into BUF.
2426  * ARGS should be an array of pointers pointing to the arguments.
2427  * RET should point to a memory buffer large enought to hold the result of the
2428  * call.
2429  * This function should be as fast as possible, any work which does not depend
2430  * on the actual values of the arguments should be done in
2431  * mono_arch_dyn_call_prepare ().
2432  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2433  * libffi.
2434  */
2435 void
2436 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2437 {
2438         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2439         DynCallArgs *p = (DynCallArgs*)buf;
2440         int arg_index, greg, freg, i, pindex;
2441         MonoMethodSignature *sig = dinfo->sig;
2442         int buffer_offset = 0;
2443         static int param_reg_to_index [16];
2444         static gboolean param_reg_to_index_inited;
2445
2446         if (!param_reg_to_index_inited) {
2447                 for (i = 0; i < PARAM_REGS; ++i)
2448                         param_reg_to_index [param_regs [i]] = i;
2449                 mono_memory_barrier ();
2450                 param_reg_to_index_inited = 1;
2451         }
2452
2453         g_assert (buf_len >= sizeof (DynCallArgs));
2454
2455         p->res = 0;
2456         p->ret = ret;
2457
2458         arg_index = 0;
2459         greg = 0;
2460         freg = 0;
2461         pindex = 0;
2462
2463         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2464                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2465                 if (!sig->hasthis)
2466                         pindex = 1;
2467         }
2468
2469         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2470                 p->regs [greg ++] = PTR_TO_GREG(ret);
2471
2472         for (i = pindex; i < sig->param_count; i++) {
2473                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2474                 gpointer *arg = args [arg_index ++];
2475                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2476                 int slot;
2477
2478                 if (ainfo->storage == ArgOnStack) {
2479                         slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
2480                 } else {
2481                         slot = param_reg_to_index [ainfo->reg];
2482                 }
2483
2484                 if (t->byref) {
2485                         p->regs [slot] = PTR_TO_GREG(*(arg));
2486                         greg ++;
2487                         continue;
2488                 }
2489
2490                 switch (t->type) {
2491                 case MONO_TYPE_STRING:
2492                 case MONO_TYPE_CLASS:
2493                 case MONO_TYPE_ARRAY:
2494                 case MONO_TYPE_SZARRAY:
2495                 case MONO_TYPE_OBJECT:
2496                 case MONO_TYPE_PTR:
2497                 case MONO_TYPE_I:
2498                 case MONO_TYPE_U:
2499 #if !defined(__mono_ilp32__)
2500                 case MONO_TYPE_I8:
2501                 case MONO_TYPE_U8:
2502 #endif
2503                         p->regs [slot] = PTR_TO_GREG(*(arg));
2504                         break;
2505 #if defined(__mono_ilp32__)
2506                 case MONO_TYPE_I8:
2507                 case MONO_TYPE_U8:
2508                         p->regs [slot] = *(guint64*)(arg);
2509                         break;
2510 #endif
2511                 case MONO_TYPE_U1:
2512                         p->regs [slot] = *(guint8*)(arg);
2513                         break;
2514                 case MONO_TYPE_I1:
2515                         p->regs [slot] = *(gint8*)(arg);
2516                         break;
2517                 case MONO_TYPE_I2:
2518                         p->regs [slot] = *(gint16*)(arg);
2519                         break;
2520                 case MONO_TYPE_U2:
2521                         p->regs [slot] = *(guint16*)(arg);
2522                         break;
2523                 case MONO_TYPE_I4:
2524                         p->regs [slot] = *(gint32*)(arg);
2525                         break;
2526                 case MONO_TYPE_U4:
2527                         p->regs [slot] = *(guint32*)(arg);
2528                         break;
2529                 case MONO_TYPE_R4: {
2530                         double d;
2531
2532                         *(float*)&d = *(float*)(arg);
2533                         p->has_fp = 1;
2534                         p->fregs [freg ++] = d;
2535                         break;
2536                 }
2537                 case MONO_TYPE_R8:
2538                         p->has_fp = 1;
2539                         p->fregs [freg ++] = *(double*)(arg);
2540                         break;
2541                 case MONO_TYPE_GENERICINST:
2542                     if (MONO_TYPE_IS_REFERENCE (t)) {
2543                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2544                                 break;
2545                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2546                                         MonoClass *klass = mono_class_from_mono_type (t);
2547                                         guint8 *nullable_buf;
2548                                         int size;
2549
2550                                         size = mono_class_value_size (klass, NULL);
2551                                         nullable_buf = p->buffer + buffer_offset;
2552                                         buffer_offset += size;
2553                                         g_assert (buffer_offset <= 256);
2554
2555                                         /* The argument pointed to by arg is either a boxed vtype or null */
2556                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2557
2558                                         arg = (gpointer*)nullable_buf;
2559                                         /* Fall though */
2560
2561                         } else {
2562                                 /* Fall through */
2563                         }
2564                 case MONO_TYPE_VALUETYPE: {
2565                         switch (ainfo->storage) {
2566                         case ArgValuetypeInReg:
2567                                 if (ainfo->pair_storage [0] != ArgNone) {
2568                                         slot = param_reg_to_index [ainfo->pair_regs [0]];
2569                                         g_assert (ainfo->pair_storage [0] == ArgInIReg);
2570                                         p->regs [slot] = ((mgreg_t*)(arg))[0];
2571                                 }
2572                                 if (ainfo->pair_storage [1] != ArgNone) {
2573                                         slot = param_reg_to_index [ainfo->pair_regs [1]];
2574                                         g_assert (ainfo->pair_storage [1] == ArgInIReg);
2575                                         p->regs [slot] = ((mgreg_t*)(arg))[1];
2576                                 }
2577                                 break;
2578                         case ArgOnStack:
2579                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2580                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2581                                 break;
2582                         default:
2583                                 g_assert_not_reached ();
2584                                 break;
2585                         }
2586                         break;
2587                 }
2588                 default:
2589                         g_assert_not_reached ();
2590                 }
2591         }
2592 }
2593
2594 /*
2595  * mono_arch_finish_dyn_call:
2596  *
2597  *   Store the result of a dyn call into the return value buffer passed to
2598  * start_dyn_call ().
2599  * This function should be as fast as possible, any work which does not depend
2600  * on the actual values of the arguments should be done in
2601  * mono_arch_dyn_call_prepare ().
2602  */
2603 void
2604 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2605 {
2606         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2607         MonoMethodSignature *sig = dinfo->sig;
2608         DynCallArgs *dargs = (DynCallArgs*)buf;
2609         guint8 *ret = dargs->ret;
2610         mgreg_t res = dargs->res;
2611         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2612
2613         switch (sig_ret->type) {
2614         case MONO_TYPE_VOID:
2615                 *(gpointer*)ret = NULL;
2616                 break;
2617         case MONO_TYPE_STRING:
2618         case MONO_TYPE_CLASS:
2619         case MONO_TYPE_ARRAY:
2620         case MONO_TYPE_SZARRAY:
2621         case MONO_TYPE_OBJECT:
2622         case MONO_TYPE_I:
2623         case MONO_TYPE_U:
2624         case MONO_TYPE_PTR:
2625                 *(gpointer*)ret = GREG_TO_PTR(res);
2626                 break;
2627         case MONO_TYPE_I1:
2628                 *(gint8*)ret = res;
2629                 break;
2630         case MONO_TYPE_U1:
2631                 *(guint8*)ret = res;
2632                 break;
2633         case MONO_TYPE_I2:
2634                 *(gint16*)ret = res;
2635                 break;
2636         case MONO_TYPE_U2:
2637                 *(guint16*)ret = res;
2638                 break;
2639         case MONO_TYPE_I4:
2640                 *(gint32*)ret = res;
2641                 break;
2642         case MONO_TYPE_U4:
2643                 *(guint32*)ret = res;
2644                 break;
2645         case MONO_TYPE_I8:
2646                 *(gint64*)ret = res;
2647                 break;
2648         case MONO_TYPE_U8:
2649                 *(guint64*)ret = res;
2650                 break;
2651         case MONO_TYPE_R4:
2652                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2653                 break;
2654         case MONO_TYPE_R8:
2655                 *(double*)ret = dargs->fregs [0];
2656                 break;
2657         case MONO_TYPE_GENERICINST:
2658                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2659                         *(gpointer*)ret = GREG_TO_PTR(res);
2660                         break;
2661                 } else {
2662                         /* Fall through */
2663                 }
2664         case MONO_TYPE_VALUETYPE:
2665                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2666                         /* Nothing to do */
2667                 } else {
2668                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2669
2670                         g_assert (ainfo->storage == ArgValuetypeInReg);
2671
2672                         if (ainfo->pair_storage [0] != ArgNone) {
2673                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2674                                 ((mgreg_t*)ret)[0] = res;
2675                         }
2676
2677                         g_assert (ainfo->pair_storage [1] == ArgNone);
2678                 }
2679                 break;
2680         default:
2681                 g_assert_not_reached ();
2682         }
2683 }
2684
2685 /* emit an exception if condition is fail */
2686 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2687         do {                                                        \
2688                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2689                 if (tins == NULL) {                                                                             \
2690                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2691                                         MONO_PATCH_INFO_EXC, exc_name);  \
2692                         x86_branch32 (code, cond, 0, signed);               \
2693                 } else {        \
2694                         EMIT_COND_BRANCH (tins, cond, signed);  \
2695                 }                       \
2696         } while (0);
2697
2698 #define EMIT_FPCOMPARE(code) do { \
2699         amd64_fcompp (code); \
2700         amd64_fnstsw (code); \
2701 } while (0);
2702
2703 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2704     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2705         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2706         amd64_ ##op (code); \
2707         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2708         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2709 } while (0);
2710
2711 static guint8*
2712 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2713 {
2714         gboolean no_patch = FALSE;
2715
2716         /*
2717          * FIXME: Add support for thunks
2718          */
2719         {
2720                 gboolean near_call = FALSE;
2721
2722                 /*
2723                  * Indirect calls are expensive so try to make a near call if possible.
2724                  * The caller memory is allocated by the code manager so it is
2725                  * guaranteed to be at a 32 bit offset.
2726                  */
2727
2728                 if (patch_type != MONO_PATCH_INFO_ABS) {
2729                         /* The target is in memory allocated using the code manager */
2730                         near_call = TRUE;
2731
2732                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2733                                 if (((MonoMethod*)data)->klass->image->aot_module)
2734                                         /* The callee might be an AOT method */
2735                                         near_call = FALSE;
2736                                 if (((MonoMethod*)data)->dynamic)
2737                                         /* The target is in malloc-ed memory */
2738                                         near_call = FALSE;
2739                         }
2740
2741                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2742                                 /*
2743                                  * The call might go directly to a native function without
2744                                  * the wrapper.
2745                                  */
2746                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2747                                 if (mi) {
2748                                         gconstpointer target = mono_icall_get_wrapper (mi);
2749                                         if ((((guint64)target) >> 32) != 0)
2750                                                 near_call = FALSE;
2751                                 }
2752                         }
2753                 }
2754                 else {
2755                         MonoJumpInfo *jinfo = NULL;
2756
2757                         if (cfg->abs_patches)
2758                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2759                         if (jinfo) {
2760                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2761                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2762                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2763                                                 near_call = TRUE;
2764                                         no_patch = TRUE;
2765                                 } else {
2766                                         /*
2767                                          * This is not really an optimization, but required because the
2768                                          * generic class init trampolines use R11 to pass the vtable.
2769                                          */
2770                                         near_call = TRUE;
2771                                 }
2772                         } else {
2773                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2774                                 if (info) {
2775                                         if (info->func == info->wrapper) {
2776                                                 /* No wrapper */
2777                                                 if ((((guint64)info->func) >> 32) == 0)
2778                                                         near_call = TRUE;
2779                                         }
2780                                         else {
2781                                                 /* See the comment in mono_codegen () */
2782                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2783                                                         near_call = TRUE;
2784                                         }
2785                                 }
2786                                 else if ((((guint64)data) >> 32) == 0) {
2787                                         near_call = TRUE;
2788                                         no_patch = TRUE;
2789                                 }
2790                         }
2791                 }
2792
2793                 if (cfg->method->dynamic)
2794                         /* These methods are allocated using malloc */
2795                         near_call = FALSE;
2796
2797 #ifdef MONO_ARCH_NOMAP32BIT
2798                 near_call = FALSE;
2799 #endif
2800                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2801                 if (optimize_for_xen)
2802                         near_call = FALSE;
2803
2804                 if (cfg->compile_aot) {
2805                         near_call = TRUE;
2806                         no_patch = TRUE;
2807                 }
2808
2809                 if (near_call) {
2810                         /*
2811                          * Align the call displacement to an address divisible by 4 so it does
2812                          * not span cache lines. This is required for code patching to work on SMP
2813                          * systems.
2814                          */
2815                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2816                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2817                                 amd64_padding (code, pad_size);
2818                         }
2819                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2820                         amd64_call_code (code, 0);
2821                 }
2822                 else {
2823                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2824                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2825                         amd64_call_reg (code, GP_SCRATCH_REG);
2826                 }
2827         }
2828
2829         return code;
2830 }
2831
2832 static inline guint8*
2833 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2834 {
2835 #ifdef TARGET_WIN32
2836         if (win64_adjust_stack)
2837                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2838 #endif
2839         code = emit_call_body (cfg, code, patch_type, data);
2840 #ifdef TARGET_WIN32
2841         if (win64_adjust_stack)
2842                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2843 #endif
2844
2845         return code;
2846 }
2847
2848 static inline int
2849 store_membase_imm_to_store_membase_reg (int opcode)
2850 {
2851         switch (opcode) {
2852         case OP_STORE_MEMBASE_IMM:
2853                 return OP_STORE_MEMBASE_REG;
2854         case OP_STOREI4_MEMBASE_IMM:
2855                 return OP_STOREI4_MEMBASE_REG;
2856         case OP_STOREI8_MEMBASE_IMM:
2857                 return OP_STOREI8_MEMBASE_REG;
2858         }
2859
2860         return -1;
2861 }
2862
2863 #ifndef DISABLE_JIT
2864
2865 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2866
2867 /*
2868  * mono_arch_peephole_pass_1:
2869  *
2870  *   Perform peephole opts which should/can be performed before local regalloc
2871  */
2872 void
2873 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2874 {
2875         MonoInst *ins, *n;
2876
2877         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2878                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2879
2880                 switch (ins->opcode) {
2881                 case OP_ADD_IMM:
2882                 case OP_IADD_IMM:
2883                 case OP_LADD_IMM:
2884                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2885                                 /*
2886                                  * X86_LEA is like ADD, but doesn't have the
2887                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2888                                  * its operand to 64 bit.
2889                                  */
2890                                 ins->opcode = OP_X86_LEA_MEMBASE;
2891                                 ins->inst_basereg = ins->sreg1;
2892                         }
2893                         break;
2894                 case OP_LXOR:
2895                 case OP_IXOR:
2896                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2897                                 MonoInst *ins2;
2898
2899                                 /*
2900                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2901                                  * the latter has length 2-3 instead of 6 (reverse constant
2902                                  * propagation). These instruction sequences are very common
2903                                  * in the initlocals bblock.
2904                                  */
2905                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2906                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2907                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2908                                                 ins2->sreg1 = ins->dreg;
2909                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2910                                                 /* Continue */
2911                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2912                                                 NULLIFY_INS (ins2);
2913                                                 /* Continue */
2914                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2915                                                 /* Continue */
2916                                         } else {
2917                                                 break;
2918                                         }
2919                                 }
2920                         }
2921                         break;
2922                 case OP_COMPARE_IMM:
2923                 case OP_LCOMPARE_IMM:
2924                         /* OP_COMPARE_IMM (reg, 0)
2925                          * -->
2926                          * OP_AMD64_TEST_NULL (reg)
2927                          */
2928                         if (!ins->inst_imm)
2929                                 ins->opcode = OP_AMD64_TEST_NULL;
2930                         break;
2931                 case OP_ICOMPARE_IMM:
2932                         if (!ins->inst_imm)
2933                                 ins->opcode = OP_X86_TEST_NULL;
2934                         break;
2935                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2936                         /*
2937                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2938                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2939                          * -->
2940                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2941                          * OP_COMPARE_IMM reg, imm
2942                          *
2943                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2944                          */
2945                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2946                             ins->inst_basereg == last_ins->inst_destbasereg &&
2947                             ins->inst_offset == last_ins->inst_offset) {
2948                                         ins->opcode = OP_ICOMPARE_IMM;
2949                                         ins->sreg1 = last_ins->sreg1;
2950
2951                                         /* check if we can remove cmp reg,0 with test null */
2952                                         if (!ins->inst_imm)
2953                                                 ins->opcode = OP_X86_TEST_NULL;
2954                                 }
2955
2956                         break;
2957                 }
2958
2959                 mono_peephole_ins (bb, ins);
2960         }
2961 }
2962
2963 void
2964 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2965 {
2966         MonoInst *ins, *n;
2967
2968         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2969                 switch (ins->opcode) {
2970                 case OP_ICONST:
2971                 case OP_I8CONST: {
2972                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
2973                         /* reg = 0 -> XOR (reg, reg) */
2974                         /* XOR sets cflags on x86, so we cant do it always */
2975                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
2976                                 ins->opcode = OP_LXOR;
2977                                 ins->sreg1 = ins->dreg;
2978                                 ins->sreg2 = ins->dreg;
2979                                 /* Fall through */
2980                         } else {
2981                                 break;
2982                         }
2983                 }
2984                 case OP_LXOR:
2985                         /*
2986                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2987                          * 0 result into 64 bits.
2988                          */
2989                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2990                                 ins->opcode = OP_IXOR;
2991                         }
2992                         /* Fall through */
2993                 case OP_IXOR:
2994                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2995                                 MonoInst *ins2;
2996
2997                                 /*
2998                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2999                                  * the latter has length 2-3 instead of 6 (reverse constant
3000                                  * propagation). These instruction sequences are very common
3001                                  * in the initlocals bblock.
3002                                  */
3003                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3004                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3005                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3006                                                 ins2->sreg1 = ins->dreg;
3007                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3008                                                 /* Continue */
3009                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3010                                                 NULLIFY_INS (ins2);
3011                                                 /* Continue */
3012                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3013                                                 /* Continue */
3014                                         } else {
3015                                                 break;
3016                                         }
3017                                 }
3018                         }
3019                         break;
3020                 case OP_IADD_IMM:
3021                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3022                                 ins->opcode = OP_X86_INC_REG;
3023                         break;
3024                 case OP_ISUB_IMM:
3025                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3026                                 ins->opcode = OP_X86_DEC_REG;
3027                         break;
3028                 }
3029
3030                 mono_peephole_ins (bb, ins);
3031         }
3032 }
3033
3034 #define NEW_INS(cfg,ins,dest,op) do {   \
3035                 MONO_INST_NEW ((cfg), (dest), (op)); \
3036         (dest)->cil_code = (ins)->cil_code; \
3037         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3038         } while (0)
3039
3040 /*
3041  * mono_arch_lowering_pass:
3042  *
3043  *  Converts complex opcodes into simpler ones so that each IR instruction
3044  * corresponds to one machine instruction.
3045  */
3046 void
3047 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3048 {
3049         MonoInst *ins, *n, *temp;
3050
3051         /*
3052          * FIXME: Need to add more instructions, but the current machine
3053          * description can't model some parts of the composite instructions like
3054          * cdq.
3055          */
3056         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3057                 switch (ins->opcode) {
3058                 case OP_DIV_IMM:
3059                 case OP_REM_IMM:
3060                 case OP_IDIV_IMM:
3061                 case OP_IDIV_UN_IMM:
3062                 case OP_IREM_UN_IMM:
3063                 case OP_LREM_IMM:
3064                 case OP_IREM_IMM:
3065                         mono_decompose_op_imm (cfg, bb, ins);
3066                         break;
3067                 case OP_COMPARE_IMM:
3068                 case OP_LCOMPARE_IMM:
3069                         if (!amd64_use_imm32 (ins->inst_imm)) {
3070                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3071                                 temp->inst_c0 = ins->inst_imm;
3072                                 temp->dreg = mono_alloc_ireg (cfg);
3073                                 ins->opcode = OP_COMPARE;
3074                                 ins->sreg2 = temp->dreg;
3075                         }
3076                         break;
3077 #ifndef __mono_ilp32__
3078                 case OP_LOAD_MEMBASE:
3079 #endif
3080                 case OP_LOADI8_MEMBASE:
3081                 /*  Don't generate memindex opcodes (to simplify */
3082                 /*  read sandboxing) */
3083                         if (!amd64_use_imm32 (ins->inst_offset)) {
3084                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3085                                 temp->inst_c0 = ins->inst_offset;
3086                                 temp->dreg = mono_alloc_ireg (cfg);
3087                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3088                                 ins->inst_indexreg = temp->dreg;
3089                         }
3090                         break;
3091 #ifndef __mono_ilp32__
3092                 case OP_STORE_MEMBASE_IMM:
3093 #endif
3094                 case OP_STOREI8_MEMBASE_IMM:
3095                         if (!amd64_use_imm32 (ins->inst_imm)) {
3096                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3097                                 temp->inst_c0 = ins->inst_imm;
3098                                 temp->dreg = mono_alloc_ireg (cfg);
3099                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3100                                 ins->sreg1 = temp->dreg;
3101                         }
3102                         break;
3103 #ifdef MONO_ARCH_SIMD_INTRINSICS
3104                 case OP_EXPAND_I1: {
3105                                 int temp_reg1 = mono_alloc_ireg (cfg);
3106                                 int temp_reg2 = mono_alloc_ireg (cfg);
3107                                 int original_reg = ins->sreg1;
3108
3109                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3110                                 temp->sreg1 = original_reg;
3111                                 temp->dreg = temp_reg1;
3112
3113                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3114                                 temp->sreg1 = temp_reg1;
3115                                 temp->dreg = temp_reg2;
3116                                 temp->inst_imm = 8;
3117
3118                                 NEW_INS (cfg, ins, temp, OP_LOR);
3119                                 temp->sreg1 = temp->dreg = temp_reg2;
3120                                 temp->sreg2 = temp_reg1;
3121
3122                                 ins->opcode = OP_EXPAND_I2;
3123                                 ins->sreg1 = temp_reg2;
3124                         }
3125                         break;
3126 #endif
3127                 default:
3128                         break;
3129                 }
3130         }
3131
3132         bb->max_vreg = cfg->next_vreg;
3133 }
3134
3135 static const int
3136 branch_cc_table [] = {
3137         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3138         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3139         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3140 };
3141
3142 /* Maps CMP_... constants to X86_CC_... constants */
3143 static const int
3144 cc_table [] = {
3145         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3146         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3147 };
3148
3149 static const int
3150 cc_signed_table [] = {
3151         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3152         FALSE, FALSE, FALSE, FALSE
3153 };
3154
3155 /*#include "cprop.c"*/
3156
3157 static unsigned char*
3158 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3159 {
3160         if (size == 8)
3161                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3162         else
3163                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3164
3165         if (size == 1)
3166                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3167         else if (size == 2)
3168                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3169         return code;
3170 }
3171
3172 static unsigned char*
3173 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3174 {
3175         int sreg = tree->sreg1;
3176         int need_touch = FALSE;
3177
3178 #if defined(TARGET_WIN32)
3179         need_touch = TRUE;
3180 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3181         if (!tree->flags & MONO_INST_INIT)
3182                 need_touch = TRUE;
3183 #endif
3184
3185         if (need_touch) {
3186                 guint8* br[5];
3187
3188                 /*
3189                  * Under Windows:
3190                  * If requested stack size is larger than one page,
3191                  * perform stack-touch operation
3192                  */
3193                 /*
3194                  * Generate stack probe code.
3195                  * Under Windows, it is necessary to allocate one page at a time,
3196                  * "touching" stack after each successful sub-allocation. This is
3197                  * because of the way stack growth is implemented - there is a
3198                  * guard page before the lowest stack page that is currently commited.
3199                  * Stack normally grows sequentially so OS traps access to the
3200                  * guard page and commits more pages when needed.
3201                  */
3202                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3203                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3204
3205                 br[2] = code; /* loop */
3206                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3207                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3208                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3209                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3210                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3211                 amd64_patch (br[3], br[2]);
3212                 amd64_test_reg_reg (code, sreg, sreg);
3213                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3214                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3215
3216                 br[1] = code; x86_jump8 (code, 0);
3217
3218                 amd64_patch (br[0], code);
3219                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3220                 amd64_patch (br[1], code);
3221                 amd64_patch (br[4], code);
3222         }
3223         else
3224                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3225
3226         if (tree->flags & MONO_INST_INIT) {
3227                 int offset = 0;
3228                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3229                         amd64_push_reg (code, AMD64_RAX);
3230                         offset += 8;
3231                 }
3232                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3233                         amd64_push_reg (code, AMD64_RCX);
3234                         offset += 8;
3235                 }
3236                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3237                         amd64_push_reg (code, AMD64_RDI);
3238                         offset += 8;
3239                 }
3240
3241                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3242                 if (sreg != AMD64_RCX)
3243                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3244                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3245
3246                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3247                 if (cfg->param_area)
3248                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3249                 amd64_cld (code);
3250                 amd64_prefix (code, X86_REP_PREFIX);
3251                 amd64_stosl (code);
3252
3253                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3254                         amd64_pop_reg (code, AMD64_RDI);
3255                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3256                         amd64_pop_reg (code, AMD64_RCX);
3257                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3258                         amd64_pop_reg (code, AMD64_RAX);
3259         }
3260         return code;
3261 }
3262
3263 static guint8*
3264 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3265 {
3266         CallInfo *cinfo;
3267         guint32 quad;
3268
3269         /* Move return value to the target register */
3270         /* FIXME: do this in the local reg allocator */
3271         switch (ins->opcode) {
3272         case OP_CALL:
3273         case OP_CALL_REG:
3274         case OP_CALL_MEMBASE:
3275         case OP_LCALL:
3276         case OP_LCALL_REG:
3277         case OP_LCALL_MEMBASE:
3278                 g_assert (ins->dreg == AMD64_RAX);
3279                 break;
3280         case OP_FCALL:
3281         case OP_FCALL_REG:
3282         case OP_FCALL_MEMBASE: {
3283                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3284                 if (rtype->type == MONO_TYPE_R4) {
3285                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3286                 }
3287                 else {
3288                         if (ins->dreg != AMD64_XMM0)
3289                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3290                 }
3291                 break;
3292         }
3293         case OP_RCALL:
3294         case OP_RCALL_REG:
3295         case OP_RCALL_MEMBASE:
3296                 if (ins->dreg != AMD64_XMM0)
3297                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3298                 break;
3299         case OP_VCALL:
3300         case OP_VCALL_REG:
3301         case OP_VCALL_MEMBASE:
3302         case OP_VCALL2:
3303         case OP_VCALL2_REG:
3304         case OP_VCALL2_MEMBASE:
3305                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3306                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3307                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3308
3309                         /* Load the destination address */
3310                         g_assert (loc->opcode == OP_REGOFFSET);
3311                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3312
3313                         for (quad = 0; quad < 2; quad ++) {
3314                                 switch (cinfo->ret.pair_storage [quad]) {
3315                                 case ArgInIReg:
3316                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3317                                         break;
3318                                 case ArgInFloatSSEReg:
3319                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3320                                         break;
3321                                 case ArgInDoubleSSEReg:
3322                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3323                                         break;
3324                                 case ArgNone:
3325                                         break;
3326                                 default:
3327                                         NOT_IMPLEMENTED;
3328                                 }
3329                         }
3330                 }
3331                 break;
3332         }
3333
3334         return code;
3335 }
3336
3337 #endif /* DISABLE_JIT */
3338
3339 #ifdef __APPLE__
3340 static int tls_gs_offset;
3341 #endif
3342
3343 gboolean
3344 mono_amd64_have_tls_get (void)
3345 {
3346 #ifdef TARGET_MACH
3347         static gboolean have_tls_get = FALSE;
3348         static gboolean inited = FALSE;
3349
3350         if (inited)
3351                 return have_tls_get;
3352
3353 #if MONO_HAVE_FAST_TLS
3354         guint8 *ins = (guint8*)pthread_getspecific;
3355
3356         /*
3357          * We're looking for these two instructions:
3358          *
3359          * mov    %gs:[offset](,%rdi,8),%rax
3360          * retq
3361          */
3362         have_tls_get = ins [0] == 0x65 &&
3363                        ins [1] == 0x48 &&
3364                        ins [2] == 0x8b &&
3365                        ins [3] == 0x04 &&
3366                        ins [4] == 0xfd &&
3367                        ins [6] == 0x00 &&
3368                        ins [7] == 0x00 &&
3369                        ins [8] == 0x00 &&
3370                        ins [9] == 0xc3;
3371
3372         tls_gs_offset = ins[5];
3373
3374         /*
3375          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3376          * For that version we're looking for these instructions:
3377          *
3378          * pushq  %rbp
3379          * movq   %rsp, %rbp
3380          * mov    %gs:[offset](,%rdi,8),%rax
3381          * popq   %rbp
3382          * retq
3383          */
3384         if (!have_tls_get) {
3385                 have_tls_get = ins [0] == 0x55 &&
3386                                ins [1] == 0x48 &&
3387                                ins [2] == 0x89 &&
3388                                ins [3] == 0xe5 &&
3389                                ins [4] == 0x65 &&
3390                                ins [5] == 0x48 &&
3391                                ins [6] == 0x8b &&
3392                                ins [7] == 0x04 &&
3393                                ins [8] == 0xfd &&
3394                                ins [10] == 0x00 &&
3395                                ins [11] == 0x00 &&
3396                                ins [12] == 0x00 &&
3397                                ins [13] == 0x5d &&
3398                                ins [14] == 0xc3;
3399
3400                 tls_gs_offset = ins[9];
3401         }
3402 #endif
3403
3404         inited = TRUE;
3405
3406         return have_tls_get;
3407 #elif defined(TARGET_ANDROID)
3408         return FALSE;
3409 #else
3410         return TRUE;
3411 #endif
3412 }
3413
3414 int
3415 mono_amd64_get_tls_gs_offset (void)
3416 {
3417 #ifdef TARGET_OSX
3418         return tls_gs_offset;
3419 #else
3420         g_assert_not_reached ();
3421         return -1;
3422 #endif
3423 }
3424
3425 /*
3426  * mono_amd64_emit_tls_get:
3427  * @code: buffer to store code to
3428  * @dreg: hard register where to place the result
3429  * @tls_offset: offset info
3430  *
3431  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3432  * the dreg register the item in the thread local storage identified
3433  * by tls_offset.
3434  *
3435  * Returns: a pointer to the end of the stored code
3436  */
3437 guint8*
3438 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3439 {
3440 #ifdef TARGET_WIN32
3441         if (tls_offset < 64) {
3442                 x86_prefix (code, X86_GS_PREFIX);
3443                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3444         } else {
3445                 guint8 *buf [16];
3446
3447                 g_assert (tls_offset < 0x440);
3448                 /* Load TEB->TlsExpansionSlots */
3449                 x86_prefix (code, X86_GS_PREFIX);
3450                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3451                 amd64_test_reg_reg (code, dreg, dreg);
3452                 buf [0] = code;
3453                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3454                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3455                 amd64_patch (buf [0], code);
3456         }
3457 #elif defined(__APPLE__)
3458         x86_prefix (code, X86_GS_PREFIX);
3459         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3460 #else
3461         if (optimize_for_xen) {
3462                 x86_prefix (code, X86_FS_PREFIX);
3463                 amd64_mov_reg_mem (code, dreg, 0, 8);
3464                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3465         } else {
3466                 x86_prefix (code, X86_FS_PREFIX);
3467                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3468         }
3469 #endif
3470         return code;
3471 }
3472
3473 #ifdef TARGET_WIN32
3474
3475 #define MAX_TEB_TLS_SLOTS 64
3476 #define TEB_TLS_SLOTS_OFFSET 0x1480
3477 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3478
3479 static guint8*
3480 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3481 {
3482         int tmp_reg = -1;
3483         guint8 * more_than_64_slots = NULL;
3484         guint8 * empty_slot = NULL;
3485         guint8 * tls_get_reg_done = NULL;
3486
3487         //Use temporary register for offset calculation?
3488         if (dreg == offset_reg) {
3489                 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3490                 amd64_push_reg (code, tmp_reg);
3491                 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3492                 offset_reg = tmp_reg;
3493         }
3494
3495         //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3496         amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3497         more_than_64_slots = code;
3498         amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3499
3500         //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3501         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3502         amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3503
3504         //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3505         x86_prefix (code, X86_GS_PREFIX);
3506         amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3507
3508         tls_get_reg_done = code;
3509         amd64_jump8 (code, 0);
3510
3511         amd64_patch (more_than_64_slots, code);
3512
3513         //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3514         x86_prefix (code, X86_GS_PREFIX);
3515         amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3516
3517         //Check for NULL in _TEB.TlsExpansionSlots.
3518         amd64_test_reg_reg (code, dreg, dreg);
3519         empty_slot = code;
3520         amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3521
3522         //TLS expansion slots are at index offset into the expansion array.
3523         //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3524         amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3525         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3526
3527         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3528
3529         amd64_patch (empty_slot, code);
3530         amd64_patch (tls_get_reg_done, code);
3531
3532         if (tmp_reg != -1)
3533                 amd64_pop_reg (code, tmp_reg);
3534
3535         return code;
3536 }
3537
3538 #endif
3539
3540 static guint8*
3541 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3542 {
3543         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3544 #ifdef TARGET_OSX
3545         if (dreg != offset_reg)
3546                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3547         amd64_prefix (code, X86_GS_PREFIX);
3548         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3549 #elif defined(__linux__)
3550         int tmpreg = -1;
3551
3552         if (dreg == offset_reg) {
3553                 /* Use a temporary reg by saving it to the redzone */
3554                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3555                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3556                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3557                 offset_reg = tmpreg;
3558         }
3559         x86_prefix (code, X86_FS_PREFIX);
3560         amd64_mov_reg_mem (code, dreg, 0, 8);
3561         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3562         if (tmpreg != -1)
3563                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3564 #elif defined(TARGET_WIN32)
3565         code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3566 #else
3567         g_assert_not_reached ();
3568 #endif
3569         return code;
3570 }
3571
3572 static guint8*
3573 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3574 {
3575 #ifdef TARGET_WIN32
3576         g_assert_not_reached ();
3577 #elif defined(__APPLE__)
3578         x86_prefix (code, X86_GS_PREFIX);
3579         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3580 #else
3581         g_assert (!optimize_for_xen);
3582         x86_prefix (code, X86_FS_PREFIX);
3583         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3584 #endif
3585         return code;
3586 }
3587
3588 static guint8*
3589 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3590 {
3591         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3592 #ifdef TARGET_WIN32
3593         g_assert_not_reached ();
3594 #elif defined(__APPLE__)
3595         x86_prefix (code, X86_GS_PREFIX);
3596         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3597 #else
3598         x86_prefix (code, X86_FS_PREFIX);
3599         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3600 #endif
3601         return code;
3602 }
3603
3604  /*
3605  * mono_arch_translate_tls_offset:
3606  *
3607  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3608  */
3609 int
3610 mono_arch_translate_tls_offset (int offset)
3611 {
3612 #ifdef __APPLE__
3613         return tls_gs_offset + (offset * 8);
3614 #else
3615         return offset;
3616 #endif
3617 }
3618
3619 /*
3620  * emit_setup_lmf:
3621  *
3622  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3623  */
3624 static guint8*
3625 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3626 {
3627         /*
3628          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3629          */
3630         /*
3631          * sp is saved right before calls but we need to save it here too so
3632          * async stack walks would work.
3633          */
3634         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3635         /* Save rbp */
3636         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3637         if (cfg->arch.omit_fp && cfa_offset != -1)
3638                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3639
3640         /* These can't contain refs */
3641         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3642         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3643         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3644         /* These are handled automatically by the stack marking code */
3645         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3646
3647         return code;
3648 }
3649
3650 /* benchmark and set based on cpu */
3651 #define LOOP_ALIGNMENT 8
3652 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3653
3654 #ifndef DISABLE_JIT
3655 void
3656 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3657 {
3658         MonoInst *ins;
3659         MonoCallInst *call;
3660         guint offset;
3661         guint8 *code = cfg->native_code + cfg->code_len;
3662         int max_len;
3663
3664         /* Fix max_offset estimate for each successor bb */
3665         if (cfg->opt & MONO_OPT_BRANCH) {
3666                 int current_offset = cfg->code_len;
3667                 MonoBasicBlock *current_bb;
3668                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3669                         current_bb->max_offset = current_offset;
3670                         current_offset += current_bb->max_length;
3671                 }
3672         }
3673
3674         if (cfg->opt & MONO_OPT_LOOP) {
3675                 int pad, align = LOOP_ALIGNMENT;
3676                 /* set alignment depending on cpu */
3677                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3678                         pad = align - pad;
3679                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3680                         amd64_padding (code, pad);
3681                         cfg->code_len += pad;
3682                         bb->native_offset = cfg->code_len;
3683                 }
3684         }
3685
3686         if (cfg->verbose_level > 2)
3687                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3688
3689         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3690                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3691                 g_assert (!cfg->compile_aot);
3692
3693                 cov->data [bb->dfn].cil_code = bb->cil_code;
3694                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3695                 /* this is not thread save, but good enough */
3696                 amd64_inc_membase (code, AMD64_R11, 0);
3697         }
3698
3699         offset = code - cfg->native_code;
3700
3701         mono_debug_open_block (cfg, bb, offset);
3702
3703     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3704                 x86_breakpoint (code);
3705
3706         MONO_BB_FOR_EACH_INS (bb, ins) {
3707                 offset = code - cfg->native_code;
3708
3709                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3710
3711 #define EXTRA_CODE_SPACE (16)
3712
3713                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3714                         cfg->code_size *= 2;
3715                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3716                         code = cfg->native_code + offset;
3717                         cfg->stat_code_reallocs++;
3718                 }
3719
3720                 if (cfg->debug_info)
3721                         mono_debug_record_line_number (cfg, ins, offset);
3722
3723                 switch (ins->opcode) {
3724                 case OP_BIGMUL:
3725                         amd64_mul_reg (code, ins->sreg2, TRUE);
3726                         break;
3727                 case OP_BIGMUL_UN:
3728                         amd64_mul_reg (code, ins->sreg2, FALSE);
3729                         break;
3730                 case OP_X86_SETEQ_MEMBASE:
3731                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3732                         break;
3733                 case OP_STOREI1_MEMBASE_IMM:
3734                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3735                         break;
3736                 case OP_STOREI2_MEMBASE_IMM:
3737                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3738                         break;
3739                 case OP_STOREI4_MEMBASE_IMM:
3740                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3741                         break;
3742                 case OP_STOREI1_MEMBASE_REG:
3743                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3744                         break;
3745                 case OP_STOREI2_MEMBASE_REG:
3746                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3747                         break;
3748                 /* In AMD64 NaCl, pointers are 4 bytes, */
3749                 /*  so STORE_* != STOREI8_*. Likewise below. */
3750                 case OP_STORE_MEMBASE_REG:
3751                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3752                         break;
3753                 case OP_STOREI8_MEMBASE_REG:
3754                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3755                         break;
3756                 case OP_STOREI4_MEMBASE_REG:
3757                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3758                         break;
3759                 case OP_STORE_MEMBASE_IMM:
3760                         /* In NaCl, this could be a PCONST type, which could */
3761                         /* mean a pointer type was copied directly into the  */
3762                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3763                         /* the value would be 0x00000000FFFFFFFF which is    */
3764                         /* not proper for an imm32 unless you cast it.       */
3765                         g_assert (amd64_is_imm32 (ins->inst_imm));
3766                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3767                         break;
3768                 case OP_STOREI8_MEMBASE_IMM:
3769                         g_assert (amd64_is_imm32 (ins->inst_imm));
3770                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3771                         break;
3772                 case OP_LOAD_MEM:
3773 #ifdef __mono_ilp32__
3774                         /* In ILP32, pointers are 4 bytes, so separate these */
3775                         /* cases, use literal 8 below where we really want 8 */
3776                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3777                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3778                         break;
3779 #endif
3780                 case OP_LOADI8_MEM:
3781                         // FIXME: Decompose this earlier
3782                         if (amd64_use_imm32 (ins->inst_imm))
3783                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3784                         else {
3785                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3786                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3787                         }
3788                         break;
3789                 case OP_LOADI4_MEM:
3790                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3791                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3792                         break;
3793                 case OP_LOADU4_MEM:
3794                         // FIXME: Decompose this earlier
3795                         if (amd64_use_imm32 (ins->inst_imm))
3796                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3797                         else {
3798                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3799                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3800                         }
3801                         break;
3802                 case OP_LOADU1_MEM:
3803                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3804                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3805                         break;
3806                 case OP_LOADU2_MEM:
3807                         /* For NaCl, pointers are 4 bytes, so separate these */
3808                         /* cases, use literal 8 below where we really want 8 */
3809                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3810                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3811                         break;
3812                 case OP_LOAD_MEMBASE:
3813                         g_assert (amd64_is_imm32 (ins->inst_offset));
3814                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3815                         break;
3816                 case OP_LOADI8_MEMBASE:
3817                         /* Use literal 8 instead of sizeof pointer or */
3818                         /* register, we really want 8 for this opcode */
3819                         g_assert (amd64_is_imm32 (ins->inst_offset));
3820                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3821                         break;
3822                 case OP_LOADI4_MEMBASE:
3823                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3824                         break;
3825                 case OP_LOADU4_MEMBASE:
3826                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3827                         break;
3828                 case OP_LOADU1_MEMBASE:
3829                         /* The cpu zero extends the result into 64 bits */
3830                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3831                         break;
3832                 case OP_LOADI1_MEMBASE:
3833                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3834                         break;
3835                 case OP_LOADU2_MEMBASE:
3836                         /* The cpu zero extends the result into 64 bits */
3837                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3838                         break;
3839                 case OP_LOADI2_MEMBASE:
3840                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3841                         break;
3842                 case OP_AMD64_LOADI8_MEMINDEX:
3843                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3844                         break;
3845                 case OP_LCONV_TO_I1:
3846                 case OP_ICONV_TO_I1:
3847                 case OP_SEXT_I1:
3848                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3849                         break;
3850                 case OP_LCONV_TO_I2:
3851                 case OP_ICONV_TO_I2:
3852                 case OP_SEXT_I2:
3853                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3854                         break;
3855                 case OP_LCONV_TO_U1:
3856                 case OP_ICONV_TO_U1:
3857                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3858                         break;
3859                 case OP_LCONV_TO_U2:
3860                 case OP_ICONV_TO_U2:
3861                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3862                         break;
3863                 case OP_ZEXT_I4:
3864                         /* Clean out the upper word */
3865                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3866                         break;
3867                 case OP_SEXT_I4:
3868                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3869                         break;
3870                 case OP_COMPARE:
3871                 case OP_LCOMPARE:
3872                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3873                         break;
3874                 case OP_COMPARE_IMM:
3875 #if defined(__mono_ilp32__)
3876                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3877                         g_assert (amd64_is_imm32 (ins->inst_imm));
3878                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3879                         break;
3880 #endif
3881                 case OP_LCOMPARE_IMM:
3882                         g_assert (amd64_is_imm32 (ins->inst_imm));
3883                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3884                         break;
3885                 case OP_X86_COMPARE_REG_MEMBASE:
3886                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3887                         break;
3888                 case OP_X86_TEST_NULL:
3889                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3890                         break;
3891                 case OP_AMD64_TEST_NULL:
3892                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3893                         break;
3894
3895                 case OP_X86_ADD_REG_MEMBASE:
3896                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3897                         break;
3898                 case OP_X86_SUB_REG_MEMBASE:
3899                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3900                         break;
3901                 case OP_X86_AND_REG_MEMBASE:
3902                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3903                         break;
3904                 case OP_X86_OR_REG_MEMBASE:
3905                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3906                         break;
3907                 case OP_X86_XOR_REG_MEMBASE:
3908                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3909                         break;
3910
3911                 case OP_X86_ADD_MEMBASE_IMM:
3912                         /* FIXME: Make a 64 version too */
3913                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3914                         break;
3915                 case OP_X86_SUB_MEMBASE_IMM:
3916                         g_assert (amd64_is_imm32 (ins->inst_imm));
3917                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3918                         break;
3919                 case OP_X86_AND_MEMBASE_IMM:
3920                         g_assert (amd64_is_imm32 (ins->inst_imm));
3921                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3922                         break;
3923                 case OP_X86_OR_MEMBASE_IMM:
3924                         g_assert (amd64_is_imm32 (ins->inst_imm));
3925                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3926                         break;
3927                 case OP_X86_XOR_MEMBASE_IMM:
3928                         g_assert (amd64_is_imm32 (ins->inst_imm));
3929                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3930                         break;
3931                 case OP_X86_ADD_MEMBASE_REG:
3932                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3933                         break;
3934                 case OP_X86_SUB_MEMBASE_REG:
3935                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3936                         break;
3937                 case OP_X86_AND_MEMBASE_REG:
3938                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3939                         break;
3940                 case OP_X86_OR_MEMBASE_REG:
3941                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3942                         break;
3943                 case OP_X86_XOR_MEMBASE_REG:
3944                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3945                         break;
3946                 case OP_X86_INC_MEMBASE:
3947                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3948                         break;
3949                 case OP_X86_INC_REG:
3950                         amd64_inc_reg_size (code, ins->dreg, 4);
3951                         break;
3952                 case OP_X86_DEC_MEMBASE:
3953                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3954                         break;
3955                 case OP_X86_DEC_REG:
3956                         amd64_dec_reg_size (code, ins->dreg, 4);
3957                         break;
3958                 case OP_X86_MUL_REG_MEMBASE:
3959                 case OP_X86_MUL_MEMBASE_REG:
3960                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3961                         break;
3962                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3963                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3964                         break;
3965                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3966                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3967                         break;
3968                 case OP_AMD64_COMPARE_MEMBASE_REG:
3969                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3970                         break;
3971                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3972                         g_assert (amd64_is_imm32 (ins->inst_imm));
3973                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3974                         break;
3975                 case OP_X86_COMPARE_MEMBASE8_IMM:
3976                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3977                         break;
3978                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3979                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3980                         break;
3981                 case OP_AMD64_COMPARE_REG_MEMBASE:
3982                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3983                         break;
3984
3985                 case OP_AMD64_ADD_REG_MEMBASE:
3986                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3987                         break;
3988                 case OP_AMD64_SUB_REG_MEMBASE:
3989                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3990                         break;
3991                 case OP_AMD64_AND_REG_MEMBASE:
3992                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3993                         break;
3994                 case OP_AMD64_OR_REG_MEMBASE:
3995                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3996                         break;
3997                 case OP_AMD64_XOR_REG_MEMBASE:
3998                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3999                         break;
4000
4001                 case OP_AMD64_ADD_MEMBASE_REG:
4002                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4003                         break;
4004                 case OP_AMD64_SUB_MEMBASE_REG:
4005                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4006                         break;
4007                 case OP_AMD64_AND_MEMBASE_REG:
4008                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4009                         break;
4010                 case OP_AMD64_OR_MEMBASE_REG:
4011                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4012                         break;
4013                 case OP_AMD64_XOR_MEMBASE_REG:
4014                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4015                         break;
4016
4017                 case OP_AMD64_ADD_MEMBASE_IMM:
4018                         g_assert (amd64_is_imm32 (ins->inst_imm));
4019                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4020                         break;
4021                 case OP_AMD64_SUB_MEMBASE_IMM:
4022                         g_assert (amd64_is_imm32 (ins->inst_imm));
4023                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4024                         break;
4025                 case OP_AMD64_AND_MEMBASE_IMM:
4026                         g_assert (amd64_is_imm32 (ins->inst_imm));
4027                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4028                         break;
4029                 case OP_AMD64_OR_MEMBASE_IMM:
4030                         g_assert (amd64_is_imm32 (ins->inst_imm));
4031                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4032                         break;
4033                 case OP_AMD64_XOR_MEMBASE_IMM:
4034                         g_assert (amd64_is_imm32 (ins->inst_imm));
4035                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4036                         break;
4037
4038                 case OP_BREAK:
4039                         amd64_breakpoint (code);
4040                         break;
4041                 case OP_RELAXED_NOP:
4042                         x86_prefix (code, X86_REP_PREFIX);
4043                         x86_nop (code);
4044                         break;
4045                 case OP_HARD_NOP:
4046                         x86_nop (code);
4047                         break;
4048                 case OP_NOP:
4049                 case OP_DUMMY_USE:
4050                 case OP_DUMMY_STORE:
4051                 case OP_DUMMY_ICONST:
4052                 case OP_DUMMY_R8CONST:
4053                 case OP_NOT_REACHED:
4054                 case OP_NOT_NULL:
4055                         break;
4056                 case OP_IL_SEQ_POINT:
4057                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4058                         break;
4059                 case OP_SEQ_POINT: {
4060                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4061                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4062                                 guint8 *label;
4063
4064                                 /* Load ss_tramp_var */
4065                                 /* This is equal to &ss_trampoline */
4066                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4067                                 /* Load the trampoline address */
4068                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4069                                 /* Call it if it is non-null */
4070                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4071                                 label = code;
4072                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4073                                 amd64_call_reg (code, AMD64_R11);
4074                                 amd64_patch (label, code);
4075                         }
4076
4077                         /*
4078                          * This is the address which is saved in seq points,
4079                          */
4080                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4081
4082                         if (cfg->compile_aot) {
4083                                 guint32 offset = code - cfg->native_code;
4084                                 guint32 val;
4085                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4086                                 guint8 *label;
4087
4088                                 /* Load info var */
4089                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4090                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4091                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4092                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4093                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4094                                 label = code;
4095                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4096                                 /* Call the trampoline */
4097                                 amd64_call_reg (code, AMD64_R11);
4098                                 amd64_patch (label, code);
4099                         } else {
4100                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4101                                 guint8 *label;
4102
4103                                 /*
4104                                  * Emit a test+branch against a constant, the constant will be overwritten
4105                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4106                                  */
4107                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4108                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4109                                 label = code;
4110                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4111
4112                                 g_assert (var);
4113                                 g_assert (var->opcode == OP_REGOFFSET);
4114                                 /* Load bp_tramp_var */
4115                                 /* This is equal to &bp_trampoline */
4116                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4117                                 /* Call the trampoline */
4118                                 amd64_call_membase (code, AMD64_R11, 0);
4119                                 amd64_patch (label, code);
4120                         }
4121                         /*
4122                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4123                          * to another IL offset.
4124                          */
4125                         x86_nop (code);
4126                         break;
4127                 }
4128                 case OP_ADDCC:
4129                 case OP_LADDCC:
4130                 case OP_LADD:
4131                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4132                         break;
4133                 case OP_ADC:
4134                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4135                         break;
4136                 case OP_ADD_IMM:
4137                 case OP_LADD_IMM:
4138                         g_assert (amd64_is_imm32 (ins->inst_imm));
4139                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4140                         break;
4141                 case OP_ADC_IMM:
4142                         g_assert (amd64_is_imm32 (ins->inst_imm));
4143                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4144                         break;
4145                 case OP_SUBCC:
4146                 case OP_LSUBCC:
4147                 case OP_LSUB:
4148                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4149                         break;
4150                 case OP_SBB:
4151                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4152                         break;
4153                 case OP_SUB_IMM:
4154                 case OP_LSUB_IMM:
4155                         g_assert (amd64_is_imm32 (ins->inst_imm));
4156                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4157                         break;
4158                 case OP_SBB_IMM:
4159                         g_assert (amd64_is_imm32 (ins->inst_imm));
4160                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4161                         break;
4162                 case OP_LAND:
4163                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4164                         break;
4165                 case OP_AND_IMM:
4166                 case OP_LAND_IMM:
4167                         g_assert (amd64_is_imm32 (ins->inst_imm));
4168                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4169                         break;
4170                 case OP_LMUL:
4171                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4172                         break;
4173                 case OP_MUL_IMM:
4174                 case OP_LMUL_IMM:
4175                 case OP_IMUL_IMM: {
4176                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4177
4178                         switch (ins->inst_imm) {
4179                         case 2:
4180                                 /* MOV r1, r2 */
4181                                 /* ADD r1, r1 */
4182                                 if (ins->dreg != ins->sreg1)
4183                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4184                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4185                                 break;
4186                         case 3:
4187                                 /* LEA r1, [r2 + r2*2] */
4188                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4189                                 break;
4190                         case 5:
4191                                 /* LEA r1, [r2 + r2*4] */
4192                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4193                                 break;
4194                         case 6:
4195                                 /* LEA r1, [r2 + r2*2] */
4196                                 /* ADD r1, r1          */
4197                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4198                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4199                                 break;
4200                         case 9:
4201                                 /* LEA r1, [r2 + r2*8] */
4202                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4203                                 break;
4204                         case 10:
4205                                 /* LEA r1, [r2 + r2*4] */
4206                                 /* ADD r1, r1          */
4207                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4208                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4209                                 break;
4210                         case 12:
4211                                 /* LEA r1, [r2 + r2*2] */
4212                                 /* SHL r1, 2           */
4213                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4214                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4215                                 break;
4216                         case 25:
4217                                 /* LEA r1, [r2 + r2*4] */
4218                                 /* LEA r1, [r1 + r1*4] */
4219                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4220                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4221                                 break;
4222                         case 100:
4223                                 /* LEA r1, [r2 + r2*4] */
4224                                 /* SHL r1, 2           */
4225                                 /* LEA r1, [r1 + r1*4] */
4226                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4227                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4228                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4229                                 break;
4230                         default:
4231                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4232                                 break;
4233                         }
4234                         break;
4235                 }
4236                 case OP_LDIV:
4237                 case OP_LREM:
4238                         /* Regalloc magic makes the div/rem cases the same */
4239                         if (ins->sreg2 == AMD64_RDX) {
4240                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4241                                 amd64_cdq (code);
4242                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4243                         } else {
4244                                 amd64_cdq (code);
4245                                 amd64_div_reg (code, ins->sreg2, TRUE);
4246                         }
4247                         break;
4248                 case OP_LDIV_UN:
4249                 case OP_LREM_UN:
4250                         if (ins->sreg2 == AMD64_RDX) {
4251                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4252                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4253                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4254                         } else {
4255                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4256                                 amd64_div_reg (code, ins->sreg2, FALSE);
4257                         }
4258                         break;
4259                 case OP_IDIV:
4260                 case OP_IREM:
4261                         if (ins->sreg2 == AMD64_RDX) {
4262                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4263                                 amd64_cdq_size (code, 4);
4264                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4265                         } else {
4266                                 amd64_cdq_size (code, 4);
4267                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4268                         }
4269                         break;
4270                 case OP_IDIV_UN:
4271                 case OP_IREM_UN:
4272                         if (ins->sreg2 == AMD64_RDX) {
4273                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4274                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4275                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4276                         } else {
4277                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4278                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4279                         }
4280                         break;
4281                 case OP_LMUL_OVF:
4282                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4283                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4284                         break;
4285                 case OP_LOR:
4286                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4287                         break;
4288                 case OP_OR_IMM:
4289                 case OP_LOR_IMM:
4290                         g_assert (amd64_is_imm32 (ins->inst_imm));
4291                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4292                         break;
4293                 case OP_LXOR:
4294                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4295                         break;
4296                 case OP_XOR_IMM:
4297                 case OP_LXOR_IMM:
4298                         g_assert (amd64_is_imm32 (ins->inst_imm));
4299                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4300                         break;
4301                 case OP_LSHL:
4302                         g_assert (ins->sreg2 == AMD64_RCX);
4303                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4304                         break;
4305                 case OP_LSHR:
4306                         g_assert (ins->sreg2 == AMD64_RCX);
4307                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4308                         break;
4309                 case OP_SHR_IMM:
4310                 case OP_LSHR_IMM:
4311                         g_assert (amd64_is_imm32 (ins->inst_imm));
4312                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4313                         break;
4314                 case OP_SHR_UN_IMM:
4315                         g_assert (amd64_is_imm32 (ins->inst_imm));
4316                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4317                         break;
4318                 case OP_LSHR_UN_IMM:
4319                         g_assert (amd64_is_imm32 (ins->inst_imm));
4320                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4321                         break;
4322                 case OP_LSHR_UN:
4323                         g_assert (ins->sreg2 == AMD64_RCX);
4324                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4325                         break;
4326                 case OP_SHL_IMM:
4327                 case OP_LSHL_IMM:
4328                         g_assert (amd64_is_imm32 (ins->inst_imm));
4329                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4330                         break;
4331
4332                 case OP_IADDCC:
4333                 case OP_IADD:
4334                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4335                         break;
4336                 case OP_IADC:
4337                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4338                         break;
4339                 case OP_IADD_IMM:
4340                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4341                         break;
4342                 case OP_IADC_IMM:
4343                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4344                         break;
4345                 case OP_ISUBCC:
4346                 case OP_ISUB:
4347                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4348                         break;
4349                 case OP_ISBB:
4350                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4351                         break;
4352                 case OP_ISUB_IMM:
4353                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4354                         break;
4355                 case OP_ISBB_IMM:
4356                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4357                         break;
4358                 case OP_IAND:
4359                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4360                         break;
4361                 case OP_IAND_IMM:
4362                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4363                         break;
4364                 case OP_IOR:
4365                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4366                         break;
4367                 case OP_IOR_IMM:
4368                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4369                         break;
4370                 case OP_IXOR:
4371                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4372                         break;
4373                 case OP_IXOR_IMM:
4374                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4375                         break;
4376                 case OP_INEG:
4377                         amd64_neg_reg_size (code, ins->sreg1, 4);
4378                         break;
4379                 case OP_INOT:
4380                         amd64_not_reg_size (code, ins->sreg1, 4);
4381                         break;
4382                 case OP_ISHL:
4383                         g_assert (ins->sreg2 == AMD64_RCX);
4384                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4385                         break;
4386                 case OP_ISHR:
4387                         g_assert (ins->sreg2 == AMD64_RCX);
4388                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4389                         break;
4390                 case OP_ISHR_IMM:
4391                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4392                         break;
4393                 case OP_ISHR_UN_IMM:
4394                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4395                         break;
4396                 case OP_ISHR_UN:
4397                         g_assert (ins->sreg2 == AMD64_RCX);
4398                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4399                         break;
4400                 case OP_ISHL_IMM:
4401                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4402                         break;
4403                 case OP_IMUL:
4404                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4405                         break;
4406                 case OP_IMUL_OVF:
4407                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4408                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4409                         break;
4410                 case OP_IMUL_OVF_UN:
4411                 case OP_LMUL_OVF_UN: {
4412                         /* the mul operation and the exception check should most likely be split */
4413                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4414                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4415                         /*g_assert (ins->sreg2 == X86_EAX);
4416                         g_assert (ins->dreg == X86_EAX);*/
4417                         if (ins->sreg2 == X86_EAX) {
4418                                 non_eax_reg = ins->sreg1;
4419                         } else if (ins->sreg1 == X86_EAX) {
4420                                 non_eax_reg = ins->sreg2;
4421                         } else {
4422                                 /* no need to save since we're going to store to it anyway */
4423                                 if (ins->dreg != X86_EAX) {
4424                                         saved_eax = TRUE;
4425                                         amd64_push_reg (code, X86_EAX);
4426                                 }
4427                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4428                                 non_eax_reg = ins->sreg2;
4429                         }
4430                         if (ins->dreg == X86_EDX) {
4431                                 if (!saved_eax) {
4432                                         saved_eax = TRUE;
4433                                         amd64_push_reg (code, X86_EAX);
4434                                 }
4435                         } else {
4436                                 saved_edx = TRUE;
4437                                 amd64_push_reg (code, X86_EDX);
4438                         }
4439                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4440                         /* save before the check since pop and mov don't change the flags */
4441                         if (ins->dreg != X86_EAX)
4442                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4443                         if (saved_edx)
4444                                 amd64_pop_reg (code, X86_EDX);
4445                         if (saved_eax)
4446                                 amd64_pop_reg (code, X86_EAX);
4447                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4448                         break;
4449                 }
4450                 case OP_ICOMPARE:
4451                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4452                         break;
4453                 case OP_ICOMPARE_IMM:
4454                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4455                         break;
4456                 case OP_IBEQ:
4457                 case OP_IBLT:
4458                 case OP_IBGT:
4459                 case OP_IBGE:
4460                 case OP_IBLE:
4461                 case OP_LBEQ:
4462                 case OP_LBLT:
4463                 case OP_LBGT:
4464                 case OP_LBGE:
4465                 case OP_LBLE:
4466                 case OP_IBNE_UN:
4467                 case OP_IBLT_UN:
4468                 case OP_IBGT_UN:
4469                 case OP_IBGE_UN:
4470                 case OP_IBLE_UN:
4471                 case OP_LBNE_UN:
4472                 case OP_LBLT_UN:
4473                 case OP_LBGT_UN:
4474                 case OP_LBGE_UN:
4475                 case OP_LBLE_UN:
4476                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4477                         break;
4478
4479                 case OP_CMOV_IEQ:
4480                 case OP_CMOV_IGE:
4481                 case OP_CMOV_IGT:
4482                 case OP_CMOV_ILE:
4483                 case OP_CMOV_ILT:
4484                 case OP_CMOV_INE_UN:
4485                 case OP_CMOV_IGE_UN:
4486                 case OP_CMOV_IGT_UN:
4487                 case OP_CMOV_ILE_UN:
4488                 case OP_CMOV_ILT_UN:
4489                 case OP_CMOV_LEQ:
4490                 case OP_CMOV_LGE:
4491                 case OP_CMOV_LGT:
4492                 case OP_CMOV_LLE:
4493                 case OP_CMOV_LLT:
4494                 case OP_CMOV_LNE_UN:
4495                 case OP_CMOV_LGE_UN:
4496                 case OP_CMOV_LGT_UN:
4497                 case OP_CMOV_LLE_UN:
4498                 case OP_CMOV_LLT_UN:
4499                         g_assert (ins->dreg == ins->sreg1);
4500                         /* This needs to operate on 64 bit values */
4501                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4502                         break;
4503
4504                 case OP_LNOT:
4505                         amd64_not_reg (code, ins->sreg1);
4506                         break;
4507                 case OP_LNEG:
4508                         amd64_neg_reg (code, ins->sreg1);
4509                         break;
4510
4511                 case OP_ICONST:
4512                 case OP_I8CONST:
4513                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4514                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4515                         else
4516                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4517                         break;
4518                 case OP_AOTCONST:
4519                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4520                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4521                         break;
4522                 case OP_JUMP_TABLE:
4523                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4524                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4525                         break;
4526                 case OP_MOVE:
4527                         if (ins->dreg != ins->sreg1)
4528                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4529                         break;
4530                 case OP_AMD64_SET_XMMREG_R4: {
4531                         if (cfg->r4fp) {
4532                                 if (ins->dreg != ins->sreg1)
4533                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4534                         } else {
4535                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4536                         }
4537                         break;
4538                 }
4539                 case OP_AMD64_SET_XMMREG_R8: {
4540                         if (ins->dreg != ins->sreg1)
4541                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4542                         break;
4543                 }
4544                 case OP_TAILCALL: {
4545                         MonoCallInst *call = (MonoCallInst*)ins;
4546                         int i, save_area_offset;
4547
4548                         g_assert (!cfg->method->save_lmf);
4549
4550                         /* Restore callee saved registers */
4551                         save_area_offset = cfg->arch.reg_save_area_offset;
4552                         for (i = 0; i < AMD64_NREG; ++i)
4553                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4554                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4555                                         save_area_offset += 8;
4556                                 }
4557
4558                         if (cfg->arch.omit_fp) {
4559                                 if (cfg->arch.stack_alloc_size)
4560                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4561                                 // FIXME:
4562                                 if (call->stack_usage)
4563                                         NOT_IMPLEMENTED;
4564                         } else {
4565                                 /* Copy arguments on the stack to our argument area */
4566                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4567                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4568                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4569                                 }
4570
4571                                 amd64_leave (code);
4572                         }
4573
4574                         offset = code - cfg->native_code;
4575                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4576                         if (cfg->compile_aot)
4577                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4578                         else
4579                                 amd64_set_reg_template (code, AMD64_R11);
4580                         amd64_jump_reg (code, AMD64_R11);
4581                         ins->flags |= MONO_INST_GC_CALLSITE;
4582                         ins->backend.pc_offset = code - cfg->native_code;
4583                         break;
4584                 }
4585                 case OP_CHECK_THIS:
4586                         /* ensure ins->sreg1 is not NULL */
4587                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4588                         break;
4589                 case OP_ARGLIST: {
4590                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4591                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4592                         break;
4593                 }
4594                 case OP_CALL:
4595                 case OP_FCALL:
4596                 case OP_RCALL:
4597                 case OP_LCALL:
4598                 case OP_VCALL:
4599                 case OP_VCALL2:
4600                 case OP_VOIDCALL:
4601                         call = (MonoCallInst*)ins;
4602                         /*
4603                          * The AMD64 ABI forces callers to know about varargs.
4604                          */
4605                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4606                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4607                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4608                                 /*
4609                                  * Since the unmanaged calling convention doesn't contain a
4610                                  * 'vararg' entry, we have to treat every pinvoke call as a
4611                                  * potential vararg call.
4612                                  */
4613                                 guint32 nregs, i;
4614                                 nregs = 0;
4615                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4616                                         if (call->used_fregs & (1 << i))
4617                                                 nregs ++;
4618                                 if (!nregs)
4619                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4620                                 else
4621                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4622                         }
4623
4624                         if (ins->flags & MONO_INST_HAS_METHOD)
4625                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4626                         else
4627                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4628                         ins->flags |= MONO_INST_GC_CALLSITE;
4629                         ins->backend.pc_offset = code - cfg->native_code;
4630                         code = emit_move_return_value (cfg, ins, code);
4631                         break;
4632                 case OP_FCALL_REG:
4633                 case OP_RCALL_REG:
4634                 case OP_LCALL_REG:
4635                 case OP_VCALL_REG:
4636                 case OP_VCALL2_REG:
4637                 case OP_VOIDCALL_REG:
4638                 case OP_CALL_REG:
4639                         call = (MonoCallInst*)ins;
4640
4641                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4642                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4643                                 ins->sreg1 = AMD64_R11;
4644                         }
4645
4646                         /*
4647                          * The AMD64 ABI forces callers to know about varargs.
4648                          */
4649                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4650                                 if (ins->sreg1 == AMD64_RAX) {
4651                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4652                                         ins->sreg1 = AMD64_R11;
4653                                 }
4654                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4655                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4656                                 /*
4657                                  * Since the unmanaged calling convention doesn't contain a
4658                                  * 'vararg' entry, we have to treat every pinvoke call as a
4659                                  * potential vararg call.
4660                                  */
4661                                 guint32 nregs, i;
4662                                 nregs = 0;
4663                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4664                                         if (call->used_fregs & (1 << i))
4665                                                 nregs ++;
4666                                 if (ins->sreg1 == AMD64_RAX) {
4667                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4668                                         ins->sreg1 = AMD64_R11;
4669                                 }
4670                                 if (!nregs)
4671                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4672                                 else
4673                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4674                         }
4675
4676                         amd64_call_reg (code, ins->sreg1);
4677                         ins->flags |= MONO_INST_GC_CALLSITE;
4678                         ins->backend.pc_offset = code - cfg->native_code;
4679                         code = emit_move_return_value (cfg, ins, code);
4680                         break;
4681                 case OP_FCALL_MEMBASE:
4682                 case OP_RCALL_MEMBASE:
4683                 case OP_LCALL_MEMBASE:
4684                 case OP_VCALL_MEMBASE:
4685                 case OP_VCALL2_MEMBASE:
4686                 case OP_VOIDCALL_MEMBASE:
4687                 case OP_CALL_MEMBASE:
4688                         call = (MonoCallInst*)ins;
4689
4690                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4691                         ins->flags |= MONO_INST_GC_CALLSITE;
4692                         ins->backend.pc_offset = code - cfg->native_code;
4693                         code = emit_move_return_value (cfg, ins, code);
4694                         break;
4695                 case OP_DYN_CALL: {
4696                         int i;
4697                         MonoInst *var = cfg->dyn_call_var;
4698                         guint8 *label;
4699
4700                         g_assert (var->opcode == OP_REGOFFSET);
4701
4702                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4703                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4704                         /* r10 = ftn */
4705                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4706
4707                         /* Save args buffer */
4708                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4709
4710                         /* Set fp arg regs */
4711                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4712                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4713                         label = code;
4714                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4715                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4716                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4717                         amd64_patch (label, code);
4718
4719                         /* Set stack args */
4720                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4721                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4722                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4723                         }
4724
4725                         /* Set argument registers */
4726                         for (i = 0; i < PARAM_REGS; ++i)
4727                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4728
4729                         /* Make the call */
4730                         amd64_call_reg (code, AMD64_R10);
4731
4732                         ins->flags |= MONO_INST_GC_CALLSITE;
4733                         ins->backend.pc_offset = code - cfg->native_code;
4734
4735                         /* Save result */
4736                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4737                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4738                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4739                         break;
4740                 }
4741                 case OP_AMD64_SAVE_SP_TO_LMF: {
4742                         MonoInst *lmf_var = cfg->lmf_var;
4743                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4744                         break;
4745                 }
4746                 case OP_X86_PUSH:
4747                         g_assert_not_reached ();
4748                         amd64_push_reg (code, ins->sreg1);
4749                         break;
4750                 case OP_X86_PUSH_IMM:
4751                         g_assert_not_reached ();
4752                         g_assert (amd64_is_imm32 (ins->inst_imm));
4753                         amd64_push_imm (code, ins->inst_imm);
4754                         break;
4755                 case OP_X86_PUSH_MEMBASE:
4756                         g_assert_not_reached ();
4757                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4758                         break;
4759                 case OP_X86_PUSH_OBJ: {
4760                         int size = ALIGN_TO (ins->inst_imm, 8);
4761
4762                         g_assert_not_reached ();
4763
4764                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4765                         amd64_push_reg (code, AMD64_RDI);
4766                         amd64_push_reg (code, AMD64_RSI);
4767                         amd64_push_reg (code, AMD64_RCX);
4768                         if (ins->inst_offset)
4769                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4770                         else
4771                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4772                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4773                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4774                         amd64_cld (code);
4775                         amd64_prefix (code, X86_REP_PREFIX);
4776                         amd64_movsd (code);
4777                         amd64_pop_reg (code, AMD64_RCX);
4778                         amd64_pop_reg (code, AMD64_RSI);
4779                         amd64_pop_reg (code, AMD64_RDI);
4780                         break;
4781                 }
4782                 case OP_GENERIC_CLASS_INIT: {
4783                         static int byte_offset = -1;
4784                         static guint8 bitmask;
4785                         guint8 *jump;
4786
4787                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4788
4789                         if (byte_offset < 0)
4790                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4791
4792                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4793                         jump = code;
4794                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4795
4796                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4797                         ins->flags |= MONO_INST_GC_CALLSITE;
4798                         ins->backend.pc_offset = code - cfg->native_code;
4799
4800                         x86_patch (jump, code);
4801                         break;
4802                 }
4803
4804                 case OP_X86_LEA:
4805                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4806                         break;
4807                 case OP_X86_LEA_MEMBASE:
4808                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4809                         break;
4810                 case OP_X86_XCHG:
4811                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4812                         break;
4813                 case OP_LOCALLOC:
4814                         /* keep alignment */
4815                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4816                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4817                         code = mono_emit_stack_alloc (cfg, code, ins);
4818                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4819                         if (cfg->param_area)
4820                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4821                         break;
4822                 case OP_LOCALLOC_IMM: {
4823                         guint32 size = ins->inst_imm;
4824                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4825
4826                         if (ins->flags & MONO_INST_INIT) {
4827                                 if (size < 64) {
4828                                         int i;
4829
4830                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4831                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4832
4833                                         for (i = 0; i < size; i += 8)
4834                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4835                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4836                                 } else {
4837                                         amd64_mov_reg_imm (code, ins->dreg, size);
4838                                         ins->sreg1 = ins->dreg;
4839
4840                                         code = mono_emit_stack_alloc (cfg, code, ins);
4841                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4842                                 }
4843                         } else {
4844                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4845                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4846                         }
4847                         if (cfg->param_area)
4848                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4849                         break;
4850                 }
4851                 case OP_THROW: {
4852                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4853                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4854                                              (gpointer)"mono_arch_throw_exception", FALSE);
4855                         ins->flags |= MONO_INST_GC_CALLSITE;
4856                         ins->backend.pc_offset = code - cfg->native_code;
4857                         break;
4858                 }
4859                 case OP_RETHROW: {
4860                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4861                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4862                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4863                         ins->flags |= MONO_INST_GC_CALLSITE;
4864                         ins->backend.pc_offset = code - cfg->native_code;
4865                         break;
4866                 }
4867                 case OP_CALL_HANDLER:
4868                         /* Align stack */
4869                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4870                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4871                         amd64_call_imm (code, 0);
4872                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4873                         /* Restore stack alignment */
4874                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4875                         break;
4876                 case OP_START_HANDLER: {
4877                         /* Even though we're saving RSP, use sizeof */
4878                         /* gpointer because spvar is of type IntPtr */
4879                         /* see: mono_create_spvar_for_region */
4880                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4881                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4882
4883                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4884                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4885                                 cfg->param_area) {
4886                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4887                         }
4888                         break;
4889                 }
4890                 case OP_ENDFINALLY: {
4891                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4892                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4893                         amd64_ret (code);
4894                         break;
4895                 }
4896                 case OP_ENDFILTER: {
4897                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4898                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4899                         /* The local allocator will put the result into RAX */
4900                         amd64_ret (code);
4901                         break;
4902                 }
4903                 case OP_GET_EX_OBJ:
4904                         if (ins->dreg != AMD64_RAX)
4905                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4906                         break;
4907                 case OP_LABEL:
4908                         ins->inst_c0 = code - cfg->native_code;
4909                         break;
4910                 case OP_BR:
4911                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4912                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4913                         //break;
4914                                 if (ins->inst_target_bb->native_offset) {
4915                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4916                                 } else {
4917                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4918                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4919                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4920                                                 x86_jump8 (code, 0);
4921                                         else
4922                                                 x86_jump32 (code, 0);
4923                         }
4924                         break;
4925                 case OP_BR_REG:
4926                         amd64_jump_reg (code, ins->sreg1);
4927                         break;
4928                 case OP_ICNEQ:
4929                 case OP_ICGE:
4930                 case OP_ICLE:
4931                 case OP_ICGE_UN:
4932                 case OP_ICLE_UN:
4933
4934                 case OP_CEQ:
4935                 case OP_LCEQ:
4936                 case OP_ICEQ:
4937                 case OP_CLT:
4938                 case OP_LCLT:
4939                 case OP_ICLT:
4940                 case OP_CGT:
4941                 case OP_ICGT:
4942                 case OP_LCGT:
4943                 case OP_CLT_UN:
4944                 case OP_LCLT_UN:
4945                 case OP_ICLT_UN:
4946                 case OP_CGT_UN:
4947                 case OP_LCGT_UN:
4948                 case OP_ICGT_UN:
4949                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4950                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4951                         break;
4952                 case OP_COND_EXC_EQ:
4953                 case OP_COND_EXC_NE_UN:
4954                 case OP_COND_EXC_LT:
4955                 case OP_COND_EXC_LT_UN:
4956                 case OP_COND_EXC_GT:
4957                 case OP_COND_EXC_GT_UN:
4958                 case OP_COND_EXC_GE:
4959                 case OP_COND_EXC_GE_UN:
4960                 case OP_COND_EXC_LE:
4961                 case OP_COND_EXC_LE_UN:
4962                 case OP_COND_EXC_IEQ:
4963                 case OP_COND_EXC_INE_UN:
4964                 case OP_COND_EXC_ILT:
4965                 case OP_COND_EXC_ILT_UN:
4966                 case OP_COND_EXC_IGT:
4967                 case OP_COND_EXC_IGT_UN:
4968                 case OP_COND_EXC_IGE:
4969                 case OP_COND_EXC_IGE_UN:
4970                 case OP_COND_EXC_ILE:
4971                 case OP_COND_EXC_ILE_UN:
4972                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4973                         break;
4974                 case OP_COND_EXC_OV:
4975                 case OP_COND_EXC_NO:
4976                 case OP_COND_EXC_C:
4977                 case OP_COND_EXC_NC:
4978                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4979                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4980                         break;
4981                 case OP_COND_EXC_IOV:
4982                 case OP_COND_EXC_INO:
4983                 case OP_COND_EXC_IC:
4984                 case OP_COND_EXC_INC:
4985                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4986                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4987                         break;
4988
4989                 /* floating point opcodes */
4990                 case OP_R8CONST: {
4991                         double d = *(double *)ins->inst_p0;
4992
4993                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4994                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4995                         }
4996                         else {
4997                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4998                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4999                         }
5000                         break;
5001                 }
5002                 case OP_R4CONST: {
5003                         float f = *(float *)ins->inst_p0;
5004
5005                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5006                                 if (cfg->r4fp)
5007                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5008                                 else
5009                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5010                         }
5011                         else {
5012                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5013                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5014                                 if (!cfg->r4fp)
5015                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5016                         }
5017                         break;
5018                 }
5019                 case OP_STORER8_MEMBASE_REG:
5020                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5021                         break;
5022                 case OP_LOADR8_MEMBASE:
5023                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5024                         break;
5025                 case OP_STORER4_MEMBASE_REG:
5026                         if (cfg->r4fp) {
5027                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5028                         } else {
5029                                 /* This requires a double->single conversion */
5030                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5031                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5032                         }
5033                         break;
5034                 case OP_LOADR4_MEMBASE:
5035                         if (cfg->r4fp) {
5036                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5037                         } else {
5038                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5039                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5040                         }
5041                         break;
5042                 case OP_ICONV_TO_R4:
5043                         if (cfg->r4fp) {
5044                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5045                         } else {
5046                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5047                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5048                         }
5049                         break;
5050                 case OP_ICONV_TO_R8:
5051                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5052                         break;
5053                 case OP_LCONV_TO_R4:
5054                         if (cfg->r4fp) {
5055                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5056                         } else {
5057                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5058                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5059                         }
5060                         break;
5061                 case OP_LCONV_TO_R8:
5062                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5063                         break;
5064                 case OP_FCONV_TO_R4:
5065                         if (cfg->r4fp) {
5066                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5067                         } else {
5068                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5069                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5070                         }
5071                         break;
5072                 case OP_FCONV_TO_I1:
5073                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5074                         break;
5075                 case OP_FCONV_TO_U1:
5076                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5077                         break;
5078                 case OP_FCONV_TO_I2:
5079                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5080                         break;
5081                 case OP_FCONV_TO_U2:
5082                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5083                         break;
5084                 case OP_FCONV_TO_U4:
5085                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5086                         break;
5087                 case OP_FCONV_TO_I4:
5088                 case OP_FCONV_TO_I:
5089                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5090                         break;
5091                 case OP_FCONV_TO_I8:
5092                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5093                         break;
5094
5095                 case OP_RCONV_TO_I1:
5096                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5097                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5098                         break;
5099                 case OP_RCONV_TO_U1:
5100                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5101                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5102                         break;
5103                 case OP_RCONV_TO_I2:
5104                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5105                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5106                         break;
5107                 case OP_RCONV_TO_U2:
5108                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5109                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5110                         break;
5111                 case OP_RCONV_TO_I4:
5112                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113                         break;
5114                 case OP_RCONV_TO_U4:
5115                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5116                         break;
5117                 case OP_RCONV_TO_I8:
5118                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5119                         break;
5120                 case OP_RCONV_TO_R8:
5121                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5122                         break;
5123                 case OP_RCONV_TO_R4:
5124                         if (ins->dreg != ins->sreg1)
5125                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5126                         break;
5127
5128                 case OP_LCONV_TO_R_UN: {
5129                         guint8 *br [2];
5130
5131                         /* Based on gcc code */
5132                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5133                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5134
5135                         /* Positive case */
5136                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5137                         br [1] = code; x86_jump8 (code, 0);
5138                         amd64_patch (br [0], code);
5139
5140                         /* Negative case */
5141                         /* Save to the red zone */
5142                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5143                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5144                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5145                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5146                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5147                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5148                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5149                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5150                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5151                         /* Restore */
5152                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5153                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5154                         amd64_patch (br [1], code);
5155                         break;
5156                 }
5157                 case OP_LCONV_TO_OVF_U4:
5158                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5159                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5160                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5161                         break;
5162                 case OP_LCONV_TO_OVF_I4_UN:
5163                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5164                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5165                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5166                         break;
5167                 case OP_FMOVE:
5168                         if (ins->dreg != ins->sreg1)
5169                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5170                         break;
5171                 case OP_RMOVE:
5172                         if (ins->dreg != ins->sreg1)
5173                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5174                         break;
5175                 case OP_MOVE_F_TO_I4:
5176                         if (cfg->r4fp) {
5177                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5178                         } else {
5179                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5180                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5181                         }
5182                         break;
5183                 case OP_MOVE_I4_TO_F:
5184                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5185                         if (!cfg->r4fp)
5186                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5187                         break;
5188                 case OP_MOVE_F_TO_I8:
5189                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5190                         break;
5191                 case OP_MOVE_I8_TO_F:
5192                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5193                         break;
5194                 case OP_FADD:
5195                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5196                         break;
5197                 case OP_FSUB:
5198                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5199                         break;
5200                 case OP_FMUL:
5201                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5202                         break;
5203                 case OP_FDIV:
5204                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5205                         break;
5206                 case OP_FNEG: {
5207                         static double r8_0 = -0.0;
5208
5209                         g_assert (ins->sreg1 == ins->dreg);
5210
5211                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5212                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5213                         break;
5214                 }
5215                 case OP_SIN:
5216                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5217                         break;
5218                 case OP_COS:
5219                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5220                         break;
5221                 case OP_ABS: {
5222                         static guint64 d = 0x7fffffffffffffffUL;
5223
5224                         g_assert (ins->sreg1 == ins->dreg);
5225
5226                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5227                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5228                         break;
5229                 }
5230                 case OP_SQRT:
5231                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5232                         break;
5233
5234                 case OP_RADD:
5235                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5236                         break;
5237                 case OP_RSUB:
5238                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5239                         break;
5240                 case OP_RMUL:
5241                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5242                         break;
5243                 case OP_RDIV:
5244                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5245                         break;
5246                 case OP_RNEG: {
5247                         static float r4_0 = -0.0;
5248
5249                         g_assert (ins->sreg1 == ins->dreg);
5250
5251                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5252                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5253                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5254                         break;
5255                 }
5256
5257                 case OP_IMIN:
5258                         g_assert (cfg->opt & MONO_OPT_CMOV);
5259                         g_assert (ins->dreg == ins->sreg1);
5260                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5261                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5262                         break;
5263                 case OP_IMIN_UN:
5264                         g_assert (cfg->opt & MONO_OPT_CMOV);
5265                         g_assert (ins->dreg == ins->sreg1);
5266                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5267                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5268                         break;
5269                 case OP_IMAX:
5270                         g_assert (cfg->opt & MONO_OPT_CMOV);
5271                         g_assert (ins->dreg == ins->sreg1);
5272                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5273                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5274                         break;
5275                 case OP_IMAX_UN:
5276                         g_assert (cfg->opt & MONO_OPT_CMOV);
5277                         g_assert (ins->dreg == ins->sreg1);
5278                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5279                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5280                         break;
5281                 case OP_LMIN:
5282                         g_assert (cfg->opt & MONO_OPT_CMOV);
5283                         g_assert (ins->dreg == ins->sreg1);
5284                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5285                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5286                         break;
5287                 case OP_LMIN_UN:
5288                         g_assert (cfg->opt & MONO_OPT_CMOV);
5289                         g_assert (ins->dreg == ins->sreg1);
5290                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5291                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5292                         break;
5293                 case OP_LMAX:
5294                         g_assert (cfg->opt & MONO_OPT_CMOV);
5295                         g_assert (ins->dreg == ins->sreg1);
5296                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5297                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5298                         break;
5299                 case OP_LMAX_UN:
5300                         g_assert (cfg->opt & MONO_OPT_CMOV);
5301                         g_assert (ins->dreg == ins->sreg1);
5302                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5303                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5304                         break;
5305                 case OP_X86_FPOP:
5306                         break;
5307                 case OP_FCOMPARE:
5308                         /*
5309                          * The two arguments are swapped because the fbranch instructions
5310                          * depend on this for the non-sse case to work.
5311                          */
5312                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5313                         break;
5314                 case OP_RCOMPARE:
5315                         /*
5316                          * FIXME: Get rid of this.
5317                          * The two arguments are swapped because the fbranch instructions
5318                          * depend on this for the non-sse case to work.
5319                          */
5320                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5321                         break;
5322                 case OP_FCNEQ:
5323                 case OP_FCEQ: {
5324                         /* zeroing the register at the start results in
5325                          * shorter and faster code (we can also remove the widening op)
5326                          */
5327                         guchar *unordered_check;
5328
5329                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5330                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5331                         unordered_check = code;
5332                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5333
5334                         if (ins->opcode == OP_FCEQ) {
5335                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5336                                 amd64_patch (unordered_check, code);
5337                         } else {
5338                                 guchar *jump_to_end;
5339                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5340                                 jump_to_end = code;
5341                                 x86_jump8 (code, 0);
5342                                 amd64_patch (unordered_check, code);
5343                                 amd64_inc_reg (code, ins->dreg);
5344                                 amd64_patch (jump_to_end, code);
5345                         }
5346                         break;
5347                 }
5348                 case OP_FCLT:
5349                 case OP_FCLT_UN: {
5350                         /* zeroing the register at the start results in
5351                          * shorter and faster code (we can also remove the widening op)
5352                          */
5353                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5354                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5355                         if (ins->opcode == OP_FCLT_UN) {
5356                                 guchar *unordered_check = code;
5357                                 guchar *jump_to_end;
5358                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5359                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5360                                 jump_to_end = code;
5361                                 x86_jump8 (code, 0);
5362                                 amd64_patch (unordered_check, code);
5363                                 amd64_inc_reg (code, ins->dreg);
5364                                 amd64_patch (jump_to_end, code);
5365                         } else {
5366                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5367                         }
5368                         break;
5369                 }
5370                 case OP_FCLE: {
5371                         guchar *unordered_check;
5372                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5373                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5374                         unordered_check = code;
5375                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5376                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5377                         amd64_patch (unordered_check, code);
5378                         break;
5379                 }
5380                 case OP_FCGT:
5381                 case OP_FCGT_UN: {
5382                         /* zeroing the register at the start results in
5383                          * shorter and faster code (we can also remove the widening op)
5384                          */
5385                         guchar *unordered_check;
5386
5387                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5388                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5389                         if (ins->opcode == OP_FCGT) {
5390                                 unordered_check = code;
5391                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5392                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5393                                 amd64_patch (unordered_check, code);
5394                         } else {
5395                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5396                         }
5397                         break;
5398                 }
5399                 case OP_FCGE: {
5400                         guchar *unordered_check;
5401                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5402                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5403                         unordered_check = code;
5404                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5405                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5406                         amd64_patch (unordered_check, code);
5407                         break;
5408                 }
5409
5410                 case OP_RCEQ:
5411                 case OP_RCGT:
5412                 case OP_RCLT:
5413                 case OP_RCLT_UN:
5414                 case OP_RCGT_UN: {
5415                         int x86_cond;
5416                         gboolean unordered = FALSE;
5417
5418                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5419                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5420
5421                         switch (ins->opcode) {
5422                         case OP_RCEQ:
5423                                 x86_cond = X86_CC_EQ;
5424                                 break;
5425                         case OP_RCGT:
5426                                 x86_cond = X86_CC_LT;
5427                                 break;
5428                         case OP_RCLT:
5429                                 x86_cond = X86_CC_GT;
5430                                 break;
5431                         case OP_RCLT_UN:
5432                                 x86_cond = X86_CC_GT;
5433                                 unordered = TRUE;
5434                                 break;
5435                         case OP_RCGT_UN:
5436                                 x86_cond = X86_CC_LT;
5437                                 unordered = TRUE;
5438                                 break;
5439                         default:
5440                                 g_assert_not_reached ();
5441                                 break;
5442                         }
5443
5444                         if (unordered) {
5445                                 guchar *unordered_check;
5446                                 guchar *jump_to_end;
5447
5448                                 unordered_check = code;
5449                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5450                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5451                                 jump_to_end = code;
5452                                 x86_jump8 (code, 0);
5453                                 amd64_patch (unordered_check, code);
5454                                 amd64_inc_reg (code, ins->dreg);
5455                                 amd64_patch (jump_to_end, code);
5456                         } else {
5457                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5458                         }
5459                         break;
5460                 }
5461                 case OP_FCLT_MEMBASE:
5462                 case OP_FCGT_MEMBASE:
5463                 case OP_FCLT_UN_MEMBASE:
5464                 case OP_FCGT_UN_MEMBASE:
5465                 case OP_FCEQ_MEMBASE: {
5466                         guchar *unordered_check, *jump_to_end;
5467                         int x86_cond;
5468
5469                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5470                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5471
5472                         switch (ins->opcode) {
5473                         case OP_FCEQ_MEMBASE:
5474                                 x86_cond = X86_CC_EQ;
5475                                 break;
5476                         case OP_FCLT_MEMBASE:
5477                         case OP_FCLT_UN_MEMBASE:
5478                                 x86_cond = X86_CC_LT;
5479                                 break;
5480                         case OP_FCGT_MEMBASE:
5481                         case OP_FCGT_UN_MEMBASE:
5482                                 x86_cond = X86_CC_GT;
5483                                 break;
5484                         default:
5485                                 g_assert_not_reached ();
5486                         }
5487
5488                         unordered_check = code;
5489                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5490                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5491
5492                         switch (ins->opcode) {
5493                         case OP_FCEQ_MEMBASE:
5494                         case OP_FCLT_MEMBASE:
5495                         case OP_FCGT_MEMBASE:
5496                                 amd64_patch (unordered_check, code);
5497                                 break;
5498                         case OP_FCLT_UN_MEMBASE:
5499                         case OP_FCGT_UN_MEMBASE:
5500                                 jump_to_end = code;
5501                                 x86_jump8 (code, 0);
5502                                 amd64_patch (unordered_check, code);
5503                                 amd64_inc_reg (code, ins->dreg);
5504                                 amd64_patch (jump_to_end, code);
5505                                 break;
5506                         default:
5507                                 break;
5508                         }
5509                         break;
5510                 }
5511                 case OP_FBEQ: {
5512                         guchar *jump = code;
5513                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5514                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5515                         amd64_patch (jump, code);
5516                         break;
5517                 }
5518                 case OP_FBNE_UN:
5519                         /* Branch if C013 != 100 */
5520                         /* branch if !ZF or (PF|CF) */
5521                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5522                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5523                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5524                         break;
5525                 case OP_FBLT:
5526                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5527                         break;
5528                 case OP_FBLT_UN:
5529                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5530                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5531                         break;
5532                 case OP_FBGT:
5533                 case OP_FBGT_UN:
5534                         if (ins->opcode == OP_FBGT) {
5535                                 guchar *br1;
5536
5537                                 /* skip branch if C1=1 */
5538                                 br1 = code;
5539                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5540                                 /* branch if (C0 | C3) = 1 */
5541                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5542                                 amd64_patch (br1, code);
5543                                 break;
5544                         } else {
5545                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5546                         }
5547                         break;
5548                 case OP_FBGE: {
5549                         /* Branch if C013 == 100 or 001 */
5550                         guchar *br1;
5551
5552                         /* skip branch if C1=1 */
5553                         br1 = code;
5554                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5555                         /* branch if (C0 | C3) = 1 */
5556                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5557                         amd64_patch (br1, code);
5558                         break;
5559                 }
5560                 case OP_FBGE_UN:
5561                         /* Branch if C013 == 000 */
5562                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5563                         break;
5564                 case OP_FBLE: {
5565                         /* Branch if C013=000 or 100 */
5566                         guchar *br1;
5567
5568                         /* skip branch if C1=1 */
5569                         br1 = code;
5570                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5571                         /* branch if C0=0 */
5572                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5573                         amd64_patch (br1, code);
5574                         break;
5575                 }
5576                 case OP_FBLE_UN:
5577                         /* Branch if C013 != 001 */
5578                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5579                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5580                         break;
5581                 case OP_CKFINITE:
5582                         /* Transfer value to the fp stack */
5583                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5584                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5585                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5586
5587                         amd64_push_reg (code, AMD64_RAX);
5588                         amd64_fxam (code);
5589                         amd64_fnstsw (code);
5590                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5591                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5592                         amd64_pop_reg (code, AMD64_RAX);
5593                         amd64_fstp (code, 0);
5594                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5595                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5596                         break;
5597                 case OP_TLS_GET: {
5598                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5599                         break;
5600                 }
5601                 case OP_TLS_GET_REG:
5602                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5603                         break;
5604                 case OP_TLS_SET: {
5605                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5606                         break;
5607                 }
5608                 case OP_TLS_SET_REG: {
5609                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5610                         break;
5611                 }
5612                 case OP_MEMORY_BARRIER: {
5613                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5614                                 x86_mfence (code);
5615                         break;
5616                 }
5617                 case OP_ATOMIC_ADD_I4:
5618                 case OP_ATOMIC_ADD_I8: {
5619                         int dreg = ins->dreg;
5620                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5621
5622                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5623                                 dreg = AMD64_R11;
5624
5625                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5626                         amd64_prefix (code, X86_LOCK_PREFIX);
5627                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5628                         /* dreg contains the old value, add with sreg2 value */
5629                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5630
5631                         if (ins->dreg != dreg)
5632                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5633
5634                         break;
5635                 }
5636                 case OP_ATOMIC_EXCHANGE_I4:
5637                 case OP_ATOMIC_EXCHANGE_I8: {
5638                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5639
5640                         /* LOCK prefix is implied. */
5641                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5642                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5643                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5644                         break;
5645                 }
5646                 case OP_ATOMIC_CAS_I4:
5647                 case OP_ATOMIC_CAS_I8: {
5648                         guint32 size;
5649
5650                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5651                                 size = 8;
5652                         else
5653                                 size = 4;
5654
5655                         /*
5656                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5657                          * an explanation of how this works.
5658                          */
5659                         g_assert (ins->sreg3 == AMD64_RAX);
5660                         g_assert (ins->sreg1 != AMD64_RAX);
5661                         g_assert (ins->sreg1 != ins->sreg2);
5662
5663                         amd64_prefix (code, X86_LOCK_PREFIX);
5664                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5665
5666                         if (ins->dreg != AMD64_RAX)
5667                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5668                         break;
5669                 }
5670                 case OP_ATOMIC_LOAD_I1: {
5671                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5672                         break;
5673                 }
5674                 case OP_ATOMIC_LOAD_U1: {
5675                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5676                         break;
5677                 }
5678                 case OP_ATOMIC_LOAD_I2: {
5679                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5680                         break;
5681                 }
5682                 case OP_ATOMIC_LOAD_U2: {
5683                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5684                         break;
5685                 }
5686                 case OP_ATOMIC_LOAD_I4: {
5687                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5688                         break;
5689                 }
5690                 case OP_ATOMIC_LOAD_U4:
5691                 case OP_ATOMIC_LOAD_I8:
5692                 case OP_ATOMIC_LOAD_U8: {
5693                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5694                         break;
5695                 }
5696                 case OP_ATOMIC_LOAD_R4: {
5697                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5698                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5699                         break;
5700                 }
5701                 case OP_ATOMIC_LOAD_R8: {
5702                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5703                         break;
5704                 }
5705                 case OP_ATOMIC_STORE_I1:
5706                 case OP_ATOMIC_STORE_U1:
5707                 case OP_ATOMIC_STORE_I2:
5708                 case OP_ATOMIC_STORE_U2:
5709                 case OP_ATOMIC_STORE_I4:
5710                 case OP_ATOMIC_STORE_U4:
5711                 case OP_ATOMIC_STORE_I8:
5712                 case OP_ATOMIC_STORE_U8: {
5713                         int size;
5714
5715                         switch (ins->opcode) {
5716                         case OP_ATOMIC_STORE_I1:
5717                         case OP_ATOMIC_STORE_U1:
5718                                 size = 1;
5719                                 break;
5720                         case OP_ATOMIC_STORE_I2:
5721                         case OP_ATOMIC_STORE_U2:
5722                                 size = 2;
5723                                 break;
5724                         case OP_ATOMIC_STORE_I4:
5725                         case OP_ATOMIC_STORE_U4:
5726                                 size = 4;
5727                                 break;
5728                         case OP_ATOMIC_STORE_I8:
5729                         case OP_ATOMIC_STORE_U8:
5730                                 size = 8;
5731                                 break;
5732                         }
5733
5734                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5735
5736                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5737                                 x86_mfence (code);
5738                         break;
5739                 }
5740                 case OP_ATOMIC_STORE_R4: {
5741                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5742                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5743
5744                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5745                                 x86_mfence (code);
5746                         break;
5747                 }
5748                 case OP_ATOMIC_STORE_R8: {
5749                         x86_nop (code);
5750                         x86_nop (code);
5751                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5752                         x86_nop (code);
5753                         x86_nop (code);
5754
5755                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5756                                 x86_mfence (code);
5757                         break;
5758                 }
5759                 case OP_CARD_TABLE_WBARRIER: {
5760                         int ptr = ins->sreg1;
5761                         int value = ins->sreg2;
5762                         guchar *br = 0;
5763                         int nursery_shift, card_table_shift;
5764                         gpointer card_table_mask;
5765                         size_t nursery_size;
5766
5767                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5768                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5769                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5770
5771                         /*If either point to the stack we can simply avoid the WB. This happens due to
5772                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5773                          */
5774                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5775                                 continue;
5776
5777                         /*
5778                          * We need one register we can clobber, we choose EDX and make sreg1
5779                          * fixed EAX to work around limitations in the local register allocator.
5780                          * sreg2 might get allocated to EDX, but that is not a problem since
5781                          * we use it before clobbering EDX.
5782                          */
5783                         g_assert (ins->sreg1 == AMD64_RAX);
5784
5785                         /*
5786                          * This is the code we produce:
5787                          *
5788                          *   edx = value
5789                          *   edx >>= nursery_shift
5790                          *   cmp edx, (nursery_start >> nursery_shift)
5791                          *   jne done
5792                          *   edx = ptr
5793                          *   edx >>= card_table_shift
5794                          *   edx += cardtable
5795                          *   [edx] = 1
5796                          * done:
5797                          */
5798
5799                         if (mono_gc_card_table_nursery_check ()) {
5800                                 if (value != AMD64_RDX)
5801                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5802                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5803                                 if (shifted_nursery_start >> 31) {
5804                                         /*
5805                                          * The value we need to compare against is 64 bits, so we need
5806                                          * another spare register.  We use RBX, which we save and
5807                                          * restore.
5808                                          */
5809                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5810                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5811                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5812                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5813                                 } else {
5814                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5815                                 }
5816                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5817                         }
5818                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5819                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5820                         if (card_table_mask)
5821                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5822
5823                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5824                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5825
5826                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5827
5828                         if (mono_gc_card_table_nursery_check ())
5829                                 x86_patch (br, code);
5830                         break;
5831                 }
5832 #ifdef MONO_ARCH_SIMD_INTRINSICS
5833                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5834                 case OP_ADDPS:
5835                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5836                         break;
5837                 case OP_DIVPS:
5838                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5839                         break;
5840                 case OP_MULPS:
5841                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5842                         break;
5843                 case OP_SUBPS:
5844                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5845                         break;
5846                 case OP_MAXPS:
5847                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5848                         break;
5849                 case OP_MINPS:
5850                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5851                         break;
5852                 case OP_COMPPS:
5853                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5854                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5855                         break;
5856                 case OP_ANDPS:
5857                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5858                         break;
5859                 case OP_ANDNPS:
5860                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5861                         break;
5862                 case OP_ORPS:
5863                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_XORPS:
5866                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_SQRTPS:
5869                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5870                         break;
5871                 case OP_RSQRTPS:
5872                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5873                         break;
5874                 case OP_RCPPS:
5875                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5876                         break;
5877                 case OP_ADDSUBPS:
5878                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_HADDPS:
5881                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883                 case OP_HSUBPS:
5884                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5885                         break;
5886                 case OP_DUPPS_HIGH:
5887                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5888                         break;
5889                 case OP_DUPPS_LOW:
5890                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5891                         break;
5892
5893                 case OP_PSHUFLEW_HIGH:
5894                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5895                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5896                         break;
5897                 case OP_PSHUFLEW_LOW:
5898                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5899                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5900                         break;
5901                 case OP_PSHUFLED:
5902                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5903                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5904                         break;
5905                 case OP_SHUFPS:
5906                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5907                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5908                         break;
5909                 case OP_SHUFPD:
5910                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5911                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5912                         break;
5913
5914                 case OP_ADDPD:
5915                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_DIVPD:
5918                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_MULPD:
5921                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_SUBPD:
5924                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_MAXPD:
5927                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_MINPD:
5930                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_COMPPD:
5933                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5934                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5935                         break;
5936                 case OP_ANDPD:
5937                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_ANDNPD:
5940                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_ORPD:
5943                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_XORPD:
5946                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_SQRTPD:
5949                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5950                         break;
5951                 case OP_ADDSUBPD:
5952                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_HADDPD:
5955                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957                 case OP_HSUBPD:
5958                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_DUPPD:
5961                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5962                         break;
5963
5964                 case OP_EXTRACT_MASK:
5965                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5966                         break;
5967
5968                 case OP_PAND:
5969                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971                 case OP_POR:
5972                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_PXOR:
5975                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977
5978                 case OP_PADDB:
5979                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_PADDW:
5982                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_PADDD:
5985                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_PADDQ:
5988                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990
5991                 case OP_PSUBB:
5992                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_PSUBW:
5995                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_PSUBD:
5998                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_PSUBQ:
6001                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003
6004                 case OP_PMAXB_UN:
6005                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_PMAXW_UN:
6008                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010                 case OP_PMAXD_UN:
6011                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013
6014                 case OP_PMAXB:
6015                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_PMAXW:
6018                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_PMAXD:
6021                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023
6024                 case OP_PAVGB_UN:
6025                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PAVGW_UN:
6028                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030
6031                 case OP_PMINB_UN:
6032                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_PMINW_UN:
6035                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PMIND_UN:
6038                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040
6041                 case OP_PMINB:
6042                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_PMINW:
6045                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PMIND:
6048                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050
6051                 case OP_PCMPEQB:
6052                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_PCMPEQW:
6055                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PCMPEQD:
6058                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_PCMPEQQ:
6061                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063
6064                 case OP_PCMPGTB:
6065                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PCMPGTW:
6068                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PCMPGTD:
6071                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PCMPGTQ:
6074                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PSUM_ABS_DIFF:
6078                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080
6081                 case OP_UNPACK_LOWB:
6082                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084                 case OP_UNPACK_LOWW:
6085                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_UNPACK_LOWD:
6088                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_UNPACK_LOWQ:
6091                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_UNPACK_LOWPS:
6094                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_UNPACK_LOWPD:
6097                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099
6100                 case OP_UNPACK_HIGHB:
6101                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_UNPACK_HIGHW:
6104                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_UNPACK_HIGHD:
6107                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_UNPACK_HIGHQ:
6110                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_UNPACK_HIGHPS:
6113                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_UNPACK_HIGHPD:
6116                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118
6119                 case OP_PACKW:
6120                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_PACKD:
6123                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_PACKW_UN:
6126                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PACKD_UN:
6129                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131
6132                 case OP_PADDB_SAT_UN:
6133                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_PSUBB_SAT_UN:
6136                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_PADDW_SAT_UN:
6139                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_PSUBW_SAT_UN:
6142                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144
6145                 case OP_PADDB_SAT:
6146                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_PSUBB_SAT:
6149                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_PADDW_SAT:
6152                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_PSUBW_SAT:
6155                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157
6158                 case OP_PMULW:
6159                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_PMULD:
6162                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_PMULQ:
6165                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_PMULW_HIGH_UN:
6168                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_PMULW_HIGH:
6171                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173
6174                 case OP_PSHRW:
6175                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6176                         break;
6177                 case OP_PSHRW_REG:
6178                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6179                         break;
6180
6181                 case OP_PSARW:
6182                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6183                         break;
6184                 case OP_PSARW_REG:
6185                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6186                         break;
6187
6188                 case OP_PSHLW:
6189                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6190                         break;
6191                 case OP_PSHLW_REG:
6192                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6193                         break;
6194
6195                 case OP_PSHRD:
6196                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6197                         break;
6198                 case OP_PSHRD_REG:
6199                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6200                         break;
6201
6202                 case OP_PSARD:
6203                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6204                         break;
6205                 case OP_PSARD_REG:
6206                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6207                         break;
6208
6209                 case OP_PSHLD:
6210                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6211                         break;
6212                 case OP_PSHLD_REG:
6213                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6214                         break;
6215
6216                 case OP_PSHRQ:
6217                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6218                         break;
6219                 case OP_PSHRQ_REG:
6220                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6221                         break;
6222
6223                 /*TODO: This is appart of the sse spec but not added
6224                 case OP_PSARQ:
6225                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6226                         break;
6227                 case OP_PSARQ_REG:
6228                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6229                         break;
6230                 */
6231
6232                 case OP_PSHLQ:
6233                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6234                         break;
6235                 case OP_PSHLQ_REG:
6236                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6237                         break;
6238                 case OP_CVTDQ2PD:
6239                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6240                         break;
6241                 case OP_CVTDQ2PS:
6242                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6243                         break;
6244                 case OP_CVTPD2DQ:
6245                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6246                         break;
6247                 case OP_CVTPD2PS:
6248                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6249                         break;
6250                 case OP_CVTPS2DQ:
6251                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6252                         break;
6253                 case OP_CVTPS2PD:
6254                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6255                         break;
6256                 case OP_CVTTPD2DQ:
6257                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6258                         break;
6259                 case OP_CVTTPS2DQ:
6260                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6261                         break;
6262
6263                 case OP_ICONV_TO_X:
6264                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6265                         break;
6266                 case OP_EXTRACT_I4:
6267                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6268                         break;
6269                 case OP_EXTRACT_I8:
6270                         if (ins->inst_c0) {
6271                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6272                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6273                         } else {
6274                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6275                         }
6276                         break;
6277                 case OP_EXTRACT_I1:
6278                 case OP_EXTRACT_U1:
6279                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6280                         if (ins->inst_c0)
6281                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6282                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6283                         break;
6284                 case OP_EXTRACT_I2:
6285                 case OP_EXTRACT_U2:
6286                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6287                         if (ins->inst_c0)
6288                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6289                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6290                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6291                         break;
6292                 case OP_EXTRACT_R8:
6293                         if (ins->inst_c0)
6294                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6295                         else
6296                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6297                         break;
6298                 case OP_INSERT_I2:
6299                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6300                         break;
6301                 case OP_EXTRACTX_U2:
6302                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6303                         break;
6304                 case OP_INSERTX_U1_SLOW:
6305                         /*sreg1 is the extracted ireg (scratch)
6306                         /sreg2 is the to be inserted ireg (scratch)
6307                         /dreg is the xreg to receive the value*/
6308
6309                         /*clear the bits from the extracted word*/
6310                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6311                         /*shift the value to insert if needed*/
6312                         if (ins->inst_c0 & 1)
6313                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6314                         /*join them together*/
6315                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6316                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6317                         break;
6318                 case OP_INSERTX_I4_SLOW:
6319                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6320                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6321                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6322                         break;
6323                 case OP_INSERTX_I8_SLOW:
6324                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6325                         if (ins->inst_c0)
6326                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6327                         else
6328                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6329                         break;
6330
6331                 case OP_INSERTX_R4_SLOW:
6332                         switch (ins->inst_c0) {
6333                         case 0:
6334                                 if (cfg->r4fp)
6335                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6336                                 else
6337                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6338                                 break;
6339                         case 1:
6340                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6341                                 if (cfg->r4fp)
6342                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6343                                 else
6344                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6345                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6346                                 break;
6347                         case 2:
6348                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6349                                 if (cfg->r4fp)
6350                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6351                                 else
6352                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6353                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6354                                 break;
6355                         case 3:
6356                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6357                                 if (cfg->r4fp)
6358                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6359                                 else
6360                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6361                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6362                                 break;
6363                         }
6364                         break;
6365                 case OP_INSERTX_R8_SLOW:
6366                         if (ins->inst_c0)
6367                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6368                         else
6369                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6370                         break;
6371                 case OP_STOREX_MEMBASE_REG:
6372                 case OP_STOREX_MEMBASE:
6373                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6374                         break;
6375                 case OP_LOADX_MEMBASE:
6376                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6377                         break;
6378                 case OP_LOADX_ALIGNED_MEMBASE:
6379                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6380                         break;
6381                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6382                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6383                         break;
6384                 case OP_STOREX_NTA_MEMBASE_REG:
6385                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6386                         break;
6387                 case OP_PREFETCH_MEMBASE:
6388                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6389                         break;
6390
6391                 case OP_XMOVE:
6392                         /*FIXME the peephole pass should have killed this*/
6393                         if (ins->dreg != ins->sreg1)
6394                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6395                         break;
6396                 case OP_XZERO:
6397                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6398                         break;
6399                 case OP_ICONV_TO_R4_RAW:
6400                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6401                         break;
6402
6403                 case OP_FCONV_TO_R8_X:
6404                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6405                         break;
6406
6407                 case OP_XCONV_R8_TO_I4:
6408                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6409                         switch (ins->backend.source_opcode) {
6410                         case OP_FCONV_TO_I1:
6411                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6412                                 break;
6413                         case OP_FCONV_TO_U1:
6414                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6415                                 break;
6416                         case OP_FCONV_TO_I2:
6417                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6418                                 break;
6419                         case OP_FCONV_TO_U2:
6420                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6421                                 break;
6422                         }
6423                         break;
6424
6425                 case OP_EXPAND_I2:
6426                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6427                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6428                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6429                         break;
6430                 case OP_EXPAND_I4:
6431                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6432                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6433                         break;
6434                 case OP_EXPAND_I8:
6435                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6436                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6437                         break;
6438                 case OP_EXPAND_R4:
6439                         if (cfg->r4fp) {
6440                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6441                         } else {
6442                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6443                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6444                         }
6445                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6446                         break;
6447                 case OP_EXPAND_R8:
6448                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6449                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6450                         break;
6451 #endif
6452                 case OP_LIVERANGE_START: {
6453                         if (cfg->verbose_level > 1)
6454                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6455                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6456                         break;
6457                 }
6458                 case OP_LIVERANGE_END: {
6459                         if (cfg->verbose_level > 1)
6460                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6461                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6462                         break;
6463                 }
6464                 case OP_GC_SAFE_POINT: {
6465                         guint8 *br [1];
6466
6467                         g_assert (mono_threads_is_coop_enabled ());
6468
6469                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6470                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6471                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6472                         amd64_patch (br[0], code);
6473                         break;
6474                 }
6475
6476                 case OP_GC_LIVENESS_DEF:
6477                 case OP_GC_LIVENESS_USE:
6478                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6479                         ins->backend.pc_offset = code - cfg->native_code;
6480                         break;
6481                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6482                         ins->backend.pc_offset = code - cfg->native_code;
6483                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6484                         break;
6485                 default:
6486                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6487                         g_assert_not_reached ();
6488                 }
6489
6490                 if ((code - cfg->native_code - offset) > max_len) {
6491                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6492                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6493                         g_assert_not_reached ();
6494                 }
6495         }
6496
6497         cfg->code_len = code - cfg->native_code;
6498 }
6499
6500 #endif /* DISABLE_JIT */
6501
6502 void
6503 mono_arch_register_lowlevel_calls (void)
6504 {
6505         /* The signature doesn't matter */
6506         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6507 }
6508
6509 void
6510 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6511 {
6512         unsigned char *ip = ji->ip.i + code;
6513
6514         /*
6515          * Debug code to help track down problems where the target of a near call is
6516          * is not valid.
6517          */
6518         if (amd64_is_near_call (ip)) {
6519                 gint64 disp = (guint8*)target - (guint8*)ip;
6520
6521                 if (!amd64_is_imm32 (disp)) {
6522                         printf ("TYPE: %d\n", ji->type);
6523                         switch (ji->type) {
6524                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6525                                 printf ("V: %s\n", ji->data.name);
6526                                 break;
6527                         case MONO_PATCH_INFO_METHOD_JUMP:
6528                         case MONO_PATCH_INFO_METHOD:
6529                                 printf ("V: %s\n", ji->data.method->name);
6530                                 break;
6531                         default:
6532                                 break;
6533                         }
6534                 }
6535         }
6536
6537         amd64_patch (ip, (gpointer)target);
6538 }
6539
6540 #ifndef DISABLE_JIT
6541
6542 static int
6543 get_max_epilog_size (MonoCompile *cfg)
6544 {
6545         int max_epilog_size = 16;
6546
6547         if (cfg->method->save_lmf)
6548                 max_epilog_size += 256;
6549
6550         if (mono_jit_trace_calls != NULL)
6551                 max_epilog_size += 50;
6552
6553         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6554                 max_epilog_size += 50;
6555
6556         max_epilog_size += (AMD64_NREG * 2);
6557
6558         return max_epilog_size;
6559 }
6560
6561 /*
6562  * This macro is used for testing whenever the unwinder works correctly at every point
6563  * where an async exception can happen.
6564  */
6565 /* This will generate a SIGSEGV at the given point in the code */
6566 #define async_exc_point(code) do { \
6567     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6568          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6569              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6570          cfg->arch.async_point_count ++; \
6571     } \
6572 } while (0)
6573
6574 guint8 *
6575 mono_arch_emit_prolog (MonoCompile *cfg)
6576 {
6577         MonoMethod *method = cfg->method;
6578         MonoBasicBlock *bb;
6579         MonoMethodSignature *sig;
6580         MonoInst *ins;
6581         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6582         guint8 *code;
6583         CallInfo *cinfo;
6584         MonoInst *lmf_var = cfg->lmf_var;
6585         gboolean args_clobbered = FALSE;
6586         gboolean trace = FALSE;
6587
6588         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6589
6590         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6591
6592         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6593                 trace = TRUE;
6594
6595         /* Amount of stack space allocated by register saving code */
6596         pos = 0;
6597
6598         /* Offset between RSP and the CFA */
6599         cfa_offset = 0;
6600
6601         /*
6602          * The prolog consists of the following parts:
6603          * FP present:
6604          * - push rbp, mov rbp, rsp
6605          * - save callee saved regs using pushes
6606          * - allocate frame
6607          * - save rgctx if needed
6608          * - save lmf if needed
6609          * FP not present:
6610          * - allocate frame
6611          * - save rgctx if needed
6612          * - save lmf if needed
6613          * - save callee saved regs using moves
6614          */
6615
6616         // CFA = sp + 8
6617         cfa_offset = 8;
6618         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6619         // IP saved at CFA - 8
6620         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6621         async_exc_point (code);
6622         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6623
6624         if (!cfg->arch.omit_fp) {
6625                 amd64_push_reg (code, AMD64_RBP);
6626                 cfa_offset += 8;
6627                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6628                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6629                 async_exc_point (code);
6630 #ifdef TARGET_WIN32
6631                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6632 #endif
6633                 /* These are handled automatically by the stack marking code */
6634                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6635
6636                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6637                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6638                 async_exc_point (code);
6639 #ifdef TARGET_WIN32
6640                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6641 #endif
6642         }
6643
6644         /* The param area is always at offset 0 from sp */
6645         /* This needs to be allocated here, since it has to come after the spill area */
6646         if (cfg->param_area) {
6647                 if (cfg->arch.omit_fp)
6648                         // FIXME:
6649                         g_assert_not_reached ();
6650                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6651         }
6652
6653         if (cfg->arch.omit_fp) {
6654                 /*
6655                  * On enter, the stack is misaligned by the pushing of the return
6656                  * address. It is either made aligned by the pushing of %rbp, or by
6657                  * this.
6658                  */
6659                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6660                 if ((alloc_size % 16) == 0) {
6661                         alloc_size += 8;
6662                         /* Mark the padding slot as NOREF */
6663                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6664                 }
6665         } else {
6666                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6667                 if (cfg->stack_offset != alloc_size) {
6668                         /* Mark the padding slot as NOREF */
6669                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6670                 }
6671                 cfg->arch.sp_fp_offset = alloc_size;
6672                 alloc_size -= pos;
6673         }
6674
6675         cfg->arch.stack_alloc_size = alloc_size;
6676
6677         /* Allocate stack frame */
6678         if (alloc_size) {
6679                 /* See mono_emit_stack_alloc */
6680 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6681                 guint32 remaining_size = alloc_size;
6682                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6683                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6684                 guint32 offset = code - cfg->native_code;
6685                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6686                         while (required_code_size >= (cfg->code_size - offset))
6687                                 cfg->code_size *= 2;
6688                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6689                         code = cfg->native_code + offset;
6690                         cfg->stat_code_reallocs++;
6691                 }
6692
6693                 while (remaining_size >= 0x1000) {
6694                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6695                         if (cfg->arch.omit_fp) {
6696                                 cfa_offset += 0x1000;
6697                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6698                         }
6699                         async_exc_point (code);
6700 #ifdef TARGET_WIN32
6701                         if (cfg->arch.omit_fp)
6702                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6703 #endif
6704
6705                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6706                         remaining_size -= 0x1000;
6707                 }
6708                 if (remaining_size) {
6709                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6710                         if (cfg->arch.omit_fp) {
6711                                 cfa_offset += remaining_size;
6712                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6713                                 async_exc_point (code);
6714                         }
6715 #ifdef TARGET_WIN32
6716                         if (cfg->arch.omit_fp)
6717                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6718 #endif
6719                 }
6720 #else
6721                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6722                 if (cfg->arch.omit_fp) {
6723                         cfa_offset += alloc_size;
6724                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6725                         async_exc_point (code);
6726                 }
6727 #endif
6728         }
6729
6730         /* Stack alignment check */
6731 #if 0
6732         {
6733                 guint8 *buf;
6734
6735                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6736                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6737                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6738                 buf = code;
6739                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6740                 amd64_breakpoint (code);
6741                 amd64_patch (buf, code);
6742         }
6743 #endif
6744
6745         if (mini_get_debug_options ()->init_stacks) {
6746                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6747
6748                 /* Save registers to the red zone */
6749                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6750                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6751
6752                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6753                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6754                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6755
6756                 amd64_cld (code);
6757                 amd64_prefix (code, X86_REP_PREFIX);
6758                 amd64_stosl (code);
6759
6760                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6761                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6762         }
6763
6764         /* Save LMF */
6765         if (method->save_lmf)
6766                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6767
6768         /* Save callee saved registers */
6769         if (cfg->arch.omit_fp) {
6770                 save_area_offset = cfg->arch.reg_save_area_offset;
6771                 /* Save caller saved registers after sp is adjusted */
6772                 /* The registers are saved at the bottom of the frame */
6773                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6774         } else {
6775                 /* The registers are saved just below the saved rbp */
6776                 save_area_offset = cfg->arch.reg_save_area_offset;
6777         }
6778
6779         for (i = 0; i < AMD64_NREG; ++i) {
6780                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6781                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6782
6783                         if (cfg->arch.omit_fp) {
6784                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6785                                 /* These are handled automatically by the stack marking code */
6786                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6787                         } else {
6788                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6789                                 // FIXME: GC
6790                         }
6791
6792                         save_area_offset += 8;
6793                         async_exc_point (code);
6794                 }
6795         }
6796
6797         /* store runtime generic context */
6798         if (cfg->rgctx_var) {
6799                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6800                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6801
6802                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6803
6804                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6805                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6806         }
6807
6808         /* compute max_length in order to use short forward jumps */
6809         max_epilog_size = get_max_epilog_size (cfg);
6810         if (cfg->opt & MONO_OPT_BRANCH) {
6811                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6812                         MonoInst *ins;
6813                         int max_length = 0;
6814
6815                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6816                                 max_length += 6;
6817                         /* max alignment for loops */
6818                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6819                                 max_length += LOOP_ALIGNMENT;
6820
6821                         MONO_BB_FOR_EACH_INS (bb, ins) {
6822                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6823                         }
6824
6825                         /* Take prolog and epilog instrumentation into account */
6826                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6827                                 max_length += max_epilog_size;
6828
6829                         bb->max_length = max_length;
6830                 }
6831         }
6832
6833         sig = mono_method_signature (method);
6834         pos = 0;
6835
6836         cinfo = (CallInfo *)cfg->arch.cinfo;
6837
6838         if (sig->ret->type != MONO_TYPE_VOID) {
6839                 /* Save volatile arguments to the stack */
6840                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6841                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6842         }
6843
6844         /* Keep this in sync with emit_load_volatile_arguments */
6845         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6846                 ArgInfo *ainfo = cinfo->args + i;
6847
6848                 ins = cfg->args [i];
6849
6850                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6851                         /* Unused arguments */
6852                         continue;
6853
6854                 /* Save volatile arguments to the stack */
6855                 if (ins->opcode != OP_REGVAR) {
6856                         switch (ainfo->storage) {
6857                         case ArgInIReg: {
6858                                 guint32 size = 8;
6859
6860                                 /* FIXME: I1 etc */
6861                                 /*
6862                                 if (stack_offset & 0x1)
6863                                         size = 1;
6864                                 else if (stack_offset & 0x2)
6865                                         size = 2;
6866                                 else if (stack_offset & 0x4)
6867                                         size = 4;
6868                                 else
6869                                         size = 8;
6870                                 */
6871                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6872
6873                                 /*
6874                                  * Save the original location of 'this',
6875                                  * get_generic_info_from_stack_frame () needs this to properly look up
6876                                  * the argument value during the handling of async exceptions.
6877                                  */
6878                                 if (ins == cfg->args [0]) {
6879                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6880                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6881                                 }
6882                                 break;
6883                         }
6884                         case ArgInFloatSSEReg:
6885                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6886                                 break;
6887                         case ArgInDoubleSSEReg:
6888                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6889                                 break;
6890                         case ArgValuetypeInReg:
6891                                 for (quad = 0; quad < 2; quad ++) {
6892                                         switch (ainfo->pair_storage [quad]) {
6893                                         case ArgInIReg:
6894                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6895                                                 break;
6896                                         case ArgInFloatSSEReg:
6897                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6898                                                 break;
6899                                         case ArgInDoubleSSEReg:
6900                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6901                                                 break;
6902                                         case ArgNone:
6903                                                 break;
6904                                         default:
6905                                                 g_assert_not_reached ();
6906                                         }
6907                                 }
6908                                 break;
6909                         case ArgValuetypeAddrInIReg:
6910                                 if (ainfo->pair_storage [0] == ArgInIReg)
6911                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6912                                 break;
6913                         case ArgGSharedVtInReg:
6914                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6915                                 break;
6916                         default:
6917                                 break;
6918                         }
6919                 } else {
6920                         /* Argument allocated to (non-volatile) register */
6921                         switch (ainfo->storage) {
6922                         case ArgInIReg:
6923                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6924                                 break;
6925                         case ArgOnStack:
6926                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6927                                 break;
6928                         default:
6929                                 g_assert_not_reached ();
6930                         }
6931
6932                         if (ins == cfg->args [0]) {
6933                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6934                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6935                         }
6936                 }
6937         }
6938
6939         if (cfg->method->save_lmf)
6940                 args_clobbered = TRUE;
6941
6942         if (trace) {
6943                 args_clobbered = TRUE;
6944                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6945         }
6946
6947         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6948                 args_clobbered = TRUE;
6949
6950         /*
6951          * Optimize the common case of the first bblock making a call with the same
6952          * arguments as the method. This works because the arguments are still in their
6953          * original argument registers.
6954          * FIXME: Generalize this
6955          */
6956         if (!args_clobbered) {
6957                 MonoBasicBlock *first_bb = cfg->bb_entry;
6958                 MonoInst *next;
6959                 int filter = FILTER_IL_SEQ_POINT;
6960
6961                 next = mono_bb_first_inst (first_bb, filter);
6962                 if (!next && first_bb->next_bb) {
6963                         first_bb = first_bb->next_bb;
6964                         next = mono_bb_first_inst (first_bb, filter);
6965                 }
6966
6967                 if (first_bb->in_count > 1)
6968                         next = NULL;
6969
6970                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6971                         ArgInfo *ainfo = cinfo->args + i;
6972                         gboolean match = FALSE;
6973
6974                         ins = cfg->args [i];
6975                         if (ins->opcode != OP_REGVAR) {
6976                                 switch (ainfo->storage) {
6977                                 case ArgInIReg: {
6978                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6979                                                 if (next->dreg == ainfo->reg) {
6980                                                         NULLIFY_INS (next);
6981                                                         match = TRUE;
6982                                                 } else {
6983                                                         next->opcode = OP_MOVE;
6984                                                         next->sreg1 = ainfo->reg;
6985                                                         /* Only continue if the instruction doesn't change argument regs */
6986                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6987                                                                 match = TRUE;
6988                                                 }
6989                                         }
6990                                         break;
6991                                 }
6992                                 default:
6993                                         break;
6994                                 }
6995                         } else {
6996                                 /* Argument allocated to (non-volatile) register */
6997                                 switch (ainfo->storage) {
6998                                 case ArgInIReg:
6999                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7000                                                 NULLIFY_INS (next);
7001                                                 match = TRUE;
7002                                         }
7003                                         break;
7004                                 default:
7005                                         break;
7006                                 }
7007                         }
7008
7009                         if (match) {
7010                                 next = mono_inst_next (next, filter);
7011                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7012                                 if (!next)
7013                                         break;
7014                         }
7015                 }
7016         }
7017
7018         if (cfg->gen_sdb_seq_points) {
7019                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7020
7021                 /* Initialize seq_point_info_var */
7022                 if (cfg->compile_aot) {
7023                         /* Initialize the variable from a GOT slot */
7024                         /* Same as OP_AOTCONST */
7025                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7026                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7027                         g_assert (info_var->opcode == OP_REGOFFSET);
7028                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7029                 }
7030
7031                 if (cfg->compile_aot) {
7032                         /* Initialize ss_tramp_var */
7033                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7034                         g_assert (ins->opcode == OP_REGOFFSET);
7035
7036                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7037                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7038                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7039                 } else {
7040                         /* Initialize ss_tramp_var */
7041                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7042                         g_assert (ins->opcode == OP_REGOFFSET);
7043
7044                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7045                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7046
7047                         /* Initialize bp_tramp_var */
7048                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7049                         g_assert (ins->opcode == OP_REGOFFSET);
7050
7051                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7052                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7053                 }
7054         }
7055
7056         cfg->code_len = code - cfg->native_code;
7057
7058         g_assert (cfg->code_len < cfg->code_size);
7059
7060         return code;
7061 }
7062
7063 void
7064 mono_arch_emit_epilog (MonoCompile *cfg)
7065 {
7066         MonoMethod *method = cfg->method;
7067         int quad, i;
7068         guint8 *code;
7069         int max_epilog_size;
7070         CallInfo *cinfo;
7071         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7072         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7073
7074         max_epilog_size = get_max_epilog_size (cfg);
7075
7076         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7077                 cfg->code_size *= 2;
7078                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7079                 cfg->stat_code_reallocs++;
7080         }
7081         code = cfg->native_code + cfg->code_len;
7082
7083         cfg->has_unwind_info_for_epilog = TRUE;
7084
7085         /* Mark the start of the epilog */
7086         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7087
7088         /* Save the uwind state which is needed by the out-of-line code */
7089         mono_emit_unwind_op_remember_state (cfg, code);
7090
7091         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7092                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7093
7094         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7095
7096         if (method->save_lmf) {
7097                 /* check if we need to restore protection of the stack after a stack overflow */
7098                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7099                         guint8 *patch;
7100                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7101                         /* we load the value in a separate instruction: this mechanism may be
7102                          * used later as a safer way to do thread interruption
7103                          */
7104                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7105                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7106                         patch = code;
7107                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7108                         /* note that the call trampoline will preserve eax/edx */
7109                         x86_call_reg (code, X86_ECX);
7110                         x86_patch (patch, code);
7111                 } else {
7112                         /* FIXME: maybe save the jit tls in the prolog */
7113                 }
7114                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7115                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7116                 }
7117         }
7118
7119         /* Restore callee saved regs */
7120         for (i = 0; i < AMD64_NREG; ++i) {
7121                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7122                         /* Restore only used_int_regs, not arch.saved_iregs */
7123                         if (cfg->used_int_regs & (1 << i)) {
7124                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7125                                 mono_emit_unwind_op_same_value (cfg, code, i);
7126                                 async_exc_point (code);
7127                         }
7128                         save_area_offset += 8;
7129                 }
7130         }
7131
7132         /* Load returned vtypes into registers if needed */
7133         cinfo = (CallInfo *)cfg->arch.cinfo;
7134         if (cinfo->ret.storage == ArgValuetypeInReg) {
7135                 ArgInfo *ainfo = &cinfo->ret;
7136                 MonoInst *inst = cfg->ret;
7137
7138                 for (quad = 0; quad < 2; quad ++) {
7139                         switch (ainfo->pair_storage [quad]) {
7140                         case ArgInIReg:
7141                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7142                                 break;
7143                         case ArgInFloatSSEReg:
7144                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7145                                 break;
7146                         case ArgInDoubleSSEReg:
7147                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7148                                 break;
7149                         case ArgNone:
7150                                 break;
7151                         default:
7152                                 g_assert_not_reached ();
7153                         }
7154                 }
7155         }
7156
7157         if (cfg->arch.omit_fp) {
7158                 if (cfg->arch.stack_alloc_size) {
7159                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7160                 }
7161         } else {
7162                 amd64_leave (code);
7163                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7164         }
7165         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7166         async_exc_point (code);
7167         amd64_ret (code);
7168
7169         /* Restore the unwind state to be the same as before the epilog */
7170         mono_emit_unwind_op_restore_state (cfg, code);
7171
7172         cfg->code_len = code - cfg->native_code;
7173
7174         g_assert (cfg->code_len < cfg->code_size);
7175 }
7176
7177 void
7178 mono_arch_emit_exceptions (MonoCompile *cfg)
7179 {
7180         MonoJumpInfo *patch_info;
7181         int nthrows, i;
7182         guint8 *code;
7183         MonoClass *exc_classes [16];
7184         guint8 *exc_throw_start [16], *exc_throw_end [16];
7185         guint32 code_size = 0;
7186
7187         /* Compute needed space */
7188         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7189                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7190                         code_size += 40;
7191                 if (patch_info->type == MONO_PATCH_INFO_R8)
7192                         code_size += 8 + 15; /* sizeof (double) + alignment */
7193                 if (patch_info->type == MONO_PATCH_INFO_R4)
7194                         code_size += 4 + 15; /* sizeof (float) + alignment */
7195                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7196                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7197         }
7198
7199         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7200                 cfg->code_size *= 2;
7201                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7202                 cfg->stat_code_reallocs++;
7203         }
7204
7205         code = cfg->native_code + cfg->code_len;
7206
7207         /* add code to raise exceptions */
7208         nthrows = 0;
7209         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7210                 switch (patch_info->type) {
7211                 case MONO_PATCH_INFO_EXC: {
7212                         MonoClass *exc_class;
7213                         guint8 *buf, *buf2;
7214                         guint32 throw_ip;
7215
7216                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7217
7218                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7219                         throw_ip = patch_info->ip.i;
7220
7221                         //x86_breakpoint (code);
7222                         /* Find a throw sequence for the same exception class */
7223                         for (i = 0; i < nthrows; ++i)
7224                                 if (exc_classes [i] == exc_class)
7225                                         break;
7226                         if (i < nthrows) {
7227                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7228                                 x86_jump_code (code, exc_throw_start [i]);
7229                                 patch_info->type = MONO_PATCH_INFO_NONE;
7230                         }
7231                         else {
7232                                 buf = code;
7233                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7234                                 buf2 = code;
7235
7236                                 if (nthrows < 16) {
7237                                         exc_classes [nthrows] = exc_class;
7238                                         exc_throw_start [nthrows] = code;
7239                                 }
7240                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7241
7242                                 patch_info->type = MONO_PATCH_INFO_NONE;
7243
7244                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7245
7246                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7247                                 while (buf < buf2)
7248                                         x86_nop (buf);
7249
7250                                 if (nthrows < 16) {
7251                                         exc_throw_end [nthrows] = code;
7252                                         nthrows ++;
7253                                 }
7254                         }
7255                         break;
7256                 }
7257                 default:
7258                         /* do nothing */
7259                         break;
7260                 }
7261                 g_assert(code < cfg->native_code + cfg->code_size);
7262         }
7263
7264         /* Handle relocations with RIP relative addressing */
7265         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7266                 gboolean remove = FALSE;
7267                 guint8 *orig_code = code;
7268
7269                 switch (patch_info->type) {
7270                 case MONO_PATCH_INFO_R8:
7271                 case MONO_PATCH_INFO_R4: {
7272                         guint8 *pos, *patch_pos;
7273                         guint32 target_pos;
7274
7275                         /* The SSE opcodes require a 16 byte alignment */
7276                         code = (guint8*)ALIGN_TO (code, 16);
7277
7278                         pos = cfg->native_code + patch_info->ip.i;
7279                         if (IS_REX (pos [1])) {
7280                                 patch_pos = pos + 5;
7281                                 target_pos = code - pos - 9;
7282                         }
7283                         else {
7284                                 patch_pos = pos + 4;
7285                                 target_pos = code - pos - 8;
7286                         }
7287
7288                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7289                                 *(double*)code = *(double*)patch_info->data.target;
7290                                 code += sizeof (double);
7291                         } else {
7292                                 *(float*)code = *(float*)patch_info->data.target;
7293                                 code += sizeof (float);
7294                         }
7295
7296                         *(guint32*)(patch_pos) = target_pos;
7297
7298                         remove = TRUE;
7299                         break;
7300                 }
7301                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7302                         guint8 *pos;
7303
7304                         if (cfg->compile_aot)
7305                                 continue;
7306
7307                         /*loading is faster against aligned addresses.*/
7308                         code = (guint8*)ALIGN_TO (code, 8);
7309                         memset (orig_code, 0, code - orig_code);
7310
7311                         pos = cfg->native_code + patch_info->ip.i;
7312
7313                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7314                         if (IS_REX (pos [1]))
7315                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7316                         else
7317                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7318
7319                         *(gpointer*)code = (gpointer)patch_info->data.target;
7320                         code += sizeof (gpointer);
7321
7322                         remove = TRUE;
7323                         break;
7324                 }
7325                 default:
7326                         break;
7327                 }
7328
7329                 if (remove) {
7330                         if (patch_info == cfg->patch_info)
7331                                 cfg->patch_info = patch_info->next;
7332                         else {
7333                                 MonoJumpInfo *tmp;
7334
7335                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7336                                         ;
7337                                 tmp->next = patch_info->next;
7338                         }
7339                 }
7340                 g_assert (code < cfg->native_code + cfg->code_size);
7341         }
7342
7343         cfg->code_len = code - cfg->native_code;
7344
7345         g_assert (cfg->code_len < cfg->code_size);
7346
7347 }
7348
7349 #endif /* DISABLE_JIT */
7350
7351 void*
7352 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7353 {
7354         guchar *code = (guchar *)p;
7355         MonoMethodSignature *sig;
7356         MonoInst *inst;
7357         int i, n, stack_area = 0;
7358
7359         /* Keep this in sync with mono_arch_get_argument_info */
7360
7361         if (enable_arguments) {
7362                 /* Allocate a new area on the stack and save arguments there */
7363                 sig = mono_method_signature (cfg->method);
7364
7365                 n = sig->param_count + sig->hasthis;
7366
7367                 stack_area = ALIGN_TO (n * 8, 16);
7368
7369                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7370
7371                 for (i = 0; i < n; ++i) {
7372                         inst = cfg->args [i];
7373
7374                         if (inst->opcode == OP_REGVAR)
7375                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7376                         else {
7377                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7378                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7379                         }
7380                 }
7381         }
7382
7383         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7384         amd64_set_reg_template (code, AMD64_ARG_REG1);
7385         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7386         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7387
7388         if (enable_arguments)
7389                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7390
7391         return code;
7392 }
7393
7394 enum {
7395         SAVE_NONE,
7396         SAVE_STRUCT,
7397         SAVE_EAX,
7398         SAVE_EAX_EDX,
7399         SAVE_XMM
7400 };
7401
7402 void*
7403 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7404 {
7405         guchar *code = (guchar *)p;
7406         int save_mode = SAVE_NONE;
7407         MonoMethod *method = cfg->method;
7408         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7409         int i;
7410
7411         switch (ret_type->type) {
7412         case MONO_TYPE_VOID:
7413                 /* special case string .ctor icall */
7414                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7415                         save_mode = SAVE_EAX;
7416                 else
7417                         save_mode = SAVE_NONE;
7418                 break;
7419         case MONO_TYPE_I8:
7420         case MONO_TYPE_U8:
7421                 save_mode = SAVE_EAX;
7422                 break;
7423         case MONO_TYPE_R4:
7424         case MONO_TYPE_R8:
7425                 save_mode = SAVE_XMM;
7426                 break;
7427         case MONO_TYPE_GENERICINST:
7428                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7429                         save_mode = SAVE_EAX;
7430                         break;
7431                 }
7432                 /* Fall through */
7433         case MONO_TYPE_VALUETYPE:
7434                 save_mode = SAVE_STRUCT;
7435                 break;
7436         default:
7437                 save_mode = SAVE_EAX;
7438                 break;
7439         }
7440
7441         /* Save the result and copy it into the proper argument register */
7442         switch (save_mode) {
7443         case SAVE_EAX:
7444                 amd64_push_reg (code, AMD64_RAX);
7445                 /* Align stack */
7446                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7447                 if (enable_arguments)
7448                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7449                 break;
7450         case SAVE_STRUCT:
7451                 /* FIXME: */
7452                 if (enable_arguments)
7453                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7454                 break;
7455         case SAVE_XMM:
7456                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7457                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7458                 /* Align stack */
7459                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7460                 /*
7461                  * The result is already in the proper argument register so no copying
7462                  * needed.
7463                  */
7464                 break;
7465         case SAVE_NONE:
7466                 break;
7467         default:
7468                 g_assert_not_reached ();
7469         }
7470
7471         /* Set %al since this is a varargs call */
7472         if (save_mode == SAVE_XMM)
7473                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7474         else
7475                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7476
7477         if (preserve_argument_registers) {
7478                 for (i = 0; i < PARAM_REGS; ++i)
7479                         amd64_push_reg (code, param_regs [i]);
7480         }
7481
7482         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7483         amd64_set_reg_template (code, AMD64_ARG_REG1);
7484         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7485
7486         if (preserve_argument_registers) {
7487                 for (i = PARAM_REGS - 1; i >= 0; --i)
7488                         amd64_pop_reg (code, param_regs [i]);
7489         }
7490
7491         /* Restore result */
7492         switch (save_mode) {
7493         case SAVE_EAX:
7494                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7495                 amd64_pop_reg (code, AMD64_RAX);
7496                 break;
7497         case SAVE_STRUCT:
7498                 /* FIXME: */
7499                 break;
7500         case SAVE_XMM:
7501                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7502                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7503                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7504                 break;
7505         case SAVE_NONE:
7506                 break;
7507         default:
7508                 g_assert_not_reached ();
7509         }
7510
7511         return code;
7512 }
7513
7514 void
7515 mono_arch_flush_icache (guint8 *code, gint size)
7516 {
7517         /* Not needed */
7518 }
7519
7520 void
7521 mono_arch_flush_register_windows (void)
7522 {
7523 }
7524
7525 gboolean
7526 mono_arch_is_inst_imm (gint64 imm)
7527 {
7528         return amd64_use_imm32 (imm);
7529 }
7530
7531 /*
7532  * Determine whenever the trap whose info is in SIGINFO is caused by
7533  * integer overflow.
7534  */
7535 gboolean
7536 mono_arch_is_int_overflow (void *sigctx, void *info)
7537 {
7538         MonoContext ctx;
7539         guint8* rip;
7540         int reg;
7541         gint64 value;
7542
7543         mono_sigctx_to_monoctx (sigctx, &ctx);
7544
7545         rip = (guint8*)ctx.gregs [AMD64_RIP];
7546
7547         if (IS_REX (rip [0])) {
7548                 reg = amd64_rex_b (rip [0]);
7549                 rip ++;
7550         }
7551         else
7552                 reg = 0;
7553
7554         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7555                 /* idiv REG */
7556                 reg += x86_modrm_rm (rip [1]);
7557
7558                 value = ctx.gregs [reg];
7559
7560                 if (value == -1)
7561                         return TRUE;
7562         }
7563
7564         return FALSE;
7565 }
7566
7567 guint32
7568 mono_arch_get_patch_offset (guint8 *code)
7569 {
7570         return 3;
7571 }
7572
7573 /**
7574  * mono_breakpoint_clean_code:
7575  *
7576  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7577  * breakpoints in the original code, they are removed in the copy.
7578  *
7579  * Returns TRUE if no sw breakpoint was present.
7580  */
7581 gboolean
7582 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7583 {
7584         /*
7585          * If method_start is non-NULL we need to perform bound checks, since we access memory
7586          * at code - offset we could go before the start of the method and end up in a different
7587          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7588          * instead.
7589          */
7590         if (!method_start || code - offset >= method_start) {
7591                 memcpy (buf, code - offset, size);
7592         } else {
7593                 int diff = code - method_start;
7594                 memset (buf, 0, size);
7595                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7596         }
7597         return TRUE;
7598 }
7599
7600 int
7601 mono_arch_get_this_arg_reg (guint8 *code)
7602 {
7603         return AMD64_ARG_REG1;
7604 }
7605
7606 gpointer
7607 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7608 {
7609         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7610 }
7611
7612 #define MAX_ARCH_DELEGATE_PARAMS 10
7613
7614 static gpointer
7615 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7616 {
7617         guint8 *code, *start;
7618         GSList *unwind_ops = NULL;
7619         int i;
7620
7621         unwind_ops = mono_arch_get_cie_program ();
7622
7623         if (has_target) {
7624                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7625
7626                 /* Replace the this argument with the target */
7627                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7628                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7629                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7630
7631                 g_assert ((code - start) < 64);
7632         } else {
7633                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7634
7635                 if (param_count == 0) {
7636                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7637                 } else {
7638                         /* We have to shift the arguments left */
7639                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7640                         for (i = 0; i < param_count; ++i) {
7641 #ifdef TARGET_WIN32
7642                                 if (i < 3)
7643                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7644                                 else
7645                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7646 #else
7647                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7648 #endif
7649                         }
7650
7651                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7652                 }
7653                 g_assert ((code - start) < 64);
7654         }
7655
7656         mono_arch_flush_icache (start, code - start);
7657
7658         if (has_target) {
7659                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7660         } else {
7661                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7662                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7663                 g_free (name);
7664         }
7665
7666         if (mono_jit_map_is_enabled ()) {
7667                 char *buff;
7668                 if (has_target)
7669                         buff = (char*)"delegate_invoke_has_target";
7670                 else
7671                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7672                 mono_emit_jit_tramp (start, code - start, buff);
7673                 if (!has_target)
7674                         g_free (buff);
7675         }
7676         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7677
7678         return start;
7679 }
7680
7681 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7682
7683 static gpointer
7684 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7685 {
7686         guint8 *code, *start;
7687         int size = 20;
7688         char *tramp_name;
7689         GSList *unwind_ops;
7690
7691         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7692                 return NULL;
7693
7694         start = code = (guint8 *)mono_global_codeman_reserve (size);
7695
7696         unwind_ops = mono_arch_get_cie_program ();
7697
7698         /* Replace the this argument with the target */
7699         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7700         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7701
7702         if (load_imt_reg) {
7703                 /* Load the IMT reg */
7704                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7705         }
7706
7707         /* Load the vtable */
7708         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7709         amd64_jump_membase (code, AMD64_RAX, offset);
7710         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7711
7712         if (load_imt_reg)
7713                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7714         else
7715                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7716         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7717         g_free (tramp_name);
7718
7719         return start;
7720 }
7721
7722 /*
7723  * mono_arch_get_delegate_invoke_impls:
7724  *
7725  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7726  * trampolines.
7727  */
7728 GSList*
7729 mono_arch_get_delegate_invoke_impls (void)
7730 {
7731         GSList *res = NULL;
7732         MonoTrampInfo *info;
7733         int i;
7734
7735         get_delegate_invoke_impl (&info, TRUE, 0);
7736         res = g_slist_prepend (res, info);
7737
7738         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7739                 get_delegate_invoke_impl (&info, FALSE, i);
7740                 res = g_slist_prepend (res, info);
7741         }
7742
7743         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7744                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7745                 res = g_slist_prepend (res, info);
7746
7747                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7748                 res = g_slist_prepend (res, info);
7749         }
7750
7751         return res;
7752 }
7753
7754 gpointer
7755 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7756 {
7757         guint8 *code, *start;
7758         int i;
7759
7760         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7761                 return NULL;
7762
7763         /* FIXME: Support more cases */
7764         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7765                 return NULL;
7766
7767         if (has_target) {
7768                 static guint8* cached = NULL;
7769
7770                 if (cached)
7771                         return cached;
7772
7773                 if (mono_aot_only) {
7774                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7775                 } else {
7776                         MonoTrampInfo *info;
7777                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7778                         mono_tramp_info_register (info, NULL);
7779                 }
7780
7781                 mono_memory_barrier ();
7782
7783                 cached = start;
7784         } else {
7785                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7786                 for (i = 0; i < sig->param_count; ++i)
7787                         if (!mono_is_regsize_var (sig->params [i]))
7788                                 return NULL;
7789                 if (sig->param_count > 4)
7790                         return NULL;
7791
7792                 code = cache [sig->param_count];
7793                 if (code)
7794                         return code;
7795
7796                 if (mono_aot_only) {
7797                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7798                         start = (guint8 *)mono_aot_get_trampoline (name);
7799                         g_free (name);
7800                 } else {
7801                         MonoTrampInfo *info;
7802                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7803                         mono_tramp_info_register (info, NULL);
7804                 }
7805
7806                 mono_memory_barrier ();
7807
7808                 cache [sig->param_count] = start;
7809         }
7810
7811         return start;
7812 }
7813
7814 gpointer
7815 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7816 {
7817         MonoTrampInfo *info;
7818         gpointer code;
7819
7820         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7821         if (code)
7822                 mono_tramp_info_register (info, NULL);
7823         return code;
7824 }
7825
7826 void
7827 mono_arch_finish_init (void)
7828 {
7829 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7830         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7831 #endif
7832 }
7833
7834 void
7835 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7836 {
7837 }
7838
7839 #define CMP_SIZE (6 + 1)
7840 #define CMP_REG_REG_SIZE (4 + 1)
7841 #define BR_SMALL_SIZE 2
7842 #define BR_LARGE_SIZE 6
7843 #define MOV_REG_IMM_SIZE 10
7844 #define MOV_REG_IMM_32BIT_SIZE 6
7845 #define JUMP_REG_SIZE (2 + 1)
7846
7847 static int
7848 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7849 {
7850         int i, distance = 0;
7851         for (i = start; i < target; ++i)
7852                 distance += imt_entries [i]->chunk_size;
7853         return distance;
7854 }
7855
7856 /*
7857  * LOCKING: called with the domain lock held
7858  */
7859 gpointer
7860 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7861         gpointer fail_tramp)
7862 {
7863         int i;
7864         int size = 0;
7865         guint8 *code, *start;
7866         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7867         GSList *unwind_ops;
7868
7869         for (i = 0; i < count; ++i) {
7870                 MonoIMTCheckItem *item = imt_entries [i];
7871                 if (item->is_equals) {
7872                         if (item->check_target_idx) {
7873                                 if (!item->compare_done) {
7874                                         if (amd64_use_imm32 ((gint64)item->key))
7875                                                 item->chunk_size += CMP_SIZE;
7876                                         else
7877                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7878                                 }
7879                                 if (item->has_target_code) {
7880                                         item->chunk_size += MOV_REG_IMM_SIZE;
7881                                 } else {
7882                                         if (vtable_is_32bit)
7883                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7884                                         else
7885                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7886                                 }
7887                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7888                         } else {
7889                                 if (fail_tramp) {
7890                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7891                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7892                                 } else {
7893                                         if (vtable_is_32bit)
7894                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7895                                         else
7896                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7897                                         item->chunk_size += JUMP_REG_SIZE;
7898                                         /* with assert below:
7899                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7900                                          */
7901                                 }
7902                         }
7903                 } else {
7904                         if (amd64_use_imm32 ((gint64)item->key))
7905                                 item->chunk_size += CMP_SIZE;
7906                         else
7907                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7908                         item->chunk_size += BR_LARGE_SIZE;
7909                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7910                 }
7911                 size += item->chunk_size;
7912         }
7913         if (fail_tramp)
7914                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
7915         else
7916                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7917         start = code;
7918
7919         unwind_ops = mono_arch_get_cie_program ();
7920
7921         for (i = 0; i < count; ++i) {
7922                 MonoIMTCheckItem *item = imt_entries [i];
7923                 item->code_target = code;
7924                 if (item->is_equals) {
7925                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7926
7927                         if (item->check_target_idx || fail_case) {
7928                                 if (!item->compare_done || fail_case) {
7929                                         if (amd64_use_imm32 ((gint64)item->key))
7930                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7931                                         else {
7932                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7933                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7934                                         }
7935                                 }
7936                                 item->jmp_code = code;
7937                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7938                                 if (item->has_target_code) {
7939                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7940                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7941                                 } else {
7942                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7943                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7944                                 }
7945
7946                                 if (fail_case) {
7947                                         amd64_patch (item->jmp_code, code);
7948                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7949                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7950                                         item->jmp_code = NULL;
7951                                 }
7952                         } else {
7953                                 /* enable the commented code to assert on wrong method */
7954 #if 0
7955                                 if (amd64_is_imm32 (item->key))
7956                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7957                                 else {
7958                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7959                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7960                                 }
7961                                 item->jmp_code = code;
7962                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7963                                 /* See the comment below about R10 */
7964                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7965                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7966                                 amd64_patch (item->jmp_code, code);
7967                                 amd64_breakpoint (code);
7968                                 item->jmp_code = NULL;
7969 #else
7970                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7971                                    needs to be preserved.  R10 needs
7972                                    to be preserved for calls which
7973                                    require a runtime generic context,
7974                                    but interface calls don't. */
7975                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7976                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7977 #endif
7978                         }
7979                 } else {
7980                         if (amd64_use_imm32 ((gint64)item->key))
7981                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7982                         else {
7983                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7984                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7985                         }
7986                         item->jmp_code = code;
7987                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7988                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7989                         else
7990                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7991                 }
7992                 g_assert (code - item->code_target <= item->chunk_size);
7993         }
7994         /* patch the branches to get to the target items */
7995         for (i = 0; i < count; ++i) {
7996                 MonoIMTCheckItem *item = imt_entries [i];
7997                 if (item->jmp_code) {
7998                         if (item->check_target_idx) {
7999                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8000                         }
8001                 }
8002         }
8003
8004         if (!fail_tramp)
8005                 mono_stats.imt_thunks_size += code - start;
8006         g_assert (code - start <= size);
8007
8008         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8009
8010         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8011
8012         return start;
8013 }
8014
8015 MonoMethod*
8016 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8017 {
8018         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8019 }
8020
8021 MonoVTable*
8022 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8023 {
8024         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8025 }
8026
8027 GSList*
8028 mono_arch_get_cie_program (void)
8029 {
8030         GSList *l = NULL;
8031
8032         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8033         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8034
8035         return l;
8036 }
8037
8038 #ifndef DISABLE_JIT
8039
8040 MonoInst*
8041 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8042 {
8043         MonoInst *ins = NULL;
8044         int opcode = 0;
8045
8046         if (cmethod->klass == mono_defaults.math_class) {
8047                 if (strcmp (cmethod->name, "Sin") == 0) {
8048                         opcode = OP_SIN;
8049                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8050                         opcode = OP_COS;
8051                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8052                         opcode = OP_SQRT;
8053                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8054                         opcode = OP_ABS;
8055                 }
8056
8057                 if (opcode && fsig->param_count == 1) {
8058                         MONO_INST_NEW (cfg, ins, opcode);
8059                         ins->type = STACK_R8;
8060                         ins->dreg = mono_alloc_freg (cfg);
8061                         ins->sreg1 = args [0]->dreg;
8062                         MONO_ADD_INS (cfg->cbb, ins);
8063                 }
8064
8065                 opcode = 0;
8066                 if (cfg->opt & MONO_OPT_CMOV) {
8067                         if (strcmp (cmethod->name, "Min") == 0) {
8068                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8069                                         opcode = OP_IMIN;
8070                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8071                                         opcode = OP_IMIN_UN;
8072                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8073                                         opcode = OP_LMIN;
8074                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8075                                         opcode = OP_LMIN_UN;
8076                         } else if (strcmp (cmethod->name, "Max") == 0) {
8077                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8078                                         opcode = OP_IMAX;
8079                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8080                                         opcode = OP_IMAX_UN;
8081                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8082                                         opcode = OP_LMAX;
8083                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8084                                         opcode = OP_LMAX_UN;
8085                         }
8086                 }
8087
8088                 if (opcode && fsig->param_count == 2) {
8089                         MONO_INST_NEW (cfg, ins, opcode);
8090                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8091                         ins->dreg = mono_alloc_ireg (cfg);
8092                         ins->sreg1 = args [0]->dreg;
8093                         ins->sreg2 = args [1]->dreg;
8094                         MONO_ADD_INS (cfg->cbb, ins);
8095                 }
8096
8097 #if 0
8098                 /* OP_FREM is not IEEE compatible */
8099                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8100                         MONO_INST_NEW (cfg, ins, OP_FREM);
8101                         ins->inst_i0 = args [0];
8102                         ins->inst_i1 = args [1];
8103                 }
8104 #endif
8105         }
8106
8107         return ins;
8108 }
8109 #endif
8110
8111 gboolean
8112 mono_arch_print_tree (MonoInst *tree, int arity)
8113 {
8114         return 0;
8115 }
8116
8117 mgreg_t
8118 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8119 {
8120         return ctx->gregs [reg];
8121 }
8122
8123 void
8124 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8125 {
8126         ctx->gregs [reg] = val;
8127 }
8128
8129 gpointer
8130 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8131 {
8132         gpointer *sp, old_value;
8133         char *bp;
8134
8135         /*Load the spvar*/
8136         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8137         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8138
8139         old_value = *sp;
8140         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8141                 return old_value;
8142
8143         *sp = new_value;
8144
8145         return old_value;
8146 }
8147
8148 /*
8149  * mono_arch_emit_load_aotconst:
8150  *
8151  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8152  * TARGET from the mscorlib GOT in full-aot code.
8153  * On AMD64, the result is placed into R11.
8154  */
8155 guint8*
8156 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8157 {
8158         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8159         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8160
8161         return code;
8162 }
8163
8164 /*
8165  * mono_arch_get_trampolines:
8166  *
8167  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8168  * for AOT.
8169  */
8170 GSList *
8171 mono_arch_get_trampolines (gboolean aot)
8172 {
8173         return mono_amd64_get_exception_trampolines (aot);
8174 }
8175
8176 /* Soft Debug support */
8177 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8178
8179 /*
8180  * mono_arch_set_breakpoint:
8181  *
8182  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8183  * The location should contain code emitted by OP_SEQ_POINT.
8184  */
8185 void
8186 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8187 {
8188         guint8 *code = ip;
8189
8190         if (ji->from_aot) {
8191                 guint32 native_offset = ip - (guint8*)ji->code_start;
8192                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8193
8194                 g_assert (info->bp_addrs [native_offset] == 0);
8195                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8196         } else {
8197                 /* ip points to a mov r11, 0 */
8198                 g_assert (code [0] == 0x41);
8199                 g_assert (code [1] == 0xbb);
8200                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8201         }
8202 }
8203
8204 /*
8205  * mono_arch_clear_breakpoint:
8206  *
8207  *   Clear the breakpoint at IP.
8208  */
8209 void
8210 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8211 {
8212         guint8 *code = ip;
8213
8214         if (ji->from_aot) {
8215                 guint32 native_offset = ip - (guint8*)ji->code_start;
8216                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8217
8218                 info->bp_addrs [native_offset] = NULL;
8219         } else {
8220                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8221         }
8222 }
8223
8224 gboolean
8225 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8226 {
8227         /* We use soft breakpoints on amd64 */
8228         return FALSE;
8229 }
8230
8231 /*
8232  * mono_arch_skip_breakpoint:
8233  *
8234  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8235  * we resume, the instruction is not executed again.
8236  */
8237 void
8238 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8239 {
8240         g_assert_not_reached ();
8241 }
8242
8243 /*
8244  * mono_arch_start_single_stepping:
8245  *
8246  *   Start single stepping.
8247  */
8248 void
8249 mono_arch_start_single_stepping (void)
8250 {
8251         ss_trampoline = mini_get_single_step_trampoline ();
8252 }
8253
8254 /*
8255  * mono_arch_stop_single_stepping:
8256  *
8257  *   Stop single stepping.
8258  */
8259 void
8260 mono_arch_stop_single_stepping (void)
8261 {
8262         ss_trampoline = NULL;
8263 }
8264
8265 /*
8266  * mono_arch_is_single_step_event:
8267  *
8268  *   Return whenever the machine state in SIGCTX corresponds to a single
8269  * step event.
8270  */
8271 gboolean
8272 mono_arch_is_single_step_event (void *info, void *sigctx)
8273 {
8274         /* We use soft breakpoints on amd64 */
8275         return FALSE;
8276 }
8277
8278 /*
8279  * mono_arch_skip_single_step:
8280  *
8281  *   Modify CTX so the ip is placed after the single step trigger instruction,
8282  * we resume, the instruction is not executed again.
8283  */
8284 void
8285 mono_arch_skip_single_step (MonoContext *ctx)
8286 {
8287         g_assert_not_reached ();
8288 }
8289
8290 /*
8291  * mono_arch_create_seq_point_info:
8292  *
8293  *   Return a pointer to a data structure which is used by the sequence
8294  * point implementation in AOTed code.
8295  */
8296 gpointer
8297 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8298 {
8299         SeqPointInfo *info;
8300         MonoJitInfo *ji;
8301
8302         // FIXME: Add a free function
8303
8304         mono_domain_lock (domain);
8305         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8306                                                                 code);
8307         mono_domain_unlock (domain);
8308
8309         if (!info) {
8310                 ji = mono_jit_info_table_find (domain, (char*)code);
8311                 g_assert (ji);
8312
8313                 // FIXME: Optimize the size
8314                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8315
8316                 info->ss_tramp_addr = &ss_trampoline;
8317
8318                 mono_domain_lock (domain);
8319                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8320                                                          code, info);
8321                 mono_domain_unlock (domain);
8322         }
8323
8324         return info;
8325 }
8326
8327 void
8328 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8329 {
8330         ext->lmf.previous_lmf = prev_lmf;
8331         /* Mark that this is a MonoLMFExt */
8332         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8333         ext->lmf.rsp = (gssize)ext;
8334 }
8335
8336 #endif
8337
8338 gboolean
8339 mono_arch_opcode_supported (int opcode)
8340 {
8341         switch (opcode) {
8342         case OP_ATOMIC_ADD_I4:
8343         case OP_ATOMIC_ADD_I8:
8344         case OP_ATOMIC_EXCHANGE_I4:
8345         case OP_ATOMIC_EXCHANGE_I8:
8346         case OP_ATOMIC_CAS_I4:
8347         case OP_ATOMIC_CAS_I8:
8348         case OP_ATOMIC_LOAD_I1:
8349         case OP_ATOMIC_LOAD_I2:
8350         case OP_ATOMIC_LOAD_I4:
8351         case OP_ATOMIC_LOAD_I8:
8352         case OP_ATOMIC_LOAD_U1:
8353         case OP_ATOMIC_LOAD_U2:
8354         case OP_ATOMIC_LOAD_U4:
8355         case OP_ATOMIC_LOAD_U8:
8356         case OP_ATOMIC_LOAD_R4:
8357         case OP_ATOMIC_LOAD_R8:
8358         case OP_ATOMIC_STORE_I1:
8359         case OP_ATOMIC_STORE_I2:
8360         case OP_ATOMIC_STORE_I4:
8361         case OP_ATOMIC_STORE_I8:
8362         case OP_ATOMIC_STORE_U1:
8363         case OP_ATOMIC_STORE_U2:
8364         case OP_ATOMIC_STORE_U4:
8365         case OP_ATOMIC_STORE_U8:
8366         case OP_ATOMIC_STORE_R4:
8367         case OP_ATOMIC_STORE_R8:
8368                 return TRUE;
8369         default:
8370                 return FALSE;
8371         }
8372 }
8373
8374 CallInfo*
8375 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8376 {
8377         return get_call_info (mp, sig);
8378 }