mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40 #include <mono/utils/unlocked.h>
  41
  42 #include "trace.h"
  43 #include "ir-emit.h"
  44 #include "mini-amd64.h"
  45 #include "cpu-amd64.h"
  46 #include "debugger-agent.h"
  47 #include "mini-gc.h"
  48
  49 #ifdef MONO_XEN_OPT
  50 static gboolean optimize_for_xen = TRUE;
  51 #else
  52 #define optimize_for_xen 0
  53 #endif
  54
  55 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  56
  57 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  58
  59 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  60
  61 #ifdef TARGET_WIN32
  62 /* Under windows, the calling convention is never stdcall */
  63 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  64 #else
  65 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  66 #endif
  67
  68 /* This mutex protects architecture specific caches */
  69 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  70 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  71 static mono_mutex_t mini_arch_mutex;
  72
  73 /* The single step trampoline */
  74 static gpointer ss_trampoline;
  75
  76 /* The breakpoint trampoline */
  77 static gpointer bp_trampoline;
  78
  79 /* Offset between fp and the first argument in the callee */
  80 #define ARGS_OFFSET 16
  81 #define GP_SCRATCH_REG AMD64_R11
  82
  83 /*
  84  * AMD64 register usage:
  85  * - callee saved registers are used for global register allocation
  86  * - %r11 is used for materializing 64 bit constants in opcodes
  87  * - the rest is used for local allocation
  88  */
  89
  90 /*
  91  * Floating point comparison results:
  92  *                  ZF PF CF
  93  * A > B            0  0  0
  94  * A < B            0  0  1
  95  * A = B            1  0  0
  96  * A > B            0  0  0
  97  * UNORDERED        1  1  1
  98  */
  99
 100 const char*
 101 mono_arch_regname (int reg)
 102 {
 103         switch (reg) {
 104         case AMD64_RAX: return "%rax";
 105         case AMD64_RBX: return "%rbx";
 106         case AMD64_RCX: return "%rcx";
 107         case AMD64_RDX: return "%rdx";
 108         case AMD64_RSP: return "%rsp";
 109         case AMD64_RBP: return "%rbp";
 110         case AMD64_RDI: return "%rdi";
 111         case AMD64_RSI: return "%rsi";
 112         case AMD64_R8: return "%r8";
 113         case AMD64_R9: return "%r9";
 114         case AMD64_R10: return "%r10";
 115         case AMD64_R11: return "%r11";
 116         case AMD64_R12: return "%r12";
 117         case AMD64_R13: return "%r13";
 118         case AMD64_R14: return "%r14";
 119         case AMD64_R15: return "%r15";
 120         }
 121         return "unknown";
 122 }
 123
 124 static const char * packed_xmmregs [] = {
 125         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 126         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 127 };
 128
 129 static const char * single_xmmregs [] = {
 130         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 131         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 132 };
 133
 134 const char*
 135 mono_arch_fregname (int reg)
 136 {
 137         if (reg < AMD64_XMM_NREG)
 138                 return single_xmmregs [reg];
 139         else
 140                 return "unknown";
 141 }
 142
 143 const char *
 144 mono_arch_xregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return packed_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 static gboolean
 153 debug_omit_fp (void)
 154 {
 155 #if 0
 156         return mono_debug_count ();
 157 #else
 158         return TRUE;
 159 #endif
 160 }
 161
 162 static inline gboolean
 163 amd64_is_near_call (guint8 *code)
 164 {
 165         /* Skip REX */
 166         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 167                 code += 1;
 168
 169         return code [0] == 0xe8;
 170 }
 171
 172 static inline gboolean
 173 amd64_use_imm32 (gint64 val)
 174 {
 175         if (mini_get_debug_options()->single_imm_size)
 176                 return FALSE;
 177
 178         return amd64_is_imm32 (val);
 179 }
 180
 181 static void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if (code [0] == 0xe8) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 #define DEBUG(a) if (cfg->verbose_level > 1) a
 221
 222 static void inline
 223 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 224 {
 225     ainfo->offset = *stack_size;
 226
 227     if (*gr >= PARAM_REGS) {
 228                 ainfo->storage = ArgOnStack;
 229                 ainfo->arg_size = sizeof (mgreg_t);
 230                 /* Since the same stack slot size is used for all arg */
 231                 /*  types, it needs to be big enough to hold them all */
 232                 (*stack_size) += sizeof(mgreg_t);
 233     }
 234     else {
 235                 ainfo->storage = ArgInIReg;
 236                 ainfo->reg = param_regs [*gr];
 237                 (*gr) ++;
 238     }
 239 }
 240
 241 static void inline
 242 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 243 {
 244     ainfo->offset = *stack_size;
 245
 246     if (*gr >= FLOAT_PARAM_REGS) {
 247                 ainfo->storage = ArgOnStack;
 248                 ainfo->arg_size = sizeof (mgreg_t);
 249                 /* Since the same stack slot size is used for both float */
 250                 /*  types, it needs to be big enough to hold them both */
 251                 (*stack_size) += sizeof(mgreg_t);
 252     }
 253     else {
 254                 /* A double register */
 255                 if (is_double)
 256                         ainfo->storage = ArgInDoubleSSEReg;
 257                 else
 258                         ainfo->storage = ArgInFloatSSEReg;
 259                 ainfo->reg = *gr;
 260                 (*gr) += 1;
 261     }
 262 }
 263
 264 typedef enum ArgumentClass {
 265         ARG_CLASS_NO_CLASS,
 266         ARG_CLASS_MEMORY,
 267         ARG_CLASS_INTEGER,
 268         ARG_CLASS_SSE
 269 } ArgumentClass;
 270
 271 static ArgumentClass
 272 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 273 {
 274         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 275         MonoType *ptype;
 276
 277         ptype = mini_get_underlying_type (type);
 278         switch (ptype->type) {
 279         case MONO_TYPE_I1:
 280         case MONO_TYPE_U1:
 281         case MONO_TYPE_I2:
 282         case MONO_TYPE_U2:
 283         case MONO_TYPE_I4:
 284         case MONO_TYPE_U4:
 285         case MONO_TYPE_I:
 286         case MONO_TYPE_U:
 287         case MONO_TYPE_OBJECT:
 288         case MONO_TYPE_PTR:
 289         case MONO_TYPE_FNPTR:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 typedef struct {
 342         MonoType *type;
 343         int size, offset;
 344 } StructFieldInfo;
 345
 346 /*
 347  * collect_field_info_nested:
 348  *
 349  *   Collect field info from KLASS recursively into FIELDS.
 350  */
 351 static void
 352 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 353 {
 354         MonoMarshalType *info;
 355         int i;
 356
 357         if (pinvoke) {
 358                 info = mono_marshal_load_type_info (klass);
 359                 g_assert(info);
 360                 for (i = 0; i < info->num_fields; ++i) {
 361                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 362                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 363                         } else {
 364                                 guint32 align;
 365                                 StructFieldInfo f;
 366
 367                                 f.type = info->fields [i].field->type;
 368                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 369                                                                                                                            info->fields [i].mspec,
 370                                                                                                                            &align, TRUE, unicode);
 371                                 f.offset = offset + info->fields [i].offset;
 372                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 373                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 374                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 375                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 376                                                 g_array_append_val (fields_array, f);
 377                                                 while (f.size + f.offset < info->native_size) {
 378                                                         f.offset += f.size;
 379                                                         g_array_append_val (fields_array, f);
 380                                                 }
 381                                         } else {
 382                                                 f.size = info->native_size - f.offset;
 383                                                 g_array_append_val (fields_array, f);
 384                                         }
 385                                 } else {
 386                                         g_array_append_val (fields_array, f);
 387                                 }
 388                         }
 389                 }
 390         } else {
 391                 gpointer iter;
 392                 MonoClassField *field;
 393
 394                 iter = NULL;
 395                 while ((field = mono_class_get_fields (klass, &iter))) {
 396                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 397                                 continue;
 398                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 399                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 400                         } else {
 401                                 int align;
 402                                 StructFieldInfo f;
 403
 404                                 f.type = field->type;
 405                                 f.size = mono_type_size (field->type, &align);
 406                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 407
 408                                 g_array_append_val (fields_array, f);
 409                         }
 410                 }
 411         }
 412 }
 413
 414 #ifdef TARGET_WIN32
 415
 416 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 417 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 418
 419 static gboolean
 420 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 421 {
 422         gboolean result = FALSE;
 423
 424         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 425         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 426
 427         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 428         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 429         arg_info->pair_size [0] = 0;
 430         arg_info->pair_size [1] = 0;
 431         arg_info->nregs = 0;
 432
 433         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 434                 /* Pass parameter in integer register. */
 435                 arg_info->pair_storage [0] = ArgInIReg;
 436                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 437                 (*current_int_reg) ++;
 438                 result = TRUE;
 439         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 440                 /* Pass parameter in float register. */
 441                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 442                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 443                 (*current_float_reg) ++;
 444                 result = TRUE;
 445         }
 446
 447         if (result == TRUE) {
 448                 arg_info->pair_size [0] = arg_size;
 449                 arg_info->nregs = 1;
 450         }
 451
 452         return result;
 453 }
 454
 455 static inline gboolean
 456 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 457 {
 458         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 459 }
 460
 461 static inline gboolean
 462 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 463 {
 464         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 465 }
 466
 467 static void
 468 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 469                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 470 {
 471         /* Windows x64 value type ABI.
 472         *
 473         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 474         *
 475         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 476         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 477         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 478         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 479         *
 480         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 481         *
 482         * Integers/Float types smaller than or equal to 8 bytes
 483         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 484         * Properly sized struct/unions (1,2,4,8)
 485         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 486         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 487         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 488         */
 489
 490         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 491
 492         if (!is_return) {
 493
 494                 /* Parameter cases. */
 495                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 496                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 497
 498                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 499                         arg_info->storage = ArgValuetypeInReg;
 500                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 501                                 /* No more registers, fallback passing parameter on stack as value. */
 502                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 503
 504                                 /* Passing value directly on stack, so use size of value. */
 505                                 arg_info->storage = ArgOnStack;
 506                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 507                                 arg_info->offset = *stack_size;
 508                                 arg_info->arg_size = arg_size;
 509                                 *stack_size += arg_size;
 510                         }
 511                 } else {
 512                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 513                         arg_info->storage = ArgValuetypeAddrInIReg;
 514                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 515                                 /* No more registers, fallback passing address to parameter on stack. */
 516                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 517
 518                                 /* Passing an address to value on stack, so use size of register as argument size. */
 519                                 arg_info->storage = ArgValuetypeAddrOnStack;
 520                                 arg_size = sizeof (mgreg_t);
 521                                 arg_info->offset = *stack_size;
 522                                 arg_info->arg_size = arg_size;
 523                                 *stack_size += arg_size;
 524                         }
 525                 }
 526         } else {
 527                 /* Return value cases. */
 528                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 529                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 530
 531                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 532                         arg_info->storage = ArgValuetypeInReg;
 533                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 534
 535                         /* Only RAX/XMM0 should be used to return valuetype. */
 536                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 537                 } else {
 538                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 539                         arg_info->storage = ArgValuetypeAddrInIReg;
 540                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 541
 542                         /* Only RAX should be used to return valuetype address. */
 543                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 544
 545                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 546                         arg_info->offset = *stack_size;
 547                         *stack_size += arg_size;
 548                 }
 549         }
 550 }
 551
 552 static void
 553 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 554 {
 555         *arg_size = 0;
 556         *arg_class = ARG_CLASS_NO_CLASS;
 557
 558         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 559
 560         if (pinvoke) {
 561                 /* Calculate argument class type and size of marshalled type. */
 562                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 563                 *arg_size = info->native_size;
 564         } else {
 565                 /* Calculate argument class type and size of managed type. */
 566                 *arg_size = mono_class_value_size (klass, NULL);
 567         }
 568
 569         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 570         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 571
 572         if (*arg_class == ARG_CLASS_MEMORY) {
 573                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 574                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 575         }
 576
 577         /*
 578         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 579         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 580         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 581         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 582         * it must be represented in call and cannot be dropped.
 583         */
 584         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 585                 arg_info->pass_empty_struct = TRUE;
 586                 *arg_size = SIZEOF_REGISTER;
 587                 *arg_class = ARG_CLASS_INTEGER;
 588         }
 589
 590         assert (*arg_class != ARG_CLASS_NO_CLASS);
 591 }
 592
 593 static void
 594 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 595                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 596 {
 597         guint32 arg_size = SIZEOF_REGISTER;
 598         MonoClass *klass = NULL;
 599         ArgumentClass arg_class;
 600
 601         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 602
 603         klass = mono_class_from_mono_type (type);
 604         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 605
 606         /* Only drop value type if its not an empty struct as input that must be represented in call */
 607         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 608                 arg_info->storage = ArgValuetypeInReg;
 609                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 610         } else {
 611                 /* Alocate storage for value type. */
 612                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 613         }
 614 }
 615
 616 #endif /* TARGET_WIN32 */
 617
 618 static void
 619 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 620                            gboolean is_return,
 621                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 622 {
 623 #ifdef TARGET_WIN32
 624         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 625 #else
 626         guint32 size, quad, nquads, i, nfields;
 627         /* Keep track of the size used in each quad so we can */
 628         /* use the right size when copying args/return vars.  */
 629         guint32 quadsize [2] = {8, 8};
 630         ArgumentClass args [2];
 631         StructFieldInfo *fields = NULL;
 632         GArray *fields_array;
 633         MonoClass *klass;
 634         gboolean pass_on_stack = FALSE;
 635         int struct_size;
 636
 637         klass = mono_class_from_mono_type (type);
 638         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 639
 640         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 641                 /* We pass and return vtypes of size 8 in a register */
 642         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 643                 pass_on_stack = TRUE;
 644         }
 645
 646         /* If this struct can't be split up naturally into 8-byte */
 647         /* chunks (registers), pass it on the stack.              */
 648         if (sig->pinvoke) {
 649                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 650                 g_assert (info);
 651                 struct_size = info->native_size;
 652         } else {
 653                 struct_size = mono_class_value_size (klass, NULL);
 654         }
 655         /*
 656          * Collect field information recursively to be able to
 657          * handle nested structures.
 658          */
 659         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 660         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 661         fields = (StructFieldInfo*)fields_array->data;
 662         nfields = fields_array->len;
 663
 664         for (i = 0; i < nfields; ++i) {
 665                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 666                         pass_on_stack = TRUE;
 667                         break;
 668                 }
 669         }
 670
 671         if (size == 0) {
 672                 ainfo->storage = ArgValuetypeInReg;
 673                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 674                 return;
 675         }
 676
 677         if (pass_on_stack) {
 678                 /* Allways pass in memory */
 679                 ainfo->offset = *stack_size;
 680                 *stack_size += ALIGN_TO (size, 8);
 681                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 682                 if (!is_return)
 683                         ainfo->arg_size = ALIGN_TO (size, 8);
 684
 685                 g_array_free (fields_array, TRUE);
 686                 return;
 687         }
 688
 689         if (size > 8)
 690                 nquads = 2;
 691         else
 692                 nquads = 1;
 693
 694         if (!sig->pinvoke) {
 695                 int n = mono_class_value_size (klass, NULL);
 696
 697                 quadsize [0] = n >= 8 ? 8 : n;
 698                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 699
 700                 /* Always pass in 1 or 2 integer registers */
 701                 args [0] = ARG_CLASS_INTEGER;
 702                 args [1] = ARG_CLASS_INTEGER;
 703                 /* Only the simplest cases are supported */
 704                 if (is_return && nquads != 1) {
 705                         args [0] = ARG_CLASS_MEMORY;
 706                         args [1] = ARG_CLASS_MEMORY;
 707                 }
 708         } else {
 709                 /*
 710                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 711                  * The X87 and SSEUP stuff is left out since there are no such types in
 712                  * the CLR.
 713                  */
 714                 if (!nfields) {
 715                         ainfo->storage = ArgValuetypeInReg;
 716                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 717                         return;
 718                 }
 719
 720                 if (struct_size > 16) {
 721                         ainfo->offset = *stack_size;
 722                         *stack_size += ALIGN_TO (struct_size, 8);
 723                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 724                         if (!is_return)
 725                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 726
 727                         g_array_free (fields_array, TRUE);
 728                         return;
 729                 }
 730
 731                 args [0] = ARG_CLASS_NO_CLASS;
 732                 args [1] = ARG_CLASS_NO_CLASS;
 733                 for (quad = 0; quad < nquads; ++quad) {
 734                         ArgumentClass class1;
 735
 736                         if (nfields == 0)
 737                                 class1 = ARG_CLASS_MEMORY;
 738                         else
 739                                 class1 = ARG_CLASS_NO_CLASS;
 740                         for (i = 0; i < nfields; ++i) {
 741                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 742                                         /* Unaligned field */
 743                                         NOT_IMPLEMENTED;
 744                                 }
 745
 746                                 /* Skip fields in other quad */
 747                                 if ((quad == 0) && (fields [i].offset >= 8))
 748                                         continue;
 749                                 if ((quad == 1) && (fields [i].offset < 8))
 750                                         continue;
 751
 752                                 /* How far into this quad this data extends.*/
 753                                 /* (8 is size of quad) */
 754                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 755
 756                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 757                         }
 758                         /* Empty structs have a nonzero size, causing this assert to be hit */
 759                         if (sig->pinvoke)
 760                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 761                         args [quad] = class1;
 762                 }
 763         }
 764
 765         g_array_free (fields_array, TRUE);
 766
 767         /* Post merger cleanup */
 768         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 769                 args [0] = args [1] = ARG_CLASS_MEMORY;
 770
 771         /* Allocate registers */
 772         {
 773                 int orig_gr = *gr;
 774                 int orig_fr = *fr;
 775
 776                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 777                         quadsize [0] ++;
 778                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 779                         quadsize [1] ++;
 780
 781                 ainfo->storage = ArgValuetypeInReg;
 782                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 783                 g_assert (quadsize [0] <= 8);
 784                 g_assert (quadsize [1] <= 8);
 785                 ainfo->pair_size [0] = quadsize [0];
 786                 ainfo->pair_size [1] = quadsize [1];
 787                 ainfo->nregs = nquads;
 788                 for (quad = 0; quad < nquads; ++quad) {
 789                         switch (args [quad]) {
 790                         case ARG_CLASS_INTEGER:
 791                                 if (*gr >= PARAM_REGS)
 792                                         args [quad] = ARG_CLASS_MEMORY;
 793                                 else {
 794                                         ainfo->pair_storage [quad] = ArgInIReg;
 795                                         if (is_return)
 796                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 797                                         else
 798                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 799                                         (*gr) ++;
 800                                 }
 801                                 break;
 802                         case ARG_CLASS_SSE:
 803                                 if (*fr >= FLOAT_PARAM_REGS)
 804                                         args [quad] = ARG_CLASS_MEMORY;
 805                                 else {
 806                                         if (quadsize[quad] <= 4)
 807                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 808                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 809                                         ainfo->pair_regs [quad] = *fr;
 810                                         (*fr) ++;
 811                                 }
 812                                 break;
 813                         case ARG_CLASS_MEMORY:
 814                                 break;
 815                         case ARG_CLASS_NO_CLASS:
 816                                 break;
 817                         default:
 818                                 g_assert_not_reached ();
 819                         }
 820                 }
 821
 822                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 823                         int arg_size;
 824                         /* Revert possible register assignments */
 825                         *gr = orig_gr;
 826                         *fr = orig_fr;
 827
 828                         ainfo->offset = *stack_size;
 829                         if (sig->pinvoke)
 830                                 arg_size = ALIGN_TO (struct_size, 8);
 831                         else
 832                                 arg_size = nquads * sizeof(mgreg_t);
 833                         *stack_size += arg_size;
 834                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 835                         if (!is_return)
 836                                 ainfo->arg_size = arg_size;
 837                 }
 838         }
 839 #endif /* !TARGET_WIN32 */
 840 }
 841
 842 /*
 843  * get_call_info:
 844  *
 845  * Obtain information about a call according to the calling convention.
 846  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 847  * Draft Version 0.23" document for more information.
 848  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 849  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 850  */
 851 static CallInfo*
 852 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 853 {
 854         guint32 i, gr, fr, pstart;
 855         MonoType *ret_type;
 856         int n = sig->hasthis + sig->param_count;
 857         guint32 stack_size = 0;
 858         CallInfo *cinfo;
 859         gboolean is_pinvoke = sig->pinvoke;
 860
 861         if (mp)
 862                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 863         else
 864                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 865
 866         cinfo->nargs = n;
 867         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 868
 869         gr = 0;
 870         fr = 0;
 871
 872 #ifdef TARGET_WIN32
 873         /* Reserve space where the callee can save the argument registers */
 874         stack_size = 4 * sizeof (mgreg_t);
 875 #endif
 876
 877         /* return value */
 878         ret_type = mini_get_underlying_type (sig->ret);
 879         switch (ret_type->type) {
 880         case MONO_TYPE_I1:
 881         case MONO_TYPE_U1:
 882         case MONO_TYPE_I2:
 883         case MONO_TYPE_U2:
 884         case MONO_TYPE_I4:
 885         case MONO_TYPE_U4:
 886         case MONO_TYPE_I:
 887         case MONO_TYPE_U:
 888         case MONO_TYPE_PTR:
 889         case MONO_TYPE_FNPTR:
 890         case MONO_TYPE_OBJECT:
 891                 cinfo->ret.storage = ArgInIReg;
 892                 cinfo->ret.reg = AMD64_RAX;
 893                 break;
 894         case MONO_TYPE_U8:
 895         case MONO_TYPE_I8:
 896                 cinfo->ret.storage = ArgInIReg;
 897                 cinfo->ret.reg = AMD64_RAX;
 898                 break;
 899         case MONO_TYPE_R4:
 900                 cinfo->ret.storage = ArgInFloatSSEReg;
 901                 cinfo->ret.reg = AMD64_XMM0;
 902                 break;
 903         case MONO_TYPE_R8:
 904                 cinfo->ret.storage = ArgInDoubleSSEReg;
 905                 cinfo->ret.reg = AMD64_XMM0;
 906                 break;
 907         case MONO_TYPE_GENERICINST:
 908                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 909                         cinfo->ret.storage = ArgInIReg;
 910                         cinfo->ret.reg = AMD64_RAX;
 911                         break;
 912                 }
 913                 if (mini_is_gsharedvt_type (ret_type)) {
 914                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 915                         break;
 916                 }
 917                 /* fall through */
 918         case MONO_TYPE_VALUETYPE:
 919         case MONO_TYPE_TYPEDBYREF: {
 920                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 921
 922                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 923                 g_assert (cinfo->ret.storage != ArgInIReg);
 924                 break;
 925         }
 926         case MONO_TYPE_VAR:
 927         case MONO_TYPE_MVAR:
 928                 g_assert (mini_is_gsharedvt_type (ret_type));
 929                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 930                 break;
 931         case MONO_TYPE_VOID:
 932                 break;
 933         default:
 934                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 935         }
 936
 937         pstart = 0;
 938         /*
 939          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 940          * the first argument, allowing 'this' to be always passed in the first arg reg.
 941          * Also do this if the first argument is a reference type, since virtual calls
 942          * are sometimes made using calli without sig->hasthis set, like in the delegate
 943          * invoke wrappers.
 944          */
 945         ArgStorage ret_storage = cinfo->ret.storage;
 946         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 947                 if (sig->hasthis) {
 948                         add_general (&gr, &stack_size, cinfo->args + 0);
 949                 } else {
 950                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 951                         pstart = 1;
 952                 }
 953                 add_general (&gr, &stack_size, &cinfo->ret);
 954                 cinfo->ret.storage = ret_storage;
 955                 cinfo->vret_arg_index = 1;
 956         } else {
 957                 /* this */
 958                 if (sig->hasthis)
 959                         add_general (&gr, &stack_size, cinfo->args + 0);
 960
 961                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 962                         add_general (&gr, &stack_size, &cinfo->ret);
 963                         cinfo->ret.storage = ret_storage;
 964                 }
 965         }
 966
 967         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 968                 gr = PARAM_REGS;
 969                 fr = FLOAT_PARAM_REGS;
 970
 971                 /* Emit the signature cookie just before the implicit arguments */
 972                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 973         }
 974
 975         for (i = pstart; i < sig->param_count; ++i) {
 976                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 977                 MonoType *ptype;
 978
 979 #ifdef TARGET_WIN32
 980                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 981                 if (gr > fr)
 982                         fr = gr;
 983                 else if (fr > gr)
 984                         gr = fr;
 985 #endif
 986
 987                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 988                         /* We allways pass the sig cookie on the stack for simplicity */
 989                         /*
 990                          * Prevent implicit arguments + the sig cookie from being passed
 991                          * in registers.
 992                          */
 993                         gr = PARAM_REGS;
 994                         fr = FLOAT_PARAM_REGS;
 995
 996                         /* Emit the signature cookie just before the implicit arguments */
 997                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 998                 }
 999
1000                 ptype = mini_get_underlying_type (sig->params [i]);
1001                 switch (ptype->type) {
1002                 case MONO_TYPE_I1:
1003                 case MONO_TYPE_U1:
1004                         add_general (&gr, &stack_size, ainfo);
1005                         ainfo->byte_arg_size = 1;
1006                         break;
1007                 case MONO_TYPE_I2:
1008                 case MONO_TYPE_U2:
1009                         add_general (&gr, &stack_size, ainfo);
1010                         ainfo->byte_arg_size = 2;
1011                         break;
1012                 case MONO_TYPE_I4:
1013                 case MONO_TYPE_U4:
1014                         add_general (&gr, &stack_size, ainfo);
1015                         ainfo->byte_arg_size = 4;
1016                         break;
1017                 case MONO_TYPE_I:
1018                 case MONO_TYPE_U:
1019                 case MONO_TYPE_PTR:
1020                 case MONO_TYPE_FNPTR:
1021                 case MONO_TYPE_OBJECT:
1022                         add_general (&gr, &stack_size, ainfo);
1023                         break;
1024                 case MONO_TYPE_GENERICINST:
1025                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1026                                 add_general (&gr, &stack_size, ainfo);
1027                                 break;
1028                         }
1029                         if (mini_is_gsharedvt_variable_type (ptype)) {
1030                                 /* gsharedvt arguments are passed by ref */
1031                                 add_general (&gr, &stack_size, ainfo);
1032                                 if (ainfo->storage == ArgInIReg)
1033                                         ainfo->storage = ArgGSharedVtInReg;
1034                                 else
1035                                         ainfo->storage = ArgGSharedVtOnStack;
1036                                 break;
1037                         }
1038                         /* fall through */
1039                 case MONO_TYPE_VALUETYPE:
1040                 case MONO_TYPE_TYPEDBYREF:
1041                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1042                         break;
1043                 case MONO_TYPE_U8:
1044
1045                 case MONO_TYPE_I8:
1046                         add_general (&gr, &stack_size, ainfo);
1047                         break;
1048                 case MONO_TYPE_R4:
1049                         add_float (&fr, &stack_size, ainfo, FALSE);
1050                         break;
1051                 case MONO_TYPE_R8:
1052                         add_float (&fr, &stack_size, ainfo, TRUE);
1053                         break;
1054                 case MONO_TYPE_VAR:
1055                 case MONO_TYPE_MVAR:
1056                         /* gsharedvt arguments are passed by ref */
1057                         g_assert (mini_is_gsharedvt_type (ptype));
1058                         add_general (&gr, &stack_size, ainfo);
1059                         if (ainfo->storage == ArgInIReg)
1060                                 ainfo->storage = ArgGSharedVtInReg;
1061                         else
1062                                 ainfo->storage = ArgGSharedVtOnStack;
1063                         break;
1064                 default:
1065                         g_assert_not_reached ();
1066                 }
1067         }
1068
1069         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1070                 gr = PARAM_REGS;
1071                 fr = FLOAT_PARAM_REGS;
1072
1073                 /* Emit the signature cookie just before the implicit arguments */
1074                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1075         }
1076
1077         cinfo->stack_usage = stack_size;
1078         cinfo->reg_usage = gr;
1079         cinfo->freg_usage = fr;
1080         return cinfo;
1081 }
1082
1083 /*
1084  * mono_arch_get_argument_info:
1085  * @csig:  a method signature
1086  * @param_count: the number of parameters to consider
1087  * @arg_info: an array to store the result infos
1088  *
1089  * Gathers information on parameters such as size, alignment and
1090  * padding. arg_info should be large enought to hold param_count + 1 entries.
1091  *
1092  * Returns the size of the argument area on the stack.
1093  */
1094 int
1095 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1096 {
1097         int k;
1098         CallInfo *cinfo = get_call_info (NULL, csig);
1099         guint32 args_size = cinfo->stack_usage;
1100
1101         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1102         if (csig->hasthis) {
1103                 arg_info [0].offset = 0;
1104         }
1105
1106         for (k = 0; k < param_count; k++) {
1107                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1108                 /* FIXME: */
1109                 arg_info [k + 1].size = 0;
1110         }
1111
1112         g_free (cinfo);
1113
1114         return args_size;
1115 }
1116
1117 gboolean
1118 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1119 {
1120         CallInfo *c1, *c2;
1121         gboolean res;
1122         MonoType *callee_ret;
1123
1124         c1 = get_call_info (NULL, caller_sig);
1125         c2 = get_call_info (NULL, callee_sig);
1126         res = c1->stack_usage >= c2->stack_usage;
1127         callee_ret = mini_get_underlying_type (callee_sig->ret);
1128         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1129                 /* An address on the callee's stack is passed as the first argument */
1130                 res = FALSE;
1131
1132         g_free (c1);
1133         g_free (c2);
1134
1135         return res;
1136 }
1137
1138 /*
1139  * Initialize the cpu to execute managed code.
1140  */
1141 void
1142 mono_arch_cpu_init (void)
1143 {
1144 #ifndef _MSC_VER
1145         guint16 fpcw;
1146
1147         /* spec compliance requires running with double precision */
1148         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1149         fpcw &= ~X86_FPCW_PRECC_MASK;
1150         fpcw |= X86_FPCW_PREC_DOUBLE;
1151         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1152         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1153 #else
1154         /* TODO: This is crashing on Win64 right now.
1155         * _control87 (_PC_53, MCW_PC);
1156         */
1157 #endif
1158 }
1159
1160 /*
1161  * Initialize architecture specific code.
1162  */
1163 void
1164 mono_arch_init (void)
1165 {
1166         mono_os_mutex_init_recursive (&mini_arch_mutex);
1167
1168         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1169         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1170         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1171         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1172
1173 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1174         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1175 #endif
1176
1177         if (!mono_aot_only)
1178                 bp_trampoline = mini_get_breakpoint_trampoline ();
1179 }
1180
1181 /*
1182  * Cleanup architecture specific code.
1183  */
1184 void
1185 mono_arch_cleanup (void)
1186 {
1187         mono_os_mutex_destroy (&mini_arch_mutex);
1188 }
1189
1190 /*
1191  * This function returns the optimizations supported on this cpu.
1192  */
1193 guint32
1194 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1195 {
1196         guint32 opts = 0;
1197
1198         *exclude_mask = 0;
1199
1200         if (mono_hwcap_x86_has_cmov) {
1201                 opts |= MONO_OPT_CMOV;
1202
1203                 if (mono_hwcap_x86_has_fcmov)
1204                         opts |= MONO_OPT_FCMOV;
1205                 else
1206                         *exclude_mask |= MONO_OPT_FCMOV;
1207         } else {
1208                 *exclude_mask |= MONO_OPT_CMOV;
1209         }
1210
1211 #ifdef TARGET_WIN32
1212         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1213         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1214         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1215         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1216         /* will now have a reference to an argument that won't be fully decomposed. */
1217         *exclude_mask |= MONO_OPT_SIMD;
1218 #endif
1219
1220         return opts;
1221 }
1222
1223 /*
1224  * This function test for all SSE functions supported.
1225  *
1226  * Returns a bitmask corresponding to all supported versions.
1227  *
1228  */
1229 guint32
1230 mono_arch_cpu_enumerate_simd_versions (void)
1231 {
1232         guint32 sse_opts = 0;
1233
1234         if (mono_hwcap_x86_has_sse1)
1235                 sse_opts |= SIMD_VERSION_SSE1;
1236
1237         if (mono_hwcap_x86_has_sse2)
1238                 sse_opts |= SIMD_VERSION_SSE2;
1239
1240         if (mono_hwcap_x86_has_sse3)
1241                 sse_opts |= SIMD_VERSION_SSE3;
1242
1243         if (mono_hwcap_x86_has_ssse3)
1244                 sse_opts |= SIMD_VERSION_SSSE3;
1245
1246         if (mono_hwcap_x86_has_sse41)
1247                 sse_opts |= SIMD_VERSION_SSE41;
1248
1249         if (mono_hwcap_x86_has_sse42)
1250                 sse_opts |= SIMD_VERSION_SSE42;
1251
1252         if (mono_hwcap_x86_has_sse4a)
1253                 sse_opts |= SIMD_VERSION_SSE4a;
1254
1255         return sse_opts;
1256 }
1257
1258 #ifndef DISABLE_JIT
1259
1260 GList *
1261 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1262 {
1263         GList *vars = NULL;
1264         int i;
1265
1266         for (i = 0; i < cfg->num_varinfo; i++) {
1267                 MonoInst *ins = cfg->varinfo [i];
1268                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1269
1270                 /* unused vars */
1271                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1272                         continue;
1273
1274                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1275                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1276                         continue;
1277
1278                 if (mono_is_regsize_var (ins->inst_vtype)) {
1279                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1280                         g_assert (i == vmv->idx);
1281                         vars = g_list_prepend (vars, vmv);
1282                 }
1283         }
1284
1285         vars = mono_varlist_sort (cfg, vars, 0);
1286
1287         return vars;
1288 }
1289
1290 /**
1291  * mono_arch_compute_omit_fp:
1292  * Determine whether the frame pointer can be eliminated.
1293  */
1294 static void
1295 mono_arch_compute_omit_fp (MonoCompile *cfg)
1296 {
1297         MonoMethodSignature *sig;
1298         MonoMethodHeader *header;
1299         int i, locals_size;
1300         CallInfo *cinfo;
1301
1302         if (cfg->arch.omit_fp_computed)
1303                 return;
1304
1305         header = cfg->header;
1306
1307         sig = mono_method_signature (cfg->method);
1308
1309         if (!cfg->arch.cinfo)
1310                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1311         cinfo = (CallInfo *)cfg->arch.cinfo;
1312
1313         /*
1314          * FIXME: Remove some of the restrictions.
1315          */
1316         cfg->arch.omit_fp = TRUE;
1317         cfg->arch.omit_fp_computed = TRUE;
1318
1319         if (cfg->disable_omit_fp)
1320                 cfg->arch.omit_fp = FALSE;
1321
1322         if (!debug_omit_fp ())
1323                 cfg->arch.omit_fp = FALSE;
1324         /*
1325         if (cfg->method->save_lmf)
1326                 cfg->arch.omit_fp = FALSE;
1327         */
1328         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1329                 cfg->arch.omit_fp = FALSE;
1330         if (header->num_clauses)
1331                 cfg->arch.omit_fp = FALSE;
1332         if (cfg->param_area)
1333                 cfg->arch.omit_fp = FALSE;
1334         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1335                 cfg->arch.omit_fp = FALSE;
1336         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1337                 cfg->arch.omit_fp = FALSE;
1338         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1339                 ArgInfo *ainfo = &cinfo->args [i];
1340
1341                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1342                         /*
1343                          * The stack offset can only be determined when the frame
1344                          * size is known.
1345                          */
1346                         cfg->arch.omit_fp = FALSE;
1347                 }
1348         }
1349
1350         locals_size = 0;
1351         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1352                 MonoInst *ins = cfg->varinfo [i];
1353                 int ialign;
1354
1355                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1356         }
1357 }
1358
1359 GList *
1360 mono_arch_get_global_int_regs (MonoCompile *cfg)
1361 {
1362         GList *regs = NULL;
1363
1364         mono_arch_compute_omit_fp (cfg);
1365
1366         if (cfg->arch.omit_fp)
1367                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1368
1369         /* We use the callee saved registers for global allocation */
1370         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1371         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1373         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1374         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1375 #ifdef TARGET_WIN32
1376         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1377         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1378 #endif
1379
1380         return regs;
1381 }
1382
1383 GList*
1384 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1385 {
1386         GList *regs = NULL;
1387         int i;
1388
1389         /* All XMM registers */
1390         for (i = 0; i < 16; ++i)
1391                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1392
1393         return regs;
1394 }
1395
1396 GList*
1397 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1398 {
1399         static GList *r = NULL;
1400
1401         if (r == NULL) {
1402                 GList *regs = NULL;
1403
1404                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1408                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1409                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1410
1411                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1419
1420                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1421         }
1422
1423         return r;
1424 }
1425
1426 GList*
1427 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1428 {
1429         int i;
1430         static GList *r = NULL;
1431
1432         if (r == NULL) {
1433                 GList *regs = NULL;
1434
1435                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1436                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1437
1438                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1439         }
1440
1441         return r;
1442 }
1443
1444 /*
1445  * mono_arch_regalloc_cost:
1446  *
1447  *  Return the cost, in number of memory references, of the action of
1448  * allocating the variable VMV into a register during global register
1449  * allocation.
1450  */
1451 guint32
1452 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1453 {
1454         MonoInst *ins = cfg->varinfo [vmv->idx];
1455
1456         if (cfg->method->save_lmf)
1457                 /* The register is already saved */
1458                 /* substract 1 for the invisible store in the prolog */
1459                 return (ins->opcode == OP_ARG) ? 0 : 1;
1460         else
1461                 /* push+pop */
1462                 return (ins->opcode == OP_ARG) ? 1 : 2;
1463 }
1464
1465 /*
1466  * mono_arch_fill_argument_info:
1467  *
1468  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1469  * of the method.
1470  */
1471 void
1472 mono_arch_fill_argument_info (MonoCompile *cfg)
1473 {
1474         MonoType *sig_ret;
1475         MonoMethodSignature *sig;
1476         MonoInst *ins;
1477         int i;
1478         CallInfo *cinfo;
1479
1480         sig = mono_method_signature (cfg->method);
1481
1482         cinfo = (CallInfo *)cfg->arch.cinfo;
1483         sig_ret = mini_get_underlying_type (sig->ret);
1484
1485         /*
1486          * Contrary to mono_arch_allocate_vars (), the information should describe
1487          * where the arguments are at the beginning of the method, not where they can be
1488          * accessed during the execution of the method. The later makes no sense for the
1489          * global register allocator, since a variable can be in more than one location.
1490          */
1491         switch (cinfo->ret.storage) {
1492         case ArgInIReg:
1493         case ArgInFloatSSEReg:
1494         case ArgInDoubleSSEReg:
1495                 cfg->ret->opcode = OP_REGVAR;
1496                 cfg->ret->inst_c0 = cinfo->ret.reg;
1497                 break;
1498         case ArgValuetypeInReg:
1499                 cfg->ret->opcode = OP_REGOFFSET;
1500                 cfg->ret->inst_basereg = -1;
1501                 cfg->ret->inst_offset = -1;
1502                 break;
1503         case ArgNone:
1504                 break;
1505         default:
1506                 g_assert_not_reached ();
1507         }
1508
1509         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1510                 ArgInfo *ainfo = &cinfo->args [i];
1511
1512                 ins = cfg->args [i];
1513
1514                 switch (ainfo->storage) {
1515                 case ArgInIReg:
1516                 case ArgInFloatSSEReg:
1517                 case ArgInDoubleSSEReg:
1518                         ins->opcode = OP_REGVAR;
1519                         ins->inst_c0 = ainfo->reg;
1520                         break;
1521                 case ArgOnStack:
1522                         ins->opcode = OP_REGOFFSET;
1523                         ins->inst_basereg = -1;
1524                         ins->inst_offset = -1;
1525                         break;
1526                 case ArgValuetypeInReg:
1527                         /* Dummy */
1528                         ins->opcode = OP_NOP;
1529                         break;
1530                 default:
1531                         g_assert_not_reached ();
1532                 }
1533         }
1534 }
1535
1536 void
1537 mono_arch_allocate_vars (MonoCompile *cfg)
1538 {
1539         MonoType *sig_ret;
1540         MonoMethodSignature *sig;
1541         MonoInst *ins;
1542         int i, offset;
1543         guint32 locals_stack_size, locals_stack_align;
1544         gint32 *offsets;
1545         CallInfo *cinfo;
1546
1547         sig = mono_method_signature (cfg->method);
1548
1549         cinfo = (CallInfo *)cfg->arch.cinfo;
1550         sig_ret = mini_get_underlying_type (sig->ret);
1551
1552         mono_arch_compute_omit_fp (cfg);
1553
1554         /*
1555          * We use the ABI calling conventions for managed code as well.
1556          * Exception: valuetypes are only sometimes passed or returned in registers.
1557          */
1558
1559         /*
1560          * The stack looks like this:
1561          * <incoming arguments passed on the stack>
1562          * <return value>
1563          * <lmf/caller saved registers>
1564          * <locals>
1565          * <spill area>
1566          * <localloc area>  -> grows dynamically
1567          * <params area>
1568          */
1569
1570         if (cfg->arch.omit_fp) {
1571                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1572                 cfg->frame_reg = AMD64_RSP;
1573                 offset = 0;
1574         } else {
1575                 /* Locals are allocated backwards from %fp */
1576                 cfg->frame_reg = AMD64_RBP;
1577                 offset = 0;
1578         }
1579
1580         cfg->arch.saved_iregs = cfg->used_int_regs;
1581         if (cfg->method->save_lmf) {
1582                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1583                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1584                 cfg->arch.saved_iregs |= iregs_to_save;
1585         }
1586
1587         if (cfg->arch.omit_fp)
1588                 cfg->arch.reg_save_area_offset = offset;
1589         /* Reserve space for callee saved registers */
1590         for (i = 0; i < AMD64_NREG; ++i)
1591                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1592                         offset += sizeof(mgreg_t);
1593                 }
1594         if (!cfg->arch.omit_fp)
1595                 cfg->arch.reg_save_area_offset = -offset;
1596
1597         if (sig_ret->type != MONO_TYPE_VOID) {
1598                 switch (cinfo->ret.storage) {
1599                 case ArgInIReg:
1600                 case ArgInFloatSSEReg:
1601                 case ArgInDoubleSSEReg:
1602                         cfg->ret->opcode = OP_REGVAR;
1603                         cfg->ret->inst_c0 = cinfo->ret.reg;
1604                         cfg->ret->dreg = cinfo->ret.reg;
1605                         break;
1606                 case ArgValuetypeAddrInIReg:
1607                 case ArgGsharedvtVariableInReg:
1608                         /* The register is volatile */
1609                         cfg->vret_addr->opcode = OP_REGOFFSET;
1610                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1611                         if (cfg->arch.omit_fp) {
1612                                 cfg->vret_addr->inst_offset = offset;
1613                                 offset += 8;
1614                         } else {
1615                                 offset += 8;
1616                                 cfg->vret_addr->inst_offset = -offset;
1617                         }
1618                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1619                                 printf ("vret_addr =");
1620                                 mono_print_ins (cfg->vret_addr);
1621                         }
1622                         break;
1623                 case ArgValuetypeInReg:
1624                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1625                         cfg->ret->opcode = OP_REGOFFSET;
1626                         cfg->ret->inst_basereg = cfg->frame_reg;
1627                         if (cfg->arch.omit_fp) {
1628                                 cfg->ret->inst_offset = offset;
1629                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1630                         } else {
1631                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1632                                 cfg->ret->inst_offset = - offset;
1633                         }
1634                         break;
1635                 default:
1636                         g_assert_not_reached ();
1637                 }
1638         }
1639
1640         /* Allocate locals */
1641         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1642         if (locals_stack_align) {
1643                 offset += (locals_stack_align - 1);
1644                 offset &= ~(locals_stack_align - 1);
1645         }
1646         if (cfg->arch.omit_fp) {
1647                 cfg->locals_min_stack_offset = offset;
1648                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1649         } else {
1650                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1651                 cfg->locals_max_stack_offset = - offset;
1652         }
1653
1654         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1655                 if (offsets [i] != -1) {
1656                         MonoInst *ins = cfg->varinfo [i];
1657                         ins->opcode = OP_REGOFFSET;
1658                         ins->inst_basereg = cfg->frame_reg;
1659                         if (cfg->arch.omit_fp)
1660                                 ins->inst_offset = (offset + offsets [i]);
1661                         else
1662                                 ins->inst_offset = - (offset + offsets [i]);
1663                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1664                 }
1665         }
1666         offset += locals_stack_size;
1667
1668         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1669                 g_assert (!cfg->arch.omit_fp);
1670                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1671                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1672         }
1673
1674         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1675                 ins = cfg->args [i];
1676                 if (ins->opcode != OP_REGVAR) {
1677                         ArgInfo *ainfo = &cinfo->args [i];
1678                         gboolean inreg = TRUE;
1679
1680                         /* FIXME: Allocate volatile arguments to registers */
1681                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1682                                 inreg = FALSE;
1683
1684                         /*
1685                          * Under AMD64, all registers used to pass arguments to functions
1686                          * are volatile across calls.
1687                          * FIXME: Optimize this.
1688                          */
1689                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1690                                 inreg = FALSE;
1691
1692                         ins->opcode = OP_REGOFFSET;
1693
1694                         switch (ainfo->storage) {
1695                         case ArgInIReg:
1696                         case ArgInFloatSSEReg:
1697                         case ArgInDoubleSSEReg:
1698                         case ArgGSharedVtInReg:
1699                                 if (inreg) {
1700                                         ins->opcode = OP_REGVAR;
1701                                         ins->dreg = ainfo->reg;
1702                                 }
1703                                 break;
1704                         case ArgOnStack:
1705                         case ArgGSharedVtOnStack:
1706                                 g_assert (!cfg->arch.omit_fp);
1707                                 ins->opcode = OP_REGOFFSET;
1708                                 ins->inst_basereg = cfg->frame_reg;
1709                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1710                                 break;
1711                         case ArgValuetypeInReg:
1712                                 break;
1713                         case ArgValuetypeAddrInIReg:
1714                         case ArgValuetypeAddrOnStack: {
1715                                 MonoInst *indir;
1716                                 g_assert (!cfg->arch.omit_fp);
1717                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1718                                 MONO_INST_NEW (cfg, indir, 0);
1719
1720                                 indir->opcode = OP_REGOFFSET;
1721                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1722                                         indir->inst_basereg = cfg->frame_reg;
1723                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1724                                         offset += (sizeof (gpointer));
1725                                         indir->inst_offset = - offset;
1726                                 }
1727                                 else {
1728                                         indir->inst_basereg = cfg->frame_reg;
1729                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1730                                 }
1731
1732                                 ins->opcode = OP_VTARG_ADDR;
1733                                 ins->inst_left = indir;
1734
1735                                 break;
1736                         }
1737                         default:
1738                                 NOT_IMPLEMENTED;
1739                         }
1740
1741                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1742                                 ins->opcode = OP_REGOFFSET;
1743                                 ins->inst_basereg = cfg->frame_reg;
1744                                 /* These arguments are saved to the stack in the prolog */
1745                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1746                                 if (cfg->arch.omit_fp) {
1747                                         ins->inst_offset = offset;
1748                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1749                                         // Arguments are yet supported by the stack map creation code
1750                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1751                                 } else {
1752                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1753                                         ins->inst_offset = - offset;
1754                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1755                                 }
1756                         }
1757                 }
1758         }
1759
1760         cfg->stack_offset = offset;
1761 }
1762
1763 void
1764 mono_arch_create_vars (MonoCompile *cfg)
1765 {
1766         MonoMethodSignature *sig;
1767         CallInfo *cinfo;
1768         MonoType *sig_ret;
1769
1770         sig = mono_method_signature (cfg->method);
1771
1772         if (!cfg->arch.cinfo)
1773                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1774         cinfo = (CallInfo *)cfg->arch.cinfo;
1775
1776         if (cinfo->ret.storage == ArgValuetypeInReg)
1777                 cfg->ret_var_is_local = TRUE;
1778
1779         sig_ret = mini_get_underlying_type (sig->ret);
1780         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1781                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1782                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1783                         printf ("vret_addr = ");
1784                         mono_print_ins (cfg->vret_addr);
1785                 }
1786         }
1787
1788         if (cfg->gen_sdb_seq_points) {
1789                 MonoInst *ins;
1790
1791                 if (cfg->compile_aot) {
1792                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1793                         ins->flags |= MONO_INST_VOLATILE;
1794                         cfg->arch.seq_point_info_var = ins;
1795                 }
1796                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1797                 ins->flags |= MONO_INST_VOLATILE;
1798                 cfg->arch.ss_tramp_var = ins;
1799
1800                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1801                 ins->flags |= MONO_INST_VOLATILE;
1802                 cfg->arch.bp_tramp_var = ins;
1803         }
1804
1805         if (cfg->method->save_lmf)
1806                 cfg->create_lmf_var = TRUE;
1807
1808         if (cfg->method->save_lmf) {
1809                 cfg->lmf_ir = TRUE;
1810         }
1811 }
1812
1813 static void
1814 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1815 {
1816         MonoInst *ins;
1817
1818         switch (storage) {
1819         case ArgInIReg:
1820                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1821                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1822                 ins->sreg1 = tree->dreg;
1823                 MONO_ADD_INS (cfg->cbb, ins);
1824                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1825                 break;
1826         case ArgInFloatSSEReg:
1827                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1828                 ins->dreg = mono_alloc_freg (cfg);
1829                 ins->sreg1 = tree->dreg;
1830                 MONO_ADD_INS (cfg->cbb, ins);
1831
1832                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1833                 break;
1834         case ArgInDoubleSSEReg:
1835                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1836                 ins->dreg = mono_alloc_freg (cfg);
1837                 ins->sreg1 = tree->dreg;
1838                 MONO_ADD_INS (cfg->cbb, ins);
1839
1840                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1841
1842                 break;
1843         default:
1844                 g_assert_not_reached ();
1845         }
1846 }
1847
1848 static int
1849 arg_storage_to_load_membase (ArgStorage storage)
1850 {
1851         switch (storage) {
1852         case ArgInIReg:
1853 #if defined(__mono_ilp32__)
1854                 return OP_LOADI8_MEMBASE;
1855 #else
1856                 return OP_LOAD_MEMBASE;
1857 #endif
1858         case ArgInDoubleSSEReg:
1859                 return OP_LOADR8_MEMBASE;
1860         case ArgInFloatSSEReg:
1861                 return OP_LOADR4_MEMBASE;
1862         default:
1863                 g_assert_not_reached ();
1864         }
1865
1866         return -1;
1867 }
1868
1869 static void
1870 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1871 {
1872         MonoMethodSignature *tmp_sig;
1873         int sig_reg;
1874
1875         if (call->tail_call)
1876                 NOT_IMPLEMENTED;
1877
1878         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1879
1880         /*
1881          * mono_ArgIterator_Setup assumes the signature cookie is
1882          * passed first and all the arguments which were before it are
1883          * passed on the stack after the signature. So compensate by
1884          * passing a different signature.
1885          */
1886         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1887         tmp_sig->param_count -= call->signature->sentinelpos;
1888         tmp_sig->sentinelpos = 0;
1889         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1890
1891         sig_reg = mono_alloc_ireg (cfg);
1892         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1893
1894         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1895 }
1896
1897 #ifdef ENABLE_LLVM
1898 static inline LLVMArgStorage
1899 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1900 {
1901         switch (storage) {
1902         case ArgInIReg:
1903                 return LLVMArgInIReg;
1904         case ArgNone:
1905                 return LLVMArgNone;
1906         case ArgGSharedVtInReg:
1907         case ArgGSharedVtOnStack:
1908                 return LLVMArgGSharedVt;
1909         default:
1910                 g_assert_not_reached ();
1911                 return LLVMArgNone;
1912         }
1913 }
1914
1915 LLVMCallInfo*
1916 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1917 {
1918         int i, n;
1919         CallInfo *cinfo;
1920         ArgInfo *ainfo;
1921         int j;
1922         LLVMCallInfo *linfo;
1923         MonoType *t, *sig_ret;
1924
1925         n = sig->param_count + sig->hasthis;
1926         sig_ret = mini_get_underlying_type (sig->ret);
1927
1928         cinfo = get_call_info (cfg->mempool, sig);
1929
1930         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1931
1932         /*
1933          * LLVM always uses the native ABI while we use our own ABI, the
1934          * only difference is the handling of vtypes:
1935          * - we only pass/receive them in registers in some cases, and only
1936          *   in 1 or 2 integer registers.
1937          */
1938         switch (cinfo->ret.storage) {
1939         case ArgNone:
1940                 linfo->ret.storage = LLVMArgNone;
1941                 break;
1942         case ArgInIReg:
1943         case ArgInFloatSSEReg:
1944         case ArgInDoubleSSEReg:
1945                 linfo->ret.storage = LLVMArgNormal;
1946                 break;
1947         case ArgValuetypeInReg: {
1948                 ainfo = &cinfo->ret;
1949
1950                 if (sig->pinvoke &&
1951                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1952                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1953                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1954                         cfg->disable_llvm = TRUE;
1955                         return linfo;
1956                 }
1957
1958                 linfo->ret.storage = LLVMArgVtypeInReg;
1959                 for (j = 0; j < 2; ++j)
1960                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1961                 break;
1962         }
1963         case ArgValuetypeAddrInIReg:
1964         case ArgGsharedvtVariableInReg:
1965                 /* Vtype returned using a hidden argument */
1966                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1967                 linfo->vret_arg_index = cinfo->vret_arg_index;
1968                 break;
1969         default:
1970                 g_assert_not_reached ();
1971                 break;
1972         }
1973
1974         for (i = 0; i < n; ++i) {
1975                 ainfo = cinfo->args + i;
1976
1977                 if (i >= sig->hasthis)
1978                         t = sig->params [i - sig->hasthis];
1979                 else
1980                         t = &mono_defaults.int_class->byval_arg;
1981                 t = mini_type_get_underlying_type (t);
1982
1983                 linfo->args [i].storage = LLVMArgNone;
1984
1985                 switch (ainfo->storage) {
1986                 case ArgInIReg:
1987                         linfo->args [i].storage = LLVMArgNormal;
1988                         break;
1989                 case ArgInDoubleSSEReg:
1990                 case ArgInFloatSSEReg:
1991                         linfo->args [i].storage = LLVMArgNormal;
1992                         break;
1993                 case ArgOnStack:
1994                         if (MONO_TYPE_ISSTRUCT (t))
1995                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1996                         else
1997                                 linfo->args [i].storage = LLVMArgNormal;
1998                         break;
1999                 case ArgValuetypeInReg:
2000                         if (sig->pinvoke &&
2001                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2002                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2003                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2004                                 cfg->disable_llvm = TRUE;
2005                                 return linfo;
2006                         }
2007
2008                         linfo->args [i].storage = LLVMArgVtypeInReg;
2009                         for (j = 0; j < 2; ++j)
2010                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2011                         break;
2012                 case ArgGSharedVtInReg:
2013                 case ArgGSharedVtOnStack:
2014                         linfo->args [i].storage = LLVMArgGSharedVt;
2015                         break;
2016                 default:
2017                         cfg->exception_message = g_strdup ("ainfo->storage");
2018                         cfg->disable_llvm = TRUE;
2019                         break;
2020                 }
2021         }
2022
2023         return linfo;
2024 }
2025 #endif
2026
2027 void
2028 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2029 {
2030         MonoInst *arg, *in;
2031         MonoMethodSignature *sig;
2032         MonoType *sig_ret;
2033         int i, n;
2034         CallInfo *cinfo;
2035         ArgInfo *ainfo;
2036
2037         sig = call->signature;
2038         n = sig->param_count + sig->hasthis;
2039
2040         cinfo = get_call_info (cfg->mempool, sig);
2041
2042         sig_ret = sig->ret;
2043
2044         if (COMPILE_LLVM (cfg)) {
2045                 /* We shouldn't be called in the llvm case */
2046                 cfg->disable_llvm = TRUE;
2047                 return;
2048         }
2049
2050         /*
2051          * Emit all arguments which are passed on the stack to prevent register
2052          * allocation problems.
2053          */
2054         for (i = 0; i < n; ++i) {
2055                 MonoType *t;
2056                 ainfo = cinfo->args + i;
2057
2058                 in = call->args [i];
2059
2060                 if (sig->hasthis && i == 0)
2061                         t = &mono_defaults.object_class->byval_arg;
2062                 else
2063                         t = sig->params [i - sig->hasthis];
2064
2065                 t = mini_get_underlying_type (t);
2066                 //XXX what about ArgGSharedVtOnStack here?
2067                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2068                         if (!t->byref) {
2069                                 if (t->type == MONO_TYPE_R4)
2070                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2071                                 else if (t->type == MONO_TYPE_R8)
2072                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2073                                 else
2074                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2075                         } else {
2076                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2077                         }
2078                         if (cfg->compute_gc_maps) {
2079                                 MonoInst *def;
2080
2081                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2082                         }
2083                 }
2084         }
2085
2086         /*
2087          * Emit all parameters passed in registers in non-reverse order for better readability
2088          * and to help the optimization in emit_prolog ().
2089          */
2090         for (i = 0; i < n; ++i) {
2091                 ainfo = cinfo->args + i;
2092
2093                 in = call->args [i];
2094
2095                 if (ainfo->storage == ArgInIReg)
2096                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2097         }
2098
2099         for (i = n - 1; i >= 0; --i) {
2100                 MonoType *t;
2101
2102                 ainfo = cinfo->args + i;
2103
2104                 in = call->args [i];
2105
2106                 if (sig->hasthis && i == 0)
2107                         t = &mono_defaults.object_class->byval_arg;
2108                 else
2109                         t = sig->params [i - sig->hasthis];
2110                 t = mini_get_underlying_type (t);
2111
2112                 switch (ainfo->storage) {
2113                 case ArgInIReg:
2114                         /* Already done */
2115                         break;
2116                 case ArgInFloatSSEReg:
2117                 case ArgInDoubleSSEReg:
2118                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2119                         break;
2120                 case ArgOnStack:
2121                 case ArgValuetypeInReg:
2122                 case ArgValuetypeAddrInIReg:
2123                 case ArgValuetypeAddrOnStack:
2124                 case ArgGSharedVtInReg:
2125                 case ArgGSharedVtOnStack: {
2126                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2127                                 /* Already emitted above */
2128                                 break;
2129                         //FIXME what about ArgGSharedVtOnStack ?
2130                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2131                                 MonoInst *call_inst = (MonoInst*)call;
2132                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2133                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2134                                 break;
2135                         }
2136
2137                         guint32 align;
2138                         guint32 size;
2139
2140                         if (sig->pinvoke)
2141                                 size = mono_type_native_stack_size (t, &align);
2142                         else {
2143                                 /*
2144                                  * Other backends use mono_type_stack_size (), but that
2145                                  * aligns the size to 8, which is larger than the size of
2146                                  * the source, leading to reads of invalid memory if the
2147                                  * source is at the end of address space.
2148                                  */
2149                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2150                         }
2151
2152                         if (size >= 10000) {
2153                                 /* Avoid asserts in emit_memcpy () */
2154                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2155                                 /* Continue normally */
2156                         }
2157
2158                         if (size > 0 || ainfo->pass_empty_struct) {
2159                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2160                                 arg->sreg1 = in->dreg;
2161                                 arg->klass = mono_class_from_mono_type (t);
2162                                 arg->backend.size = size;
2163                                 arg->inst_p0 = call;
2164                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2165                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2166
2167                                 MONO_ADD_INS (cfg->cbb, arg);
2168                         }
2169                         break;
2170                 }
2171                 default:
2172                         g_assert_not_reached ();
2173                 }
2174
2175                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2176                         /* Emit the signature cookie just before the implicit arguments */
2177                         emit_sig_cookie (cfg, call, cinfo);
2178         }
2179
2180         /* Handle the case where there are no implicit arguments */
2181         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2182                 emit_sig_cookie (cfg, call, cinfo);
2183
2184         switch (cinfo->ret.storage) {
2185         case ArgValuetypeInReg:
2186                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2187                         /*
2188                          * Tell the JIT to use a more efficient calling convention: call using
2189                          * OP_CALL, compute the result location after the call, and save the
2190                          * result there.
2191                          */
2192                         call->vret_in_reg = TRUE;
2193                         /*
2194                          * Nullify the instruction computing the vret addr to enable
2195                          * future optimizations.
2196                          */
2197                         if (call->vret_var)
2198                                 NULLIFY_INS (call->vret_var);
2199                 } else {
2200                         if (call->tail_call)
2201                                 NOT_IMPLEMENTED;
2202                         /*
2203                          * The valuetype is in RAX:RDX after the call, need to be copied to
2204                          * the stack. Push the address here, so the call instruction can
2205                          * access it.
2206                          */
2207                         if (!cfg->arch.vret_addr_loc) {
2208                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2209                                 /* Prevent it from being register allocated or optimized away */
2210                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2211                         }
2212
2213                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2214                 }
2215                 break;
2216         case ArgValuetypeAddrInIReg:
2217         case ArgGsharedvtVariableInReg: {
2218                 MonoInst *vtarg;
2219                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2220                 vtarg->sreg1 = call->vret_var->dreg;
2221                 vtarg->dreg = mono_alloc_preg (cfg);
2222                 MONO_ADD_INS (cfg->cbb, vtarg);
2223
2224                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2225                 break;
2226         }
2227         default:
2228                 break;
2229         }
2230
2231         if (cfg->method->save_lmf) {
2232                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2233                 MONO_ADD_INS (cfg->cbb, arg);
2234         }
2235
2236         call->stack_usage = cinfo->stack_usage;
2237 }
2238
2239 void
2240 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2241 {
2242         MonoInst *arg;
2243         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2244         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2245         int size = ins->backend.size;
2246
2247         switch (ainfo->storage) {
2248         case ArgValuetypeInReg: {
2249                 MonoInst *load;
2250                 int part;
2251
2252                 for (part = 0; part < 2; ++part) {
2253                         if (ainfo->pair_storage [part] == ArgNone)
2254                                 continue;
2255
2256                         if (ainfo->pass_empty_struct) {
2257                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2258                                 NEW_ICONST (cfg, load, 0);
2259                         }
2260                         else {
2261                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2262                                 load->inst_basereg = src->dreg;
2263                                 load->inst_offset = part * sizeof(mgreg_t);
2264
2265                                 switch (ainfo->pair_storage [part]) {
2266                                 case ArgInIReg:
2267                                         load->dreg = mono_alloc_ireg (cfg);
2268                                         break;
2269                                 case ArgInDoubleSSEReg:
2270                                 case ArgInFloatSSEReg:
2271                                         load->dreg = mono_alloc_freg (cfg);
2272                                         break;
2273                                 default:
2274                                         g_assert_not_reached ();
2275                                 }
2276                         }
2277
2278                         MONO_ADD_INS (cfg->cbb, load);
2279
2280                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2281                 }
2282                 break;
2283         }
2284         case ArgValuetypeAddrInIReg:
2285         case ArgValuetypeAddrOnStack: {
2286                 MonoInst *vtaddr, *load;
2287
2288                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2289
2290                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2291
2292                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2293                 cfg->has_indirection = TRUE;
2294                 load->inst_p0 = vtaddr;
2295                 vtaddr->flags |= MONO_INST_INDIRECT;
2296                 load->type = STACK_MP;
2297                 load->klass = vtaddr->klass;
2298                 load->dreg = mono_alloc_ireg (cfg);
2299                 MONO_ADD_INS (cfg->cbb, load);
2300                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2301
2302                 if (ainfo->pair_storage [0] == ArgInIReg) {
2303                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2304                         arg->dreg = mono_alloc_ireg (cfg);
2305                         arg->sreg1 = load->dreg;
2306                         arg->inst_imm = 0;
2307                         MONO_ADD_INS (cfg->cbb, arg);
2308                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2309                 } else {
2310                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2311                 }
2312                 break;
2313         }
2314         case ArgGSharedVtInReg:
2315                 /* Pass by addr */
2316                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2317                 break;
2318         case ArgGSharedVtOnStack:
2319                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2320                 break;
2321         default:
2322                 if (size == 8) {
2323                         int dreg = mono_alloc_ireg (cfg);
2324
2325                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2326                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2327                 } else if (size <= 40) {
2328                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2329                 } else {
2330                         // FIXME: Code growth
2331                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2332                 }
2333
2334                 if (cfg->compute_gc_maps) {
2335                         MonoInst *def;
2336                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2337                 }
2338         }
2339 }
2340
2341 void
2342 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2343 {
2344         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2345
2346         if (ret->type == MONO_TYPE_R4) {
2347                 if (COMPILE_LLVM (cfg))
2348                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2349                 else
2350                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2351                 return;
2352         } else if (ret->type == MONO_TYPE_R8) {
2353                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2354                 return;
2355         }
2356
2357         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2358 }
2359
2360 #endif /* DISABLE_JIT */
2361
2362 #define EMIT_COND_BRANCH(ins,cond,sign) \
2363         if (ins->inst_true_bb->native_offset) { \
2364                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2365         } else { \
2366                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2367                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2368             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2369                         x86_branch8 (code, cond, 0, sign); \
2370                 else \
2371                         x86_branch32 (code, cond, 0, sign); \
2372 }
2373
2374 typedef struct {
2375         MonoMethodSignature *sig;
2376         CallInfo *cinfo;
2377 } ArchDynCallInfo;
2378
2379 static gboolean
2380 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2381 {
2382         int i;
2383
2384         switch (cinfo->ret.storage) {
2385         case ArgNone:
2386         case ArgInIReg:
2387         case ArgInFloatSSEReg:
2388         case ArgInDoubleSSEReg:
2389         case ArgValuetypeAddrInIReg:
2390         case ArgValuetypeInReg:
2391                 break;
2392         default:
2393                 return FALSE;
2394         }
2395
2396         for (i = 0; i < cinfo->nargs; ++i) {
2397                 ArgInfo *ainfo = &cinfo->args [i];
2398                 switch (ainfo->storage) {
2399                 case ArgInIReg:
2400                 case ArgInFloatSSEReg:
2401                 case ArgInDoubleSSEReg:
2402                 case ArgValuetypeInReg:
2403                         break;
2404                 case ArgOnStack:
2405                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2406                                 return FALSE;
2407                         break;
2408                 default:
2409                         return FALSE;
2410                 }
2411         }
2412
2413         return TRUE;
2414 }
2415
2416 /*
2417  * mono_arch_dyn_call_prepare:
2418  *
2419  *   Return a pointer to an arch-specific structure which contains information
2420  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2421  * supported for SIG.
2422  * This function is equivalent to ffi_prep_cif in libffi.
2423  */
2424 MonoDynCallInfo*
2425 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2426 {
2427         ArchDynCallInfo *info;
2428         CallInfo *cinfo;
2429
2430         cinfo = get_call_info (NULL, sig);
2431
2432         if (!dyn_call_supported (sig, cinfo)) {
2433                 g_free (cinfo);
2434                 return NULL;
2435         }
2436
2437         info = g_new0 (ArchDynCallInfo, 1);
2438         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2439         info->sig = sig;
2440         info->cinfo = cinfo;
2441
2442         return (MonoDynCallInfo*)info;
2443 }
2444
2445 /*
2446  * mono_arch_dyn_call_free:
2447  *
2448  *   Free a MonoDynCallInfo structure.
2449  */
2450 void
2451 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2452 {
2453         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2454
2455         g_free (ainfo->cinfo);
2456         g_free (ainfo);
2457 }
2458
2459 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2460 #define GREG_TO_PTR(greg) (gpointer)(greg)
2461
2462 /*
2463  * mono_arch_get_start_dyn_call:
2464  *
2465  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2466  * store the result into BUF.
2467  * ARGS should be an array of pointers pointing to the arguments.
2468  * RET should point to a memory buffer large enought to hold the result of the
2469  * call.
2470  * This function should be as fast as possible, any work which does not depend
2471  * on the actual values of the arguments should be done in
2472  * mono_arch_dyn_call_prepare ().
2473  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2474  * libffi.
2475  */
2476 void
2477 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2478 {
2479         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2480         DynCallArgs *p = (DynCallArgs*)buf;
2481         int arg_index, greg, freg, i, pindex;
2482         MonoMethodSignature *sig = dinfo->sig;
2483         int buffer_offset = 0;
2484         static int param_reg_to_index [16];
2485         static gboolean param_reg_to_index_inited;
2486
2487         if (!param_reg_to_index_inited) {
2488                 for (i = 0; i < PARAM_REGS; ++i)
2489                         param_reg_to_index [param_regs [i]] = i;
2490                 mono_memory_barrier ();
2491                 param_reg_to_index_inited = 1;
2492         }
2493
2494         g_assert (buf_len >= sizeof (DynCallArgs));
2495
2496         p->res = 0;
2497         p->ret = ret;
2498
2499         arg_index = 0;
2500         greg = 0;
2501         freg = 0;
2502         pindex = 0;
2503
2504         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2505                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2506                 if (!sig->hasthis)
2507                         pindex = 1;
2508         }
2509
2510         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2511                 p->regs [greg ++] = PTR_TO_GREG(ret);
2512
2513         for (; pindex < sig->param_count; pindex++) {
2514                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2515                 gpointer *arg = args [arg_index ++];
2516                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2517                 int slot;
2518
2519                 if (ainfo->storage == ArgOnStack) {
2520                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2521                 } else {
2522                         slot = param_reg_to_index [ainfo->reg];
2523                 }
2524
2525                 if (t->byref) {
2526                         p->regs [slot] = PTR_TO_GREG(*(arg));
2527                         greg ++;
2528                         continue;
2529                 }
2530
2531                 switch (t->type) {
2532                 case MONO_TYPE_OBJECT:
2533                 case MONO_TYPE_PTR:
2534                 case MONO_TYPE_I:
2535                 case MONO_TYPE_U:
2536 #if !defined(__mono_ilp32__)
2537                 case MONO_TYPE_I8:
2538                 case MONO_TYPE_U8:
2539 #endif
2540                         p->regs [slot] = PTR_TO_GREG(*(arg));
2541                         break;
2542 #if defined(__mono_ilp32__)
2543                 case MONO_TYPE_I8:
2544                 case MONO_TYPE_U8:
2545                         p->regs [slot] = *(guint64*)(arg);
2546                         break;
2547 #endif
2548                 case MONO_TYPE_U1:
2549                         p->regs [slot] = *(guint8*)(arg);
2550                         break;
2551                 case MONO_TYPE_I1:
2552                         p->regs [slot] = *(gint8*)(arg);
2553                         break;
2554                 case MONO_TYPE_I2:
2555                         p->regs [slot] = *(gint16*)(arg);
2556                         break;
2557                 case MONO_TYPE_U2:
2558                         p->regs [slot] = *(guint16*)(arg);
2559                         break;
2560                 case MONO_TYPE_I4:
2561                         p->regs [slot] = *(gint32*)(arg);
2562                         break;
2563                 case MONO_TYPE_U4:
2564                         p->regs [slot] = *(guint32*)(arg);
2565                         break;
2566                 case MONO_TYPE_R4: {
2567                         double d;
2568
2569                         *(float*)&d = *(float*)(arg);
2570                         p->has_fp = 1;
2571                         p->fregs [freg ++] = d;
2572                         break;
2573                 }
2574                 case MONO_TYPE_R8:
2575                         p->has_fp = 1;
2576                         p->fregs [freg ++] = *(double*)(arg);
2577                         break;
2578                 case MONO_TYPE_GENERICINST:
2579                     if (MONO_TYPE_IS_REFERENCE (t)) {
2580                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2581                                 break;
2582                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2583                                         MonoClass *klass = mono_class_from_mono_type (t);
2584                                         guint8 *nullable_buf;
2585                                         int size;
2586
2587                                         size = mono_class_value_size (klass, NULL);
2588                                         nullable_buf = p->buffer + buffer_offset;
2589                                         buffer_offset += size;
2590                                         g_assert (buffer_offset <= 256);
2591
2592                                         /* The argument pointed to by arg is either a boxed vtype or null */
2593                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2594
2595                                         arg = (gpointer*)nullable_buf;
2596                                         /* Fall though */
2597
2598                         } else {
2599                                 /* Fall through */
2600                         }
2601                 case MONO_TYPE_VALUETYPE: {
2602                         switch (ainfo->storage) {
2603                         case ArgValuetypeInReg:
2604                                 for (i = 0; i < 2; ++i) {
2605                                         switch (ainfo->pair_storage [i]) {
2606                                         case ArgNone:
2607                                                 break;
2608                                         case ArgInIReg:
2609                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2610                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2611                                                 break;
2612                                         case ArgInDoubleSSEReg:
2613                                                 p->has_fp = 1;
2614                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2615                                                 break;
2616                                         default:
2617                                                 g_assert_not_reached ();
2618                                                 break;
2619                                         }
2620                                 }
2621                                 break;
2622                         case ArgOnStack:
2623                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2624                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2625                                 break;
2626                         default:
2627                                 g_assert_not_reached ();
2628                                 break;
2629                         }
2630                         break;
2631                 }
2632                 default:
2633                         g_assert_not_reached ();
2634                 }
2635         }
2636 }
2637
2638 /*
2639  * mono_arch_finish_dyn_call:
2640  *
2641  *   Store the result of a dyn call into the return value buffer passed to
2642  * start_dyn_call ().
2643  * This function should be as fast as possible, any work which does not depend
2644  * on the actual values of the arguments should be done in
2645  * mono_arch_dyn_call_prepare ().
2646  */
2647 void
2648 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2649 {
2650         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2651         MonoMethodSignature *sig = dinfo->sig;
2652         DynCallArgs *dargs = (DynCallArgs*)buf;
2653         guint8 *ret = dargs->ret;
2654         mgreg_t res = dargs->res;
2655         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2656         int i;
2657
2658         switch (sig_ret->type) {
2659         case MONO_TYPE_VOID:
2660                 *(gpointer*)ret = NULL;
2661                 break;
2662         case MONO_TYPE_OBJECT:
2663         case MONO_TYPE_I:
2664         case MONO_TYPE_U:
2665         case MONO_TYPE_PTR:
2666                 *(gpointer*)ret = GREG_TO_PTR(res);
2667                 break;
2668         case MONO_TYPE_I1:
2669                 *(gint8*)ret = res;
2670                 break;
2671         case MONO_TYPE_U1:
2672                 *(guint8*)ret = res;
2673                 break;
2674         case MONO_TYPE_I2:
2675                 *(gint16*)ret = res;
2676                 break;
2677         case MONO_TYPE_U2:
2678                 *(guint16*)ret = res;
2679                 break;
2680         case MONO_TYPE_I4:
2681                 *(gint32*)ret = res;
2682                 break;
2683         case MONO_TYPE_U4:
2684                 *(guint32*)ret = res;
2685                 break;
2686         case MONO_TYPE_I8:
2687                 *(gint64*)ret = res;
2688                 break;
2689         case MONO_TYPE_U8:
2690                 *(guint64*)ret = res;
2691                 break;
2692         case MONO_TYPE_R4:
2693                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2694                 break;
2695         case MONO_TYPE_R8:
2696                 *(double*)ret = dargs->fregs [0];
2697                 break;
2698         case MONO_TYPE_GENERICINST:
2699                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2700                         *(gpointer*)ret = GREG_TO_PTR(res);
2701                         break;
2702                 } else {
2703                         /* Fall through */
2704                 }
2705         case MONO_TYPE_VALUETYPE:
2706                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2707                         /* Nothing to do */
2708                 } else {
2709                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2710
2711                         g_assert (ainfo->storage == ArgValuetypeInReg);
2712
2713                         for (i = 0; i < 2; ++i) {
2714                                 switch (ainfo->pair_storage [0]) {
2715                                 case ArgInIReg:
2716                                         ((mgreg_t*)ret)[i] = res;
2717                                         break;
2718                                 case ArgInDoubleSSEReg:
2719                                         ((double*)ret)[i] = dargs->fregs [i];
2720                                         break;
2721                                 case ArgNone:
2722                                         break;
2723                                 default:
2724                                         g_assert_not_reached ();
2725                                         break;
2726                                 }
2727                         }
2728                 }
2729                 break;
2730         default:
2731                 g_assert_not_reached ();
2732         }
2733 }
2734
2735 /* emit an exception if condition is fail */
2736 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2737         do {                                                        \
2738                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2739                 if (tins == NULL) {                                                                             \
2740                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2741                                         MONO_PATCH_INFO_EXC, exc_name);  \
2742                         x86_branch32 (code, cond, 0, signed);               \
2743                 } else {        \
2744                         EMIT_COND_BRANCH (tins, cond, signed);  \
2745                 }                       \
2746         } while (0);
2747
2748 #define EMIT_FPCOMPARE(code) do { \
2749         amd64_fcompp (code); \
2750         amd64_fnstsw (code); \
2751 } while (0);
2752
2753 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2754     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2755         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2756         amd64_ ##op (code); \
2757         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2758         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2759 } while (0);
2760
2761 static guint8*
2762 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2763 {
2764         gboolean no_patch = FALSE;
2765
2766         /*
2767          * FIXME: Add support for thunks
2768          */
2769         {
2770                 gboolean near_call = FALSE;
2771
2772                 /*
2773                  * Indirect calls are expensive so try to make a near call if possible.
2774                  * The caller memory is allocated by the code manager so it is
2775                  * guaranteed to be at a 32 bit offset.
2776                  */
2777
2778                 if (patch_type != MONO_PATCH_INFO_ABS) {
2779                         /* The target is in memory allocated using the code manager */
2780                         near_call = TRUE;
2781
2782                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2783                                 if (((MonoMethod*)data)->klass->image->aot_module)
2784                                         /* The callee might be an AOT method */
2785                                         near_call = FALSE;
2786                                 if (((MonoMethod*)data)->dynamic)
2787                                         /* The target is in malloc-ed memory */
2788                                         near_call = FALSE;
2789                         }
2790
2791                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2792                                 /*
2793                                  * The call might go directly to a native function without
2794                                  * the wrapper.
2795                                  */
2796                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2797                                 if (mi) {
2798                                         gconstpointer target = mono_icall_get_wrapper (mi);
2799                                         if ((((guint64)target) >> 32) != 0)
2800                                                 near_call = FALSE;
2801                                 }
2802                         }
2803                 }
2804                 else {
2805                         MonoJumpInfo *jinfo = NULL;
2806
2807                         if (cfg->abs_patches)
2808                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2809                         if (jinfo) {
2810                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2811                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2812                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2813                                                 near_call = TRUE;
2814                                         no_patch = TRUE;
2815                                 } else {
2816                                         /*
2817                                          * This is not really an optimization, but required because the
2818                                          * generic class init trampolines use R11 to pass the vtable.
2819                                          */
2820                                         near_call = TRUE;
2821                                 }
2822                         } else {
2823                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2824                                 if (info) {
2825                                         if (info->func == info->wrapper) {
2826                                                 /* No wrapper */
2827                                                 if ((((guint64)info->func) >> 32) == 0)
2828                                                         near_call = TRUE;
2829                                         }
2830                                         else {
2831                                                 /* See the comment in mono_codegen () */
2832                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2833                                                         near_call = TRUE;
2834                                         }
2835                                 }
2836                                 else if ((((guint64)data) >> 32) == 0) {
2837                                         near_call = TRUE;
2838                                         no_patch = TRUE;
2839                                 }
2840                         }
2841                 }
2842
2843                 if (cfg->method->dynamic)
2844                         /* These methods are allocated using malloc */
2845                         near_call = FALSE;
2846
2847 #ifdef MONO_ARCH_NOMAP32BIT
2848                 near_call = FALSE;
2849 #endif
2850                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2851                 if (optimize_for_xen)
2852                         near_call = FALSE;
2853
2854                 if (cfg->compile_aot) {
2855                         near_call = TRUE;
2856                         no_patch = TRUE;
2857                 }
2858
2859                 if (near_call) {
2860                         /*
2861                          * Align the call displacement to an address divisible by 4 so it does
2862                          * not span cache lines. This is required for code patching to work on SMP
2863                          * systems.
2864                          */
2865                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2866                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2867                                 amd64_padding (code, pad_size);
2868                         }
2869                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2870                         amd64_call_code (code, 0);
2871                 }
2872                 else {
2873                         if (!no_patch && ((guint32)(code + 2 - cfg->native_code) % 8) != 0) {
2874                                 guint32 pad_size = 8 - ((guint32)(code + 2 - cfg->native_code) % 8);
2875                                 amd64_padding (code, pad_size);
2876                                 g_assert ((guint64)(code + 2 - cfg->native_code) % 8 == 0);
2877                         }
2878                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2879                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2880                         amd64_call_reg (code, GP_SCRATCH_REG);
2881                 }
2882         }
2883
2884         return code;
2885 }
2886
2887 static inline guint8*
2888 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2889 {
2890 #ifdef TARGET_WIN32
2891         if (win64_adjust_stack)
2892                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2893 #endif
2894         code = emit_call_body (cfg, code, patch_type, data);
2895 #ifdef TARGET_WIN32
2896         if (win64_adjust_stack)
2897                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2898 #endif
2899
2900         return code;
2901 }
2902
2903 static inline int
2904 store_membase_imm_to_store_membase_reg (int opcode)
2905 {
2906         switch (opcode) {
2907         case OP_STORE_MEMBASE_IMM:
2908                 return OP_STORE_MEMBASE_REG;
2909         case OP_STOREI4_MEMBASE_IMM:
2910                 return OP_STOREI4_MEMBASE_REG;
2911         case OP_STOREI8_MEMBASE_IMM:
2912                 return OP_STOREI8_MEMBASE_REG;
2913         }
2914
2915         return -1;
2916 }
2917
2918 #ifndef DISABLE_JIT
2919
2920 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2921
2922 /*
2923  * mono_arch_peephole_pass_1:
2924  *
2925  *   Perform peephole opts which should/can be performed before local regalloc
2926  */
2927 void
2928 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2929 {
2930         MonoInst *ins, *n;
2931
2932         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2933                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2934
2935                 switch (ins->opcode) {
2936                 case OP_ADD_IMM:
2937                 case OP_IADD_IMM:
2938                 case OP_LADD_IMM:
2939                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2940                                 /*
2941                                  * X86_LEA is like ADD, but doesn't have the
2942                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2943                                  * its operand to 64 bit.
2944                                  */
2945                                 ins->opcode = OP_X86_LEA_MEMBASE;
2946                                 ins->inst_basereg = ins->sreg1;
2947                         }
2948                         break;
2949                 case OP_LXOR:
2950                 case OP_IXOR:
2951                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2952                                 MonoInst *ins2;
2953
2954                                 /*
2955                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2956                                  * the latter has length 2-3 instead of 6 (reverse constant
2957                                  * propagation). These instruction sequences are very common
2958                                  * in the initlocals bblock.
2959                                  */
2960                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2961                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2962                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2963                                                 ins2->sreg1 = ins->dreg;
2964                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2965                                                 /* Continue */
2966                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2967                                                 NULLIFY_INS (ins2);
2968                                                 /* Continue */
2969                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2970                                                 /* Continue */
2971                                         } else {
2972                                                 break;
2973                                         }
2974                                 }
2975                         }
2976                         break;
2977                 case OP_COMPARE_IMM:
2978                 case OP_LCOMPARE_IMM:
2979                         /* OP_COMPARE_IMM (reg, 0)
2980                          * -->
2981                          * OP_AMD64_TEST_NULL (reg)
2982                          */
2983                         if (!ins->inst_imm)
2984                                 ins->opcode = OP_AMD64_TEST_NULL;
2985                         break;
2986                 case OP_ICOMPARE_IMM:
2987                         if (!ins->inst_imm)
2988                                 ins->opcode = OP_X86_TEST_NULL;
2989                         break;
2990                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2991                         /*
2992                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2993                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2994                          * -->
2995                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2996                          * OP_COMPARE_IMM reg, imm
2997                          *
2998                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2999                          */
3000                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3001                             ins->inst_basereg == last_ins->inst_destbasereg &&
3002                             ins->inst_offset == last_ins->inst_offset) {
3003                                         ins->opcode = OP_ICOMPARE_IMM;
3004                                         ins->sreg1 = last_ins->sreg1;
3005
3006                                         /* check if we can remove cmp reg,0 with test null */
3007                                         if (!ins->inst_imm)
3008                                                 ins->opcode = OP_X86_TEST_NULL;
3009                                 }
3010
3011                         break;
3012                 }
3013
3014                 mono_peephole_ins (bb, ins);
3015         }
3016 }
3017
3018 void
3019 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3020 {
3021         MonoInst *ins, *n;
3022
3023         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3024                 switch (ins->opcode) {
3025                 case OP_ICONST:
3026                 case OP_I8CONST: {
3027                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3028                         /* reg = 0 -> XOR (reg, reg) */
3029                         /* XOR sets cflags on x86, so we cant do it always */
3030                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3031                                 ins->opcode = OP_LXOR;
3032                                 ins->sreg1 = ins->dreg;
3033                                 ins->sreg2 = ins->dreg;
3034                                 /* Fall through */
3035                         } else {
3036                                 break;
3037                         }
3038                 }
3039                 case OP_LXOR:
3040                         /*
3041                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3042                          * 0 result into 64 bits.
3043                          */
3044                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3045                                 ins->opcode = OP_IXOR;
3046                         }
3047                         /* Fall through */
3048                 case OP_IXOR:
3049                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3050                                 MonoInst *ins2;
3051
3052                                 /*
3053                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3054                                  * the latter has length 2-3 instead of 6 (reverse constant
3055                                  * propagation). These instruction sequences are very common
3056                                  * in the initlocals bblock.
3057                                  */
3058                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3059                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3060                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3061                                                 ins2->sreg1 = ins->dreg;
3062                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3063                                                 /* Continue */
3064                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3065                                                 NULLIFY_INS (ins2);
3066                                                 /* Continue */
3067                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3068                                                 /* Continue */
3069                                         } else {
3070                                                 break;
3071                                         }
3072                                 }
3073                         }
3074                         break;
3075                 case OP_IADD_IMM:
3076                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3077                                 ins->opcode = OP_X86_INC_REG;
3078                         break;
3079                 case OP_ISUB_IMM:
3080                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3081                                 ins->opcode = OP_X86_DEC_REG;
3082                         break;
3083                 }
3084
3085                 mono_peephole_ins (bb, ins);
3086         }
3087 }
3088
3089 #define NEW_INS(cfg,ins,dest,op) do {   \
3090                 MONO_INST_NEW ((cfg), (dest), (op)); \
3091         (dest)->cil_code = (ins)->cil_code; \
3092         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3093         } while (0)
3094
3095 /*
3096  * mono_arch_lowering_pass:
3097  *
3098  *  Converts complex opcodes into simpler ones so that each IR instruction
3099  * corresponds to one machine instruction.
3100  */
3101 void
3102 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3103 {
3104         MonoInst *ins, *n, *temp;
3105
3106         /*
3107          * FIXME: Need to add more instructions, but the current machine
3108          * description can't model some parts of the composite instructions like
3109          * cdq.
3110          */
3111         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3112                 switch (ins->opcode) {
3113                 case OP_DIV_IMM:
3114                 case OP_REM_IMM:
3115                 case OP_IDIV_IMM:
3116                 case OP_IDIV_UN_IMM:
3117                 case OP_IREM_UN_IMM:
3118                 case OP_LREM_IMM:
3119                 case OP_IREM_IMM:
3120                         mono_decompose_op_imm (cfg, bb, ins);
3121                         break;
3122                 case OP_COMPARE_IMM:
3123                 case OP_LCOMPARE_IMM:
3124                         if (!amd64_use_imm32 (ins->inst_imm)) {
3125                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3126                                 temp->inst_c0 = ins->inst_imm;
3127                                 temp->dreg = mono_alloc_ireg (cfg);
3128                                 ins->opcode = OP_COMPARE;
3129                                 ins->sreg2 = temp->dreg;
3130                         }
3131                         break;
3132 #ifndef __mono_ilp32__
3133                 case OP_LOAD_MEMBASE:
3134 #endif
3135                 case OP_LOADI8_MEMBASE:
3136                 /*  Don't generate memindex opcodes (to simplify */
3137                 /*  read sandboxing) */
3138                         if (!amd64_use_imm32 (ins->inst_offset)) {
3139                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3140                                 temp->inst_c0 = ins->inst_offset;
3141                                 temp->dreg = mono_alloc_ireg (cfg);
3142                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3143                                 ins->inst_indexreg = temp->dreg;
3144                         }
3145                         break;
3146 #ifndef __mono_ilp32__
3147                 case OP_STORE_MEMBASE_IMM:
3148 #endif
3149                 case OP_STOREI8_MEMBASE_IMM:
3150                         if (!amd64_use_imm32 (ins->inst_imm)) {
3151                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3152                                 temp->inst_c0 = ins->inst_imm;
3153                                 temp->dreg = mono_alloc_ireg (cfg);
3154                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3155                                 ins->sreg1 = temp->dreg;
3156                         }
3157                         break;
3158 #ifdef MONO_ARCH_SIMD_INTRINSICS
3159                 case OP_EXPAND_I1: {
3160                                 int temp_reg1 = mono_alloc_ireg (cfg);
3161                                 int temp_reg2 = mono_alloc_ireg (cfg);
3162                                 int original_reg = ins->sreg1;
3163
3164                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3165                                 temp->sreg1 = original_reg;
3166                                 temp->dreg = temp_reg1;
3167
3168                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3169                                 temp->sreg1 = temp_reg1;
3170                                 temp->dreg = temp_reg2;
3171                                 temp->inst_imm = 8;
3172
3173                                 NEW_INS (cfg, ins, temp, OP_LOR);
3174                                 temp->sreg1 = temp->dreg = temp_reg2;
3175                                 temp->sreg2 = temp_reg1;
3176
3177                                 ins->opcode = OP_EXPAND_I2;
3178                                 ins->sreg1 = temp_reg2;
3179                         }
3180                         break;
3181 #endif
3182                 default:
3183                         break;
3184                 }
3185         }
3186
3187         bb->max_vreg = cfg->next_vreg;
3188 }
3189
3190 static const int
3191 branch_cc_table [] = {
3192         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3193         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3194         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3195 };
3196
3197 /* Maps CMP_... constants to X86_CC_... constants */
3198 static const int
3199 cc_table [] = {
3200         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3201         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3202 };
3203
3204 static const int
3205 cc_signed_table [] = {
3206         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3207         FALSE, FALSE, FALSE, FALSE
3208 };
3209
3210 /*#include "cprop.c"*/
3211
3212 static unsigned char*
3213 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3214 {
3215         if (size == 8)
3216                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3217         else
3218                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3219
3220         if (size == 1)
3221                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3222         else if (size == 2)
3223                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3224         return code;
3225 }
3226
3227 static unsigned char*
3228 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3229 {
3230         int sreg = tree->sreg1;
3231         int need_touch = FALSE;
3232
3233 #if defined(TARGET_WIN32)
3234         need_touch = TRUE;
3235 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3236         if (!(tree->flags & MONO_INST_INIT))
3237                 need_touch = TRUE;
3238 #endif
3239
3240         if (need_touch) {
3241                 guint8* br[5];
3242
3243                 /*
3244                  * Under Windows:
3245                  * If requested stack size is larger than one page,
3246                  * perform stack-touch operation
3247                  */
3248                 /*
3249                  * Generate stack probe code.
3250                  * Under Windows, it is necessary to allocate one page at a time,
3251                  * "touching" stack after each successful sub-allocation. This is
3252                  * because of the way stack growth is implemented - there is a
3253                  * guard page before the lowest stack page that is currently commited.
3254                  * Stack normally grows sequentially so OS traps access to the
3255                  * guard page and commits more pages when needed.
3256                  */
3257                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3258                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3259
3260                 br[2] = code; /* loop */
3261                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3262                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3263                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3264                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3265                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3266                 amd64_patch (br[3], br[2]);
3267                 amd64_test_reg_reg (code, sreg, sreg);
3268                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3269                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3270
3271                 br[1] = code; x86_jump8 (code, 0);
3272
3273                 amd64_patch (br[0], code);
3274                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3275                 amd64_patch (br[1], code);
3276                 amd64_patch (br[4], code);
3277         }
3278         else
3279                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3280
3281         if (tree->flags & MONO_INST_INIT) {
3282                 int offset = 0;
3283                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3284                         amd64_push_reg (code, AMD64_RAX);
3285                         offset += 8;
3286                 }
3287                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3288                         amd64_push_reg (code, AMD64_RCX);
3289                         offset += 8;
3290                 }
3291                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3292                         amd64_push_reg (code, AMD64_RDI);
3293                         offset += 8;
3294                 }
3295
3296                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3297                 if (sreg != AMD64_RCX)
3298                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3299                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3300
3301                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3302                 if (cfg->param_area)
3303                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3304                 amd64_cld (code);
3305                 amd64_prefix (code, X86_REP_PREFIX);
3306                 amd64_stosl (code);
3307
3308                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3309                         amd64_pop_reg (code, AMD64_RDI);
3310                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3311                         amd64_pop_reg (code, AMD64_RCX);
3312                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3313                         amd64_pop_reg (code, AMD64_RAX);
3314         }
3315         return code;
3316 }
3317
3318 static guint8*
3319 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3320 {
3321         CallInfo *cinfo;
3322         guint32 quad;
3323
3324         /* Move return value to the target register */
3325         /* FIXME: do this in the local reg allocator */
3326         switch (ins->opcode) {
3327         case OP_CALL:
3328         case OP_CALL_REG:
3329         case OP_CALL_MEMBASE:
3330         case OP_LCALL:
3331         case OP_LCALL_REG:
3332         case OP_LCALL_MEMBASE:
3333                 g_assert (ins->dreg == AMD64_RAX);
3334                 break;
3335         case OP_FCALL:
3336         case OP_FCALL_REG:
3337         case OP_FCALL_MEMBASE: {
3338                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3339                 if (rtype->type == MONO_TYPE_R4) {
3340                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3341                 }
3342                 else {
3343                         if (ins->dreg != AMD64_XMM0)
3344                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3345                 }
3346                 break;
3347         }
3348         case OP_RCALL:
3349         case OP_RCALL_REG:
3350         case OP_RCALL_MEMBASE:
3351                 if (ins->dreg != AMD64_XMM0)
3352                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3353                 break;
3354         case OP_VCALL:
3355         case OP_VCALL_REG:
3356         case OP_VCALL_MEMBASE:
3357         case OP_VCALL2:
3358         case OP_VCALL2_REG:
3359         case OP_VCALL2_MEMBASE:
3360                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3361                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3362                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3363
3364                         /* Load the destination address */
3365                         g_assert (loc->opcode == OP_REGOFFSET);
3366                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3367
3368                         for (quad = 0; quad < 2; quad ++) {
3369                                 switch (cinfo->ret.pair_storage [quad]) {
3370                                 case ArgInIReg:
3371                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3372                                         break;
3373                                 case ArgInFloatSSEReg:
3374                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3375                                         break;
3376                                 case ArgInDoubleSSEReg:
3377                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3378                                         break;
3379                                 case ArgNone:
3380                                         break;
3381                                 default:
3382                                         NOT_IMPLEMENTED;
3383                                 }
3384                         }
3385                 }
3386                 break;
3387         }
3388
3389         return code;
3390 }
3391
3392 #endif /* DISABLE_JIT */
3393
3394 #ifdef TARGET_MACH
3395 static int tls_gs_offset;
3396 #endif
3397
3398 gboolean
3399 mono_arch_have_fast_tls (void)
3400 {
3401 #ifdef TARGET_MACH
3402         static gboolean have_fast_tls = FALSE;
3403         static gboolean inited = FALSE;
3404         guint8 *ins;
3405
3406         if (mini_get_debug_options ()->use_fallback_tls)
3407                 return FALSE;
3408
3409         if (inited)
3410                 return have_fast_tls;
3411
3412         ins = (guint8*)pthread_getspecific;
3413
3414         /*
3415          * We're looking for these two instructions:
3416          *
3417          * mov    %gs:[offset](,%rdi,8),%rax
3418          * retq
3419          */
3420         have_fast_tls = ins [0] == 0x65 &&
3421                        ins [1] == 0x48 &&
3422                        ins [2] == 0x8b &&
3423                        ins [3] == 0x04 &&
3424                        ins [4] == 0xfd &&
3425                        ins [6] == 0x00 &&
3426                        ins [7] == 0x00 &&
3427                        ins [8] == 0x00 &&
3428                        ins [9] == 0xc3;
3429
3430         tls_gs_offset = ins[5];
3431
3432         /*
3433          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3434          * For that version we're looking for these instructions:
3435          *
3436          * pushq  %rbp
3437          * movq   %rsp, %rbp
3438          * mov    %gs:[offset](,%rdi,8),%rax
3439          * popq   %rbp
3440          * retq
3441          */
3442         if (!have_fast_tls) {
3443                 have_fast_tls = ins [0] == 0x55 &&
3444                                ins [1] == 0x48 &&
3445                                ins [2] == 0x89 &&
3446                                ins [3] == 0xe5 &&
3447                                ins [4] == 0x65 &&
3448                                ins [5] == 0x48 &&
3449                                ins [6] == 0x8b &&
3450                                ins [7] == 0x04 &&
3451                                ins [8] == 0xfd &&
3452                                ins [10] == 0x00 &&
3453                                ins [11] == 0x00 &&
3454                                ins [12] == 0x00 &&
3455                                ins [13] == 0x5d &&
3456                                ins [14] == 0xc3;
3457
3458                 tls_gs_offset = ins[9];
3459         }
3460         inited = TRUE;
3461
3462         return have_fast_tls;
3463 #elif defined(TARGET_ANDROID)
3464         return FALSE;
3465 #else
3466         if (mini_get_debug_options ()->use_fallback_tls)
3467                 return FALSE;
3468         return TRUE;
3469 #endif
3470 }
3471
3472 int
3473 mono_amd64_get_tls_gs_offset (void)
3474 {
3475 #ifdef TARGET_OSX
3476         return tls_gs_offset;
3477 #else
3478         g_assert_not_reached ();
3479         return -1;
3480 #endif
3481 }
3482
3483 /*
3484  * \param code buffer to store code to
3485  * \param dreg hard register where to place the result
3486  * \param tls_offset offset info
3487  * \return a pointer to the end of the stored code
3488  *
3489  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3490  * the dreg register the item in the thread local storage identified
3491  * by tls_offset.
3492  */
3493 static guint8*
3494 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3495 {
3496 #ifdef TARGET_WIN32
3497         if (tls_offset < 64) {
3498                 x86_prefix (code, X86_GS_PREFIX);
3499                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3500         } else {
3501                 guint8 *buf [16];
3502
3503                 g_assert (tls_offset < 0x440);
3504                 /* Load TEB->TlsExpansionSlots */
3505                 x86_prefix (code, X86_GS_PREFIX);
3506                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3507                 amd64_test_reg_reg (code, dreg, dreg);
3508                 buf [0] = code;
3509                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3510                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3511                 amd64_patch (buf [0], code);
3512         }
3513 #elif defined(TARGET_MACH)
3514         x86_prefix (code, X86_GS_PREFIX);
3515         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3516 #else
3517         if (optimize_for_xen) {
3518                 x86_prefix (code, X86_FS_PREFIX);
3519                 amd64_mov_reg_mem (code, dreg, 0, 8);
3520                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3521         } else {
3522                 x86_prefix (code, X86_FS_PREFIX);
3523                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3524         }
3525 #endif
3526         return code;
3527 }
3528
3529 static guint8*
3530 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3531 {
3532 #ifdef TARGET_WIN32
3533         g_assert_not_reached ();
3534 #elif defined(TARGET_MACH)
3535         x86_prefix (code, X86_GS_PREFIX);
3536         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3537 #else
3538         g_assert (!optimize_for_xen);
3539         x86_prefix (code, X86_FS_PREFIX);
3540         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3541 #endif
3542         return code;
3543 }
3544
3545 /*
3546  * emit_setup_lmf:
3547  *
3548  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3549  */
3550 static guint8*
3551 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3552 {
3553         /*
3554          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3555          */
3556         /*
3557          * sp is saved right before calls but we need to save it here too so
3558          * async stack walks would work.
3559          */
3560         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3561         /* Save rbp */
3562         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3563         if (cfg->arch.omit_fp && cfa_offset != -1)
3564                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3565
3566         /* These can't contain refs */
3567         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3568         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3569         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3570         /* These are handled automatically by the stack marking code */
3571         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3572
3573         return code;
3574 }
3575
3576 #ifdef TARGET_WIN32
3577
3578 #define TEB_LAST_ERROR_OFFSET 0x068
3579
3580 static guint8*
3581 emit_get_last_error (guint8* code, int dreg)
3582 {
3583         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3584         x86_prefix (code, X86_GS_PREFIX);
3585         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3586
3587         return code;
3588 }
3589
3590 #else
3591
3592 static guint8*
3593 emit_get_last_error (guint8* code, int dreg)
3594 {
3595         g_assert_not_reached ();
3596 }
3597
3598 #endif
3599
3600 /* benchmark and set based on cpu */
3601 #define LOOP_ALIGNMENT 8
3602 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3603
3604 #ifndef DISABLE_JIT
3605 void
3606 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3607 {
3608         MonoInst *ins;
3609         MonoCallInst *call;
3610         guint offset;
3611         guint8 *code = cfg->native_code + cfg->code_len;
3612         int max_len;
3613
3614         /* Fix max_offset estimate for each successor bb */
3615         if (cfg->opt & MONO_OPT_BRANCH) {
3616                 int current_offset = cfg->code_len;
3617                 MonoBasicBlock *current_bb;
3618                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3619                         current_bb->max_offset = current_offset;
3620                         current_offset += current_bb->max_length;
3621                 }
3622         }
3623
3624         if (cfg->opt & MONO_OPT_LOOP) {
3625                 int pad, align = LOOP_ALIGNMENT;
3626                 /* set alignment depending on cpu */
3627                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3628                         pad = align - pad;
3629                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3630                         amd64_padding (code, pad);
3631                         cfg->code_len += pad;
3632                         bb->native_offset = cfg->code_len;
3633                 }
3634         }
3635
3636         if (cfg->verbose_level > 2)
3637                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3638
3639         offset = code - cfg->native_code;
3640
3641         mono_debug_open_block (cfg, bb, offset);
3642
3643     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3644                 x86_breakpoint (code);
3645
3646         MONO_BB_FOR_EACH_INS (bb, ins) {
3647                 offset = code - cfg->native_code;
3648
3649                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3650
3651 #define EXTRA_CODE_SPACE (16)
3652
3653                 if (G_UNLIKELY ((offset + max_len + EXTRA_CODE_SPACE) > cfg->code_size)) {
3654                         cfg->code_size *= 2;
3655                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3656                         code = cfg->native_code + offset;
3657                         cfg->stat_code_reallocs++;
3658                 }
3659
3660                 if (cfg->debug_info)
3661                         mono_debug_record_line_number (cfg, ins, offset);
3662
3663                 switch (ins->opcode) {
3664                 case OP_BIGMUL:
3665                         amd64_mul_reg (code, ins->sreg2, TRUE);
3666                         break;
3667                 case OP_BIGMUL_UN:
3668                         amd64_mul_reg (code, ins->sreg2, FALSE);
3669                         break;
3670                 case OP_X86_SETEQ_MEMBASE:
3671                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3672                         break;
3673                 case OP_STOREI1_MEMBASE_IMM:
3674                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3675                         break;
3676                 case OP_STOREI2_MEMBASE_IMM:
3677                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3678                         break;
3679                 case OP_STOREI4_MEMBASE_IMM:
3680                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3681                         break;
3682                 case OP_STOREI1_MEMBASE_REG:
3683                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3684                         break;
3685                 case OP_STOREI2_MEMBASE_REG:
3686                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3687                         break;
3688                 /* In AMD64 NaCl, pointers are 4 bytes, */
3689                 /*  so STORE_* != STOREI8_*. Likewise below. */
3690                 case OP_STORE_MEMBASE_REG:
3691                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3692                         break;
3693                 case OP_STOREI8_MEMBASE_REG:
3694                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3695                         break;
3696                 case OP_STOREI4_MEMBASE_REG:
3697                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3698                         break;
3699                 case OP_STORE_MEMBASE_IMM:
3700                         /* In NaCl, this could be a PCONST type, which could */
3701                         /* mean a pointer type was copied directly into the  */
3702                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3703                         /* the value would be 0x00000000FFFFFFFF which is    */
3704                         /* not proper for an imm32 unless you cast it.       */
3705                         g_assert (amd64_is_imm32 (ins->inst_imm));
3706                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3707                         break;
3708                 case OP_STOREI8_MEMBASE_IMM:
3709                         g_assert (amd64_is_imm32 (ins->inst_imm));
3710                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3711                         break;
3712                 case OP_LOAD_MEM:
3713 #ifdef __mono_ilp32__
3714                         /* In ILP32, pointers are 4 bytes, so separate these */
3715                         /* cases, use literal 8 below where we really want 8 */
3716                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3717                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3718                         break;
3719 #endif
3720                 case OP_LOADI8_MEM:
3721                         // FIXME: Decompose this earlier
3722                         if (amd64_use_imm32 (ins->inst_imm))
3723                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3724                         else {
3725                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3726                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3727                         }
3728                         break;
3729                 case OP_LOADI4_MEM:
3730                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3731                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3732                         break;
3733                 case OP_LOADU4_MEM:
3734                         // FIXME: Decompose this earlier
3735                         if (amd64_use_imm32 (ins->inst_imm))
3736                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3737                         else {
3738                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3739                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3740                         }
3741                         break;
3742                 case OP_LOADU1_MEM:
3743                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3744                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3745                         break;
3746                 case OP_LOADU2_MEM:
3747                         /* For NaCl, pointers are 4 bytes, so separate these */
3748                         /* cases, use literal 8 below where we really want 8 */
3749                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3750                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3751                         break;
3752                 case OP_LOAD_MEMBASE:
3753                         g_assert (amd64_is_imm32 (ins->inst_offset));
3754                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3755                         break;
3756                 case OP_LOADI8_MEMBASE:
3757                         /* Use literal 8 instead of sizeof pointer or */
3758                         /* register, we really want 8 for this opcode */
3759                         g_assert (amd64_is_imm32 (ins->inst_offset));
3760                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3761                         break;
3762                 case OP_LOADI4_MEMBASE:
3763                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3764                         break;
3765                 case OP_LOADU4_MEMBASE:
3766                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3767                         break;
3768                 case OP_LOADU1_MEMBASE:
3769                         /* The cpu zero extends the result into 64 bits */
3770                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3771                         break;
3772                 case OP_LOADI1_MEMBASE:
3773                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3774                         break;
3775                 case OP_LOADU2_MEMBASE:
3776                         /* The cpu zero extends the result into 64 bits */
3777                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3778                         break;
3779                 case OP_LOADI2_MEMBASE:
3780                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3781                         break;
3782                 case OP_AMD64_LOADI8_MEMINDEX:
3783                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3784                         break;
3785                 case OP_LCONV_TO_I1:
3786                 case OP_ICONV_TO_I1:
3787                 case OP_SEXT_I1:
3788                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3789                         break;
3790                 case OP_LCONV_TO_I2:
3791                 case OP_ICONV_TO_I2:
3792                 case OP_SEXT_I2:
3793                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3794                         break;
3795                 case OP_LCONV_TO_U1:
3796                 case OP_ICONV_TO_U1:
3797                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3798                         break;
3799                 case OP_LCONV_TO_U2:
3800                 case OP_ICONV_TO_U2:
3801                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3802                         break;
3803                 case OP_ZEXT_I4:
3804                         /* Clean out the upper word */
3805                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3806                         break;
3807                 case OP_SEXT_I4:
3808                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3809                         break;
3810                 case OP_COMPARE:
3811                 case OP_LCOMPARE:
3812                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3813                         break;
3814                 case OP_COMPARE_IMM:
3815 #if defined(__mono_ilp32__)
3816                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3817                         g_assert (amd64_is_imm32 (ins->inst_imm));
3818                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3819                         break;
3820 #endif
3821                 case OP_LCOMPARE_IMM:
3822                         g_assert (amd64_is_imm32 (ins->inst_imm));
3823                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3824                         break;
3825                 case OP_X86_COMPARE_REG_MEMBASE:
3826                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3827                         break;
3828                 case OP_X86_TEST_NULL:
3829                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3830                         break;
3831                 case OP_AMD64_TEST_NULL:
3832                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3833                         break;
3834
3835                 case OP_X86_ADD_REG_MEMBASE:
3836                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3837                         break;
3838                 case OP_X86_SUB_REG_MEMBASE:
3839                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3840                         break;
3841                 case OP_X86_AND_REG_MEMBASE:
3842                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3843                         break;
3844                 case OP_X86_OR_REG_MEMBASE:
3845                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3846                         break;
3847                 case OP_X86_XOR_REG_MEMBASE:
3848                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3849                         break;
3850
3851                 case OP_X86_ADD_MEMBASE_IMM:
3852                         /* FIXME: Make a 64 version too */
3853                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3854                         break;
3855                 case OP_X86_SUB_MEMBASE_IMM:
3856                         g_assert (amd64_is_imm32 (ins->inst_imm));
3857                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3858                         break;
3859                 case OP_X86_AND_MEMBASE_IMM:
3860                         g_assert (amd64_is_imm32 (ins->inst_imm));
3861                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3862                         break;
3863                 case OP_X86_OR_MEMBASE_IMM:
3864                         g_assert (amd64_is_imm32 (ins->inst_imm));
3865                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3866                         break;
3867                 case OP_X86_XOR_MEMBASE_IMM:
3868                         g_assert (amd64_is_imm32 (ins->inst_imm));
3869                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3870                         break;
3871                 case OP_X86_ADD_MEMBASE_REG:
3872                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3873                         break;
3874                 case OP_X86_SUB_MEMBASE_REG:
3875                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3876                         break;
3877                 case OP_X86_AND_MEMBASE_REG:
3878                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3879                         break;
3880                 case OP_X86_OR_MEMBASE_REG:
3881                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3882                         break;
3883                 case OP_X86_XOR_MEMBASE_REG:
3884                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3885                         break;
3886                 case OP_X86_INC_MEMBASE:
3887                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3888                         break;
3889                 case OP_X86_INC_REG:
3890                         amd64_inc_reg_size (code, ins->dreg, 4);
3891                         break;
3892                 case OP_X86_DEC_MEMBASE:
3893                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3894                         break;
3895                 case OP_X86_DEC_REG:
3896                         amd64_dec_reg_size (code, ins->dreg, 4);
3897                         break;
3898                 case OP_X86_MUL_REG_MEMBASE:
3899                 case OP_X86_MUL_MEMBASE_REG:
3900                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3901                         break;
3902                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3903                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3904                         break;
3905                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3906                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3907                         break;
3908                 case OP_AMD64_COMPARE_MEMBASE_REG:
3909                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3910                         break;
3911                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3912                         g_assert (amd64_is_imm32 (ins->inst_imm));
3913                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3914                         break;
3915                 case OP_X86_COMPARE_MEMBASE8_IMM:
3916                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3917                         break;
3918                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3919                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3920                         break;
3921                 case OP_AMD64_COMPARE_REG_MEMBASE:
3922                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3923                         break;
3924
3925                 case OP_AMD64_ADD_REG_MEMBASE:
3926                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3927                         break;
3928                 case OP_AMD64_SUB_REG_MEMBASE:
3929                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3930                         break;
3931                 case OP_AMD64_AND_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3933                         break;
3934                 case OP_AMD64_OR_REG_MEMBASE:
3935                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3936                         break;
3937                 case OP_AMD64_XOR_REG_MEMBASE:
3938                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3939                         break;
3940
3941                 case OP_AMD64_ADD_MEMBASE_REG:
3942                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3943                         break;
3944                 case OP_AMD64_SUB_MEMBASE_REG:
3945                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3946                         break;
3947                 case OP_AMD64_AND_MEMBASE_REG:
3948                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3949                         break;
3950                 case OP_AMD64_OR_MEMBASE_REG:
3951                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3952                         break;
3953                 case OP_AMD64_XOR_MEMBASE_REG:
3954                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3955                         break;
3956
3957                 case OP_AMD64_ADD_MEMBASE_IMM:
3958                         g_assert (amd64_is_imm32 (ins->inst_imm));
3959                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3960                         break;
3961                 case OP_AMD64_SUB_MEMBASE_IMM:
3962                         g_assert (amd64_is_imm32 (ins->inst_imm));
3963                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3964                         break;
3965                 case OP_AMD64_AND_MEMBASE_IMM:
3966                         g_assert (amd64_is_imm32 (ins->inst_imm));
3967                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3968                         break;
3969                 case OP_AMD64_OR_MEMBASE_IMM:
3970                         g_assert (amd64_is_imm32 (ins->inst_imm));
3971                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3972                         break;
3973                 case OP_AMD64_XOR_MEMBASE_IMM:
3974                         g_assert (amd64_is_imm32 (ins->inst_imm));
3975                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3976                         break;
3977
3978                 case OP_BREAK:
3979                         amd64_breakpoint (code);
3980                         break;
3981                 case OP_RELAXED_NOP:
3982                         x86_prefix (code, X86_REP_PREFIX);
3983                         x86_nop (code);
3984                         break;
3985                 case OP_HARD_NOP:
3986                         x86_nop (code);
3987                         break;
3988                 case OP_NOP:
3989                 case OP_DUMMY_USE:
3990                 case OP_DUMMY_STORE:
3991                 case OP_DUMMY_ICONST:
3992                 case OP_DUMMY_R8CONST:
3993                 case OP_NOT_REACHED:
3994                 case OP_NOT_NULL:
3995                         break;
3996                 case OP_IL_SEQ_POINT:
3997                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3998                         break;
3999                 case OP_SEQ_POINT: {
4000                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4001                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4002                                 guint8 *label;
4003
4004                                 /* Load ss_tramp_var */
4005                                 /* This is equal to &ss_trampoline */
4006                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4007                                 /* Load the trampoline address */
4008                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4009                                 /* Call it if it is non-null */
4010                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4011                                 label = code;
4012                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4013                                 amd64_call_reg (code, AMD64_R11);
4014                                 amd64_patch (label, code);
4015                         }
4016
4017                         /*
4018                          * This is the address which is saved in seq points,
4019                          */
4020                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4021
4022                         if (cfg->compile_aot) {
4023                                 guint32 offset = code - cfg->native_code;
4024                                 guint32 val;
4025                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4026                                 guint8 *label;
4027
4028                                 /* Load info var */
4029                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4030                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4031                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4032                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4033                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4034                                 label = code;
4035                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4036                                 /* Call the trampoline */
4037                                 amd64_call_reg (code, AMD64_R11);
4038                                 amd64_patch (label, code);
4039                         } else {
4040                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4041                                 guint8 *label;
4042
4043                                 /*
4044                                  * Emit a test+branch against a constant, the constant will be overwritten
4045                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4046                                  */
4047                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4048                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4049                                 label = code;
4050                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4051
4052                                 g_assert (var);
4053                                 g_assert (var->opcode == OP_REGOFFSET);
4054                                 /* Load bp_tramp_var */
4055                                 /* This is equal to &bp_trampoline */
4056                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4057                                 /* Call the trampoline */
4058                                 amd64_call_membase (code, AMD64_R11, 0);
4059                                 amd64_patch (label, code);
4060                         }
4061                         /*
4062                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4063                          * to another IL offset.
4064                          */
4065                         x86_nop (code);
4066                         break;
4067                 }
4068                 case OP_ADDCC:
4069                 case OP_LADDCC:
4070                 case OP_LADD:
4071                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4072                         break;
4073                 case OP_ADC:
4074                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4075                         break;
4076                 case OP_ADD_IMM:
4077                 case OP_LADD_IMM:
4078                         g_assert (amd64_is_imm32 (ins->inst_imm));
4079                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4080                         break;
4081                 case OP_ADC_IMM:
4082                         g_assert (amd64_is_imm32 (ins->inst_imm));
4083                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4084                         break;
4085                 case OP_SUBCC:
4086                 case OP_LSUBCC:
4087                 case OP_LSUB:
4088                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4089                         break;
4090                 case OP_SBB:
4091                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4092                         break;
4093                 case OP_SUB_IMM:
4094                 case OP_LSUB_IMM:
4095                         g_assert (amd64_is_imm32 (ins->inst_imm));
4096                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4097                         break;
4098                 case OP_SBB_IMM:
4099                         g_assert (amd64_is_imm32 (ins->inst_imm));
4100                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4101                         break;
4102                 case OP_LAND:
4103                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4104                         break;
4105                 case OP_AND_IMM:
4106                 case OP_LAND_IMM:
4107                         g_assert (amd64_is_imm32 (ins->inst_imm));
4108                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4109                         break;
4110                 case OP_LMUL:
4111                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4112                         break;
4113                 case OP_MUL_IMM:
4114                 case OP_LMUL_IMM:
4115                 case OP_IMUL_IMM: {
4116                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4117
4118                         switch (ins->inst_imm) {
4119                         case 2:
4120                                 /* MOV r1, r2 */
4121                                 /* ADD r1, r1 */
4122                                 if (ins->dreg != ins->sreg1)
4123                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4124                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4125                                 break;
4126                         case 3:
4127                                 /* LEA r1, [r2 + r2*2] */
4128                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4129                                 break;
4130                         case 5:
4131                                 /* LEA r1, [r2 + r2*4] */
4132                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4133                                 break;
4134                         case 6:
4135                                 /* LEA r1, [r2 + r2*2] */
4136                                 /* ADD r1, r1          */
4137                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4138                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4139                                 break;
4140                         case 9:
4141                                 /* LEA r1, [r2 + r2*8] */
4142                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4143                                 break;
4144                         case 10:
4145                                 /* LEA r1, [r2 + r2*4] */
4146                                 /* ADD r1, r1          */
4147                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4148                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4149                                 break;
4150                         case 12:
4151                                 /* LEA r1, [r2 + r2*2] */
4152                                 /* SHL r1, 2           */
4153                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4154                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4155                                 break;
4156                         case 25:
4157                                 /* LEA r1, [r2 + r2*4] */
4158                                 /* LEA r1, [r1 + r1*4] */
4159                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4160                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4161                                 break;
4162                         case 100:
4163                                 /* LEA r1, [r2 + r2*4] */
4164                                 /* SHL r1, 2           */
4165                                 /* LEA r1, [r1 + r1*4] */
4166                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4167                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4168                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4169                                 break;
4170                         default:
4171                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4172                                 break;
4173                         }
4174                         break;
4175                 }
4176                 case OP_LDIV:
4177                 case OP_LREM:
4178                         /* Regalloc magic makes the div/rem cases the same */
4179                         if (ins->sreg2 == AMD64_RDX) {
4180                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4181                                 amd64_cdq (code);
4182                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4183                         } else {
4184                                 amd64_cdq (code);
4185                                 amd64_div_reg (code, ins->sreg2, TRUE);
4186                         }
4187                         break;
4188                 case OP_LDIV_UN:
4189                 case OP_LREM_UN:
4190                         if (ins->sreg2 == AMD64_RDX) {
4191                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4192                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4193                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4194                         } else {
4195                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4196                                 amd64_div_reg (code, ins->sreg2, FALSE);
4197                         }
4198                         break;
4199                 case OP_IDIV:
4200                 case OP_IREM:
4201                         if (ins->sreg2 == AMD64_RDX) {
4202                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4203                                 amd64_cdq_size (code, 4);
4204                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4205                         } else {
4206                                 amd64_cdq_size (code, 4);
4207                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4208                         }
4209                         break;
4210                 case OP_IDIV_UN:
4211                 case OP_IREM_UN:
4212                         if (ins->sreg2 == AMD64_RDX) {
4213                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4214                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4215                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4216                         } else {
4217                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4218                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4219                         }
4220                         break;
4221                 case OP_LMUL_OVF:
4222                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4223                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4224                         break;
4225                 case OP_LOR:
4226                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4227                         break;
4228                 case OP_OR_IMM:
4229                 case OP_LOR_IMM:
4230                         g_assert (amd64_is_imm32 (ins->inst_imm));
4231                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4232                         break;
4233                 case OP_LXOR:
4234                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4235                         break;
4236                 case OP_XOR_IMM:
4237                 case OP_LXOR_IMM:
4238                         g_assert (amd64_is_imm32 (ins->inst_imm));
4239                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4240                         break;
4241                 case OP_LSHL:
4242                         g_assert (ins->sreg2 == AMD64_RCX);
4243                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4244                         break;
4245                 case OP_LSHR:
4246                         g_assert (ins->sreg2 == AMD64_RCX);
4247                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4248                         break;
4249                 case OP_SHR_IMM:
4250                 case OP_LSHR_IMM:
4251                         g_assert (amd64_is_imm32 (ins->inst_imm));
4252                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4253                         break;
4254                 case OP_SHR_UN_IMM:
4255                         g_assert (amd64_is_imm32 (ins->inst_imm));
4256                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4257                         break;
4258                 case OP_LSHR_UN_IMM:
4259                         g_assert (amd64_is_imm32 (ins->inst_imm));
4260                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4261                         break;
4262                 case OP_LSHR_UN:
4263                         g_assert (ins->sreg2 == AMD64_RCX);
4264                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4265                         break;
4266                 case OP_SHL_IMM:
4267                 case OP_LSHL_IMM:
4268                         g_assert (amd64_is_imm32 (ins->inst_imm));
4269                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4270                         break;
4271
4272                 case OP_IADDCC:
4273                 case OP_IADD:
4274                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4275                         break;
4276                 case OP_IADC:
4277                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4278                         break;
4279                 case OP_IADD_IMM:
4280                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4281                         break;
4282                 case OP_IADC_IMM:
4283                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4284                         break;
4285                 case OP_ISUBCC:
4286                 case OP_ISUB:
4287                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4288                         break;
4289                 case OP_ISBB:
4290                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4291                         break;
4292                 case OP_ISUB_IMM:
4293                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4294                         break;
4295                 case OP_ISBB_IMM:
4296                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4297                         break;
4298                 case OP_IAND:
4299                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4300                         break;
4301                 case OP_IAND_IMM:
4302                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4303                         break;
4304                 case OP_IOR:
4305                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4306                         break;
4307                 case OP_IOR_IMM:
4308                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4309                         break;
4310                 case OP_IXOR:
4311                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4312                         break;
4313                 case OP_IXOR_IMM:
4314                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4315                         break;
4316                 case OP_INEG:
4317                         amd64_neg_reg_size (code, ins->sreg1, 4);
4318                         break;
4319                 case OP_INOT:
4320                         amd64_not_reg_size (code, ins->sreg1, 4);
4321                         break;
4322                 case OP_ISHL:
4323                         g_assert (ins->sreg2 == AMD64_RCX);
4324                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4325                         break;
4326                 case OP_ISHR:
4327                         g_assert (ins->sreg2 == AMD64_RCX);
4328                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4329                         break;
4330                 case OP_ISHR_IMM:
4331                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4332                         break;
4333                 case OP_ISHR_UN_IMM:
4334                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4335                         break;
4336                 case OP_ISHR_UN:
4337                         g_assert (ins->sreg2 == AMD64_RCX);
4338                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4339                         break;
4340                 case OP_ISHL_IMM:
4341                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4342                         break;
4343                 case OP_IMUL:
4344                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4345                         break;
4346                 case OP_IMUL_OVF:
4347                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4349                         break;
4350                 case OP_IMUL_OVF_UN:
4351                 case OP_LMUL_OVF_UN: {
4352                         /* the mul operation and the exception check should most likely be split */
4353                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4354                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4355                         /*g_assert (ins->sreg2 == X86_EAX);
4356                         g_assert (ins->dreg == X86_EAX);*/
4357                         if (ins->sreg2 == X86_EAX) {
4358                                 non_eax_reg = ins->sreg1;
4359                         } else if (ins->sreg1 == X86_EAX) {
4360                                 non_eax_reg = ins->sreg2;
4361                         } else {
4362                                 /* no need to save since we're going to store to it anyway */
4363                                 if (ins->dreg != X86_EAX) {
4364                                         saved_eax = TRUE;
4365                                         amd64_push_reg (code, X86_EAX);
4366                                 }
4367                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4368                                 non_eax_reg = ins->sreg2;
4369                         }
4370                         if (ins->dreg == X86_EDX) {
4371                                 if (!saved_eax) {
4372                                         saved_eax = TRUE;
4373                                         amd64_push_reg (code, X86_EAX);
4374                                 }
4375                         } else {
4376                                 saved_edx = TRUE;
4377                                 amd64_push_reg (code, X86_EDX);
4378                         }
4379                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4380                         /* save before the check since pop and mov don't change the flags */
4381                         if (ins->dreg != X86_EAX)
4382                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4383                         if (saved_edx)
4384                                 amd64_pop_reg (code, X86_EDX);
4385                         if (saved_eax)
4386                                 amd64_pop_reg (code, X86_EAX);
4387                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4388                         break;
4389                 }
4390                 case OP_ICOMPARE:
4391                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4392                         break;
4393                 case OP_ICOMPARE_IMM:
4394                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4395                         break;
4396                 case OP_IBEQ:
4397                 case OP_IBLT:
4398                 case OP_IBGT:
4399                 case OP_IBGE:
4400                 case OP_IBLE:
4401                 case OP_LBEQ:
4402                 case OP_LBLT:
4403                 case OP_LBGT:
4404                 case OP_LBGE:
4405                 case OP_LBLE:
4406                 case OP_IBNE_UN:
4407                 case OP_IBLT_UN:
4408                 case OP_IBGT_UN:
4409                 case OP_IBGE_UN:
4410                 case OP_IBLE_UN:
4411                 case OP_LBNE_UN:
4412                 case OP_LBLT_UN:
4413                 case OP_LBGT_UN:
4414                 case OP_LBGE_UN:
4415                 case OP_LBLE_UN:
4416                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4417                         break;
4418
4419                 case OP_CMOV_IEQ:
4420                 case OP_CMOV_IGE:
4421                 case OP_CMOV_IGT:
4422                 case OP_CMOV_ILE:
4423                 case OP_CMOV_ILT:
4424                 case OP_CMOV_INE_UN:
4425                 case OP_CMOV_IGE_UN:
4426                 case OP_CMOV_IGT_UN:
4427                 case OP_CMOV_ILE_UN:
4428                 case OP_CMOV_ILT_UN:
4429                 case OP_CMOV_LEQ:
4430                 case OP_CMOV_LGE:
4431                 case OP_CMOV_LGT:
4432                 case OP_CMOV_LLE:
4433                 case OP_CMOV_LLT:
4434                 case OP_CMOV_LNE_UN:
4435                 case OP_CMOV_LGE_UN:
4436                 case OP_CMOV_LGT_UN:
4437                 case OP_CMOV_LLE_UN:
4438                 case OP_CMOV_LLT_UN:
4439                         g_assert (ins->dreg == ins->sreg1);
4440                         /* This needs to operate on 64 bit values */
4441                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4442                         break;
4443
4444                 case OP_LNOT:
4445                         amd64_not_reg (code, ins->sreg1);
4446                         break;
4447                 case OP_LNEG:
4448                         amd64_neg_reg (code, ins->sreg1);
4449                         break;
4450
4451                 case OP_ICONST:
4452                 case OP_I8CONST:
4453                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4454                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4455                         else
4456                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4457                         break;
4458                 case OP_AOTCONST:
4459                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4460                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4461                         break;
4462                 case OP_JUMP_TABLE:
4463                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4464                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4465                         break;
4466                 case OP_MOVE:
4467                         if (ins->dreg != ins->sreg1)
4468                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4469                         break;
4470                 case OP_AMD64_SET_XMMREG_R4: {
4471                         if (cfg->r4fp) {
4472                                 if (ins->dreg != ins->sreg1)
4473                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4474                         } else {
4475                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4476                         }
4477                         break;
4478                 }
4479                 case OP_AMD64_SET_XMMREG_R8: {
4480                         if (ins->dreg != ins->sreg1)
4481                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4482                         break;
4483                 }
4484                 case OP_TAILCALL: {
4485                         MonoCallInst *call = (MonoCallInst*)ins;
4486                         int i, save_area_offset;
4487
4488                         g_assert (!cfg->method->save_lmf);
4489
4490                         /* the size of the tailcall op depends on signature, let's check for enough
4491                          * space in the code buffer here again */
4492                         max_len += AMD64_NREG * 4 + call->stack_usage * 15 + EXTRA_CODE_SPACE;
4493
4494                         if (G_UNLIKELY (offset + max_len > cfg->code_size)) {
4495                                 cfg->code_size *= 2;
4496                                 cfg->native_code = (unsigned char *) mono_realloc_native_code(cfg);
4497                                 code = cfg->native_code + offset;
4498                                 cfg->stat_code_reallocs++;
4499                         }
4500
4501                         /* Restore callee saved registers */
4502                         save_area_offset = cfg->arch.reg_save_area_offset;
4503                         for (i = 0; i < AMD64_NREG; ++i)
4504                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4505                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4506                                         save_area_offset += 8;
4507                                 }
4508
4509                         if (cfg->arch.omit_fp) {
4510                                 if (cfg->arch.stack_alloc_size)
4511                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4512                                 // FIXME:
4513                                 if (call->stack_usage)
4514                                         NOT_IMPLEMENTED;
4515                         } else {
4516                                 /* Copy arguments on the stack to our argument area */
4517                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4518                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4519                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4520                                 }
4521
4522 #ifdef TARGET_WIN32
4523                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4524                                 amd64_pop_reg (code, AMD64_RBP);
4525                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4526 #else
4527                                 amd64_leave (code);
4528 #endif
4529                         }
4530
4531                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4532                         if (cfg->compile_aot)
4533                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4534                         else
4535                                 amd64_set_reg_template (code, AMD64_R11);
4536                         amd64_jump_reg (code, AMD64_R11);
4537                         ins->flags |= MONO_INST_GC_CALLSITE;
4538                         ins->backend.pc_offset = code - cfg->native_code;
4539                         break;
4540                 }
4541                 case OP_CHECK_THIS:
4542                         /* ensure ins->sreg1 is not NULL */
4543                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4544                         break;
4545                 case OP_ARGLIST: {
4546                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4547                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4548                         break;
4549                 }
4550                 case OP_CALL:
4551                 case OP_FCALL:
4552                 case OP_RCALL:
4553                 case OP_LCALL:
4554                 case OP_VCALL:
4555                 case OP_VCALL2:
4556                 case OP_VOIDCALL:
4557                         call = (MonoCallInst*)ins;
4558                         /*
4559                          * The AMD64 ABI forces callers to know about varargs.
4560                          */
4561                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4562                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4563                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4564                                 /*
4565                                  * Since the unmanaged calling convention doesn't contain a
4566                                  * 'vararg' entry, we have to treat every pinvoke call as a
4567                                  * potential vararg call.
4568                                  */
4569                                 guint32 nregs, i;
4570                                 nregs = 0;
4571                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4572                                         if (call->used_fregs & (1 << i))
4573                                                 nregs ++;
4574                                 if (!nregs)
4575                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4576                                 else
4577                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4578                         }
4579
4580                         if (ins->flags & MONO_INST_HAS_METHOD)
4581                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4582                         else
4583                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4584                         ins->flags |= MONO_INST_GC_CALLSITE;
4585                         ins->backend.pc_offset = code - cfg->native_code;
4586                         code = emit_move_return_value (cfg, ins, code);
4587                         break;
4588                 case OP_FCALL_REG:
4589                 case OP_RCALL_REG:
4590                 case OP_LCALL_REG:
4591                 case OP_VCALL_REG:
4592                 case OP_VCALL2_REG:
4593                 case OP_VOIDCALL_REG:
4594                 case OP_CALL_REG:
4595                         call = (MonoCallInst*)ins;
4596
4597                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4598                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4599                                 ins->sreg1 = AMD64_R11;
4600                         }
4601
4602                         /*
4603                          * The AMD64 ABI forces callers to know about varargs.
4604                          */
4605                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4606                                 if (ins->sreg1 == AMD64_RAX) {
4607                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4608                                         ins->sreg1 = AMD64_R11;
4609                                 }
4610                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4611                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4612                                 /*
4613                                  * Since the unmanaged calling convention doesn't contain a
4614                                  * 'vararg' entry, we have to treat every pinvoke call as a
4615                                  * potential vararg call.
4616                                  */
4617                                 guint32 nregs, i;
4618                                 nregs = 0;
4619                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4620                                         if (call->used_fregs & (1 << i))
4621                                                 nregs ++;
4622                                 if (ins->sreg1 == AMD64_RAX) {
4623                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4624                                         ins->sreg1 = AMD64_R11;
4625                                 }
4626                                 if (!nregs)
4627                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4628                                 else
4629                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4630                         }
4631
4632                         amd64_call_reg (code, ins->sreg1);
4633                         ins->flags |= MONO_INST_GC_CALLSITE;
4634                         ins->backend.pc_offset = code - cfg->native_code;
4635                         code = emit_move_return_value (cfg, ins, code);
4636                         break;
4637                 case OP_FCALL_MEMBASE:
4638                 case OP_RCALL_MEMBASE:
4639                 case OP_LCALL_MEMBASE:
4640                 case OP_VCALL_MEMBASE:
4641                 case OP_VCALL2_MEMBASE:
4642                 case OP_VOIDCALL_MEMBASE:
4643                 case OP_CALL_MEMBASE:
4644                         call = (MonoCallInst*)ins;
4645
4646                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4647                         ins->flags |= MONO_INST_GC_CALLSITE;
4648                         ins->backend.pc_offset = code - cfg->native_code;
4649                         code = emit_move_return_value (cfg, ins, code);
4650                         break;
4651                 case OP_DYN_CALL: {
4652                         int i;
4653                         MonoInst *var = cfg->dyn_call_var;
4654                         guint8 *label;
4655
4656                         g_assert (var->opcode == OP_REGOFFSET);
4657
4658                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4659                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4660                         /* r10 = ftn */
4661                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4662
4663                         /* Save args buffer */
4664                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4665
4666                         /* Set fp arg regs */
4667                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4668                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4669                         label = code;
4670                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4671                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4672                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4673                         amd64_patch (label, code);
4674
4675                         /* Set stack args */
4676                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4677                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4678                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4679                         }
4680
4681                         /* Set argument registers */
4682                         for (i = 0; i < PARAM_REGS; ++i)
4683                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4684
4685                         /* Make the call */
4686                         amd64_call_reg (code, AMD64_R10);
4687
4688                         ins->flags |= MONO_INST_GC_CALLSITE;
4689                         ins->backend.pc_offset = code - cfg->native_code;
4690
4691                         /* Save result */
4692                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4693                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4694                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4695                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4696                         break;
4697                 }
4698                 case OP_AMD64_SAVE_SP_TO_LMF: {
4699                         MonoInst *lmf_var = cfg->lmf_var;
4700                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4701                         break;
4702                 }
4703                 case OP_X86_PUSH:
4704                         g_assert_not_reached ();
4705                         amd64_push_reg (code, ins->sreg1);
4706                         break;
4707                 case OP_X86_PUSH_IMM:
4708                         g_assert_not_reached ();
4709                         g_assert (amd64_is_imm32 (ins->inst_imm));
4710                         amd64_push_imm (code, ins->inst_imm);
4711                         break;
4712                 case OP_X86_PUSH_MEMBASE:
4713                         g_assert_not_reached ();
4714                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4715                         break;
4716                 case OP_X86_PUSH_OBJ: {
4717                         int size = ALIGN_TO (ins->inst_imm, 8);
4718
4719                         g_assert_not_reached ();
4720
4721                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4722                         amd64_push_reg (code, AMD64_RDI);
4723                         amd64_push_reg (code, AMD64_RSI);
4724                         amd64_push_reg (code, AMD64_RCX);
4725                         if (ins->inst_offset)
4726                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4727                         else
4728                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4729                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4730                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4731                         amd64_cld (code);
4732                         amd64_prefix (code, X86_REP_PREFIX);
4733                         amd64_movsd (code);
4734                         amd64_pop_reg (code, AMD64_RCX);
4735                         amd64_pop_reg (code, AMD64_RSI);
4736                         amd64_pop_reg (code, AMD64_RDI);
4737                         break;
4738                 }
4739                 case OP_GENERIC_CLASS_INIT: {
4740                         guint8 *jump;
4741
4742                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4743
4744                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4745                         jump = code;
4746                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4747
4748                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4749                         ins->flags |= MONO_INST_GC_CALLSITE;
4750                         ins->backend.pc_offset = code - cfg->native_code;
4751
4752                         x86_patch (jump, code);
4753                         break;
4754                 }
4755
4756                 case OP_X86_LEA:
4757                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4758                         break;
4759                 case OP_X86_LEA_MEMBASE:
4760                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4761                         break;
4762                 case OP_X86_XCHG:
4763                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4764                         break;
4765                 case OP_LOCALLOC:
4766                         /* keep alignment */
4767                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4768                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4769                         code = mono_emit_stack_alloc (cfg, code, ins);
4770                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4771                         if (cfg->param_area)
4772                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4773                         break;
4774                 case OP_LOCALLOC_IMM: {
4775                         guint32 size = ins->inst_imm;
4776                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4777
4778                         if (ins->flags & MONO_INST_INIT) {
4779                                 if (size < 64) {
4780                                         int i;
4781
4782                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4783                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4784
4785                                         for (i = 0; i < size; i += 8)
4786                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4787                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4788                                 } else {
4789                                         amd64_mov_reg_imm (code, ins->dreg, size);
4790                                         ins->sreg1 = ins->dreg;
4791
4792                                         code = mono_emit_stack_alloc (cfg, code, ins);
4793                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4794                                 }
4795                         } else {
4796                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4797                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4798                         }
4799                         if (cfg->param_area)
4800                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4801                         break;
4802                 }
4803                 case OP_THROW: {
4804                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4805                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4806                                              (gpointer)"mono_arch_throw_exception", FALSE);
4807                         ins->flags |= MONO_INST_GC_CALLSITE;
4808                         ins->backend.pc_offset = code - cfg->native_code;
4809                         break;
4810                 }
4811                 case OP_RETHROW: {
4812                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4813                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4814                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4815                         ins->flags |= MONO_INST_GC_CALLSITE;
4816                         ins->backend.pc_offset = code - cfg->native_code;
4817                         break;
4818                 }
4819                 case OP_CALL_HANDLER:
4820                         /* Align stack */
4821                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4822                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4823                         amd64_call_imm (code, 0);
4824                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4825                         /* Restore stack alignment */
4826                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4827                         break;
4828                 case OP_START_HANDLER: {
4829                         /* Even though we're saving RSP, use sizeof */
4830                         /* gpointer because spvar is of type IntPtr */
4831                         /* see: mono_create_spvar_for_region */
4832                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4833                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4834
4835                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4836                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4837                                 cfg->param_area) {
4838                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4839                         }
4840                         break;
4841                 }
4842                 case OP_ENDFINALLY: {
4843                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4844                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4845                         amd64_ret (code);
4846                         break;
4847                 }
4848                 case OP_ENDFILTER: {
4849                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4850                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4851                         /* The local allocator will put the result into RAX */
4852                         amd64_ret (code);
4853                         break;
4854                 }
4855                 case OP_GET_EX_OBJ:
4856                         if (ins->dreg != AMD64_RAX)
4857                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4858                         break;
4859                 case OP_LABEL:
4860                         ins->inst_c0 = code - cfg->native_code;
4861                         break;
4862                 case OP_BR:
4863                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4864                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4865                         //break;
4866                                 if (ins->inst_target_bb->native_offset) {
4867                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4868                                 } else {
4869                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4870                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4871                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4872                                                 x86_jump8 (code, 0);
4873                                         else
4874                                                 x86_jump32 (code, 0);
4875                         }
4876                         break;
4877                 case OP_BR_REG:
4878                         amd64_jump_reg (code, ins->sreg1);
4879                         break;
4880                 case OP_ICNEQ:
4881                 case OP_ICGE:
4882                 case OP_ICLE:
4883                 case OP_ICGE_UN:
4884                 case OP_ICLE_UN:
4885
4886                 case OP_CEQ:
4887                 case OP_LCEQ:
4888                 case OP_ICEQ:
4889                 case OP_CLT:
4890                 case OP_LCLT:
4891                 case OP_ICLT:
4892                 case OP_CGT:
4893                 case OP_ICGT:
4894                 case OP_LCGT:
4895                 case OP_CLT_UN:
4896                 case OP_LCLT_UN:
4897                 case OP_ICLT_UN:
4898                 case OP_CGT_UN:
4899                 case OP_LCGT_UN:
4900                 case OP_ICGT_UN:
4901                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4902                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4903                         break;
4904                 case OP_COND_EXC_EQ:
4905                 case OP_COND_EXC_NE_UN:
4906                 case OP_COND_EXC_LT:
4907                 case OP_COND_EXC_LT_UN:
4908                 case OP_COND_EXC_GT:
4909                 case OP_COND_EXC_GT_UN:
4910                 case OP_COND_EXC_GE:
4911                 case OP_COND_EXC_GE_UN:
4912                 case OP_COND_EXC_LE:
4913                 case OP_COND_EXC_LE_UN:
4914                 case OP_COND_EXC_IEQ:
4915                 case OP_COND_EXC_INE_UN:
4916                 case OP_COND_EXC_ILT:
4917                 case OP_COND_EXC_ILT_UN:
4918                 case OP_COND_EXC_IGT:
4919                 case OP_COND_EXC_IGT_UN:
4920                 case OP_COND_EXC_IGE:
4921                 case OP_COND_EXC_IGE_UN:
4922                 case OP_COND_EXC_ILE:
4923                 case OP_COND_EXC_ILE_UN:
4924                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4925                         break;
4926                 case OP_COND_EXC_OV:
4927                 case OP_COND_EXC_NO:
4928                 case OP_COND_EXC_C:
4929                 case OP_COND_EXC_NC:
4930                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4931                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4932                         break;
4933                 case OP_COND_EXC_IOV:
4934                 case OP_COND_EXC_INO:
4935                 case OP_COND_EXC_IC:
4936                 case OP_COND_EXC_INC:
4937                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4938                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4939                         break;
4940
4941                 /* floating point opcodes */
4942                 case OP_R8CONST: {
4943                         double d = *(double *)ins->inst_p0;
4944
4945                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4946                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4947                         }
4948                         else {
4949                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4950                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4951                         }
4952                         break;
4953                 }
4954                 case OP_R4CONST: {
4955                         float f = *(float *)ins->inst_p0;
4956
4957                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4958                                 if (cfg->r4fp)
4959                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4960                                 else
4961                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4962                         }
4963                         else {
4964                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4965                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4966                                 if (!cfg->r4fp)
4967                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4968                         }
4969                         break;
4970                 }
4971                 case OP_STORER8_MEMBASE_REG:
4972                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4973                         break;
4974                 case OP_LOADR8_MEMBASE:
4975                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4976                         break;
4977                 case OP_STORER4_MEMBASE_REG:
4978                         if (cfg->r4fp) {
4979                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4980                         } else {
4981                                 /* This requires a double->single conversion */
4982                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4983                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4984                         }
4985                         break;
4986                 case OP_LOADR4_MEMBASE:
4987                         if (cfg->r4fp) {
4988                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4989                         } else {
4990                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4991                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4992                         }
4993                         break;
4994                 case OP_ICONV_TO_R4:
4995                         if (cfg->r4fp) {
4996                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4997                         } else {
4998                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4999                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5000                         }
5001                         break;
5002                 case OP_ICONV_TO_R8:
5003                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5004                         break;
5005                 case OP_LCONV_TO_R4:
5006                         if (cfg->r4fp) {
5007                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5008                         } else {
5009                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5010                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5011                         }
5012                         break;
5013                 case OP_LCONV_TO_R8:
5014                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5015                         break;
5016                 case OP_FCONV_TO_R4:
5017                         if (cfg->r4fp) {
5018                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5019                         } else {
5020                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5021                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5022                         }
5023                         break;
5024                 case OP_FCONV_TO_I1:
5025                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5026                         break;
5027                 case OP_FCONV_TO_U1:
5028                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5029                         break;
5030                 case OP_FCONV_TO_I2:
5031                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5032                         break;
5033                 case OP_FCONV_TO_U2:
5034                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5035                         break;
5036                 case OP_FCONV_TO_U4:
5037                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5038                         break;
5039                 case OP_FCONV_TO_I4:
5040                 case OP_FCONV_TO_I:
5041                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5042                         break;
5043                 case OP_FCONV_TO_I8:
5044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5045                         break;
5046
5047                 case OP_RCONV_TO_I1:
5048                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5050                         break;
5051                 case OP_RCONV_TO_U1:
5052                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5053                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5054                         break;
5055                 case OP_RCONV_TO_I2:
5056                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5057                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5058                         break;
5059                 case OP_RCONV_TO_U2:
5060                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5061                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5062                         break;
5063                 case OP_RCONV_TO_I4:
5064                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5065                         break;
5066                 case OP_RCONV_TO_U4:
5067                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5068                         break;
5069                 case OP_RCONV_TO_I8:
5070                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5071                         break;
5072                 case OP_RCONV_TO_R8:
5073                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5074                         break;
5075                 case OP_RCONV_TO_R4:
5076                         if (ins->dreg != ins->sreg1)
5077                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5078                         break;
5079
5080                 case OP_LCONV_TO_R_UN: {
5081                         guint8 *br [2];
5082
5083                         /* Based on gcc code */
5084                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5085                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5086
5087                         /* Positive case */
5088                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5089                         br [1] = code; x86_jump8 (code, 0);
5090                         amd64_patch (br [0], code);
5091
5092                         /* Negative case */
5093                         /* Save to the red zone */
5094                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5095                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5096                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5097                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5098                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5099                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5100                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5101                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5102                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5103                         /* Restore */
5104                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5105                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5106                         amd64_patch (br [1], code);
5107                         break;
5108                 }
5109                 case OP_LCONV_TO_OVF_U4:
5110                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5111                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5112                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5113                         break;
5114                 case OP_LCONV_TO_OVF_I4_UN:
5115                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5116                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5117                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5118                         break;
5119                 case OP_FMOVE:
5120                         if (ins->dreg != ins->sreg1)
5121                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5122                         break;
5123                 case OP_RMOVE:
5124                         if (ins->dreg != ins->sreg1)
5125                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5126                         break;
5127                 case OP_MOVE_F_TO_I4:
5128                         if (cfg->r4fp) {
5129                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5130                         } else {
5131                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5132                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5133                         }
5134                         break;
5135                 case OP_MOVE_I4_TO_F:
5136                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5137                         if (!cfg->r4fp)
5138                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5139                         break;
5140                 case OP_MOVE_F_TO_I8:
5141                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5142                         break;
5143                 case OP_MOVE_I8_TO_F:
5144                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5145                         break;
5146                 case OP_FADD:
5147                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5148                         break;
5149                 case OP_FSUB:
5150                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5151                         break;
5152                 case OP_FMUL:
5153                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5154                         break;
5155                 case OP_FDIV:
5156                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5157                         break;
5158                 case OP_FNEG: {
5159                         static double r8_0 = -0.0;
5160
5161                         g_assert (ins->sreg1 == ins->dreg);
5162
5163                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5164                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5165                         break;
5166                 }
5167                 case OP_SIN:
5168                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5169                         break;
5170                 case OP_COS:
5171                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5172                         break;
5173                 case OP_ABS: {
5174                         static guint64 d = 0x7fffffffffffffffUL;
5175
5176                         g_assert (ins->sreg1 == ins->dreg);
5177
5178                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5179                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5180                         break;
5181                 }
5182                 case OP_SQRT:
5183                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5184                         break;
5185
5186                 case OP_RADD:
5187                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5188                         break;
5189                 case OP_RSUB:
5190                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5191                         break;
5192                 case OP_RMUL:
5193                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5194                         break;
5195                 case OP_RDIV:
5196                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5197                         break;
5198                 case OP_RNEG: {
5199                         static float r4_0 = -0.0;
5200
5201                         g_assert (ins->sreg1 == ins->dreg);
5202
5203                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5204                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5205                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5206                         break;
5207                 }
5208
5209                 case OP_IMIN:
5210                         g_assert (cfg->opt & MONO_OPT_CMOV);
5211                         g_assert (ins->dreg == ins->sreg1);
5212                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5213                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5214                         break;
5215                 case OP_IMIN_UN:
5216                         g_assert (cfg->opt & MONO_OPT_CMOV);
5217                         g_assert (ins->dreg == ins->sreg1);
5218                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5219                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5220                         break;
5221                 case OP_IMAX:
5222                         g_assert (cfg->opt & MONO_OPT_CMOV);
5223                         g_assert (ins->dreg == ins->sreg1);
5224                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5225                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5226                         break;
5227                 case OP_IMAX_UN:
5228                         g_assert (cfg->opt & MONO_OPT_CMOV);
5229                         g_assert (ins->dreg == ins->sreg1);
5230                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5231                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5232                         break;
5233                 case OP_LMIN:
5234                         g_assert (cfg->opt & MONO_OPT_CMOV);
5235                         g_assert (ins->dreg == ins->sreg1);
5236                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5237                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5238                         break;
5239                 case OP_LMIN_UN:
5240                         g_assert (cfg->opt & MONO_OPT_CMOV);
5241                         g_assert (ins->dreg == ins->sreg1);
5242                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5243                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5244                         break;
5245                 case OP_LMAX:
5246                         g_assert (cfg->opt & MONO_OPT_CMOV);
5247                         g_assert (ins->dreg == ins->sreg1);
5248                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5249                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5250                         break;
5251                 case OP_LMAX_UN:
5252                         g_assert (cfg->opt & MONO_OPT_CMOV);
5253                         g_assert (ins->dreg == ins->sreg1);
5254                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5255                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5256                         break;
5257                 case OP_X86_FPOP:
5258                         break;
5259                 case OP_FCOMPARE:
5260                         /*
5261                          * The two arguments are swapped because the fbranch instructions
5262                          * depend on this for the non-sse case to work.
5263                          */
5264                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5265                         break;
5266                 case OP_RCOMPARE:
5267                         /*
5268                          * FIXME: Get rid of this.
5269                          * The two arguments are swapped because the fbranch instructions
5270                          * depend on this for the non-sse case to work.
5271                          */
5272                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5273                         break;
5274                 case OP_FCNEQ:
5275                 case OP_FCEQ: {
5276                         /* zeroing the register at the start results in
5277                          * shorter and faster code (we can also remove the widening op)
5278                          */
5279                         guchar *unordered_check;
5280
5281                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5282                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5283                         unordered_check = code;
5284                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5285
5286                         if (ins->opcode == OP_FCEQ) {
5287                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5288                                 amd64_patch (unordered_check, code);
5289                         } else {
5290                                 guchar *jump_to_end;
5291                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5292                                 jump_to_end = code;
5293                                 x86_jump8 (code, 0);
5294                                 amd64_patch (unordered_check, code);
5295                                 amd64_inc_reg (code, ins->dreg);
5296                                 amd64_patch (jump_to_end, code);
5297                         }
5298                         break;
5299                 }
5300                 case OP_FCLT:
5301                 case OP_FCLT_UN: {
5302                         /* zeroing the register at the start results in
5303                          * shorter and faster code (we can also remove the widening op)
5304                          */
5305                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5306                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5307                         if (ins->opcode == OP_FCLT_UN) {
5308                                 guchar *unordered_check = code;
5309                                 guchar *jump_to_end;
5310                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5311                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5312                                 jump_to_end = code;
5313                                 x86_jump8 (code, 0);
5314                                 amd64_patch (unordered_check, code);
5315                                 amd64_inc_reg (code, ins->dreg);
5316                                 amd64_patch (jump_to_end, code);
5317                         } else {
5318                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5319                         }
5320                         break;
5321                 }
5322                 case OP_FCLE: {
5323                         guchar *unordered_check;
5324                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5325                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5326                         unordered_check = code;
5327                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5328                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5329                         amd64_patch (unordered_check, code);
5330                         break;
5331                 }
5332                 case OP_FCGT:
5333                 case OP_FCGT_UN: {
5334                         /* zeroing the register at the start results in
5335                          * shorter and faster code (we can also remove the widening op)
5336                          */
5337                         guchar *unordered_check;
5338
5339                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5340                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341                         if (ins->opcode == OP_FCGT) {
5342                                 unordered_check = code;
5343                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5344                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5345                                 amd64_patch (unordered_check, code);
5346                         } else {
5347                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5348                         }
5349                         break;
5350                 }
5351                 case OP_FCGE: {
5352                         guchar *unordered_check;
5353                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5354                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5355                         unordered_check = code;
5356                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5357                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5358                         amd64_patch (unordered_check, code);
5359                         break;
5360                 }
5361
5362                 case OP_RCEQ:
5363                 case OP_RCGT:
5364                 case OP_RCLT:
5365                 case OP_RCLT_UN:
5366                 case OP_RCGT_UN: {
5367                         int x86_cond;
5368                         gboolean unordered = FALSE;
5369
5370                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5371                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5372
5373                         switch (ins->opcode) {
5374                         case OP_RCEQ:
5375                                 x86_cond = X86_CC_EQ;
5376                                 break;
5377                         case OP_RCGT:
5378                                 x86_cond = X86_CC_LT;
5379                                 break;
5380                         case OP_RCLT:
5381                                 x86_cond = X86_CC_GT;
5382                                 break;
5383                         case OP_RCLT_UN:
5384                                 x86_cond = X86_CC_GT;
5385                                 unordered = TRUE;
5386                                 break;
5387                         case OP_RCGT_UN:
5388                                 x86_cond = X86_CC_LT;
5389                                 unordered = TRUE;
5390                                 break;
5391                         default:
5392                                 g_assert_not_reached ();
5393                                 break;
5394                         }
5395
5396                         if (unordered) {
5397                                 guchar *unordered_check;
5398                                 guchar *jump_to_end;
5399
5400                                 unordered_check = code;
5401                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5402                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5403                                 jump_to_end = code;
5404                                 x86_jump8 (code, 0);
5405                                 amd64_patch (unordered_check, code);
5406                                 amd64_inc_reg (code, ins->dreg);
5407                                 amd64_patch (jump_to_end, code);
5408                         } else {
5409                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5410                         }
5411                         break;
5412                 }
5413                 case OP_FCLT_MEMBASE:
5414                 case OP_FCGT_MEMBASE:
5415                 case OP_FCLT_UN_MEMBASE:
5416                 case OP_FCGT_UN_MEMBASE:
5417                 case OP_FCEQ_MEMBASE: {
5418                         guchar *unordered_check, *jump_to_end;
5419                         int x86_cond;
5420
5421                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5422                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5423
5424                         switch (ins->opcode) {
5425                         case OP_FCEQ_MEMBASE:
5426                                 x86_cond = X86_CC_EQ;
5427                                 break;
5428                         case OP_FCLT_MEMBASE:
5429                         case OP_FCLT_UN_MEMBASE:
5430                                 x86_cond = X86_CC_LT;
5431                                 break;
5432                         case OP_FCGT_MEMBASE:
5433                         case OP_FCGT_UN_MEMBASE:
5434                                 x86_cond = X86_CC_GT;
5435                                 break;
5436                         default:
5437                                 g_assert_not_reached ();
5438                         }
5439
5440                         unordered_check = code;
5441                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5442                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5443
5444                         switch (ins->opcode) {
5445                         case OP_FCEQ_MEMBASE:
5446                         case OP_FCLT_MEMBASE:
5447                         case OP_FCGT_MEMBASE:
5448                                 amd64_patch (unordered_check, code);
5449                                 break;
5450                         case OP_FCLT_UN_MEMBASE:
5451                         case OP_FCGT_UN_MEMBASE:
5452                                 jump_to_end = code;
5453                                 x86_jump8 (code, 0);
5454                                 amd64_patch (unordered_check, code);
5455                                 amd64_inc_reg (code, ins->dreg);
5456                                 amd64_patch (jump_to_end, code);
5457                                 break;
5458                         default:
5459                                 break;
5460                         }
5461                         break;
5462                 }
5463                 case OP_FBEQ: {
5464                         guchar *jump = code;
5465                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5466                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5467                         amd64_patch (jump, code);
5468                         break;
5469                 }
5470                 case OP_FBNE_UN:
5471                         /* Branch if C013 != 100 */
5472                         /* branch if !ZF or (PF|CF) */
5473                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5474                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5475                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5476                         break;
5477                 case OP_FBLT:
5478                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5479                         break;
5480                 case OP_FBLT_UN:
5481                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5482                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5483                         break;
5484                 case OP_FBGT:
5485                 case OP_FBGT_UN:
5486                         if (ins->opcode == OP_FBGT) {
5487                                 guchar *br1;
5488
5489                                 /* skip branch if C1=1 */
5490                                 br1 = code;
5491                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5492                                 /* branch if (C0 | C3) = 1 */
5493                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5494                                 amd64_patch (br1, code);
5495                                 break;
5496                         } else {
5497                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5498                         }
5499                         break;
5500                 case OP_FBGE: {
5501                         /* Branch if C013 == 100 or 001 */
5502                         guchar *br1;
5503
5504                         /* skip branch if C1=1 */
5505                         br1 = code;
5506                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5507                         /* branch if (C0 | C3) = 1 */
5508                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5509                         amd64_patch (br1, code);
5510                         break;
5511                 }
5512                 case OP_FBGE_UN:
5513                         /* Branch if C013 == 000 */
5514                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5515                         break;
5516                 case OP_FBLE: {
5517                         /* Branch if C013=000 or 100 */
5518                         guchar *br1;
5519
5520                         /* skip branch if C1=1 */
5521                         br1 = code;
5522                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5523                         /* branch if C0=0 */
5524                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5525                         amd64_patch (br1, code);
5526                         break;
5527                 }
5528                 case OP_FBLE_UN:
5529                         /* Branch if C013 != 001 */
5530                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5531                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5532                         break;
5533                 case OP_CKFINITE:
5534                         /* Transfer value to the fp stack */
5535                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5536                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5537                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5538
5539                         amd64_push_reg (code, AMD64_RAX);
5540                         amd64_fxam (code);
5541                         amd64_fnstsw (code);
5542                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5543                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5544                         amd64_pop_reg (code, AMD64_RAX);
5545                         amd64_fstp (code, 0);
5546                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5547                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5548                         break;
5549                 case OP_TLS_GET: {
5550                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5551                         break;
5552                 }
5553                 case OP_TLS_SET: {
5554                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5555                         break;
5556                 }
5557                 case OP_MEMORY_BARRIER: {
5558                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5559                                 x86_mfence (code);
5560                         break;
5561                 }
5562                 case OP_ATOMIC_ADD_I4:
5563                 case OP_ATOMIC_ADD_I8: {
5564                         int dreg = ins->dreg;
5565                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5566
5567                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5568                                 dreg = AMD64_R11;
5569
5570                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5571                         amd64_prefix (code, X86_LOCK_PREFIX);
5572                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5573                         /* dreg contains the old value, add with sreg2 value */
5574                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5575
5576                         if (ins->dreg != dreg)
5577                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5578
5579                         break;
5580                 }
5581                 case OP_ATOMIC_EXCHANGE_I4:
5582                 case OP_ATOMIC_EXCHANGE_I8: {
5583                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5584
5585                         /* LOCK prefix is implied. */
5586                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5587                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5588                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5589                         break;
5590                 }
5591                 case OP_ATOMIC_CAS_I4:
5592                 case OP_ATOMIC_CAS_I8: {
5593                         guint32 size;
5594
5595                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5596                                 size = 8;
5597                         else
5598                                 size = 4;
5599
5600                         /*
5601                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5602                          * an explanation of how this works.
5603                          */
5604                         g_assert (ins->sreg3 == AMD64_RAX);
5605                         g_assert (ins->sreg1 != AMD64_RAX);
5606                         g_assert (ins->sreg1 != ins->sreg2);
5607
5608                         amd64_prefix (code, X86_LOCK_PREFIX);
5609                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5610
5611                         if (ins->dreg != AMD64_RAX)
5612                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5613                         break;
5614                 }
5615                 case OP_ATOMIC_LOAD_I1: {
5616                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5617                         break;
5618                 }
5619                 case OP_ATOMIC_LOAD_U1: {
5620                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5621                         break;
5622                 }
5623                 case OP_ATOMIC_LOAD_I2: {
5624                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5625                         break;
5626                 }
5627                 case OP_ATOMIC_LOAD_U2: {
5628                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5629                         break;
5630                 }
5631                 case OP_ATOMIC_LOAD_I4: {
5632                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5633                         break;
5634                 }
5635                 case OP_ATOMIC_LOAD_U4:
5636                 case OP_ATOMIC_LOAD_I8:
5637                 case OP_ATOMIC_LOAD_U8: {
5638                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5639                         break;
5640                 }
5641                 case OP_ATOMIC_LOAD_R4: {
5642                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5643                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5644                         break;
5645                 }
5646                 case OP_ATOMIC_LOAD_R8: {
5647                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5648                         break;
5649                 }
5650                 case OP_ATOMIC_STORE_I1:
5651                 case OP_ATOMIC_STORE_U1:
5652                 case OP_ATOMIC_STORE_I2:
5653                 case OP_ATOMIC_STORE_U2:
5654                 case OP_ATOMIC_STORE_I4:
5655                 case OP_ATOMIC_STORE_U4:
5656                 case OP_ATOMIC_STORE_I8:
5657                 case OP_ATOMIC_STORE_U8: {
5658                         int size;
5659
5660                         switch (ins->opcode) {
5661                         case OP_ATOMIC_STORE_I1:
5662                         case OP_ATOMIC_STORE_U1:
5663                                 size = 1;
5664                                 break;
5665                         case OP_ATOMIC_STORE_I2:
5666                         case OP_ATOMIC_STORE_U2:
5667                                 size = 2;
5668                                 break;
5669                         case OP_ATOMIC_STORE_I4:
5670                         case OP_ATOMIC_STORE_U4:
5671                                 size = 4;
5672                                 break;
5673                         case OP_ATOMIC_STORE_I8:
5674                         case OP_ATOMIC_STORE_U8:
5675                                 size = 8;
5676                                 break;
5677                         }
5678
5679                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5680
5681                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5682                                 x86_mfence (code);
5683                         break;
5684                 }
5685                 case OP_ATOMIC_STORE_R4: {
5686                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5687                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5688
5689                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5690                                 x86_mfence (code);
5691                         break;
5692                 }
5693                 case OP_ATOMIC_STORE_R8: {
5694                         x86_nop (code);
5695                         x86_nop (code);
5696                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5697                         x86_nop (code);
5698                         x86_nop (code);
5699
5700                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5701                                 x86_mfence (code);
5702                         break;
5703                 }
5704                 case OP_CARD_TABLE_WBARRIER: {
5705                         int ptr = ins->sreg1;
5706                         int value = ins->sreg2;
5707                         guchar *br = 0;
5708                         int nursery_shift, card_table_shift;
5709                         gpointer card_table_mask;
5710                         size_t nursery_size;
5711
5712                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5713                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5714                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5715
5716                         /*If either point to the stack we can simply avoid the WB. This happens due to
5717                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5718                          */
5719                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5720                                 continue;
5721
5722                         /*
5723                          * We need one register we can clobber, we choose EDX and make sreg1
5724                          * fixed EAX to work around limitations in the local register allocator.
5725                          * sreg2 might get allocated to EDX, but that is not a problem since
5726                          * we use it before clobbering EDX.
5727                          */
5728                         g_assert (ins->sreg1 == AMD64_RAX);
5729
5730                         /*
5731                          * This is the code we produce:
5732                          *
5733                          *   edx = value
5734                          *   edx >>= nursery_shift
5735                          *   cmp edx, (nursery_start >> nursery_shift)
5736                          *   jne done
5737                          *   edx = ptr
5738                          *   edx >>= card_table_shift
5739                          *   edx += cardtable
5740                          *   [edx] = 1
5741                          * done:
5742                          */
5743
5744                         if (mono_gc_card_table_nursery_check ()) {
5745                                 if (value != AMD64_RDX)
5746                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5747                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5748                                 if (shifted_nursery_start >> 31) {
5749                                         /*
5750                                          * The value we need to compare against is 64 bits, so we need
5751                                          * another spare register.  We use RBX, which we save and
5752                                          * restore.
5753                                          */
5754                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5755                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5756                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5757                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5758                                 } else {
5759                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5760                                 }
5761                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5762                         }
5763                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5764                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5765                         if (card_table_mask)
5766                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5767
5768                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5769                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5770
5771                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5772
5773                         if (mono_gc_card_table_nursery_check ())
5774                                 x86_patch (br, code);
5775                         break;
5776                 }
5777 #ifdef MONO_ARCH_SIMD_INTRINSICS
5778                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5779                 case OP_ADDPS:
5780                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5781                         break;
5782                 case OP_DIVPS:
5783                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5784                         break;
5785                 case OP_MULPS:
5786                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5787                         break;
5788                 case OP_SUBPS:
5789                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5790                         break;
5791                 case OP_MAXPS:
5792                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5793                         break;
5794                 case OP_MINPS:
5795                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5796                         break;
5797                 case OP_COMPPS:
5798                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5799                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5800                         break;
5801                 case OP_ANDPS:
5802                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5803                         break;
5804                 case OP_ANDNPS:
5805                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5806                         break;
5807                 case OP_ORPS:
5808                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5809                         break;
5810                 case OP_XORPS:
5811                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_SQRTPS:
5814                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5815                         break;
5816                 case OP_RSQRTPS:
5817                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5818                         break;
5819                 case OP_RCPPS:
5820                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5821                         break;
5822                 case OP_ADDSUBPS:
5823                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5824                         break;
5825                 case OP_HADDPS:
5826                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5827                         break;
5828                 case OP_HSUBPS:
5829                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5830                         break;
5831                 case OP_DUPPS_HIGH:
5832                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5833                         break;
5834                 case OP_DUPPS_LOW:
5835                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5836                         break;
5837
5838                 case OP_PSHUFLEW_HIGH:
5839                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5840                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5841                         break;
5842                 case OP_PSHUFLEW_LOW:
5843                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5844                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5845                         break;
5846                 case OP_PSHUFLED:
5847                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5848                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5849                         break;
5850                 case OP_SHUFPS:
5851                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5852                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5853                         break;
5854                 case OP_SHUFPD:
5855                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5856                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5857                         break;
5858
5859                 case OP_ADDPD:
5860                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5861                         break;
5862                 case OP_DIVPD:
5863                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_MULPD:
5866                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_SUBPD:
5869                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_MAXPD:
5872                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874                 case OP_MINPD:
5875                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_COMPPD:
5878                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5879                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5880                         break;
5881                 case OP_ANDPD:
5882                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883                         break;
5884                 case OP_ANDNPD:
5885                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_ORPD:
5888                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_XORPD:
5891                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_SQRTPD:
5894                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5895                         break;
5896                 case OP_ADDSUBPD:
5897                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898                         break;
5899                 case OP_HADDPD:
5900                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902                 case OP_HSUBPD:
5903                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_DUPPD:
5906                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5907                         break;
5908
5909                 case OP_EXTRACT_MASK:
5910                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5911                         break;
5912
5913                 case OP_PAND:
5914                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_POR:
5917                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_PXOR:
5920                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922
5923                 case OP_PADDB:
5924                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_PADDW:
5927                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_PADDD:
5930                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_PADDQ:
5933                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935
5936                 case OP_PSUBB:
5937                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PSUBW:
5940                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_PSUBD:
5943                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_PSUBQ:
5946                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948
5949                 case OP_PMAXB_UN:
5950                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PMAXW_UN:
5953                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955                 case OP_PMAXD_UN:
5956                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958
5959                 case OP_PMAXB:
5960                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PMAXW:
5963                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PMAXD:
5966                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PAVGB_UN:
5970                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PAVGW_UN:
5973                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975
5976                 case OP_PMINB_UN:
5977                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979                 case OP_PMINW_UN:
5980                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PMIND_UN:
5983                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985
5986                 case OP_PMINB:
5987                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_PMINW:
5990                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_PMIND:
5993                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995
5996                 case OP_PCMPEQB:
5997                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_PCMPEQW:
6000                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PCMPEQD:
6003                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_PCMPEQQ:
6006                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008
6009                 case OP_PCMPGTB:
6010                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PCMPGTW:
6013                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_PCMPGTD:
6016                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_PCMPGTQ:
6019                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021
6022                 case OP_PSUM_ABS_DIFF:
6023                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025
6026                 case OP_UNPACK_LOWB:
6027                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029                 case OP_UNPACK_LOWW:
6030                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_UNPACK_LOWD:
6033                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_UNPACK_LOWQ:
6036                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_UNPACK_LOWPS:
6039                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_UNPACK_LOWPD:
6042                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044
6045                 case OP_UNPACK_HIGHB:
6046                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_UNPACK_HIGHW:
6049                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_UNPACK_HIGHD:
6052                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_UNPACK_HIGHQ:
6055                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_UNPACK_HIGHPS:
6058                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_UNPACK_HIGHPD:
6061                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063
6064                 case OP_PACKW:
6065                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PACKD:
6068                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PACKW_UN:
6071                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PACKD_UN:
6074                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PADDB_SAT_UN:
6078                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PSUBB_SAT_UN:
6081                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PADDW_SAT_UN:
6084                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PSUBW_SAT_UN:
6087                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089
6090                 case OP_PADDB_SAT:
6091                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PSUBB_SAT:
6094                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PADDW_SAT:
6097                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PSUBW_SAT:
6100                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PMULW:
6104                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PMULD:
6107                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMULQ:
6110                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMULW_HIGH_UN:
6113                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PMULW_HIGH:
6116                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118
6119                 case OP_PSHRW:
6120                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6121                         break;
6122                 case OP_PSHRW_REG:
6123                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6124                         break;
6125
6126                 case OP_PSARW:
6127                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6128                         break;
6129                 case OP_PSARW_REG:
6130                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6131                         break;
6132
6133                 case OP_PSHLW:
6134                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6135                         break;
6136                 case OP_PSHLW_REG:
6137                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6138                         break;
6139
6140                 case OP_PSHRD:
6141                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6142                         break;
6143                 case OP_PSHRD_REG:
6144                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6145                         break;
6146
6147                 case OP_PSARD:
6148                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6149                         break;
6150                 case OP_PSARD_REG:
6151                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6152                         break;
6153
6154                 case OP_PSHLD:
6155                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6156                         break;
6157                 case OP_PSHLD_REG:
6158                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6159                         break;
6160
6161                 case OP_PSHRQ:
6162                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6163                         break;
6164                 case OP_PSHRQ_REG:
6165                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6166                         break;
6167
6168                 /*TODO: This is appart of the sse spec but not added
6169                 case OP_PSARQ:
6170                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6171                         break;
6172                 case OP_PSARQ_REG:
6173                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6174                         break;
6175                 */
6176
6177                 case OP_PSHLQ:
6178                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6179                         break;
6180                 case OP_PSHLQ_REG:
6181                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6182                         break;
6183                 case OP_CVTDQ2PD:
6184                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6185                         break;
6186                 case OP_CVTDQ2PS:
6187                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6188                         break;
6189                 case OP_CVTPD2DQ:
6190                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6191                         break;
6192                 case OP_CVTPD2PS:
6193                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6194                         break;
6195                 case OP_CVTPS2DQ:
6196                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6197                         break;
6198                 case OP_CVTPS2PD:
6199                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6200                         break;
6201                 case OP_CVTTPD2DQ:
6202                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6203                         break;
6204                 case OP_CVTTPS2DQ:
6205                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6206                         break;
6207
6208                 case OP_ICONV_TO_X:
6209                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6210                         break;
6211                 case OP_EXTRACT_I4:
6212                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6213                         break;
6214                 case OP_EXTRACT_I8:
6215                         if (ins->inst_c0) {
6216                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6217                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6218                         } else {
6219                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6220                         }
6221                         break;
6222                 case OP_EXTRACT_I1:
6223                 case OP_EXTRACT_U1:
6224                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6225                         if (ins->inst_c0)
6226                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6227                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6228                         break;
6229                 case OP_EXTRACT_I2:
6230                 case OP_EXTRACT_U2:
6231                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6232                         if (ins->inst_c0)
6233                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6234                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6235                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6236                         break;
6237                 case OP_EXTRACT_R8:
6238                         if (ins->inst_c0)
6239                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6240                         else
6241                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6242                         break;
6243                 case OP_INSERT_I2:
6244                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6245                         break;
6246                 case OP_EXTRACTX_U2:
6247                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6248                         break;
6249                 case OP_INSERTX_U1_SLOW:
6250                         /*sreg1 is the extracted ireg (scratch)
6251                         /sreg2 is the to be inserted ireg (scratch)
6252                         /dreg is the xreg to receive the value*/
6253
6254                         /*clear the bits from the extracted word*/
6255                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6256                         /*shift the value to insert if needed*/
6257                         if (ins->inst_c0 & 1)
6258                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6259                         /*join them together*/
6260                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6261                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6262                         break;
6263                 case OP_INSERTX_I4_SLOW:
6264                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6265                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6266                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6267                         break;
6268                 case OP_INSERTX_I8_SLOW:
6269                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6270                         if (ins->inst_c0)
6271                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6272                         else
6273                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6274                         break;
6275
6276                 case OP_INSERTX_R4_SLOW:
6277                         switch (ins->inst_c0) {
6278                         case 0:
6279                                 if (cfg->r4fp)
6280                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6281                                 else
6282                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6283                                 break;
6284                         case 1:
6285                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6286                                 if (cfg->r4fp)
6287                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6288                                 else
6289                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6290                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6291                                 break;
6292                         case 2:
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6294                                 if (cfg->r4fp)
6295                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6296                                 else
6297                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6298                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6299                                 break;
6300                         case 3:
6301                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6302                                 if (cfg->r4fp)
6303                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6304                                 else
6305                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6306                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6307                                 break;
6308                         }
6309                         break;
6310                 case OP_INSERTX_R8_SLOW:
6311                         if (ins->inst_c0)
6312                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6313                         else
6314                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6315                         break;
6316                 case OP_STOREX_MEMBASE_REG:
6317                 case OP_STOREX_MEMBASE:
6318                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6319                         break;
6320                 case OP_LOADX_MEMBASE:
6321                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6322                         break;
6323                 case OP_LOADX_ALIGNED_MEMBASE:
6324                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6325                         break;
6326                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6327                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6328                         break;
6329                 case OP_STOREX_NTA_MEMBASE_REG:
6330                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6331                         break;
6332                 case OP_PREFETCH_MEMBASE:
6333                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6334                         break;
6335
6336                 case OP_XMOVE:
6337                         /*FIXME the peephole pass should have killed this*/
6338                         if (ins->dreg != ins->sreg1)
6339                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6340                         break;
6341                 case OP_XZERO:
6342                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6343                         break;
6344                 case OP_XONES:
6345                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6346                         break;
6347                 case OP_ICONV_TO_R4_RAW:
6348                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6349                         if (!cfg->r4fp)
6350                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6351                         break;
6352
6353                 case OP_FCONV_TO_R8_X:
6354                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6355                         break;
6356
6357                 case OP_XCONV_R8_TO_I4:
6358                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6359                         switch (ins->backend.source_opcode) {
6360                         case OP_FCONV_TO_I1:
6361                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6362                                 break;
6363                         case OP_FCONV_TO_U1:
6364                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6365                                 break;
6366                         case OP_FCONV_TO_I2:
6367                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6368                                 break;
6369                         case OP_FCONV_TO_U2:
6370                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6371                                 break;
6372                         }
6373                         break;
6374
6375                 case OP_EXPAND_I2:
6376                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6377                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6378                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6379                         break;
6380                 case OP_EXPAND_I4:
6381                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6382                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6383                         break;
6384                 case OP_EXPAND_I8:
6385                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6386                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6387                         break;
6388                 case OP_EXPAND_R4:
6389                         if (cfg->r4fp) {
6390                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6391                         } else {
6392                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6393                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6394                         }
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6396                         break;
6397                 case OP_EXPAND_R8:
6398                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6400                         break;
6401 #endif
6402                 case OP_LIVERANGE_START: {
6403                         if (cfg->verbose_level > 1)
6404                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6405                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6406                         break;
6407                 }
6408                 case OP_LIVERANGE_END: {
6409                         if (cfg->verbose_level > 1)
6410                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6411                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6412                         break;
6413                 }
6414                 case OP_GC_SAFE_POINT: {
6415                         guint8 *br [1];
6416
6417                         g_assert (mono_threads_is_coop_enabled ());
6418
6419                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6420                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6421                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6422                         amd64_patch (br[0], code);
6423                         break;
6424                 }
6425
6426                 case OP_GC_LIVENESS_DEF:
6427                 case OP_GC_LIVENESS_USE:
6428                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6429                         ins->backend.pc_offset = code - cfg->native_code;
6430                         break;
6431                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6432                         ins->backend.pc_offset = code - cfg->native_code;
6433                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6434                         break;
6435                 case OP_GET_LAST_ERROR:
6436                         emit_get_last_error(code, ins->dreg);
6437                         break;
6438                 case OP_FILL_PROF_CALL_CTX:
6439                         for (int i = 0; i < AMD64_NREG; i++)
6440                                 if (AMD64_IS_CALLEE_SAVED_REG (i) || i == AMD64_RSP)
6441                                         amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (mgreg_t), i, sizeof (mgreg_t));
6442                         break;
6443                 default:
6444                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6445                         g_assert_not_reached ();
6446                 }
6447
6448                 if ((code - cfg->native_code - offset) > max_len) {
6449                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6450                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6451                         g_assert_not_reached ();
6452                 }
6453         }
6454
6455         cfg->code_len = code - cfg->native_code;
6456 }
6457
6458 #endif /* DISABLE_JIT */
6459
6460 void
6461 mono_arch_register_lowlevel_calls (void)
6462 {
6463         /* The signature doesn't matter */
6464         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6465
6466 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6467 #if _MSC_VER
6468         extern void __chkstk (void);
6469         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6470 #else
6471         extern void ___chkstk_ms (void);
6472         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6473 #endif
6474 #endif
6475 }
6476
6477 void
6478 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6479 {
6480         unsigned char *ip = ji->ip.i + code;
6481
6482         /*
6483          * Debug code to help track down problems where the target of a near call is
6484          * is not valid.
6485          */
6486         if (amd64_is_near_call (ip)) {
6487                 gint64 disp = (guint8*)target - (guint8*)ip;
6488
6489                 if (!amd64_is_imm32 (disp)) {
6490                         printf ("TYPE: %d\n", ji->type);
6491                         switch (ji->type) {
6492                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6493                                 printf ("V: %s\n", ji->data.name);
6494                                 break;
6495                         case MONO_PATCH_INFO_METHOD_JUMP:
6496                         case MONO_PATCH_INFO_METHOD:
6497                                 printf ("V: %s\n", ji->data.method->name);
6498                                 break;
6499                         default:
6500                                 break;
6501                         }
6502                 }
6503         }
6504
6505         amd64_patch (ip, (gpointer)target);
6506 }
6507
6508 #ifndef DISABLE_JIT
6509
6510 static int
6511 get_max_epilog_size (MonoCompile *cfg)
6512 {
6513         int max_epilog_size = 16;
6514
6515         if (cfg->method->save_lmf)
6516                 max_epilog_size += 256;
6517
6518         if (mono_jit_trace_calls != NULL)
6519                 max_epilog_size += 50;
6520
6521         max_epilog_size += (AMD64_NREG * 2);
6522
6523         return max_epilog_size;
6524 }
6525
6526 /*
6527  * This macro is used for testing whenever the unwinder works correctly at every point
6528  * where an async exception can happen.
6529  */
6530 /* This will generate a SIGSEGV at the given point in the code */
6531 #define async_exc_point(code) do { \
6532     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6533          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6534              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6535          cfg->arch.async_point_count ++; \
6536     } \
6537 } while (0)
6538
6539 #ifdef TARGET_WIN32
6540 static guint8 *
6541 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6542 {
6543         int cfa_offset = *cfa_offset_input;
6544
6545         /* Allocate windows stack frame using stack probing method */
6546         if (alloc_size) {
6547
6548                 if (alloc_size >= 0x1000) {
6549                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6550                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6551                 }
6552
6553                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6554                 if (cfg->arch.omit_fp) {
6555                         cfa_offset += alloc_size;
6556                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6557                         async_exc_point (code);
6558                 }
6559
6560                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6561                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6562                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6563                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6564                 // that will retrieve the expected results.
6565                 if (cfg->arch.omit_fp)
6566                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6567         }
6568
6569         *cfa_offset_input = cfa_offset;
6570         return code;
6571 }
6572 #endif /* TARGET_WIN32 */
6573
6574 guint8 *
6575 mono_arch_emit_prolog (MonoCompile *cfg)
6576 {
6577         MonoMethod *method = cfg->method;
6578         MonoBasicBlock *bb;
6579         MonoMethodSignature *sig;
6580         MonoInst *ins;
6581         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6582         guint8 *code;
6583         CallInfo *cinfo;
6584         MonoInst *lmf_var = cfg->lmf_var;
6585         gboolean args_clobbered = FALSE;
6586         gboolean trace = FALSE;
6587
6588         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6589
6590         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6591
6592         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6593                 trace = TRUE;
6594
6595         /* Amount of stack space allocated by register saving code */
6596         pos = 0;
6597
6598         /* Offset between RSP and the CFA */
6599         cfa_offset = 0;
6600
6601         /*
6602          * The prolog consists of the following parts:
6603          * FP present:
6604          * - push rbp
6605          * - mov rbp, rsp
6606          * - save callee saved regs using moves
6607          * - allocate frame
6608          * - save rgctx if needed
6609          * - save lmf if needed
6610          * FP not present:
6611          * - allocate frame
6612          * - save rgctx if needed
6613          * - save lmf if needed
6614          * - save callee saved regs using moves
6615          */
6616
6617         // CFA = sp + 8
6618         cfa_offset = 8;
6619         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6620         // IP saved at CFA - 8
6621         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6622         async_exc_point (code);
6623         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6624
6625         if (!cfg->arch.omit_fp) {
6626                 amd64_push_reg (code, AMD64_RBP);
6627                 cfa_offset += 8;
6628                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6629                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6630                 async_exc_point (code);
6631                 /* These are handled automatically by the stack marking code */
6632                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6633
6634                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6635                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6636                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6637                 async_exc_point (code);
6638         }
6639
6640         /* The param area is always at offset 0 from sp */
6641         /* This needs to be allocated here, since it has to come after the spill area */
6642         if (cfg->param_area) {
6643                 if (cfg->arch.omit_fp)
6644                         // FIXME:
6645                         g_assert_not_reached ();
6646                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6647         }
6648
6649         if (cfg->arch.omit_fp) {
6650                 /*
6651                  * On enter, the stack is misaligned by the pushing of the return
6652                  * address. It is either made aligned by the pushing of %rbp, or by
6653                  * this.
6654                  */
6655                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6656                 if ((alloc_size % 16) == 0) {
6657                         alloc_size += 8;
6658                         /* Mark the padding slot as NOREF */
6659                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6660                 }
6661         } else {
6662                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6663                 if (cfg->stack_offset != alloc_size) {
6664                         /* Mark the padding slot as NOREF */
6665                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6666                 }
6667                 cfg->arch.sp_fp_offset = alloc_size;
6668                 alloc_size -= pos;
6669         }
6670
6671         cfg->arch.stack_alloc_size = alloc_size;
6672
6673         /* Allocate stack frame */
6674 #ifdef TARGET_WIN32
6675         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6676 #else
6677         if (alloc_size) {
6678                 /* See mono_emit_stack_alloc */
6679 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6680                 guint32 remaining_size = alloc_size;
6681
6682                 /* Use a loop for large sizes */
6683                 if (remaining_size > 10 * 0x1000) {
6684                         amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6685                         guint8 *label = code;
6686                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6687                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6688                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6689                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6690                         guint8 *label2 = code;
6691                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
6692                         amd64_patch (label2, label);
6693                         if (cfg->arch.omit_fp) {
6694                                 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6695                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6696                         }
6697
6698                         remaining_size = remaining_size % 0x1000;
6699                 }
6700
6701                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6702                 guint32 offset = code - cfg->native_code;
6703                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6704                         while (required_code_size >= (cfg->code_size - offset))
6705                                 cfg->code_size *= 2;
6706                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6707                         code = cfg->native_code + offset;
6708                         cfg->stat_code_reallocs++;
6709                 }
6710
6711                 while (remaining_size >= 0x1000) {
6712                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6713                         if (cfg->arch.omit_fp) {
6714                                 cfa_offset += 0x1000;
6715                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6716                         }
6717                         async_exc_point (code);
6718
6719                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6720                         remaining_size -= 0x1000;
6721                 }
6722                 if (remaining_size) {
6723                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6724                         if (cfg->arch.omit_fp) {
6725                                 cfa_offset += remaining_size;
6726                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6727                                 async_exc_point (code);
6728                         }
6729                 }
6730 #else
6731                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6732                 if (cfg->arch.omit_fp) {
6733                         cfa_offset += alloc_size;
6734                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6735                         async_exc_point (code);
6736                 }
6737 #endif
6738         }
6739 #endif
6740
6741         /* Stack alignment check */
6742 #if 0
6743         {
6744                 guint8 *buf;
6745
6746                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6747                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6748                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6749                 buf = code;
6750                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6751                 amd64_breakpoint (code);
6752                 amd64_patch (buf, code);
6753         }
6754 #endif
6755
6756         if (mini_get_debug_options ()->init_stacks) {
6757                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6758
6759                 /* Save registers to the red zone */
6760                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6761                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6762
6763                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6764                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6765                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6766
6767                 amd64_cld (code);
6768                 amd64_prefix (code, X86_REP_PREFIX);
6769                 amd64_stosl (code);
6770
6771                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6772                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6773         }
6774
6775         /* Save LMF */
6776         if (method->save_lmf)
6777                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6778
6779         /* Save callee saved registers */
6780         if (cfg->arch.omit_fp) {
6781                 save_area_offset = cfg->arch.reg_save_area_offset;
6782                 /* Save caller saved registers after sp is adjusted */
6783                 /* The registers are saved at the bottom of the frame */
6784                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6785         } else {
6786                 /* The registers are saved just below the saved rbp */
6787                 save_area_offset = cfg->arch.reg_save_area_offset;
6788         }
6789
6790         for (i = 0; i < AMD64_NREG; ++i) {
6791                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6792                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6793
6794                         if (cfg->arch.omit_fp) {
6795                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6796                                 /* These are handled automatically by the stack marking code */
6797                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6798                         } else {
6799                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6800                                 // FIXME: GC
6801                         }
6802
6803                         save_area_offset += 8;
6804                         async_exc_point (code);
6805                 }
6806         }
6807
6808         /* store runtime generic context */
6809         if (cfg->rgctx_var) {
6810                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6811                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6812
6813                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6814
6815                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6816                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6817         }
6818
6819         /* compute max_length in order to use short forward jumps */
6820         max_epilog_size = get_max_epilog_size (cfg);
6821         if (cfg->opt & MONO_OPT_BRANCH) {
6822                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6823                         MonoInst *ins;
6824                         int max_length = 0;
6825
6826                         /* max alignment for loops */
6827                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6828                                 max_length += LOOP_ALIGNMENT;
6829
6830                         MONO_BB_FOR_EACH_INS (bb, ins) {
6831                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6832                         }
6833
6834                         /* Take prolog and epilog instrumentation into account */
6835                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6836                                 max_length += max_epilog_size;
6837
6838                         bb->max_length = max_length;
6839                 }
6840         }
6841
6842         sig = mono_method_signature (method);
6843         pos = 0;
6844
6845         cinfo = (CallInfo *)cfg->arch.cinfo;
6846
6847         if (sig->ret->type != MONO_TYPE_VOID) {
6848                 /* Save volatile arguments to the stack */
6849                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6850                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6851         }
6852
6853         /* Keep this in sync with emit_load_volatile_arguments */
6854         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6855                 ArgInfo *ainfo = cinfo->args + i;
6856
6857                 ins = cfg->args [i];
6858
6859                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6860                         /* Unused arguments */
6861                         continue;
6862
6863                 /* Save volatile arguments to the stack */
6864                 if (ins->opcode != OP_REGVAR) {
6865                         switch (ainfo->storage) {
6866                         case ArgInIReg: {
6867                                 guint32 size = 8;
6868
6869                                 /* FIXME: I1 etc */
6870                                 /*
6871                                 if (stack_offset & 0x1)
6872                                         size = 1;
6873                                 else if (stack_offset & 0x2)
6874                                         size = 2;
6875                                 else if (stack_offset & 0x4)
6876                                         size = 4;
6877                                 else
6878                                         size = 8;
6879                                 */
6880                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6881
6882                                 /*
6883                                  * Save the original location of 'this',
6884                                  * get_generic_info_from_stack_frame () needs this to properly look up
6885                                  * the argument value during the handling of async exceptions.
6886                                  */
6887                                 if (ins == cfg->args [0]) {
6888                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6889                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6890                                 }
6891                                 break;
6892                         }
6893                         case ArgInFloatSSEReg:
6894                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6895                                 break;
6896                         case ArgInDoubleSSEReg:
6897                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6898                                 break;
6899                         case ArgValuetypeInReg:
6900                                 for (quad = 0; quad < 2; quad ++) {
6901                                         switch (ainfo->pair_storage [quad]) {
6902                                         case ArgInIReg:
6903                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6904                                                 break;
6905                                         case ArgInFloatSSEReg:
6906                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6907                                                 break;
6908                                         case ArgInDoubleSSEReg:
6909                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6910                                                 break;
6911                                         case ArgNone:
6912                                                 break;
6913                                         default:
6914                                                 g_assert_not_reached ();
6915                                         }
6916                                 }
6917                                 break;
6918                         case ArgValuetypeAddrInIReg:
6919                                 if (ainfo->pair_storage [0] == ArgInIReg)
6920                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6921                                 break;
6922                         case ArgValuetypeAddrOnStack:
6923                                 break;
6924                         case ArgGSharedVtInReg:
6925                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6926                                 break;
6927                         default:
6928                                 break;
6929                         }
6930                 } else {
6931                         /* Argument allocated to (non-volatile) register */
6932                         switch (ainfo->storage) {
6933                         case ArgInIReg:
6934                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6935                                 break;
6936                         case ArgOnStack:
6937                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6938                                 break;
6939                         default:
6940                                 g_assert_not_reached ();
6941                         }
6942
6943                         if (ins == cfg->args [0]) {
6944                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6945                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6946                         }
6947                 }
6948         }
6949
6950         if (cfg->method->save_lmf)
6951                 args_clobbered = TRUE;
6952
6953         if (trace) {
6954                 args_clobbered = TRUE;
6955                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6956         }
6957
6958         /*
6959          * Optimize the common case of the first bblock making a call with the same
6960          * arguments as the method. This works because the arguments are still in their
6961          * original argument registers.
6962          * FIXME: Generalize this
6963          */
6964         if (!args_clobbered) {
6965                 MonoBasicBlock *first_bb = cfg->bb_entry;
6966                 MonoInst *next;
6967                 int filter = FILTER_IL_SEQ_POINT;
6968
6969                 next = mono_bb_first_inst (first_bb, filter);
6970                 if (!next && first_bb->next_bb) {
6971                         first_bb = first_bb->next_bb;
6972                         next = mono_bb_first_inst (first_bb, filter);
6973                 }
6974
6975                 if (first_bb->in_count > 1)
6976                         next = NULL;
6977
6978                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6979                         ArgInfo *ainfo = cinfo->args + i;
6980                         gboolean match = FALSE;
6981
6982                         ins = cfg->args [i];
6983                         if (ins->opcode != OP_REGVAR) {
6984                                 switch (ainfo->storage) {
6985                                 case ArgInIReg: {
6986                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6987                                                 if (next->dreg == ainfo->reg) {
6988                                                         NULLIFY_INS (next);
6989                                                         match = TRUE;
6990                                                 } else {
6991                                                         next->opcode = OP_MOVE;
6992                                                         next->sreg1 = ainfo->reg;
6993                                                         /* Only continue if the instruction doesn't change argument regs */
6994                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6995                                                                 match = TRUE;
6996                                                 }
6997                                         }
6998                                         break;
6999                                 }
7000                                 default:
7001                                         break;
7002                                 }
7003                         } else {
7004                                 /* Argument allocated to (non-volatile) register */
7005                                 switch (ainfo->storage) {
7006                                 case ArgInIReg:
7007                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7008                                                 NULLIFY_INS (next);
7009                                                 match = TRUE;
7010                                         }
7011                                         break;
7012                                 default:
7013                                         break;
7014                                 }
7015                         }
7016
7017                         if (match) {
7018                                 next = mono_inst_next (next, filter);
7019                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7020                                 if (!next)
7021                                         break;
7022                         }
7023                 }
7024         }
7025
7026         if (cfg->gen_sdb_seq_points) {
7027                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7028
7029                 /* Initialize seq_point_info_var */
7030                 if (cfg->compile_aot) {
7031                         /* Initialize the variable from a GOT slot */
7032                         /* Same as OP_AOTCONST */
7033                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7034                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7035                         g_assert (info_var->opcode == OP_REGOFFSET);
7036                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7037                 }
7038
7039                 if (cfg->compile_aot) {
7040                         /* Initialize ss_tramp_var */
7041                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7042                         g_assert (ins->opcode == OP_REGOFFSET);
7043
7044                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7045                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7046                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7047                 } else {
7048                         /* Initialize ss_tramp_var */
7049                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7050                         g_assert (ins->opcode == OP_REGOFFSET);
7051
7052                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7053                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7054
7055                         /* Initialize bp_tramp_var */
7056                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7057                         g_assert (ins->opcode == OP_REGOFFSET);
7058
7059                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7060                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7061                 }
7062         }
7063
7064         cfg->code_len = code - cfg->native_code;
7065
7066         g_assert (cfg->code_len < cfg->code_size);
7067
7068         return code;
7069 }
7070
7071 void
7072 mono_arch_emit_epilog (MonoCompile *cfg)
7073 {
7074         MonoMethod *method = cfg->method;
7075         int quad, i;
7076         guint8 *code;
7077         int max_epilog_size;
7078         CallInfo *cinfo;
7079         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7080         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7081
7082         max_epilog_size = get_max_epilog_size (cfg);
7083
7084         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7085                 cfg->code_size *= 2;
7086                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7087                 cfg->stat_code_reallocs++;
7088         }
7089         code = cfg->native_code + cfg->code_len;
7090
7091         cfg->has_unwind_info_for_epilog = TRUE;
7092
7093         /* Mark the start of the epilog */
7094         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7095
7096         /* Save the uwind state which is needed by the out-of-line code */
7097         mono_emit_unwind_op_remember_state (cfg, code);
7098
7099         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7100                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7101
7102         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7103
7104         if (method->save_lmf) {
7105                 /* check if we need to restore protection of the stack after a stack overflow */
7106                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7107                         guint8 *patch;
7108                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7109                         /* we load the value in a separate instruction: this mechanism may be
7110                          * used later as a safer way to do thread interruption
7111                          */
7112                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7113                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7114                         patch = code;
7115                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7116                         /* note that the call trampoline will preserve eax/edx */
7117                         x86_call_reg (code, X86_ECX);
7118                         x86_patch (patch, code);
7119                 } else {
7120                         /* FIXME: maybe save the jit tls in the prolog */
7121                 }
7122                 if (cfg->used_int_regs & (1 << AMD64_RBP))
7123                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7124                 if (cfg->arch.omit_fp)
7125                         /*
7126                          * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
7127                          * since its stack slot will become invalid.
7128                          */
7129                         mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7130         }
7131
7132         /* Restore callee saved regs */
7133         for (i = 0; i < AMD64_NREG; ++i) {
7134                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7135                         /* Restore only used_int_regs, not arch.saved_iregs */
7136 #if defined(MONO_SUPPORT_TASKLETS)
7137                         int restore_reg = 1;
7138 #else
7139                         int restore_reg = (cfg->used_int_regs & (1 << i));
7140 #endif
7141                         if (restore_reg) {
7142                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7143                                 mono_emit_unwind_op_same_value (cfg, code, i);
7144                                 async_exc_point (code);
7145                         }
7146                         save_area_offset += 8;
7147                 }
7148         }
7149
7150         /* Load returned vtypes into registers if needed */
7151         cinfo = (CallInfo *)cfg->arch.cinfo;
7152         if (cinfo->ret.storage == ArgValuetypeInReg) {
7153                 ArgInfo *ainfo = &cinfo->ret;
7154                 MonoInst *inst = cfg->ret;
7155
7156                 for (quad = 0; quad < 2; quad ++) {
7157                         switch (ainfo->pair_storage [quad]) {
7158                         case ArgInIReg:
7159                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7160                                 break;
7161                         case ArgInFloatSSEReg:
7162                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7163                                 break;
7164                         case ArgInDoubleSSEReg:
7165                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7166                                 break;
7167                         case ArgNone:
7168                                 break;
7169                         default:
7170                                 g_assert_not_reached ();
7171                         }
7172                 }
7173         }
7174
7175         if (cfg->arch.omit_fp) {
7176                 if (cfg->arch.stack_alloc_size) {
7177                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7178                 }
7179         } else {
7180 #ifdef TARGET_WIN32
7181                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7182                 amd64_pop_reg (code, AMD64_RBP);
7183                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7184 #else
7185                 amd64_leave (code);
7186                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7187 #endif
7188         }
7189         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7190         async_exc_point (code);
7191         amd64_ret (code);
7192
7193         /* Restore the unwind state to be the same as before the epilog */
7194         mono_emit_unwind_op_restore_state (cfg, code);
7195
7196         cfg->code_len = code - cfg->native_code;
7197
7198         g_assert (cfg->code_len < cfg->code_size);
7199 }
7200
7201 void
7202 mono_arch_emit_exceptions (MonoCompile *cfg)
7203 {
7204         MonoJumpInfo *patch_info;
7205         int nthrows, i;
7206         guint8 *code;
7207         MonoClass *exc_classes [16];
7208         guint8 *exc_throw_start [16], *exc_throw_end [16];
7209         guint32 code_size = 0;
7210
7211         /* Compute needed space */
7212         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7213                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7214                         code_size += 40;
7215                 if (patch_info->type == MONO_PATCH_INFO_R8)
7216                         code_size += 8 + 15; /* sizeof (double) + alignment */
7217                 if (patch_info->type == MONO_PATCH_INFO_R4)
7218                         code_size += 4 + 15; /* sizeof (float) + alignment */
7219                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7220                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7221         }
7222
7223         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7224                 cfg->code_size *= 2;
7225                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7226                 cfg->stat_code_reallocs++;
7227         }
7228
7229         code = cfg->native_code + cfg->code_len;
7230
7231         /* add code to raise exceptions */
7232         nthrows = 0;
7233         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7234                 switch (patch_info->type) {
7235                 case MONO_PATCH_INFO_EXC: {
7236                         MonoClass *exc_class;
7237                         guint8 *buf, *buf2;
7238                         guint32 throw_ip;
7239
7240                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7241
7242                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7243                         throw_ip = patch_info->ip.i;
7244
7245                         //x86_breakpoint (code);
7246                         /* Find a throw sequence for the same exception class */
7247                         for (i = 0; i < nthrows; ++i)
7248                                 if (exc_classes [i] == exc_class)
7249                                         break;
7250                         if (i < nthrows) {
7251                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7252                                 x86_jump_code (code, exc_throw_start [i]);
7253                                 patch_info->type = MONO_PATCH_INFO_NONE;
7254                         }
7255                         else {
7256                                 buf = code;
7257                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7258                                 buf2 = code;
7259
7260                                 if (nthrows < 16) {
7261                                         exc_classes [nthrows] = exc_class;
7262                                         exc_throw_start [nthrows] = code;
7263                                 }
7264                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7265
7266                                 patch_info->type = MONO_PATCH_INFO_NONE;
7267
7268                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7269
7270                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7271                                 while (buf < buf2)
7272                                         x86_nop (buf);
7273
7274                                 if (nthrows < 16) {
7275                                         exc_throw_end [nthrows] = code;
7276                                         nthrows ++;
7277                                 }
7278                         }
7279                         break;
7280                 }
7281                 default:
7282                         /* do nothing */
7283                         break;
7284                 }
7285                 g_assert(code < cfg->native_code + cfg->code_size);
7286         }
7287
7288         /* Handle relocations with RIP relative addressing */
7289         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7290                 gboolean remove = FALSE;
7291                 guint8 *orig_code = code;
7292
7293                 switch (patch_info->type) {
7294                 case MONO_PATCH_INFO_R8:
7295                 case MONO_PATCH_INFO_R4: {
7296                         guint8 *pos, *patch_pos;
7297                         guint32 target_pos;
7298
7299                         /* The SSE opcodes require a 16 byte alignment */
7300                         code = (guint8*)ALIGN_TO (code, 16);
7301
7302                         pos = cfg->native_code + patch_info->ip.i;
7303                         if (IS_REX (pos [1])) {
7304                                 patch_pos = pos + 5;
7305                                 target_pos = code - pos - 9;
7306                         }
7307                         else {
7308                                 patch_pos = pos + 4;
7309                                 target_pos = code - pos - 8;
7310                         }
7311
7312                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7313                                 *(double*)code = *(double*)patch_info->data.target;
7314                                 code += sizeof (double);
7315                         } else {
7316                                 *(float*)code = *(float*)patch_info->data.target;
7317                                 code += sizeof (float);
7318                         }
7319
7320                         *(guint32*)(patch_pos) = target_pos;
7321
7322                         remove = TRUE;
7323                         break;
7324                 }
7325                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7326                         guint8 *pos;
7327
7328                         if (cfg->compile_aot)
7329                                 continue;
7330
7331                         /*loading is faster against aligned addresses.*/
7332                         code = (guint8*)ALIGN_TO (code, 8);
7333                         memset (orig_code, 0, code - orig_code);
7334
7335                         pos = cfg->native_code + patch_info->ip.i;
7336
7337                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7338                         if (IS_REX (pos [1]))
7339                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7340                         else
7341                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7342
7343                         *(gpointer*)code = (gpointer)patch_info->data.target;
7344                         code += sizeof (gpointer);
7345
7346                         remove = TRUE;
7347                         break;
7348                 }
7349                 default:
7350                         break;
7351                 }
7352
7353                 if (remove) {
7354                         if (patch_info == cfg->patch_info)
7355                                 cfg->patch_info = patch_info->next;
7356                         else {
7357                                 MonoJumpInfo *tmp;
7358
7359                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7360                                         ;
7361                                 tmp->next = patch_info->next;
7362                         }
7363                 }
7364                 g_assert (code < cfg->native_code + cfg->code_size);
7365         }
7366
7367         cfg->code_len = code - cfg->native_code;
7368
7369         g_assert (cfg->code_len < cfg->code_size);
7370
7371 }
7372
7373 #endif /* DISABLE_JIT */
7374
7375 void*
7376 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7377 {
7378         guchar *code = (guchar *)p;
7379         MonoMethodSignature *sig;
7380         MonoInst *inst;
7381         int i, n, stack_area = 0;
7382
7383         /* Keep this in sync with mono_arch_get_argument_info */
7384
7385         if (enable_arguments) {
7386                 /* Allocate a new area on the stack and save arguments there */
7387                 sig = mono_method_signature (cfg->method);
7388
7389                 n = sig->param_count + sig->hasthis;
7390
7391                 stack_area = ALIGN_TO (n * 8, 16);
7392
7393                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7394
7395                 for (i = 0; i < n; ++i) {
7396                         inst = cfg->args [i];
7397
7398                         if (inst->opcode == OP_REGVAR)
7399                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7400                         else {
7401                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7402                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7403                         }
7404                 }
7405         }
7406
7407         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7408         amd64_set_reg_template (code, AMD64_ARG_REG1);
7409         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7410         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7411
7412         if (enable_arguments)
7413                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7414
7415         return code;
7416 }
7417
7418 enum {
7419         SAVE_NONE,
7420         SAVE_STRUCT,
7421         SAVE_EAX,
7422         SAVE_EAX_EDX,
7423         SAVE_XMM
7424 };
7425
7426 void*
7427 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7428 {
7429         guchar *code = (guchar *)p;
7430         int save_mode = SAVE_NONE;
7431         MonoMethod *method = cfg->method;
7432         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7433         int i;
7434
7435         switch (ret_type->type) {
7436         case MONO_TYPE_VOID:
7437                 /* special case string .ctor icall */
7438                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7439                         save_mode = SAVE_EAX;
7440                 else
7441                         save_mode = SAVE_NONE;
7442                 break;
7443         case MONO_TYPE_I8:
7444         case MONO_TYPE_U8:
7445                 save_mode = SAVE_EAX;
7446                 break;
7447         case MONO_TYPE_R4:
7448         case MONO_TYPE_R8:
7449                 save_mode = SAVE_XMM;
7450                 break;
7451         case MONO_TYPE_GENERICINST:
7452                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7453                         save_mode = SAVE_EAX;
7454                         break;
7455                 }
7456                 /* Fall through */
7457         case MONO_TYPE_VALUETYPE:
7458                 save_mode = SAVE_STRUCT;
7459                 break;
7460         default:
7461                 save_mode = SAVE_EAX;
7462                 break;
7463         }
7464
7465         /* Save the result and copy it into the proper argument register */
7466         switch (save_mode) {
7467         case SAVE_EAX:
7468                 amd64_push_reg (code, AMD64_RAX);
7469                 /* Align stack */
7470                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7471                 if (enable_arguments)
7472                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7473                 break;
7474         case SAVE_STRUCT:
7475                 /* FIXME: */
7476                 if (enable_arguments)
7477                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7478                 break;
7479         case SAVE_XMM:
7480                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7481                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7482                 /* Align stack */
7483                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7484                 /*
7485                  * The result is already in the proper argument register so no copying
7486                  * needed.
7487                  */
7488                 break;
7489         case SAVE_NONE:
7490                 break;
7491         default:
7492                 g_assert_not_reached ();
7493         }
7494
7495         /* Set %al since this is a varargs call */
7496         if (save_mode == SAVE_XMM)
7497                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7498         else
7499                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7500
7501         if (preserve_argument_registers) {
7502                 for (i = 0; i < PARAM_REGS; ++i)
7503                         amd64_push_reg (code, param_regs [i]);
7504         }
7505
7506         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7507         amd64_set_reg_template (code, AMD64_ARG_REG1);
7508         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7509
7510         if (preserve_argument_registers) {
7511                 for (i = PARAM_REGS - 1; i >= 0; --i)
7512                         amd64_pop_reg (code, param_regs [i]);
7513         }
7514
7515         /* Restore result */
7516         switch (save_mode) {
7517         case SAVE_EAX:
7518                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7519                 amd64_pop_reg (code, AMD64_RAX);
7520                 break;
7521         case SAVE_STRUCT:
7522                 /* FIXME: */
7523                 break;
7524         case SAVE_XMM:
7525                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7526                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7527                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7528                 break;
7529         case SAVE_NONE:
7530                 break;
7531         default:
7532                 g_assert_not_reached ();
7533         }
7534
7535         return code;
7536 }
7537
7538 void
7539 mono_arch_flush_icache (guint8 *code, gint size)
7540 {
7541         /* Not needed */
7542 }
7543
7544 void
7545 mono_arch_flush_register_windows (void)
7546 {
7547 }
7548
7549 gboolean
7550 mono_arch_is_inst_imm (gint64 imm)
7551 {
7552         return amd64_use_imm32 (imm);
7553 }
7554
7555 /*
7556  * Determine whenever the trap whose info is in SIGINFO is caused by
7557  * integer overflow.
7558  */
7559 gboolean
7560 mono_arch_is_int_overflow (void *sigctx, void *info)
7561 {
7562         MonoContext ctx;
7563         guint8* rip;
7564         int reg;
7565         gint64 value;
7566
7567         mono_sigctx_to_monoctx (sigctx, &ctx);
7568
7569         rip = (guint8*)ctx.gregs [AMD64_RIP];
7570
7571         if (IS_REX (rip [0])) {
7572                 reg = amd64_rex_b (rip [0]);
7573                 rip ++;
7574         }
7575         else
7576                 reg = 0;
7577
7578         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7579                 /* idiv REG */
7580                 reg += x86_modrm_rm (rip [1]);
7581
7582                 value = ctx.gregs [reg];
7583
7584                 if (value == -1)
7585                         return TRUE;
7586         }
7587
7588         return FALSE;
7589 }
7590
7591 guint32
7592 mono_arch_get_patch_offset (guint8 *code)
7593 {
7594         return 3;
7595 }
7596
7597 /**
7598  * \return TRUE if no sw breakpoint was present.
7599  *
7600  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7601  * breakpoints in the original code, they are removed in the copy.
7602  */
7603 gboolean
7604 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7605 {
7606         /*
7607          * If method_start is non-NULL we need to perform bound checks, since we access memory
7608          * at code - offset we could go before the start of the method and end up in a different
7609          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7610          * instead.
7611          */
7612         if (!method_start || code - offset >= method_start) {
7613                 memcpy (buf, code - offset, size);
7614         } else {
7615                 int diff = code - method_start;
7616                 memset (buf, 0, size);
7617                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7618         }
7619         return TRUE;
7620 }
7621
7622 int
7623 mono_arch_get_this_arg_reg (guint8 *code)
7624 {
7625         return AMD64_ARG_REG1;
7626 }
7627
7628 gpointer
7629 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7630 {
7631         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7632 }
7633
7634 #define MAX_ARCH_DELEGATE_PARAMS 10
7635
7636 static gpointer
7637 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7638 {
7639         guint8 *code, *start;
7640         GSList *unwind_ops = NULL;
7641         int i;
7642
7643         unwind_ops = mono_arch_get_cie_program ();
7644
7645         if (has_target) {
7646                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7647
7648                 /* Replace the this argument with the target */
7649                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7650                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7651                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7652
7653                 g_assert ((code - start) < 64);
7654                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7655         } else {
7656                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7657
7658                 if (param_count == 0) {
7659                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7660                 } else {
7661                         /* We have to shift the arguments left */
7662                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7663                         for (i = 0; i < param_count; ++i) {
7664 #ifdef TARGET_WIN32
7665                                 if (i < 3)
7666                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7667                                 else
7668                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7669 #else
7670                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7671 #endif
7672                         }
7673
7674                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7675                 }
7676                 g_assert ((code - start) < 64);
7677                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7678         }
7679
7680         mono_arch_flush_icache (start, code - start);
7681
7682         if (has_target) {
7683                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7684         } else {
7685                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7686                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7687                 g_free (name);
7688         }
7689
7690         if (mono_jit_map_is_enabled ()) {
7691                 char *buff;
7692                 if (has_target)
7693                         buff = (char*)"delegate_invoke_has_target";
7694                 else
7695                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7696                 mono_emit_jit_tramp (start, code - start, buff);
7697                 if (!has_target)
7698                         g_free (buff);
7699         }
7700         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7701
7702         return start;
7703 }
7704
7705 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7706
7707 static gpointer
7708 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7709 {
7710         guint8 *code, *start;
7711         int size = 20;
7712         char *tramp_name;
7713         GSList *unwind_ops;
7714
7715         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7716                 return NULL;
7717
7718         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7719
7720         unwind_ops = mono_arch_get_cie_program ();
7721
7722         /* Replace the this argument with the target */
7723         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7724         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7725
7726         if (load_imt_reg) {
7727                 /* Load the IMT reg */
7728                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7729         }
7730
7731         /* Load the vtable */
7732         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7733         amd64_jump_membase (code, AMD64_RAX, offset);
7734         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7735
7736         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7737         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7738         g_free (tramp_name);
7739
7740         return start;
7741 }
7742
7743 /*
7744  * mono_arch_get_delegate_invoke_impls:
7745  *
7746  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7747  * trampolines.
7748  */
7749 GSList*
7750 mono_arch_get_delegate_invoke_impls (void)
7751 {
7752         GSList *res = NULL;
7753         MonoTrampInfo *info;
7754         int i;
7755
7756         get_delegate_invoke_impl (&info, TRUE, 0);
7757         res = g_slist_prepend (res, info);
7758
7759         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7760                 get_delegate_invoke_impl (&info, FALSE, i);
7761                 res = g_slist_prepend (res, info);
7762         }
7763
7764         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7765                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7766                 res = g_slist_prepend (res, info);
7767         }
7768
7769         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7770                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7771                 res = g_slist_prepend (res, info);
7772                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7773                 res = g_slist_prepend (res, info);
7774         }
7775
7776         return res;
7777 }
7778
7779 gpointer
7780 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7781 {
7782         guint8 *code, *start;
7783         int i;
7784
7785         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7786                 return NULL;
7787
7788         /* FIXME: Support more cases */
7789         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7790                 return NULL;
7791
7792         if (has_target) {
7793                 static guint8* cached = NULL;
7794
7795                 if (cached)
7796                         return cached;
7797
7798                 if (mono_aot_only) {
7799                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7800                 } else {
7801                         MonoTrampInfo *info;
7802                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7803                         mono_tramp_info_register (info, NULL);
7804                 }
7805
7806                 mono_memory_barrier ();
7807
7808                 cached = start;
7809         } else {
7810                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7811                 for (i = 0; i < sig->param_count; ++i)
7812                         if (!mono_is_regsize_var (sig->params [i]))
7813                                 return NULL;
7814                 if (sig->param_count > 4)
7815                         return NULL;
7816
7817                 code = cache [sig->param_count];
7818                 if (code)
7819                         return code;
7820
7821                 if (mono_aot_only) {
7822                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7823                         start = (guint8 *)mono_aot_get_trampoline (name);
7824                         g_free (name);
7825                 } else {
7826                         MonoTrampInfo *info;
7827                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7828                         mono_tramp_info_register (info, NULL);
7829                 }
7830
7831                 mono_memory_barrier ();
7832
7833                 cache [sig->param_count] = start;
7834         }
7835
7836         return start;
7837 }
7838
7839 gpointer
7840 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7841 {
7842         MonoTrampInfo *info;
7843         gpointer code;
7844
7845         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7846         if (code)
7847                 mono_tramp_info_register (info, NULL);
7848         return code;
7849 }
7850
7851 void
7852 mono_arch_finish_init (void)
7853 {
7854 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7855         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7856 #endif
7857 }
7858
7859 void
7860 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7861 {
7862 }
7863
7864 #define CMP_SIZE (6 + 1)
7865 #define CMP_REG_REG_SIZE (4 + 1)
7866 #define BR_SMALL_SIZE 2
7867 #define BR_LARGE_SIZE 6
7868 #define MOV_REG_IMM_SIZE 10
7869 #define MOV_REG_IMM_32BIT_SIZE 6
7870 #define JUMP_REG_SIZE (2 + 1)
7871
7872 static int
7873 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7874 {
7875         int i, distance = 0;
7876         for (i = start; i < target; ++i)
7877                 distance += imt_entries [i]->chunk_size;
7878         return distance;
7879 }
7880
7881 /*
7882  * LOCKING: called with the domain lock held
7883  */
7884 gpointer
7885 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7886         gpointer fail_tramp)
7887 {
7888         int i;
7889         int size = 0;
7890         guint8 *code, *start;
7891         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7892         GSList *unwind_ops;
7893
7894         for (i = 0; i < count; ++i) {
7895                 MonoIMTCheckItem *item = imt_entries [i];
7896                 if (item->is_equals) {
7897                         if (item->check_target_idx) {
7898                                 if (!item->compare_done) {
7899                                         if (amd64_use_imm32 ((gint64)item->key))
7900                                                 item->chunk_size += CMP_SIZE;
7901                                         else
7902                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7903                                 }
7904                                 if (item->has_target_code) {
7905                                         item->chunk_size += MOV_REG_IMM_SIZE;
7906                                 } else {
7907                                         if (vtable_is_32bit)
7908                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7909                                         else
7910                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7911                                 }
7912                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7913                         } else {
7914                                 if (fail_tramp) {
7915                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7916                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7917                                 } else {
7918                                         if (vtable_is_32bit)
7919                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7920                                         else
7921                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7922                                         item->chunk_size += JUMP_REG_SIZE;
7923                                         /* with assert below:
7924                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7925                                          */
7926                                 }
7927                         }
7928                 } else {
7929                         if (amd64_use_imm32 ((gint64)item->key))
7930                                 item->chunk_size += CMP_SIZE;
7931                         else
7932                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7933                         item->chunk_size += BR_LARGE_SIZE;
7934                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7935                 }
7936                 size += item->chunk_size;
7937         }
7938         if (fail_tramp)
7939                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7940         else
7941                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7942         start = code;
7943
7944         unwind_ops = mono_arch_get_cie_program ();
7945
7946         for (i = 0; i < count; ++i) {
7947                 MonoIMTCheckItem *item = imt_entries [i];
7948                 item->code_target = code;
7949                 if (item->is_equals) {
7950                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7951
7952                         if (item->check_target_idx || fail_case) {
7953                                 if (!item->compare_done || fail_case) {
7954                                         if (amd64_use_imm32 ((gint64)item->key))
7955                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7956                                         else {
7957                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7958                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7959                                         }
7960                                 }
7961                                 item->jmp_code = code;
7962                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7963                                 if (item->has_target_code) {
7964                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7965                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7966                                 } else {
7967                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7968                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7969                                 }
7970
7971                                 if (fail_case) {
7972                                         amd64_patch (item->jmp_code, code);
7973                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7974                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7975                                         item->jmp_code = NULL;
7976                                 }
7977                         } else {
7978                                 /* enable the commented code to assert on wrong method */
7979 #if 0
7980                                 if (amd64_is_imm32 (item->key))
7981                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7982                                 else {
7983                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7984                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7985                                 }
7986                                 item->jmp_code = code;
7987                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7988                                 /* See the comment below about R10 */
7989                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7990                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7991                                 amd64_patch (item->jmp_code, code);
7992                                 amd64_breakpoint (code);
7993                                 item->jmp_code = NULL;
7994 #else
7995                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7996                                    needs to be preserved.  R10 needs
7997                                    to be preserved for calls which
7998                                    require a runtime generic context,
7999                                    but interface calls don't. */
8000                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8001                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8002 #endif
8003                         }
8004                 } else {
8005                         if (amd64_use_imm32 ((gint64)item->key))
8006                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8007                         else {
8008                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8009                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8010                         }
8011                         item->jmp_code = code;
8012                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8013                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8014                         else
8015                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8016                 }
8017                 g_assert (code - item->code_target <= item->chunk_size);
8018         }
8019         /* patch the branches to get to the target items */
8020         for (i = 0; i < count; ++i) {
8021                 MonoIMTCheckItem *item = imt_entries [i];
8022                 if (item->jmp_code) {
8023                         if (item->check_target_idx) {
8024                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8025                         }
8026                 }
8027         }
8028
8029         if (!fail_tramp)
8030                 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
8031         g_assert (code - start <= size);
8032         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8033
8034         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8035
8036         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8037
8038         return start;
8039 }
8040
8041 MonoMethod*
8042 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8043 {
8044         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8045 }
8046
8047 MonoVTable*
8048 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8049 {
8050         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8051 }
8052
8053 GSList*
8054 mono_arch_get_cie_program (void)
8055 {
8056         GSList *l = NULL;
8057
8058         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8059         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8060
8061         return l;
8062 }
8063
8064 #ifndef DISABLE_JIT
8065
8066 MonoInst*
8067 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8068 {
8069         MonoInst *ins = NULL;
8070         int opcode = 0;
8071
8072         if (cmethod->klass == mono_defaults.math_class) {
8073                 if (strcmp (cmethod->name, "Sin") == 0) {
8074                         opcode = OP_SIN;
8075                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8076                         opcode = OP_COS;
8077                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8078                         opcode = OP_SQRT;
8079                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8080                         opcode = OP_ABS;
8081                 }
8082
8083                 if (opcode && fsig->param_count == 1) {
8084                         MONO_INST_NEW (cfg, ins, opcode);
8085                         ins->type = STACK_R8;
8086                         ins->dreg = mono_alloc_freg (cfg);
8087                         ins->sreg1 = args [0]->dreg;
8088                         MONO_ADD_INS (cfg->cbb, ins);
8089                 }
8090
8091                 opcode = 0;
8092                 if (cfg->opt & MONO_OPT_CMOV) {
8093                         if (strcmp (cmethod->name, "Min") == 0) {
8094                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8095                                         opcode = OP_IMIN;
8096                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8097                                         opcode = OP_IMIN_UN;
8098                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8099                                         opcode = OP_LMIN;
8100                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8101                                         opcode = OP_LMIN_UN;
8102                         } else if (strcmp (cmethod->name, "Max") == 0) {
8103                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8104                                         opcode = OP_IMAX;
8105                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8106                                         opcode = OP_IMAX_UN;
8107                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8108                                         opcode = OP_LMAX;
8109                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8110                                         opcode = OP_LMAX_UN;
8111                         }
8112                 }
8113
8114                 if (opcode && fsig->param_count == 2) {
8115                         MONO_INST_NEW (cfg, ins, opcode);
8116                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8117                         ins->dreg = mono_alloc_ireg (cfg);
8118                         ins->sreg1 = args [0]->dreg;
8119                         ins->sreg2 = args [1]->dreg;
8120                         MONO_ADD_INS (cfg->cbb, ins);
8121                 }
8122
8123 #if 0
8124                 /* OP_FREM is not IEEE compatible */
8125                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8126                         MONO_INST_NEW (cfg, ins, OP_FREM);
8127                         ins->inst_i0 = args [0];
8128                         ins->inst_i1 = args [1];
8129                 }
8130 #endif
8131         }
8132
8133         return ins;
8134 }
8135 #endif
8136
8137 mgreg_t
8138 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8139 {
8140         return ctx->gregs [reg];
8141 }
8142
8143 void
8144 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8145 {
8146         ctx->gregs [reg] = val;
8147 }
8148
8149 /*
8150  * mono_arch_emit_load_aotconst:
8151  *
8152  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8153  * TARGET from the mscorlib GOT in full-aot code.
8154  * On AMD64, the result is placed into R11.
8155  */
8156 guint8*
8157 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8158 {
8159         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8160         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8161
8162         return code;
8163 }
8164
8165 /*
8166  * mono_arch_get_trampolines:
8167  *
8168  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8169  * for AOT.
8170  */
8171 GSList *
8172 mono_arch_get_trampolines (gboolean aot)
8173 {
8174         return mono_amd64_get_exception_trampolines (aot);
8175 }
8176
8177 /* Soft Debug support */
8178 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8179
8180 /*
8181  * mono_arch_set_breakpoint:
8182  *
8183  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8184  * The location should contain code emitted by OP_SEQ_POINT.
8185  */
8186 void
8187 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8188 {
8189         guint8 *code = ip;
8190
8191         if (ji->from_aot) {
8192                 guint32 native_offset = ip - (guint8*)ji->code_start;
8193                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8194
8195                 g_assert (info->bp_addrs [native_offset] == 0);
8196                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8197         } else {
8198                 /* ip points to a mov r11, 0 */
8199                 g_assert (code [0] == 0x41);
8200                 g_assert (code [1] == 0xbb);
8201                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8202         }
8203 }
8204
8205 /*
8206  * mono_arch_clear_breakpoint:
8207  *
8208  *   Clear the breakpoint at IP.
8209  */
8210 void
8211 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8212 {
8213         guint8 *code = ip;
8214
8215         if (ji->from_aot) {
8216                 guint32 native_offset = ip - (guint8*)ji->code_start;
8217                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8218
8219                 info->bp_addrs [native_offset] = NULL;
8220         } else {
8221                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8222         }
8223 }
8224
8225 gboolean
8226 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8227 {
8228         /* We use soft breakpoints on amd64 */
8229         return FALSE;
8230 }
8231
8232 /*
8233  * mono_arch_skip_breakpoint:
8234  *
8235  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8236  * we resume, the instruction is not executed again.
8237  */
8238 void
8239 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8240 {
8241         g_assert_not_reached ();
8242 }
8243
8244 /*
8245  * mono_arch_start_single_stepping:
8246  *
8247  *   Start single stepping.
8248  */
8249 void
8250 mono_arch_start_single_stepping (void)
8251 {
8252         ss_trampoline = mini_get_single_step_trampoline ();
8253 }
8254
8255 /*
8256  * mono_arch_stop_single_stepping:
8257  *
8258  *   Stop single stepping.
8259  */
8260 void
8261 mono_arch_stop_single_stepping (void)
8262 {
8263         ss_trampoline = NULL;
8264 }
8265
8266 /*
8267  * mono_arch_is_single_step_event:
8268  *
8269  *   Return whenever the machine state in SIGCTX corresponds to a single
8270  * step event.
8271  */
8272 gboolean
8273 mono_arch_is_single_step_event (void *info, void *sigctx)
8274 {
8275         /* We use soft breakpoints on amd64 */
8276         return FALSE;
8277 }
8278
8279 /*
8280  * mono_arch_skip_single_step:
8281  *
8282  *   Modify CTX so the ip is placed after the single step trigger instruction,
8283  * we resume, the instruction is not executed again.
8284  */
8285 void
8286 mono_arch_skip_single_step (MonoContext *ctx)
8287 {
8288         g_assert_not_reached ();
8289 }
8290
8291 /*
8292  * mono_arch_create_seq_point_info:
8293  *
8294  *   Return a pointer to a data structure which is used by the sequence
8295  * point implementation in AOTed code.
8296  */
8297 gpointer
8298 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8299 {
8300         SeqPointInfo *info;
8301         MonoJitInfo *ji;
8302
8303         // FIXME: Add a free function
8304
8305         mono_domain_lock (domain);
8306         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8307                                                                 code);
8308         mono_domain_unlock (domain);
8309
8310         if (!info) {
8311                 ji = mono_jit_info_table_find (domain, (char*)code);
8312                 g_assert (ji);
8313
8314                 // FIXME: Optimize the size
8315                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8316
8317                 info->ss_tramp_addr = &ss_trampoline;
8318
8319                 mono_domain_lock (domain);
8320                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8321                                                          code, info);
8322                 mono_domain_unlock (domain);
8323         }
8324
8325         return info;
8326 }
8327
8328 void
8329 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8330 {
8331         ext->lmf.previous_lmf = prev_lmf;
8332         /* Mark that this is a MonoLMFExt */
8333         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8334         ext->lmf.rsp = (gssize)ext;
8335 }
8336
8337 #endif
8338
8339 gboolean
8340 mono_arch_opcode_supported (int opcode)
8341 {
8342         switch (opcode) {
8343         case OP_ATOMIC_ADD_I4:
8344         case OP_ATOMIC_ADD_I8:
8345         case OP_ATOMIC_EXCHANGE_I4:
8346         case OP_ATOMIC_EXCHANGE_I8:
8347         case OP_ATOMIC_CAS_I4:
8348         case OP_ATOMIC_CAS_I8:
8349         case OP_ATOMIC_LOAD_I1:
8350         case OP_ATOMIC_LOAD_I2:
8351         case OP_ATOMIC_LOAD_I4:
8352         case OP_ATOMIC_LOAD_I8:
8353         case OP_ATOMIC_LOAD_U1:
8354         case OP_ATOMIC_LOAD_U2:
8355         case OP_ATOMIC_LOAD_U4:
8356         case OP_ATOMIC_LOAD_U8:
8357         case OP_ATOMIC_LOAD_R4:
8358         case OP_ATOMIC_LOAD_R8:
8359         case OP_ATOMIC_STORE_I1:
8360         case OP_ATOMIC_STORE_I2:
8361         case OP_ATOMIC_STORE_I4:
8362         case OP_ATOMIC_STORE_I8:
8363         case OP_ATOMIC_STORE_U1:
8364         case OP_ATOMIC_STORE_U2:
8365         case OP_ATOMIC_STORE_U4:
8366         case OP_ATOMIC_STORE_U8:
8367         case OP_ATOMIC_STORE_R4:
8368         case OP_ATOMIC_STORE_R8:
8369                 return TRUE;
8370         default:
8371                 return FALSE;
8372         }
8373 }
8374
8375 CallInfo*
8376 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8377 {
8378         return get_call_info (mp, sig);
8379 }