mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 static void
 178 amd64_patch (unsigned char* code, gpointer target)
 179 {
 180         guint8 rex = 0;
 181
 182         /* Skip REX */
 183         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 184                 rex = code [0];
 185                 code += 1;
 186         }
 187
 188         if ((code [0] & 0xf8) == 0xb8) {
 189                 /* amd64_set_reg_template */
 190                 *(guint64*)(code + 1) = (guint64)target;
 191         }
 192         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 193                 /* mov 0(%rip), %dreg */
 194                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 195         }
 196         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 197                 /* call *<OFFSET>(%rip) */
 198                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 199         }
 200         else if (code [0] == 0xe8) {
 201                 /* call <DISP> */
 202                 gint64 disp = (guint8*)target - (guint8*)code;
 203                 g_assert (amd64_is_imm32 (disp));
 204                 x86_patch (code, (unsigned char*)target);
 205         }
 206         else
 207                 x86_patch (code, (unsigned char*)target);
 208 }
 209
 210 void
 211 mono_amd64_patch (unsigned char* code, gpointer target)
 212 {
 213         amd64_patch (code, target);
 214 }
 215
 216 #define DEBUG(a) if (cfg->verbose_level > 1) a
 217
 218 static void inline
 219 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 ainfo->arg_size = sizeof (mgreg_t);
 226                 /* Since the same stack slot size is used for all arg */
 227                 /*  types, it needs to be big enough to hold them all */
 228                 (*stack_size) += sizeof(mgreg_t);
 229     }
 230     else {
 231                 ainfo->storage = ArgInIReg;
 232                 ainfo->reg = param_regs [*gr];
 233                 (*gr) ++;
 234     }
 235 }
 236
 237 static void inline
 238 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 239 {
 240     ainfo->offset = *stack_size;
 241
 242     if (*gr >= FLOAT_PARAM_REGS) {
 243                 ainfo->storage = ArgOnStack;
 244                 ainfo->arg_size = sizeof (mgreg_t);
 245                 /* Since the same stack slot size is used for both float */
 246                 /*  types, it needs to be big enough to hold them both */
 247                 (*stack_size) += sizeof(mgreg_t);
 248     }
 249     else {
 250                 /* A double register */
 251                 if (is_double)
 252                         ainfo->storage = ArgInDoubleSSEReg;
 253                 else
 254                         ainfo->storage = ArgInFloatSSEReg;
 255                 ainfo->reg = *gr;
 256                 (*gr) += 1;
 257     }
 258 }
 259
 260 typedef enum ArgumentClass {
 261         ARG_CLASS_NO_CLASS,
 262         ARG_CLASS_MEMORY,
 263         ARG_CLASS_INTEGER,
 264         ARG_CLASS_SSE
 265 } ArgumentClass;
 266
 267 static ArgumentClass
 268 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 269 {
 270         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 271         MonoType *ptype;
 272
 273         ptype = mini_get_underlying_type (type);
 274         switch (ptype->type) {
 275         case MONO_TYPE_I1:
 276         case MONO_TYPE_U1:
 277         case MONO_TYPE_I2:
 278         case MONO_TYPE_U2:
 279         case MONO_TYPE_I4:
 280         case MONO_TYPE_U4:
 281         case MONO_TYPE_I:
 282         case MONO_TYPE_U:
 283         case MONO_TYPE_STRING:
 284         case MONO_TYPE_OBJECT:
 285         case MONO_TYPE_CLASS:
 286         case MONO_TYPE_SZARRAY:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_ARRAY:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 static int
 342 count_fields_nested (MonoClass *klass)
 343 {
 344         MonoMarshalType *info;
 345         int i, count;
 346
 347         info = mono_marshal_load_type_info (klass);
 348         g_assert(info);
 349         count = 0;
 350         for (i = 0; i < info->num_fields; ++i) {
 351                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 352                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 353                 else
 354                         count ++;
 355         }
 356         return count;
 357 }
 358
 359 static int
 360 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 361 {
 362         MonoMarshalType *info;
 363         int i;
 364
 365         info = mono_marshal_load_type_info (klass);
 366         g_assert(info);
 367         for (i = 0; i < info->num_fields; ++i) {
 368                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 369                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 370                 } else {
 371                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 372                         fields [index].offset += offset;
 373                         index ++;
 374                 }
 375         }
 376         return index;
 377 }
 378
 379 #ifdef TARGET_WIN32
 380 static void
 381 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 382                                          gboolean is_return,
 383                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 384 {
 385         guint32 size, i, nfields;
 386         guint32 argsize = 8;
 387         ArgumentClass arg_class;
 388         MonoMarshalType *info = NULL;
 389         MonoMarshalField *fields = NULL;
 390         MonoClass *klass;
 391         gboolean pass_on_stack = FALSE;
 392
 393         klass = mono_class_from_mono_type (type);
 394         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 395
 396         /*
 397         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 398         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 399         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 400         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 401         * it must be represented in call and cannot be dropped.
 402         */
 403         if (0 == size && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke)
 404                 ainfo->pass_empty_struct = TRUE;
 405
 406         if (!sig->pinvoke)
 407                 pass_on_stack = TRUE;
 408
 409         /* If this struct can't be split up naturally into 8-byte */
 410         /* chunks (registers), pass it on the stack.              */
 411         if (sig->pinvoke && !pass_on_stack) {
 412                 guint32 align;
 413                 guint32 field_size;
 414
 415                 info = mono_marshal_load_type_info (klass);
 416                 g_assert (info);
 417
 418                 /*
 419                  * Collect field information recursively to be able to
 420                  * handle nested structures.
 421                  */
 422                 nfields = count_fields_nested (klass);
 423                 fields = g_new0 (MonoMarshalField, nfields);
 424                 collect_field_info_nested (klass, fields, 0, 0);
 425
 426                 for (i = 0; i < nfields; ++i) {
 427                         field_size = mono_marshal_type_size (fields [i].field->type,
 428                                                            fields [i].mspec,
 429                                                            &align, TRUE, klass->unicode);
 430                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 431                                 pass_on_stack = TRUE;
 432                                 break;
 433                         }
 434                 }
 435         }
 436
 437         if (pass_on_stack) {
 438                 /* Allways pass in memory */
 439                 ainfo->offset = *stack_size;
 440                 *stack_size += ALIGN_TO (size, 8);
 441                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 442                 if (!is_return)
 443                         ainfo->arg_size = ALIGN_TO (size, 8);
 444
 445                 g_free (fields);
 446                 return;
 447         }
 448
 449         if (!sig->pinvoke) {
 450                 int n = mono_class_value_size (klass, NULL);
 451
 452                 argsize = n;
 453
 454                 if (n > 8)
 455                         arg_class = ARG_CLASS_MEMORY;
 456                 else
 457                         /* Always pass in 1 integer register */
 458                         arg_class = ARG_CLASS_INTEGER;
 459         } else {
 460                 g_assert (info);
 461
 462                 /*Only drop value type if its not an empty struct as input that must be represented in call*/
 463                 if ((!fields && !ainfo->pass_empty_struct) || (!fields && ainfo->pass_empty_struct && is_return)) {
 464                         ainfo->storage = ArgValuetypeInReg;
 465                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 466                         return;
 467                 }
 468
 469                 switch (info->native_size) {
 470                 case 0:
 471                         g_assert (!fields && MONO_TYPE_ISSTRUCT (type) && !is_return);
 472                         break;
 473                 case 1: case 2: case 4: case 8:
 474                         break;
 475                 default:
 476                         if (is_return) {
 477                                 ainfo->storage = ArgValuetypeAddrInIReg;
 478                                 ainfo->offset = *stack_size;
 479                                 *stack_size += ALIGN_TO (info->native_size, 8);
 480                         }
 481                         else {
 482                                 ainfo->storage = ArgValuetypeAddrInIReg;
 483
 484                                 if (*gr < PARAM_REGS) {
 485                                         ainfo->pair_storage [0] = ArgInIReg;
 486                                         ainfo->pair_regs [0] = param_regs [*gr];
 487                                         (*gr) ++;
 488                                 }
 489                                 else {
 490                                         ainfo->pair_storage [0] = ArgOnStack;
 491                                         ainfo->offset = *stack_size;
 492                                         ainfo->arg_size = sizeof (mgreg_t);
 493                                         *stack_size += 8;
 494                                 }
 495                         }
 496
 497                         g_free (fields);
 498                         return;
 499                 }
 500
 501                 int size;
 502                 guint32 align;
 503                 ArgumentClass class1;
 504
 505                 if (nfields == 0 && ainfo->pass_empty_struct) {
 506                         g_assert (!fields && !is_return);
 507                         class1 = ARG_CLASS_INTEGER;
 508                 }
 509                 else if (nfields == 0)
 510                         class1 = ARG_CLASS_MEMORY;
 511                 else
 512                         class1 = ARG_CLASS_NO_CLASS;
 513                 for (i = 0; i < nfields; ++i) {
 514                         size = mono_marshal_type_size (fields [i].field->type,
 515                                                                                    fields [i].mspec,
 516                                                                                    &align, TRUE, klass->unicode);
 517                         /* How far into this quad this data extends.*/
 518                         /* (8 is size of quad) */
 519                         argsize = fields [i].offset + size;
 520
 521                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 522                 }
 523                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 524                 arg_class = class1;
 525         }
 526
 527         g_free (fields);
 528
 529         /* Allocate registers */
 530         {
 531                 int orig_gr = *gr;
 532                 int orig_fr = *fr;
 533
 534                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 535                         argsize ++;
 536
 537                 ainfo->storage = ArgValuetypeInReg;
 538                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 539                 ainfo->pair_size [0] = argsize;
 540                 ainfo->pair_size [1] = 0;
 541                 ainfo->nregs = 1;
 542                 switch (arg_class) {
 543                 case ARG_CLASS_INTEGER:
 544                         if (*gr >= PARAM_REGS)
 545                                 arg_class = ARG_CLASS_MEMORY;
 546                         else {
 547                                 ainfo->pair_storage [0] = ArgInIReg;
 548                                 if (is_return)
 549                                         ainfo->pair_regs [0] = return_regs [*gr];
 550                                 else
 551                                         ainfo->pair_regs [0] = param_regs [*gr];
 552                                 (*gr) ++;
 553                         }
 554                         break;
 555                 case ARG_CLASS_SSE:
 556                         if (*fr >= FLOAT_PARAM_REGS)
 557                                 arg_class = ARG_CLASS_MEMORY;
 558                         else {
 559                                 if (argsize <= 4)
 560                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 561                                 else
 562                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 563                                 ainfo->pair_regs [0] = *fr;
 564                                 (*fr) ++;
 565                         }
 566                         break;
 567                 case ARG_CLASS_MEMORY:
 568                         break;
 569                 default:
 570                         g_assert_not_reached ();
 571                 }
 572
 573                 if (arg_class == ARG_CLASS_MEMORY) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         *stack_size += sizeof (mgreg_t);
 580                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 581                         if (!is_return)
 582                                 ainfo->arg_size = sizeof (mgreg_t);
 583                 }
 584         }
 585 }
 586 #endif /* TARGET_WIN32 */
 587
 588 static void
 589 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 590                            gboolean is_return,
 591                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 592 {
 593 #ifdef TARGET_WIN32
 594         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 595 #else
 596         guint32 size, quad, nquads, i, nfields;
 597         /* Keep track of the size used in each quad so we can */
 598         /* use the right size when copying args/return vars.  */
 599         guint32 quadsize [2] = {8, 8};
 600         ArgumentClass args [2];
 601         MonoMarshalType *info = NULL;
 602         MonoMarshalField *fields = NULL;
 603         MonoClass *klass;
 604         gboolean pass_on_stack = FALSE;
 605
 606         klass = mono_class_from_mono_type (type);
 607         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 608
 609         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 610                 /* We pass and return vtypes of size 8 in a register */
 611         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 612                 pass_on_stack = TRUE;
 613         }
 614
 615         /* If this struct can't be split up naturally into 8-byte */
 616         /* chunks (registers), pass it on the stack.              */
 617         if (sig->pinvoke && !pass_on_stack) {
 618                 guint32 align;
 619                 guint32 field_size;
 620
 621                 info = mono_marshal_load_type_info (klass);
 622                 g_assert (info);
 623
 624                 /*
 625                  * Collect field information recursively to be able to
 626                  * handle nested structures.
 627                  */
 628                 nfields = count_fields_nested (klass);
 629                 fields = g_new0 (MonoMarshalField, nfields);
 630                 collect_field_info_nested (klass, fields, 0, 0);
 631
 632                 for (i = 0; i < nfields; ++i) {
 633                         field_size = mono_marshal_type_size (fields [i].field->type,
 634                                                            fields [i].mspec,
 635                                                            &align, TRUE, klass->unicode);
 636                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 637                                 pass_on_stack = TRUE;
 638                                 break;
 639                         }
 640                 }
 641         }
 642
 643         if (size == 0) {
 644                 ainfo->storage = ArgValuetypeInReg;
 645                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 646                 return;
 647         }
 648
 649         if (pass_on_stack) {
 650                 /* Allways pass in memory */
 651                 ainfo->offset = *stack_size;
 652                 *stack_size += ALIGN_TO (size, 8);
 653                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 654                 if (!is_return)
 655                         ainfo->arg_size = ALIGN_TO (size, 8);
 656
 657                 g_free (fields);
 658                 return;
 659         }
 660
 661         if (size > 8)
 662                 nquads = 2;
 663         else
 664                 nquads = 1;
 665
 666         if (!sig->pinvoke) {
 667                 int n = mono_class_value_size (klass, NULL);
 668
 669                 quadsize [0] = n >= 8 ? 8 : n;
 670                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 671
 672                 /* Always pass in 1 or 2 integer registers */
 673                 args [0] = ARG_CLASS_INTEGER;
 674                 args [1] = ARG_CLASS_INTEGER;
 675                 /* Only the simplest cases are supported */
 676                 if (is_return && nquads != 1) {
 677                         args [0] = ARG_CLASS_MEMORY;
 678                         args [1] = ARG_CLASS_MEMORY;
 679                 }
 680         } else {
 681                 /*
 682                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 683                  * The X87 and SSEUP stuff is left out since there are no such types in
 684                  * the CLR.
 685                  */
 686                 g_assert (info);
 687
 688                 if (!fields) {
 689                         ainfo->storage = ArgValuetypeInReg;
 690                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 691                         return;
 692                 }
 693
 694                 if (info->native_size > 16) {
 695                         ainfo->offset = *stack_size;
 696                         *stack_size += ALIGN_TO (info->native_size, 8);
 697                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 698                         if (!is_return)
 699                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 700
 701                         g_free (fields);
 702                         return;
 703                 }
 704
 705                 args [0] = ARG_CLASS_NO_CLASS;
 706                 args [1] = ARG_CLASS_NO_CLASS;
 707                 for (quad = 0; quad < nquads; ++quad) {
 708                         int size;
 709                         guint32 align;
 710                         ArgumentClass class1;
 711
 712                         if (nfields == 0)
 713                                 class1 = ARG_CLASS_MEMORY;
 714                         else
 715                                 class1 = ARG_CLASS_NO_CLASS;
 716                         for (i = 0; i < nfields; ++i) {
 717                                 size = mono_marshal_type_size (fields [i].field->type,
 718                                                                                            fields [i].mspec,
 719                                                                                            &align, TRUE, klass->unicode);
 720                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 721                                         /* Unaligned field */
 722                                         NOT_IMPLEMENTED;
 723                                 }
 724
 725                                 /* Skip fields in other quad */
 726                                 if ((quad == 0) && (fields [i].offset >= 8))
 727                                         continue;
 728                                 if ((quad == 1) && (fields [i].offset < 8))
 729                                         continue;
 730
 731                                 /* How far into this quad this data extends.*/
 732                                 /* (8 is size of quad) */
 733                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 734
 735                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 736                         }
 737                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 738                         args [quad] = class1;
 739                 }
 740         }
 741
 742         g_free (fields);
 743
 744         /* Post merger cleanup */
 745         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 746                 args [0] = args [1] = ARG_CLASS_MEMORY;
 747
 748         /* Allocate registers */
 749         {
 750                 int orig_gr = *gr;
 751                 int orig_fr = *fr;
 752
 753                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 754                         quadsize [0] ++;
 755                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 756                         quadsize [1] ++;
 757
 758                 ainfo->storage = ArgValuetypeInReg;
 759                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 760                 g_assert (quadsize [0] <= 8);
 761                 g_assert (quadsize [1] <= 8);
 762                 ainfo->pair_size [0] = quadsize [0];
 763                 ainfo->pair_size [1] = quadsize [1];
 764                 ainfo->nregs = nquads;
 765                 for (quad = 0; quad < nquads; ++quad) {
 766                         switch (args [quad]) {
 767                         case ARG_CLASS_INTEGER:
 768                                 if (*gr >= PARAM_REGS)
 769                                         args [quad] = ARG_CLASS_MEMORY;
 770                                 else {
 771                                         ainfo->pair_storage [quad] = ArgInIReg;
 772                                         if (is_return)
 773                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 774                                         else
 775                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 776                                         (*gr) ++;
 777                                 }
 778                                 break;
 779                         case ARG_CLASS_SSE:
 780                                 if (*fr >= FLOAT_PARAM_REGS)
 781                                         args [quad] = ARG_CLASS_MEMORY;
 782                                 else {
 783                                         if (quadsize[quad] <= 4)
 784                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 785                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 786                                         ainfo->pair_regs [quad] = *fr;
 787                                         (*fr) ++;
 788                                 }
 789                                 break;
 790                         case ARG_CLASS_MEMORY:
 791                                 break;
 792                         default:
 793                                 g_assert_not_reached ();
 794                         }
 795                 }
 796
 797                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 798                         int arg_size;
 799                         /* Revert possible register assignments */
 800                         *gr = orig_gr;
 801                         *fr = orig_fr;
 802
 803                         ainfo->offset = *stack_size;
 804                         if (sig->pinvoke)
 805                                 arg_size = ALIGN_TO (info->native_size, 8);
 806                         else
 807                                 arg_size = nquads * sizeof(mgreg_t);
 808                         *stack_size += arg_size;
 809                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 810                         if (!is_return)
 811                                 ainfo->arg_size = arg_size;
 812                 }
 813         }
 814 #endif /* !TARGET_WIN32 */
 815 }
 816
 817 /*
 818  * get_call_info:
 819  *
 820  * Obtain information about a call according to the calling convention.
 821  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 822  * Draft Version 0.23" document for more information.
 823  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 824  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 825  */
 826 static CallInfo*
 827 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 828 {
 829         guint32 i, gr, fr, pstart;
 830         MonoType *ret_type;
 831         int n = sig->hasthis + sig->param_count;
 832         guint32 stack_size = 0;
 833         CallInfo *cinfo;
 834         gboolean is_pinvoke = sig->pinvoke;
 835
 836         if (mp)
 837                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 838         else
 839                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 840
 841         cinfo->nargs = n;
 842         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 843
 844         gr = 0;
 845         fr = 0;
 846
 847 #ifdef TARGET_WIN32
 848         /* Reserve space where the callee can save the argument registers */
 849         stack_size = 4 * sizeof (mgreg_t);
 850 #endif
 851
 852         /* return value */
 853         ret_type = mini_get_underlying_type (sig->ret);
 854         switch (ret_type->type) {
 855         case MONO_TYPE_I1:
 856         case MONO_TYPE_U1:
 857         case MONO_TYPE_I2:
 858         case MONO_TYPE_U2:
 859         case MONO_TYPE_I4:
 860         case MONO_TYPE_U4:
 861         case MONO_TYPE_I:
 862         case MONO_TYPE_U:
 863         case MONO_TYPE_PTR:
 864         case MONO_TYPE_FNPTR:
 865         case MONO_TYPE_CLASS:
 866         case MONO_TYPE_OBJECT:
 867         case MONO_TYPE_SZARRAY:
 868         case MONO_TYPE_ARRAY:
 869         case MONO_TYPE_STRING:
 870                 cinfo->ret.storage = ArgInIReg;
 871                 cinfo->ret.reg = AMD64_RAX;
 872                 break;
 873         case MONO_TYPE_U8:
 874         case MONO_TYPE_I8:
 875                 cinfo->ret.storage = ArgInIReg;
 876                 cinfo->ret.reg = AMD64_RAX;
 877                 break;
 878         case MONO_TYPE_R4:
 879                 cinfo->ret.storage = ArgInFloatSSEReg;
 880                 cinfo->ret.reg = AMD64_XMM0;
 881                 break;
 882         case MONO_TYPE_R8:
 883                 cinfo->ret.storage = ArgInDoubleSSEReg;
 884                 cinfo->ret.reg = AMD64_XMM0;
 885                 break;
 886         case MONO_TYPE_GENERICINST:
 887                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 888                         cinfo->ret.storage = ArgInIReg;
 889                         cinfo->ret.reg = AMD64_RAX;
 890                         break;
 891                 }
 892                 if (mini_is_gsharedvt_type (ret_type)) {
 893                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 894                         break;
 895                 }
 896                 /* fall through */
 897         case MONO_TYPE_VALUETYPE:
 898         case MONO_TYPE_TYPEDBYREF: {
 899                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 900
 901                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 902                 g_assert (cinfo->ret.storage != ArgInIReg);
 903                 break;
 904         }
 905         case MONO_TYPE_VAR:
 906         case MONO_TYPE_MVAR:
 907                 g_assert (mini_is_gsharedvt_type (ret_type));
 908                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 909                 break;
 910         case MONO_TYPE_VOID:
 911                 break;
 912         default:
 913                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 914         }
 915
 916         pstart = 0;
 917         /*
 918          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 919          * the first argument, allowing 'this' to be always passed in the first arg reg.
 920          * Also do this if the first argument is a reference type, since virtual calls
 921          * are sometimes made using calli without sig->hasthis set, like in the delegate
 922          * invoke wrappers.
 923          */
 924         ArgStorage ret_storage = cinfo->ret.storage;
 925         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 926                 if (sig->hasthis) {
 927                         add_general (&gr, &stack_size, cinfo->args + 0);
 928                 } else {
 929                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 930                         pstart = 1;
 931                 }
 932                 add_general (&gr, &stack_size, &cinfo->ret);
 933                 cinfo->ret.storage = ret_storage;
 934                 cinfo->vret_arg_index = 1;
 935         } else {
 936                 /* this */
 937                 if (sig->hasthis)
 938                         add_general (&gr, &stack_size, cinfo->args + 0);
 939
 940                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 941                         add_general (&gr, &stack_size, &cinfo->ret);
 942                         cinfo->ret.storage = ret_storage;
 943                 }
 944         }
 945
 946         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 947                 gr = PARAM_REGS;
 948                 fr = FLOAT_PARAM_REGS;
 949
 950                 /* Emit the signature cookie just before the implicit arguments */
 951                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 952         }
 953
 954         for (i = pstart; i < sig->param_count; ++i) {
 955                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 956                 MonoType *ptype;
 957
 958 #ifdef TARGET_WIN32
 959                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 960                 if (gr > fr)
 961                         fr = gr;
 962                 else if (fr > gr)
 963                         gr = fr;
 964 #endif
 965
 966                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 967                         /* We allways pass the sig cookie on the stack for simplicity */
 968                         /*
 969                          * Prevent implicit arguments + the sig cookie from being passed
 970                          * in registers.
 971                          */
 972                         gr = PARAM_REGS;
 973                         fr = FLOAT_PARAM_REGS;
 974
 975                         /* Emit the signature cookie just before the implicit arguments */
 976                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 977                 }
 978
 979                 ptype = mini_get_underlying_type (sig->params [i]);
 980                 switch (ptype->type) {
 981                 case MONO_TYPE_I1:
 982                 case MONO_TYPE_U1:
 983                         add_general (&gr, &stack_size, ainfo);
 984                         break;
 985                 case MONO_TYPE_I2:
 986                 case MONO_TYPE_U2:
 987                         add_general (&gr, &stack_size, ainfo);
 988                         break;
 989                 case MONO_TYPE_I4:
 990                 case MONO_TYPE_U4:
 991                         add_general (&gr, &stack_size, ainfo);
 992                         break;
 993                 case MONO_TYPE_I:
 994                 case MONO_TYPE_U:
 995                 case MONO_TYPE_PTR:
 996                 case MONO_TYPE_FNPTR:
 997                 case MONO_TYPE_CLASS:
 998                 case MONO_TYPE_OBJECT:
 999                 case MONO_TYPE_STRING:
1000                 case MONO_TYPE_SZARRAY:
1001                 case MONO_TYPE_ARRAY:
1002                         add_general (&gr, &stack_size, ainfo);
1003                         break;
1004                 case MONO_TYPE_GENERICINST:
1005                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1006                                 add_general (&gr, &stack_size, ainfo);
1007                                 break;
1008                         }
1009                         if (mini_is_gsharedvt_variable_type (ptype)) {
1010                                 /* gsharedvt arguments are passed by ref */
1011                                 add_general (&gr, &stack_size, ainfo);
1012                                 if (ainfo->storage == ArgInIReg)
1013                                         ainfo->storage = ArgGSharedVtInReg;
1014                                 else
1015                                         ainfo->storage = ArgGSharedVtOnStack;
1016                                 break;
1017                         }
1018                         /* fall through */
1019                 case MONO_TYPE_VALUETYPE:
1020                 case MONO_TYPE_TYPEDBYREF:
1021                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1022                         break;
1023                 case MONO_TYPE_U8:
1024
1025                 case MONO_TYPE_I8:
1026                         add_general (&gr, &stack_size, ainfo);
1027                         break;
1028                 case MONO_TYPE_R4:
1029                         add_float (&fr, &stack_size, ainfo, FALSE);
1030                         break;
1031                 case MONO_TYPE_R8:
1032                         add_float (&fr, &stack_size, ainfo, TRUE);
1033                         break;
1034                 case MONO_TYPE_VAR:
1035                 case MONO_TYPE_MVAR:
1036                         /* gsharedvt arguments are passed by ref */
1037                         g_assert (mini_is_gsharedvt_type (ptype));
1038                         add_general (&gr, &stack_size, ainfo);
1039                         if (ainfo->storage == ArgInIReg)
1040                                 ainfo->storage = ArgGSharedVtInReg;
1041                         else
1042                                 ainfo->storage = ArgGSharedVtOnStack;
1043                         break;
1044                 default:
1045                         g_assert_not_reached ();
1046                 }
1047         }
1048
1049         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1050                 gr = PARAM_REGS;
1051                 fr = FLOAT_PARAM_REGS;
1052
1053                 /* Emit the signature cookie just before the implicit arguments */
1054                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1055         }
1056
1057         cinfo->stack_usage = stack_size;
1058         cinfo->reg_usage = gr;
1059         cinfo->freg_usage = fr;
1060         return cinfo;
1061 }
1062
1063 /*
1064  * mono_arch_get_argument_info:
1065  * @csig:  a method signature
1066  * @param_count: the number of parameters to consider
1067  * @arg_info: an array to store the result infos
1068  *
1069  * Gathers information on parameters such as size, alignment and
1070  * padding. arg_info should be large enought to hold param_count + 1 entries.
1071  *
1072  * Returns the size of the argument area on the stack.
1073  */
1074 int
1075 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1076 {
1077         int k;
1078         CallInfo *cinfo = get_call_info (NULL, csig);
1079         guint32 args_size = cinfo->stack_usage;
1080
1081         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1082         if (csig->hasthis) {
1083                 arg_info [0].offset = 0;
1084         }
1085
1086         for (k = 0; k < param_count; k++) {
1087                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1088                 /* FIXME: */
1089                 arg_info [k + 1].size = 0;
1090         }
1091
1092         g_free (cinfo);
1093
1094         return args_size;
1095 }
1096
1097 gboolean
1098 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1099 {
1100         CallInfo *c1, *c2;
1101         gboolean res;
1102         MonoType *callee_ret;
1103
1104         c1 = get_call_info (NULL, caller_sig);
1105         c2 = get_call_info (NULL, callee_sig);
1106         res = c1->stack_usage >= c2->stack_usage;
1107         callee_ret = mini_get_underlying_type (callee_sig->ret);
1108         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1109                 /* An address on the callee's stack is passed as the first argument */
1110                 res = FALSE;
1111
1112         g_free (c1);
1113         g_free (c2);
1114
1115         return res;
1116 }
1117
1118 /*
1119  * Initialize the cpu to execute managed code.
1120  */
1121 void
1122 mono_arch_cpu_init (void)
1123 {
1124 #ifndef _MSC_VER
1125         guint16 fpcw;
1126
1127         /* spec compliance requires running with double precision */
1128         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1129         fpcw &= ~X86_FPCW_PRECC_MASK;
1130         fpcw |= X86_FPCW_PREC_DOUBLE;
1131         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1132         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1133 #else
1134         /* TODO: This is crashing on Win64 right now.
1135         * _control87 (_PC_53, MCW_PC);
1136         */
1137 #endif
1138 }
1139
1140 /*
1141  * Initialize architecture specific code.
1142  */
1143 void
1144 mono_arch_init (void)
1145 {
1146         mono_os_mutex_init_recursive (&mini_arch_mutex);
1147
1148         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1149         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1150         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1151         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1152 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1153         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1154 #endif
1155
1156         if (!mono_aot_only)
1157                 bp_trampoline = mini_get_breakpoint_trampoline ();
1158 }
1159
1160 /*
1161  * Cleanup architecture specific code.
1162  */
1163 void
1164 mono_arch_cleanup (void)
1165 {
1166         mono_os_mutex_destroy (&mini_arch_mutex);
1167 }
1168
1169 /*
1170  * This function returns the optimizations supported on this cpu.
1171  */
1172 guint32
1173 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1174 {
1175         guint32 opts = 0;
1176
1177         *exclude_mask = 0;
1178
1179         if (mono_hwcap_x86_has_cmov) {
1180                 opts |= MONO_OPT_CMOV;
1181
1182                 if (mono_hwcap_x86_has_fcmov)
1183                         opts |= MONO_OPT_FCMOV;
1184                 else
1185                         *exclude_mask |= MONO_OPT_FCMOV;
1186         } else {
1187                 *exclude_mask |= MONO_OPT_CMOV;
1188         }
1189
1190         return opts;
1191 }
1192
1193 /*
1194  * This function test for all SSE functions supported.
1195  *
1196  * Returns a bitmask corresponding to all supported versions.
1197  *
1198  */
1199 guint32
1200 mono_arch_cpu_enumerate_simd_versions (void)
1201 {
1202         guint32 sse_opts = 0;
1203
1204         if (mono_hwcap_x86_has_sse1)
1205                 sse_opts |= SIMD_VERSION_SSE1;
1206
1207         if (mono_hwcap_x86_has_sse2)
1208                 sse_opts |= SIMD_VERSION_SSE2;
1209
1210         if (mono_hwcap_x86_has_sse3)
1211                 sse_opts |= SIMD_VERSION_SSE3;
1212
1213         if (mono_hwcap_x86_has_ssse3)
1214                 sse_opts |= SIMD_VERSION_SSSE3;
1215
1216         if (mono_hwcap_x86_has_sse41)
1217                 sse_opts |= SIMD_VERSION_SSE41;
1218
1219         if (mono_hwcap_x86_has_sse42)
1220                 sse_opts |= SIMD_VERSION_SSE42;
1221
1222         if (mono_hwcap_x86_has_sse4a)
1223                 sse_opts |= SIMD_VERSION_SSE4a;
1224
1225         return sse_opts;
1226 }
1227
1228 #ifndef DISABLE_JIT
1229
1230 GList *
1231 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1232 {
1233         GList *vars = NULL;
1234         int i;
1235
1236         for (i = 0; i < cfg->num_varinfo; i++) {
1237                 MonoInst *ins = cfg->varinfo [i];
1238                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1239
1240                 /* unused vars */
1241                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1242                         continue;
1243
1244                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1245                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1246                         continue;
1247
1248                 if (mono_is_regsize_var (ins->inst_vtype)) {
1249                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1250                         g_assert (i == vmv->idx);
1251                         vars = g_list_prepend (vars, vmv);
1252                 }
1253         }
1254
1255         vars = mono_varlist_sort (cfg, vars, 0);
1256
1257         return vars;
1258 }
1259
1260 /**
1261  * mono_arch_compute_omit_fp:
1262  *
1263  *   Determine whenever the frame pointer can be eliminated.
1264  */
1265 static void
1266 mono_arch_compute_omit_fp (MonoCompile *cfg)
1267 {
1268         MonoMethodSignature *sig;
1269         MonoMethodHeader *header;
1270         int i, locals_size;
1271         CallInfo *cinfo;
1272
1273         if (cfg->arch.omit_fp_computed)
1274                 return;
1275
1276         header = cfg->header;
1277
1278         sig = mono_method_signature (cfg->method);
1279
1280         if (!cfg->arch.cinfo)
1281                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1282         cinfo = (CallInfo *)cfg->arch.cinfo;
1283
1284         /*
1285          * FIXME: Remove some of the restrictions.
1286          */
1287         cfg->arch.omit_fp = TRUE;
1288         cfg->arch.omit_fp_computed = TRUE;
1289
1290         if (cfg->disable_omit_fp)
1291                 cfg->arch.omit_fp = FALSE;
1292
1293         if (!debug_omit_fp ())
1294                 cfg->arch.omit_fp = FALSE;
1295         /*
1296         if (cfg->method->save_lmf)
1297                 cfg->arch.omit_fp = FALSE;
1298         */
1299         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1300                 cfg->arch.omit_fp = FALSE;
1301         if (header->num_clauses)
1302                 cfg->arch.omit_fp = FALSE;
1303         if (cfg->param_area)
1304                 cfg->arch.omit_fp = FALSE;
1305         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1306                 cfg->arch.omit_fp = FALSE;
1307         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1308                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1309                 cfg->arch.omit_fp = FALSE;
1310         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1311                 ArgInfo *ainfo = &cinfo->args [i];
1312
1313                 if (ainfo->storage == ArgOnStack) {
1314                         /*
1315                          * The stack offset can only be determined when the frame
1316                          * size is known.
1317                          */
1318                         cfg->arch.omit_fp = FALSE;
1319                 }
1320         }
1321
1322         locals_size = 0;
1323         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1324                 MonoInst *ins = cfg->varinfo [i];
1325                 int ialign;
1326
1327                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1328         }
1329 }
1330
1331 GList *
1332 mono_arch_get_global_int_regs (MonoCompile *cfg)
1333 {
1334         GList *regs = NULL;
1335
1336         mono_arch_compute_omit_fp (cfg);
1337
1338         if (cfg->arch.omit_fp)
1339                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1340
1341         /* We use the callee saved registers for global allocation */
1342         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1343         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1344         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1345         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1346         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1347 #ifdef TARGET_WIN32
1348         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1349         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1350 #endif
1351
1352         return regs;
1353 }
1354
1355 GList*
1356 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1357 {
1358         GList *regs = NULL;
1359         int i;
1360
1361         /* All XMM registers */
1362         for (i = 0; i < 16; ++i)
1363                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1364
1365         return regs;
1366 }
1367
1368 GList*
1369 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1370 {
1371         static GList *r = NULL;
1372
1373         if (r == NULL) {
1374                 GList *regs = NULL;
1375
1376                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1377                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1378                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1379                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1380                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1381                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1382
1383                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1384                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1385                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1386                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1387                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1388                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1389                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1390                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1391
1392                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1393         }
1394
1395         return r;
1396 }
1397
1398 GList*
1399 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1400 {
1401         int i;
1402         static GList *r = NULL;
1403
1404         if (r == NULL) {
1405                 GList *regs = NULL;
1406
1407                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1408                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1409
1410                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1411         }
1412
1413         return r;
1414 }
1415
1416 /*
1417  * mono_arch_regalloc_cost:
1418  *
1419  *  Return the cost, in number of memory references, of the action of
1420  * allocating the variable VMV into a register during global register
1421  * allocation.
1422  */
1423 guint32
1424 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1425 {
1426         MonoInst *ins = cfg->varinfo [vmv->idx];
1427
1428         if (cfg->method->save_lmf)
1429                 /* The register is already saved */
1430                 /* substract 1 for the invisible store in the prolog */
1431                 return (ins->opcode == OP_ARG) ? 0 : 1;
1432         else
1433                 /* push+pop */
1434                 return (ins->opcode == OP_ARG) ? 1 : 2;
1435 }
1436
1437 /*
1438  * mono_arch_fill_argument_info:
1439  *
1440  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1441  * of the method.
1442  */
1443 void
1444 mono_arch_fill_argument_info (MonoCompile *cfg)
1445 {
1446         MonoType *sig_ret;
1447         MonoMethodSignature *sig;
1448         MonoInst *ins;
1449         int i;
1450         CallInfo *cinfo;
1451
1452         sig = mono_method_signature (cfg->method);
1453
1454         cinfo = (CallInfo *)cfg->arch.cinfo;
1455         sig_ret = mini_get_underlying_type (sig->ret);
1456
1457         /*
1458          * Contrary to mono_arch_allocate_vars (), the information should describe
1459          * where the arguments are at the beginning of the method, not where they can be
1460          * accessed during the execution of the method. The later makes no sense for the
1461          * global register allocator, since a variable can be in more than one location.
1462          */
1463         switch (cinfo->ret.storage) {
1464         case ArgInIReg:
1465         case ArgInFloatSSEReg:
1466         case ArgInDoubleSSEReg:
1467                 cfg->ret->opcode = OP_REGVAR;
1468                 cfg->ret->inst_c0 = cinfo->ret.reg;
1469                 break;
1470         case ArgValuetypeInReg:
1471                 cfg->ret->opcode = OP_REGOFFSET;
1472                 cfg->ret->inst_basereg = -1;
1473                 cfg->ret->inst_offset = -1;
1474                 break;
1475         case ArgNone:
1476                 break;
1477         default:
1478                 g_assert_not_reached ();
1479         }
1480
1481         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1482                 ArgInfo *ainfo = &cinfo->args [i];
1483
1484                 ins = cfg->args [i];
1485
1486                 switch (ainfo->storage) {
1487                 case ArgInIReg:
1488                 case ArgInFloatSSEReg:
1489                 case ArgInDoubleSSEReg:
1490                         ins->opcode = OP_REGVAR;
1491                         ins->inst_c0 = ainfo->reg;
1492                         break;
1493                 case ArgOnStack:
1494                         ins->opcode = OP_REGOFFSET;
1495                         ins->inst_basereg = -1;
1496                         ins->inst_offset = -1;
1497                         break;
1498                 case ArgValuetypeInReg:
1499                         /* Dummy */
1500                         ins->opcode = OP_NOP;
1501                         break;
1502                 default:
1503                         g_assert_not_reached ();
1504                 }
1505         }
1506 }
1507
1508 void
1509 mono_arch_allocate_vars (MonoCompile *cfg)
1510 {
1511         MonoType *sig_ret;
1512         MonoMethodSignature *sig;
1513         MonoInst *ins;
1514         int i, offset;
1515         guint32 locals_stack_size, locals_stack_align;
1516         gint32 *offsets;
1517         CallInfo *cinfo;
1518
1519         sig = mono_method_signature (cfg->method);
1520
1521         cinfo = (CallInfo *)cfg->arch.cinfo;
1522         sig_ret = mini_get_underlying_type (sig->ret);
1523
1524         mono_arch_compute_omit_fp (cfg);
1525
1526         /*
1527          * We use the ABI calling conventions for managed code as well.
1528          * Exception: valuetypes are only sometimes passed or returned in registers.
1529          */
1530
1531         /*
1532          * The stack looks like this:
1533          * <incoming arguments passed on the stack>
1534          * <return value>
1535          * <lmf/caller saved registers>
1536          * <locals>
1537          * <spill area>
1538          * <localloc area>  -> grows dynamically
1539          * <params area>
1540          */
1541
1542         if (cfg->arch.omit_fp) {
1543                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1544                 cfg->frame_reg = AMD64_RSP;
1545                 offset = 0;
1546         } else {
1547                 /* Locals are allocated backwards from %fp */
1548                 cfg->frame_reg = AMD64_RBP;
1549                 offset = 0;
1550         }
1551
1552         cfg->arch.saved_iregs = cfg->used_int_regs;
1553         if (cfg->method->save_lmf) {
1554                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1555                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1556                 cfg->arch.saved_iregs |= iregs_to_save;
1557         }
1558
1559         if (cfg->arch.omit_fp)
1560                 cfg->arch.reg_save_area_offset = offset;
1561         /* Reserve space for callee saved registers */
1562         for (i = 0; i < AMD64_NREG; ++i)
1563                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1564                         offset += sizeof(mgreg_t);
1565                 }
1566         if (!cfg->arch.omit_fp)
1567                 cfg->arch.reg_save_area_offset = -offset;
1568
1569         if (sig_ret->type != MONO_TYPE_VOID) {
1570                 switch (cinfo->ret.storage) {
1571                 case ArgInIReg:
1572                 case ArgInFloatSSEReg:
1573                 case ArgInDoubleSSEReg:
1574                         cfg->ret->opcode = OP_REGVAR;
1575                         cfg->ret->inst_c0 = cinfo->ret.reg;
1576                         cfg->ret->dreg = cinfo->ret.reg;
1577                         break;
1578                 case ArgValuetypeAddrInIReg:
1579                 case ArgGsharedvtVariableInReg:
1580                         /* The register is volatile */
1581                         cfg->vret_addr->opcode = OP_REGOFFSET;
1582                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1583                         if (cfg->arch.omit_fp) {
1584                                 cfg->vret_addr->inst_offset = offset;
1585                                 offset += 8;
1586                         } else {
1587                                 offset += 8;
1588                                 cfg->vret_addr->inst_offset = -offset;
1589                         }
1590                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1591                                 printf ("vret_addr =");
1592                                 mono_print_ins (cfg->vret_addr);
1593                         }
1594                         break;
1595                 case ArgValuetypeInReg:
1596                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1597                         cfg->ret->opcode = OP_REGOFFSET;
1598                         cfg->ret->inst_basereg = cfg->frame_reg;
1599                         if (cfg->arch.omit_fp) {
1600                                 cfg->ret->inst_offset = offset;
1601                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1602                         } else {
1603                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1604                                 cfg->ret->inst_offset = - offset;
1605                         }
1606                         break;
1607                 default:
1608                         g_assert_not_reached ();
1609                 }
1610         }
1611
1612         /* Allocate locals */
1613         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1614         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1615                 char *mname = mono_method_full_name (cfg->method, TRUE);
1616                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1617                 g_free (mname);
1618                 return;
1619         }
1620
1621         if (locals_stack_align) {
1622                 offset += (locals_stack_align - 1);
1623                 offset &= ~(locals_stack_align - 1);
1624         }
1625         if (cfg->arch.omit_fp) {
1626                 cfg->locals_min_stack_offset = offset;
1627                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1628         } else {
1629                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1630                 cfg->locals_max_stack_offset = - offset;
1631         }
1632
1633         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1634                 if (offsets [i] != -1) {
1635                         MonoInst *ins = cfg->varinfo [i];
1636                         ins->opcode = OP_REGOFFSET;
1637                         ins->inst_basereg = cfg->frame_reg;
1638                         if (cfg->arch.omit_fp)
1639                                 ins->inst_offset = (offset + offsets [i]);
1640                         else
1641                                 ins->inst_offset = - (offset + offsets [i]);
1642                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1643                 }
1644         }
1645         offset += locals_stack_size;
1646
1647         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1648                 g_assert (!cfg->arch.omit_fp);
1649                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1650                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1651         }
1652
1653         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1654                 ins = cfg->args [i];
1655                 if (ins->opcode != OP_REGVAR) {
1656                         ArgInfo *ainfo = &cinfo->args [i];
1657                         gboolean inreg = TRUE;
1658
1659                         /* FIXME: Allocate volatile arguments to registers */
1660                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1661                                 inreg = FALSE;
1662
1663                         /*
1664                          * Under AMD64, all registers used to pass arguments to functions
1665                          * are volatile across calls.
1666                          * FIXME: Optimize this.
1667                          */
1668                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1669                                 inreg = FALSE;
1670
1671                         ins->opcode = OP_REGOFFSET;
1672
1673                         switch (ainfo->storage) {
1674                         case ArgInIReg:
1675                         case ArgInFloatSSEReg:
1676                         case ArgInDoubleSSEReg:
1677                         case ArgGSharedVtInReg:
1678                                 if (inreg) {
1679                                         ins->opcode = OP_REGVAR;
1680                                         ins->dreg = ainfo->reg;
1681                                 }
1682                                 break;
1683                         case ArgOnStack:
1684                         case ArgGSharedVtOnStack:
1685                                 g_assert (!cfg->arch.omit_fp);
1686                                 ins->opcode = OP_REGOFFSET;
1687                                 ins->inst_basereg = cfg->frame_reg;
1688                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1689                                 break;
1690                         case ArgValuetypeInReg:
1691                                 break;
1692                         case ArgValuetypeAddrInIReg: {
1693                                 MonoInst *indir;
1694                                 g_assert (!cfg->arch.omit_fp);
1695
1696                                 MONO_INST_NEW (cfg, indir, 0);
1697                                 indir->opcode = OP_REGOFFSET;
1698                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1699                                         indir->inst_basereg = cfg->frame_reg;
1700                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1701                                         offset += (sizeof (gpointer));
1702                                         indir->inst_offset = - offset;
1703                                 }
1704                                 else {
1705                                         indir->inst_basereg = cfg->frame_reg;
1706                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1707                                 }
1708
1709                                 ins->opcode = OP_VTARG_ADDR;
1710                                 ins->inst_left = indir;
1711
1712                                 break;
1713                         }
1714                         default:
1715                                 NOT_IMPLEMENTED;
1716                         }
1717
1718                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
1719                                 ins->opcode = OP_REGOFFSET;
1720                                 ins->inst_basereg = cfg->frame_reg;
1721                                 /* These arguments are saved to the stack in the prolog */
1722                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1723                                 if (cfg->arch.omit_fp) {
1724                                         ins->inst_offset = offset;
1725                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1726                                         // Arguments are yet supported by the stack map creation code
1727                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1728                                 } else {
1729                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1730                                         ins->inst_offset = - offset;
1731                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1732                                 }
1733                         }
1734                 }
1735         }
1736
1737         cfg->stack_offset = offset;
1738 }
1739
1740 void
1741 mono_arch_create_vars (MonoCompile *cfg)
1742 {
1743         MonoMethodSignature *sig;
1744         CallInfo *cinfo;
1745         MonoType *sig_ret;
1746
1747         sig = mono_method_signature (cfg->method);
1748
1749         if (!cfg->arch.cinfo)
1750                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1751         cinfo = (CallInfo *)cfg->arch.cinfo;
1752
1753         if (cinfo->ret.storage == ArgValuetypeInReg)
1754                 cfg->ret_var_is_local = TRUE;
1755
1756         sig_ret = mini_get_underlying_type (sig->ret);
1757         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1758                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1759                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1760                         printf ("vret_addr = ");
1761                         mono_print_ins (cfg->vret_addr);
1762                 }
1763         }
1764
1765         if (cfg->gen_sdb_seq_points) {
1766                 MonoInst *ins;
1767
1768                 if (cfg->compile_aot) {
1769                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1770                         ins->flags |= MONO_INST_VOLATILE;
1771                         cfg->arch.seq_point_info_var = ins;
1772                 }
1773                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1774                 ins->flags |= MONO_INST_VOLATILE;
1775                 cfg->arch.ss_tramp_var = ins;
1776
1777                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1778                 ins->flags |= MONO_INST_VOLATILE;
1779                 cfg->arch.bp_tramp_var = ins;
1780         }
1781
1782         if (cfg->method->save_lmf)
1783                 cfg->create_lmf_var = TRUE;
1784
1785         if (cfg->method->save_lmf) {
1786                 cfg->lmf_ir = TRUE;
1787 #if !defined(TARGET_WIN32)
1788                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1789                         cfg->lmf_ir_mono_lmf = TRUE;
1790 #endif
1791         }
1792 }
1793
1794 static void
1795 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1796 {
1797         MonoInst *ins;
1798
1799         switch (storage) {
1800         case ArgInIReg:
1801                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1802                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1803                 ins->sreg1 = tree->dreg;
1804                 MONO_ADD_INS (cfg->cbb, ins);
1805                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1806                 break;
1807         case ArgInFloatSSEReg:
1808                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1809                 ins->dreg = mono_alloc_freg (cfg);
1810                 ins->sreg1 = tree->dreg;
1811                 MONO_ADD_INS (cfg->cbb, ins);
1812
1813                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1814                 break;
1815         case ArgInDoubleSSEReg:
1816                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1817                 ins->dreg = mono_alloc_freg (cfg);
1818                 ins->sreg1 = tree->dreg;
1819                 MONO_ADD_INS (cfg->cbb, ins);
1820
1821                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1822
1823                 break;
1824         default:
1825                 g_assert_not_reached ();
1826         }
1827 }
1828
1829 static int
1830 arg_storage_to_load_membase (ArgStorage storage)
1831 {
1832         switch (storage) {
1833         case ArgInIReg:
1834 #if defined(__mono_ilp32__)
1835                 return OP_LOADI8_MEMBASE;
1836 #else
1837                 return OP_LOAD_MEMBASE;
1838 #endif
1839         case ArgInDoubleSSEReg:
1840                 return OP_LOADR8_MEMBASE;
1841         case ArgInFloatSSEReg:
1842                 return OP_LOADR4_MEMBASE;
1843         default:
1844                 g_assert_not_reached ();
1845         }
1846
1847         return -1;
1848 }
1849
1850 static void
1851 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1852 {
1853         MonoMethodSignature *tmp_sig;
1854         int sig_reg;
1855
1856         if (call->tail_call)
1857                 NOT_IMPLEMENTED;
1858
1859         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1860
1861         /*
1862          * mono_ArgIterator_Setup assumes the signature cookie is
1863          * passed first and all the arguments which were before it are
1864          * passed on the stack after the signature. So compensate by
1865          * passing a different signature.
1866          */
1867         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1868         tmp_sig->param_count -= call->signature->sentinelpos;
1869         tmp_sig->sentinelpos = 0;
1870         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1871
1872         sig_reg = mono_alloc_ireg (cfg);
1873         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1874
1875         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1876 }
1877
1878 #ifdef ENABLE_LLVM
1879 static inline LLVMArgStorage
1880 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1881 {
1882         switch (storage) {
1883         case ArgInIReg:
1884                 return LLVMArgInIReg;
1885         case ArgNone:
1886                 return LLVMArgNone;
1887         case ArgGSharedVtInReg:
1888         case ArgGSharedVtOnStack:
1889                 return LLVMArgGSharedVt;
1890         default:
1891                 g_assert_not_reached ();
1892                 return LLVMArgNone;
1893         }
1894 }
1895
1896 LLVMCallInfo*
1897 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1898 {
1899         int i, n;
1900         CallInfo *cinfo;
1901         ArgInfo *ainfo;
1902         int j;
1903         LLVMCallInfo *linfo;
1904         MonoType *t, *sig_ret;
1905
1906         n = sig->param_count + sig->hasthis;
1907         sig_ret = mini_get_underlying_type (sig->ret);
1908
1909         cinfo = get_call_info (cfg->mempool, sig);
1910
1911         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1912
1913         /*
1914          * LLVM always uses the native ABI while we use our own ABI, the
1915          * only difference is the handling of vtypes:
1916          * - we only pass/receive them in registers in some cases, and only
1917          *   in 1 or 2 integer registers.
1918          */
1919         switch (cinfo->ret.storage) {
1920         case ArgNone:
1921                 linfo->ret.storage = LLVMArgNone;
1922                 break;
1923         case ArgInIReg:
1924         case ArgInFloatSSEReg:
1925         case ArgInDoubleSSEReg:
1926                 linfo->ret.storage = LLVMArgNormal;
1927                 break;
1928         case ArgValuetypeInReg: {
1929                 ainfo = &cinfo->ret;
1930
1931                 if (sig->pinvoke &&
1932                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1933                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1934                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1935                         cfg->disable_llvm = TRUE;
1936                         return linfo;
1937                 }
1938
1939                 linfo->ret.storage = LLVMArgVtypeInReg;
1940                 for (j = 0; j < 2; ++j)
1941                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1942                 break;
1943         }
1944         case ArgValuetypeAddrInIReg:
1945         case ArgGsharedvtVariableInReg:
1946                 /* Vtype returned using a hidden argument */
1947                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1948                 linfo->vret_arg_index = cinfo->vret_arg_index;
1949                 break;
1950         default:
1951                 g_assert_not_reached ();
1952                 break;
1953         }
1954
1955         for (i = 0; i < n; ++i) {
1956                 ainfo = cinfo->args + i;
1957
1958                 if (i >= sig->hasthis)
1959                         t = sig->params [i - sig->hasthis];
1960                 else
1961                         t = &mono_defaults.int_class->byval_arg;
1962                 t = mini_type_get_underlying_type (t);
1963
1964                 linfo->args [i].storage = LLVMArgNone;
1965
1966                 switch (ainfo->storage) {
1967                 case ArgInIReg:
1968                         linfo->args [i].storage = LLVMArgNormal;
1969                         break;
1970                 case ArgInDoubleSSEReg:
1971                 case ArgInFloatSSEReg:
1972                         linfo->args [i].storage = LLVMArgNormal;
1973                         break;
1974                 case ArgOnStack:
1975                         if (MONO_TYPE_ISSTRUCT (t))
1976                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1977                         else
1978                                 linfo->args [i].storage = LLVMArgNormal;
1979                         break;
1980                 case ArgValuetypeInReg:
1981                         if (sig->pinvoke &&
1982                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1983                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1984                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1985                                 cfg->disable_llvm = TRUE;
1986                                 return linfo;
1987                         }
1988
1989                         linfo->args [i].storage = LLVMArgVtypeInReg;
1990                         for (j = 0; j < 2; ++j)
1991                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1992                         break;
1993                 case ArgGSharedVtInReg:
1994                 case ArgGSharedVtOnStack:
1995                         linfo->args [i].storage = LLVMArgGSharedVt;
1996                         break;
1997                 default:
1998                         cfg->exception_message = g_strdup ("ainfo->storage");
1999                         cfg->disable_llvm = TRUE;
2000                         break;
2001                 }
2002         }
2003
2004         return linfo;
2005 }
2006 #endif
2007
2008 void
2009 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2010 {
2011         MonoInst *arg, *in;
2012         MonoMethodSignature *sig;
2013         MonoType *sig_ret;
2014         int i, n;
2015         CallInfo *cinfo;
2016         ArgInfo *ainfo;
2017
2018         sig = call->signature;
2019         n = sig->param_count + sig->hasthis;
2020
2021         cinfo = get_call_info (cfg->mempool, sig);
2022
2023         sig_ret = sig->ret;
2024
2025         if (COMPILE_LLVM (cfg)) {
2026                 /* We shouldn't be called in the llvm case */
2027                 cfg->disable_llvm = TRUE;
2028                 return;
2029         }
2030
2031         /*
2032          * Emit all arguments which are passed on the stack to prevent register
2033          * allocation problems.
2034          */
2035         for (i = 0; i < n; ++i) {
2036                 MonoType *t;
2037                 ainfo = cinfo->args + i;
2038
2039                 in = call->args [i];
2040
2041                 if (sig->hasthis && i == 0)
2042                         t = &mono_defaults.object_class->byval_arg;
2043                 else
2044                         t = sig->params [i - sig->hasthis];
2045
2046                 t = mini_get_underlying_type (t);
2047                 //XXX what about ArgGSharedVtOnStack here?
2048                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2049                         if (!t->byref) {
2050                                 if (t->type == MONO_TYPE_R4)
2051                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2052                                 else if (t->type == MONO_TYPE_R8)
2053                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2054                                 else
2055                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2056                         } else {
2057                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2058                         }
2059                         if (cfg->compute_gc_maps) {
2060                                 MonoInst *def;
2061
2062                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2063                         }
2064                 }
2065         }
2066
2067         /*
2068          * Emit all parameters passed in registers in non-reverse order for better readability
2069          * and to help the optimization in emit_prolog ().
2070          */
2071         for (i = 0; i < n; ++i) {
2072                 ainfo = cinfo->args + i;
2073
2074                 in = call->args [i];
2075
2076                 if (ainfo->storage == ArgInIReg)
2077                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2078         }
2079
2080         for (i = n - 1; i >= 0; --i) {
2081                 MonoType *t;
2082
2083                 ainfo = cinfo->args + i;
2084
2085                 in = call->args [i];
2086
2087                 if (sig->hasthis && i == 0)
2088                         t = &mono_defaults.object_class->byval_arg;
2089                 else
2090                         t = sig->params [i - sig->hasthis];
2091                 t = mini_get_underlying_type (t);
2092
2093                 switch (ainfo->storage) {
2094                 case ArgInIReg:
2095                         /* Already done */
2096                         break;
2097                 case ArgInFloatSSEReg:
2098                 case ArgInDoubleSSEReg:
2099                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2100                         break;
2101                 case ArgOnStack:
2102                 case ArgValuetypeInReg:
2103                 case ArgValuetypeAddrInIReg:
2104                 case ArgGSharedVtInReg:
2105                 case ArgGSharedVtOnStack: {
2106                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2107                                 /* Already emitted above */
2108                                 break;
2109                         //FIXME what about ArgGSharedVtOnStack ?
2110                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2111                                 MonoInst *call_inst = (MonoInst*)call;
2112                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2113                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2114                                 break;
2115                         }
2116
2117                         guint32 align;
2118                         guint32 size;
2119
2120                         if (sig->pinvoke)
2121                                 size = mono_type_native_stack_size (t, &align);
2122                         else {
2123                                 /*
2124                                  * Other backends use mono_type_stack_size (), but that
2125                                  * aligns the size to 8, which is larger than the size of
2126                                  * the source, leading to reads of invalid memory if the
2127                                  * source is at the end of address space.
2128                                  */
2129                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2130                         }
2131
2132                         if (size >= 10000) {
2133                                 /* Avoid asserts in emit_memcpy () */
2134                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2135                                 /* Continue normally */
2136                         }
2137
2138                         if (size > 0 || ainfo->pass_empty_struct) {
2139                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2140                                 arg->sreg1 = in->dreg;
2141                                 arg->klass = mono_class_from_mono_type (t);
2142                                 arg->backend.size = size;
2143                                 arg->inst_p0 = call;
2144                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2145                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2146
2147                                 MONO_ADD_INS (cfg->cbb, arg);
2148                         }
2149                         break;
2150                 }
2151                 default:
2152                         g_assert_not_reached ();
2153                 }
2154
2155                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2156                         /* Emit the signature cookie just before the implicit arguments */
2157                         emit_sig_cookie (cfg, call, cinfo);
2158         }
2159
2160         /* Handle the case where there are no implicit arguments */
2161         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2162                 emit_sig_cookie (cfg, call, cinfo);
2163
2164         switch (cinfo->ret.storage) {
2165         case ArgValuetypeInReg:
2166                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2167                         /*
2168                          * Tell the JIT to use a more efficient calling convention: call using
2169                          * OP_CALL, compute the result location after the call, and save the
2170                          * result there.
2171                          */
2172                         call->vret_in_reg = TRUE;
2173                         /*
2174                          * Nullify the instruction computing the vret addr to enable
2175                          * future optimizations.
2176                          */
2177                         if (call->vret_var)
2178                                 NULLIFY_INS (call->vret_var);
2179                 } else {
2180                         if (call->tail_call)
2181                                 NOT_IMPLEMENTED;
2182                         /*
2183                          * The valuetype is in RAX:RDX after the call, need to be copied to
2184                          * the stack. Push the address here, so the call instruction can
2185                          * access it.
2186                          */
2187                         if (!cfg->arch.vret_addr_loc) {
2188                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2189                                 /* Prevent it from being register allocated or optimized away */
2190                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2191                         }
2192
2193                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2194                 }
2195                 break;
2196         case ArgValuetypeAddrInIReg:
2197         case ArgGsharedvtVariableInReg: {
2198                 MonoInst *vtarg;
2199                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2200                 vtarg->sreg1 = call->vret_var->dreg;
2201                 vtarg->dreg = mono_alloc_preg (cfg);
2202                 MONO_ADD_INS (cfg->cbb, vtarg);
2203
2204                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2205                 break;
2206         }
2207         default:
2208                 break;
2209         }
2210
2211         if (cfg->method->save_lmf) {
2212                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2213                 MONO_ADD_INS (cfg->cbb, arg);
2214         }
2215
2216         call->stack_usage = cinfo->stack_usage;
2217 }
2218
2219 void
2220 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2221 {
2222         MonoInst *arg;
2223         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2224         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2225         int size = ins->backend.size;
2226
2227         switch (ainfo->storage) {
2228         case ArgValuetypeInReg: {
2229                 MonoInst *load;
2230                 int part;
2231
2232                 for (part = 0; part < 2; ++part) {
2233                         if (ainfo->pair_storage [part] == ArgNone)
2234                                 continue;
2235
2236                         if (ainfo->pass_empty_struct) {
2237                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2238                                 NEW_ICONST (cfg, load, 0);
2239                         }
2240                         else {
2241                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2242                                 load->inst_basereg = src->dreg;
2243                                 load->inst_offset = part * sizeof(mgreg_t);
2244
2245                                 switch (ainfo->pair_storage [part]) {
2246                                 case ArgInIReg:
2247                                         load->dreg = mono_alloc_ireg (cfg);
2248                                         break;
2249                                 case ArgInDoubleSSEReg:
2250                                 case ArgInFloatSSEReg:
2251                                         load->dreg = mono_alloc_freg (cfg);
2252                                         break;
2253                                 default:
2254                                         g_assert_not_reached ();
2255                                 }
2256                         }
2257
2258                         MONO_ADD_INS (cfg->cbb, load);
2259
2260                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2261                 }
2262                 break;
2263         }
2264         case ArgValuetypeAddrInIReg: {
2265                 MonoInst *vtaddr, *load;
2266                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2267
2268                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2269                 cfg->has_indirection = TRUE;
2270                 load->inst_p0 = vtaddr;
2271                 vtaddr->flags |= MONO_INST_INDIRECT;
2272                 load->type = STACK_MP;
2273                 load->klass = vtaddr->klass;
2274                 load->dreg = mono_alloc_ireg (cfg);
2275                 MONO_ADD_INS (cfg->cbb, load);
2276                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2277
2278                 if (ainfo->pair_storage [0] == ArgInIReg) {
2279                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2280                         arg->dreg = mono_alloc_ireg (cfg);
2281                         arg->sreg1 = load->dreg;
2282                         arg->inst_imm = 0;
2283                         MONO_ADD_INS (cfg->cbb, arg);
2284                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2285                 } else {
2286                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2287                 }
2288                 break;
2289         }
2290         case ArgGSharedVtInReg:
2291                 /* Pass by addr */
2292                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2293                 break;
2294         case ArgGSharedVtOnStack:
2295                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2296                 break;
2297         default:
2298                 if (size == 8) {
2299                         int dreg = mono_alloc_ireg (cfg);
2300
2301                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2302                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2303                 } else if (size <= 40) {
2304                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2305                 } else {
2306                         // FIXME: Code growth
2307                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2308                 }
2309
2310                 if (cfg->compute_gc_maps) {
2311                         MonoInst *def;
2312                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2313                 }
2314         }
2315 }
2316
2317 void
2318 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2319 {
2320         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2321
2322         if (ret->type == MONO_TYPE_R4) {
2323                 if (COMPILE_LLVM (cfg))
2324                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2325                 else
2326                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2327                 return;
2328         } else if (ret->type == MONO_TYPE_R8) {
2329                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2330                 return;
2331         }
2332
2333         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2334 }
2335
2336 #endif /* DISABLE_JIT */
2337
2338 #define EMIT_COND_BRANCH(ins,cond,sign) \
2339         if (ins->inst_true_bb->native_offset) { \
2340                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2341         } else { \
2342                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2343                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2344             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2345                         x86_branch8 (code, cond, 0, sign); \
2346                 else \
2347                         x86_branch32 (code, cond, 0, sign); \
2348 }
2349
2350 typedef struct {
2351         MonoMethodSignature *sig;
2352         CallInfo *cinfo;
2353 } ArchDynCallInfo;
2354
2355 static gboolean
2356 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2357 {
2358         int i;
2359
2360         switch (cinfo->ret.storage) {
2361         case ArgNone:
2362         case ArgInIReg:
2363         case ArgInFloatSSEReg:
2364         case ArgInDoubleSSEReg:
2365         case ArgValuetypeAddrInIReg:
2366                 break;
2367         case ArgValuetypeInReg: {
2368                 ArgInfo *ainfo = &cinfo->ret;
2369
2370                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2371                         return FALSE;
2372                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2373                         return FALSE;
2374                 break;
2375         }
2376         default:
2377                 return FALSE;
2378         }
2379
2380         for (i = 0; i < cinfo->nargs; ++i) {
2381                 ArgInfo *ainfo = &cinfo->args [i];
2382                 switch (ainfo->storage) {
2383                 case ArgInIReg:
2384                 case ArgInFloatSSEReg:
2385                 case ArgInDoubleSSEReg:
2386                         break;
2387                 case ArgValuetypeInReg:
2388                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2389                                 return FALSE;
2390                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2391                                 return FALSE;
2392                         break;
2393                 case ArgOnStack:
2394                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2395                                 return FALSE;
2396                         break;
2397                 default:
2398                         return FALSE;
2399                 }
2400         }
2401
2402         return TRUE;
2403 }
2404
2405 /*
2406  * mono_arch_dyn_call_prepare:
2407  *
2408  *   Return a pointer to an arch-specific structure which contains information
2409  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2410  * supported for SIG.
2411  * This function is equivalent to ffi_prep_cif in libffi.
2412  */
2413 MonoDynCallInfo*
2414 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2415 {
2416         ArchDynCallInfo *info;
2417         CallInfo *cinfo;
2418
2419         cinfo = get_call_info (NULL, sig);
2420
2421         if (!dyn_call_supported (sig, cinfo)) {
2422                 g_free (cinfo);
2423                 return NULL;
2424         }
2425
2426         info = g_new0 (ArchDynCallInfo, 1);
2427         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2428         info->sig = sig;
2429         info->cinfo = cinfo;
2430
2431         return (MonoDynCallInfo*)info;
2432 }
2433
2434 /*
2435  * mono_arch_dyn_call_free:
2436  *
2437  *   Free a MonoDynCallInfo structure.
2438  */
2439 void
2440 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2441 {
2442         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2443
2444         g_free (ainfo->cinfo);
2445         g_free (ainfo);
2446 }
2447
2448 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2449 #define GREG_TO_PTR(greg) (gpointer)(greg)
2450
2451 /*
2452  * mono_arch_get_start_dyn_call:
2453  *
2454  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2455  * store the result into BUF.
2456  * ARGS should be an array of pointers pointing to the arguments.
2457  * RET should point to a memory buffer large enought to hold the result of the
2458  * call.
2459  * This function should be as fast as possible, any work which does not depend
2460  * on the actual values of the arguments should be done in
2461  * mono_arch_dyn_call_prepare ().
2462  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2463  * libffi.
2464  */
2465 void
2466 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2467 {
2468         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2469         DynCallArgs *p = (DynCallArgs*)buf;
2470         int arg_index, greg, freg, i, pindex;
2471         MonoMethodSignature *sig = dinfo->sig;
2472         int buffer_offset = 0;
2473         static int param_reg_to_index [16];
2474         static gboolean param_reg_to_index_inited;
2475
2476         if (!param_reg_to_index_inited) {
2477                 for (i = 0; i < PARAM_REGS; ++i)
2478                         param_reg_to_index [param_regs [i]] = i;
2479                 mono_memory_barrier ();
2480                 param_reg_to_index_inited = 1;
2481         }
2482
2483         g_assert (buf_len >= sizeof (DynCallArgs));
2484
2485         p->res = 0;
2486         p->ret = ret;
2487
2488         arg_index = 0;
2489         greg = 0;
2490         freg = 0;
2491         pindex = 0;
2492
2493         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2494                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2495                 if (!sig->hasthis)
2496                         pindex = 1;
2497         }
2498
2499         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2500                 p->regs [greg ++] = PTR_TO_GREG(ret);
2501
2502         for (; pindex < sig->param_count; pindex++) {
2503                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2504                 gpointer *arg = args [arg_index ++];
2505                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2506                 int slot;
2507
2508                 if (ainfo->storage == ArgOnStack) {
2509                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2510                 } else {
2511                         slot = param_reg_to_index [ainfo->reg];
2512                 }
2513
2514                 if (t->byref) {
2515                         p->regs [slot] = PTR_TO_GREG(*(arg));
2516                         greg ++;
2517                         continue;
2518                 }
2519
2520                 switch (t->type) {
2521                 case MONO_TYPE_STRING:
2522                 case MONO_TYPE_CLASS:
2523                 case MONO_TYPE_ARRAY:
2524                 case MONO_TYPE_SZARRAY:
2525                 case MONO_TYPE_OBJECT:
2526                 case MONO_TYPE_PTR:
2527                 case MONO_TYPE_I:
2528                 case MONO_TYPE_U:
2529 #if !defined(__mono_ilp32__)
2530                 case MONO_TYPE_I8:
2531                 case MONO_TYPE_U8:
2532 #endif
2533                         p->regs [slot] = PTR_TO_GREG(*(arg));
2534                         break;
2535 #if defined(__mono_ilp32__)
2536                 case MONO_TYPE_I8:
2537                 case MONO_TYPE_U8:
2538                         p->regs [slot] = *(guint64*)(arg);
2539                         break;
2540 #endif
2541                 case MONO_TYPE_U1:
2542                         p->regs [slot] = *(guint8*)(arg);
2543                         break;
2544                 case MONO_TYPE_I1:
2545                         p->regs [slot] = *(gint8*)(arg);
2546                         break;
2547                 case MONO_TYPE_I2:
2548                         p->regs [slot] = *(gint16*)(arg);
2549                         break;
2550                 case MONO_TYPE_U2:
2551                         p->regs [slot] = *(guint16*)(arg);
2552                         break;
2553                 case MONO_TYPE_I4:
2554                         p->regs [slot] = *(gint32*)(arg);
2555                         break;
2556                 case MONO_TYPE_U4:
2557                         p->regs [slot] = *(guint32*)(arg);
2558                         break;
2559                 case MONO_TYPE_R4: {
2560                         double d;
2561
2562                         *(float*)&d = *(float*)(arg);
2563                         p->has_fp = 1;
2564                         p->fregs [freg ++] = d;
2565                         break;
2566                 }
2567                 case MONO_TYPE_R8:
2568                         p->has_fp = 1;
2569                         p->fregs [freg ++] = *(double*)(arg);
2570                         break;
2571                 case MONO_TYPE_GENERICINST:
2572                     if (MONO_TYPE_IS_REFERENCE (t)) {
2573                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2574                                 break;
2575                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2576                                         MonoClass *klass = mono_class_from_mono_type (t);
2577                                         guint8 *nullable_buf;
2578                                         int size;
2579
2580                                         size = mono_class_value_size (klass, NULL);
2581                                         nullable_buf = p->buffer + buffer_offset;
2582                                         buffer_offset += size;
2583                                         g_assert (buffer_offset <= 256);
2584
2585                                         /* The argument pointed to by arg is either a boxed vtype or null */
2586                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2587
2588                                         arg = (gpointer*)nullable_buf;
2589                                         /* Fall though */
2590
2591                         } else {
2592                                 /* Fall through */
2593                         }
2594                 case MONO_TYPE_VALUETYPE: {
2595                         switch (ainfo->storage) {
2596                         case ArgValuetypeInReg:
2597                                 if (ainfo->pair_storage [0] != ArgNone) {
2598                                         slot = param_reg_to_index [ainfo->pair_regs [0]];
2599                                         g_assert (ainfo->pair_storage [0] == ArgInIReg);
2600                                         p->regs [slot] = ((mgreg_t*)(arg))[0];
2601                                 }
2602                                 if (ainfo->pair_storage [1] != ArgNone) {
2603                                         slot = param_reg_to_index [ainfo->pair_regs [1]];
2604                                         g_assert (ainfo->pair_storage [1] == ArgInIReg);
2605                                         p->regs [slot] = ((mgreg_t*)(arg))[1];
2606                                 }
2607                                 break;
2608                         case ArgOnStack:
2609                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2610                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2611                                 break;
2612                         default:
2613                                 g_assert_not_reached ();
2614                                 break;
2615                         }
2616                         break;
2617                 }
2618                 default:
2619                         g_assert_not_reached ();
2620                 }
2621         }
2622 }
2623
2624 /*
2625  * mono_arch_finish_dyn_call:
2626  *
2627  *   Store the result of a dyn call into the return value buffer passed to
2628  * start_dyn_call ().
2629  * This function should be as fast as possible, any work which does not depend
2630  * on the actual values of the arguments should be done in
2631  * mono_arch_dyn_call_prepare ().
2632  */
2633 void
2634 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2635 {
2636         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2637         MonoMethodSignature *sig = dinfo->sig;
2638         DynCallArgs *dargs = (DynCallArgs*)buf;
2639         guint8 *ret = dargs->ret;
2640         mgreg_t res = dargs->res;
2641         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2642
2643         switch (sig_ret->type) {
2644         case MONO_TYPE_VOID:
2645                 *(gpointer*)ret = NULL;
2646                 break;
2647         case MONO_TYPE_STRING:
2648         case MONO_TYPE_CLASS:
2649         case MONO_TYPE_ARRAY:
2650         case MONO_TYPE_SZARRAY:
2651         case MONO_TYPE_OBJECT:
2652         case MONO_TYPE_I:
2653         case MONO_TYPE_U:
2654         case MONO_TYPE_PTR:
2655                 *(gpointer*)ret = GREG_TO_PTR(res);
2656                 break;
2657         case MONO_TYPE_I1:
2658                 *(gint8*)ret = res;
2659                 break;
2660         case MONO_TYPE_U1:
2661                 *(guint8*)ret = res;
2662                 break;
2663         case MONO_TYPE_I2:
2664                 *(gint16*)ret = res;
2665                 break;
2666         case MONO_TYPE_U2:
2667                 *(guint16*)ret = res;
2668                 break;
2669         case MONO_TYPE_I4:
2670                 *(gint32*)ret = res;
2671                 break;
2672         case MONO_TYPE_U4:
2673                 *(guint32*)ret = res;
2674                 break;
2675         case MONO_TYPE_I8:
2676                 *(gint64*)ret = res;
2677                 break;
2678         case MONO_TYPE_U8:
2679                 *(guint64*)ret = res;
2680                 break;
2681         case MONO_TYPE_R4:
2682                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2683                 break;
2684         case MONO_TYPE_R8:
2685                 *(double*)ret = dargs->fregs [0];
2686                 break;
2687         case MONO_TYPE_GENERICINST:
2688                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2689                         *(gpointer*)ret = GREG_TO_PTR(res);
2690                         break;
2691                 } else {
2692                         /* Fall through */
2693                 }
2694         case MONO_TYPE_VALUETYPE:
2695                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2696                         /* Nothing to do */
2697                 } else {
2698                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2699
2700                         g_assert (ainfo->storage == ArgValuetypeInReg);
2701
2702                         if (ainfo->pair_storage [0] != ArgNone) {
2703                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2704                                 ((mgreg_t*)ret)[0] = res;
2705                         }
2706
2707                         g_assert (ainfo->pair_storage [1] == ArgNone);
2708                 }
2709                 break;
2710         default:
2711                 g_assert_not_reached ();
2712         }
2713 }
2714
2715 /* emit an exception if condition is fail */
2716 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2717         do {                                                        \
2718                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2719                 if (tins == NULL) {                                                                             \
2720                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2721                                         MONO_PATCH_INFO_EXC, exc_name);  \
2722                         x86_branch32 (code, cond, 0, signed);               \
2723                 } else {        \
2724                         EMIT_COND_BRANCH (tins, cond, signed);  \
2725                 }                       \
2726         } while (0);
2727
2728 #define EMIT_FPCOMPARE(code) do { \
2729         amd64_fcompp (code); \
2730         amd64_fnstsw (code); \
2731 } while (0);
2732
2733 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2734     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2735         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2736         amd64_ ##op (code); \
2737         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2738         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2739 } while (0);
2740
2741 static guint8*
2742 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2743 {
2744         gboolean no_patch = FALSE;
2745
2746         /*
2747          * FIXME: Add support for thunks
2748          */
2749         {
2750                 gboolean near_call = FALSE;
2751
2752                 /*
2753                  * Indirect calls are expensive so try to make a near call if possible.
2754                  * The caller memory is allocated by the code manager so it is
2755                  * guaranteed to be at a 32 bit offset.
2756                  */
2757
2758                 if (patch_type != MONO_PATCH_INFO_ABS) {
2759                         /* The target is in memory allocated using the code manager */
2760                         near_call = TRUE;
2761
2762                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2763                                 if (((MonoMethod*)data)->klass->image->aot_module)
2764                                         /* The callee might be an AOT method */
2765                                         near_call = FALSE;
2766                                 if (((MonoMethod*)data)->dynamic)
2767                                         /* The target is in malloc-ed memory */
2768                                         near_call = FALSE;
2769                         }
2770
2771                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2772                                 /*
2773                                  * The call might go directly to a native function without
2774                                  * the wrapper.
2775                                  */
2776                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2777                                 if (mi) {
2778                                         gconstpointer target = mono_icall_get_wrapper (mi);
2779                                         if ((((guint64)target) >> 32) != 0)
2780                                                 near_call = FALSE;
2781                                 }
2782                         }
2783                 }
2784                 else {
2785                         MonoJumpInfo *jinfo = NULL;
2786
2787                         if (cfg->abs_patches)
2788                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2789                         if (jinfo) {
2790                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2791                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2792                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2793                                                 near_call = TRUE;
2794                                         no_patch = TRUE;
2795                                 } else {
2796                                         /*
2797                                          * This is not really an optimization, but required because the
2798                                          * generic class init trampolines use R11 to pass the vtable.
2799                                          */
2800                                         near_call = TRUE;
2801                                 }
2802                         } else {
2803                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2804                                 if (info) {
2805                                         if (info->func == info->wrapper) {
2806                                                 /* No wrapper */
2807                                                 if ((((guint64)info->func) >> 32) == 0)
2808                                                         near_call = TRUE;
2809                                         }
2810                                         else {
2811                                                 /* See the comment in mono_codegen () */
2812                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2813                                                         near_call = TRUE;
2814                                         }
2815                                 }
2816                                 else if ((((guint64)data) >> 32) == 0) {
2817                                         near_call = TRUE;
2818                                         no_patch = TRUE;
2819                                 }
2820                         }
2821                 }
2822
2823                 if (cfg->method->dynamic)
2824                         /* These methods are allocated using malloc */
2825                         near_call = FALSE;
2826
2827 #ifdef MONO_ARCH_NOMAP32BIT
2828                 near_call = FALSE;
2829 #endif
2830                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2831                 if (optimize_for_xen)
2832                         near_call = FALSE;
2833
2834                 if (cfg->compile_aot) {
2835                         near_call = TRUE;
2836                         no_patch = TRUE;
2837                 }
2838
2839                 if (near_call) {
2840                         /*
2841                          * Align the call displacement to an address divisible by 4 so it does
2842                          * not span cache lines. This is required for code patching to work on SMP
2843                          * systems.
2844                          */
2845                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2846                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2847                                 amd64_padding (code, pad_size);
2848                         }
2849                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2850                         amd64_call_code (code, 0);
2851                 }
2852                 else {
2853                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2854                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2855                         amd64_call_reg (code, GP_SCRATCH_REG);
2856                 }
2857         }
2858
2859         return code;
2860 }
2861
2862 static inline guint8*
2863 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2864 {
2865 #ifdef TARGET_WIN32
2866         if (win64_adjust_stack)
2867                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2868 #endif
2869         code = emit_call_body (cfg, code, patch_type, data);
2870 #ifdef TARGET_WIN32
2871         if (win64_adjust_stack)
2872                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2873 #endif
2874
2875         return code;
2876 }
2877
2878 static inline int
2879 store_membase_imm_to_store_membase_reg (int opcode)
2880 {
2881         switch (opcode) {
2882         case OP_STORE_MEMBASE_IMM:
2883                 return OP_STORE_MEMBASE_REG;
2884         case OP_STOREI4_MEMBASE_IMM:
2885                 return OP_STOREI4_MEMBASE_REG;
2886         case OP_STOREI8_MEMBASE_IMM:
2887                 return OP_STOREI8_MEMBASE_REG;
2888         }
2889
2890         return -1;
2891 }
2892
2893 #ifndef DISABLE_JIT
2894
2895 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2896
2897 /*
2898  * mono_arch_peephole_pass_1:
2899  *
2900  *   Perform peephole opts which should/can be performed before local regalloc
2901  */
2902 void
2903 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2904 {
2905         MonoInst *ins, *n;
2906
2907         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2908                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2909
2910                 switch (ins->opcode) {
2911                 case OP_ADD_IMM:
2912                 case OP_IADD_IMM:
2913                 case OP_LADD_IMM:
2914                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2915                                 /*
2916                                  * X86_LEA is like ADD, but doesn't have the
2917                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2918                                  * its operand to 64 bit.
2919                                  */
2920                                 ins->opcode = OP_X86_LEA_MEMBASE;
2921                                 ins->inst_basereg = ins->sreg1;
2922                         }
2923                         break;
2924                 case OP_LXOR:
2925                 case OP_IXOR:
2926                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2927                                 MonoInst *ins2;
2928
2929                                 /*
2930                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2931                                  * the latter has length 2-3 instead of 6 (reverse constant
2932                                  * propagation). These instruction sequences are very common
2933                                  * in the initlocals bblock.
2934                                  */
2935                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2936                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2937                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2938                                                 ins2->sreg1 = ins->dreg;
2939                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2940                                                 /* Continue */
2941                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2942                                                 NULLIFY_INS (ins2);
2943                                                 /* Continue */
2944                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2945                                                 /* Continue */
2946                                         } else {
2947                                                 break;
2948                                         }
2949                                 }
2950                         }
2951                         break;
2952                 case OP_COMPARE_IMM:
2953                 case OP_LCOMPARE_IMM:
2954                         /* OP_COMPARE_IMM (reg, 0)
2955                          * -->
2956                          * OP_AMD64_TEST_NULL (reg)
2957                          */
2958                         if (!ins->inst_imm)
2959                                 ins->opcode = OP_AMD64_TEST_NULL;
2960                         break;
2961                 case OP_ICOMPARE_IMM:
2962                         if (!ins->inst_imm)
2963                                 ins->opcode = OP_X86_TEST_NULL;
2964                         break;
2965                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2966                         /*
2967                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2968                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2969                          * -->
2970                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2971                          * OP_COMPARE_IMM reg, imm
2972                          *
2973                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2974                          */
2975                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2976                             ins->inst_basereg == last_ins->inst_destbasereg &&
2977                             ins->inst_offset == last_ins->inst_offset) {
2978                                         ins->opcode = OP_ICOMPARE_IMM;
2979                                         ins->sreg1 = last_ins->sreg1;
2980
2981                                         /* check if we can remove cmp reg,0 with test null */
2982                                         if (!ins->inst_imm)
2983                                                 ins->opcode = OP_X86_TEST_NULL;
2984                                 }
2985
2986                         break;
2987                 }
2988
2989                 mono_peephole_ins (bb, ins);
2990         }
2991 }
2992
2993 void
2994 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2995 {
2996         MonoInst *ins, *n;
2997
2998         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2999                 switch (ins->opcode) {
3000                 case OP_ICONST:
3001                 case OP_I8CONST: {
3002                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3003                         /* reg = 0 -> XOR (reg, reg) */
3004                         /* XOR sets cflags on x86, so we cant do it always */
3005                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3006                                 ins->opcode = OP_LXOR;
3007                                 ins->sreg1 = ins->dreg;
3008                                 ins->sreg2 = ins->dreg;
3009                                 /* Fall through */
3010                         } else {
3011                                 break;
3012                         }
3013                 }
3014                 case OP_LXOR:
3015                         /*
3016                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3017                          * 0 result into 64 bits.
3018                          */
3019                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3020                                 ins->opcode = OP_IXOR;
3021                         }
3022                         /* Fall through */
3023                 case OP_IXOR:
3024                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3025                                 MonoInst *ins2;
3026
3027                                 /*
3028                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3029                                  * the latter has length 2-3 instead of 6 (reverse constant
3030                                  * propagation). These instruction sequences are very common
3031                                  * in the initlocals bblock.
3032                                  */
3033                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3034                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3035                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3036                                                 ins2->sreg1 = ins->dreg;
3037                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3038                                                 /* Continue */
3039                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3040                                                 NULLIFY_INS (ins2);
3041                                                 /* Continue */
3042                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3043                                                 /* Continue */
3044                                         } else {
3045                                                 break;
3046                                         }
3047                                 }
3048                         }
3049                         break;
3050                 case OP_IADD_IMM:
3051                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3052                                 ins->opcode = OP_X86_INC_REG;
3053                         break;
3054                 case OP_ISUB_IMM:
3055                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3056                                 ins->opcode = OP_X86_DEC_REG;
3057                         break;
3058                 }
3059
3060                 mono_peephole_ins (bb, ins);
3061         }
3062 }
3063
3064 #define NEW_INS(cfg,ins,dest,op) do {   \
3065                 MONO_INST_NEW ((cfg), (dest), (op)); \
3066         (dest)->cil_code = (ins)->cil_code; \
3067         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3068         } while (0)
3069
3070 /*
3071  * mono_arch_lowering_pass:
3072  *
3073  *  Converts complex opcodes into simpler ones so that each IR instruction
3074  * corresponds to one machine instruction.
3075  */
3076 void
3077 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3078 {
3079         MonoInst *ins, *n, *temp;
3080
3081         /*
3082          * FIXME: Need to add more instructions, but the current machine
3083          * description can't model some parts of the composite instructions like
3084          * cdq.
3085          */
3086         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3087                 switch (ins->opcode) {
3088                 case OP_DIV_IMM:
3089                 case OP_REM_IMM:
3090                 case OP_IDIV_IMM:
3091                 case OP_IDIV_UN_IMM:
3092                 case OP_IREM_UN_IMM:
3093                 case OP_LREM_IMM:
3094                 case OP_IREM_IMM:
3095                         mono_decompose_op_imm (cfg, bb, ins);
3096                         break;
3097                 case OP_COMPARE_IMM:
3098                 case OP_LCOMPARE_IMM:
3099                         if (!amd64_use_imm32 (ins->inst_imm)) {
3100                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3101                                 temp->inst_c0 = ins->inst_imm;
3102                                 temp->dreg = mono_alloc_ireg (cfg);
3103                                 ins->opcode = OP_COMPARE;
3104                                 ins->sreg2 = temp->dreg;
3105                         }
3106                         break;
3107 #ifndef __mono_ilp32__
3108                 case OP_LOAD_MEMBASE:
3109 #endif
3110                 case OP_LOADI8_MEMBASE:
3111                 /*  Don't generate memindex opcodes (to simplify */
3112                 /*  read sandboxing) */
3113                         if (!amd64_use_imm32 (ins->inst_offset)) {
3114                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3115                                 temp->inst_c0 = ins->inst_offset;
3116                                 temp->dreg = mono_alloc_ireg (cfg);
3117                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3118                                 ins->inst_indexreg = temp->dreg;
3119                         }
3120                         break;
3121 #ifndef __mono_ilp32__
3122                 case OP_STORE_MEMBASE_IMM:
3123 #endif
3124                 case OP_STOREI8_MEMBASE_IMM:
3125                         if (!amd64_use_imm32 (ins->inst_imm)) {
3126                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3127                                 temp->inst_c0 = ins->inst_imm;
3128                                 temp->dreg = mono_alloc_ireg (cfg);
3129                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3130                                 ins->sreg1 = temp->dreg;
3131                         }
3132                         break;
3133 #ifdef MONO_ARCH_SIMD_INTRINSICS
3134                 case OP_EXPAND_I1: {
3135                                 int temp_reg1 = mono_alloc_ireg (cfg);
3136                                 int temp_reg2 = mono_alloc_ireg (cfg);
3137                                 int original_reg = ins->sreg1;
3138
3139                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3140                                 temp->sreg1 = original_reg;
3141                                 temp->dreg = temp_reg1;
3142
3143                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3144                                 temp->sreg1 = temp_reg1;
3145                                 temp->dreg = temp_reg2;
3146                                 temp->inst_imm = 8;
3147
3148                                 NEW_INS (cfg, ins, temp, OP_LOR);
3149                                 temp->sreg1 = temp->dreg = temp_reg2;
3150                                 temp->sreg2 = temp_reg1;
3151
3152                                 ins->opcode = OP_EXPAND_I2;
3153                                 ins->sreg1 = temp_reg2;
3154                         }
3155                         break;
3156 #endif
3157                 default:
3158                         break;
3159                 }
3160         }
3161
3162         bb->max_vreg = cfg->next_vreg;
3163 }
3164
3165 static const int
3166 branch_cc_table [] = {
3167         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3168         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3169         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3170 };
3171
3172 /* Maps CMP_... constants to X86_CC_... constants */
3173 static const int
3174 cc_table [] = {
3175         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3176         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3177 };
3178
3179 static const int
3180 cc_signed_table [] = {
3181         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3182         FALSE, FALSE, FALSE, FALSE
3183 };
3184
3185 /*#include "cprop.c"*/
3186
3187 static unsigned char*
3188 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3189 {
3190         if (size == 8)
3191                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3192         else
3193                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3194
3195         if (size == 1)
3196                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3197         else if (size == 2)
3198                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3199         return code;
3200 }
3201
3202 static unsigned char*
3203 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3204 {
3205         int sreg = tree->sreg1;
3206         int need_touch = FALSE;
3207
3208 #if defined(TARGET_WIN32)
3209         need_touch = TRUE;
3210 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3211         if (!tree->flags & MONO_INST_INIT)
3212                 need_touch = TRUE;
3213 #endif
3214
3215         if (need_touch) {
3216                 guint8* br[5];
3217
3218                 /*
3219                  * Under Windows:
3220                  * If requested stack size is larger than one page,
3221                  * perform stack-touch operation
3222                  */
3223                 /*
3224                  * Generate stack probe code.
3225                  * Under Windows, it is necessary to allocate one page at a time,
3226                  * "touching" stack after each successful sub-allocation. This is
3227                  * because of the way stack growth is implemented - there is a
3228                  * guard page before the lowest stack page that is currently commited.
3229                  * Stack normally grows sequentially so OS traps access to the
3230                  * guard page and commits more pages when needed.
3231                  */
3232                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3233                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3234
3235                 br[2] = code; /* loop */
3236                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3237                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3238                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3239                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3240                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3241                 amd64_patch (br[3], br[2]);
3242                 amd64_test_reg_reg (code, sreg, sreg);
3243                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3244                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3245
3246                 br[1] = code; x86_jump8 (code, 0);
3247
3248                 amd64_patch (br[0], code);
3249                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3250                 amd64_patch (br[1], code);
3251                 amd64_patch (br[4], code);
3252         }
3253         else
3254                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3255
3256         if (tree->flags & MONO_INST_INIT) {
3257                 int offset = 0;
3258                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3259                         amd64_push_reg (code, AMD64_RAX);
3260                         offset += 8;
3261                 }
3262                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3263                         amd64_push_reg (code, AMD64_RCX);
3264                         offset += 8;
3265                 }
3266                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3267                         amd64_push_reg (code, AMD64_RDI);
3268                         offset += 8;
3269                 }
3270
3271                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3272                 if (sreg != AMD64_RCX)
3273                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3274                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3275
3276                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3277                 if (cfg->param_area)
3278                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3279                 amd64_cld (code);
3280                 amd64_prefix (code, X86_REP_PREFIX);
3281                 amd64_stosl (code);
3282
3283                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3284                         amd64_pop_reg (code, AMD64_RDI);
3285                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3286                         amd64_pop_reg (code, AMD64_RCX);
3287                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3288                         amd64_pop_reg (code, AMD64_RAX);
3289         }
3290         return code;
3291 }
3292
3293 static guint8*
3294 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3295 {
3296         CallInfo *cinfo;
3297         guint32 quad;
3298
3299         /* Move return value to the target register */
3300         /* FIXME: do this in the local reg allocator */
3301         switch (ins->opcode) {
3302         case OP_CALL:
3303         case OP_CALL_REG:
3304         case OP_CALL_MEMBASE:
3305         case OP_LCALL:
3306         case OP_LCALL_REG:
3307         case OP_LCALL_MEMBASE:
3308                 g_assert (ins->dreg == AMD64_RAX);
3309                 break;
3310         case OP_FCALL:
3311         case OP_FCALL_REG:
3312         case OP_FCALL_MEMBASE: {
3313                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3314                 if (rtype->type == MONO_TYPE_R4) {
3315                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3316                 }
3317                 else {
3318                         if (ins->dreg != AMD64_XMM0)
3319                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3320                 }
3321                 break;
3322         }
3323         case OP_RCALL:
3324         case OP_RCALL_REG:
3325         case OP_RCALL_MEMBASE:
3326                 if (ins->dreg != AMD64_XMM0)
3327                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3328                 break;
3329         case OP_VCALL:
3330         case OP_VCALL_REG:
3331         case OP_VCALL_MEMBASE:
3332         case OP_VCALL2:
3333         case OP_VCALL2_REG:
3334         case OP_VCALL2_MEMBASE:
3335                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3336                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3337                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3338
3339                         /* Load the destination address */
3340                         g_assert (loc->opcode == OP_REGOFFSET);
3341                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3342
3343                         for (quad = 0; quad < 2; quad ++) {
3344                                 switch (cinfo->ret.pair_storage [quad]) {
3345                                 case ArgInIReg:
3346                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3347                                         break;
3348                                 case ArgInFloatSSEReg:
3349                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3350                                         break;
3351                                 case ArgInDoubleSSEReg:
3352                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3353                                         break;
3354                                 case ArgNone:
3355                                         break;
3356                                 default:
3357                                         NOT_IMPLEMENTED;
3358                                 }
3359                         }
3360                 }
3361                 break;
3362         }
3363
3364         return code;
3365 }
3366
3367 #endif /* DISABLE_JIT */
3368
3369 #ifdef __APPLE__
3370 static int tls_gs_offset;
3371 #endif
3372
3373 gboolean
3374 mono_amd64_have_tls_get (void)
3375 {
3376 #ifdef TARGET_MACH
3377         static gboolean have_tls_get = FALSE;
3378         static gboolean inited = FALSE;
3379
3380         if (inited)
3381                 return have_tls_get;
3382
3383 #if MONO_HAVE_FAST_TLS
3384         guint8 *ins = (guint8*)pthread_getspecific;
3385
3386         /*
3387          * We're looking for these two instructions:
3388          *
3389          * mov    %gs:[offset](,%rdi,8),%rax
3390          * retq
3391          */
3392         have_tls_get = ins [0] == 0x65 &&
3393                        ins [1] == 0x48 &&
3394                        ins [2] == 0x8b &&
3395                        ins [3] == 0x04 &&
3396                        ins [4] == 0xfd &&
3397                        ins [6] == 0x00 &&
3398                        ins [7] == 0x00 &&
3399                        ins [8] == 0x00 &&
3400                        ins [9] == 0xc3;
3401
3402         tls_gs_offset = ins[5];
3403
3404         /*
3405          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3406          * For that version we're looking for these instructions:
3407          *
3408          * pushq  %rbp
3409          * movq   %rsp, %rbp
3410          * mov    %gs:[offset](,%rdi,8),%rax
3411          * popq   %rbp
3412          * retq
3413          */
3414         if (!have_tls_get) {
3415                 have_tls_get = ins [0] == 0x55 &&
3416                                ins [1] == 0x48 &&
3417                                ins [2] == 0x89 &&
3418                                ins [3] == 0xe5 &&
3419                                ins [4] == 0x65 &&
3420                                ins [5] == 0x48 &&
3421                                ins [6] == 0x8b &&
3422                                ins [7] == 0x04 &&
3423                                ins [8] == 0xfd &&
3424                                ins [10] == 0x00 &&
3425                                ins [11] == 0x00 &&
3426                                ins [12] == 0x00 &&
3427                                ins [13] == 0x5d &&
3428                                ins [14] == 0xc3;
3429
3430                 tls_gs_offset = ins[9];
3431         }
3432 #endif
3433
3434         inited = TRUE;
3435
3436         return have_tls_get;
3437 #elif defined(TARGET_ANDROID)
3438         return FALSE;
3439 #else
3440         return TRUE;
3441 #endif
3442 }
3443
3444 int
3445 mono_amd64_get_tls_gs_offset (void)
3446 {
3447 #ifdef TARGET_OSX
3448         return tls_gs_offset;
3449 #else
3450         g_assert_not_reached ();
3451         return -1;
3452 #endif
3453 }
3454
3455 /*
3456  * mono_amd64_emit_tls_get:
3457  * @code: buffer to store code to
3458  * @dreg: hard register where to place the result
3459  * @tls_offset: offset info
3460  *
3461  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3462  * the dreg register the item in the thread local storage identified
3463  * by tls_offset.
3464  *
3465  * Returns: a pointer to the end of the stored code
3466  */
3467 guint8*
3468 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3469 {
3470 #ifdef TARGET_WIN32
3471         if (tls_offset < 64) {
3472                 x86_prefix (code, X86_GS_PREFIX);
3473                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3474         } else {
3475                 guint8 *buf [16];
3476
3477                 g_assert (tls_offset < 0x440);
3478                 /* Load TEB->TlsExpansionSlots */
3479                 x86_prefix (code, X86_GS_PREFIX);
3480                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3481                 amd64_test_reg_reg (code, dreg, dreg);
3482                 buf [0] = code;
3483                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3484                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3485                 amd64_patch (buf [0], code);
3486         }
3487 #elif defined(__APPLE__)
3488         x86_prefix (code, X86_GS_PREFIX);
3489         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3490 #else
3491         if (optimize_for_xen) {
3492                 x86_prefix (code, X86_FS_PREFIX);
3493                 amd64_mov_reg_mem (code, dreg, 0, 8);
3494                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3495         } else {
3496                 x86_prefix (code, X86_FS_PREFIX);
3497                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3498         }
3499 #endif
3500         return code;
3501 }
3502
3503 #ifdef TARGET_WIN32
3504
3505 #define MAX_TEB_TLS_SLOTS 64
3506 #define TEB_TLS_SLOTS_OFFSET 0x1480
3507 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3508
3509 static guint8*
3510 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3511 {
3512         int tmp_reg = -1;
3513         guint8 * more_than_64_slots = NULL;
3514         guint8 * empty_slot = NULL;
3515         guint8 * tls_get_reg_done = NULL;
3516
3517         //Use temporary register for offset calculation?
3518         if (dreg == offset_reg) {
3519                 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3520                 amd64_push_reg (code, tmp_reg);
3521                 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3522                 offset_reg = tmp_reg;
3523         }
3524
3525         //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3526         amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3527         more_than_64_slots = code;
3528         amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3529
3530         //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3531         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3532         amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3533
3534         //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3535         x86_prefix (code, X86_GS_PREFIX);
3536         amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3537
3538         tls_get_reg_done = code;
3539         amd64_jump8 (code, 0);
3540
3541         amd64_patch (more_than_64_slots, code);
3542
3543         //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3544         x86_prefix (code, X86_GS_PREFIX);
3545         amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3546
3547         //Check for NULL in _TEB.TlsExpansionSlots.
3548         amd64_test_reg_reg (code, dreg, dreg);
3549         empty_slot = code;
3550         amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3551
3552         //TLS expansion slots are at index offset into the expansion array.
3553         //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3554         amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3555         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3556
3557         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3558
3559         amd64_patch (empty_slot, code);
3560         amd64_patch (tls_get_reg_done, code);
3561
3562         if (tmp_reg != -1)
3563                 amd64_pop_reg (code, tmp_reg);
3564
3565         return code;
3566 }
3567
3568 #endif
3569
3570 static guint8*
3571 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3572 {
3573         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3574 #ifdef TARGET_OSX
3575         if (dreg != offset_reg)
3576                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3577         amd64_prefix (code, X86_GS_PREFIX);
3578         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3579 #elif defined(__linux__)
3580         int tmpreg = -1;
3581
3582         if (dreg == offset_reg) {
3583                 /* Use a temporary reg by saving it to the redzone */
3584                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3585                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3586                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3587                 offset_reg = tmpreg;
3588         }
3589         x86_prefix (code, X86_FS_PREFIX);
3590         amd64_mov_reg_mem (code, dreg, 0, 8);
3591         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3592         if (tmpreg != -1)
3593                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3594 #elif defined(TARGET_WIN32)
3595         code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3596 #else
3597         g_assert_not_reached ();
3598 #endif
3599         return code;
3600 }
3601
3602 static guint8*
3603 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3604 {
3605 #ifdef TARGET_WIN32
3606         g_assert_not_reached ();
3607 #elif defined(__APPLE__)
3608         x86_prefix (code, X86_GS_PREFIX);
3609         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3610 #else
3611         g_assert (!optimize_for_xen);
3612         x86_prefix (code, X86_FS_PREFIX);
3613         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3614 #endif
3615         return code;
3616 }
3617
3618 static guint8*
3619 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3620 {
3621         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3622 #ifdef TARGET_WIN32
3623         g_assert_not_reached ();
3624 #elif defined(__APPLE__)
3625         x86_prefix (code, X86_GS_PREFIX);
3626         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3627 #else
3628         x86_prefix (code, X86_FS_PREFIX);
3629         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3630 #endif
3631         return code;
3632 }
3633
3634  /*
3635  * mono_arch_translate_tls_offset:
3636  *
3637  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3638  */
3639 int
3640 mono_arch_translate_tls_offset (int offset)
3641 {
3642 #ifdef __APPLE__
3643         return tls_gs_offset + (offset * 8);
3644 #else
3645         return offset;
3646 #endif
3647 }
3648
3649 /*
3650  * emit_setup_lmf:
3651  *
3652  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3653  */
3654 static guint8*
3655 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3656 {
3657         /*
3658          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3659          */
3660         /*
3661          * sp is saved right before calls but we need to save it here too so
3662          * async stack walks would work.
3663          */
3664         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3665         /* Save rbp */
3666         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3667         if (cfg->arch.omit_fp && cfa_offset != -1)
3668                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3669
3670         /* These can't contain refs */
3671         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3672         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3673         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3674         /* These are handled automatically by the stack marking code */
3675         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3676
3677         return code;
3678 }
3679
3680 /* benchmark and set based on cpu */
3681 #define LOOP_ALIGNMENT 8
3682 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3683
3684 #ifndef DISABLE_JIT
3685 void
3686 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3687 {
3688         MonoInst *ins;
3689         MonoCallInst *call;
3690         guint offset;
3691         guint8 *code = cfg->native_code + cfg->code_len;
3692         int max_len;
3693
3694         /* Fix max_offset estimate for each successor bb */
3695         if (cfg->opt & MONO_OPT_BRANCH) {
3696                 int current_offset = cfg->code_len;
3697                 MonoBasicBlock *current_bb;
3698                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3699                         current_bb->max_offset = current_offset;
3700                         current_offset += current_bb->max_length;
3701                 }
3702         }
3703
3704         if (cfg->opt & MONO_OPT_LOOP) {
3705                 int pad, align = LOOP_ALIGNMENT;
3706                 /* set alignment depending on cpu */
3707                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3708                         pad = align - pad;
3709                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3710                         amd64_padding (code, pad);
3711                         cfg->code_len += pad;
3712                         bb->native_offset = cfg->code_len;
3713                 }
3714         }
3715
3716         if (cfg->verbose_level > 2)
3717                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3718
3719         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3720                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3721                 g_assert (!cfg->compile_aot);
3722
3723                 cov->data [bb->dfn].cil_code = bb->cil_code;
3724                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3725                 /* this is not thread save, but good enough */
3726                 amd64_inc_membase (code, AMD64_R11, 0);
3727         }
3728
3729         offset = code - cfg->native_code;
3730
3731         mono_debug_open_block (cfg, bb, offset);
3732
3733     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3734                 x86_breakpoint (code);
3735
3736         MONO_BB_FOR_EACH_INS (bb, ins) {
3737                 offset = code - cfg->native_code;
3738
3739                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3740
3741 #define EXTRA_CODE_SPACE (16)
3742
3743                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3744                         cfg->code_size *= 2;
3745                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3746                         code = cfg->native_code + offset;
3747                         cfg->stat_code_reallocs++;
3748                 }
3749
3750                 if (cfg->debug_info)
3751                         mono_debug_record_line_number (cfg, ins, offset);
3752
3753                 switch (ins->opcode) {
3754                 case OP_BIGMUL:
3755                         amd64_mul_reg (code, ins->sreg2, TRUE);
3756                         break;
3757                 case OP_BIGMUL_UN:
3758                         amd64_mul_reg (code, ins->sreg2, FALSE);
3759                         break;
3760                 case OP_X86_SETEQ_MEMBASE:
3761                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3762                         break;
3763                 case OP_STOREI1_MEMBASE_IMM:
3764                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3765                         break;
3766                 case OP_STOREI2_MEMBASE_IMM:
3767                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3768                         break;
3769                 case OP_STOREI4_MEMBASE_IMM:
3770                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3771                         break;
3772                 case OP_STOREI1_MEMBASE_REG:
3773                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3774                         break;
3775                 case OP_STOREI2_MEMBASE_REG:
3776                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3777                         break;
3778                 /* In AMD64 NaCl, pointers are 4 bytes, */
3779                 /*  so STORE_* != STOREI8_*. Likewise below. */
3780                 case OP_STORE_MEMBASE_REG:
3781                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3782                         break;
3783                 case OP_STOREI8_MEMBASE_REG:
3784                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3785                         break;
3786                 case OP_STOREI4_MEMBASE_REG:
3787                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3788                         break;
3789                 case OP_STORE_MEMBASE_IMM:
3790                         /* In NaCl, this could be a PCONST type, which could */
3791                         /* mean a pointer type was copied directly into the  */
3792                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3793                         /* the value would be 0x00000000FFFFFFFF which is    */
3794                         /* not proper for an imm32 unless you cast it.       */
3795                         g_assert (amd64_is_imm32 (ins->inst_imm));
3796                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3797                         break;
3798                 case OP_STOREI8_MEMBASE_IMM:
3799                         g_assert (amd64_is_imm32 (ins->inst_imm));
3800                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3801                         break;
3802                 case OP_LOAD_MEM:
3803 #ifdef __mono_ilp32__
3804                         /* In ILP32, pointers are 4 bytes, so separate these */
3805                         /* cases, use literal 8 below where we really want 8 */
3806                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3807                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3808                         break;
3809 #endif
3810                 case OP_LOADI8_MEM:
3811                         // FIXME: Decompose this earlier
3812                         if (amd64_use_imm32 (ins->inst_imm))
3813                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3814                         else {
3815                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3816                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3817                         }
3818                         break;
3819                 case OP_LOADI4_MEM:
3820                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3821                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3822                         break;
3823                 case OP_LOADU4_MEM:
3824                         // FIXME: Decompose this earlier
3825                         if (amd64_use_imm32 (ins->inst_imm))
3826                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3827                         else {
3828                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3829                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3830                         }
3831                         break;
3832                 case OP_LOADU1_MEM:
3833                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3834                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3835                         break;
3836                 case OP_LOADU2_MEM:
3837                         /* For NaCl, pointers are 4 bytes, so separate these */
3838                         /* cases, use literal 8 below where we really want 8 */
3839                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3840                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3841                         break;
3842                 case OP_LOAD_MEMBASE:
3843                         g_assert (amd64_is_imm32 (ins->inst_offset));
3844                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3845                         break;
3846                 case OP_LOADI8_MEMBASE:
3847                         /* Use literal 8 instead of sizeof pointer or */
3848                         /* register, we really want 8 for this opcode */
3849                         g_assert (amd64_is_imm32 (ins->inst_offset));
3850                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3851                         break;
3852                 case OP_LOADI4_MEMBASE:
3853                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3854                         break;
3855                 case OP_LOADU4_MEMBASE:
3856                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3857                         break;
3858                 case OP_LOADU1_MEMBASE:
3859                         /* The cpu zero extends the result into 64 bits */
3860                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3861                         break;
3862                 case OP_LOADI1_MEMBASE:
3863                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3864                         break;
3865                 case OP_LOADU2_MEMBASE:
3866                         /* The cpu zero extends the result into 64 bits */
3867                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3868                         break;
3869                 case OP_LOADI2_MEMBASE:
3870                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3871                         break;
3872                 case OP_AMD64_LOADI8_MEMINDEX:
3873                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3874                         break;
3875                 case OP_LCONV_TO_I1:
3876                 case OP_ICONV_TO_I1:
3877                 case OP_SEXT_I1:
3878                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3879                         break;
3880                 case OP_LCONV_TO_I2:
3881                 case OP_ICONV_TO_I2:
3882                 case OP_SEXT_I2:
3883                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3884                         break;
3885                 case OP_LCONV_TO_U1:
3886                 case OP_ICONV_TO_U1:
3887                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3888                         break;
3889                 case OP_LCONV_TO_U2:
3890                 case OP_ICONV_TO_U2:
3891                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3892                         break;
3893                 case OP_ZEXT_I4:
3894                         /* Clean out the upper word */
3895                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3896                         break;
3897                 case OP_SEXT_I4:
3898                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3899                         break;
3900                 case OP_COMPARE:
3901                 case OP_LCOMPARE:
3902                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3903                         break;
3904                 case OP_COMPARE_IMM:
3905 #if defined(__mono_ilp32__)
3906                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3907                         g_assert (amd64_is_imm32 (ins->inst_imm));
3908                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3909                         break;
3910 #endif
3911                 case OP_LCOMPARE_IMM:
3912                         g_assert (amd64_is_imm32 (ins->inst_imm));
3913                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3914                         break;
3915                 case OP_X86_COMPARE_REG_MEMBASE:
3916                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3917                         break;
3918                 case OP_X86_TEST_NULL:
3919                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3920                         break;
3921                 case OP_AMD64_TEST_NULL:
3922                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3923                         break;
3924
3925                 case OP_X86_ADD_REG_MEMBASE:
3926                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3927                         break;
3928                 case OP_X86_SUB_REG_MEMBASE:
3929                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3930                         break;
3931                 case OP_X86_AND_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3933                         break;
3934                 case OP_X86_OR_REG_MEMBASE:
3935                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3936                         break;
3937                 case OP_X86_XOR_REG_MEMBASE:
3938                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3939                         break;
3940
3941                 case OP_X86_ADD_MEMBASE_IMM:
3942                         /* FIXME: Make a 64 version too */
3943                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3944                         break;
3945                 case OP_X86_SUB_MEMBASE_IMM:
3946                         g_assert (amd64_is_imm32 (ins->inst_imm));
3947                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3948                         break;
3949                 case OP_X86_AND_MEMBASE_IMM:
3950                         g_assert (amd64_is_imm32 (ins->inst_imm));
3951                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3952                         break;
3953                 case OP_X86_OR_MEMBASE_IMM:
3954                         g_assert (amd64_is_imm32 (ins->inst_imm));
3955                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3956                         break;
3957                 case OP_X86_XOR_MEMBASE_IMM:
3958                         g_assert (amd64_is_imm32 (ins->inst_imm));
3959                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3960                         break;
3961                 case OP_X86_ADD_MEMBASE_REG:
3962                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3963                         break;
3964                 case OP_X86_SUB_MEMBASE_REG:
3965                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3966                         break;
3967                 case OP_X86_AND_MEMBASE_REG:
3968                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3969                         break;
3970                 case OP_X86_OR_MEMBASE_REG:
3971                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3972                         break;
3973                 case OP_X86_XOR_MEMBASE_REG:
3974                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3975                         break;
3976                 case OP_X86_INC_MEMBASE:
3977                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3978                         break;
3979                 case OP_X86_INC_REG:
3980                         amd64_inc_reg_size (code, ins->dreg, 4);
3981                         break;
3982                 case OP_X86_DEC_MEMBASE:
3983                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3984                         break;
3985                 case OP_X86_DEC_REG:
3986                         amd64_dec_reg_size (code, ins->dreg, 4);
3987                         break;
3988                 case OP_X86_MUL_REG_MEMBASE:
3989                 case OP_X86_MUL_MEMBASE_REG:
3990                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3991                         break;
3992                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3993                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3994                         break;
3995                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3996                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3997                         break;
3998                 case OP_AMD64_COMPARE_MEMBASE_REG:
3999                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4000                         break;
4001                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4002                         g_assert (amd64_is_imm32 (ins->inst_imm));
4003                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4004                         break;
4005                 case OP_X86_COMPARE_MEMBASE8_IMM:
4006                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4007                         break;
4008                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4009                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4010                         break;
4011                 case OP_AMD64_COMPARE_REG_MEMBASE:
4012                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4013                         break;
4014
4015                 case OP_AMD64_ADD_REG_MEMBASE:
4016                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4017                         break;
4018                 case OP_AMD64_SUB_REG_MEMBASE:
4019                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4020                         break;
4021                 case OP_AMD64_AND_REG_MEMBASE:
4022                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4023                         break;
4024                 case OP_AMD64_OR_REG_MEMBASE:
4025                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4026                         break;
4027                 case OP_AMD64_XOR_REG_MEMBASE:
4028                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4029                         break;
4030
4031                 case OP_AMD64_ADD_MEMBASE_REG:
4032                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4033                         break;
4034                 case OP_AMD64_SUB_MEMBASE_REG:
4035                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4036                         break;
4037                 case OP_AMD64_AND_MEMBASE_REG:
4038                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4039                         break;
4040                 case OP_AMD64_OR_MEMBASE_REG:
4041                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4042                         break;
4043                 case OP_AMD64_XOR_MEMBASE_REG:
4044                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4045                         break;
4046
4047                 case OP_AMD64_ADD_MEMBASE_IMM:
4048                         g_assert (amd64_is_imm32 (ins->inst_imm));
4049                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4050                         break;
4051                 case OP_AMD64_SUB_MEMBASE_IMM:
4052                         g_assert (amd64_is_imm32 (ins->inst_imm));
4053                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4054                         break;
4055                 case OP_AMD64_AND_MEMBASE_IMM:
4056                         g_assert (amd64_is_imm32 (ins->inst_imm));
4057                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4058                         break;
4059                 case OP_AMD64_OR_MEMBASE_IMM:
4060                         g_assert (amd64_is_imm32 (ins->inst_imm));
4061                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4062                         break;
4063                 case OP_AMD64_XOR_MEMBASE_IMM:
4064                         g_assert (amd64_is_imm32 (ins->inst_imm));
4065                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4066                         break;
4067
4068                 case OP_BREAK:
4069                         amd64_breakpoint (code);
4070                         break;
4071                 case OP_RELAXED_NOP:
4072                         x86_prefix (code, X86_REP_PREFIX);
4073                         x86_nop (code);
4074                         break;
4075                 case OP_HARD_NOP:
4076                         x86_nop (code);
4077                         break;
4078                 case OP_NOP:
4079                 case OP_DUMMY_USE:
4080                 case OP_DUMMY_STORE:
4081                 case OP_DUMMY_ICONST:
4082                 case OP_DUMMY_R8CONST:
4083                 case OP_NOT_REACHED:
4084                 case OP_NOT_NULL:
4085                         break;
4086                 case OP_IL_SEQ_POINT:
4087                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4088                         break;
4089                 case OP_SEQ_POINT: {
4090                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4091                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4092                                 guint8 *label;
4093
4094                                 /* Load ss_tramp_var */
4095                                 /* This is equal to &ss_trampoline */
4096                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4097                                 /* Load the trampoline address */
4098                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4099                                 /* Call it if it is non-null */
4100                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4101                                 label = code;
4102                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4103                                 amd64_call_reg (code, AMD64_R11);
4104                                 amd64_patch (label, code);
4105                         }
4106
4107                         /*
4108                          * This is the address which is saved in seq points,
4109                          */
4110                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4111
4112                         if (cfg->compile_aot) {
4113                                 guint32 offset = code - cfg->native_code;
4114                                 guint32 val;
4115                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4116                                 guint8 *label;
4117
4118                                 /* Load info var */
4119                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4120                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4121                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4122                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4123                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4124                                 label = code;
4125                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4126                                 /* Call the trampoline */
4127                                 amd64_call_reg (code, AMD64_R11);
4128                                 amd64_patch (label, code);
4129                         } else {
4130                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4131                                 guint8 *label;
4132
4133                                 /*
4134                                  * Emit a test+branch against a constant, the constant will be overwritten
4135                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4136                                  */
4137                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4138                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4139                                 label = code;
4140                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4141
4142                                 g_assert (var);
4143                                 g_assert (var->opcode == OP_REGOFFSET);
4144                                 /* Load bp_tramp_var */
4145                                 /* This is equal to &bp_trampoline */
4146                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4147                                 /* Call the trampoline */
4148                                 amd64_call_membase (code, AMD64_R11, 0);
4149                                 amd64_patch (label, code);
4150                         }
4151                         /*
4152                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4153                          * to another IL offset.
4154                          */
4155                         x86_nop (code);
4156                         break;
4157                 }
4158                 case OP_ADDCC:
4159                 case OP_LADDCC:
4160                 case OP_LADD:
4161                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4162                         break;
4163                 case OP_ADC:
4164                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4165                         break;
4166                 case OP_ADD_IMM:
4167                 case OP_LADD_IMM:
4168                         g_assert (amd64_is_imm32 (ins->inst_imm));
4169                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4170                         break;
4171                 case OP_ADC_IMM:
4172                         g_assert (amd64_is_imm32 (ins->inst_imm));
4173                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4174                         break;
4175                 case OP_SUBCC:
4176                 case OP_LSUBCC:
4177                 case OP_LSUB:
4178                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4179                         break;
4180                 case OP_SBB:
4181                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4182                         break;
4183                 case OP_SUB_IMM:
4184                 case OP_LSUB_IMM:
4185                         g_assert (amd64_is_imm32 (ins->inst_imm));
4186                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4187                         break;
4188                 case OP_SBB_IMM:
4189                         g_assert (amd64_is_imm32 (ins->inst_imm));
4190                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4191                         break;
4192                 case OP_LAND:
4193                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4194                         break;
4195                 case OP_AND_IMM:
4196                 case OP_LAND_IMM:
4197                         g_assert (amd64_is_imm32 (ins->inst_imm));
4198                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4199                         break;
4200                 case OP_LMUL:
4201                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4202                         break;
4203                 case OP_MUL_IMM:
4204                 case OP_LMUL_IMM:
4205                 case OP_IMUL_IMM: {
4206                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4207
4208                         switch (ins->inst_imm) {
4209                         case 2:
4210                                 /* MOV r1, r2 */
4211                                 /* ADD r1, r1 */
4212                                 if (ins->dreg != ins->sreg1)
4213                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4214                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4215                                 break;
4216                         case 3:
4217                                 /* LEA r1, [r2 + r2*2] */
4218                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4219                                 break;
4220                         case 5:
4221                                 /* LEA r1, [r2 + r2*4] */
4222                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4223                                 break;
4224                         case 6:
4225                                 /* LEA r1, [r2 + r2*2] */
4226                                 /* ADD r1, r1          */
4227                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4228                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4229                                 break;
4230                         case 9:
4231                                 /* LEA r1, [r2 + r2*8] */
4232                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4233                                 break;
4234                         case 10:
4235                                 /* LEA r1, [r2 + r2*4] */
4236                                 /* ADD r1, r1          */
4237                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4238                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4239                                 break;
4240                         case 12:
4241                                 /* LEA r1, [r2 + r2*2] */
4242                                 /* SHL r1, 2           */
4243                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4244                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4245                                 break;
4246                         case 25:
4247                                 /* LEA r1, [r2 + r2*4] */
4248                                 /* LEA r1, [r1 + r1*4] */
4249                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4250                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4251                                 break;
4252                         case 100:
4253                                 /* LEA r1, [r2 + r2*4] */
4254                                 /* SHL r1, 2           */
4255                                 /* LEA r1, [r1 + r1*4] */
4256                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4257                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4258                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4259                                 break;
4260                         default:
4261                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4262                                 break;
4263                         }
4264                         break;
4265                 }
4266                 case OP_LDIV:
4267                 case OP_LREM:
4268                         /* Regalloc magic makes the div/rem cases the same */
4269                         if (ins->sreg2 == AMD64_RDX) {
4270                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4271                                 amd64_cdq (code);
4272                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4273                         } else {
4274                                 amd64_cdq (code);
4275                                 amd64_div_reg (code, ins->sreg2, TRUE);
4276                         }
4277                         break;
4278                 case OP_LDIV_UN:
4279                 case OP_LREM_UN:
4280                         if (ins->sreg2 == AMD64_RDX) {
4281                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4282                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4283                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4284                         } else {
4285                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4286                                 amd64_div_reg (code, ins->sreg2, FALSE);
4287                         }
4288                         break;
4289                 case OP_IDIV:
4290                 case OP_IREM:
4291                         if (ins->sreg2 == AMD64_RDX) {
4292                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4293                                 amd64_cdq_size (code, 4);
4294                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4295                         } else {
4296                                 amd64_cdq_size (code, 4);
4297                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4298                         }
4299                         break;
4300                 case OP_IDIV_UN:
4301                 case OP_IREM_UN:
4302                         if (ins->sreg2 == AMD64_RDX) {
4303                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4304                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4305                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4306                         } else {
4307                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4308                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4309                         }
4310                         break;
4311                 case OP_LMUL_OVF:
4312                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4313                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4314                         break;
4315                 case OP_LOR:
4316                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4317                         break;
4318                 case OP_OR_IMM:
4319                 case OP_LOR_IMM:
4320                         g_assert (amd64_is_imm32 (ins->inst_imm));
4321                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4322                         break;
4323                 case OP_LXOR:
4324                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4325                         break;
4326                 case OP_XOR_IMM:
4327                 case OP_LXOR_IMM:
4328                         g_assert (amd64_is_imm32 (ins->inst_imm));
4329                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4330                         break;
4331                 case OP_LSHL:
4332                         g_assert (ins->sreg2 == AMD64_RCX);
4333                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4334                         break;
4335                 case OP_LSHR:
4336                         g_assert (ins->sreg2 == AMD64_RCX);
4337                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4338                         break;
4339                 case OP_SHR_IMM:
4340                 case OP_LSHR_IMM:
4341                         g_assert (amd64_is_imm32 (ins->inst_imm));
4342                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4343                         break;
4344                 case OP_SHR_UN_IMM:
4345                         g_assert (amd64_is_imm32 (ins->inst_imm));
4346                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4347                         break;
4348                 case OP_LSHR_UN_IMM:
4349                         g_assert (amd64_is_imm32 (ins->inst_imm));
4350                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4351                         break;
4352                 case OP_LSHR_UN:
4353                         g_assert (ins->sreg2 == AMD64_RCX);
4354                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4355                         break;
4356                 case OP_SHL_IMM:
4357                 case OP_LSHL_IMM:
4358                         g_assert (amd64_is_imm32 (ins->inst_imm));
4359                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4360                         break;
4361
4362                 case OP_IADDCC:
4363                 case OP_IADD:
4364                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4365                         break;
4366                 case OP_IADC:
4367                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4368                         break;
4369                 case OP_IADD_IMM:
4370                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4371                         break;
4372                 case OP_IADC_IMM:
4373                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4374                         break;
4375                 case OP_ISUBCC:
4376                 case OP_ISUB:
4377                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4378                         break;
4379                 case OP_ISBB:
4380                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4381                         break;
4382                 case OP_ISUB_IMM:
4383                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4384                         break;
4385                 case OP_ISBB_IMM:
4386                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4387                         break;
4388                 case OP_IAND:
4389                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4390                         break;
4391                 case OP_IAND_IMM:
4392                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4393                         break;
4394                 case OP_IOR:
4395                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4396                         break;
4397                 case OP_IOR_IMM:
4398                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4399                         break;
4400                 case OP_IXOR:
4401                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4402                         break;
4403                 case OP_IXOR_IMM:
4404                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4405                         break;
4406                 case OP_INEG:
4407                         amd64_neg_reg_size (code, ins->sreg1, 4);
4408                         break;
4409                 case OP_INOT:
4410                         amd64_not_reg_size (code, ins->sreg1, 4);
4411                         break;
4412                 case OP_ISHL:
4413                         g_assert (ins->sreg2 == AMD64_RCX);
4414                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4415                         break;
4416                 case OP_ISHR:
4417                         g_assert (ins->sreg2 == AMD64_RCX);
4418                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4419                         break;
4420                 case OP_ISHR_IMM:
4421                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4422                         break;
4423                 case OP_ISHR_UN_IMM:
4424                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4425                         break;
4426                 case OP_ISHR_UN:
4427                         g_assert (ins->sreg2 == AMD64_RCX);
4428                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4429                         break;
4430                 case OP_ISHL_IMM:
4431                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4432                         break;
4433                 case OP_IMUL:
4434                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4435                         break;
4436                 case OP_IMUL_OVF:
4437                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4438                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4439                         break;
4440                 case OP_IMUL_OVF_UN:
4441                 case OP_LMUL_OVF_UN: {
4442                         /* the mul operation and the exception check should most likely be split */
4443                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4444                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4445                         /*g_assert (ins->sreg2 == X86_EAX);
4446                         g_assert (ins->dreg == X86_EAX);*/
4447                         if (ins->sreg2 == X86_EAX) {
4448                                 non_eax_reg = ins->sreg1;
4449                         } else if (ins->sreg1 == X86_EAX) {
4450                                 non_eax_reg = ins->sreg2;
4451                         } else {
4452                                 /* no need to save since we're going to store to it anyway */
4453                                 if (ins->dreg != X86_EAX) {
4454                                         saved_eax = TRUE;
4455                                         amd64_push_reg (code, X86_EAX);
4456                                 }
4457                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4458                                 non_eax_reg = ins->sreg2;
4459                         }
4460                         if (ins->dreg == X86_EDX) {
4461                                 if (!saved_eax) {
4462                                         saved_eax = TRUE;
4463                                         amd64_push_reg (code, X86_EAX);
4464                                 }
4465                         } else {
4466                                 saved_edx = TRUE;
4467                                 amd64_push_reg (code, X86_EDX);
4468                         }
4469                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4470                         /* save before the check since pop and mov don't change the flags */
4471                         if (ins->dreg != X86_EAX)
4472                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4473                         if (saved_edx)
4474                                 amd64_pop_reg (code, X86_EDX);
4475                         if (saved_eax)
4476                                 amd64_pop_reg (code, X86_EAX);
4477                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4478                         break;
4479                 }
4480                 case OP_ICOMPARE:
4481                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4482                         break;
4483                 case OP_ICOMPARE_IMM:
4484                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4485                         break;
4486                 case OP_IBEQ:
4487                 case OP_IBLT:
4488                 case OP_IBGT:
4489                 case OP_IBGE:
4490                 case OP_IBLE:
4491                 case OP_LBEQ:
4492                 case OP_LBLT:
4493                 case OP_LBGT:
4494                 case OP_LBGE:
4495                 case OP_LBLE:
4496                 case OP_IBNE_UN:
4497                 case OP_IBLT_UN:
4498                 case OP_IBGT_UN:
4499                 case OP_IBGE_UN:
4500                 case OP_IBLE_UN:
4501                 case OP_LBNE_UN:
4502                 case OP_LBLT_UN:
4503                 case OP_LBGT_UN:
4504                 case OP_LBGE_UN:
4505                 case OP_LBLE_UN:
4506                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4507                         break;
4508
4509                 case OP_CMOV_IEQ:
4510                 case OP_CMOV_IGE:
4511                 case OP_CMOV_IGT:
4512                 case OP_CMOV_ILE:
4513                 case OP_CMOV_ILT:
4514                 case OP_CMOV_INE_UN:
4515                 case OP_CMOV_IGE_UN:
4516                 case OP_CMOV_IGT_UN:
4517                 case OP_CMOV_ILE_UN:
4518                 case OP_CMOV_ILT_UN:
4519                 case OP_CMOV_LEQ:
4520                 case OP_CMOV_LGE:
4521                 case OP_CMOV_LGT:
4522                 case OP_CMOV_LLE:
4523                 case OP_CMOV_LLT:
4524                 case OP_CMOV_LNE_UN:
4525                 case OP_CMOV_LGE_UN:
4526                 case OP_CMOV_LGT_UN:
4527                 case OP_CMOV_LLE_UN:
4528                 case OP_CMOV_LLT_UN:
4529                         g_assert (ins->dreg == ins->sreg1);
4530                         /* This needs to operate on 64 bit values */
4531                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4532                         break;
4533
4534                 case OP_LNOT:
4535                         amd64_not_reg (code, ins->sreg1);
4536                         break;
4537                 case OP_LNEG:
4538                         amd64_neg_reg (code, ins->sreg1);
4539                         break;
4540
4541                 case OP_ICONST:
4542                 case OP_I8CONST:
4543                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4544                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4545                         else
4546                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4547                         break;
4548                 case OP_AOTCONST:
4549                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4550                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4551                         break;
4552                 case OP_JUMP_TABLE:
4553                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4554                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4555                         break;
4556                 case OP_MOVE:
4557                         if (ins->dreg != ins->sreg1)
4558                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4559                         break;
4560                 case OP_AMD64_SET_XMMREG_R4: {
4561                         if (cfg->r4fp) {
4562                                 if (ins->dreg != ins->sreg1)
4563                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4564                         } else {
4565                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4566                         }
4567                         break;
4568                 }
4569                 case OP_AMD64_SET_XMMREG_R8: {
4570                         if (ins->dreg != ins->sreg1)
4571                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4572                         break;
4573                 }
4574                 case OP_TAILCALL: {
4575                         MonoCallInst *call = (MonoCallInst*)ins;
4576                         int i, save_area_offset;
4577
4578                         g_assert (!cfg->method->save_lmf);
4579
4580                         /* Restore callee saved registers */
4581                         save_area_offset = cfg->arch.reg_save_area_offset;
4582                         for (i = 0; i < AMD64_NREG; ++i)
4583                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4584                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4585                                         save_area_offset += 8;
4586                                 }
4587
4588                         if (cfg->arch.omit_fp) {
4589                                 if (cfg->arch.stack_alloc_size)
4590                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4591                                 // FIXME:
4592                                 if (call->stack_usage)
4593                                         NOT_IMPLEMENTED;
4594                         } else {
4595                                 /* Copy arguments on the stack to our argument area */
4596                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4597                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4598                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4599                                 }
4600
4601                                 amd64_leave (code);
4602                         }
4603
4604                         offset = code - cfg->native_code;
4605                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4606                         if (cfg->compile_aot)
4607                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4608                         else
4609                                 amd64_set_reg_template (code, AMD64_R11);
4610                         amd64_jump_reg (code, AMD64_R11);
4611                         ins->flags |= MONO_INST_GC_CALLSITE;
4612                         ins->backend.pc_offset = code - cfg->native_code;
4613                         break;
4614                 }
4615                 case OP_CHECK_THIS:
4616                         /* ensure ins->sreg1 is not NULL */
4617                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4618                         break;
4619                 case OP_ARGLIST: {
4620                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4621                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4622                         break;
4623                 }
4624                 case OP_CALL:
4625                 case OP_FCALL:
4626                 case OP_RCALL:
4627                 case OP_LCALL:
4628                 case OP_VCALL:
4629                 case OP_VCALL2:
4630                 case OP_VOIDCALL:
4631                         call = (MonoCallInst*)ins;
4632                         /*
4633                          * The AMD64 ABI forces callers to know about varargs.
4634                          */
4635                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4636                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4637                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4638                                 /*
4639                                  * Since the unmanaged calling convention doesn't contain a
4640                                  * 'vararg' entry, we have to treat every pinvoke call as a
4641                                  * potential vararg call.
4642                                  */
4643                                 guint32 nregs, i;
4644                                 nregs = 0;
4645                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4646                                         if (call->used_fregs & (1 << i))
4647                                                 nregs ++;
4648                                 if (!nregs)
4649                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4650                                 else
4651                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4652                         }
4653
4654                         if (ins->flags & MONO_INST_HAS_METHOD)
4655                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4656                         else
4657                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4658                         ins->flags |= MONO_INST_GC_CALLSITE;
4659                         ins->backend.pc_offset = code - cfg->native_code;
4660                         code = emit_move_return_value (cfg, ins, code);
4661                         break;
4662                 case OP_FCALL_REG:
4663                 case OP_RCALL_REG:
4664                 case OP_LCALL_REG:
4665                 case OP_VCALL_REG:
4666                 case OP_VCALL2_REG:
4667                 case OP_VOIDCALL_REG:
4668                 case OP_CALL_REG:
4669                         call = (MonoCallInst*)ins;
4670
4671                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4672                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4673                                 ins->sreg1 = AMD64_R11;
4674                         }
4675
4676                         /*
4677                          * The AMD64 ABI forces callers to know about varargs.
4678                          */
4679                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4680                                 if (ins->sreg1 == AMD64_RAX) {
4681                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4682                                         ins->sreg1 = AMD64_R11;
4683                                 }
4684                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4685                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4686                                 /*
4687                                  * Since the unmanaged calling convention doesn't contain a
4688                                  * 'vararg' entry, we have to treat every pinvoke call as a
4689                                  * potential vararg call.
4690                                  */
4691                                 guint32 nregs, i;
4692                                 nregs = 0;
4693                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4694                                         if (call->used_fregs & (1 << i))
4695                                                 nregs ++;
4696                                 if (ins->sreg1 == AMD64_RAX) {
4697                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4698                                         ins->sreg1 = AMD64_R11;
4699                                 }
4700                                 if (!nregs)
4701                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4702                                 else
4703                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4704                         }
4705
4706                         amd64_call_reg (code, ins->sreg1);
4707                         ins->flags |= MONO_INST_GC_CALLSITE;
4708                         ins->backend.pc_offset = code - cfg->native_code;
4709                         code = emit_move_return_value (cfg, ins, code);
4710                         break;
4711                 case OP_FCALL_MEMBASE:
4712                 case OP_RCALL_MEMBASE:
4713                 case OP_LCALL_MEMBASE:
4714                 case OP_VCALL_MEMBASE:
4715                 case OP_VCALL2_MEMBASE:
4716                 case OP_VOIDCALL_MEMBASE:
4717                 case OP_CALL_MEMBASE:
4718                         call = (MonoCallInst*)ins;
4719
4720                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4721                         ins->flags |= MONO_INST_GC_CALLSITE;
4722                         ins->backend.pc_offset = code - cfg->native_code;
4723                         code = emit_move_return_value (cfg, ins, code);
4724                         break;
4725                 case OP_DYN_CALL: {
4726                         int i;
4727                         MonoInst *var = cfg->dyn_call_var;
4728                         guint8 *label;
4729
4730                         g_assert (var->opcode == OP_REGOFFSET);
4731
4732                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4733                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4734                         /* r10 = ftn */
4735                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4736
4737                         /* Save args buffer */
4738                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4739
4740                         /* Set fp arg regs */
4741                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4742                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4743                         label = code;
4744                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4745                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4746                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4747                         amd64_patch (label, code);
4748
4749                         /* Set stack args */
4750                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4751                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4752                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4753                         }
4754
4755                         /* Set argument registers */
4756                         for (i = 0; i < PARAM_REGS; ++i)
4757                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4758
4759                         /* Make the call */
4760                         amd64_call_reg (code, AMD64_R10);
4761
4762                         ins->flags |= MONO_INST_GC_CALLSITE;
4763                         ins->backend.pc_offset = code - cfg->native_code;
4764
4765                         /* Save result */
4766                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4767                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4768                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4769                         break;
4770                 }
4771                 case OP_AMD64_SAVE_SP_TO_LMF: {
4772                         MonoInst *lmf_var = cfg->lmf_var;
4773                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4774                         break;
4775                 }
4776                 case OP_X86_PUSH:
4777                         g_assert_not_reached ();
4778                         amd64_push_reg (code, ins->sreg1);
4779                         break;
4780                 case OP_X86_PUSH_IMM:
4781                         g_assert_not_reached ();
4782                         g_assert (amd64_is_imm32 (ins->inst_imm));
4783                         amd64_push_imm (code, ins->inst_imm);
4784                         break;
4785                 case OP_X86_PUSH_MEMBASE:
4786                         g_assert_not_reached ();
4787                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4788                         break;
4789                 case OP_X86_PUSH_OBJ: {
4790                         int size = ALIGN_TO (ins->inst_imm, 8);
4791
4792                         g_assert_not_reached ();
4793
4794                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4795                         amd64_push_reg (code, AMD64_RDI);
4796                         amd64_push_reg (code, AMD64_RSI);
4797                         amd64_push_reg (code, AMD64_RCX);
4798                         if (ins->inst_offset)
4799                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4800                         else
4801                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4802                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4803                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4804                         amd64_cld (code);
4805                         amd64_prefix (code, X86_REP_PREFIX);
4806                         amd64_movsd (code);
4807                         amd64_pop_reg (code, AMD64_RCX);
4808                         amd64_pop_reg (code, AMD64_RSI);
4809                         amd64_pop_reg (code, AMD64_RDI);
4810                         break;
4811                 }
4812                 case OP_GENERIC_CLASS_INIT: {
4813                         static int byte_offset = -1;
4814                         static guint8 bitmask;
4815                         guint8 *jump;
4816
4817                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4818
4819                         if (byte_offset < 0)
4820                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4821
4822                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4823                         jump = code;
4824                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4825
4826                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4827                         ins->flags |= MONO_INST_GC_CALLSITE;
4828                         ins->backend.pc_offset = code - cfg->native_code;
4829
4830                         x86_patch (jump, code);
4831                         break;
4832                 }
4833
4834                 case OP_X86_LEA:
4835                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4836                         break;
4837                 case OP_X86_LEA_MEMBASE:
4838                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4839                         break;
4840                 case OP_X86_XCHG:
4841                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4842                         break;
4843                 case OP_LOCALLOC:
4844                         /* keep alignment */
4845                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4846                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4847                         code = mono_emit_stack_alloc (cfg, code, ins);
4848                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4849                         if (cfg->param_area)
4850                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4851                         break;
4852                 case OP_LOCALLOC_IMM: {
4853                         guint32 size = ins->inst_imm;
4854                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4855
4856                         if (ins->flags & MONO_INST_INIT) {
4857                                 if (size < 64) {
4858                                         int i;
4859
4860                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4861                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4862
4863                                         for (i = 0; i < size; i += 8)
4864                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4865                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4866                                 } else {
4867                                         amd64_mov_reg_imm (code, ins->dreg, size);
4868                                         ins->sreg1 = ins->dreg;
4869
4870                                         code = mono_emit_stack_alloc (cfg, code, ins);
4871                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4872                                 }
4873                         } else {
4874                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4875                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4876                         }
4877                         if (cfg->param_area)
4878                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4879                         break;
4880                 }
4881                 case OP_THROW: {
4882                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4883                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4884                                              (gpointer)"mono_arch_throw_exception", FALSE);
4885                         ins->flags |= MONO_INST_GC_CALLSITE;
4886                         ins->backend.pc_offset = code - cfg->native_code;
4887                         break;
4888                 }
4889                 case OP_RETHROW: {
4890                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4891                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4892                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4893                         ins->flags |= MONO_INST_GC_CALLSITE;
4894                         ins->backend.pc_offset = code - cfg->native_code;
4895                         break;
4896                 }
4897                 case OP_CALL_HANDLER:
4898                         /* Align stack */
4899                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4900                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4901                         amd64_call_imm (code, 0);
4902                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4903                         /* Restore stack alignment */
4904                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4905                         break;
4906                 case OP_START_HANDLER: {
4907                         /* Even though we're saving RSP, use sizeof */
4908                         /* gpointer because spvar is of type IntPtr */
4909                         /* see: mono_create_spvar_for_region */
4910                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4911                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4912
4913                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4914                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4915                                 cfg->param_area) {
4916                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4917                         }
4918                         break;
4919                 }
4920                 case OP_ENDFINALLY: {
4921                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4922                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4923                         amd64_ret (code);
4924                         break;
4925                 }
4926                 case OP_ENDFILTER: {
4927                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4928                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4929                         /* The local allocator will put the result into RAX */
4930                         amd64_ret (code);
4931                         break;
4932                 }
4933                 case OP_GET_EX_OBJ:
4934                         if (ins->dreg != AMD64_RAX)
4935                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4936                         break;
4937                 case OP_LABEL:
4938                         ins->inst_c0 = code - cfg->native_code;
4939                         break;
4940                 case OP_BR:
4941                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4942                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4943                         //break;
4944                                 if (ins->inst_target_bb->native_offset) {
4945                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4946                                 } else {
4947                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4948                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4949                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4950                                                 x86_jump8 (code, 0);
4951                                         else
4952                                                 x86_jump32 (code, 0);
4953                         }
4954                         break;
4955                 case OP_BR_REG:
4956                         amd64_jump_reg (code, ins->sreg1);
4957                         break;
4958                 case OP_ICNEQ:
4959                 case OP_ICGE:
4960                 case OP_ICLE:
4961                 case OP_ICGE_UN:
4962                 case OP_ICLE_UN:
4963
4964                 case OP_CEQ:
4965                 case OP_LCEQ:
4966                 case OP_ICEQ:
4967                 case OP_CLT:
4968                 case OP_LCLT:
4969                 case OP_ICLT:
4970                 case OP_CGT:
4971                 case OP_ICGT:
4972                 case OP_LCGT:
4973                 case OP_CLT_UN:
4974                 case OP_LCLT_UN:
4975                 case OP_ICLT_UN:
4976                 case OP_CGT_UN:
4977                 case OP_LCGT_UN:
4978                 case OP_ICGT_UN:
4979                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4980                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4981                         break;
4982                 case OP_COND_EXC_EQ:
4983                 case OP_COND_EXC_NE_UN:
4984                 case OP_COND_EXC_LT:
4985                 case OP_COND_EXC_LT_UN:
4986                 case OP_COND_EXC_GT:
4987                 case OP_COND_EXC_GT_UN:
4988                 case OP_COND_EXC_GE:
4989                 case OP_COND_EXC_GE_UN:
4990                 case OP_COND_EXC_LE:
4991                 case OP_COND_EXC_LE_UN:
4992                 case OP_COND_EXC_IEQ:
4993                 case OP_COND_EXC_INE_UN:
4994                 case OP_COND_EXC_ILT:
4995                 case OP_COND_EXC_ILT_UN:
4996                 case OP_COND_EXC_IGT:
4997                 case OP_COND_EXC_IGT_UN:
4998                 case OP_COND_EXC_IGE:
4999                 case OP_COND_EXC_IGE_UN:
5000                 case OP_COND_EXC_ILE:
5001                 case OP_COND_EXC_ILE_UN:
5002                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5003                         break;
5004                 case OP_COND_EXC_OV:
5005                 case OP_COND_EXC_NO:
5006                 case OP_COND_EXC_C:
5007                 case OP_COND_EXC_NC:
5008                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5009                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5010                         break;
5011                 case OP_COND_EXC_IOV:
5012                 case OP_COND_EXC_INO:
5013                 case OP_COND_EXC_IC:
5014                 case OP_COND_EXC_INC:
5015                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5016                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5017                         break;
5018
5019                 /* floating point opcodes */
5020                 case OP_R8CONST: {
5021                         double d = *(double *)ins->inst_p0;
5022
5023                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5024                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5025                         }
5026                         else {
5027                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5028                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5029                         }
5030                         break;
5031                 }
5032                 case OP_R4CONST: {
5033                         float f = *(float *)ins->inst_p0;
5034
5035                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5036                                 if (cfg->r4fp)
5037                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5038                                 else
5039                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5040                         }
5041                         else {
5042                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5043                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5044                                 if (!cfg->r4fp)
5045                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5046                         }
5047                         break;
5048                 }
5049                 case OP_STORER8_MEMBASE_REG:
5050                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5051                         break;
5052                 case OP_LOADR8_MEMBASE:
5053                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5054                         break;
5055                 case OP_STORER4_MEMBASE_REG:
5056                         if (cfg->r4fp) {
5057                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5058                         } else {
5059                                 /* This requires a double->single conversion */
5060                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5061                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5062                         }
5063                         break;
5064                 case OP_LOADR4_MEMBASE:
5065                         if (cfg->r4fp) {
5066                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5067                         } else {
5068                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5069                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5070                         }
5071                         break;
5072                 case OP_ICONV_TO_R4:
5073                         if (cfg->r4fp) {
5074                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5075                         } else {
5076                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5077                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5078                         }
5079                         break;
5080                 case OP_ICONV_TO_R8:
5081                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5082                         break;
5083                 case OP_LCONV_TO_R4:
5084                         if (cfg->r4fp) {
5085                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5086                         } else {
5087                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5088                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5089                         }
5090                         break;
5091                 case OP_LCONV_TO_R8:
5092                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5093                         break;
5094                 case OP_FCONV_TO_R4:
5095                         if (cfg->r4fp) {
5096                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5097                         } else {
5098                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5099                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5100                         }
5101                         break;
5102                 case OP_FCONV_TO_I1:
5103                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5104                         break;
5105                 case OP_FCONV_TO_U1:
5106                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5107                         break;
5108                 case OP_FCONV_TO_I2:
5109                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5110                         break;
5111                 case OP_FCONV_TO_U2:
5112                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5113                         break;
5114                 case OP_FCONV_TO_U4:
5115                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5116                         break;
5117                 case OP_FCONV_TO_I4:
5118                 case OP_FCONV_TO_I:
5119                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5120                         break;
5121                 case OP_FCONV_TO_I8:
5122                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5123                         break;
5124
5125                 case OP_RCONV_TO_I1:
5126                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5127                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5128                         break;
5129                 case OP_RCONV_TO_U1:
5130                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5131                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5132                         break;
5133                 case OP_RCONV_TO_I2:
5134                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5135                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5136                         break;
5137                 case OP_RCONV_TO_U2:
5138                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5139                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5140                         break;
5141                 case OP_RCONV_TO_I4:
5142                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5143                         break;
5144                 case OP_RCONV_TO_U4:
5145                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5146                         break;
5147                 case OP_RCONV_TO_I8:
5148                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5149                         break;
5150                 case OP_RCONV_TO_R8:
5151                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5152                         break;
5153                 case OP_RCONV_TO_R4:
5154                         if (ins->dreg != ins->sreg1)
5155                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5156                         break;
5157
5158                 case OP_LCONV_TO_R_UN: {
5159                         guint8 *br [2];
5160
5161                         /* Based on gcc code */
5162                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5163                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5164
5165                         /* Positive case */
5166                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5167                         br [1] = code; x86_jump8 (code, 0);
5168                         amd64_patch (br [0], code);
5169
5170                         /* Negative case */
5171                         /* Save to the red zone */
5172                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5173                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5174                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5175                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5176                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5177                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5178                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5179                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5180                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5181                         /* Restore */
5182                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5183                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5184                         amd64_patch (br [1], code);
5185                         break;
5186                 }
5187                 case OP_LCONV_TO_OVF_U4:
5188                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5189                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5190                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5191                         break;
5192                 case OP_LCONV_TO_OVF_I4_UN:
5193                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5194                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5195                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5196                         break;
5197                 case OP_FMOVE:
5198                         if (ins->dreg != ins->sreg1)
5199                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5200                         break;
5201                 case OP_RMOVE:
5202                         if (ins->dreg != ins->sreg1)
5203                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5204                         break;
5205                 case OP_MOVE_F_TO_I4:
5206                         if (cfg->r4fp) {
5207                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5208                         } else {
5209                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5210                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5211                         }
5212                         break;
5213                 case OP_MOVE_I4_TO_F:
5214                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5215                         if (!cfg->r4fp)
5216                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5217                         break;
5218                 case OP_MOVE_F_TO_I8:
5219                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5220                         break;
5221                 case OP_MOVE_I8_TO_F:
5222                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5223                         break;
5224                 case OP_FADD:
5225                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5226                         break;
5227                 case OP_FSUB:
5228                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5229                         break;
5230                 case OP_FMUL:
5231                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5232                         break;
5233                 case OP_FDIV:
5234                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5235                         break;
5236                 case OP_FNEG: {
5237                         static double r8_0 = -0.0;
5238
5239                         g_assert (ins->sreg1 == ins->dreg);
5240
5241                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5242                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5243                         break;
5244                 }
5245                 case OP_SIN:
5246                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5247                         break;
5248                 case OP_COS:
5249                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5250                         break;
5251                 case OP_ABS: {
5252                         static guint64 d = 0x7fffffffffffffffUL;
5253
5254                         g_assert (ins->sreg1 == ins->dreg);
5255
5256                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5257                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5258                         break;
5259                 }
5260                 case OP_SQRT:
5261                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5262                         break;
5263
5264                 case OP_RADD:
5265                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5266                         break;
5267                 case OP_RSUB:
5268                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5269                         break;
5270                 case OP_RMUL:
5271                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5272                         break;
5273                 case OP_RDIV:
5274                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5275                         break;
5276                 case OP_RNEG: {
5277                         static float r4_0 = -0.0;
5278
5279                         g_assert (ins->sreg1 == ins->dreg);
5280
5281                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5282                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5283                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5284                         break;
5285                 }
5286
5287                 case OP_IMIN:
5288                         g_assert (cfg->opt & MONO_OPT_CMOV);
5289                         g_assert (ins->dreg == ins->sreg1);
5290                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5291                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5292                         break;
5293                 case OP_IMIN_UN:
5294                         g_assert (cfg->opt & MONO_OPT_CMOV);
5295                         g_assert (ins->dreg == ins->sreg1);
5296                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5297                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5298                         break;
5299                 case OP_IMAX:
5300                         g_assert (cfg->opt & MONO_OPT_CMOV);
5301                         g_assert (ins->dreg == ins->sreg1);
5302                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5303                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5304                         break;
5305                 case OP_IMAX_UN:
5306                         g_assert (cfg->opt & MONO_OPT_CMOV);
5307                         g_assert (ins->dreg == ins->sreg1);
5308                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5309                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5310                         break;
5311                 case OP_LMIN:
5312                         g_assert (cfg->opt & MONO_OPT_CMOV);
5313                         g_assert (ins->dreg == ins->sreg1);
5314                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5315                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5316                         break;
5317                 case OP_LMIN_UN:
5318                         g_assert (cfg->opt & MONO_OPT_CMOV);
5319                         g_assert (ins->dreg == ins->sreg1);
5320                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5321                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5322                         break;
5323                 case OP_LMAX:
5324                         g_assert (cfg->opt & MONO_OPT_CMOV);
5325                         g_assert (ins->dreg == ins->sreg1);
5326                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5327                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5328                         break;
5329                 case OP_LMAX_UN:
5330                         g_assert (cfg->opt & MONO_OPT_CMOV);
5331                         g_assert (ins->dreg == ins->sreg1);
5332                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5333                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5334                         break;
5335                 case OP_X86_FPOP:
5336                         break;
5337                 case OP_FCOMPARE:
5338                         /*
5339                          * The two arguments are swapped because the fbranch instructions
5340                          * depend on this for the non-sse case to work.
5341                          */
5342                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5343                         break;
5344                 case OP_RCOMPARE:
5345                         /*
5346                          * FIXME: Get rid of this.
5347                          * The two arguments are swapped because the fbranch instructions
5348                          * depend on this for the non-sse case to work.
5349                          */
5350                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5351                         break;
5352                 case OP_FCNEQ:
5353                 case OP_FCEQ: {
5354                         /* zeroing the register at the start results in
5355                          * shorter and faster code (we can also remove the widening op)
5356                          */
5357                         guchar *unordered_check;
5358
5359                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5360                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5361                         unordered_check = code;
5362                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5363
5364                         if (ins->opcode == OP_FCEQ) {
5365                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5366                                 amd64_patch (unordered_check, code);
5367                         } else {
5368                                 guchar *jump_to_end;
5369                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5370                                 jump_to_end = code;
5371                                 x86_jump8 (code, 0);
5372                                 amd64_patch (unordered_check, code);
5373                                 amd64_inc_reg (code, ins->dreg);
5374                                 amd64_patch (jump_to_end, code);
5375                         }
5376                         break;
5377                 }
5378                 case OP_FCLT:
5379                 case OP_FCLT_UN: {
5380                         /* zeroing the register at the start results in
5381                          * shorter and faster code (we can also remove the widening op)
5382                          */
5383                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5384                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5385                         if (ins->opcode == OP_FCLT_UN) {
5386                                 guchar *unordered_check = code;
5387                                 guchar *jump_to_end;
5388                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5389                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5390                                 jump_to_end = code;
5391                                 x86_jump8 (code, 0);
5392                                 amd64_patch (unordered_check, code);
5393                                 amd64_inc_reg (code, ins->dreg);
5394                                 amd64_patch (jump_to_end, code);
5395                         } else {
5396                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5397                         }
5398                         break;
5399                 }
5400                 case OP_FCLE: {
5401                         guchar *unordered_check;
5402                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5403                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5404                         unordered_check = code;
5405                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5406                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5407                         amd64_patch (unordered_check, code);
5408                         break;
5409                 }
5410                 case OP_FCGT:
5411                 case OP_FCGT_UN: {
5412                         /* zeroing the register at the start results in
5413                          * shorter and faster code (we can also remove the widening op)
5414                          */
5415                         guchar *unordered_check;
5416
5417                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5418                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5419                         if (ins->opcode == OP_FCGT) {
5420                                 unordered_check = code;
5421                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5423                                 amd64_patch (unordered_check, code);
5424                         } else {
5425                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5426                         }
5427                         break;
5428                 }
5429                 case OP_FCGE: {
5430                         guchar *unordered_check;
5431                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5432                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5433                         unordered_check = code;
5434                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5435                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5436                         amd64_patch (unordered_check, code);
5437                         break;
5438                 }
5439
5440                 case OP_RCEQ:
5441                 case OP_RCGT:
5442                 case OP_RCLT:
5443                 case OP_RCLT_UN:
5444                 case OP_RCGT_UN: {
5445                         int x86_cond;
5446                         gboolean unordered = FALSE;
5447
5448                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5449                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5450
5451                         switch (ins->opcode) {
5452                         case OP_RCEQ:
5453                                 x86_cond = X86_CC_EQ;
5454                                 break;
5455                         case OP_RCGT:
5456                                 x86_cond = X86_CC_LT;
5457                                 break;
5458                         case OP_RCLT:
5459                                 x86_cond = X86_CC_GT;
5460                                 break;
5461                         case OP_RCLT_UN:
5462                                 x86_cond = X86_CC_GT;
5463                                 unordered = TRUE;
5464                                 break;
5465                         case OP_RCGT_UN:
5466                                 x86_cond = X86_CC_LT;
5467                                 unordered = TRUE;
5468                                 break;
5469                         default:
5470                                 g_assert_not_reached ();
5471                                 break;
5472                         }
5473
5474                         if (unordered) {
5475                                 guchar *unordered_check;
5476                                 guchar *jump_to_end;
5477
5478                                 unordered_check = code;
5479                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5480                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5481                                 jump_to_end = code;
5482                                 x86_jump8 (code, 0);
5483                                 amd64_patch (unordered_check, code);
5484                                 amd64_inc_reg (code, ins->dreg);
5485                                 amd64_patch (jump_to_end, code);
5486                         } else {
5487                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5488                         }
5489                         break;
5490                 }
5491                 case OP_FCLT_MEMBASE:
5492                 case OP_FCGT_MEMBASE:
5493                 case OP_FCLT_UN_MEMBASE:
5494                 case OP_FCGT_UN_MEMBASE:
5495                 case OP_FCEQ_MEMBASE: {
5496                         guchar *unordered_check, *jump_to_end;
5497                         int x86_cond;
5498
5499                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5500                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5501
5502                         switch (ins->opcode) {
5503                         case OP_FCEQ_MEMBASE:
5504                                 x86_cond = X86_CC_EQ;
5505                                 break;
5506                         case OP_FCLT_MEMBASE:
5507                         case OP_FCLT_UN_MEMBASE:
5508                                 x86_cond = X86_CC_LT;
5509                                 break;
5510                         case OP_FCGT_MEMBASE:
5511                         case OP_FCGT_UN_MEMBASE:
5512                                 x86_cond = X86_CC_GT;
5513                                 break;
5514                         default:
5515                                 g_assert_not_reached ();
5516                         }
5517
5518                         unordered_check = code;
5519                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5520                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5521
5522                         switch (ins->opcode) {
5523                         case OP_FCEQ_MEMBASE:
5524                         case OP_FCLT_MEMBASE:
5525                         case OP_FCGT_MEMBASE:
5526                                 amd64_patch (unordered_check, code);
5527                                 break;
5528                         case OP_FCLT_UN_MEMBASE:
5529                         case OP_FCGT_UN_MEMBASE:
5530                                 jump_to_end = code;
5531                                 x86_jump8 (code, 0);
5532                                 amd64_patch (unordered_check, code);
5533                                 amd64_inc_reg (code, ins->dreg);
5534                                 amd64_patch (jump_to_end, code);
5535                                 break;
5536                         default:
5537                                 break;
5538                         }
5539                         break;
5540                 }
5541                 case OP_FBEQ: {
5542                         guchar *jump = code;
5543                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5544                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5545                         amd64_patch (jump, code);
5546                         break;
5547                 }
5548                 case OP_FBNE_UN:
5549                         /* Branch if C013 != 100 */
5550                         /* branch if !ZF or (PF|CF) */
5551                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5552                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5553                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5554                         break;
5555                 case OP_FBLT:
5556                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5557                         break;
5558                 case OP_FBLT_UN:
5559                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5560                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5561                         break;
5562                 case OP_FBGT:
5563                 case OP_FBGT_UN:
5564                         if (ins->opcode == OP_FBGT) {
5565                                 guchar *br1;
5566
5567                                 /* skip branch if C1=1 */
5568                                 br1 = code;
5569                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5570                                 /* branch if (C0 | C3) = 1 */
5571                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5572                                 amd64_patch (br1, code);
5573                                 break;
5574                         } else {
5575                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5576                         }
5577                         break;
5578                 case OP_FBGE: {
5579                         /* Branch if C013 == 100 or 001 */
5580                         guchar *br1;
5581
5582                         /* skip branch if C1=1 */
5583                         br1 = code;
5584                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5585                         /* branch if (C0 | C3) = 1 */
5586                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5587                         amd64_patch (br1, code);
5588                         break;
5589                 }
5590                 case OP_FBGE_UN:
5591                         /* Branch if C013 == 000 */
5592                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5593                         break;
5594                 case OP_FBLE: {
5595                         /* Branch if C013=000 or 100 */
5596                         guchar *br1;
5597
5598                         /* skip branch if C1=1 */
5599                         br1 = code;
5600                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5601                         /* branch if C0=0 */
5602                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5603                         amd64_patch (br1, code);
5604                         break;
5605                 }
5606                 case OP_FBLE_UN:
5607                         /* Branch if C013 != 001 */
5608                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5609                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5610                         break;
5611                 case OP_CKFINITE:
5612                         /* Transfer value to the fp stack */
5613                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5614                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5615                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5616
5617                         amd64_push_reg (code, AMD64_RAX);
5618                         amd64_fxam (code);
5619                         amd64_fnstsw (code);
5620                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5621                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5622                         amd64_pop_reg (code, AMD64_RAX);
5623                         amd64_fstp (code, 0);
5624                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5625                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5626                         break;
5627                 case OP_TLS_GET: {
5628                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5629                         break;
5630                 }
5631                 case OP_TLS_GET_REG:
5632                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5633                         break;
5634                 case OP_TLS_SET: {
5635                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5636                         break;
5637                 }
5638                 case OP_TLS_SET_REG: {
5639                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5640                         break;
5641                 }
5642                 case OP_MEMORY_BARRIER: {
5643                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5644                                 x86_mfence (code);
5645                         break;
5646                 }
5647                 case OP_ATOMIC_ADD_I4:
5648                 case OP_ATOMIC_ADD_I8: {
5649                         int dreg = ins->dreg;
5650                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5651
5652                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5653                                 dreg = AMD64_R11;
5654
5655                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5656                         amd64_prefix (code, X86_LOCK_PREFIX);
5657                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5658                         /* dreg contains the old value, add with sreg2 value */
5659                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5660
5661                         if (ins->dreg != dreg)
5662                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5663
5664                         break;
5665                 }
5666                 case OP_ATOMIC_EXCHANGE_I4:
5667                 case OP_ATOMIC_EXCHANGE_I8: {
5668                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5669
5670                         /* LOCK prefix is implied. */
5671                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5672                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5673                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5674                         break;
5675                 }
5676                 case OP_ATOMIC_CAS_I4:
5677                 case OP_ATOMIC_CAS_I8: {
5678                         guint32 size;
5679
5680                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5681                                 size = 8;
5682                         else
5683                                 size = 4;
5684
5685                         /*
5686                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5687                          * an explanation of how this works.
5688                          */
5689                         g_assert (ins->sreg3 == AMD64_RAX);
5690                         g_assert (ins->sreg1 != AMD64_RAX);
5691                         g_assert (ins->sreg1 != ins->sreg2);
5692
5693                         amd64_prefix (code, X86_LOCK_PREFIX);
5694                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5695
5696                         if (ins->dreg != AMD64_RAX)
5697                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5698                         break;
5699                 }
5700                 case OP_ATOMIC_LOAD_I1: {
5701                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5702                         break;
5703                 }
5704                 case OP_ATOMIC_LOAD_U1: {
5705                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5706                         break;
5707                 }
5708                 case OP_ATOMIC_LOAD_I2: {
5709                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5710                         break;
5711                 }
5712                 case OP_ATOMIC_LOAD_U2: {
5713                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5714                         break;
5715                 }
5716                 case OP_ATOMIC_LOAD_I4: {
5717                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5718                         break;
5719                 }
5720                 case OP_ATOMIC_LOAD_U4:
5721                 case OP_ATOMIC_LOAD_I8:
5722                 case OP_ATOMIC_LOAD_U8: {
5723                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5724                         break;
5725                 }
5726                 case OP_ATOMIC_LOAD_R4: {
5727                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5728                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5729                         break;
5730                 }
5731                 case OP_ATOMIC_LOAD_R8: {
5732                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5733                         break;
5734                 }
5735                 case OP_ATOMIC_STORE_I1:
5736                 case OP_ATOMIC_STORE_U1:
5737                 case OP_ATOMIC_STORE_I2:
5738                 case OP_ATOMIC_STORE_U2:
5739                 case OP_ATOMIC_STORE_I4:
5740                 case OP_ATOMIC_STORE_U4:
5741                 case OP_ATOMIC_STORE_I8:
5742                 case OP_ATOMIC_STORE_U8: {
5743                         int size;
5744
5745                         switch (ins->opcode) {
5746                         case OP_ATOMIC_STORE_I1:
5747                         case OP_ATOMIC_STORE_U1:
5748                                 size = 1;
5749                                 break;
5750                         case OP_ATOMIC_STORE_I2:
5751                         case OP_ATOMIC_STORE_U2:
5752                                 size = 2;
5753                                 break;
5754                         case OP_ATOMIC_STORE_I4:
5755                         case OP_ATOMIC_STORE_U4:
5756                                 size = 4;
5757                                 break;
5758                         case OP_ATOMIC_STORE_I8:
5759                         case OP_ATOMIC_STORE_U8:
5760                                 size = 8;
5761                                 break;
5762                         }
5763
5764                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5765
5766                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5767                                 x86_mfence (code);
5768                         break;
5769                 }
5770                 case OP_ATOMIC_STORE_R4: {
5771                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5772                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5773
5774                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5775                                 x86_mfence (code);
5776                         break;
5777                 }
5778                 case OP_ATOMIC_STORE_R8: {
5779                         x86_nop (code);
5780                         x86_nop (code);
5781                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5782                         x86_nop (code);
5783                         x86_nop (code);
5784
5785                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5786                                 x86_mfence (code);
5787                         break;
5788                 }
5789                 case OP_CARD_TABLE_WBARRIER: {
5790                         int ptr = ins->sreg1;
5791                         int value = ins->sreg2;
5792                         guchar *br = 0;
5793                         int nursery_shift, card_table_shift;
5794                         gpointer card_table_mask;
5795                         size_t nursery_size;
5796
5797                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5798                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5799                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5800
5801                         /*If either point to the stack we can simply avoid the WB. This happens due to
5802                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5803                          */
5804                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5805                                 continue;
5806
5807                         /*
5808                          * We need one register we can clobber, we choose EDX and make sreg1
5809                          * fixed EAX to work around limitations in the local register allocator.
5810                          * sreg2 might get allocated to EDX, but that is not a problem since
5811                          * we use it before clobbering EDX.
5812                          */
5813                         g_assert (ins->sreg1 == AMD64_RAX);
5814
5815                         /*
5816                          * This is the code we produce:
5817                          *
5818                          *   edx = value
5819                          *   edx >>= nursery_shift
5820                          *   cmp edx, (nursery_start >> nursery_shift)
5821                          *   jne done
5822                          *   edx = ptr
5823                          *   edx >>= card_table_shift
5824                          *   edx += cardtable
5825                          *   [edx] = 1
5826                          * done:
5827                          */
5828
5829                         if (mono_gc_card_table_nursery_check ()) {
5830                                 if (value != AMD64_RDX)
5831                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5832                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5833                                 if (shifted_nursery_start >> 31) {
5834                                         /*
5835                                          * The value we need to compare against is 64 bits, so we need
5836                                          * another spare register.  We use RBX, which we save and
5837                                          * restore.
5838                                          */
5839                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5840                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5841                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5842                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5843                                 } else {
5844                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5845                                 }
5846                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5847                         }
5848                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5849                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5850                         if (card_table_mask)
5851                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5852
5853                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5854                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5855
5856                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5857
5858                         if (mono_gc_card_table_nursery_check ())
5859                                 x86_patch (br, code);
5860                         break;
5861                 }
5862 #ifdef MONO_ARCH_SIMD_INTRINSICS
5863                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5864                 case OP_ADDPS:
5865                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5866                         break;
5867                 case OP_DIVPS:
5868                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_MULPS:
5871                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_SUBPS:
5874                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 case OP_MAXPS:
5877                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 case OP_MINPS:
5880                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_COMPPS:
5883                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5884                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5885                         break;
5886                 case OP_ANDPS:
5887                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_ANDNPS:
5890                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892                 case OP_ORPS:
5893                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_XORPS:
5896                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_SQRTPS:
5899                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5900                         break;
5901                 case OP_RSQRTPS:
5902                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5903                         break;
5904                 case OP_RCPPS:
5905                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5906                         break;
5907                 case OP_ADDSUBPS:
5908                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_HADDPS:
5911                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_HSUBPS:
5914                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_DUPPS_HIGH:
5917                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5918                         break;
5919                 case OP_DUPPS_LOW:
5920                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5921                         break;
5922
5923                 case OP_PSHUFLEW_HIGH:
5924                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5925                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5926                         break;
5927                 case OP_PSHUFLEW_LOW:
5928                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5929                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5930                         break;
5931                 case OP_PSHUFLED:
5932                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5933                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5934                         break;
5935                 case OP_SHUFPS:
5936                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5937                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5938                         break;
5939                 case OP_SHUFPD:
5940                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5941                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5942                         break;
5943
5944                 case OP_ADDPD:
5945                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_DIVPD:
5948                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5949                         break;
5950                 case OP_MULPD:
5951                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953                 case OP_SUBPD:
5954                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956                 case OP_MAXPD:
5957                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_MINPD:
5960                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_COMPPD:
5963                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5964                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5965                         break;
5966                 case OP_ANDPD:
5967                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969                 case OP_ANDNPD:
5970                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_ORPD:
5973                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_XORPD:
5976                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_SQRTPD:
5979                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5980                         break;
5981                 case OP_ADDSUBPD:
5982                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_HADDPD:
5985                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_HSUBPD:
5988                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_DUPPD:
5991                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5992                         break;
5993
5994                 case OP_EXTRACT_MASK:
5995                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5996                         break;
5997
5998                 case OP_PAND:
5999                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_POR:
6002                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_PXOR:
6005                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007
6008                 case OP_PADDB:
6009                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PADDW:
6012                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PADDD:
6015                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_PADDQ:
6018                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020
6021                 case OP_PSUBB:
6022                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_PSUBW:
6025                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PSUBD:
6028                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030                 case OP_PSUBQ:
6031                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033
6034                 case OP_PMAXB_UN:
6035                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PMAXW_UN:
6038                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_PMAXD_UN:
6041                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043
6044                 case OP_PMAXB:
6045                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PMAXW:
6048                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_PMAXD:
6051                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053
6054                 case OP_PAVGB_UN:
6055                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PAVGW_UN:
6058                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060
6061                 case OP_PMINB_UN:
6062                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_PMINW_UN:
6065                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PMIND_UN:
6068                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070
6071                 case OP_PMINB:
6072                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_PMINW:
6075                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_PMIND:
6078                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080
6081                 case OP_PCMPEQB:
6082                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084                 case OP_PCMPEQW:
6085                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PCMPEQD:
6088                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PCMPEQQ:
6091                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093
6094                 case OP_PCMPGTB:
6095                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097                 case OP_PCMPGTW:
6098                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PCMPGTD:
6101                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_PCMPGTQ:
6104                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106
6107                 case OP_PSUM_ABS_DIFF:
6108                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110
6111                 case OP_UNPACK_LOWB:
6112                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_UNPACK_LOWW:
6115                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_UNPACK_LOWD:
6118                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_UNPACK_LOWQ:
6121                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_UNPACK_LOWPS:
6124                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_UNPACK_LOWPD:
6127                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129
6130                 case OP_UNPACK_HIGHB:
6131                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_UNPACK_HIGHW:
6134                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_UNPACK_HIGHD:
6137                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_UNPACK_HIGHQ:
6140                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_UNPACK_HIGHPS:
6143                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_UNPACK_HIGHPD:
6146                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148
6149                 case OP_PACKW:
6150                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152                 case OP_PACKD:
6153                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155                 case OP_PACKW_UN:
6156                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158                 case OP_PACKD_UN:
6159                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161
6162                 case OP_PADDB_SAT_UN:
6163                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_PSUBB_SAT_UN:
6166                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6167                         break;
6168                 case OP_PADDW_SAT_UN:
6169                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171                 case OP_PSUBW_SAT_UN:
6172                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174
6175                 case OP_PADDB_SAT:
6176                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_PSUBB_SAT:
6179                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_PADDW_SAT:
6182                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184                 case OP_PSUBW_SAT:
6185                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6186                         break;
6187
6188                 case OP_PMULW:
6189                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_PMULD:
6192                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_PMULQ:
6195                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_PMULW_HIGH_UN:
6198                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_PMULW_HIGH:
6201                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203
6204                 case OP_PSHRW:
6205                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6206                         break;
6207                 case OP_PSHRW_REG:
6208                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6209                         break;
6210
6211                 case OP_PSARW:
6212                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6213                         break;
6214                 case OP_PSARW_REG:
6215                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6216                         break;
6217
6218                 case OP_PSHLW:
6219                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6220                         break;
6221                 case OP_PSHLW_REG:
6222                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6223                         break;
6224
6225                 case OP_PSHRD:
6226                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6227                         break;
6228                 case OP_PSHRD_REG:
6229                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6230                         break;
6231
6232                 case OP_PSARD:
6233                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6234                         break;
6235                 case OP_PSARD_REG:
6236                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6237                         break;
6238
6239                 case OP_PSHLD:
6240                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6241                         break;
6242                 case OP_PSHLD_REG:
6243                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6244                         break;
6245
6246                 case OP_PSHRQ:
6247                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6248                         break;
6249                 case OP_PSHRQ_REG:
6250                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6251                         break;
6252
6253                 /*TODO: This is appart of the sse spec but not added
6254                 case OP_PSARQ:
6255                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6256                         break;
6257                 case OP_PSARQ_REG:
6258                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6259                         break;
6260                 */
6261
6262                 case OP_PSHLQ:
6263                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6264                         break;
6265                 case OP_PSHLQ_REG:
6266                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6267                         break;
6268                 case OP_CVTDQ2PD:
6269                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6270                         break;
6271                 case OP_CVTDQ2PS:
6272                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6273                         break;
6274                 case OP_CVTPD2DQ:
6275                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6276                         break;
6277                 case OP_CVTPD2PS:
6278                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6279                         break;
6280                 case OP_CVTPS2DQ:
6281                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6282                         break;
6283                 case OP_CVTPS2PD:
6284                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6285                         break;
6286                 case OP_CVTTPD2DQ:
6287                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6288                         break;
6289                 case OP_CVTTPS2DQ:
6290                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6291                         break;
6292
6293                 case OP_ICONV_TO_X:
6294                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6295                         break;
6296                 case OP_EXTRACT_I4:
6297                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6298                         break;
6299                 case OP_EXTRACT_I8:
6300                         if (ins->inst_c0) {
6301                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6302                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6303                         } else {
6304                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6305                         }
6306                         break;
6307                 case OP_EXTRACT_I1:
6308                 case OP_EXTRACT_U1:
6309                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6310                         if (ins->inst_c0)
6311                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6312                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6313                         break;
6314                 case OP_EXTRACT_I2:
6315                 case OP_EXTRACT_U2:
6316                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6317                         if (ins->inst_c0)
6318                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6319                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6320                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6321                         break;
6322                 case OP_EXTRACT_R8:
6323                         if (ins->inst_c0)
6324                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6325                         else
6326                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6327                         break;
6328                 case OP_INSERT_I2:
6329                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6330                         break;
6331                 case OP_EXTRACTX_U2:
6332                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6333                         break;
6334                 case OP_INSERTX_U1_SLOW:
6335                         /*sreg1 is the extracted ireg (scratch)
6336                         /sreg2 is the to be inserted ireg (scratch)
6337                         /dreg is the xreg to receive the value*/
6338
6339                         /*clear the bits from the extracted word*/
6340                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6341                         /*shift the value to insert if needed*/
6342                         if (ins->inst_c0 & 1)
6343                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6344                         /*join them together*/
6345                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6346                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6347                         break;
6348                 case OP_INSERTX_I4_SLOW:
6349                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6350                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6351                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6352                         break;
6353                 case OP_INSERTX_I8_SLOW:
6354                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6355                         if (ins->inst_c0)
6356                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6357                         else
6358                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6359                         break;
6360
6361                 case OP_INSERTX_R4_SLOW:
6362                         switch (ins->inst_c0) {
6363                         case 0:
6364                                 if (cfg->r4fp)
6365                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6366                                 else
6367                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6368                                 break;
6369                         case 1:
6370                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6371                                 if (cfg->r4fp)
6372                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6373                                 else
6374                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6375                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6376                                 break;
6377                         case 2:
6378                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6379                                 if (cfg->r4fp)
6380                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6381                                 else
6382                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6383                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6384                                 break;
6385                         case 3:
6386                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6387                                 if (cfg->r4fp)
6388                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6389                                 else
6390                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6391                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6392                                 break;
6393                         }
6394                         break;
6395                 case OP_INSERTX_R8_SLOW:
6396                         if (ins->inst_c0)
6397                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6398                         else
6399                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6400                         break;
6401                 case OP_STOREX_MEMBASE_REG:
6402                 case OP_STOREX_MEMBASE:
6403                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6404                         break;
6405                 case OP_LOADX_MEMBASE:
6406                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6407                         break;
6408                 case OP_LOADX_ALIGNED_MEMBASE:
6409                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6410                         break;
6411                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6412                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6413                         break;
6414                 case OP_STOREX_NTA_MEMBASE_REG:
6415                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6416                         break;
6417                 case OP_PREFETCH_MEMBASE:
6418                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6419                         break;
6420
6421                 case OP_XMOVE:
6422                         /*FIXME the peephole pass should have killed this*/
6423                         if (ins->dreg != ins->sreg1)
6424                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6425                         break;
6426                 case OP_XZERO:
6427                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6428                         break;
6429                 case OP_ICONV_TO_R4_RAW:
6430                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6431                         break;
6432
6433                 case OP_FCONV_TO_R8_X:
6434                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6435                         break;
6436
6437                 case OP_XCONV_R8_TO_I4:
6438                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6439                         switch (ins->backend.source_opcode) {
6440                         case OP_FCONV_TO_I1:
6441                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6442                                 break;
6443                         case OP_FCONV_TO_U1:
6444                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6445                                 break;
6446                         case OP_FCONV_TO_I2:
6447                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6448                                 break;
6449                         case OP_FCONV_TO_U2:
6450                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6451                                 break;
6452                         }
6453                         break;
6454
6455                 case OP_EXPAND_I2:
6456                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6457                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6458                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6459                         break;
6460                 case OP_EXPAND_I4:
6461                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6462                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6463                         break;
6464                 case OP_EXPAND_I8:
6465                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6466                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6467                         break;
6468                 case OP_EXPAND_R4:
6469                         if (cfg->r4fp) {
6470                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6471                         } else {
6472                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6473                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6474                         }
6475                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6476                         break;
6477                 case OP_EXPAND_R8:
6478                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6479                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6480                         break;
6481 #endif
6482                 case OP_LIVERANGE_START: {
6483                         if (cfg->verbose_level > 1)
6484                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6485                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6486                         break;
6487                 }
6488                 case OP_LIVERANGE_END: {
6489                         if (cfg->verbose_level > 1)
6490                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6491                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6492                         break;
6493                 }
6494                 case OP_GC_SAFE_POINT: {
6495                         guint8 *br [1];
6496
6497                         g_assert (mono_threads_is_coop_enabled ());
6498
6499                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6500                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6501                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6502                         amd64_patch (br[0], code);
6503                         break;
6504                 }
6505
6506                 case OP_GC_LIVENESS_DEF:
6507                 case OP_GC_LIVENESS_USE:
6508                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6509                         ins->backend.pc_offset = code - cfg->native_code;
6510                         break;
6511                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6512                         ins->backend.pc_offset = code - cfg->native_code;
6513                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6514                         break;
6515                 default:
6516                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6517                         g_assert_not_reached ();
6518                 }
6519
6520                 if ((code - cfg->native_code - offset) > max_len) {
6521                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6522                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6523                         g_assert_not_reached ();
6524                 }
6525         }
6526
6527         cfg->code_len = code - cfg->native_code;
6528 }
6529
6530 #endif /* DISABLE_JIT */
6531
6532 void
6533 mono_arch_register_lowlevel_calls (void)
6534 {
6535         /* The signature doesn't matter */
6536         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6537 }
6538
6539 void
6540 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6541 {
6542         unsigned char *ip = ji->ip.i + code;
6543
6544         /*
6545          * Debug code to help track down problems where the target of a near call is
6546          * is not valid.
6547          */
6548         if (amd64_is_near_call (ip)) {
6549                 gint64 disp = (guint8*)target - (guint8*)ip;
6550
6551                 if (!amd64_is_imm32 (disp)) {
6552                         printf ("TYPE: %d\n", ji->type);
6553                         switch (ji->type) {
6554                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6555                                 printf ("V: %s\n", ji->data.name);
6556                                 break;
6557                         case MONO_PATCH_INFO_METHOD_JUMP:
6558                         case MONO_PATCH_INFO_METHOD:
6559                                 printf ("V: %s\n", ji->data.method->name);
6560                                 break;
6561                         default:
6562                                 break;
6563                         }
6564                 }
6565         }
6566
6567         amd64_patch (ip, (gpointer)target);
6568 }
6569
6570 #ifndef DISABLE_JIT
6571
6572 static int
6573 get_max_epilog_size (MonoCompile *cfg)
6574 {
6575         int max_epilog_size = 16;
6576
6577         if (cfg->method->save_lmf)
6578                 max_epilog_size += 256;
6579
6580         if (mono_jit_trace_calls != NULL)
6581                 max_epilog_size += 50;
6582
6583         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6584                 max_epilog_size += 50;
6585
6586         max_epilog_size += (AMD64_NREG * 2);
6587
6588         return max_epilog_size;
6589 }
6590
6591 /*
6592  * This macro is used for testing whenever the unwinder works correctly at every point
6593  * where an async exception can happen.
6594  */
6595 /* This will generate a SIGSEGV at the given point in the code */
6596 #define async_exc_point(code) do { \
6597     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6598          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6599              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6600          cfg->arch.async_point_count ++; \
6601     } \
6602 } while (0)
6603
6604 guint8 *
6605 mono_arch_emit_prolog (MonoCompile *cfg)
6606 {
6607         MonoMethod *method = cfg->method;
6608         MonoBasicBlock *bb;
6609         MonoMethodSignature *sig;
6610         MonoInst *ins;
6611         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6612         guint8 *code;
6613         CallInfo *cinfo;
6614         MonoInst *lmf_var = cfg->lmf_var;
6615         gboolean args_clobbered = FALSE;
6616         gboolean trace = FALSE;
6617
6618         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6619
6620         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6621
6622         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6623                 trace = TRUE;
6624
6625         /* Amount of stack space allocated by register saving code */
6626         pos = 0;
6627
6628         /* Offset between RSP and the CFA */
6629         cfa_offset = 0;
6630
6631         /*
6632          * The prolog consists of the following parts:
6633          * FP present:
6634          * - push rbp, mov rbp, rsp
6635          * - save callee saved regs using pushes
6636          * - allocate frame
6637          * - save rgctx if needed
6638          * - save lmf if needed
6639          * FP not present:
6640          * - allocate frame
6641          * - save rgctx if needed
6642          * - save lmf if needed
6643          * - save callee saved regs using moves
6644          */
6645
6646         // CFA = sp + 8
6647         cfa_offset = 8;
6648         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6649         // IP saved at CFA - 8
6650         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6651         async_exc_point (code);
6652         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6653
6654         if (!cfg->arch.omit_fp) {
6655                 amd64_push_reg (code, AMD64_RBP);
6656                 cfa_offset += 8;
6657                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6658                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6659                 async_exc_point (code);
6660 #ifdef TARGET_WIN32
6661                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6662 #endif
6663                 /* These are handled automatically by the stack marking code */
6664                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6665
6666                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6667                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6668                 async_exc_point (code);
6669 #ifdef TARGET_WIN32
6670                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6671 #endif
6672         }
6673
6674         /* The param area is always at offset 0 from sp */
6675         /* This needs to be allocated here, since it has to come after the spill area */
6676         if (cfg->param_area) {
6677                 if (cfg->arch.omit_fp)
6678                         // FIXME:
6679                         g_assert_not_reached ();
6680                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6681         }
6682
6683         if (cfg->arch.omit_fp) {
6684                 /*
6685                  * On enter, the stack is misaligned by the pushing of the return
6686                  * address. It is either made aligned by the pushing of %rbp, or by
6687                  * this.
6688                  */
6689                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6690                 if ((alloc_size % 16) == 0) {
6691                         alloc_size += 8;
6692                         /* Mark the padding slot as NOREF */
6693                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6694                 }
6695         } else {
6696                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6697                 if (cfg->stack_offset != alloc_size) {
6698                         /* Mark the padding slot as NOREF */
6699                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6700                 }
6701                 cfg->arch.sp_fp_offset = alloc_size;
6702                 alloc_size -= pos;
6703         }
6704
6705         cfg->arch.stack_alloc_size = alloc_size;
6706
6707         /* Allocate stack frame */
6708         if (alloc_size) {
6709                 /* See mono_emit_stack_alloc */
6710 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6711                 guint32 remaining_size = alloc_size;
6712                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6713                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6714                 guint32 offset = code - cfg->native_code;
6715                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6716                         while (required_code_size >= (cfg->code_size - offset))
6717                                 cfg->code_size *= 2;
6718                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6719                         code = cfg->native_code + offset;
6720                         cfg->stat_code_reallocs++;
6721                 }
6722
6723                 while (remaining_size >= 0x1000) {
6724                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6725                         if (cfg->arch.omit_fp) {
6726                                 cfa_offset += 0x1000;
6727                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6728                         }
6729                         async_exc_point (code);
6730 #ifdef TARGET_WIN32
6731                         if (cfg->arch.omit_fp)
6732                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6733 #endif
6734
6735                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6736                         remaining_size -= 0x1000;
6737                 }
6738                 if (remaining_size) {
6739                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6740                         if (cfg->arch.omit_fp) {
6741                                 cfa_offset += remaining_size;
6742                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6743                                 async_exc_point (code);
6744                         }
6745 #ifdef TARGET_WIN32
6746                         if (cfg->arch.omit_fp)
6747                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6748 #endif
6749                 }
6750 #else
6751                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6752                 if (cfg->arch.omit_fp) {
6753                         cfa_offset += alloc_size;
6754                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6755                         async_exc_point (code);
6756                 }
6757 #endif
6758         }
6759
6760         /* Stack alignment check */
6761 #if 0
6762         {
6763                 guint8 *buf;
6764
6765                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6766                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6767                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6768                 buf = code;
6769                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6770                 amd64_breakpoint (code);
6771                 amd64_patch (buf, code);
6772         }
6773 #endif
6774
6775         if (mini_get_debug_options ()->init_stacks) {
6776                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6777
6778                 /* Save registers to the red zone */
6779                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6780                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6781
6782                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6783                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6784                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6785
6786                 amd64_cld (code);
6787                 amd64_prefix (code, X86_REP_PREFIX);
6788                 amd64_stosl (code);
6789
6790                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6791                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6792         }
6793
6794         /* Save LMF */
6795         if (method->save_lmf)
6796                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6797
6798         /* Save callee saved registers */
6799         if (cfg->arch.omit_fp) {
6800                 save_area_offset = cfg->arch.reg_save_area_offset;
6801                 /* Save caller saved registers after sp is adjusted */
6802                 /* The registers are saved at the bottom of the frame */
6803                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6804         } else {
6805                 /* The registers are saved just below the saved rbp */
6806                 save_area_offset = cfg->arch.reg_save_area_offset;
6807         }
6808
6809         for (i = 0; i < AMD64_NREG; ++i) {
6810                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6811                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6812
6813                         if (cfg->arch.omit_fp) {
6814                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6815                                 /* These are handled automatically by the stack marking code */
6816                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6817                         } else {
6818                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6819                                 // FIXME: GC
6820                         }
6821
6822                         save_area_offset += 8;
6823                         async_exc_point (code);
6824                 }
6825         }
6826
6827         /* store runtime generic context */
6828         if (cfg->rgctx_var) {
6829                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6830                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6831
6832                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6833
6834                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6835                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6836         }
6837
6838         /* compute max_length in order to use short forward jumps */
6839         max_epilog_size = get_max_epilog_size (cfg);
6840         if (cfg->opt & MONO_OPT_BRANCH) {
6841                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6842                         MonoInst *ins;
6843                         int max_length = 0;
6844
6845                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6846                                 max_length += 6;
6847                         /* max alignment for loops */
6848                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6849                                 max_length += LOOP_ALIGNMENT;
6850
6851                         MONO_BB_FOR_EACH_INS (bb, ins) {
6852                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6853                         }
6854
6855                         /* Take prolog and epilog instrumentation into account */
6856                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6857                                 max_length += max_epilog_size;
6858
6859                         bb->max_length = max_length;
6860                 }
6861         }
6862
6863         sig = mono_method_signature (method);
6864         pos = 0;
6865
6866         cinfo = (CallInfo *)cfg->arch.cinfo;
6867
6868         if (sig->ret->type != MONO_TYPE_VOID) {
6869                 /* Save volatile arguments to the stack */
6870                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6871                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6872         }
6873
6874         /* Keep this in sync with emit_load_volatile_arguments */
6875         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6876                 ArgInfo *ainfo = cinfo->args + i;
6877
6878                 ins = cfg->args [i];
6879
6880                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6881                         /* Unused arguments */
6882                         continue;
6883
6884                 /* Save volatile arguments to the stack */
6885                 if (ins->opcode != OP_REGVAR) {
6886                         switch (ainfo->storage) {
6887                         case ArgInIReg: {
6888                                 guint32 size = 8;
6889
6890                                 /* FIXME: I1 etc */
6891                                 /*
6892                                 if (stack_offset & 0x1)
6893                                         size = 1;
6894                                 else if (stack_offset & 0x2)
6895                                         size = 2;
6896                                 else if (stack_offset & 0x4)
6897                                         size = 4;
6898                                 else
6899                                         size = 8;
6900                                 */
6901                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6902
6903                                 /*
6904                                  * Save the original location of 'this',
6905                                  * get_generic_info_from_stack_frame () needs this to properly look up
6906                                  * the argument value during the handling of async exceptions.
6907                                  */
6908                                 if (ins == cfg->args [0]) {
6909                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6910                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6911                                 }
6912                                 break;
6913                         }
6914                         case ArgInFloatSSEReg:
6915                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6916                                 break;
6917                         case ArgInDoubleSSEReg:
6918                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6919                                 break;
6920                         case ArgValuetypeInReg:
6921                                 for (quad = 0; quad < 2; quad ++) {
6922                                         switch (ainfo->pair_storage [quad]) {
6923                                         case ArgInIReg:
6924                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6925                                                 break;
6926                                         case ArgInFloatSSEReg:
6927                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6928                                                 break;
6929                                         case ArgInDoubleSSEReg:
6930                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6931                                                 break;
6932                                         case ArgNone:
6933                                                 break;
6934                                         default:
6935                                                 g_assert_not_reached ();
6936                                         }
6937                                 }
6938                                 break;
6939                         case ArgValuetypeAddrInIReg:
6940                                 if (ainfo->pair_storage [0] == ArgInIReg)
6941                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6942                                 break;
6943                         case ArgGSharedVtInReg:
6944                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6945                                 break;
6946                         default:
6947                                 break;
6948                         }
6949                 } else {
6950                         /* Argument allocated to (non-volatile) register */
6951                         switch (ainfo->storage) {
6952                         case ArgInIReg:
6953                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6954                                 break;
6955                         case ArgOnStack:
6956                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6957                                 break;
6958                         default:
6959                                 g_assert_not_reached ();
6960                         }
6961
6962                         if (ins == cfg->args [0]) {
6963                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6964                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6965                         }
6966                 }
6967         }
6968
6969         if (cfg->method->save_lmf)
6970                 args_clobbered = TRUE;
6971
6972         if (trace) {
6973                 args_clobbered = TRUE;
6974                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6975         }
6976
6977         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6978                 args_clobbered = TRUE;
6979
6980         /*
6981          * Optimize the common case of the first bblock making a call with the same
6982          * arguments as the method. This works because the arguments are still in their
6983          * original argument registers.
6984          * FIXME: Generalize this
6985          */
6986         if (!args_clobbered) {
6987                 MonoBasicBlock *first_bb = cfg->bb_entry;
6988                 MonoInst *next;
6989                 int filter = FILTER_IL_SEQ_POINT;
6990
6991                 next = mono_bb_first_inst (first_bb, filter);
6992                 if (!next && first_bb->next_bb) {
6993                         first_bb = first_bb->next_bb;
6994                         next = mono_bb_first_inst (first_bb, filter);
6995                 }
6996
6997                 if (first_bb->in_count > 1)
6998                         next = NULL;
6999
7000                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7001                         ArgInfo *ainfo = cinfo->args + i;
7002                         gboolean match = FALSE;
7003
7004                         ins = cfg->args [i];
7005                         if (ins->opcode != OP_REGVAR) {
7006                                 switch (ainfo->storage) {
7007                                 case ArgInIReg: {
7008                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7009                                                 if (next->dreg == ainfo->reg) {
7010                                                         NULLIFY_INS (next);
7011                                                         match = TRUE;
7012                                                 } else {
7013                                                         next->opcode = OP_MOVE;
7014                                                         next->sreg1 = ainfo->reg;
7015                                                         /* Only continue if the instruction doesn't change argument regs */
7016                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7017                                                                 match = TRUE;
7018                                                 }
7019                                         }
7020                                         break;
7021                                 }
7022                                 default:
7023                                         break;
7024                                 }
7025                         } else {
7026                                 /* Argument allocated to (non-volatile) register */
7027                                 switch (ainfo->storage) {
7028                                 case ArgInIReg:
7029                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7030                                                 NULLIFY_INS (next);
7031                                                 match = TRUE;
7032                                         }
7033                                         break;
7034                                 default:
7035                                         break;
7036                                 }
7037                         }
7038
7039                         if (match) {
7040                                 next = mono_inst_next (next, filter);
7041                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7042                                 if (!next)
7043                                         break;
7044                         }
7045                 }
7046         }
7047
7048         if (cfg->gen_sdb_seq_points) {
7049                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7050
7051                 /* Initialize seq_point_info_var */
7052                 if (cfg->compile_aot) {
7053                         /* Initialize the variable from a GOT slot */
7054                         /* Same as OP_AOTCONST */
7055                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7056                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7057                         g_assert (info_var->opcode == OP_REGOFFSET);
7058                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7059                 }
7060
7061                 if (cfg->compile_aot) {
7062                         /* Initialize ss_tramp_var */
7063                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7064                         g_assert (ins->opcode == OP_REGOFFSET);
7065
7066                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7067                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7068                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7069                 } else {
7070                         /* Initialize ss_tramp_var */
7071                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7072                         g_assert (ins->opcode == OP_REGOFFSET);
7073
7074                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7075                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7076
7077                         /* Initialize bp_tramp_var */
7078                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7079                         g_assert (ins->opcode == OP_REGOFFSET);
7080
7081                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7082                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7083                 }
7084         }
7085
7086         cfg->code_len = code - cfg->native_code;
7087
7088         g_assert (cfg->code_len < cfg->code_size);
7089
7090         return code;
7091 }
7092
7093 void
7094 mono_arch_emit_epilog (MonoCompile *cfg)
7095 {
7096         MonoMethod *method = cfg->method;
7097         int quad, i;
7098         guint8 *code;
7099         int max_epilog_size;
7100         CallInfo *cinfo;
7101         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7102         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7103
7104         max_epilog_size = get_max_epilog_size (cfg);
7105
7106         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7107                 cfg->code_size *= 2;
7108                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7109                 cfg->stat_code_reallocs++;
7110         }
7111         code = cfg->native_code + cfg->code_len;
7112
7113         cfg->has_unwind_info_for_epilog = TRUE;
7114
7115         /* Mark the start of the epilog */
7116         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7117
7118         /* Save the uwind state which is needed by the out-of-line code */
7119         mono_emit_unwind_op_remember_state (cfg, code);
7120
7121         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7122                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7123
7124         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7125
7126         if (method->save_lmf) {
7127                 /* check if we need to restore protection of the stack after a stack overflow */
7128                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7129                         guint8 *patch;
7130                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7131                         /* we load the value in a separate instruction: this mechanism may be
7132                          * used later as a safer way to do thread interruption
7133                          */
7134                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7135                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7136                         patch = code;
7137                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7138                         /* note that the call trampoline will preserve eax/edx */
7139                         x86_call_reg (code, X86_ECX);
7140                         x86_patch (patch, code);
7141                 } else {
7142                         /* FIXME: maybe save the jit tls in the prolog */
7143                 }
7144                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7145                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7146                 }
7147         }
7148
7149         /* Restore callee saved regs */
7150         for (i = 0; i < AMD64_NREG; ++i) {
7151                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7152                         /* Restore only used_int_regs, not arch.saved_iregs */
7153 #if defined(MONO_SUPPORT_TASKLETS)
7154                         int restore_reg=1;
7155 #else
7156                         int restore_reg=(cfg->used_int_regs & (1 << i));
7157 #endif
7158                         if (restore_reg) {
7159                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7160                                 mono_emit_unwind_op_same_value (cfg, code, i);
7161                                 async_exc_point (code);
7162                         }
7163                         save_area_offset += 8;
7164                 }
7165         }
7166
7167         /* Load returned vtypes into registers if needed */
7168         cinfo = (CallInfo *)cfg->arch.cinfo;
7169         if (cinfo->ret.storage == ArgValuetypeInReg) {
7170                 ArgInfo *ainfo = &cinfo->ret;
7171                 MonoInst *inst = cfg->ret;
7172
7173                 for (quad = 0; quad < 2; quad ++) {
7174                         switch (ainfo->pair_storage [quad]) {
7175                         case ArgInIReg:
7176                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7177                                 break;
7178                         case ArgInFloatSSEReg:
7179                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7180                                 break;
7181                         case ArgInDoubleSSEReg:
7182                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7183                                 break;
7184                         case ArgNone:
7185                                 break;
7186                         default:
7187                                 g_assert_not_reached ();
7188                         }
7189                 }
7190         }
7191
7192         if (cfg->arch.omit_fp) {
7193                 if (cfg->arch.stack_alloc_size) {
7194                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7195                 }
7196         } else {
7197                 amd64_leave (code);
7198                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7199         }
7200         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7201         async_exc_point (code);
7202         amd64_ret (code);
7203
7204         /* Restore the unwind state to be the same as before the epilog */
7205         mono_emit_unwind_op_restore_state (cfg, code);
7206
7207         cfg->code_len = code - cfg->native_code;
7208
7209         g_assert (cfg->code_len < cfg->code_size);
7210 }
7211
7212 void
7213 mono_arch_emit_exceptions (MonoCompile *cfg)
7214 {
7215         MonoJumpInfo *patch_info;
7216         int nthrows, i;
7217         guint8 *code;
7218         MonoClass *exc_classes [16];
7219         guint8 *exc_throw_start [16], *exc_throw_end [16];
7220         guint32 code_size = 0;
7221
7222         /* Compute needed space */
7223         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7224                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7225                         code_size += 40;
7226                 if (patch_info->type == MONO_PATCH_INFO_R8)
7227                         code_size += 8 + 15; /* sizeof (double) + alignment */
7228                 if (patch_info->type == MONO_PATCH_INFO_R4)
7229                         code_size += 4 + 15; /* sizeof (float) + alignment */
7230                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7231                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7232         }
7233
7234         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7235                 cfg->code_size *= 2;
7236                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7237                 cfg->stat_code_reallocs++;
7238         }
7239
7240         code = cfg->native_code + cfg->code_len;
7241
7242         /* add code to raise exceptions */
7243         nthrows = 0;
7244         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7245                 switch (patch_info->type) {
7246                 case MONO_PATCH_INFO_EXC: {
7247                         MonoClass *exc_class;
7248                         guint8 *buf, *buf2;
7249                         guint32 throw_ip;
7250
7251                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7252
7253                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7254                         throw_ip = patch_info->ip.i;
7255
7256                         //x86_breakpoint (code);
7257                         /* Find a throw sequence for the same exception class */
7258                         for (i = 0; i < nthrows; ++i)
7259                                 if (exc_classes [i] == exc_class)
7260                                         break;
7261                         if (i < nthrows) {
7262                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7263                                 x86_jump_code (code, exc_throw_start [i]);
7264                                 patch_info->type = MONO_PATCH_INFO_NONE;
7265                         }
7266                         else {
7267                                 buf = code;
7268                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7269                                 buf2 = code;
7270
7271                                 if (nthrows < 16) {
7272                                         exc_classes [nthrows] = exc_class;
7273                                         exc_throw_start [nthrows] = code;
7274                                 }
7275                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7276
7277                                 patch_info->type = MONO_PATCH_INFO_NONE;
7278
7279                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7280
7281                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7282                                 while (buf < buf2)
7283                                         x86_nop (buf);
7284
7285                                 if (nthrows < 16) {
7286                                         exc_throw_end [nthrows] = code;
7287                                         nthrows ++;
7288                                 }
7289                         }
7290                         break;
7291                 }
7292                 default:
7293                         /* do nothing */
7294                         break;
7295                 }
7296                 g_assert(code < cfg->native_code + cfg->code_size);
7297         }
7298
7299         /* Handle relocations with RIP relative addressing */
7300         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7301                 gboolean remove = FALSE;
7302                 guint8 *orig_code = code;
7303
7304                 switch (patch_info->type) {
7305                 case MONO_PATCH_INFO_R8:
7306                 case MONO_PATCH_INFO_R4: {
7307                         guint8 *pos, *patch_pos;
7308                         guint32 target_pos;
7309
7310                         /* The SSE opcodes require a 16 byte alignment */
7311                         code = (guint8*)ALIGN_TO (code, 16);
7312
7313                         pos = cfg->native_code + patch_info->ip.i;
7314                         if (IS_REX (pos [1])) {
7315                                 patch_pos = pos + 5;
7316                                 target_pos = code - pos - 9;
7317                         }
7318                         else {
7319                                 patch_pos = pos + 4;
7320                                 target_pos = code - pos - 8;
7321                         }
7322
7323                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7324                                 *(double*)code = *(double*)patch_info->data.target;
7325                                 code += sizeof (double);
7326                         } else {
7327                                 *(float*)code = *(float*)patch_info->data.target;
7328                                 code += sizeof (float);
7329                         }
7330
7331                         *(guint32*)(patch_pos) = target_pos;
7332
7333                         remove = TRUE;
7334                         break;
7335                 }
7336                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7337                         guint8 *pos;
7338
7339                         if (cfg->compile_aot)
7340                                 continue;
7341
7342                         /*loading is faster against aligned addresses.*/
7343                         code = (guint8*)ALIGN_TO (code, 8);
7344                         memset (orig_code, 0, code - orig_code);
7345
7346                         pos = cfg->native_code + patch_info->ip.i;
7347
7348                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7349                         if (IS_REX (pos [1]))
7350                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7351                         else
7352                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7353
7354                         *(gpointer*)code = (gpointer)patch_info->data.target;
7355                         code += sizeof (gpointer);
7356
7357                         remove = TRUE;
7358                         break;
7359                 }
7360                 default:
7361                         break;
7362                 }
7363
7364                 if (remove) {
7365                         if (patch_info == cfg->patch_info)
7366                                 cfg->patch_info = patch_info->next;
7367                         else {
7368                                 MonoJumpInfo *tmp;
7369
7370                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7371                                         ;
7372                                 tmp->next = patch_info->next;
7373                         }
7374                 }
7375                 g_assert (code < cfg->native_code + cfg->code_size);
7376         }
7377
7378         cfg->code_len = code - cfg->native_code;
7379
7380         g_assert (cfg->code_len < cfg->code_size);
7381
7382 }
7383
7384 #endif /* DISABLE_JIT */
7385
7386 void*
7387 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7388 {
7389         guchar *code = (guchar *)p;
7390         MonoMethodSignature *sig;
7391         MonoInst *inst;
7392         int i, n, stack_area = 0;
7393
7394         /* Keep this in sync with mono_arch_get_argument_info */
7395
7396         if (enable_arguments) {
7397                 /* Allocate a new area on the stack and save arguments there */
7398                 sig = mono_method_signature (cfg->method);
7399
7400                 n = sig->param_count + sig->hasthis;
7401
7402                 stack_area = ALIGN_TO (n * 8, 16);
7403
7404                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7405
7406                 for (i = 0; i < n; ++i) {
7407                         inst = cfg->args [i];
7408
7409                         if (inst->opcode == OP_REGVAR)
7410                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7411                         else {
7412                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7413                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7414                         }
7415                 }
7416         }
7417
7418         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7419         amd64_set_reg_template (code, AMD64_ARG_REG1);
7420         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7421         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7422
7423         if (enable_arguments)
7424                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7425
7426         return code;
7427 }
7428
7429 enum {
7430         SAVE_NONE,
7431         SAVE_STRUCT,
7432         SAVE_EAX,
7433         SAVE_EAX_EDX,
7434         SAVE_XMM
7435 };
7436
7437 void*
7438 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7439 {
7440         guchar *code = (guchar *)p;
7441         int save_mode = SAVE_NONE;
7442         MonoMethod *method = cfg->method;
7443         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7444         int i;
7445
7446         switch (ret_type->type) {
7447         case MONO_TYPE_VOID:
7448                 /* special case string .ctor icall */
7449                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7450                         save_mode = SAVE_EAX;
7451                 else
7452                         save_mode = SAVE_NONE;
7453                 break;
7454         case MONO_TYPE_I8:
7455         case MONO_TYPE_U8:
7456                 save_mode = SAVE_EAX;
7457                 break;
7458         case MONO_TYPE_R4:
7459         case MONO_TYPE_R8:
7460                 save_mode = SAVE_XMM;
7461                 break;
7462         case MONO_TYPE_GENERICINST:
7463                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7464                         save_mode = SAVE_EAX;
7465                         break;
7466                 }
7467                 /* Fall through */
7468         case MONO_TYPE_VALUETYPE:
7469                 save_mode = SAVE_STRUCT;
7470                 break;
7471         default:
7472                 save_mode = SAVE_EAX;
7473                 break;
7474         }
7475
7476         /* Save the result and copy it into the proper argument register */
7477         switch (save_mode) {
7478         case SAVE_EAX:
7479                 amd64_push_reg (code, AMD64_RAX);
7480                 /* Align stack */
7481                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7482                 if (enable_arguments)
7483                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7484                 break;
7485         case SAVE_STRUCT:
7486                 /* FIXME: */
7487                 if (enable_arguments)
7488                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7489                 break;
7490         case SAVE_XMM:
7491                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7492                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7493                 /* Align stack */
7494                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7495                 /*
7496                  * The result is already in the proper argument register so no copying
7497                  * needed.
7498                  */
7499                 break;
7500         case SAVE_NONE:
7501                 break;
7502         default:
7503                 g_assert_not_reached ();
7504         }
7505
7506         /* Set %al since this is a varargs call */
7507         if (save_mode == SAVE_XMM)
7508                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7509         else
7510                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7511
7512         if (preserve_argument_registers) {
7513                 for (i = 0; i < PARAM_REGS; ++i)
7514                         amd64_push_reg (code, param_regs [i]);
7515         }
7516
7517         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7518         amd64_set_reg_template (code, AMD64_ARG_REG1);
7519         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7520
7521         if (preserve_argument_registers) {
7522                 for (i = PARAM_REGS - 1; i >= 0; --i)
7523                         amd64_pop_reg (code, param_regs [i]);
7524         }
7525
7526         /* Restore result */
7527         switch (save_mode) {
7528         case SAVE_EAX:
7529                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7530                 amd64_pop_reg (code, AMD64_RAX);
7531                 break;
7532         case SAVE_STRUCT:
7533                 /* FIXME: */
7534                 break;
7535         case SAVE_XMM:
7536                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7537                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7538                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7539                 break;
7540         case SAVE_NONE:
7541                 break;
7542         default:
7543                 g_assert_not_reached ();
7544         }
7545
7546         return code;
7547 }
7548
7549 void
7550 mono_arch_flush_icache (guint8 *code, gint size)
7551 {
7552         /* Not needed */
7553 }
7554
7555 void
7556 mono_arch_flush_register_windows (void)
7557 {
7558 }
7559
7560 gboolean
7561 mono_arch_is_inst_imm (gint64 imm)
7562 {
7563         return amd64_use_imm32 (imm);
7564 }
7565
7566 /*
7567  * Determine whenever the trap whose info is in SIGINFO is caused by
7568  * integer overflow.
7569  */
7570 gboolean
7571 mono_arch_is_int_overflow (void *sigctx, void *info)
7572 {
7573         MonoContext ctx;
7574         guint8* rip;
7575         int reg;
7576         gint64 value;
7577
7578         mono_sigctx_to_monoctx (sigctx, &ctx);
7579
7580         rip = (guint8*)ctx.gregs [AMD64_RIP];
7581
7582         if (IS_REX (rip [0])) {
7583                 reg = amd64_rex_b (rip [0]);
7584                 rip ++;
7585         }
7586         else
7587                 reg = 0;
7588
7589         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7590                 /* idiv REG */
7591                 reg += x86_modrm_rm (rip [1]);
7592
7593                 value = ctx.gregs [reg];
7594
7595                 if (value == -1)
7596                         return TRUE;
7597         }
7598
7599         return FALSE;
7600 }
7601
7602 guint32
7603 mono_arch_get_patch_offset (guint8 *code)
7604 {
7605         return 3;
7606 }
7607
7608 /**
7609  * mono_breakpoint_clean_code:
7610  *
7611  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7612  * breakpoints in the original code, they are removed in the copy.
7613  *
7614  * Returns TRUE if no sw breakpoint was present.
7615  */
7616 gboolean
7617 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7618 {
7619         /*
7620          * If method_start is non-NULL we need to perform bound checks, since we access memory
7621          * at code - offset we could go before the start of the method and end up in a different
7622          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7623          * instead.
7624          */
7625         if (!method_start || code - offset >= method_start) {
7626                 memcpy (buf, code - offset, size);
7627         } else {
7628                 int diff = code - method_start;
7629                 memset (buf, 0, size);
7630                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7631         }
7632         return TRUE;
7633 }
7634
7635 int
7636 mono_arch_get_this_arg_reg (guint8 *code)
7637 {
7638         return AMD64_ARG_REG1;
7639 }
7640
7641 gpointer
7642 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7643 {
7644         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7645 }
7646
7647 #define MAX_ARCH_DELEGATE_PARAMS 10
7648
7649 static gpointer
7650 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7651 {
7652         guint8 *code, *start;
7653         GSList *unwind_ops = NULL;
7654         int i;
7655
7656         unwind_ops = mono_arch_get_cie_program ();
7657
7658         if (has_target) {
7659                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7660
7661                 /* Replace the this argument with the target */
7662                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7663                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7664                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7665
7666                 g_assert ((code - start) < 64);
7667         } else {
7668                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7669
7670                 if (param_count == 0) {
7671                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7672                 } else {
7673                         /* We have to shift the arguments left */
7674                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7675                         for (i = 0; i < param_count; ++i) {
7676 #ifdef TARGET_WIN32
7677                                 if (i < 3)
7678                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7679                                 else
7680                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7681 #else
7682                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7683 #endif
7684                         }
7685
7686                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7687                 }
7688                 g_assert ((code - start) < 64);
7689         }
7690
7691         mono_arch_flush_icache (start, code - start);
7692
7693         if (has_target) {
7694                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7695         } else {
7696                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7697                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7698                 g_free (name);
7699         }
7700
7701         if (mono_jit_map_is_enabled ()) {
7702                 char *buff;
7703                 if (has_target)
7704                         buff = (char*)"delegate_invoke_has_target";
7705                 else
7706                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7707                 mono_emit_jit_tramp (start, code - start, buff);
7708                 if (!has_target)
7709                         g_free (buff);
7710         }
7711         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7712
7713         return start;
7714 }
7715
7716 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7717
7718 static gpointer
7719 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7720 {
7721         guint8 *code, *start;
7722         int size = 20;
7723         char *tramp_name;
7724         GSList *unwind_ops;
7725
7726         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7727                 return NULL;
7728
7729         start = code = (guint8 *)mono_global_codeman_reserve (size);
7730
7731         unwind_ops = mono_arch_get_cie_program ();
7732
7733         /* Replace the this argument with the target */
7734         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7735         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7736
7737         if (load_imt_reg) {
7738                 /* Load the IMT reg */
7739                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7740         }
7741
7742         /* Load the vtable */
7743         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7744         amd64_jump_membase (code, AMD64_RAX, offset);
7745         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7746
7747         if (load_imt_reg)
7748                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7749         else
7750                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7751         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7752         g_free (tramp_name);
7753
7754         return start;
7755 }
7756
7757 /*
7758  * mono_arch_get_delegate_invoke_impls:
7759  *
7760  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7761  * trampolines.
7762  */
7763 GSList*
7764 mono_arch_get_delegate_invoke_impls (void)
7765 {
7766         GSList *res = NULL;
7767         MonoTrampInfo *info;
7768         int i;
7769
7770         get_delegate_invoke_impl (&info, TRUE, 0);
7771         res = g_slist_prepend (res, info);
7772
7773         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7774                 get_delegate_invoke_impl (&info, FALSE, i);
7775                 res = g_slist_prepend (res, info);
7776         }
7777
7778         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7779                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7780                 res = g_slist_prepend (res, info);
7781
7782                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7783                 res = g_slist_prepend (res, info);
7784         }
7785
7786         return res;
7787 }
7788
7789 gpointer
7790 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7791 {
7792         guint8 *code, *start;
7793         int i;
7794
7795         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7796                 return NULL;
7797
7798         /* FIXME: Support more cases */
7799         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7800                 return NULL;
7801
7802         if (has_target) {
7803                 static guint8* cached = NULL;
7804
7805                 if (cached)
7806                         return cached;
7807
7808                 if (mono_aot_only) {
7809                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7810                 } else {
7811                         MonoTrampInfo *info;
7812                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7813                         mono_tramp_info_register (info, NULL);
7814                 }
7815
7816                 mono_memory_barrier ();
7817
7818                 cached = start;
7819         } else {
7820                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7821                 for (i = 0; i < sig->param_count; ++i)
7822                         if (!mono_is_regsize_var (sig->params [i]))
7823                                 return NULL;
7824                 if (sig->param_count > 4)
7825                         return NULL;
7826
7827                 code = cache [sig->param_count];
7828                 if (code)
7829                         return code;
7830
7831                 if (mono_aot_only) {
7832                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7833                         start = (guint8 *)mono_aot_get_trampoline (name);
7834                         g_free (name);
7835                 } else {
7836                         MonoTrampInfo *info;
7837                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7838                         mono_tramp_info_register (info, NULL);
7839                 }
7840
7841                 mono_memory_barrier ();
7842
7843                 cache [sig->param_count] = start;
7844         }
7845
7846         return start;
7847 }
7848
7849 gpointer
7850 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7851 {
7852         MonoTrampInfo *info;
7853         gpointer code;
7854
7855         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7856         if (code)
7857                 mono_tramp_info_register (info, NULL);
7858         return code;
7859 }
7860
7861 void
7862 mono_arch_finish_init (void)
7863 {
7864 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7865         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7866 #endif
7867 }
7868
7869 void
7870 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7871 {
7872 }
7873
7874 #define CMP_SIZE (6 + 1)
7875 #define CMP_REG_REG_SIZE (4 + 1)
7876 #define BR_SMALL_SIZE 2
7877 #define BR_LARGE_SIZE 6
7878 #define MOV_REG_IMM_SIZE 10
7879 #define MOV_REG_IMM_32BIT_SIZE 6
7880 #define JUMP_REG_SIZE (2 + 1)
7881
7882 static int
7883 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7884 {
7885         int i, distance = 0;
7886         for (i = start; i < target; ++i)
7887                 distance += imt_entries [i]->chunk_size;
7888         return distance;
7889 }
7890
7891 /*
7892  * LOCKING: called with the domain lock held
7893  */
7894 gpointer
7895 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7896         gpointer fail_tramp)
7897 {
7898         int i;
7899         int size = 0;
7900         guint8 *code, *start;
7901         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7902         GSList *unwind_ops;
7903
7904         for (i = 0; i < count; ++i) {
7905                 MonoIMTCheckItem *item = imt_entries [i];
7906                 if (item->is_equals) {
7907                         if (item->check_target_idx) {
7908                                 if (!item->compare_done) {
7909                                         if (amd64_use_imm32 ((gint64)item->key))
7910                                                 item->chunk_size += CMP_SIZE;
7911                                         else
7912                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7913                                 }
7914                                 if (item->has_target_code) {
7915                                         item->chunk_size += MOV_REG_IMM_SIZE;
7916                                 } else {
7917                                         if (vtable_is_32bit)
7918                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7919                                         else
7920                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7921                                 }
7922                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7923                         } else {
7924                                 if (fail_tramp) {
7925                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7926                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7927                                 } else {
7928                                         if (vtable_is_32bit)
7929                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7930                                         else
7931                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7932                                         item->chunk_size += JUMP_REG_SIZE;
7933                                         /* with assert below:
7934                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7935                                          */
7936                                 }
7937                         }
7938                 } else {
7939                         if (amd64_use_imm32 ((gint64)item->key))
7940                                 item->chunk_size += CMP_SIZE;
7941                         else
7942                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7943                         item->chunk_size += BR_LARGE_SIZE;
7944                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7945                 }
7946                 size += item->chunk_size;
7947         }
7948         if (fail_tramp)
7949                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
7950         else
7951                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7952         start = code;
7953
7954         unwind_ops = mono_arch_get_cie_program ();
7955
7956         for (i = 0; i < count; ++i) {
7957                 MonoIMTCheckItem *item = imt_entries [i];
7958                 item->code_target = code;
7959                 if (item->is_equals) {
7960                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7961
7962                         if (item->check_target_idx || fail_case) {
7963                                 if (!item->compare_done || fail_case) {
7964                                         if (amd64_use_imm32 ((gint64)item->key))
7965                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7966                                         else {
7967                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7968                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7969                                         }
7970                                 }
7971                                 item->jmp_code = code;
7972                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7973                                 if (item->has_target_code) {
7974                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7975                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7976                                 } else {
7977                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7978                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7979                                 }
7980
7981                                 if (fail_case) {
7982                                         amd64_patch (item->jmp_code, code);
7983                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7984                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7985                                         item->jmp_code = NULL;
7986                                 }
7987                         } else {
7988                                 /* enable the commented code to assert on wrong method */
7989 #if 0
7990                                 if (amd64_is_imm32 (item->key))
7991                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7992                                 else {
7993                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7994                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7995                                 }
7996                                 item->jmp_code = code;
7997                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7998                                 /* See the comment below about R10 */
7999                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8000                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8001                                 amd64_patch (item->jmp_code, code);
8002                                 amd64_breakpoint (code);
8003                                 item->jmp_code = NULL;
8004 #else
8005                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8006                                    needs to be preserved.  R10 needs
8007                                    to be preserved for calls which
8008                                    require a runtime generic context,
8009                                    but interface calls don't. */
8010                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8011                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8012 #endif
8013                         }
8014                 } else {
8015                         if (amd64_use_imm32 ((gint64)item->key))
8016                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8017                         else {
8018                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8019                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8020                         }
8021                         item->jmp_code = code;
8022                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8023                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8024                         else
8025                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8026                 }
8027                 g_assert (code - item->code_target <= item->chunk_size);
8028         }
8029         /* patch the branches to get to the target items */
8030         for (i = 0; i < count; ++i) {
8031                 MonoIMTCheckItem *item = imt_entries [i];
8032                 if (item->jmp_code) {
8033                         if (item->check_target_idx) {
8034                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8035                         }
8036                 }
8037         }
8038
8039         if (!fail_tramp)
8040                 mono_stats.imt_thunks_size += code - start;
8041         g_assert (code - start <= size);
8042
8043         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8044
8045         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8046
8047         return start;
8048 }
8049
8050 MonoMethod*
8051 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8052 {
8053         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8054 }
8055
8056 MonoVTable*
8057 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8058 {
8059         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8060 }
8061
8062 GSList*
8063 mono_arch_get_cie_program (void)
8064 {
8065         GSList *l = NULL;
8066
8067         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8068         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8069
8070         return l;
8071 }
8072
8073 #ifndef DISABLE_JIT
8074
8075 MonoInst*
8076 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8077 {
8078         MonoInst *ins = NULL;
8079         int opcode = 0;
8080
8081         if (cmethod->klass == mono_defaults.math_class) {
8082                 if (strcmp (cmethod->name, "Sin") == 0) {
8083                         opcode = OP_SIN;
8084                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8085                         opcode = OP_COS;
8086                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8087                         opcode = OP_SQRT;
8088                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8089                         opcode = OP_ABS;
8090                 }
8091
8092                 if (opcode && fsig->param_count == 1) {
8093                         MONO_INST_NEW (cfg, ins, opcode);
8094                         ins->type = STACK_R8;
8095                         ins->dreg = mono_alloc_freg (cfg);
8096                         ins->sreg1 = args [0]->dreg;
8097                         MONO_ADD_INS (cfg->cbb, ins);
8098                 }
8099
8100                 opcode = 0;
8101                 if (cfg->opt & MONO_OPT_CMOV) {
8102                         if (strcmp (cmethod->name, "Min") == 0) {
8103                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8104                                         opcode = OP_IMIN;
8105                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8106                                         opcode = OP_IMIN_UN;
8107                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8108                                         opcode = OP_LMIN;
8109                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8110                                         opcode = OP_LMIN_UN;
8111                         } else if (strcmp (cmethod->name, "Max") == 0) {
8112                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8113                                         opcode = OP_IMAX;
8114                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8115                                         opcode = OP_IMAX_UN;
8116                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8117                                         opcode = OP_LMAX;
8118                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8119                                         opcode = OP_LMAX_UN;
8120                         }
8121                 }
8122
8123                 if (opcode && fsig->param_count == 2) {
8124                         MONO_INST_NEW (cfg, ins, opcode);
8125                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8126                         ins->dreg = mono_alloc_ireg (cfg);
8127                         ins->sreg1 = args [0]->dreg;
8128                         ins->sreg2 = args [1]->dreg;
8129                         MONO_ADD_INS (cfg->cbb, ins);
8130                 }
8131
8132 #if 0
8133                 /* OP_FREM is not IEEE compatible */
8134                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8135                         MONO_INST_NEW (cfg, ins, OP_FREM);
8136                         ins->inst_i0 = args [0];
8137                         ins->inst_i1 = args [1];
8138                 }
8139 #endif
8140         }
8141
8142         return ins;
8143 }
8144 #endif
8145
8146 gboolean
8147 mono_arch_print_tree (MonoInst *tree, int arity)
8148 {
8149         return 0;
8150 }
8151
8152 mgreg_t
8153 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8154 {
8155         return ctx->gregs [reg];
8156 }
8157
8158 void
8159 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8160 {
8161         ctx->gregs [reg] = val;
8162 }
8163
8164 gpointer
8165 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8166 {
8167         gpointer *sp, old_value;
8168         char *bp;
8169
8170         /*Load the spvar*/
8171         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8172         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8173
8174         old_value = *sp;
8175         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8176                 return old_value;
8177
8178         *sp = new_value;
8179
8180         return old_value;
8181 }
8182
8183 /*
8184  * mono_arch_emit_load_aotconst:
8185  *
8186  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8187  * TARGET from the mscorlib GOT in full-aot code.
8188  * On AMD64, the result is placed into R11.
8189  */
8190 guint8*
8191 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8192 {
8193         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8194         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8195
8196         return code;
8197 }
8198
8199 /*
8200  * mono_arch_get_trampolines:
8201  *
8202  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8203  * for AOT.
8204  */
8205 GSList *
8206 mono_arch_get_trampolines (gboolean aot)
8207 {
8208         return mono_amd64_get_exception_trampolines (aot);
8209 }
8210
8211 /* Soft Debug support */
8212 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8213
8214 /*
8215  * mono_arch_set_breakpoint:
8216  *
8217  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8218  * The location should contain code emitted by OP_SEQ_POINT.
8219  */
8220 void
8221 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8222 {
8223         guint8 *code = ip;
8224
8225         if (ji->from_aot) {
8226                 guint32 native_offset = ip - (guint8*)ji->code_start;
8227                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8228
8229                 g_assert (info->bp_addrs [native_offset] == 0);
8230                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8231         } else {
8232                 /* ip points to a mov r11, 0 */
8233                 g_assert (code [0] == 0x41);
8234                 g_assert (code [1] == 0xbb);
8235                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8236         }
8237 }
8238
8239 /*
8240  * mono_arch_clear_breakpoint:
8241  *
8242  *   Clear the breakpoint at IP.
8243  */
8244 void
8245 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8246 {
8247         guint8 *code = ip;
8248
8249         if (ji->from_aot) {
8250                 guint32 native_offset = ip - (guint8*)ji->code_start;
8251                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8252
8253                 info->bp_addrs [native_offset] = NULL;
8254         } else {
8255                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8256         }
8257 }
8258
8259 gboolean
8260 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8261 {
8262         /* We use soft breakpoints on amd64 */
8263         return FALSE;
8264 }
8265
8266 /*
8267  * mono_arch_skip_breakpoint:
8268  *
8269  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8270  * we resume, the instruction is not executed again.
8271  */
8272 void
8273 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8274 {
8275         g_assert_not_reached ();
8276 }
8277
8278 /*
8279  * mono_arch_start_single_stepping:
8280  *
8281  *   Start single stepping.
8282  */
8283 void
8284 mono_arch_start_single_stepping (void)
8285 {
8286         ss_trampoline = mini_get_single_step_trampoline ();
8287 }
8288
8289 /*
8290  * mono_arch_stop_single_stepping:
8291  *
8292  *   Stop single stepping.
8293  */
8294 void
8295 mono_arch_stop_single_stepping (void)
8296 {
8297         ss_trampoline = NULL;
8298 }
8299
8300 /*
8301  * mono_arch_is_single_step_event:
8302  *
8303  *   Return whenever the machine state in SIGCTX corresponds to a single
8304  * step event.
8305  */
8306 gboolean
8307 mono_arch_is_single_step_event (void *info, void *sigctx)
8308 {
8309         /* We use soft breakpoints on amd64 */
8310         return FALSE;
8311 }
8312
8313 /*
8314  * mono_arch_skip_single_step:
8315  *
8316  *   Modify CTX so the ip is placed after the single step trigger instruction,
8317  * we resume, the instruction is not executed again.
8318  */
8319 void
8320 mono_arch_skip_single_step (MonoContext *ctx)
8321 {
8322         g_assert_not_reached ();
8323 }
8324
8325 /*
8326  * mono_arch_create_seq_point_info:
8327  *
8328  *   Return a pointer to a data structure which is used by the sequence
8329  * point implementation in AOTed code.
8330  */
8331 gpointer
8332 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8333 {
8334         SeqPointInfo *info;
8335         MonoJitInfo *ji;
8336
8337         // FIXME: Add a free function
8338
8339         mono_domain_lock (domain);
8340         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8341                                                                 code);
8342         mono_domain_unlock (domain);
8343
8344         if (!info) {
8345                 ji = mono_jit_info_table_find (domain, (char*)code);
8346                 g_assert (ji);
8347
8348                 // FIXME: Optimize the size
8349                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8350
8351                 info->ss_tramp_addr = &ss_trampoline;
8352
8353                 mono_domain_lock (domain);
8354                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8355                                                          code, info);
8356                 mono_domain_unlock (domain);
8357         }
8358
8359         return info;
8360 }
8361
8362 void
8363 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8364 {
8365         ext->lmf.previous_lmf = prev_lmf;
8366         /* Mark that this is a MonoLMFExt */
8367         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8368         ext->lmf.rsp = (gssize)ext;
8369 }
8370
8371 #endif
8372
8373 gboolean
8374 mono_arch_opcode_supported (int opcode)
8375 {
8376         switch (opcode) {
8377         case OP_ATOMIC_ADD_I4:
8378         case OP_ATOMIC_ADD_I8:
8379         case OP_ATOMIC_EXCHANGE_I4:
8380         case OP_ATOMIC_EXCHANGE_I8:
8381         case OP_ATOMIC_CAS_I4:
8382         case OP_ATOMIC_CAS_I8:
8383         case OP_ATOMIC_LOAD_I1:
8384         case OP_ATOMIC_LOAD_I2:
8385         case OP_ATOMIC_LOAD_I4:
8386         case OP_ATOMIC_LOAD_I8:
8387         case OP_ATOMIC_LOAD_U1:
8388         case OP_ATOMIC_LOAD_U2:
8389         case OP_ATOMIC_LOAD_U4:
8390         case OP_ATOMIC_LOAD_U8:
8391         case OP_ATOMIC_LOAD_R4:
8392         case OP_ATOMIC_LOAD_R8:
8393         case OP_ATOMIC_STORE_I1:
8394         case OP_ATOMIC_STORE_I2:
8395         case OP_ATOMIC_STORE_I4:
8396         case OP_ATOMIC_STORE_I8:
8397         case OP_ATOMIC_STORE_U1:
8398         case OP_ATOMIC_STORE_U2:
8399         case OP_ATOMIC_STORE_U4:
8400         case OP_ATOMIC_STORE_U8:
8401         case OP_ATOMIC_STORE_R4:
8402         case OP_ATOMIC_STORE_R8:
8403                 return TRUE;
8404         default:
8405                 return FALSE;
8406         }
8407 }
8408
8409 CallInfo*
8410 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8411 {
8412         return get_call_info (mp, sig);
8413 }