mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 #ifdef __native_client_codegen__
 178
 179 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 180 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 181 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 182 /* We only want to force bundle alignment for the top level instruction,    */
 183 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 184 static MonoNativeTlsKey nacl_instruction_depth;
 185
 186 static MonoNativeTlsKey nacl_rex_tag;
 187 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 188
 189 void
 190 amd64_nacl_clear_legacy_prefix_tag ()
 191 {
 192         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 193 }
 194
 195 void
 196 amd64_nacl_tag_legacy_prefix (guint8* code)
 197 {
 198         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 199                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 200 }
 201
 202 void
 203 amd64_nacl_tag_rex (guint8* code)
 204 {
 205         mono_native_tls_set_value (nacl_rex_tag, code);
 206 }
 207
 208 guint8*
 209 amd64_nacl_get_legacy_prefix_tag ()
 210 {
 211         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 212 }
 213
 214 guint8*
 215 amd64_nacl_get_rex_tag ()
 216 {
 217         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 218 }
 219
 220 /* Increment the instruction "depth" described above */
 221 void
 222 amd64_nacl_instruction_pre ()
 223 {
 224         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 225         depth++;
 226         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 227 }
 228
 229 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 230 /* alignment if depth == 0 (top level instruction)                          */
 231 /* IN: start, end    pointers to instruction beginning and end              */
 232 /* OUT: start, end   pointers to beginning and end after possible alignment */
 233 /* GLOBALS: nacl_instruction_depth     defined above                        */
 234 void
 235 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 236 {
 237         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 238         depth--;
 239         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 240
 241         g_assert ( depth >= 0 );
 242         if (depth == 0) {
 243                 uintptr_t space_in_block;
 244                 uintptr_t instlen;
 245                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 246                 /* if legacy prefix is present, and if it was emitted before */
 247                 /* the start of the instruction sequence, adjust the start   */
 248                 if (prefix != NULL && prefix < *start) {
 249                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 250                         *start = prefix;
 251                 }
 252                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 253                 instlen = (uintptr_t)(*end - *start);
 254                 /* Only check for instructions which are less than        */
 255                 /* kNaClAlignment. The only instructions that should ever */
 256                 /* be that long are call sequences, which are already     */
 257                 /* padded out to align the return to the next bundle.     */
 258                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 259                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 260                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 261                         const size_t length = (size_t)((*end)-(*start));
 262                         g_assert (length < MAX_NACL_INST_LENGTH);
 263
 264                         memcpy (copy_of_instruction, *start, length);
 265                         *start = mono_arch_nacl_pad (*start, space_in_block);
 266                         memcpy (*start, copy_of_instruction, length);
 267                         *end = *start + length;
 268                 }
 269                 amd64_nacl_clear_legacy_prefix_tag ();
 270                 amd64_nacl_tag_rex (NULL);
 271         }
 272 }
 273
 274 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 275 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 276 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 277 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 278 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 279 /* IN:      code                                                            */
 280 /*             pointer to current instruction stream (in the                */
 281 /*             middle of an instruction, after opcode is emitted)           */
 282 /*          basereg/offset/dreg                                             */
 283 /*             operands of normal membase address                           */
 284 /* OUT:     code                                                            */
 285 /*             pointer to the end of the membase/memindex emit              */
 286 /* GLOBALS: nacl_rex_tag                                                    */
 287 /*             position in instruction stream that rex prefix was emitted   */
 288 /*          nacl_legacy_prefix_tag                                          */
 289 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 290 void
 291 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 292 {
 293         gint8 true_basereg = basereg;
 294
 295         /* Cache these values, they might change  */
 296         /* as new instructions are emitted below. */
 297         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 298         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 299
 300         /* 'basereg' is given masked to 0x7 at this point, so check */
 301         /* the rex prefix to see if this is an extended register.   */
 302         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 303                 true_basereg |= 0x8;
 304         }
 305
 306 #define X86_LEA_OPCODE (0x8D)
 307
 308         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 309                 guint8* old_instruction_start;
 310
 311                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 312                 /* 32-bits of the old base register (new index register)     */
 313                 guint8 buf[32];
 314                 guint8* buf_ptr = buf;
 315                 size_t insert_len;
 316
 317                 g_assert (rex_tag != NULL);
 318
 319                 if (IS_REX(*rex_tag)) {
 320                         /* The old rex.B should be the new rex.X */
 321                         if (*rex_tag & AMD64_REX_B) {
 322                                 *rex_tag |= AMD64_REX_X;
 323                         }
 324                         /* Since our new base is %r15 set rex.B */
 325                         *rex_tag |= AMD64_REX_B;
 326                 } else {
 327                         /* Shift the instruction by one byte  */
 328                         /* so we can insert a rex prefix      */
 329                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 330                         *code += 1;
 331                         /* New rex prefix only needs rex.B for %r15 base */
 332                         *rex_tag = AMD64_REX(AMD64_REX_B);
 333                 }
 334
 335                 if (legacy_prefix_tag) {
 336                         old_instruction_start = legacy_prefix_tag;
 337                 } else {
 338                         old_instruction_start = rex_tag;
 339                 }
 340
 341                 /* Clears the upper 32-bits of the previous base register */
 342                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 343                 insert_len = buf_ptr - buf;
 344
 345                 /* Move the old instruction forward to make */
 346                 /* room for 'mov' stored in 'buf_ptr'       */
 347                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 348                 *code += insert_len;
 349                 memcpy (old_instruction_start, buf, insert_len);
 350
 351                 /* Sandboxed replacement for the normal membase_emit */
 352                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 353
 354         } else {
 355                 /* Normal default behavior, emit membase memory location */
 356                 x86_membase_emit_body (*code, dreg, basereg, offset);
 357         }
 358 }
 359
 360
 361 static inline unsigned char*
 362 amd64_skip_nops (unsigned char* code)
 363 {
 364         guint8 in_nop;
 365         do {
 366                 in_nop = 0;
 367                 if (   code[0] == 0x90) {
 368                         in_nop = 1;
 369                         code += 1;
 370                 }
 371                 if (   code[0] == 0x66 && code[1] == 0x90) {
 372                         in_nop = 1;
 373                         code += 2;
 374                 }
 375                 if (code[0] == 0x0f && code[1] == 0x1f
 376                  && code[2] == 0x00) {
 377                         in_nop = 1;
 378                         code += 3;
 379                 }
 380                 if (code[0] == 0x0f && code[1] == 0x1f
 381                  && code[2] == 0x40 && code[3] == 0x00) {
 382                         in_nop = 1;
 383                         code += 4;
 384                 }
 385                 if (code[0] == 0x0f && code[1] == 0x1f
 386                  && code[2] == 0x44 && code[3] == 0x00
 387                  && code[4] == 0x00) {
 388                         in_nop = 1;
 389                         code += 5;
 390                 }
 391                 if (code[0] == 0x66 && code[1] == 0x0f
 392                  && code[2] == 0x1f && code[3] == 0x44
 393                  && code[4] == 0x00 && code[5] == 0x00) {
 394                         in_nop = 1;
 395                         code += 6;
 396                 }
 397                 if (code[0] == 0x0f && code[1] == 0x1f
 398                  && code[2] == 0x80 && code[3] == 0x00
 399                  && code[4] == 0x00 && code[5] == 0x00
 400                  && code[6] == 0x00) {
 401                         in_nop = 1;
 402                         code += 7;
 403                 }
 404                 if (code[0] == 0x0f && code[1] == 0x1f
 405                  && code[2] == 0x84 && code[3] == 0x00
 406                  && code[4] == 0x00 && code[5] == 0x00
 407                  && code[6] == 0x00 && code[7] == 0x00) {
 408                         in_nop = 1;
 409                         code += 8;
 410                 }
 411         } while ( in_nop );
 412         return code;
 413 }
 414
 415 guint8*
 416 mono_arch_nacl_skip_nops (guint8* code)
 417 {
 418   return amd64_skip_nops(code);
 419 }
 420
 421 #endif /*__native_client_codegen__*/
 422
 423 static void
 424 amd64_patch (unsigned char* code, gpointer target)
 425 {
 426         guint8 rex = 0;
 427
 428 #ifdef __native_client_codegen__
 429         code = amd64_skip_nops (code);
 430 #endif
 431 #if defined(__native_client_codegen__) && defined(__native_client__)
 432         if (nacl_is_code_address (code)) {
 433                 /* For tail calls, code is patched after being installed */
 434                 /* but not through the normal "patch callsite" method.   */
 435                 unsigned char buf[kNaClAlignment];
 436                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 437                 int ret;
 438                 memcpy (buf, aligned_code, kNaClAlignment);
 439                 /* Patch a temp buffer of bundle size, */
 440                 /* then install to actual location.    */
 441                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 442                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 443                 g_assert (ret == 0);
 444                 return;
 445         }
 446         target = nacl_modify_patch_target (target);
 447 #endif
 448
 449         /* Skip REX */
 450         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 451                 rex = code [0];
 452                 code += 1;
 453         }
 454
 455         if ((code [0] & 0xf8) == 0xb8) {
 456                 /* amd64_set_reg_template */
 457                 *(guint64*)(code + 1) = (guint64)target;
 458         }
 459         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 460                 /* mov 0(%rip), %dreg */
 461                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 462         }
 463         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 464                 /* call *<OFFSET>(%rip) */
 465                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 466         }
 467         else if (code [0] == 0xe8) {
 468                 /* call <DISP> */
 469                 gint64 disp = (guint8*)target - (guint8*)code;
 470                 g_assert (amd64_is_imm32 (disp));
 471                 x86_patch (code, (unsigned char*)target);
 472         }
 473         else
 474                 x86_patch (code, (unsigned char*)target);
 475 }
 476
 477 void
 478 mono_amd64_patch (unsigned char* code, gpointer target)
 479 {
 480         amd64_patch (code, target);
 481 }
 482
 483 #define DEBUG(a) if (cfg->verbose_level > 1) a
 484
 485 static void inline
 486 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 487 {
 488     ainfo->offset = *stack_size;
 489
 490     if (*gr >= PARAM_REGS) {
 491                 ainfo->storage = ArgOnStack;
 492                 ainfo->arg_size = sizeof (mgreg_t);
 493                 /* Since the same stack slot size is used for all arg */
 494                 /*  types, it needs to be big enough to hold them all */
 495                 (*stack_size) += sizeof(mgreg_t);
 496     }
 497     else {
 498                 ainfo->storage = ArgInIReg;
 499                 ainfo->reg = param_regs [*gr];
 500                 (*gr) ++;
 501     }
 502 }
 503
 504 static void inline
 505 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 506 {
 507     ainfo->offset = *stack_size;
 508
 509     if (*gr >= FLOAT_PARAM_REGS) {
 510                 ainfo->storage = ArgOnStack;
 511                 ainfo->arg_size = sizeof (mgreg_t);
 512                 /* Since the same stack slot size is used for both float */
 513                 /*  types, it needs to be big enough to hold them both */
 514                 (*stack_size) += sizeof(mgreg_t);
 515     }
 516     else {
 517                 /* A double register */
 518                 if (is_double)
 519                         ainfo->storage = ArgInDoubleSSEReg;
 520                 else
 521                         ainfo->storage = ArgInFloatSSEReg;
 522                 ainfo->reg = *gr;
 523                 (*gr) += 1;
 524     }
 525 }
 526
 527 typedef enum ArgumentClass {
 528         ARG_CLASS_NO_CLASS,
 529         ARG_CLASS_MEMORY,
 530         ARG_CLASS_INTEGER,
 531         ARG_CLASS_SSE
 532 } ArgumentClass;
 533
 534 static ArgumentClass
 535 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 536 {
 537         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 538         MonoType *ptype;
 539
 540         ptype = mini_get_underlying_type (type);
 541         switch (ptype->type) {
 542         case MONO_TYPE_I1:
 543         case MONO_TYPE_U1:
 544         case MONO_TYPE_I2:
 545         case MONO_TYPE_U2:
 546         case MONO_TYPE_I4:
 547         case MONO_TYPE_U4:
 548         case MONO_TYPE_I:
 549         case MONO_TYPE_U:
 550         case MONO_TYPE_STRING:
 551         case MONO_TYPE_OBJECT:
 552         case MONO_TYPE_CLASS:
 553         case MONO_TYPE_SZARRAY:
 554         case MONO_TYPE_PTR:
 555         case MONO_TYPE_FNPTR:
 556         case MONO_TYPE_ARRAY:
 557         case MONO_TYPE_I8:
 558         case MONO_TYPE_U8:
 559                 class2 = ARG_CLASS_INTEGER;
 560                 break;
 561         case MONO_TYPE_R4:
 562         case MONO_TYPE_R8:
 563 #ifdef TARGET_WIN32
 564                 class2 = ARG_CLASS_INTEGER;
 565 #else
 566                 class2 = ARG_CLASS_SSE;
 567 #endif
 568                 break;
 569
 570         case MONO_TYPE_TYPEDBYREF:
 571                 g_assert_not_reached ();
 572
 573         case MONO_TYPE_GENERICINST:
 574                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 575                         class2 = ARG_CLASS_INTEGER;
 576                         break;
 577                 }
 578                 /* fall through */
 579         case MONO_TYPE_VALUETYPE: {
 580                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 581                 int i;
 582
 583                 for (i = 0; i < info->num_fields; ++i) {
 584                         class2 = class1;
 585                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 586                 }
 587                 break;
 588         }
 589         default:
 590                 g_assert_not_reached ();
 591         }
 592
 593         /* Merge */
 594         if (class1 == class2)
 595                 ;
 596         else if (class1 == ARG_CLASS_NO_CLASS)
 597                 class1 = class2;
 598         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 599                 class1 = ARG_CLASS_MEMORY;
 600         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 601                 class1 = ARG_CLASS_INTEGER;
 602         else
 603                 class1 = ARG_CLASS_SSE;
 604
 605         return class1;
 606 }
 607 #ifdef __native_client_codegen__
 608
 609 /* Default alignment for Native Client is 32-byte. */
 610 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 611
 612 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 613 /* Check that alignment doesn't cross an alignment boundary.             */
 614 guint8*
 615 mono_arch_nacl_pad(guint8 *code, int pad)
 616 {
 617         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 618
 619         if (pad == 0) return code;
 620         /* assertion: alignment cannot cross a block boundary */
 621         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 622                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 623         while (pad >= kMaxPadding) {
 624                 amd64_padding (code, kMaxPadding);
 625                 pad -= kMaxPadding;
 626         }
 627         if (pad != 0) amd64_padding (code, pad);
 628         return code;
 629 }
 630 #endif
 631
 632 static int
 633 count_fields_nested (MonoClass *klass)
 634 {
 635         MonoMarshalType *info;
 636         int i, count;
 637
 638         info = mono_marshal_load_type_info (klass);
 639         g_assert(info);
 640         count = 0;
 641         for (i = 0; i < info->num_fields; ++i) {
 642                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 643                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 644                 else
 645                         count ++;
 646         }
 647         return count;
 648 }
 649
 650 static int
 651 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 652 {
 653         MonoMarshalType *info;
 654         int i;
 655
 656         info = mono_marshal_load_type_info (klass);
 657         g_assert(info);
 658         for (i = 0; i < info->num_fields; ++i) {
 659                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 660                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 661                 } else {
 662                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 663                         fields [index].offset += offset;
 664                         index ++;
 665                 }
 666         }
 667         return index;
 668 }
 669
 670 #ifdef TARGET_WIN32
 671 static void
 672 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 673                                          gboolean is_return,
 674                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 675 {
 676         guint32 size, i, nfields;
 677         guint32 argsize = 8;
 678         ArgumentClass arg_class;
 679         MonoMarshalType *info = NULL;
 680         MonoMarshalField *fields = NULL;
 681         MonoClass *klass;
 682         gboolean pass_on_stack = FALSE;
 683
 684         klass = mono_class_from_mono_type (type);
 685         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 686         if (!sig->pinvoke)
 687                 pass_on_stack = TRUE;
 688
 689         /* If this struct can't be split up naturally into 8-byte */
 690         /* chunks (registers), pass it on the stack.              */
 691         if (sig->pinvoke && !pass_on_stack) {
 692                 guint32 align;
 693                 guint32 field_size;
 694
 695                 info = mono_marshal_load_type_info (klass);
 696                 g_assert (info);
 697
 698                 /*
 699                  * Collect field information recursively to be able to
 700                  * handle nested structures.
 701                  */
 702                 nfields = count_fields_nested (klass);
 703                 fields = g_new0 (MonoMarshalField, nfields);
 704                 collect_field_info_nested (klass, fields, 0, 0);
 705
 706                 for (i = 0; i < nfields; ++i) {
 707                         field_size = mono_marshal_type_size (fields [i].field->type,
 708                                                            fields [i].mspec,
 709                                                            &align, TRUE, klass->unicode);
 710                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 711                                 pass_on_stack = TRUE;
 712                                 break;
 713                         }
 714                 }
 715         }
 716
 717         if (pass_on_stack) {
 718                 /* Allways pass in memory */
 719                 ainfo->offset = *stack_size;
 720                 *stack_size += ALIGN_TO (size, 8);
 721                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 722                 if (!is_return)
 723                         ainfo->arg_size = ALIGN_TO (size, 8);
 724
 725                 g_free (fields);
 726                 return;
 727         }
 728
 729         if (!sig->pinvoke) {
 730                 int n = mono_class_value_size (klass, NULL);
 731
 732                 argsize = n;
 733
 734                 if (n > 8)
 735                         arg_class = ARG_CLASS_MEMORY;
 736                 else
 737                         /* Always pass in 1 integer register */
 738                         arg_class = ARG_CLASS_INTEGER;
 739         } else {
 740                 g_assert (info);
 741
 742                 if (!fields) {
 743                         ainfo->storage = ArgValuetypeInReg;
 744                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 745                         return;
 746                 }
 747
 748                 switch (info->native_size) {
 749                 case 1: case 2: case 4: case 8:
 750                         break;
 751                 default:
 752                         if (is_return) {
 753                                 ainfo->storage = ArgValuetypeAddrInIReg;
 754                                 ainfo->offset = *stack_size;
 755                                 *stack_size += ALIGN_TO (info->native_size, 8);
 756                         }
 757                         else {
 758                                 ainfo->storage = ArgValuetypeAddrInIReg;
 759
 760                                 if (*gr < PARAM_REGS) {
 761                                         ainfo->pair_storage [0] = ArgInIReg;
 762                                         ainfo->pair_regs [0] = param_regs [*gr];
 763                                         (*gr) ++;
 764                                 }
 765                                 else {
 766                                         ainfo->pair_storage [0] = ArgOnStack;
 767                                         ainfo->offset = *stack_size;
 768                                         ainfo->arg_size = sizeof (mgreg_t);
 769                                         *stack_size += 8;
 770                                 }
 771                         }
 772
 773                         g_free (fields);
 774                         return;
 775                 }
 776
 777                 int size;
 778                 guint32 align;
 779                 ArgumentClass class1;
 780
 781                 if (nfields == 0)
 782                         class1 = ARG_CLASS_MEMORY;
 783                 else
 784                         class1 = ARG_CLASS_NO_CLASS;
 785                 for (i = 0; i < nfields; ++i) {
 786                         size = mono_marshal_type_size (fields [i].field->type,
 787                                                                                    fields [i].mspec,
 788                                                                                    &align, TRUE, klass->unicode);
 789                         /* How far into this quad this data extends.*/
 790                         /* (8 is size of quad) */
 791                         argsize = fields [i].offset + size;
 792
 793                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 794                 }
 795                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 796                 arg_class = class1;
 797         }
 798
 799         g_free (fields);
 800
 801         /* Allocate registers */
 802         {
 803                 int orig_gr = *gr;
 804                 int orig_fr = *fr;
 805
 806                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 807                         argsize ++;
 808
 809                 ainfo->storage = ArgValuetypeInReg;
 810                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 811                 ainfo->pair_size [0] = argsize;
 812                 ainfo->pair_size [1] = 0;
 813                 ainfo->nregs = 1;
 814                 switch (arg_class) {
 815                 case ARG_CLASS_INTEGER:
 816                         if (*gr >= PARAM_REGS)
 817                                 arg_class = ARG_CLASS_MEMORY;
 818                         else {
 819                                 ainfo->pair_storage [0] = ArgInIReg;
 820                                 if (is_return)
 821                                         ainfo->pair_regs [0] = return_regs [*gr];
 822                                 else
 823                                         ainfo->pair_regs [0] = param_regs [*gr];
 824                                 (*gr) ++;
 825                         }
 826                         break;
 827                 case ARG_CLASS_SSE:
 828                         if (*fr >= FLOAT_PARAM_REGS)
 829                                 arg_class = ARG_CLASS_MEMORY;
 830                         else {
 831                                 if (argsize <= 4)
 832                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 833                                 else
 834                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 835                                 ainfo->pair_regs [0] = *fr;
 836                                 (*fr) ++;
 837                         }
 838                         break;
 839                 case ARG_CLASS_MEMORY:
 840                         break;
 841                 default:
 842                         g_assert_not_reached ();
 843                 }
 844
 845                 if (arg_class == ARG_CLASS_MEMORY) {
 846                         /* Revert possible register assignments */
 847                         *gr = orig_gr;
 848                         *fr = orig_fr;
 849
 850                         ainfo->offset = *stack_size;
 851                         *stack_size += sizeof (mgreg_t);
 852                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 853                         if (!is_return)
 854                                 ainfo->arg_size = sizeof (mgreg_t);
 855                 }
 856         }
 857 }
 858 #endif /* TARGET_WIN32 */
 859
 860 static void
 861 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 862                            gboolean is_return,
 863                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 864 {
 865 #ifdef TARGET_WIN32
 866         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 867 #else
 868         guint32 size, quad, nquads, i, nfields;
 869         /* Keep track of the size used in each quad so we can */
 870         /* use the right size when copying args/return vars.  */
 871         guint32 quadsize [2] = {8, 8};
 872         ArgumentClass args [2];
 873         MonoMarshalType *info = NULL;
 874         MonoMarshalField *fields = NULL;
 875         MonoClass *klass;
 876         gboolean pass_on_stack = FALSE;
 877
 878         klass = mono_class_from_mono_type (type);
 879         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 880         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 881                 /* We pass and return vtypes of size 8 in a register */
 882         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 883                 pass_on_stack = TRUE;
 884         }
 885
 886         /* If this struct can't be split up naturally into 8-byte */
 887         /* chunks (registers), pass it on the stack.              */
 888         if (sig->pinvoke && !pass_on_stack) {
 889                 guint32 align;
 890                 guint32 field_size;
 891
 892                 info = mono_marshal_load_type_info (klass);
 893                 g_assert (info);
 894
 895                 /*
 896                  * Collect field information recursively to be able to
 897                  * handle nested structures.
 898                  */
 899                 nfields = count_fields_nested (klass);
 900                 fields = g_new0 (MonoMarshalField, nfields);
 901                 collect_field_info_nested (klass, fields, 0, 0);
 902
 903                 for (i = 0; i < nfields; ++i) {
 904                         field_size = mono_marshal_type_size (fields [i].field->type,
 905                                                            fields [i].mspec,
 906                                                            &align, TRUE, klass->unicode);
 907                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 908                                 pass_on_stack = TRUE;
 909                                 break;
 910                         }
 911                 }
 912         }
 913
 914         if (size == 0) {
 915                 ainfo->storage = ArgValuetypeInReg;
 916                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 917                 return;
 918         }
 919
 920         if (pass_on_stack) {
 921                 /* Allways pass in memory */
 922                 ainfo->offset = *stack_size;
 923                 *stack_size += ALIGN_TO (size, 8);
 924                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 925                 if (!is_return)
 926                         ainfo->arg_size = ALIGN_TO (size, 8);
 927
 928                 g_free (fields);
 929                 return;
 930         }
 931
 932         if (size > 8)
 933                 nquads = 2;
 934         else
 935                 nquads = 1;
 936
 937         if (!sig->pinvoke) {
 938                 int n = mono_class_value_size (klass, NULL);
 939
 940                 quadsize [0] = n >= 8 ? 8 : n;
 941                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 942
 943                 /* Always pass in 1 or 2 integer registers */
 944                 args [0] = ARG_CLASS_INTEGER;
 945                 args [1] = ARG_CLASS_INTEGER;
 946                 /* Only the simplest cases are supported */
 947                 if (is_return && nquads != 1) {
 948                         args [0] = ARG_CLASS_MEMORY;
 949                         args [1] = ARG_CLASS_MEMORY;
 950                 }
 951         } else {
 952                 /*
 953                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 954                  * The X87 and SSEUP stuff is left out since there are no such types in
 955                  * the CLR.
 956                  */
 957                 g_assert (info);
 958
 959                 if (!fields) {
 960                         ainfo->storage = ArgValuetypeInReg;
 961                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 962                         return;
 963                 }
 964
 965                 if (info->native_size > 16) {
 966                         ainfo->offset = *stack_size;
 967                         *stack_size += ALIGN_TO (info->native_size, 8);
 968                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 969                         if (!is_return)
 970                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 971
 972                         g_free (fields);
 973                         return;
 974                 }
 975
 976                 args [0] = ARG_CLASS_NO_CLASS;
 977                 args [1] = ARG_CLASS_NO_CLASS;
 978                 for (quad = 0; quad < nquads; ++quad) {
 979                         int size;
 980                         guint32 align;
 981                         ArgumentClass class1;
 982
 983                         if (nfields == 0)
 984                                 class1 = ARG_CLASS_MEMORY;
 985                         else
 986                                 class1 = ARG_CLASS_NO_CLASS;
 987                         for (i = 0; i < nfields; ++i) {
 988                                 size = mono_marshal_type_size (fields [i].field->type,
 989                                                                                            fields [i].mspec,
 990                                                                                            &align, TRUE, klass->unicode);
 991                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 992                                         /* Unaligned field */
 993                                         NOT_IMPLEMENTED;
 994                                 }
 995
 996                                 /* Skip fields in other quad */
 997                                 if ((quad == 0) && (fields [i].offset >= 8))
 998                                         continue;
 999                                 if ((quad == 1) && (fields [i].offset < 8))
1000                                         continue;
1001
1002                                 /* How far into this quad this data extends.*/
1003                                 /* (8 is size of quad) */
1004                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1005
1006                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1007                         }
1008                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1009                         args [quad] = class1;
1010                 }
1011         }
1012
1013         g_free (fields);
1014
1015         /* Post merger cleanup */
1016         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1017                 args [0] = args [1] = ARG_CLASS_MEMORY;
1018
1019         /* Allocate registers */
1020         {
1021                 int orig_gr = *gr;
1022                 int orig_fr = *fr;
1023
1024                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1025                         quadsize [0] ++;
1026                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1027                         quadsize [1] ++;
1028
1029                 ainfo->storage = ArgValuetypeInReg;
1030                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1031                 g_assert (quadsize [0] <= 8);
1032                 g_assert (quadsize [1] <= 8);
1033                 ainfo->pair_size [0] = quadsize [0];
1034                 ainfo->pair_size [1] = quadsize [1];
1035                 ainfo->nregs = nquads;
1036                 for (quad = 0; quad < nquads; ++quad) {
1037                         switch (args [quad]) {
1038                         case ARG_CLASS_INTEGER:
1039                                 if (*gr >= PARAM_REGS)
1040                                         args [quad] = ARG_CLASS_MEMORY;
1041                                 else {
1042                                         ainfo->pair_storage [quad] = ArgInIReg;
1043                                         if (is_return)
1044                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1045                                         else
1046                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1047                                         (*gr) ++;
1048                                 }
1049                                 break;
1050                         case ARG_CLASS_SSE:
1051                                 if (*fr >= FLOAT_PARAM_REGS)
1052                                         args [quad] = ARG_CLASS_MEMORY;
1053                                 else {
1054                                         if (quadsize[quad] <= 4)
1055                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1056                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1057                                         ainfo->pair_regs [quad] = *fr;
1058                                         (*fr) ++;
1059                                 }
1060                                 break;
1061                         case ARG_CLASS_MEMORY:
1062                                 break;
1063                         default:
1064                                 g_assert_not_reached ();
1065                         }
1066                 }
1067
1068                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1069                         int arg_size;
1070                         /* Revert possible register assignments */
1071                         *gr = orig_gr;
1072                         *fr = orig_fr;
1073
1074                         ainfo->offset = *stack_size;
1075                         if (sig->pinvoke)
1076                                 arg_size = ALIGN_TO (info->native_size, 8);
1077                         else
1078                                 arg_size = nquads * sizeof(mgreg_t);
1079                         *stack_size += arg_size;
1080                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1081                         if (!is_return)
1082                                 ainfo->arg_size = arg_size;
1083                 }
1084         }
1085 #endif /* !TARGET_WIN32 */
1086 }
1087
1088 /*
1089  * get_call_info:
1090  *
1091  *  Obtain information about a call according to the calling convention.
1092  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1093  * Draft Version 0.23" document for more information.
1094  */
1095 static CallInfo*
1096 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1097 {
1098         guint32 i, gr, fr, pstart;
1099         MonoType *ret_type;
1100         int n = sig->hasthis + sig->param_count;
1101         guint32 stack_size = 0;
1102         CallInfo *cinfo;
1103         gboolean is_pinvoke = sig->pinvoke;
1104
1105         if (mp)
1106                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1107         else
1108                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1109
1110         cinfo->nargs = n;
1111         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
1112
1113         gr = 0;
1114         fr = 0;
1115
1116 #ifdef TARGET_WIN32
1117         /* Reserve space where the callee can save the argument registers */
1118         stack_size = 4 * sizeof (mgreg_t);
1119 #endif
1120
1121         /* return value */
1122         ret_type = mini_get_underlying_type (sig->ret);
1123         switch (ret_type->type) {
1124         case MONO_TYPE_I1:
1125         case MONO_TYPE_U1:
1126         case MONO_TYPE_I2:
1127         case MONO_TYPE_U2:
1128         case MONO_TYPE_I4:
1129         case MONO_TYPE_U4:
1130         case MONO_TYPE_I:
1131         case MONO_TYPE_U:
1132         case MONO_TYPE_PTR:
1133         case MONO_TYPE_FNPTR:
1134         case MONO_TYPE_CLASS:
1135         case MONO_TYPE_OBJECT:
1136         case MONO_TYPE_SZARRAY:
1137         case MONO_TYPE_ARRAY:
1138         case MONO_TYPE_STRING:
1139                 cinfo->ret.storage = ArgInIReg;
1140                 cinfo->ret.reg = AMD64_RAX;
1141                 break;
1142         case MONO_TYPE_U8:
1143         case MONO_TYPE_I8:
1144                 cinfo->ret.storage = ArgInIReg;
1145                 cinfo->ret.reg = AMD64_RAX;
1146                 break;
1147         case MONO_TYPE_R4:
1148                 cinfo->ret.storage = ArgInFloatSSEReg;
1149                 cinfo->ret.reg = AMD64_XMM0;
1150                 break;
1151         case MONO_TYPE_R8:
1152                 cinfo->ret.storage = ArgInDoubleSSEReg;
1153                 cinfo->ret.reg = AMD64_XMM0;
1154                 break;
1155         case MONO_TYPE_GENERICINST:
1156                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1157                         cinfo->ret.storage = ArgInIReg;
1158                         cinfo->ret.reg = AMD64_RAX;
1159                         break;
1160                 }
1161                 if (mini_is_gsharedvt_type (ret_type)) {
1162                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
1163                         break;
1164                 }
1165                 /* fall through */
1166         case MONO_TYPE_VALUETYPE:
1167         case MONO_TYPE_TYPEDBYREF: {
1168                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1169
1170                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1171                 g_assert (cinfo->ret.storage != ArgInIReg);
1172                 break;
1173         }
1174         case MONO_TYPE_VAR:
1175         case MONO_TYPE_MVAR:
1176                 g_assert (mini_is_gsharedvt_type (ret_type));
1177                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
1178                 break;
1179         case MONO_TYPE_VOID:
1180                 break;
1181         default:
1182                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1183         }
1184
1185         pstart = 0;
1186         /*
1187          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1188          * the first argument, allowing 'this' to be always passed in the first arg reg.
1189          * Also do this if the first argument is a reference type, since virtual calls
1190          * are sometimes made using calli without sig->hasthis set, like in the delegate
1191          * invoke wrappers.
1192          */
1193         ArgStorage ret_storage = cinfo->ret.storage;
1194         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1195                 if (sig->hasthis) {
1196                         add_general (&gr, &stack_size, cinfo->args + 0);
1197                 } else {
1198                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1199                         pstart = 1;
1200                 }
1201                 add_general (&gr, &stack_size, &cinfo->ret);
1202                 cinfo->ret.storage = ret_storage;
1203                 cinfo->vret_arg_index = 1;
1204         } else {
1205                 /* this */
1206                 if (sig->hasthis)
1207                         add_general (&gr, &stack_size, cinfo->args + 0);
1208
1209                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
1210                         add_general (&gr, &stack_size, &cinfo->ret);
1211                         cinfo->ret.storage = ret_storage;
1212                 }
1213         }
1214
1215         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1216                 gr = PARAM_REGS;
1217                 fr = FLOAT_PARAM_REGS;
1218
1219                 /* Emit the signature cookie just before the implicit arguments */
1220                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1221         }
1222
1223         for (i = pstart; i < sig->param_count; ++i) {
1224                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1225                 MonoType *ptype;
1226
1227 #ifdef TARGET_WIN32
1228                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1229                 if (gr > fr)
1230                         fr = gr;
1231                 else if (fr > gr)
1232                         gr = fr;
1233 #endif
1234
1235                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1236                         /* We allways pass the sig cookie on the stack for simplicity */
1237                         /*
1238                          * Prevent implicit arguments + the sig cookie from being passed
1239                          * in registers.
1240                          */
1241                         gr = PARAM_REGS;
1242                         fr = FLOAT_PARAM_REGS;
1243
1244                         /* Emit the signature cookie just before the implicit arguments */
1245                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1246                 }
1247
1248                 ptype = mini_get_underlying_type (sig->params [i]);
1249                 switch (ptype->type) {
1250                 case MONO_TYPE_I1:
1251                 case MONO_TYPE_U1:
1252                         add_general (&gr, &stack_size, ainfo);
1253                         break;
1254                 case MONO_TYPE_I2:
1255                 case MONO_TYPE_U2:
1256                         add_general (&gr, &stack_size, ainfo);
1257                         break;
1258                 case MONO_TYPE_I4:
1259                 case MONO_TYPE_U4:
1260                         add_general (&gr, &stack_size, ainfo);
1261                         break;
1262                 case MONO_TYPE_I:
1263                 case MONO_TYPE_U:
1264                 case MONO_TYPE_PTR:
1265                 case MONO_TYPE_FNPTR:
1266                 case MONO_TYPE_CLASS:
1267                 case MONO_TYPE_OBJECT:
1268                 case MONO_TYPE_STRING:
1269                 case MONO_TYPE_SZARRAY:
1270                 case MONO_TYPE_ARRAY:
1271                         add_general (&gr, &stack_size, ainfo);
1272                         break;
1273                 case MONO_TYPE_GENERICINST:
1274                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1275                                 add_general (&gr, &stack_size, ainfo);
1276                                 break;
1277                         }
1278                         if (mini_is_gsharedvt_variable_type (ptype)) {
1279                                 /* gsharedvt arguments are passed by ref */
1280                                 add_general (&gr, &stack_size, ainfo);
1281                                 if (ainfo->storage == ArgInIReg)
1282                                         ainfo->storage = ArgGSharedVtInReg;
1283                                 else
1284                                         ainfo->storage = ArgGSharedVtOnStack;
1285                                 break;
1286                         }
1287                         /* fall through */
1288                 case MONO_TYPE_VALUETYPE:
1289                 case MONO_TYPE_TYPEDBYREF:
1290                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1291                         break;
1292                 case MONO_TYPE_U8:
1293
1294                 case MONO_TYPE_I8:
1295                         add_general (&gr, &stack_size, ainfo);
1296                         break;
1297                 case MONO_TYPE_R4:
1298                         add_float (&fr, &stack_size, ainfo, FALSE);
1299                         break;
1300                 case MONO_TYPE_R8:
1301                         add_float (&fr, &stack_size, ainfo, TRUE);
1302                         break;
1303                 case MONO_TYPE_VAR:
1304                 case MONO_TYPE_MVAR:
1305                         /* gsharedvt arguments are passed by ref */
1306                         g_assert (mini_is_gsharedvt_type (ptype));
1307                         add_general (&gr, &stack_size, ainfo);
1308                         if (ainfo->storage == ArgInIReg)
1309                                 ainfo->storage = ArgGSharedVtInReg;
1310                         else
1311                                 ainfo->storage = ArgGSharedVtOnStack;
1312                         break;
1313                 default:
1314                         g_assert_not_reached ();
1315                 }
1316         }
1317
1318         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1319                 gr = PARAM_REGS;
1320                 fr = FLOAT_PARAM_REGS;
1321
1322                 /* Emit the signature cookie just before the implicit arguments */
1323                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1324         }
1325
1326         cinfo->stack_usage = stack_size;
1327         cinfo->reg_usage = gr;
1328         cinfo->freg_usage = fr;
1329         return cinfo;
1330 }
1331
1332 /*
1333  * mono_arch_get_argument_info:
1334  * @csig:  a method signature
1335  * @param_count: the number of parameters to consider
1336  * @arg_info: an array to store the result infos
1337  *
1338  * Gathers information on parameters such as size, alignment and
1339  * padding. arg_info should be large enought to hold param_count + 1 entries.
1340  *
1341  * Returns the size of the argument area on the stack.
1342  */
1343 int
1344 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1345 {
1346         int k;
1347         CallInfo *cinfo = get_call_info (NULL, csig);
1348         guint32 args_size = cinfo->stack_usage;
1349
1350         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1351         if (csig->hasthis) {
1352                 arg_info [0].offset = 0;
1353         }
1354
1355         for (k = 0; k < param_count; k++) {
1356                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1357                 /* FIXME: */
1358                 arg_info [k + 1].size = 0;
1359         }
1360
1361         g_free (cinfo);
1362
1363         return args_size;
1364 }
1365
1366 gboolean
1367 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1368 {
1369         CallInfo *c1, *c2;
1370         gboolean res;
1371         MonoType *callee_ret;
1372
1373         c1 = get_call_info (NULL, caller_sig);
1374         c2 = get_call_info (NULL, callee_sig);
1375         res = c1->stack_usage >= c2->stack_usage;
1376         callee_ret = mini_get_underlying_type (callee_sig->ret);
1377         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1378                 /* An address on the callee's stack is passed as the first argument */
1379                 res = FALSE;
1380
1381         g_free (c1);
1382         g_free (c2);
1383
1384         return res;
1385 }
1386
1387 /*
1388  * Initialize the cpu to execute managed code.
1389  */
1390 void
1391 mono_arch_cpu_init (void)
1392 {
1393 #ifndef _MSC_VER
1394         guint16 fpcw;
1395
1396         /* spec compliance requires running with double precision */
1397         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1398         fpcw &= ~X86_FPCW_PRECC_MASK;
1399         fpcw |= X86_FPCW_PREC_DOUBLE;
1400         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1401         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1402 #else
1403         /* TODO: This is crashing on Win64 right now.
1404         * _control87 (_PC_53, MCW_PC);
1405         */
1406 #endif
1407 }
1408
1409 /*
1410  * Initialize architecture specific code.
1411  */
1412 void
1413 mono_arch_init (void)
1414 {
1415         mono_os_mutex_init_recursive (&mini_arch_mutex);
1416 #if defined(__native_client_codegen__)
1417         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1418         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1419         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1420         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1421 #endif
1422
1423         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1424         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1425         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1426         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1427 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1428         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1429 #endif
1430
1431         if (!mono_aot_only)
1432                 bp_trampoline = mini_get_breakpoint_trampoline ();
1433 }
1434
1435 /*
1436  * Cleanup architecture specific code.
1437  */
1438 void
1439 mono_arch_cleanup (void)
1440 {
1441         mono_os_mutex_destroy (&mini_arch_mutex);
1442 #if defined(__native_client_codegen__)
1443         mono_native_tls_free (nacl_instruction_depth);
1444         mono_native_tls_free (nacl_rex_tag);
1445         mono_native_tls_free (nacl_legacy_prefix_tag);
1446 #endif
1447 }
1448
1449 /*
1450  * This function returns the optimizations supported on this cpu.
1451  */
1452 guint32
1453 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1454 {
1455         guint32 opts = 0;
1456
1457         *exclude_mask = 0;
1458
1459         if (mono_hwcap_x86_has_cmov) {
1460                 opts |= MONO_OPT_CMOV;
1461
1462                 if (mono_hwcap_x86_has_fcmov)
1463                         opts |= MONO_OPT_FCMOV;
1464                 else
1465                         *exclude_mask |= MONO_OPT_FCMOV;
1466         } else {
1467                 *exclude_mask |= MONO_OPT_CMOV;
1468         }
1469
1470         return opts;
1471 }
1472
1473 /*
1474  * This function test for all SSE functions supported.
1475  *
1476  * Returns a bitmask corresponding to all supported versions.
1477  *
1478  */
1479 guint32
1480 mono_arch_cpu_enumerate_simd_versions (void)
1481 {
1482         guint32 sse_opts = 0;
1483
1484         if (mono_hwcap_x86_has_sse1)
1485                 sse_opts |= SIMD_VERSION_SSE1;
1486
1487         if (mono_hwcap_x86_has_sse2)
1488                 sse_opts |= SIMD_VERSION_SSE2;
1489
1490         if (mono_hwcap_x86_has_sse3)
1491                 sse_opts |= SIMD_VERSION_SSE3;
1492
1493         if (mono_hwcap_x86_has_ssse3)
1494                 sse_opts |= SIMD_VERSION_SSSE3;
1495
1496         if (mono_hwcap_x86_has_sse41)
1497                 sse_opts |= SIMD_VERSION_SSE41;
1498
1499         if (mono_hwcap_x86_has_sse42)
1500                 sse_opts |= SIMD_VERSION_SSE42;
1501
1502         if (mono_hwcap_x86_has_sse4a)
1503                 sse_opts |= SIMD_VERSION_SSE4a;
1504
1505         return sse_opts;
1506 }
1507
1508 #ifndef DISABLE_JIT
1509
1510 GList *
1511 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1512 {
1513         GList *vars = NULL;
1514         int i;
1515
1516         for (i = 0; i < cfg->num_varinfo; i++) {
1517                 MonoInst *ins = cfg->varinfo [i];
1518                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1519
1520                 /* unused vars */
1521                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1522                         continue;
1523
1524                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1525                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1526                         continue;
1527
1528                 if (mono_is_regsize_var (ins->inst_vtype)) {
1529                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1530                         g_assert (i == vmv->idx);
1531                         vars = g_list_prepend (vars, vmv);
1532                 }
1533         }
1534
1535         vars = mono_varlist_sort (cfg, vars, 0);
1536
1537         return vars;
1538 }
1539
1540 /**
1541  * mono_arch_compute_omit_fp:
1542  *
1543  *   Determine whenever the frame pointer can be eliminated.
1544  */
1545 static void
1546 mono_arch_compute_omit_fp (MonoCompile *cfg)
1547 {
1548         MonoMethodSignature *sig;
1549         MonoMethodHeader *header;
1550         int i, locals_size;
1551         CallInfo *cinfo;
1552
1553         if (cfg->arch.omit_fp_computed)
1554                 return;
1555
1556         header = cfg->header;
1557
1558         sig = mono_method_signature (cfg->method);
1559
1560         if (!cfg->arch.cinfo)
1561                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1562         cinfo = (CallInfo *)cfg->arch.cinfo;
1563
1564         /*
1565          * FIXME: Remove some of the restrictions.
1566          */
1567         cfg->arch.omit_fp = TRUE;
1568         cfg->arch.omit_fp_computed = TRUE;
1569
1570 #ifdef __native_client_codegen__
1571         /* NaCl modules may not change the value of RBP, so it cannot be */
1572         /* used as a normal register, but it can be used as a frame pointer*/
1573         cfg->disable_omit_fp = TRUE;
1574         cfg->arch.omit_fp = FALSE;
1575 #endif
1576
1577         if (cfg->disable_omit_fp)
1578                 cfg->arch.omit_fp = FALSE;
1579
1580         if (!debug_omit_fp ())
1581                 cfg->arch.omit_fp = FALSE;
1582         /*
1583         if (cfg->method->save_lmf)
1584                 cfg->arch.omit_fp = FALSE;
1585         */
1586         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1587                 cfg->arch.omit_fp = FALSE;
1588         if (header->num_clauses)
1589                 cfg->arch.omit_fp = FALSE;
1590         if (cfg->param_area)
1591                 cfg->arch.omit_fp = FALSE;
1592         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1593                 cfg->arch.omit_fp = FALSE;
1594         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1595                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1596                 cfg->arch.omit_fp = FALSE;
1597         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1598                 ArgInfo *ainfo = &cinfo->args [i];
1599
1600                 if (ainfo->storage == ArgOnStack) {
1601                         /*
1602                          * The stack offset can only be determined when the frame
1603                          * size is known.
1604                          */
1605                         cfg->arch.omit_fp = FALSE;
1606                 }
1607         }
1608
1609         locals_size = 0;
1610         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1611                 MonoInst *ins = cfg->varinfo [i];
1612                 int ialign;
1613
1614                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1615         }
1616 }
1617
1618 GList *
1619 mono_arch_get_global_int_regs (MonoCompile *cfg)
1620 {
1621         GList *regs = NULL;
1622
1623         mono_arch_compute_omit_fp (cfg);
1624
1625         if (cfg->arch.omit_fp)
1626                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1627
1628         /* We use the callee saved registers for global allocation */
1629         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1630         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1631         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1632         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1633 #ifndef __native_client_codegen__
1634         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1635 #endif
1636 #ifdef TARGET_WIN32
1637         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1638         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1639 #endif
1640
1641         return regs;
1642 }
1643
1644 GList*
1645 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1646 {
1647         GList *regs = NULL;
1648         int i;
1649
1650         /* All XMM registers */
1651         for (i = 0; i < 16; ++i)
1652                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1653
1654         return regs;
1655 }
1656
1657 GList*
1658 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1659 {
1660         static GList *r = NULL;
1661
1662         if (r == NULL) {
1663                 GList *regs = NULL;
1664
1665                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1666                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1667                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1668                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1669                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1670 #ifndef __native_client_codegen__
1671                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1672 #endif
1673
1674                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1675                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1676                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1677                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1678                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1679                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1680                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1681                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1682
1683                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1684         }
1685
1686         return r;
1687 }
1688
1689 GList*
1690 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1691 {
1692         int i;
1693         static GList *r = NULL;
1694
1695         if (r == NULL) {
1696                 GList *regs = NULL;
1697
1698                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1699                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1700
1701                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1702         }
1703
1704         return r;
1705 }
1706
1707 /*
1708  * mono_arch_regalloc_cost:
1709  *
1710  *  Return the cost, in number of memory references, of the action of
1711  * allocating the variable VMV into a register during global register
1712  * allocation.
1713  */
1714 guint32
1715 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1716 {
1717         MonoInst *ins = cfg->varinfo [vmv->idx];
1718
1719         if (cfg->method->save_lmf)
1720                 /* The register is already saved */
1721                 /* substract 1 for the invisible store in the prolog */
1722                 return (ins->opcode == OP_ARG) ? 0 : 1;
1723         else
1724                 /* push+pop */
1725                 return (ins->opcode == OP_ARG) ? 1 : 2;
1726 }
1727
1728 /*
1729  * mono_arch_fill_argument_info:
1730  *
1731  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1732  * of the method.
1733  */
1734 void
1735 mono_arch_fill_argument_info (MonoCompile *cfg)
1736 {
1737         MonoType *sig_ret;
1738         MonoMethodSignature *sig;
1739         MonoInst *ins;
1740         int i;
1741         CallInfo *cinfo;
1742
1743         sig = mono_method_signature (cfg->method);
1744
1745         cinfo = (CallInfo *)cfg->arch.cinfo;
1746         sig_ret = mini_get_underlying_type (sig->ret);
1747
1748         /*
1749          * Contrary to mono_arch_allocate_vars (), the information should describe
1750          * where the arguments are at the beginning of the method, not where they can be
1751          * accessed during the execution of the method. The later makes no sense for the
1752          * global register allocator, since a variable can be in more than one location.
1753          */
1754         switch (cinfo->ret.storage) {
1755         case ArgInIReg:
1756         case ArgInFloatSSEReg:
1757         case ArgInDoubleSSEReg:
1758                 cfg->ret->opcode = OP_REGVAR;
1759                 cfg->ret->inst_c0 = cinfo->ret.reg;
1760                 break;
1761         case ArgValuetypeInReg:
1762                 cfg->ret->opcode = OP_REGOFFSET;
1763                 cfg->ret->inst_basereg = -1;
1764                 cfg->ret->inst_offset = -1;
1765                 break;
1766         case ArgNone:
1767                 break;
1768         default:
1769                 g_assert_not_reached ();
1770         }
1771
1772         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1773                 ArgInfo *ainfo = &cinfo->args [i];
1774
1775                 ins = cfg->args [i];
1776
1777                 switch (ainfo->storage) {
1778                 case ArgInIReg:
1779                 case ArgInFloatSSEReg:
1780                 case ArgInDoubleSSEReg:
1781                         ins->opcode = OP_REGVAR;
1782                         ins->inst_c0 = ainfo->reg;
1783                         break;
1784                 case ArgOnStack:
1785                         ins->opcode = OP_REGOFFSET;
1786                         ins->inst_basereg = -1;
1787                         ins->inst_offset = -1;
1788                         break;
1789                 case ArgValuetypeInReg:
1790                         /* Dummy */
1791                         ins->opcode = OP_NOP;
1792                         break;
1793                 default:
1794                         g_assert_not_reached ();
1795                 }
1796         }
1797 }
1798
1799 void
1800 mono_arch_allocate_vars (MonoCompile *cfg)
1801 {
1802         MonoType *sig_ret;
1803         MonoMethodSignature *sig;
1804         MonoInst *ins;
1805         int i, offset;
1806         guint32 locals_stack_size, locals_stack_align;
1807         gint32 *offsets;
1808         CallInfo *cinfo;
1809
1810         sig = mono_method_signature (cfg->method);
1811
1812         cinfo = (CallInfo *)cfg->arch.cinfo;
1813         sig_ret = mini_get_underlying_type (sig->ret);
1814
1815         mono_arch_compute_omit_fp (cfg);
1816
1817         /*
1818          * We use the ABI calling conventions for managed code as well.
1819          * Exception: valuetypes are only sometimes passed or returned in registers.
1820          */
1821
1822         /*
1823          * The stack looks like this:
1824          * <incoming arguments passed on the stack>
1825          * <return value>
1826          * <lmf/caller saved registers>
1827          * <locals>
1828          * <spill area>
1829          * <localloc area>  -> grows dynamically
1830          * <params area>
1831          */
1832
1833         if (cfg->arch.omit_fp) {
1834                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1835                 cfg->frame_reg = AMD64_RSP;
1836                 offset = 0;
1837         } else {
1838                 /* Locals are allocated backwards from %fp */
1839                 cfg->frame_reg = AMD64_RBP;
1840                 offset = 0;
1841         }
1842
1843         cfg->arch.saved_iregs = cfg->used_int_regs;
1844         if (cfg->method->save_lmf)
1845                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1846                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1847
1848         if (cfg->arch.omit_fp)
1849                 cfg->arch.reg_save_area_offset = offset;
1850         /* Reserve space for callee saved registers */
1851         for (i = 0; i < AMD64_NREG; ++i)
1852                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1853                         offset += sizeof(mgreg_t);
1854                 }
1855         if (!cfg->arch.omit_fp)
1856                 cfg->arch.reg_save_area_offset = -offset;
1857
1858         if (sig_ret->type != MONO_TYPE_VOID) {
1859                 switch (cinfo->ret.storage) {
1860                 case ArgInIReg:
1861                 case ArgInFloatSSEReg:
1862                 case ArgInDoubleSSEReg:
1863                         cfg->ret->opcode = OP_REGVAR;
1864                         cfg->ret->inst_c0 = cinfo->ret.reg;
1865                         cfg->ret->dreg = cinfo->ret.reg;
1866                         break;
1867                 case ArgValuetypeAddrInIReg:
1868                 case ArgGsharedvtVariableInReg:
1869                         /* The register is volatile */
1870                         cfg->vret_addr->opcode = OP_REGOFFSET;
1871                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1872                         if (cfg->arch.omit_fp) {
1873                                 cfg->vret_addr->inst_offset = offset;
1874                                 offset += 8;
1875                         } else {
1876                                 offset += 8;
1877                                 cfg->vret_addr->inst_offset = -offset;
1878                         }
1879                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1880                                 printf ("vret_addr =");
1881                                 mono_print_ins (cfg->vret_addr);
1882                         }
1883                         break;
1884                 case ArgValuetypeInReg:
1885                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1886                         cfg->ret->opcode = OP_REGOFFSET;
1887                         cfg->ret->inst_basereg = cfg->frame_reg;
1888                         if (cfg->arch.omit_fp) {
1889                                 cfg->ret->inst_offset = offset;
1890                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1891                         } else {
1892                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1893                                 cfg->ret->inst_offset = - offset;
1894                         }
1895                         break;
1896                 default:
1897                         g_assert_not_reached ();
1898                 }
1899         }
1900
1901         /* Allocate locals */
1902         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1903         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1904                 char *mname = mono_method_full_name (cfg->method, TRUE);
1905                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1906                 g_free (mname);
1907                 return;
1908         }
1909
1910         if (locals_stack_align) {
1911                 offset += (locals_stack_align - 1);
1912                 offset &= ~(locals_stack_align - 1);
1913         }
1914         if (cfg->arch.omit_fp) {
1915                 cfg->locals_min_stack_offset = offset;
1916                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1917         } else {
1918                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1919                 cfg->locals_max_stack_offset = - offset;
1920         }
1921
1922         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1923                 if (offsets [i] != -1) {
1924                         MonoInst *ins = cfg->varinfo [i];
1925                         ins->opcode = OP_REGOFFSET;
1926                         ins->inst_basereg = cfg->frame_reg;
1927                         if (cfg->arch.omit_fp)
1928                                 ins->inst_offset = (offset + offsets [i]);
1929                         else
1930                                 ins->inst_offset = - (offset + offsets [i]);
1931                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1932                 }
1933         }
1934         offset += locals_stack_size;
1935
1936         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1937                 g_assert (!cfg->arch.omit_fp);
1938                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1939                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1940         }
1941
1942         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1943                 ins = cfg->args [i];
1944                 if (ins->opcode != OP_REGVAR) {
1945                         ArgInfo *ainfo = &cinfo->args [i];
1946                         gboolean inreg = TRUE;
1947
1948                         /* FIXME: Allocate volatile arguments to registers */
1949                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1950                                 inreg = FALSE;
1951
1952                         /*
1953                          * Under AMD64, all registers used to pass arguments to functions
1954                          * are volatile across calls.
1955                          * FIXME: Optimize this.
1956                          */
1957                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1958                                 inreg = FALSE;
1959
1960                         ins->opcode = OP_REGOFFSET;
1961
1962                         switch (ainfo->storage) {
1963                         case ArgInIReg:
1964                         case ArgInFloatSSEReg:
1965                         case ArgInDoubleSSEReg:
1966                         case ArgGSharedVtInReg:
1967                                 if (inreg) {
1968                                         ins->opcode = OP_REGVAR;
1969                                         ins->dreg = ainfo->reg;
1970                                 }
1971                                 break;
1972                         case ArgOnStack:
1973                         case ArgGSharedVtOnStack:
1974                                 g_assert (!cfg->arch.omit_fp);
1975                                 ins->opcode = OP_REGOFFSET;
1976                                 ins->inst_basereg = cfg->frame_reg;
1977                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1978                                 break;
1979                         case ArgValuetypeInReg:
1980                                 break;
1981                         case ArgValuetypeAddrInIReg: {
1982                                 MonoInst *indir;
1983                                 g_assert (!cfg->arch.omit_fp);
1984
1985                                 MONO_INST_NEW (cfg, indir, 0);
1986                                 indir->opcode = OP_REGOFFSET;
1987                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1988                                         indir->inst_basereg = cfg->frame_reg;
1989                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1990                                         offset += (sizeof (gpointer));
1991                                         indir->inst_offset = - offset;
1992                                 }
1993                                 else {
1994                                         indir->inst_basereg = cfg->frame_reg;
1995                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1996                                 }
1997
1998                                 ins->opcode = OP_VTARG_ADDR;
1999                                 ins->inst_left = indir;
2000
2001                                 break;
2002                         }
2003                         default:
2004                                 NOT_IMPLEMENTED;
2005                         }
2006
2007                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2008                                 ins->opcode = OP_REGOFFSET;
2009                                 ins->inst_basereg = cfg->frame_reg;
2010                                 /* These arguments are saved to the stack in the prolog */
2011                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2012                                 if (cfg->arch.omit_fp) {
2013                                         ins->inst_offset = offset;
2014                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2015                                         // Arguments are yet supported by the stack map creation code
2016                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2017                                 } else {
2018                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2019                                         ins->inst_offset = - offset;
2020                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2021                                 }
2022                         }
2023                 }
2024         }
2025
2026         cfg->stack_offset = offset;
2027 }
2028
2029 void
2030 mono_arch_create_vars (MonoCompile *cfg)
2031 {
2032         MonoMethodSignature *sig;
2033         CallInfo *cinfo;
2034         MonoType *sig_ret;
2035
2036         sig = mono_method_signature (cfg->method);
2037
2038         if (!cfg->arch.cinfo)
2039                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2040         cinfo = (CallInfo *)cfg->arch.cinfo;
2041
2042         if (cinfo->ret.storage == ArgValuetypeInReg)
2043                 cfg->ret_var_is_local = TRUE;
2044
2045         sig_ret = mini_get_underlying_type (sig->ret);
2046         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2047                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2048                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2049                         printf ("vret_addr = ");
2050                         mono_print_ins (cfg->vret_addr);
2051                 }
2052         }
2053
2054         if (cfg->gen_sdb_seq_points) {
2055                 MonoInst *ins;
2056
2057                 if (cfg->compile_aot) {
2058                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2059                         ins->flags |= MONO_INST_VOLATILE;
2060                         cfg->arch.seq_point_info_var = ins;
2061                 }
2062                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2063                 ins->flags |= MONO_INST_VOLATILE;
2064                 cfg->arch.ss_tramp_var = ins;
2065
2066                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2067                 ins->flags |= MONO_INST_VOLATILE;
2068                 cfg->arch.bp_tramp_var = ins;
2069         }
2070
2071         if (cfg->method->save_lmf)
2072                 cfg->create_lmf_var = TRUE;
2073
2074         if (cfg->method->save_lmf) {
2075                 cfg->lmf_ir = TRUE;
2076 #if !defined(TARGET_WIN32)
2077                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2078                         cfg->lmf_ir_mono_lmf = TRUE;
2079 #endif
2080         }
2081 }
2082
2083 static void
2084 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2085 {
2086         MonoInst *ins;
2087
2088         switch (storage) {
2089         case ArgInIReg:
2090                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2091                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2092                 ins->sreg1 = tree->dreg;
2093                 MONO_ADD_INS (cfg->cbb, ins);
2094                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2095                 break;
2096         case ArgInFloatSSEReg:
2097                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2098                 ins->dreg = mono_alloc_freg (cfg);
2099                 ins->sreg1 = tree->dreg;
2100                 MONO_ADD_INS (cfg->cbb, ins);
2101
2102                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2103                 break;
2104         case ArgInDoubleSSEReg:
2105                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2106                 ins->dreg = mono_alloc_freg (cfg);
2107                 ins->sreg1 = tree->dreg;
2108                 MONO_ADD_INS (cfg->cbb, ins);
2109
2110                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2111
2112                 break;
2113         default:
2114                 g_assert_not_reached ();
2115         }
2116 }
2117
2118 static int
2119 arg_storage_to_load_membase (ArgStorage storage)
2120 {
2121         switch (storage) {
2122         case ArgInIReg:
2123 #if defined(__mono_ilp32__)
2124                 return OP_LOADI8_MEMBASE;
2125 #else
2126                 return OP_LOAD_MEMBASE;
2127 #endif
2128         case ArgInDoubleSSEReg:
2129                 return OP_LOADR8_MEMBASE;
2130         case ArgInFloatSSEReg:
2131                 return OP_LOADR4_MEMBASE;
2132         default:
2133                 g_assert_not_reached ();
2134         }
2135
2136         return -1;
2137 }
2138
2139 static void
2140 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2141 {
2142         MonoMethodSignature *tmp_sig;
2143         int sig_reg;
2144
2145         if (call->tail_call)
2146                 NOT_IMPLEMENTED;
2147
2148         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2149
2150         /*
2151          * mono_ArgIterator_Setup assumes the signature cookie is
2152          * passed first and all the arguments which were before it are
2153          * passed on the stack after the signature. So compensate by
2154          * passing a different signature.
2155          */
2156         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2157         tmp_sig->param_count -= call->signature->sentinelpos;
2158         tmp_sig->sentinelpos = 0;
2159         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2160
2161         sig_reg = mono_alloc_ireg (cfg);
2162         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2163
2164         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2165 }
2166
2167 #ifdef ENABLE_LLVM
2168 static inline LLVMArgStorage
2169 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2170 {
2171         switch (storage) {
2172         case ArgInIReg:
2173                 return LLVMArgInIReg;
2174         case ArgNone:
2175                 return LLVMArgNone;
2176         case ArgGSharedVtInReg:
2177         case ArgGSharedVtOnStack:
2178                 return LLVMArgGSharedVt;
2179         default:
2180                 g_assert_not_reached ();
2181                 return LLVMArgNone;
2182         }
2183 }
2184
2185 LLVMCallInfo*
2186 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2187 {
2188         int i, n;
2189         CallInfo *cinfo;
2190         ArgInfo *ainfo;
2191         int j;
2192         LLVMCallInfo *linfo;
2193         MonoType *t, *sig_ret;
2194
2195         n = sig->param_count + sig->hasthis;
2196         sig_ret = mini_get_underlying_type (sig->ret);
2197
2198         cinfo = get_call_info (cfg->mempool, sig);
2199
2200         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2201
2202         /*
2203          * LLVM always uses the native ABI while we use our own ABI, the
2204          * only difference is the handling of vtypes:
2205          * - we only pass/receive them in registers in some cases, and only
2206          *   in 1 or 2 integer registers.
2207          */
2208         switch (cinfo->ret.storage) {
2209         case ArgNone:
2210                 linfo->ret.storage = LLVMArgNone;
2211                 break;
2212         case ArgInIReg:
2213         case ArgInFloatSSEReg:
2214         case ArgInDoubleSSEReg:
2215                 linfo->ret.storage = LLVMArgNormal;
2216                 break;
2217         case ArgValuetypeInReg: {
2218                 ainfo = &cinfo->ret;
2219
2220                 if (sig->pinvoke &&
2221                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2222                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2223                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2224                         cfg->disable_llvm = TRUE;
2225                         return linfo;
2226                 }
2227
2228                 linfo->ret.storage = LLVMArgVtypeInReg;
2229                 for (j = 0; j < 2; ++j)
2230                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2231                 break;
2232         }
2233         case ArgValuetypeAddrInIReg:
2234         case ArgGsharedvtVariableInReg:
2235                 /* Vtype returned using a hidden argument */
2236                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2237                 linfo->vret_arg_index = cinfo->vret_arg_index;
2238                 break;
2239         default:
2240                 g_assert_not_reached ();
2241                 break;
2242         }
2243
2244         for (i = 0; i < n; ++i) {
2245                 ainfo = cinfo->args + i;
2246
2247                 if (i >= sig->hasthis)
2248                         t = sig->params [i - sig->hasthis];
2249                 else
2250                         t = &mono_defaults.int_class->byval_arg;
2251
2252                 linfo->args [i].storage = LLVMArgNone;
2253
2254                 switch (ainfo->storage) {
2255                 case ArgInIReg:
2256                         linfo->args [i].storage = LLVMArgNormal;
2257                         break;
2258                 case ArgInDoubleSSEReg:
2259                 case ArgInFloatSSEReg:
2260                         linfo->args [i].storage = LLVMArgNormal;
2261                         break;
2262                 case ArgOnStack:
2263                         if (MONO_TYPE_ISSTRUCT (t))
2264                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2265                         else
2266                                 linfo->args [i].storage = LLVMArgNormal;
2267                         break;
2268                 case ArgValuetypeInReg:
2269                         if (sig->pinvoke &&
2270                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2271                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2272                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2273                                 cfg->disable_llvm = TRUE;
2274                                 return linfo;
2275                         }
2276
2277                         linfo->args [i].storage = LLVMArgVtypeInReg;
2278                         for (j = 0; j < 2; ++j)
2279                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2280                         break;
2281                 case ArgGSharedVtInReg:
2282                 case ArgGSharedVtOnStack:
2283                         linfo->args [i].storage = LLVMArgGSharedVt;
2284                         break;
2285                 default:
2286                         cfg->exception_message = g_strdup ("ainfo->storage");
2287                         cfg->disable_llvm = TRUE;
2288                         break;
2289                 }
2290         }
2291
2292         return linfo;
2293 }
2294 #endif
2295
2296 void
2297 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2298 {
2299         MonoInst *arg, *in;
2300         MonoMethodSignature *sig;
2301         MonoType *sig_ret;
2302         int i, n;
2303         CallInfo *cinfo;
2304         ArgInfo *ainfo;
2305
2306         sig = call->signature;
2307         n = sig->param_count + sig->hasthis;
2308
2309         cinfo = get_call_info (cfg->mempool, sig);
2310
2311         sig_ret = sig->ret;
2312
2313         if (COMPILE_LLVM (cfg)) {
2314                 /* We shouldn't be called in the llvm case */
2315                 cfg->disable_llvm = TRUE;
2316                 return;
2317         }
2318
2319         /*
2320          * Emit all arguments which are passed on the stack to prevent register
2321          * allocation problems.
2322          */
2323         for (i = 0; i < n; ++i) {
2324                 MonoType *t;
2325                 ainfo = cinfo->args + i;
2326
2327                 in = call->args [i];
2328
2329                 if (sig->hasthis && i == 0)
2330                         t = &mono_defaults.object_class->byval_arg;
2331                 else
2332                         t = sig->params [i - sig->hasthis];
2333
2334                 t = mini_get_underlying_type (t);
2335                 //XXX what about ArgGSharedVtOnStack here?
2336                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2337                         if (!t->byref) {
2338                                 if (t->type == MONO_TYPE_R4)
2339                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2340                                 else if (t->type == MONO_TYPE_R8)
2341                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2342                                 else
2343                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2344                         } else {
2345                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2346                         }
2347                         if (cfg->compute_gc_maps) {
2348                                 MonoInst *def;
2349
2350                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2351                         }
2352                 }
2353         }
2354
2355         /*
2356          * Emit all parameters passed in registers in non-reverse order for better readability
2357          * and to help the optimization in emit_prolog ().
2358          */
2359         for (i = 0; i < n; ++i) {
2360                 ainfo = cinfo->args + i;
2361
2362                 in = call->args [i];
2363
2364                 if (ainfo->storage == ArgInIReg)
2365                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2366         }
2367
2368         for (i = n - 1; i >= 0; --i) {
2369                 MonoType *t;
2370
2371                 ainfo = cinfo->args + i;
2372
2373                 in = call->args [i];
2374
2375                 if (sig->hasthis && i == 0)
2376                         t = &mono_defaults.object_class->byval_arg;
2377                 else
2378                         t = sig->params [i - sig->hasthis];
2379                 t = mini_get_underlying_type (t);
2380
2381                 switch (ainfo->storage) {
2382                 case ArgInIReg:
2383                         /* Already done */
2384                         break;
2385                 case ArgInFloatSSEReg:
2386                 case ArgInDoubleSSEReg:
2387                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2388                         break;
2389                 case ArgOnStack:
2390                 case ArgValuetypeInReg:
2391                 case ArgValuetypeAddrInIReg:
2392                 case ArgGSharedVtInReg:
2393                 case ArgGSharedVtOnStack: {
2394                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2395                                 /* Already emitted above */
2396                                 break;
2397                         //FIXME what about ArgGSharedVtOnStack ?
2398                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2399                                 MonoInst *call_inst = (MonoInst*)call;
2400                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2401                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2402                                 break;
2403                         }
2404
2405                         guint32 align;
2406                         guint32 size;
2407
2408                         if (sig->pinvoke)
2409                                 size = mono_type_native_stack_size (t, &align);
2410                         else {
2411                                 /*
2412                                  * Other backends use mono_type_stack_size (), but that
2413                                  * aligns the size to 8, which is larger than the size of
2414                                  * the source, leading to reads of invalid memory if the
2415                                  * source is at the end of address space.
2416                                  */
2417                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2418                         }
2419
2420                         if (size >= 10000) {
2421                                 /* Avoid asserts in emit_memcpy () */
2422                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2423                                 /* Continue normally */
2424                         }
2425
2426                         if (size > 0) {
2427                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2428                                 arg->sreg1 = in->dreg;
2429                                 arg->klass = mono_class_from_mono_type (t);
2430                                 arg->backend.size = size;
2431                                 arg->inst_p0 = call;
2432                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2433                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2434
2435                                 MONO_ADD_INS (cfg->cbb, arg);
2436                         }
2437                         break;
2438                 }
2439                 default:
2440                         g_assert_not_reached ();
2441                 }
2442
2443                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2444                         /* Emit the signature cookie just before the implicit arguments */
2445                         emit_sig_cookie (cfg, call, cinfo);
2446         }
2447
2448         /* Handle the case where there are no implicit arguments */
2449         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2450                 emit_sig_cookie (cfg, call, cinfo);
2451
2452         switch (cinfo->ret.storage) {
2453         case ArgValuetypeInReg:
2454                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2455                         /*
2456                          * Tell the JIT to use a more efficient calling convention: call using
2457                          * OP_CALL, compute the result location after the call, and save the
2458                          * result there.
2459                          */
2460                         call->vret_in_reg = TRUE;
2461                         /*
2462                          * Nullify the instruction computing the vret addr to enable
2463                          * future optimizations.
2464                          */
2465                         if (call->vret_var)
2466                                 NULLIFY_INS (call->vret_var);
2467                 } else {
2468                         if (call->tail_call)
2469                                 NOT_IMPLEMENTED;
2470                         /*
2471                          * The valuetype is in RAX:RDX after the call, need to be copied to
2472                          * the stack. Push the address here, so the call instruction can
2473                          * access it.
2474                          */
2475                         if (!cfg->arch.vret_addr_loc) {
2476                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2477                                 /* Prevent it from being register allocated or optimized away */
2478                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2479                         }
2480
2481                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2482                 }
2483                 break;
2484         case ArgValuetypeAddrInIReg:
2485         case ArgGsharedvtVariableInReg: {
2486                 MonoInst *vtarg;
2487                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2488                 vtarg->sreg1 = call->vret_var->dreg;
2489                 vtarg->dreg = mono_alloc_preg (cfg);
2490                 MONO_ADD_INS (cfg->cbb, vtarg);
2491
2492                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2493                 break;
2494         }
2495         default:
2496                 break;
2497         }
2498
2499         if (cfg->method->save_lmf) {
2500                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2501                 MONO_ADD_INS (cfg->cbb, arg);
2502         }
2503
2504         call->stack_usage = cinfo->stack_usage;
2505 }
2506
2507 void
2508 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2509 {
2510         MonoInst *arg;
2511         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2512         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2513         int size = ins->backend.size;
2514
2515         switch (ainfo->storage) {
2516         case ArgValuetypeInReg: {
2517                 MonoInst *load;
2518                 int part;
2519
2520                 for (part = 0; part < 2; ++part) {
2521                         if (ainfo->pair_storage [part] == ArgNone)
2522                                 continue;
2523
2524                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2525                         load->inst_basereg = src->dreg;
2526                         load->inst_offset = part * sizeof(mgreg_t);
2527
2528                         switch (ainfo->pair_storage [part]) {
2529                         case ArgInIReg:
2530                                 load->dreg = mono_alloc_ireg (cfg);
2531                                 break;
2532                         case ArgInDoubleSSEReg:
2533                         case ArgInFloatSSEReg:
2534                                 load->dreg = mono_alloc_freg (cfg);
2535                                 break;
2536                         default:
2537                                 g_assert_not_reached ();
2538                         }
2539                         MONO_ADD_INS (cfg->cbb, load);
2540
2541                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2542                 }
2543                 break;
2544         }
2545         case ArgValuetypeAddrInIReg: {
2546                 MonoInst *vtaddr, *load;
2547                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2548
2549                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2550                 cfg->has_indirection = TRUE;
2551                 load->inst_p0 = vtaddr;
2552                 vtaddr->flags |= MONO_INST_INDIRECT;
2553                 load->type = STACK_MP;
2554                 load->klass = vtaddr->klass;
2555                 load->dreg = mono_alloc_ireg (cfg);
2556                 MONO_ADD_INS (cfg->cbb, load);
2557                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2558
2559                 if (ainfo->pair_storage [0] == ArgInIReg) {
2560                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2561                         arg->dreg = mono_alloc_ireg (cfg);
2562                         arg->sreg1 = load->dreg;
2563                         arg->inst_imm = 0;
2564                         MONO_ADD_INS (cfg->cbb, arg);
2565                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2566                 } else {
2567                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2568                 }
2569                 break;
2570         }
2571         case ArgGSharedVtInReg:
2572                 /* Pass by addr */
2573                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2574                 break;
2575         case ArgGSharedVtOnStack:
2576                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2577                 break;
2578         default:
2579                 if (size == 8) {
2580                         int dreg = mono_alloc_ireg (cfg);
2581
2582                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2583                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2584                 } else if (size <= 40) {
2585                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2586                 } else {
2587                         // FIXME: Code growth
2588                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2589                 }
2590
2591                 if (cfg->compute_gc_maps) {
2592                         MonoInst *def;
2593                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2594                 }
2595         }
2596 }
2597
2598 void
2599 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2600 {
2601         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2602
2603         if (ret->type == MONO_TYPE_R4) {
2604                 if (COMPILE_LLVM (cfg))
2605                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2606                 else
2607                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2608                 return;
2609         } else if (ret->type == MONO_TYPE_R8) {
2610                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2611                 return;
2612         }
2613
2614         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2615 }
2616
2617 #endif /* DISABLE_JIT */
2618
2619 #define EMIT_COND_BRANCH(ins,cond,sign) \
2620         if (ins->inst_true_bb->native_offset) { \
2621                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2622         } else { \
2623                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2624                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2625             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2626                         x86_branch8 (code, cond, 0, sign); \
2627                 else \
2628                         x86_branch32 (code, cond, 0, sign); \
2629 }
2630
2631 typedef struct {
2632         MonoMethodSignature *sig;
2633         CallInfo *cinfo;
2634 } ArchDynCallInfo;
2635
2636 static gboolean
2637 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2638 {
2639         int i;
2640
2641 #ifdef HOST_WIN32
2642         return FALSE;
2643 #endif
2644
2645         switch (cinfo->ret.storage) {
2646         case ArgNone:
2647         case ArgInIReg:
2648         case ArgInFloatSSEReg:
2649         case ArgInDoubleSSEReg:
2650                 break;
2651         case ArgValuetypeInReg: {
2652                 ArgInfo *ainfo = &cinfo->ret;
2653
2654                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2655                         return FALSE;
2656                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2657                         return FALSE;
2658                 break;
2659         }
2660         default:
2661                 return FALSE;
2662         }
2663
2664         for (i = 0; i < cinfo->nargs; ++i) {
2665                 ArgInfo *ainfo = &cinfo->args [i];
2666                 switch (ainfo->storage) {
2667                 case ArgInIReg:
2668                 case ArgInFloatSSEReg:
2669                 case ArgInDoubleSSEReg:
2670                         break;
2671                 case ArgValuetypeInReg:
2672                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2673                                 return FALSE;
2674                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2675                                 return FALSE;
2676                         break;
2677                 default:
2678                         return FALSE;
2679                 }
2680         }
2681
2682         return TRUE;
2683 }
2684
2685 /*
2686  * mono_arch_dyn_call_prepare:
2687  *
2688  *   Return a pointer to an arch-specific structure which contains information
2689  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2690  * supported for SIG.
2691  * This function is equivalent to ffi_prep_cif in libffi.
2692  */
2693 MonoDynCallInfo*
2694 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2695 {
2696         ArchDynCallInfo *info;
2697         CallInfo *cinfo;
2698
2699         cinfo = get_call_info (NULL, sig);
2700
2701         if (!dyn_call_supported (sig, cinfo)) {
2702                 g_free (cinfo);
2703                 return NULL;
2704         }
2705
2706         info = g_new0 (ArchDynCallInfo, 1);
2707         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2708         info->sig = sig;
2709         info->cinfo = cinfo;
2710
2711         return (MonoDynCallInfo*)info;
2712 }
2713
2714 /*
2715  * mono_arch_dyn_call_free:
2716  *
2717  *   Free a MonoDynCallInfo structure.
2718  */
2719 void
2720 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2721 {
2722         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2723
2724         g_free (ainfo->cinfo);
2725         g_free (ainfo);
2726 }
2727
2728 #if !defined(__native_client__)
2729 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2730 #define GREG_TO_PTR(greg) (gpointer)(greg)
2731 #else
2732 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2733 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2734 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2735 #endif
2736
2737 /*
2738  * mono_arch_get_start_dyn_call:
2739  *
2740  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2741  * store the result into BUF.
2742  * ARGS should be an array of pointers pointing to the arguments.
2743  * RET should point to a memory buffer large enought to hold the result of the
2744  * call.
2745  * This function should be as fast as possible, any work which does not depend
2746  * on the actual values of the arguments should be done in
2747  * mono_arch_dyn_call_prepare ().
2748  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2749  * libffi.
2750  */
2751 void
2752 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2753 {
2754         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2755         DynCallArgs *p = (DynCallArgs*)buf;
2756         int arg_index, greg, freg, i, pindex;
2757         MonoMethodSignature *sig = dinfo->sig;
2758         int buffer_offset = 0;
2759
2760         g_assert (buf_len >= sizeof (DynCallArgs));
2761
2762         p->res = 0;
2763         p->ret = ret;
2764
2765         arg_index = 0;
2766         greg = 0;
2767         freg = 0;
2768         pindex = 0;
2769
2770         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2771                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2772                 if (!sig->hasthis)
2773                         pindex = 1;
2774         }
2775
2776         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2777                 p->regs [greg ++] = PTR_TO_GREG(ret);
2778
2779         for (i = pindex; i < sig->param_count; i++) {
2780                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2781                 gpointer *arg = args [arg_index ++];
2782
2783                 if (t->byref) {
2784                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2785                         continue;
2786                 }
2787
2788                 switch (t->type) {
2789                 case MONO_TYPE_STRING:
2790                 case MONO_TYPE_CLASS:
2791                 case MONO_TYPE_ARRAY:
2792                 case MONO_TYPE_SZARRAY:
2793                 case MONO_TYPE_OBJECT:
2794                 case MONO_TYPE_PTR:
2795                 case MONO_TYPE_I:
2796                 case MONO_TYPE_U:
2797 #if !defined(__mono_ilp32__)
2798                 case MONO_TYPE_I8:
2799                 case MONO_TYPE_U8:
2800 #endif
2801                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2802                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2803                         break;
2804 #if defined(__mono_ilp32__)
2805                 case MONO_TYPE_I8:
2806                 case MONO_TYPE_U8:
2807                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2808                         p->regs [greg ++] = *(guint64*)(arg);
2809                         break;
2810 #endif
2811                 case MONO_TYPE_U1:
2812                         p->regs [greg ++] = *(guint8*)(arg);
2813                         break;
2814                 case MONO_TYPE_I1:
2815                         p->regs [greg ++] = *(gint8*)(arg);
2816                         break;
2817                 case MONO_TYPE_I2:
2818                         p->regs [greg ++] = *(gint16*)(arg);
2819                         break;
2820                 case MONO_TYPE_U2:
2821                         p->regs [greg ++] = *(guint16*)(arg);
2822                         break;
2823                 case MONO_TYPE_I4:
2824                         p->regs [greg ++] = *(gint32*)(arg);
2825                         break;
2826                 case MONO_TYPE_U4:
2827                         p->regs [greg ++] = *(guint32*)(arg);
2828                         break;
2829                 case MONO_TYPE_R4: {
2830                         double d;
2831
2832                         *(float*)&d = *(float*)(arg);
2833                         p->has_fp = 1;
2834                         p->fregs [freg ++] = d;
2835                         break;
2836                 }
2837                 case MONO_TYPE_R8:
2838                         p->has_fp = 1;
2839                         p->fregs [freg ++] = *(double*)(arg);
2840                         break;
2841                 case MONO_TYPE_GENERICINST:
2842                     if (MONO_TYPE_IS_REFERENCE (t)) {
2843                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2844                                 break;
2845                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2846                                         MonoClass *klass = mono_class_from_mono_type (t);
2847                                         guint8 *nullable_buf;
2848                                         int size;
2849
2850                                         size = mono_class_value_size (klass, NULL);
2851                                         nullable_buf = p->buffer + buffer_offset;
2852                                         buffer_offset += size;
2853                                         g_assert (buffer_offset <= 256);
2854
2855                                         /* The argument pointed to by arg is either a boxed vtype or null */
2856                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2857
2858                                         arg = (gpointer*)nullable_buf;
2859                                         /* Fall though */
2860
2861                         } else {
2862                                 /* Fall through */
2863                         }
2864                 case MONO_TYPE_VALUETYPE: {
2865                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2866
2867                         g_assert (ainfo->storage == ArgValuetypeInReg);
2868                         if (ainfo->pair_storage [0] != ArgNone) {
2869                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2870                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2871                         }
2872                         if (ainfo->pair_storage [1] != ArgNone) {
2873                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2874                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2875                         }
2876                         break;
2877                 }
2878                 default:
2879                         g_assert_not_reached ();
2880                 }
2881         }
2882
2883         g_assert (greg <= PARAM_REGS);
2884 }
2885
2886 /*
2887  * mono_arch_finish_dyn_call:
2888  *
2889  *   Store the result of a dyn call into the return value buffer passed to
2890  * start_dyn_call ().
2891  * This function should be as fast as possible, any work which does not depend
2892  * on the actual values of the arguments should be done in
2893  * mono_arch_dyn_call_prepare ().
2894  */
2895 void
2896 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2897 {
2898         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2899         MonoMethodSignature *sig = dinfo->sig;
2900         DynCallArgs *dargs = (DynCallArgs*)buf;
2901         guint8 *ret = dargs->ret;
2902         mgreg_t res = dargs->res;
2903         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2904
2905         switch (sig_ret->type) {
2906         case MONO_TYPE_VOID:
2907                 *(gpointer*)ret = NULL;
2908                 break;
2909         case MONO_TYPE_STRING:
2910         case MONO_TYPE_CLASS:
2911         case MONO_TYPE_ARRAY:
2912         case MONO_TYPE_SZARRAY:
2913         case MONO_TYPE_OBJECT:
2914         case MONO_TYPE_I:
2915         case MONO_TYPE_U:
2916         case MONO_TYPE_PTR:
2917                 *(gpointer*)ret = GREG_TO_PTR(res);
2918                 break;
2919         case MONO_TYPE_I1:
2920                 *(gint8*)ret = res;
2921                 break;
2922         case MONO_TYPE_U1:
2923                 *(guint8*)ret = res;
2924                 break;
2925         case MONO_TYPE_I2:
2926                 *(gint16*)ret = res;
2927                 break;
2928         case MONO_TYPE_U2:
2929                 *(guint16*)ret = res;
2930                 break;
2931         case MONO_TYPE_I4:
2932                 *(gint32*)ret = res;
2933                 break;
2934         case MONO_TYPE_U4:
2935                 *(guint32*)ret = res;
2936                 break;
2937         case MONO_TYPE_I8:
2938                 *(gint64*)ret = res;
2939                 break;
2940         case MONO_TYPE_U8:
2941                 *(guint64*)ret = res;
2942                 break;
2943         case MONO_TYPE_R4:
2944                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2945                 break;
2946         case MONO_TYPE_R8:
2947                 *(double*)ret = dargs->fregs [0];
2948                 break;
2949         case MONO_TYPE_GENERICINST:
2950                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2951                         *(gpointer*)ret = GREG_TO_PTR(res);
2952                         break;
2953                 } else {
2954                         /* Fall through */
2955                 }
2956         case MONO_TYPE_VALUETYPE:
2957                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2958                         /* Nothing to do */
2959                 } else {
2960                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2961
2962                         g_assert (ainfo->storage == ArgValuetypeInReg);
2963
2964                         if (ainfo->pair_storage [0] != ArgNone) {
2965                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2966                                 ((mgreg_t*)ret)[0] = res;
2967                         }
2968
2969                         g_assert (ainfo->pair_storage [1] == ArgNone);
2970                 }
2971                 break;
2972         default:
2973                 g_assert_not_reached ();
2974         }
2975 }
2976
2977 /* emit an exception if condition is fail */
2978 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2979         do {                                                        \
2980                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2981                 if (tins == NULL) {                                                                             \
2982                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2983                                         MONO_PATCH_INFO_EXC, exc_name);  \
2984                         x86_branch32 (code, cond, 0, signed);               \
2985                 } else {        \
2986                         EMIT_COND_BRANCH (tins, cond, signed);  \
2987                 }                       \
2988         } while (0);
2989
2990 #define EMIT_FPCOMPARE(code) do { \
2991         amd64_fcompp (code); \
2992         amd64_fnstsw (code); \
2993 } while (0);
2994
2995 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2996     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2997         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2998         amd64_ ##op (code); \
2999         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3000         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3001 } while (0);
3002
3003 static guint8*
3004 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3005 {
3006         gboolean no_patch = FALSE;
3007
3008         /*
3009          * FIXME: Add support for thunks
3010          */
3011         {
3012                 gboolean near_call = FALSE;
3013
3014                 /*
3015                  * Indirect calls are expensive so try to make a near call if possible.
3016                  * The caller memory is allocated by the code manager so it is
3017                  * guaranteed to be at a 32 bit offset.
3018                  */
3019
3020                 if (patch_type != MONO_PATCH_INFO_ABS) {
3021                         /* The target is in memory allocated using the code manager */
3022                         near_call = TRUE;
3023
3024                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3025                                 if (((MonoMethod*)data)->klass->image->aot_module)
3026                                         /* The callee might be an AOT method */
3027                                         near_call = FALSE;
3028                                 if (((MonoMethod*)data)->dynamic)
3029                                         /* The target is in malloc-ed memory */
3030                                         near_call = FALSE;
3031                         }
3032
3033                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3034                                 /*
3035                                  * The call might go directly to a native function without
3036                                  * the wrapper.
3037                                  */
3038                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3039                                 if (mi) {
3040                                         gconstpointer target = mono_icall_get_wrapper (mi);
3041                                         if ((((guint64)target) >> 32) != 0)
3042                                                 near_call = FALSE;
3043                                 }
3044                         }
3045                 }
3046                 else {
3047                         MonoJumpInfo *jinfo = NULL;
3048
3049                         if (cfg->abs_patches)
3050                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3051                         if (jinfo) {
3052                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3053                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3054                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3055                                                 near_call = TRUE;
3056                                         no_patch = TRUE;
3057                                 } else {
3058                                         /*
3059                                          * This is not really an optimization, but required because the
3060                                          * generic class init trampolines use R11 to pass the vtable.
3061                                          */
3062                                         near_call = TRUE;
3063                                 }
3064                         } else {
3065                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3066                                 if (info) {
3067                                         if (info->func == info->wrapper) {
3068                                                 /* No wrapper */
3069                                                 if ((((guint64)info->func) >> 32) == 0)
3070                                                         near_call = TRUE;
3071                                         }
3072                                         else {
3073                                                 /* See the comment in mono_codegen () */
3074                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3075                                                         near_call = TRUE;
3076                                         }
3077                                 }
3078                                 else if ((((guint64)data) >> 32) == 0) {
3079                                         near_call = TRUE;
3080                                         no_patch = TRUE;
3081                                 }
3082                         }
3083                 }
3084
3085                 if (cfg->method->dynamic)
3086                         /* These methods are allocated using malloc */
3087                         near_call = FALSE;
3088
3089 #ifdef MONO_ARCH_NOMAP32BIT
3090                 near_call = FALSE;
3091 #endif
3092 #if defined(__native_client__)
3093                 /* Always use near_call == TRUE for Native Client */
3094                 near_call = TRUE;
3095 #endif
3096                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3097                 if (optimize_for_xen)
3098                         near_call = FALSE;
3099
3100                 if (cfg->compile_aot) {
3101                         near_call = TRUE;
3102                         no_patch = TRUE;
3103                 }
3104
3105                 if (near_call) {
3106                         /*
3107                          * Align the call displacement to an address divisible by 4 so it does
3108                          * not span cache lines. This is required for code patching to work on SMP
3109                          * systems.
3110                          */
3111                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3112                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3113                                 amd64_padding (code, pad_size);
3114                         }
3115                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3116                         amd64_call_code (code, 0);
3117                 }
3118                 else {
3119                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3120                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3121                         amd64_call_reg (code, GP_SCRATCH_REG);
3122                 }
3123         }
3124
3125         return code;
3126 }
3127
3128 static inline guint8*
3129 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3130 {
3131 #ifdef TARGET_WIN32
3132         if (win64_adjust_stack)
3133                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3134 #endif
3135         code = emit_call_body (cfg, code, patch_type, data);
3136 #ifdef TARGET_WIN32
3137         if (win64_adjust_stack)
3138                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3139 #endif
3140
3141         return code;
3142 }
3143
3144 static inline int
3145 store_membase_imm_to_store_membase_reg (int opcode)
3146 {
3147         switch (opcode) {
3148         case OP_STORE_MEMBASE_IMM:
3149                 return OP_STORE_MEMBASE_REG;
3150         case OP_STOREI4_MEMBASE_IMM:
3151                 return OP_STOREI4_MEMBASE_REG;
3152         case OP_STOREI8_MEMBASE_IMM:
3153                 return OP_STOREI8_MEMBASE_REG;
3154         }
3155
3156         return -1;
3157 }
3158
3159 #ifndef DISABLE_JIT
3160
3161 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3162
3163 /*
3164  * mono_arch_peephole_pass_1:
3165  *
3166  *   Perform peephole opts which should/can be performed before local regalloc
3167  */
3168 void
3169 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3170 {
3171         MonoInst *ins, *n;
3172
3173         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3174                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3175
3176                 switch (ins->opcode) {
3177                 case OP_ADD_IMM:
3178                 case OP_IADD_IMM:
3179                 case OP_LADD_IMM:
3180                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3181                                 /*
3182                                  * X86_LEA is like ADD, but doesn't have the
3183                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3184                                  * its operand to 64 bit.
3185                                  */
3186                                 ins->opcode = OP_X86_LEA_MEMBASE;
3187                                 ins->inst_basereg = ins->sreg1;
3188                         }
3189                         break;
3190                 case OP_LXOR:
3191                 case OP_IXOR:
3192                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3193                                 MonoInst *ins2;
3194
3195                                 /*
3196                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3197                                  * the latter has length 2-3 instead of 6 (reverse constant
3198                                  * propagation). These instruction sequences are very common
3199                                  * in the initlocals bblock.
3200                                  */
3201                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3202                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3203                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3204                                                 ins2->sreg1 = ins->dreg;
3205                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3206                                                 /* Continue */
3207                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3208                                                 NULLIFY_INS (ins2);
3209                                                 /* Continue */
3210                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3211                                                 /* Continue */
3212                                         } else {
3213                                                 break;
3214                                         }
3215                                 }
3216                         }
3217                         break;
3218                 case OP_COMPARE_IMM:
3219                 case OP_LCOMPARE_IMM:
3220                         /* OP_COMPARE_IMM (reg, 0)
3221                          * -->
3222                          * OP_AMD64_TEST_NULL (reg)
3223                          */
3224                         if (!ins->inst_imm)
3225                                 ins->opcode = OP_AMD64_TEST_NULL;
3226                         break;
3227                 case OP_ICOMPARE_IMM:
3228                         if (!ins->inst_imm)
3229                                 ins->opcode = OP_X86_TEST_NULL;
3230                         break;
3231                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3232                         /*
3233                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3234                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3235                          * -->
3236                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3237                          * OP_COMPARE_IMM reg, imm
3238                          *
3239                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3240                          */
3241                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3242                             ins->inst_basereg == last_ins->inst_destbasereg &&
3243                             ins->inst_offset == last_ins->inst_offset) {
3244                                         ins->opcode = OP_ICOMPARE_IMM;
3245                                         ins->sreg1 = last_ins->sreg1;
3246
3247                                         /* check if we can remove cmp reg,0 with test null */
3248                                         if (!ins->inst_imm)
3249                                                 ins->opcode = OP_X86_TEST_NULL;
3250                                 }
3251
3252                         break;
3253                 }
3254
3255                 mono_peephole_ins (bb, ins);
3256         }
3257 }
3258
3259 void
3260 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3261 {
3262         MonoInst *ins, *n;
3263
3264         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3265                 switch (ins->opcode) {
3266                 case OP_ICONST:
3267                 case OP_I8CONST: {
3268                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3269                         /* reg = 0 -> XOR (reg, reg) */
3270                         /* XOR sets cflags on x86, so we cant do it always */
3271                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3272                                 ins->opcode = OP_LXOR;
3273                                 ins->sreg1 = ins->dreg;
3274                                 ins->sreg2 = ins->dreg;
3275                                 /* Fall through */
3276                         } else {
3277                                 break;
3278                         }
3279                 }
3280                 case OP_LXOR:
3281                         /*
3282                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3283                          * 0 result into 64 bits.
3284                          */
3285                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3286                                 ins->opcode = OP_IXOR;
3287                         }
3288                         /* Fall through */
3289                 case OP_IXOR:
3290                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3291                                 MonoInst *ins2;
3292
3293                                 /*
3294                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3295                                  * the latter has length 2-3 instead of 6 (reverse constant
3296                                  * propagation). These instruction sequences are very common
3297                                  * in the initlocals bblock.
3298                                  */
3299                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3300                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3301                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3302                                                 ins2->sreg1 = ins->dreg;
3303                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3304                                                 /* Continue */
3305                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3306                                                 NULLIFY_INS (ins2);
3307                                                 /* Continue */
3308                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3309                                                 /* Continue */
3310                                         } else {
3311                                                 break;
3312                                         }
3313                                 }
3314                         }
3315                         break;
3316                 case OP_IADD_IMM:
3317                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3318                                 ins->opcode = OP_X86_INC_REG;
3319                         break;
3320                 case OP_ISUB_IMM:
3321                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3322                                 ins->opcode = OP_X86_DEC_REG;
3323                         break;
3324                 }
3325
3326                 mono_peephole_ins (bb, ins);
3327         }
3328 }
3329
3330 #define NEW_INS(cfg,ins,dest,op) do {   \
3331                 MONO_INST_NEW ((cfg), (dest), (op)); \
3332         (dest)->cil_code = (ins)->cil_code; \
3333         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3334         } while (0)
3335
3336 /*
3337  * mono_arch_lowering_pass:
3338  *
3339  *  Converts complex opcodes into simpler ones so that each IR instruction
3340  * corresponds to one machine instruction.
3341  */
3342 void
3343 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3344 {
3345         MonoInst *ins, *n, *temp;
3346
3347         /*
3348          * FIXME: Need to add more instructions, but the current machine
3349          * description can't model some parts of the composite instructions like
3350          * cdq.
3351          */
3352         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3353                 switch (ins->opcode) {
3354                 case OP_DIV_IMM:
3355                 case OP_REM_IMM:
3356                 case OP_IDIV_IMM:
3357                 case OP_IDIV_UN_IMM:
3358                 case OP_IREM_UN_IMM:
3359                 case OP_LREM_IMM:
3360                 case OP_IREM_IMM:
3361                         mono_decompose_op_imm (cfg, bb, ins);
3362                         break;
3363                 case OP_COMPARE_IMM:
3364                 case OP_LCOMPARE_IMM:
3365                         if (!amd64_use_imm32 (ins->inst_imm)) {
3366                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3367                                 temp->inst_c0 = ins->inst_imm;
3368                                 temp->dreg = mono_alloc_ireg (cfg);
3369                                 ins->opcode = OP_COMPARE;
3370                                 ins->sreg2 = temp->dreg;
3371                         }
3372                         break;
3373 #ifndef __mono_ilp32__
3374                 case OP_LOAD_MEMBASE:
3375 #endif
3376                 case OP_LOADI8_MEMBASE:
3377 #ifndef __native_client_codegen__
3378                 /*  Don't generate memindex opcodes (to simplify */
3379                 /*  read sandboxing) */
3380                         if (!amd64_use_imm32 (ins->inst_offset)) {
3381                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3382                                 temp->inst_c0 = ins->inst_offset;
3383                                 temp->dreg = mono_alloc_ireg (cfg);
3384                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3385                                 ins->inst_indexreg = temp->dreg;
3386                         }
3387 #endif
3388                         break;
3389 #ifndef __mono_ilp32__
3390                 case OP_STORE_MEMBASE_IMM:
3391 #endif
3392                 case OP_STOREI8_MEMBASE_IMM:
3393                         if (!amd64_use_imm32 (ins->inst_imm)) {
3394                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3395                                 temp->inst_c0 = ins->inst_imm;
3396                                 temp->dreg = mono_alloc_ireg (cfg);
3397                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3398                                 ins->sreg1 = temp->dreg;
3399                         }
3400                         break;
3401 #ifdef MONO_ARCH_SIMD_INTRINSICS
3402                 case OP_EXPAND_I1: {
3403                                 int temp_reg1 = mono_alloc_ireg (cfg);
3404                                 int temp_reg2 = mono_alloc_ireg (cfg);
3405                                 int original_reg = ins->sreg1;
3406
3407                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3408                                 temp->sreg1 = original_reg;
3409                                 temp->dreg = temp_reg1;
3410
3411                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3412                                 temp->sreg1 = temp_reg1;
3413                                 temp->dreg = temp_reg2;
3414                                 temp->inst_imm = 8;
3415
3416                                 NEW_INS (cfg, ins, temp, OP_LOR);
3417                                 temp->sreg1 = temp->dreg = temp_reg2;
3418                                 temp->sreg2 = temp_reg1;
3419
3420                                 ins->opcode = OP_EXPAND_I2;
3421                                 ins->sreg1 = temp_reg2;
3422                         }
3423                         break;
3424 #endif
3425                 default:
3426                         break;
3427                 }
3428         }
3429
3430         bb->max_vreg = cfg->next_vreg;
3431 }
3432
3433 static const int
3434 branch_cc_table [] = {
3435         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3436         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3437         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3438 };
3439
3440 /* Maps CMP_... constants to X86_CC_... constants */
3441 static const int
3442 cc_table [] = {
3443         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3444         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3445 };
3446
3447 static const int
3448 cc_signed_table [] = {
3449         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3450         FALSE, FALSE, FALSE, FALSE
3451 };
3452
3453 /*#include "cprop.c"*/
3454
3455 static unsigned char*
3456 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3457 {
3458         if (size == 8)
3459                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3460         else
3461                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3462
3463         if (size == 1)
3464                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3465         else if (size == 2)
3466                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3467         return code;
3468 }
3469
3470 static unsigned char*
3471 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3472 {
3473         int sreg = tree->sreg1;
3474         int need_touch = FALSE;
3475
3476 #if defined(TARGET_WIN32)
3477         need_touch = TRUE;
3478 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3479         if (!tree->flags & MONO_INST_INIT)
3480                 need_touch = TRUE;
3481 #endif
3482
3483         if (need_touch) {
3484                 guint8* br[5];
3485
3486                 /*
3487                  * Under Windows:
3488                  * If requested stack size is larger than one page,
3489                  * perform stack-touch operation
3490                  */
3491                 /*
3492                  * Generate stack probe code.
3493                  * Under Windows, it is necessary to allocate one page at a time,
3494                  * "touching" stack after each successful sub-allocation. This is
3495                  * because of the way stack growth is implemented - there is a
3496                  * guard page before the lowest stack page that is currently commited.
3497                  * Stack normally grows sequentially so OS traps access to the
3498                  * guard page and commits more pages when needed.
3499                  */
3500                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3501                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3502
3503                 br[2] = code; /* loop */
3504                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3505                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3506                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3507                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3508                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3509                 amd64_patch (br[3], br[2]);
3510                 amd64_test_reg_reg (code, sreg, sreg);
3511                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3512                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3513
3514                 br[1] = code; x86_jump8 (code, 0);
3515
3516                 amd64_patch (br[0], code);
3517                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3518                 amd64_patch (br[1], code);
3519                 amd64_patch (br[4], code);
3520         }
3521         else
3522                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3523
3524         if (tree->flags & MONO_INST_INIT) {
3525                 int offset = 0;
3526                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3527                         amd64_push_reg (code, AMD64_RAX);
3528                         offset += 8;
3529                 }
3530                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3531                         amd64_push_reg (code, AMD64_RCX);
3532                         offset += 8;
3533                 }
3534                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3535                         amd64_push_reg (code, AMD64_RDI);
3536                         offset += 8;
3537                 }
3538
3539                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3540                 if (sreg != AMD64_RCX)
3541                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3542                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3543
3544                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3545                 if (cfg->param_area)
3546                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3547                 amd64_cld (code);
3548 #if defined(__default_codegen__)
3549                 amd64_prefix (code, X86_REP_PREFIX);
3550                 amd64_stosl (code);
3551 #elif defined(__native_client_codegen__)
3552                 /* NaCl stos pseudo-instruction */
3553                 amd64_codegen_pre(code);
3554                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3555                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3556                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3557                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3558                 amd64_prefix (code, X86_REP_PREFIX);
3559                 amd64_stosl (code);
3560                 amd64_codegen_post(code);
3561 #endif /* __native_client_codegen__ */
3562
3563                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3564                         amd64_pop_reg (code, AMD64_RDI);
3565                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3566                         amd64_pop_reg (code, AMD64_RCX);
3567                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3568                         amd64_pop_reg (code, AMD64_RAX);
3569         }
3570         return code;
3571 }
3572
3573 static guint8*
3574 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3575 {
3576         CallInfo *cinfo;
3577         guint32 quad;
3578
3579         /* Move return value to the target register */
3580         /* FIXME: do this in the local reg allocator */
3581         switch (ins->opcode) {
3582         case OP_CALL:
3583         case OP_CALL_REG:
3584         case OP_CALL_MEMBASE:
3585         case OP_LCALL:
3586         case OP_LCALL_REG:
3587         case OP_LCALL_MEMBASE:
3588                 g_assert (ins->dreg == AMD64_RAX);
3589                 break;
3590         case OP_FCALL:
3591         case OP_FCALL_REG:
3592         case OP_FCALL_MEMBASE: {
3593                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3594                 if (rtype->type == MONO_TYPE_R4) {
3595                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3596                 }
3597                 else {
3598                         if (ins->dreg != AMD64_XMM0)
3599                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3600                 }
3601                 break;
3602         }
3603         case OP_RCALL:
3604         case OP_RCALL_REG:
3605         case OP_RCALL_MEMBASE:
3606                 if (ins->dreg != AMD64_XMM0)
3607                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3608                 break;
3609         case OP_VCALL:
3610         case OP_VCALL_REG:
3611         case OP_VCALL_MEMBASE:
3612         case OP_VCALL2:
3613         case OP_VCALL2_REG:
3614         case OP_VCALL2_MEMBASE:
3615                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3616                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3617                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3618
3619                         /* Load the destination address */
3620                         g_assert (loc->opcode == OP_REGOFFSET);
3621                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3622
3623                         for (quad = 0; quad < 2; quad ++) {
3624                                 switch (cinfo->ret.pair_storage [quad]) {
3625                                 case ArgInIReg:
3626                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3627                                         break;
3628                                 case ArgInFloatSSEReg:
3629                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3630                                         break;
3631                                 case ArgInDoubleSSEReg:
3632                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3633                                         break;
3634                                 case ArgNone:
3635                                         break;
3636                                 default:
3637                                         NOT_IMPLEMENTED;
3638                                 }
3639                         }
3640                 }
3641                 break;
3642         }
3643
3644         return code;
3645 }
3646
3647 #endif /* DISABLE_JIT */
3648
3649 #ifdef __APPLE__
3650 static int tls_gs_offset;
3651 #endif
3652
3653 gboolean
3654 mono_amd64_have_tls_get (void)
3655 {
3656 #ifdef TARGET_MACH
3657         static gboolean have_tls_get = FALSE;
3658         static gboolean inited = FALSE;
3659
3660         if (inited)
3661                 return have_tls_get;
3662
3663 #if MONO_HAVE_FAST_TLS
3664         guint8 *ins = (guint8*)pthread_getspecific;
3665
3666         /*
3667          * We're looking for these two instructions:
3668          *
3669          * mov    %gs:[offset](,%rdi,8),%rax
3670          * retq
3671          */
3672         have_tls_get = ins [0] == 0x65 &&
3673                        ins [1] == 0x48 &&
3674                        ins [2] == 0x8b &&
3675                        ins [3] == 0x04 &&
3676                        ins [4] == 0xfd &&
3677                        ins [6] == 0x00 &&
3678                        ins [7] == 0x00 &&
3679                        ins [8] == 0x00 &&
3680                        ins [9] == 0xc3;
3681
3682         tls_gs_offset = ins[5];
3683
3684         /*
3685          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3686          * For that version we're looking for these instructions:
3687          *
3688          * pushq  %rbp
3689          * movq   %rsp, %rbp
3690          * mov    %gs:[offset](,%rdi,8),%rax
3691          * popq   %rbp
3692          * retq
3693          */
3694         if (!have_tls_get) {
3695                 have_tls_get = ins [0] == 0x55 &&
3696                                ins [1] == 0x48 &&
3697                                ins [2] == 0x89 &&
3698                                ins [3] == 0xe5 &&
3699                                ins [4] == 0x65 &&
3700                                ins [5] == 0x48 &&
3701                                ins [6] == 0x8b &&
3702                                ins [7] == 0x04 &&
3703                                ins [8] == 0xfd &&
3704                                ins [10] == 0x00 &&
3705                                ins [11] == 0x00 &&
3706                                ins [12] == 0x00 &&
3707                                ins [13] == 0x5d &&
3708                                ins [14] == 0xc3;
3709
3710                 tls_gs_offset = ins[9];
3711         }
3712 #endif
3713
3714         inited = TRUE;
3715
3716         return have_tls_get;
3717 #elif defined(TARGET_ANDROID)
3718         return FALSE;
3719 #else
3720         return TRUE;
3721 #endif
3722 }
3723
3724 int
3725 mono_amd64_get_tls_gs_offset (void)
3726 {
3727 #ifdef TARGET_OSX
3728         return tls_gs_offset;
3729 #else
3730         g_assert_not_reached ();
3731         return -1;
3732 #endif
3733 }
3734
3735 /*
3736  * mono_amd64_emit_tls_get:
3737  * @code: buffer to store code to
3738  * @dreg: hard register where to place the result
3739  * @tls_offset: offset info
3740  *
3741  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3742  * the dreg register the item in the thread local storage identified
3743  * by tls_offset.
3744  *
3745  * Returns: a pointer to the end of the stored code
3746  */
3747 guint8*
3748 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3749 {
3750 #ifdef TARGET_WIN32
3751         if (tls_offset < 64) {
3752                 x86_prefix (code, X86_GS_PREFIX);
3753                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3754         } else {
3755                 guint8 *buf [16];
3756
3757                 g_assert (tls_offset < 0x440);
3758                 /* Load TEB->TlsExpansionSlots */
3759                 x86_prefix (code, X86_GS_PREFIX);
3760                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3761                 amd64_test_reg_reg (code, dreg, dreg);
3762                 buf [0] = code;
3763                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3764                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3765                 amd64_patch (buf [0], code);
3766         }
3767 #elif defined(__APPLE__)
3768         x86_prefix (code, X86_GS_PREFIX);
3769         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3770 #else
3771         if (optimize_for_xen) {
3772                 x86_prefix (code, X86_FS_PREFIX);
3773                 amd64_mov_reg_mem (code, dreg, 0, 8);
3774                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3775         } else {
3776                 x86_prefix (code, X86_FS_PREFIX);
3777                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3778         }
3779 #endif
3780         return code;
3781 }
3782
3783 static guint8*
3784 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3785 {
3786         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3787 #ifdef TARGET_OSX
3788         if (dreg != offset_reg)
3789                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3790         amd64_prefix (code, X86_GS_PREFIX);
3791         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3792 #elif defined(__linux__)
3793         int tmpreg = -1;
3794
3795         if (dreg == offset_reg) {
3796                 /* Use a temporary reg by saving it to the redzone */
3797                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3798                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3799                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3800                 offset_reg = tmpreg;
3801         }
3802         x86_prefix (code, X86_FS_PREFIX);
3803         amd64_mov_reg_mem (code, dreg, 0, 8);
3804         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3805         if (tmpreg != -1)
3806                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3807 #else
3808         g_assert_not_reached ();
3809 #endif
3810         return code;
3811 }
3812
3813 static guint8*
3814 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3815 {
3816 #ifdef TARGET_WIN32
3817         g_assert_not_reached ();
3818 #elif defined(__APPLE__)
3819         x86_prefix (code, X86_GS_PREFIX);
3820         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3821 #else
3822         g_assert (!optimize_for_xen);
3823         x86_prefix (code, X86_FS_PREFIX);
3824         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3825 #endif
3826         return code;
3827 }
3828
3829 static guint8*
3830 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3831 {
3832         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3833 #ifdef TARGET_WIN32
3834         g_assert_not_reached ();
3835 #elif defined(__APPLE__)
3836         x86_prefix (code, X86_GS_PREFIX);
3837         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3838 #else
3839         x86_prefix (code, X86_FS_PREFIX);
3840         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3841 #endif
3842         return code;
3843 }
3844
3845  /*
3846  * mono_arch_translate_tls_offset:
3847  *
3848  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3849  */
3850 int
3851 mono_arch_translate_tls_offset (int offset)
3852 {
3853 #ifdef __APPLE__
3854         return tls_gs_offset + (offset * 8);
3855 #else
3856         return offset;
3857 #endif
3858 }
3859
3860 /*
3861  * emit_setup_lmf:
3862  *
3863  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3864  */
3865 static guint8*
3866 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3867 {
3868         /*
3869          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3870          */
3871         /*
3872          * sp is saved right before calls but we need to save it here too so
3873          * async stack walks would work.
3874          */
3875         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3876         /* Save rbp */
3877         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3878         if (cfg->arch.omit_fp && cfa_offset != -1)
3879                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3880
3881         /* These can't contain refs */
3882         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3883         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3884         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3885         /* These are handled automatically by the stack marking code */
3886         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3887
3888         return code;
3889 }
3890
3891 /* benchmark and set based on cpu */
3892 #define LOOP_ALIGNMENT 8
3893 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3894
3895 #ifndef DISABLE_JIT
3896 void
3897 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3898 {
3899         MonoInst *ins;
3900         MonoCallInst *call;
3901         guint offset;
3902         guint8 *code = cfg->native_code + cfg->code_len;
3903         int max_len;
3904
3905         /* Fix max_offset estimate for each successor bb */
3906         if (cfg->opt & MONO_OPT_BRANCH) {
3907                 int current_offset = cfg->code_len;
3908                 MonoBasicBlock *current_bb;
3909                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3910                         current_bb->max_offset = current_offset;
3911                         current_offset += current_bb->max_length;
3912                 }
3913         }
3914
3915         if (cfg->opt & MONO_OPT_LOOP) {
3916                 int pad, align = LOOP_ALIGNMENT;
3917                 /* set alignment depending on cpu */
3918                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3919                         pad = align - pad;
3920                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3921                         amd64_padding (code, pad);
3922                         cfg->code_len += pad;
3923                         bb->native_offset = cfg->code_len;
3924                 }
3925         }
3926
3927 #if defined(__native_client_codegen__)
3928         /* For Native Client, all indirect call/jump targets must be */
3929         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3930         /* indirectly as well.                                       */
3931         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3932                                       (bb->flags & BB_EXCEPTION_HANDLER);
3933
3934         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3935                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3936                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3937                 cfg->code_len += pad;
3938                 bb->native_offset = cfg->code_len;
3939         }
3940 #endif  /*__native_client_codegen__*/
3941
3942         if (cfg->verbose_level > 2)
3943                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3944
3945         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3946                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3947                 g_assert (!cfg->compile_aot);
3948
3949                 cov->data [bb->dfn].cil_code = bb->cil_code;
3950                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3951                 /* this is not thread save, but good enough */
3952                 amd64_inc_membase (code, AMD64_R11, 0);
3953         }
3954
3955         offset = code - cfg->native_code;
3956
3957         mono_debug_open_block (cfg, bb, offset);
3958
3959     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3960                 x86_breakpoint (code);
3961
3962         MONO_BB_FOR_EACH_INS (bb, ins) {
3963                 offset = code - cfg->native_code;
3964
3965                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3966
3967 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3968
3969                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3970                         cfg->code_size *= 2;
3971                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3972                         code = cfg->native_code + offset;
3973                         cfg->stat_code_reallocs++;
3974                 }
3975
3976                 if (cfg->debug_info)
3977                         mono_debug_record_line_number (cfg, ins, offset);
3978
3979                 switch (ins->opcode) {
3980                 case OP_BIGMUL:
3981                         amd64_mul_reg (code, ins->sreg2, TRUE);
3982                         break;
3983                 case OP_BIGMUL_UN:
3984                         amd64_mul_reg (code, ins->sreg2, FALSE);
3985                         break;
3986                 case OP_X86_SETEQ_MEMBASE:
3987                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3988                         break;
3989                 case OP_STOREI1_MEMBASE_IMM:
3990                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3991                         break;
3992                 case OP_STOREI2_MEMBASE_IMM:
3993                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3994                         break;
3995                 case OP_STOREI4_MEMBASE_IMM:
3996                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3997                         break;
3998                 case OP_STOREI1_MEMBASE_REG:
3999                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4000                         break;
4001                 case OP_STOREI2_MEMBASE_REG:
4002                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4003                         break;
4004                 /* In AMD64 NaCl, pointers are 4 bytes, */
4005                 /*  so STORE_* != STOREI8_*. Likewise below. */
4006                 case OP_STORE_MEMBASE_REG:
4007                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4008                         break;
4009                 case OP_STOREI8_MEMBASE_REG:
4010                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4011                         break;
4012                 case OP_STOREI4_MEMBASE_REG:
4013                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4014                         break;
4015                 case OP_STORE_MEMBASE_IMM:
4016 #ifndef __native_client_codegen__
4017                         /* In NaCl, this could be a PCONST type, which could */
4018                         /* mean a pointer type was copied directly into the  */
4019                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4020                         /* the value would be 0x00000000FFFFFFFF which is    */
4021                         /* not proper for an imm32 unless you cast it.       */
4022                         g_assert (amd64_is_imm32 (ins->inst_imm));
4023 #endif
4024                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4025                         break;
4026                 case OP_STOREI8_MEMBASE_IMM:
4027                         g_assert (amd64_is_imm32 (ins->inst_imm));
4028                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4029                         break;
4030                 case OP_LOAD_MEM:
4031 #ifdef __mono_ilp32__
4032                         /* In ILP32, pointers are 4 bytes, so separate these */
4033                         /* cases, use literal 8 below where we really want 8 */
4034                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4035                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4036                         break;
4037 #endif
4038                 case OP_LOADI8_MEM:
4039                         // FIXME: Decompose this earlier
4040                         if (amd64_use_imm32 (ins->inst_imm))
4041                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4042                         else {
4043                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4044                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4045                         }
4046                         break;
4047                 case OP_LOADI4_MEM:
4048                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4049                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4050                         break;
4051                 case OP_LOADU4_MEM:
4052                         // FIXME: Decompose this earlier
4053                         if (amd64_use_imm32 (ins->inst_imm))
4054                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4055                         else {
4056                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4057                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4058                         }
4059                         break;
4060                 case OP_LOADU1_MEM:
4061                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4062                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4063                         break;
4064                 case OP_LOADU2_MEM:
4065                         /* For NaCl, pointers are 4 bytes, so separate these */
4066                         /* cases, use literal 8 below where we really want 8 */
4067                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4068                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4069                         break;
4070                 case OP_LOAD_MEMBASE:
4071                         g_assert (amd64_is_imm32 (ins->inst_offset));
4072                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4073                         break;
4074                 case OP_LOADI8_MEMBASE:
4075                         /* Use literal 8 instead of sizeof pointer or */
4076                         /* register, we really want 8 for this opcode */
4077                         g_assert (amd64_is_imm32 (ins->inst_offset));
4078                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4079                         break;
4080                 case OP_LOADI4_MEMBASE:
4081                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4082                         break;
4083                 case OP_LOADU4_MEMBASE:
4084                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4085                         break;
4086                 case OP_LOADU1_MEMBASE:
4087                         /* The cpu zero extends the result into 64 bits */
4088                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4089                         break;
4090                 case OP_LOADI1_MEMBASE:
4091                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4092                         break;
4093                 case OP_LOADU2_MEMBASE:
4094                         /* The cpu zero extends the result into 64 bits */
4095                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4096                         break;
4097                 case OP_LOADI2_MEMBASE:
4098                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4099                         break;
4100                 case OP_AMD64_LOADI8_MEMINDEX:
4101                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4102                         break;
4103                 case OP_LCONV_TO_I1:
4104                 case OP_ICONV_TO_I1:
4105                 case OP_SEXT_I1:
4106                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4107                         break;
4108                 case OP_LCONV_TO_I2:
4109                 case OP_ICONV_TO_I2:
4110                 case OP_SEXT_I2:
4111                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4112                         break;
4113                 case OP_LCONV_TO_U1:
4114                 case OP_ICONV_TO_U1:
4115                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4116                         break;
4117                 case OP_LCONV_TO_U2:
4118                 case OP_ICONV_TO_U2:
4119                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4120                         break;
4121                 case OP_ZEXT_I4:
4122                         /* Clean out the upper word */
4123                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4124                         break;
4125                 case OP_SEXT_I4:
4126                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4127                         break;
4128                 case OP_COMPARE:
4129                 case OP_LCOMPARE:
4130                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4131                         break;
4132                 case OP_COMPARE_IMM:
4133 #if defined(__mono_ilp32__)
4134                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4135                         g_assert (amd64_is_imm32 (ins->inst_imm));
4136                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4137                         break;
4138 #endif
4139                 case OP_LCOMPARE_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4142                         break;
4143                 case OP_X86_COMPARE_REG_MEMBASE:
4144                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4145                         break;
4146                 case OP_X86_TEST_NULL:
4147                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4148                         break;
4149                 case OP_AMD64_TEST_NULL:
4150                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4151                         break;
4152
4153                 case OP_X86_ADD_REG_MEMBASE:
4154                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4155                         break;
4156                 case OP_X86_SUB_REG_MEMBASE:
4157                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4158                         break;
4159                 case OP_X86_AND_REG_MEMBASE:
4160                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4161                         break;
4162                 case OP_X86_OR_REG_MEMBASE:
4163                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4164                         break;
4165                 case OP_X86_XOR_REG_MEMBASE:
4166                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4167                         break;
4168
4169                 case OP_X86_ADD_MEMBASE_IMM:
4170                         /* FIXME: Make a 64 version too */
4171                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4172                         break;
4173                 case OP_X86_SUB_MEMBASE_IMM:
4174                         g_assert (amd64_is_imm32 (ins->inst_imm));
4175                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4176                         break;
4177                 case OP_X86_AND_MEMBASE_IMM:
4178                         g_assert (amd64_is_imm32 (ins->inst_imm));
4179                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4180                         break;
4181                 case OP_X86_OR_MEMBASE_IMM:
4182                         g_assert (amd64_is_imm32 (ins->inst_imm));
4183                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4184                         break;
4185                 case OP_X86_XOR_MEMBASE_IMM:
4186                         g_assert (amd64_is_imm32 (ins->inst_imm));
4187                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4188                         break;
4189                 case OP_X86_ADD_MEMBASE_REG:
4190                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4191                         break;
4192                 case OP_X86_SUB_MEMBASE_REG:
4193                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4194                         break;
4195                 case OP_X86_AND_MEMBASE_REG:
4196                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4197                         break;
4198                 case OP_X86_OR_MEMBASE_REG:
4199                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4200                         break;
4201                 case OP_X86_XOR_MEMBASE_REG:
4202                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4203                         break;
4204                 case OP_X86_INC_MEMBASE:
4205                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4206                         break;
4207                 case OP_X86_INC_REG:
4208                         amd64_inc_reg_size (code, ins->dreg, 4);
4209                         break;
4210                 case OP_X86_DEC_MEMBASE:
4211                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4212                         break;
4213                 case OP_X86_DEC_REG:
4214                         amd64_dec_reg_size (code, ins->dreg, 4);
4215                         break;
4216                 case OP_X86_MUL_REG_MEMBASE:
4217                 case OP_X86_MUL_MEMBASE_REG:
4218                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4219                         break;
4220                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4221                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4222                         break;
4223                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4224                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4225                         break;
4226                 case OP_AMD64_COMPARE_MEMBASE_REG:
4227                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4228                         break;
4229                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4230                         g_assert (amd64_is_imm32 (ins->inst_imm));
4231                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4232                         break;
4233                 case OP_X86_COMPARE_MEMBASE8_IMM:
4234                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4235                         break;
4236                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4237                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4238                         break;
4239                 case OP_AMD64_COMPARE_REG_MEMBASE:
4240                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4241                         break;
4242
4243                 case OP_AMD64_ADD_REG_MEMBASE:
4244                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4245                         break;
4246                 case OP_AMD64_SUB_REG_MEMBASE:
4247                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4248                         break;
4249                 case OP_AMD64_AND_REG_MEMBASE:
4250                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4251                         break;
4252                 case OP_AMD64_OR_REG_MEMBASE:
4253                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4254                         break;
4255                 case OP_AMD64_XOR_REG_MEMBASE:
4256                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4257                         break;
4258
4259                 case OP_AMD64_ADD_MEMBASE_REG:
4260                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4261                         break;
4262                 case OP_AMD64_SUB_MEMBASE_REG:
4263                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4264                         break;
4265                 case OP_AMD64_AND_MEMBASE_REG:
4266                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4267                         break;
4268                 case OP_AMD64_OR_MEMBASE_REG:
4269                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4270                         break;
4271                 case OP_AMD64_XOR_MEMBASE_REG:
4272                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4273                         break;
4274
4275                 case OP_AMD64_ADD_MEMBASE_IMM:
4276                         g_assert (amd64_is_imm32 (ins->inst_imm));
4277                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4278                         break;
4279                 case OP_AMD64_SUB_MEMBASE_IMM:
4280                         g_assert (amd64_is_imm32 (ins->inst_imm));
4281                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4282                         break;
4283                 case OP_AMD64_AND_MEMBASE_IMM:
4284                         g_assert (amd64_is_imm32 (ins->inst_imm));
4285                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4286                         break;
4287                 case OP_AMD64_OR_MEMBASE_IMM:
4288                         g_assert (amd64_is_imm32 (ins->inst_imm));
4289                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4290                         break;
4291                 case OP_AMD64_XOR_MEMBASE_IMM:
4292                         g_assert (amd64_is_imm32 (ins->inst_imm));
4293                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4294                         break;
4295
4296                 case OP_BREAK:
4297                         amd64_breakpoint (code);
4298                         break;
4299                 case OP_RELAXED_NOP:
4300                         x86_prefix (code, X86_REP_PREFIX);
4301                         x86_nop (code);
4302                         break;
4303                 case OP_HARD_NOP:
4304                         x86_nop (code);
4305                         break;
4306                 case OP_NOP:
4307                 case OP_DUMMY_USE:
4308                 case OP_DUMMY_STORE:
4309                 case OP_DUMMY_ICONST:
4310                 case OP_DUMMY_R8CONST:
4311                 case OP_NOT_REACHED:
4312                 case OP_NOT_NULL:
4313                         break;
4314                 case OP_IL_SEQ_POINT:
4315                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4316                         break;
4317                 case OP_SEQ_POINT: {
4318                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4319                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4320                                 guint8 *label;
4321
4322                                 /* Load ss_tramp_var */
4323                                 /* This is equal to &ss_trampoline */
4324                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4325                                 /* Load the trampoline address */
4326                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4327                                 /* Call it if it is non-null */
4328                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4329                                 label = code;
4330                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4331                                 amd64_call_reg (code, AMD64_R11);
4332                                 amd64_patch (label, code);
4333                         }
4334
4335                         /*
4336                          * This is the address which is saved in seq points,
4337                          */
4338                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4339
4340                         if (cfg->compile_aot) {
4341                                 guint32 offset = code - cfg->native_code;
4342                                 guint32 val;
4343                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4344                                 guint8 *label;
4345
4346                                 /* Load info var */
4347                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4348                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4349                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4350                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4351                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4352                                 label = code;
4353                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4354                                 /* Call the trampoline */
4355                                 amd64_call_reg (code, AMD64_R11);
4356                                 amd64_patch (label, code);
4357                         } else {
4358                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4359                                 guint8 *label;
4360
4361                                 /*
4362                                  * Emit a test+branch against a constant, the constant will be overwritten
4363                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4364                                  */
4365                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4366                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4367                                 label = code;
4368                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4369
4370                                 g_assert (var);
4371                                 g_assert (var->opcode == OP_REGOFFSET);
4372                                 /* Load bp_tramp_var */
4373                                 /* This is equal to &bp_trampoline */
4374                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4375                                 /* Call the trampoline */
4376                                 amd64_call_membase (code, AMD64_R11, 0);
4377                                 amd64_patch (label, code);
4378                         }
4379                         /*
4380                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4381                          * to another IL offset.
4382                          */
4383                         x86_nop (code);
4384                         break;
4385                 }
4386                 case OP_ADDCC:
4387                 case OP_LADDCC:
4388                 case OP_LADD:
4389                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4390                         break;
4391                 case OP_ADC:
4392                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4393                         break;
4394                 case OP_ADD_IMM:
4395                 case OP_LADD_IMM:
4396                         g_assert (amd64_is_imm32 (ins->inst_imm));
4397                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4398                         break;
4399                 case OP_ADC_IMM:
4400                         g_assert (amd64_is_imm32 (ins->inst_imm));
4401                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4402                         break;
4403                 case OP_SUBCC:
4404                 case OP_LSUBCC:
4405                 case OP_LSUB:
4406                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4407                         break;
4408                 case OP_SBB:
4409                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4410                         break;
4411                 case OP_SUB_IMM:
4412                 case OP_LSUB_IMM:
4413                         g_assert (amd64_is_imm32 (ins->inst_imm));
4414                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4415                         break;
4416                 case OP_SBB_IMM:
4417                         g_assert (amd64_is_imm32 (ins->inst_imm));
4418                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4419                         break;
4420                 case OP_LAND:
4421                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4422                         break;
4423                 case OP_AND_IMM:
4424                 case OP_LAND_IMM:
4425                         g_assert (amd64_is_imm32 (ins->inst_imm));
4426                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4427                         break;
4428                 case OP_LMUL:
4429                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4430                         break;
4431                 case OP_MUL_IMM:
4432                 case OP_LMUL_IMM:
4433                 case OP_IMUL_IMM: {
4434                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4435
4436                         switch (ins->inst_imm) {
4437                         case 2:
4438                                 /* MOV r1, r2 */
4439                                 /* ADD r1, r1 */
4440                                 if (ins->dreg != ins->sreg1)
4441                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4442                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4443                                 break;
4444                         case 3:
4445                                 /* LEA r1, [r2 + r2*2] */
4446                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4447                                 break;
4448                         case 5:
4449                                 /* LEA r1, [r2 + r2*4] */
4450                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4451                                 break;
4452                         case 6:
4453                                 /* LEA r1, [r2 + r2*2] */
4454                                 /* ADD r1, r1          */
4455                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4456                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4457                                 break;
4458                         case 9:
4459                                 /* LEA r1, [r2 + r2*8] */
4460                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4461                                 break;
4462                         case 10:
4463                                 /* LEA r1, [r2 + r2*4] */
4464                                 /* ADD r1, r1          */
4465                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4466                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4467                                 break;
4468                         case 12:
4469                                 /* LEA r1, [r2 + r2*2] */
4470                                 /* SHL r1, 2           */
4471                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4472                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4473                                 break;
4474                         case 25:
4475                                 /* LEA r1, [r2 + r2*4] */
4476                                 /* LEA r1, [r1 + r1*4] */
4477                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4478                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4479                                 break;
4480                         case 100:
4481                                 /* LEA r1, [r2 + r2*4] */
4482                                 /* SHL r1, 2           */
4483                                 /* LEA r1, [r1 + r1*4] */
4484                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4485                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4486                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4487                                 break;
4488                         default:
4489                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4490                                 break;
4491                         }
4492                         break;
4493                 }
4494                 case OP_LDIV:
4495                 case OP_LREM:
4496 #if defined( __native_client_codegen__ )
4497                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4498                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4499 #endif
4500                         /* Regalloc magic makes the div/rem cases the same */
4501                         if (ins->sreg2 == AMD64_RDX) {
4502                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4503                                 amd64_cdq (code);
4504                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4505                         } else {
4506                                 amd64_cdq (code);
4507                                 amd64_div_reg (code, ins->sreg2, TRUE);
4508                         }
4509                         break;
4510                 case OP_LDIV_UN:
4511                 case OP_LREM_UN:
4512 #if defined( __native_client_codegen__ )
4513                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4514                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4515 #endif
4516                         if (ins->sreg2 == AMD64_RDX) {
4517                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4518                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4519                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4520                         } else {
4521                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4522                                 amd64_div_reg (code, ins->sreg2, FALSE);
4523                         }
4524                         break;
4525                 case OP_IDIV:
4526                 case OP_IREM:
4527 #if defined( __native_client_codegen__ )
4528                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4529                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4530 #endif
4531                         if (ins->sreg2 == AMD64_RDX) {
4532                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4533                                 amd64_cdq_size (code, 4);
4534                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4535                         } else {
4536                                 amd64_cdq_size (code, 4);
4537                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4538                         }
4539                         break;
4540                 case OP_IDIV_UN:
4541                 case OP_IREM_UN:
4542 #if defined( __native_client_codegen__ )
4543                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4544                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4545 #endif
4546                         if (ins->sreg2 == AMD64_RDX) {
4547                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4548                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4549                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4550                         } else {
4551                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4552                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4553                         }
4554                         break;
4555                 case OP_LMUL_OVF:
4556                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4557                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4558                         break;
4559                 case OP_LOR:
4560                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4561                         break;
4562                 case OP_OR_IMM:
4563                 case OP_LOR_IMM:
4564                         g_assert (amd64_is_imm32 (ins->inst_imm));
4565                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4566                         break;
4567                 case OP_LXOR:
4568                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4569                         break;
4570                 case OP_XOR_IMM:
4571                 case OP_LXOR_IMM:
4572                         g_assert (amd64_is_imm32 (ins->inst_imm));
4573                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4574                         break;
4575                 case OP_LSHL:
4576                         g_assert (ins->sreg2 == AMD64_RCX);
4577                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4578                         break;
4579                 case OP_LSHR:
4580                         g_assert (ins->sreg2 == AMD64_RCX);
4581                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4582                         break;
4583                 case OP_SHR_IMM:
4584                 case OP_LSHR_IMM:
4585                         g_assert (amd64_is_imm32 (ins->inst_imm));
4586                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4587                         break;
4588                 case OP_SHR_UN_IMM:
4589                         g_assert (amd64_is_imm32 (ins->inst_imm));
4590                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4591                         break;
4592                 case OP_LSHR_UN_IMM:
4593                         g_assert (amd64_is_imm32 (ins->inst_imm));
4594                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4595                         break;
4596                 case OP_LSHR_UN:
4597                         g_assert (ins->sreg2 == AMD64_RCX);
4598                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4599                         break;
4600                 case OP_SHL_IMM:
4601                 case OP_LSHL_IMM:
4602                         g_assert (amd64_is_imm32 (ins->inst_imm));
4603                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4604                         break;
4605
4606                 case OP_IADDCC:
4607                 case OP_IADD:
4608                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4609                         break;
4610                 case OP_IADC:
4611                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4612                         break;
4613                 case OP_IADD_IMM:
4614                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4615                         break;
4616                 case OP_IADC_IMM:
4617                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4618                         break;
4619                 case OP_ISUBCC:
4620                 case OP_ISUB:
4621                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4622                         break;
4623                 case OP_ISBB:
4624                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4625                         break;
4626                 case OP_ISUB_IMM:
4627                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4628                         break;
4629                 case OP_ISBB_IMM:
4630                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4631                         break;
4632                 case OP_IAND:
4633                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4634                         break;
4635                 case OP_IAND_IMM:
4636                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4637                         break;
4638                 case OP_IOR:
4639                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4640                         break;
4641                 case OP_IOR_IMM:
4642                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4643                         break;
4644                 case OP_IXOR:
4645                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4646                         break;
4647                 case OP_IXOR_IMM:
4648                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4649                         break;
4650                 case OP_INEG:
4651                         amd64_neg_reg_size (code, ins->sreg1, 4);
4652                         break;
4653                 case OP_INOT:
4654                         amd64_not_reg_size (code, ins->sreg1, 4);
4655                         break;
4656                 case OP_ISHL:
4657                         g_assert (ins->sreg2 == AMD64_RCX);
4658                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4659                         break;
4660                 case OP_ISHR:
4661                         g_assert (ins->sreg2 == AMD64_RCX);
4662                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4663                         break;
4664                 case OP_ISHR_IMM:
4665                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4666                         break;
4667                 case OP_ISHR_UN_IMM:
4668                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4669                         break;
4670                 case OP_ISHR_UN:
4671                         g_assert (ins->sreg2 == AMD64_RCX);
4672                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4673                         break;
4674                 case OP_ISHL_IMM:
4675                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4676                         break;
4677                 case OP_IMUL:
4678                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4679                         break;
4680                 case OP_IMUL_OVF:
4681                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4682                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4683                         break;
4684                 case OP_IMUL_OVF_UN:
4685                 case OP_LMUL_OVF_UN: {
4686                         /* the mul operation and the exception check should most likely be split */
4687                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4688                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4689                         /*g_assert (ins->sreg2 == X86_EAX);
4690                         g_assert (ins->dreg == X86_EAX);*/
4691                         if (ins->sreg2 == X86_EAX) {
4692                                 non_eax_reg = ins->sreg1;
4693                         } else if (ins->sreg1 == X86_EAX) {
4694                                 non_eax_reg = ins->sreg2;
4695                         } else {
4696                                 /* no need to save since we're going to store to it anyway */
4697                                 if (ins->dreg != X86_EAX) {
4698                                         saved_eax = TRUE;
4699                                         amd64_push_reg (code, X86_EAX);
4700                                 }
4701                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4702                                 non_eax_reg = ins->sreg2;
4703                         }
4704                         if (ins->dreg == X86_EDX) {
4705                                 if (!saved_eax) {
4706                                         saved_eax = TRUE;
4707                                         amd64_push_reg (code, X86_EAX);
4708                                 }
4709                         } else {
4710                                 saved_edx = TRUE;
4711                                 amd64_push_reg (code, X86_EDX);
4712                         }
4713                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4714                         /* save before the check since pop and mov don't change the flags */
4715                         if (ins->dreg != X86_EAX)
4716                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4717                         if (saved_edx)
4718                                 amd64_pop_reg (code, X86_EDX);
4719                         if (saved_eax)
4720                                 amd64_pop_reg (code, X86_EAX);
4721                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4722                         break;
4723                 }
4724                 case OP_ICOMPARE:
4725                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4726                         break;
4727                 case OP_ICOMPARE_IMM:
4728                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4729                         break;
4730                 case OP_IBEQ:
4731                 case OP_IBLT:
4732                 case OP_IBGT:
4733                 case OP_IBGE:
4734                 case OP_IBLE:
4735                 case OP_LBEQ:
4736                 case OP_LBLT:
4737                 case OP_LBGT:
4738                 case OP_LBGE:
4739                 case OP_LBLE:
4740                 case OP_IBNE_UN:
4741                 case OP_IBLT_UN:
4742                 case OP_IBGT_UN:
4743                 case OP_IBGE_UN:
4744                 case OP_IBLE_UN:
4745                 case OP_LBNE_UN:
4746                 case OP_LBLT_UN:
4747                 case OP_LBGT_UN:
4748                 case OP_LBGE_UN:
4749                 case OP_LBLE_UN:
4750                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4751                         break;
4752
4753                 case OP_CMOV_IEQ:
4754                 case OP_CMOV_IGE:
4755                 case OP_CMOV_IGT:
4756                 case OP_CMOV_ILE:
4757                 case OP_CMOV_ILT:
4758                 case OP_CMOV_INE_UN:
4759                 case OP_CMOV_IGE_UN:
4760                 case OP_CMOV_IGT_UN:
4761                 case OP_CMOV_ILE_UN:
4762                 case OP_CMOV_ILT_UN:
4763                 case OP_CMOV_LEQ:
4764                 case OP_CMOV_LGE:
4765                 case OP_CMOV_LGT:
4766                 case OP_CMOV_LLE:
4767                 case OP_CMOV_LLT:
4768                 case OP_CMOV_LNE_UN:
4769                 case OP_CMOV_LGE_UN:
4770                 case OP_CMOV_LGT_UN:
4771                 case OP_CMOV_LLE_UN:
4772                 case OP_CMOV_LLT_UN:
4773                         g_assert (ins->dreg == ins->sreg1);
4774                         /* This needs to operate on 64 bit values */
4775                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4776                         break;
4777
4778                 case OP_LNOT:
4779                         amd64_not_reg (code, ins->sreg1);
4780                         break;
4781                 case OP_LNEG:
4782                         amd64_neg_reg (code, ins->sreg1);
4783                         break;
4784
4785                 case OP_ICONST:
4786                 case OP_I8CONST:
4787                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4788                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4789                         else
4790                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4791                         break;
4792                 case OP_AOTCONST:
4793                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4794                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4795                         break;
4796                 case OP_JUMP_TABLE:
4797                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4798                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4799                         break;
4800                 case OP_MOVE:
4801                         if (ins->dreg != ins->sreg1)
4802                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4803                         break;
4804                 case OP_AMD64_SET_XMMREG_R4: {
4805                         if (cfg->r4fp) {
4806                                 if (ins->dreg != ins->sreg1)
4807                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4808                         } else {
4809                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4810                         }
4811                         break;
4812                 }
4813                 case OP_AMD64_SET_XMMREG_R8: {
4814                         if (ins->dreg != ins->sreg1)
4815                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4816                         break;
4817                 }
4818                 case OP_TAILCALL: {
4819                         MonoCallInst *call = (MonoCallInst*)ins;
4820                         int i, save_area_offset;
4821
4822                         g_assert (!cfg->method->save_lmf);
4823
4824                         /* Restore callee saved registers */
4825                         save_area_offset = cfg->arch.reg_save_area_offset;
4826                         for (i = 0; i < AMD64_NREG; ++i)
4827                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4828                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4829                                         save_area_offset += 8;
4830                                 }
4831
4832                         if (cfg->arch.omit_fp) {
4833                                 if (cfg->arch.stack_alloc_size)
4834                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4835                                 // FIXME:
4836                                 if (call->stack_usage)
4837                                         NOT_IMPLEMENTED;
4838                         } else {
4839                                 /* Copy arguments on the stack to our argument area */
4840                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4841                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4842                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4843                                 }
4844
4845                                 amd64_leave (code);
4846                         }
4847
4848                         offset = code - cfg->native_code;
4849                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4850                         if (cfg->compile_aot)
4851                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4852                         else
4853                                 amd64_set_reg_template (code, AMD64_R11);
4854                         amd64_jump_reg (code, AMD64_R11);
4855                         ins->flags |= MONO_INST_GC_CALLSITE;
4856                         ins->backend.pc_offset = code - cfg->native_code;
4857                         break;
4858                 }
4859                 case OP_CHECK_THIS:
4860                         /* ensure ins->sreg1 is not NULL */
4861                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4862                         break;
4863                 case OP_ARGLIST: {
4864                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4865                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4866                         break;
4867                 }
4868                 case OP_CALL:
4869                 case OP_FCALL:
4870                 case OP_RCALL:
4871                 case OP_LCALL:
4872                 case OP_VCALL:
4873                 case OP_VCALL2:
4874                 case OP_VOIDCALL:
4875                         call = (MonoCallInst*)ins;
4876                         /*
4877                          * The AMD64 ABI forces callers to know about varargs.
4878                          */
4879                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4880                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4881                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4882                                 /*
4883                                  * Since the unmanaged calling convention doesn't contain a
4884                                  * 'vararg' entry, we have to treat every pinvoke call as a
4885                                  * potential vararg call.
4886                                  */
4887                                 guint32 nregs, i;
4888                                 nregs = 0;
4889                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4890                                         if (call->used_fregs & (1 << i))
4891                                                 nregs ++;
4892                                 if (!nregs)
4893                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4894                                 else
4895                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4896                         }
4897
4898                         if (ins->flags & MONO_INST_HAS_METHOD)
4899                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4900                         else
4901                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4902                         ins->flags |= MONO_INST_GC_CALLSITE;
4903                         ins->backend.pc_offset = code - cfg->native_code;
4904                         code = emit_move_return_value (cfg, ins, code);
4905                         break;
4906                 case OP_FCALL_REG:
4907                 case OP_RCALL_REG:
4908                 case OP_LCALL_REG:
4909                 case OP_VCALL_REG:
4910                 case OP_VCALL2_REG:
4911                 case OP_VOIDCALL_REG:
4912                 case OP_CALL_REG:
4913                         call = (MonoCallInst*)ins;
4914
4915                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4916                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4917                                 ins->sreg1 = AMD64_R11;
4918                         }
4919
4920                         /*
4921                          * The AMD64 ABI forces callers to know about varargs.
4922                          */
4923                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4924                                 if (ins->sreg1 == AMD64_RAX) {
4925                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4926                                         ins->sreg1 = AMD64_R11;
4927                                 }
4928                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4929                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4930                                 /*
4931                                  * Since the unmanaged calling convention doesn't contain a
4932                                  * 'vararg' entry, we have to treat every pinvoke call as a
4933                                  * potential vararg call.
4934                                  */
4935                                 guint32 nregs, i;
4936                                 nregs = 0;
4937                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4938                                         if (call->used_fregs & (1 << i))
4939                                                 nregs ++;
4940                                 if (ins->sreg1 == AMD64_RAX) {
4941                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4942                                         ins->sreg1 = AMD64_R11;
4943                                 }
4944                                 if (!nregs)
4945                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4946                                 else
4947                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4948                         }
4949
4950                         amd64_call_reg (code, ins->sreg1);
4951                         ins->flags |= MONO_INST_GC_CALLSITE;
4952                         ins->backend.pc_offset = code - cfg->native_code;
4953                         code = emit_move_return_value (cfg, ins, code);
4954                         break;
4955                 case OP_FCALL_MEMBASE:
4956                 case OP_RCALL_MEMBASE:
4957                 case OP_LCALL_MEMBASE:
4958                 case OP_VCALL_MEMBASE:
4959                 case OP_VCALL2_MEMBASE:
4960                 case OP_VOIDCALL_MEMBASE:
4961                 case OP_CALL_MEMBASE:
4962                         call = (MonoCallInst*)ins;
4963
4964                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4965                         ins->flags |= MONO_INST_GC_CALLSITE;
4966                         ins->backend.pc_offset = code - cfg->native_code;
4967                         code = emit_move_return_value (cfg, ins, code);
4968                         break;
4969                 case OP_DYN_CALL: {
4970                         int i;
4971                         MonoInst *var = cfg->dyn_call_var;
4972                         guint8 *label;
4973
4974                         g_assert (var->opcode == OP_REGOFFSET);
4975
4976                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4977                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4978                         /* r10 = ftn */
4979                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4980
4981                         /* Save args buffer */
4982                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4983
4984                         /* Set fp arg regs */
4985                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4986                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4987                         label = code;
4988                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4989                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4990                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4991                         amd64_patch (label, code);
4992
4993                         /* Set argument registers */
4994                         for (i = 0; i < PARAM_REGS; ++i)
4995                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4996
4997                         /* Make the call */
4998                         amd64_call_reg (code, AMD64_R10);
4999
5000                         ins->flags |= MONO_INST_GC_CALLSITE;
5001                         ins->backend.pc_offset = code - cfg->native_code;
5002
5003                         /* Save result */
5004                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5005                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5006                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5007                         break;
5008                 }
5009                 case OP_AMD64_SAVE_SP_TO_LMF: {
5010                         MonoInst *lmf_var = cfg->lmf_var;
5011                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5012                         break;
5013                 }
5014                 case OP_X86_PUSH:
5015                         g_assert_not_reached ();
5016                         amd64_push_reg (code, ins->sreg1);
5017                         break;
5018                 case OP_X86_PUSH_IMM:
5019                         g_assert_not_reached ();
5020                         g_assert (amd64_is_imm32 (ins->inst_imm));
5021                         amd64_push_imm (code, ins->inst_imm);
5022                         break;
5023                 case OP_X86_PUSH_MEMBASE:
5024                         g_assert_not_reached ();
5025                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5026                         break;
5027                 case OP_X86_PUSH_OBJ: {
5028                         int size = ALIGN_TO (ins->inst_imm, 8);
5029
5030                         g_assert_not_reached ();
5031
5032                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5033                         amd64_push_reg (code, AMD64_RDI);
5034                         amd64_push_reg (code, AMD64_RSI);
5035                         amd64_push_reg (code, AMD64_RCX);
5036                         if (ins->inst_offset)
5037                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5038                         else
5039                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5040                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5041                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5042                         amd64_cld (code);
5043                         amd64_prefix (code, X86_REP_PREFIX);
5044                         amd64_movsd (code);
5045                         amd64_pop_reg (code, AMD64_RCX);
5046                         amd64_pop_reg (code, AMD64_RSI);
5047                         amd64_pop_reg (code, AMD64_RDI);
5048                         break;
5049                 }
5050                 case OP_GENERIC_CLASS_INIT: {
5051                         static int byte_offset = -1;
5052                         static guint8 bitmask;
5053                         guint8 *jump;
5054
5055                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5056
5057                         if (byte_offset < 0)
5058                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5059
5060                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5061                         jump = code;
5062                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5063
5064                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5065                         ins->flags |= MONO_INST_GC_CALLSITE;
5066                         ins->backend.pc_offset = code - cfg->native_code;
5067
5068                         x86_patch (jump, code);
5069                         break;
5070                 }
5071
5072                 case OP_X86_LEA:
5073                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5074                         break;
5075                 case OP_X86_LEA_MEMBASE:
5076                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5077                         break;
5078                 case OP_X86_XCHG:
5079                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5080                         break;
5081                 case OP_LOCALLOC:
5082                         /* keep alignment */
5083                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5084                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5085                         code = mono_emit_stack_alloc (cfg, code, ins);
5086                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5087                         if (cfg->param_area)
5088                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5089                         break;
5090                 case OP_LOCALLOC_IMM: {
5091                         guint32 size = ins->inst_imm;
5092                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5093
5094                         if (ins->flags & MONO_INST_INIT) {
5095                                 if (size < 64) {
5096                                         int i;
5097
5098                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5099                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5100
5101                                         for (i = 0; i < size; i += 8)
5102                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5103                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5104                                 } else {
5105                                         amd64_mov_reg_imm (code, ins->dreg, size);
5106                                         ins->sreg1 = ins->dreg;
5107
5108                                         code = mono_emit_stack_alloc (cfg, code, ins);
5109                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5110                                 }
5111                         } else {
5112                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5113                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5114                         }
5115                         if (cfg->param_area)
5116                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5117                         break;
5118                 }
5119                 case OP_THROW: {
5120                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5121                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5122                                              (gpointer)"mono_arch_throw_exception", FALSE);
5123                         ins->flags |= MONO_INST_GC_CALLSITE;
5124                         ins->backend.pc_offset = code - cfg->native_code;
5125                         break;
5126                 }
5127                 case OP_RETHROW: {
5128                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5129                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5130                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5131                         ins->flags |= MONO_INST_GC_CALLSITE;
5132                         ins->backend.pc_offset = code - cfg->native_code;
5133                         break;
5134                 }
5135                 case OP_CALL_HANDLER:
5136                         /* Align stack */
5137                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5138                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5139                         amd64_call_imm (code, 0);
5140                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5141                         /* Restore stack alignment */
5142                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5143                         break;
5144                 case OP_START_HANDLER: {
5145                         /* Even though we're saving RSP, use sizeof */
5146                         /* gpointer because spvar is of type IntPtr */
5147                         /* see: mono_create_spvar_for_region */
5148                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5149                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5150
5151                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5152                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5153                                 cfg->param_area) {
5154                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5155                         }
5156                         break;
5157                 }
5158                 case OP_ENDFINALLY: {
5159                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5160                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5161                         amd64_ret (code);
5162                         break;
5163                 }
5164                 case OP_ENDFILTER: {
5165                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5166                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5167                         /* The local allocator will put the result into RAX */
5168                         amd64_ret (code);
5169                         break;
5170                 }
5171                 case OP_GET_EX_OBJ:
5172                         if (ins->dreg != AMD64_RAX)
5173                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5174                         break;
5175                 case OP_LABEL:
5176                         ins->inst_c0 = code - cfg->native_code;
5177                         break;
5178                 case OP_BR:
5179                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5180                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5181                         //break;
5182                                 if (ins->inst_target_bb->native_offset) {
5183                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5184                                 } else {
5185                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5186                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5187                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5188                                                 x86_jump8 (code, 0);
5189                                         else
5190                                                 x86_jump32 (code, 0);
5191                         }
5192                         break;
5193                 case OP_BR_REG:
5194                         amd64_jump_reg (code, ins->sreg1);
5195                         break;
5196                 case OP_ICNEQ:
5197                 case OP_ICGE:
5198                 case OP_ICLE:
5199                 case OP_ICGE_UN:
5200                 case OP_ICLE_UN:
5201
5202                 case OP_CEQ:
5203                 case OP_LCEQ:
5204                 case OP_ICEQ:
5205                 case OP_CLT:
5206                 case OP_LCLT:
5207                 case OP_ICLT:
5208                 case OP_CGT:
5209                 case OP_ICGT:
5210                 case OP_LCGT:
5211                 case OP_CLT_UN:
5212                 case OP_LCLT_UN:
5213                 case OP_ICLT_UN:
5214                 case OP_CGT_UN:
5215                 case OP_LCGT_UN:
5216                 case OP_ICGT_UN:
5217                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5218                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5219                         break;
5220                 case OP_COND_EXC_EQ:
5221                 case OP_COND_EXC_NE_UN:
5222                 case OP_COND_EXC_LT:
5223                 case OP_COND_EXC_LT_UN:
5224                 case OP_COND_EXC_GT:
5225                 case OP_COND_EXC_GT_UN:
5226                 case OP_COND_EXC_GE:
5227                 case OP_COND_EXC_GE_UN:
5228                 case OP_COND_EXC_LE:
5229                 case OP_COND_EXC_LE_UN:
5230                 case OP_COND_EXC_IEQ:
5231                 case OP_COND_EXC_INE_UN:
5232                 case OP_COND_EXC_ILT:
5233                 case OP_COND_EXC_ILT_UN:
5234                 case OP_COND_EXC_IGT:
5235                 case OP_COND_EXC_IGT_UN:
5236                 case OP_COND_EXC_IGE:
5237                 case OP_COND_EXC_IGE_UN:
5238                 case OP_COND_EXC_ILE:
5239                 case OP_COND_EXC_ILE_UN:
5240                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5241                         break;
5242                 case OP_COND_EXC_OV:
5243                 case OP_COND_EXC_NO:
5244                 case OP_COND_EXC_C:
5245                 case OP_COND_EXC_NC:
5246                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5247                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5248                         break;
5249                 case OP_COND_EXC_IOV:
5250                 case OP_COND_EXC_INO:
5251                 case OP_COND_EXC_IC:
5252                 case OP_COND_EXC_INC:
5253                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5254                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5255                         break;
5256
5257                 /* floating point opcodes */
5258                 case OP_R8CONST: {
5259                         double d = *(double *)ins->inst_p0;
5260
5261                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5262                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5263                         }
5264                         else {
5265                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5266                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5267                         }
5268                         break;
5269                 }
5270                 case OP_R4CONST: {
5271                         float f = *(float *)ins->inst_p0;
5272
5273                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5274                                 if (cfg->r4fp)
5275                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5276                                 else
5277                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5278                         }
5279                         else {
5280                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5281                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5282                                 if (!cfg->r4fp)
5283                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5284                         }
5285                         break;
5286                 }
5287                 case OP_STORER8_MEMBASE_REG:
5288                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5289                         break;
5290                 case OP_LOADR8_MEMBASE:
5291                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5292                         break;
5293                 case OP_STORER4_MEMBASE_REG:
5294                         if (cfg->r4fp) {
5295                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5296                         } else {
5297                                 /* This requires a double->single conversion */
5298                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5299                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5300                         }
5301                         break;
5302                 case OP_LOADR4_MEMBASE:
5303                         if (cfg->r4fp) {
5304                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5305                         } else {
5306                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5307                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5308                         }
5309                         break;
5310                 case OP_ICONV_TO_R4:
5311                         if (cfg->r4fp) {
5312                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5313                         } else {
5314                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5315                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5316                         }
5317                         break;
5318                 case OP_ICONV_TO_R8:
5319                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5320                         break;
5321                 case OP_LCONV_TO_R4:
5322                         if (cfg->r4fp) {
5323                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5324                         } else {
5325                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5326                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5327                         }
5328                         break;
5329                 case OP_LCONV_TO_R8:
5330                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5331                         break;
5332                 case OP_FCONV_TO_R4:
5333                         if (cfg->r4fp) {
5334                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5335                         } else {
5336                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5337                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5338                         }
5339                         break;
5340                 case OP_FCONV_TO_I1:
5341                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5342                         break;
5343                 case OP_FCONV_TO_U1:
5344                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5345                         break;
5346                 case OP_FCONV_TO_I2:
5347                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5348                         break;
5349                 case OP_FCONV_TO_U2:
5350                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5351                         break;
5352                 case OP_FCONV_TO_U4:
5353                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5354                         break;
5355                 case OP_FCONV_TO_I4:
5356                 case OP_FCONV_TO_I:
5357                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5358                         break;
5359                 case OP_FCONV_TO_I8:
5360                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5361                         break;
5362
5363                 case OP_RCONV_TO_I1:
5364                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5365                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5366                         break;
5367                 case OP_RCONV_TO_U1:
5368                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5369                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5370                         break;
5371                 case OP_RCONV_TO_I2:
5372                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5373                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5374                         break;
5375                 case OP_RCONV_TO_U2:
5376                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5377                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5378                         break;
5379                 case OP_RCONV_TO_I4:
5380                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5381                         break;
5382                 case OP_RCONV_TO_U4:
5383                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5384                         break;
5385                 case OP_RCONV_TO_I8:
5386                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5387                         break;
5388                 case OP_RCONV_TO_R8:
5389                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5390                         break;
5391                 case OP_RCONV_TO_R4:
5392                         if (ins->dreg != ins->sreg1)
5393                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5394                         break;
5395
5396                 case OP_LCONV_TO_R_UN: {
5397                         guint8 *br [2];
5398
5399                         /* Based on gcc code */
5400                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5401                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5402
5403                         /* Positive case */
5404                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5405                         br [1] = code; x86_jump8 (code, 0);
5406                         amd64_patch (br [0], code);
5407
5408                         /* Negative case */
5409                         /* Save to the red zone */
5410                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5411                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5412                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5413                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5414                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5415                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5416                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5417                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5418                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5419                         /* Restore */
5420                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5421                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5422                         amd64_patch (br [1], code);
5423                         break;
5424                 }
5425                 case OP_LCONV_TO_OVF_U4:
5426                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5427                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5428                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5429                         break;
5430                 case OP_LCONV_TO_OVF_I4_UN:
5431                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5432                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5433                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5434                         break;
5435                 case OP_FMOVE:
5436                         if (ins->dreg != ins->sreg1)
5437                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5438                         break;
5439                 case OP_RMOVE:
5440                         if (ins->dreg != ins->sreg1)
5441                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5442                         break;
5443                 case OP_MOVE_F_TO_I4:
5444                         if (cfg->r4fp) {
5445                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5446                         } else {
5447                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5448                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5449                         }
5450                         break;
5451                 case OP_MOVE_I4_TO_F:
5452                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5453                         if (!cfg->r4fp)
5454                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5455                         break;
5456                 case OP_MOVE_F_TO_I8:
5457                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5458                         break;
5459                 case OP_MOVE_I8_TO_F:
5460                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5461                         break;
5462                 case OP_FADD:
5463                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5464                         break;
5465                 case OP_FSUB:
5466                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5467                         break;
5468                 case OP_FMUL:
5469                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5470                         break;
5471                 case OP_FDIV:
5472                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5473                         break;
5474                 case OP_FNEG: {
5475                         static double r8_0 = -0.0;
5476
5477                         g_assert (ins->sreg1 == ins->dreg);
5478
5479                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5480                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5481                         break;
5482                 }
5483                 case OP_SIN:
5484                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5485                         break;
5486                 case OP_COS:
5487                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5488                         break;
5489                 case OP_ABS: {
5490                         static guint64 d = 0x7fffffffffffffffUL;
5491
5492                         g_assert (ins->sreg1 == ins->dreg);
5493
5494                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5495                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5496                         break;
5497                 }
5498                 case OP_SQRT:
5499                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5500                         break;
5501
5502                 case OP_RADD:
5503                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5504                         break;
5505                 case OP_RSUB:
5506                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5507                         break;
5508                 case OP_RMUL:
5509                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5510                         break;
5511                 case OP_RDIV:
5512                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5513                         break;
5514                 case OP_RNEG: {
5515                         static float r4_0 = -0.0;
5516
5517                         g_assert (ins->sreg1 == ins->dreg);
5518
5519                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5520                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5521                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5522                         break;
5523                 }
5524
5525                 case OP_IMIN:
5526                         g_assert (cfg->opt & MONO_OPT_CMOV);
5527                         g_assert (ins->dreg == ins->sreg1);
5528                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5529                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5530                         break;
5531                 case OP_IMIN_UN:
5532                         g_assert (cfg->opt & MONO_OPT_CMOV);
5533                         g_assert (ins->dreg == ins->sreg1);
5534                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5535                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5536                         break;
5537                 case OP_IMAX:
5538                         g_assert (cfg->opt & MONO_OPT_CMOV);
5539                         g_assert (ins->dreg == ins->sreg1);
5540                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5541                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5542                         break;
5543                 case OP_IMAX_UN:
5544                         g_assert (cfg->opt & MONO_OPT_CMOV);
5545                         g_assert (ins->dreg == ins->sreg1);
5546                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5547                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5548                         break;
5549                 case OP_LMIN:
5550                         g_assert (cfg->opt & MONO_OPT_CMOV);
5551                         g_assert (ins->dreg == ins->sreg1);
5552                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5553                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5554                         break;
5555                 case OP_LMIN_UN:
5556                         g_assert (cfg->opt & MONO_OPT_CMOV);
5557                         g_assert (ins->dreg == ins->sreg1);
5558                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5559                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5560                         break;
5561                 case OP_LMAX:
5562                         g_assert (cfg->opt & MONO_OPT_CMOV);
5563                         g_assert (ins->dreg == ins->sreg1);
5564                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5565                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5566                         break;
5567                 case OP_LMAX_UN:
5568                         g_assert (cfg->opt & MONO_OPT_CMOV);
5569                         g_assert (ins->dreg == ins->sreg1);
5570                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5571                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5572                         break;
5573                 case OP_X86_FPOP:
5574                         break;
5575                 case OP_FCOMPARE:
5576                         /*
5577                          * The two arguments are swapped because the fbranch instructions
5578                          * depend on this for the non-sse case to work.
5579                          */
5580                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5581                         break;
5582                 case OP_RCOMPARE:
5583                         /*
5584                          * FIXME: Get rid of this.
5585                          * The two arguments are swapped because the fbranch instructions
5586                          * depend on this for the non-sse case to work.
5587                          */
5588                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5589                         break;
5590                 case OP_FCNEQ:
5591                 case OP_FCEQ: {
5592                         /* zeroing the register at the start results in
5593                          * shorter and faster code (we can also remove the widening op)
5594                          */
5595                         guchar *unordered_check;
5596
5597                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5598                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5599                         unordered_check = code;
5600                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5601
5602                         if (ins->opcode == OP_FCEQ) {
5603                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5604                                 amd64_patch (unordered_check, code);
5605                         } else {
5606                                 guchar *jump_to_end;
5607                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5608                                 jump_to_end = code;
5609                                 x86_jump8 (code, 0);
5610                                 amd64_patch (unordered_check, code);
5611                                 amd64_inc_reg (code, ins->dreg);
5612                                 amd64_patch (jump_to_end, code);
5613                         }
5614                         break;
5615                 }
5616                 case OP_FCLT:
5617                 case OP_FCLT_UN: {
5618                         /* zeroing the register at the start results in
5619                          * shorter and faster code (we can also remove the widening op)
5620                          */
5621                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5622                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5623                         if (ins->opcode == OP_FCLT_UN) {
5624                                 guchar *unordered_check = code;
5625                                 guchar *jump_to_end;
5626                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5627                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5628                                 jump_to_end = code;
5629                                 x86_jump8 (code, 0);
5630                                 amd64_patch (unordered_check, code);
5631                                 amd64_inc_reg (code, ins->dreg);
5632                                 amd64_patch (jump_to_end, code);
5633                         } else {
5634                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5635                         }
5636                         break;
5637                 }
5638                 case OP_FCLE: {
5639                         guchar *unordered_check;
5640                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5641                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5642                         unordered_check = code;
5643                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5644                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5645                         amd64_patch (unordered_check, code);
5646                         break;
5647                 }
5648                 case OP_FCGT:
5649                 case OP_FCGT_UN: {
5650                         /* zeroing the register at the start results in
5651                          * shorter and faster code (we can also remove the widening op)
5652                          */
5653                         guchar *unordered_check;
5654
5655                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5656                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5657                         if (ins->opcode == OP_FCGT) {
5658                                 unordered_check = code;
5659                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5660                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5661                                 amd64_patch (unordered_check, code);
5662                         } else {
5663                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5664                         }
5665                         break;
5666                 }
5667                 case OP_FCGE: {
5668                         guchar *unordered_check;
5669                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5670                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5671                         unordered_check = code;
5672                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5673                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5674                         amd64_patch (unordered_check, code);
5675                         break;
5676                 }
5677
5678                 case OP_RCEQ:
5679                 case OP_RCGT:
5680                 case OP_RCLT:
5681                 case OP_RCLT_UN:
5682                 case OP_RCGT_UN: {
5683                         int x86_cond;
5684                         gboolean unordered = FALSE;
5685
5686                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5687                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5688
5689                         switch (ins->opcode) {
5690                         case OP_RCEQ:
5691                                 x86_cond = X86_CC_EQ;
5692                                 break;
5693                         case OP_RCGT:
5694                                 x86_cond = X86_CC_LT;
5695                                 break;
5696                         case OP_RCLT:
5697                                 x86_cond = X86_CC_GT;
5698                                 break;
5699                         case OP_RCLT_UN:
5700                                 x86_cond = X86_CC_GT;
5701                                 unordered = TRUE;
5702                                 break;
5703                         case OP_RCGT_UN:
5704                                 x86_cond = X86_CC_LT;
5705                                 unordered = TRUE;
5706                                 break;
5707                         default:
5708                                 g_assert_not_reached ();
5709                                 break;
5710                         }
5711
5712                         if (unordered) {
5713                                 guchar *unordered_check;
5714                                 guchar *jump_to_end;
5715
5716                                 unordered_check = code;
5717                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5718                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5719                                 jump_to_end = code;
5720                                 x86_jump8 (code, 0);
5721                                 amd64_patch (unordered_check, code);
5722                                 amd64_inc_reg (code, ins->dreg);
5723                                 amd64_patch (jump_to_end, code);
5724                         } else {
5725                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5726                         }
5727                         break;
5728                 }
5729                 case OP_FCLT_MEMBASE:
5730                 case OP_FCGT_MEMBASE:
5731                 case OP_FCLT_UN_MEMBASE:
5732                 case OP_FCGT_UN_MEMBASE:
5733                 case OP_FCEQ_MEMBASE: {
5734                         guchar *unordered_check, *jump_to_end;
5735                         int x86_cond;
5736
5737                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5738                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5739
5740                         switch (ins->opcode) {
5741                         case OP_FCEQ_MEMBASE:
5742                                 x86_cond = X86_CC_EQ;
5743                                 break;
5744                         case OP_FCLT_MEMBASE:
5745                         case OP_FCLT_UN_MEMBASE:
5746                                 x86_cond = X86_CC_LT;
5747                                 break;
5748                         case OP_FCGT_MEMBASE:
5749                         case OP_FCGT_UN_MEMBASE:
5750                                 x86_cond = X86_CC_GT;
5751                                 break;
5752                         default:
5753                                 g_assert_not_reached ();
5754                         }
5755
5756                         unordered_check = code;
5757                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5758                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5759
5760                         switch (ins->opcode) {
5761                         case OP_FCEQ_MEMBASE:
5762                         case OP_FCLT_MEMBASE:
5763                         case OP_FCGT_MEMBASE:
5764                                 amd64_patch (unordered_check, code);
5765                                 break;
5766                         case OP_FCLT_UN_MEMBASE:
5767                         case OP_FCGT_UN_MEMBASE:
5768                                 jump_to_end = code;
5769                                 x86_jump8 (code, 0);
5770                                 amd64_patch (unordered_check, code);
5771                                 amd64_inc_reg (code, ins->dreg);
5772                                 amd64_patch (jump_to_end, code);
5773                                 break;
5774                         default:
5775                                 break;
5776                         }
5777                         break;
5778                 }
5779                 case OP_FBEQ: {
5780                         guchar *jump = code;
5781                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5782                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5783                         amd64_patch (jump, code);
5784                         break;
5785                 }
5786                 case OP_FBNE_UN:
5787                         /* Branch if C013 != 100 */
5788                         /* branch if !ZF or (PF|CF) */
5789                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5790                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5791                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5792                         break;
5793                 case OP_FBLT:
5794                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5795                         break;
5796                 case OP_FBLT_UN:
5797                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5798                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5799                         break;
5800                 case OP_FBGT:
5801                 case OP_FBGT_UN:
5802                         if (ins->opcode == OP_FBGT) {
5803                                 guchar *br1;
5804
5805                                 /* skip branch if C1=1 */
5806                                 br1 = code;
5807                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5808                                 /* branch if (C0 | C3) = 1 */
5809                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5810                                 amd64_patch (br1, code);
5811                                 break;
5812                         } else {
5813                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5814                         }
5815                         break;
5816                 case OP_FBGE: {
5817                         /* Branch if C013 == 100 or 001 */
5818                         guchar *br1;
5819
5820                         /* skip branch if C1=1 */
5821                         br1 = code;
5822                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5823                         /* branch if (C0 | C3) = 1 */
5824                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5825                         amd64_patch (br1, code);
5826                         break;
5827                 }
5828                 case OP_FBGE_UN:
5829                         /* Branch if C013 == 000 */
5830                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5831                         break;
5832                 case OP_FBLE: {
5833                         /* Branch if C013=000 or 100 */
5834                         guchar *br1;
5835
5836                         /* skip branch if C1=1 */
5837                         br1 = code;
5838                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5839                         /* branch if C0=0 */
5840                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5841                         amd64_patch (br1, code);
5842                         break;
5843                 }
5844                 case OP_FBLE_UN:
5845                         /* Branch if C013 != 001 */
5846                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5847                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5848                         break;
5849                 case OP_CKFINITE:
5850                         /* Transfer value to the fp stack */
5851                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5852                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5853                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5854
5855                         amd64_push_reg (code, AMD64_RAX);
5856                         amd64_fxam (code);
5857                         amd64_fnstsw (code);
5858                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5859                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5860                         amd64_pop_reg (code, AMD64_RAX);
5861                         amd64_fstp (code, 0);
5862                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5863                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5864                         break;
5865                 case OP_TLS_GET: {
5866                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5867                         break;
5868                 }
5869                 case OP_TLS_GET_REG:
5870                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5871                         break;
5872                 case OP_TLS_SET: {
5873                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5874                         break;
5875                 }
5876                 case OP_TLS_SET_REG: {
5877                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 }
5880                 case OP_MEMORY_BARRIER: {
5881                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5882                                 x86_mfence (code);
5883                         break;
5884                 }
5885                 case OP_ATOMIC_ADD_I4:
5886                 case OP_ATOMIC_ADD_I8: {
5887                         int dreg = ins->dreg;
5888                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5889
5890                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5891                                 dreg = AMD64_R11;
5892
5893                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5894                         amd64_prefix (code, X86_LOCK_PREFIX);
5895                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5896                         /* dreg contains the old value, add with sreg2 value */
5897                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5898
5899                         if (ins->dreg != dreg)
5900                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5901
5902                         break;
5903                 }
5904                 case OP_ATOMIC_EXCHANGE_I4:
5905                 case OP_ATOMIC_EXCHANGE_I8: {
5906                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5907
5908                         /* LOCK prefix is implied. */
5909                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5910                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5911                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5912                         break;
5913                 }
5914                 case OP_ATOMIC_CAS_I4:
5915                 case OP_ATOMIC_CAS_I8: {
5916                         guint32 size;
5917
5918                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5919                                 size = 8;
5920                         else
5921                                 size = 4;
5922
5923                         /*
5924                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5925                          * an explanation of how this works.
5926                          */
5927                         g_assert (ins->sreg3 == AMD64_RAX);
5928                         g_assert (ins->sreg1 != AMD64_RAX);
5929                         g_assert (ins->sreg1 != ins->sreg2);
5930
5931                         amd64_prefix (code, X86_LOCK_PREFIX);
5932                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5933
5934                         if (ins->dreg != AMD64_RAX)
5935                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5936                         break;
5937                 }
5938                 case OP_ATOMIC_LOAD_I1: {
5939                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5940                         break;
5941                 }
5942                 case OP_ATOMIC_LOAD_U1: {
5943                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5944                         break;
5945                 }
5946                 case OP_ATOMIC_LOAD_I2: {
5947                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5948                         break;
5949                 }
5950                 case OP_ATOMIC_LOAD_U2: {
5951                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5952                         break;
5953                 }
5954                 case OP_ATOMIC_LOAD_I4: {
5955                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5956                         break;
5957                 }
5958                 case OP_ATOMIC_LOAD_U4:
5959                 case OP_ATOMIC_LOAD_I8:
5960                 case OP_ATOMIC_LOAD_U8: {
5961                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5962                         break;
5963                 }
5964                 case OP_ATOMIC_LOAD_R4: {
5965                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5966                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5967                         break;
5968                 }
5969                 case OP_ATOMIC_LOAD_R8: {
5970                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5971                         break;
5972                 }
5973                 case OP_ATOMIC_STORE_I1:
5974                 case OP_ATOMIC_STORE_U1:
5975                 case OP_ATOMIC_STORE_I2:
5976                 case OP_ATOMIC_STORE_U2:
5977                 case OP_ATOMIC_STORE_I4:
5978                 case OP_ATOMIC_STORE_U4:
5979                 case OP_ATOMIC_STORE_I8:
5980                 case OP_ATOMIC_STORE_U8: {
5981                         int size;
5982
5983                         switch (ins->opcode) {
5984                         case OP_ATOMIC_STORE_I1:
5985                         case OP_ATOMIC_STORE_U1:
5986                                 size = 1;
5987                                 break;
5988                         case OP_ATOMIC_STORE_I2:
5989                         case OP_ATOMIC_STORE_U2:
5990                                 size = 2;
5991                                 break;
5992                         case OP_ATOMIC_STORE_I4:
5993                         case OP_ATOMIC_STORE_U4:
5994                                 size = 4;
5995                                 break;
5996                         case OP_ATOMIC_STORE_I8:
5997                         case OP_ATOMIC_STORE_U8:
5998                                 size = 8;
5999                                 break;
6000                         }
6001
6002                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6003
6004                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6005                                 x86_mfence (code);
6006                         break;
6007                 }
6008                 case OP_ATOMIC_STORE_R4: {
6009                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6010                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6011
6012                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6013                                 x86_mfence (code);
6014                         break;
6015                 }
6016                 case OP_ATOMIC_STORE_R8: {
6017                         x86_nop (code);
6018                         x86_nop (code);
6019                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6020                         x86_nop (code);
6021                         x86_nop (code);
6022
6023                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6024                                 x86_mfence (code);
6025                         break;
6026                 }
6027                 case OP_CARD_TABLE_WBARRIER: {
6028                         int ptr = ins->sreg1;
6029                         int value = ins->sreg2;
6030                         guchar *br = 0;
6031                         int nursery_shift, card_table_shift;
6032                         gpointer card_table_mask;
6033                         size_t nursery_size;
6034
6035                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6036                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6037                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6038
6039                         /*If either point to the stack we can simply avoid the WB. This happens due to
6040                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6041                          */
6042                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6043                                 continue;
6044
6045                         /*
6046                          * We need one register we can clobber, we choose EDX and make sreg1
6047                          * fixed EAX to work around limitations in the local register allocator.
6048                          * sreg2 might get allocated to EDX, but that is not a problem since
6049                          * we use it before clobbering EDX.
6050                          */
6051                         g_assert (ins->sreg1 == AMD64_RAX);
6052
6053                         /*
6054                          * This is the code we produce:
6055                          *
6056                          *   edx = value
6057                          *   edx >>= nursery_shift
6058                          *   cmp edx, (nursery_start >> nursery_shift)
6059                          *   jne done
6060                          *   edx = ptr
6061                          *   edx >>= card_table_shift
6062                          *   edx += cardtable
6063                          *   [edx] = 1
6064                          * done:
6065                          */
6066
6067                         if (mono_gc_card_table_nursery_check ()) {
6068                                 if (value != AMD64_RDX)
6069                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6070                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6071                                 if (shifted_nursery_start >> 31) {
6072                                         /*
6073                                          * The value we need to compare against is 64 bits, so we need
6074                                          * another spare register.  We use RBX, which we save and
6075                                          * restore.
6076                                          */
6077                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6078                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6079                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6080                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6081                                 } else {
6082                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6083                                 }
6084                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6085                         }
6086                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6087                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6088                         if (card_table_mask)
6089                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6090
6091                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6092                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6093
6094                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6095
6096                         if (mono_gc_card_table_nursery_check ())
6097                                 x86_patch (br, code);
6098                         break;
6099                 }
6100 #ifdef MONO_ARCH_SIMD_INTRINSICS
6101                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6102                 case OP_ADDPS:
6103                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_DIVPS:
6106                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_MULPS:
6109                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_SUBPS:
6112                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_MAXPS:
6115                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_MINPS:
6118                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_COMPPS:
6121                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6122                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6123                         break;
6124                 case OP_ANDPS:
6125                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127                 case OP_ANDNPS:
6128                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130                 case OP_ORPS:
6131                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_XORPS:
6134                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_SQRTPS:
6137                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6138                         break;
6139                 case OP_RSQRTPS:
6140                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6141                         break;
6142                 case OP_RCPPS:
6143                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6144                         break;
6145                 case OP_ADDSUBPS:
6146                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_HADDPS:
6149                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_HSUBPS:
6152                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_DUPPS_HIGH:
6155                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6156                         break;
6157                 case OP_DUPPS_LOW:
6158                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6159                         break;
6160
6161                 case OP_PSHUFLEW_HIGH:
6162                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6163                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6164                         break;
6165                 case OP_PSHUFLEW_LOW:
6166                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6167                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6168                         break;
6169                 case OP_PSHUFLED:
6170                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6171                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6172                         break;
6173                 case OP_SHUFPS:
6174                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6175                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6176                         break;
6177                 case OP_SHUFPD:
6178                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6179                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6180                         break;
6181
6182                 case OP_ADDPD:
6183                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_DIVPD:
6186                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_MULPD:
6189                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_SUBPD:
6192                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_MAXPD:
6195                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_MINPD:
6198                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_COMPPD:
6201                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6202                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6203                         break;
6204                 case OP_ANDPD:
6205                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_ANDNPD:
6208                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_ORPD:
6211                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213                 case OP_XORPD:
6214                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216                 case OP_SQRTPD:
6217                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6218                         break;
6219                 case OP_ADDSUBPD:
6220                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_HADDPD:
6223                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225                 case OP_HSUBPD:
6226                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_DUPPD:
6229                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6230                         break;
6231
6232                 case OP_EXTRACT_MASK:
6233                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6234                         break;
6235
6236                 case OP_PAND:
6237                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_POR:
6240                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6241                         break;
6242                 case OP_PXOR:
6243                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6244                         break;
6245
6246                 case OP_PADDB:
6247                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249                 case OP_PADDW:
6250                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6251                         break;
6252                 case OP_PADDD:
6253                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6254                         break;
6255                 case OP_PADDQ:
6256                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6257                         break;
6258
6259                 case OP_PSUBB:
6260                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262                 case OP_PSUBW:
6263                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6264                         break;
6265                 case OP_PSUBD:
6266                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6267                         break;
6268                 case OP_PSUBQ:
6269                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6270                         break;
6271
6272                 case OP_PMAXB_UN:
6273                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275                 case OP_PMAXW_UN:
6276                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6277                         break;
6278                 case OP_PMAXD_UN:
6279                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6280                         break;
6281
6282                 case OP_PMAXB:
6283                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285                 case OP_PMAXW:
6286                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6287                         break;
6288                 case OP_PMAXD:
6289                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6290                         break;
6291
6292                 case OP_PAVGB_UN:
6293                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295                 case OP_PAVGW_UN:
6296                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6297                         break;
6298
6299                 case OP_PMINB_UN:
6300                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302                 case OP_PMINW_UN:
6303                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6304                         break;
6305                 case OP_PMIND_UN:
6306                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6307                         break;
6308
6309                 case OP_PMINB:
6310                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6311                         break;
6312                 case OP_PMINW:
6313                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6314                         break;
6315                 case OP_PMIND:
6316                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6317                         break;
6318
6319                 case OP_PCMPEQB:
6320                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6321                         break;
6322                 case OP_PCMPEQW:
6323                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6324                         break;
6325                 case OP_PCMPEQD:
6326                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6327                         break;
6328                 case OP_PCMPEQQ:
6329                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6330                         break;
6331
6332                 case OP_PCMPGTB:
6333                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6334                         break;
6335                 case OP_PCMPGTW:
6336                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6337                         break;
6338                 case OP_PCMPGTD:
6339                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6340                         break;
6341                 case OP_PCMPGTQ:
6342                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6343                         break;
6344
6345                 case OP_PSUM_ABS_DIFF:
6346                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6347                         break;
6348
6349                 case OP_UNPACK_LOWB:
6350                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6351                         break;
6352                 case OP_UNPACK_LOWW:
6353                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6354                         break;
6355                 case OP_UNPACK_LOWD:
6356                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6357                         break;
6358                 case OP_UNPACK_LOWQ:
6359                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6360                         break;
6361                 case OP_UNPACK_LOWPS:
6362                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6363                         break;
6364                 case OP_UNPACK_LOWPD:
6365                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6366                         break;
6367
6368                 case OP_UNPACK_HIGHB:
6369                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371                 case OP_UNPACK_HIGHW:
6372                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6373                         break;
6374                 case OP_UNPACK_HIGHD:
6375                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6376                         break;
6377                 case OP_UNPACK_HIGHQ:
6378                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6379                         break;
6380                 case OP_UNPACK_HIGHPS:
6381                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6382                         break;
6383                 case OP_UNPACK_HIGHPD:
6384                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6385                         break;
6386
6387                 case OP_PACKW:
6388                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6389                         break;
6390                 case OP_PACKD:
6391                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6392                         break;
6393                 case OP_PACKW_UN:
6394                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6395                         break;
6396                 case OP_PACKD_UN:
6397                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6398                         break;
6399
6400                 case OP_PADDB_SAT_UN:
6401                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6402                         break;
6403                 case OP_PSUBB_SAT_UN:
6404                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6405                         break;
6406                 case OP_PADDW_SAT_UN:
6407                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6408                         break;
6409                 case OP_PSUBW_SAT_UN:
6410                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6411                         break;
6412
6413                 case OP_PADDB_SAT:
6414                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6415                         break;
6416                 case OP_PSUBB_SAT:
6417                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6418                         break;
6419                 case OP_PADDW_SAT:
6420                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6421                         break;
6422                 case OP_PSUBW_SAT:
6423                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6424                         break;
6425
6426                 case OP_PMULW:
6427                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6428                         break;
6429                 case OP_PMULD:
6430                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6431                         break;
6432                 case OP_PMULQ:
6433                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6434                         break;
6435                 case OP_PMULW_HIGH_UN:
6436                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6437                         break;
6438                 case OP_PMULW_HIGH:
6439                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6440                         break;
6441
6442                 case OP_PSHRW:
6443                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6444                         break;
6445                 case OP_PSHRW_REG:
6446                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6447                         break;
6448
6449                 case OP_PSARW:
6450                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6451                         break;
6452                 case OP_PSARW_REG:
6453                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6454                         break;
6455
6456                 case OP_PSHLW:
6457                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6458                         break;
6459                 case OP_PSHLW_REG:
6460                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6461                         break;
6462
6463                 case OP_PSHRD:
6464                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6465                         break;
6466                 case OP_PSHRD_REG:
6467                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6468                         break;
6469
6470                 case OP_PSARD:
6471                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6472                         break;
6473                 case OP_PSARD_REG:
6474                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6475                         break;
6476
6477                 case OP_PSHLD:
6478                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6479                         break;
6480                 case OP_PSHLD_REG:
6481                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6482                         break;
6483
6484                 case OP_PSHRQ:
6485                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6486                         break;
6487                 case OP_PSHRQ_REG:
6488                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6489                         break;
6490
6491                 /*TODO: This is appart of the sse spec but not added
6492                 case OP_PSARQ:
6493                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6494                         break;
6495                 case OP_PSARQ_REG:
6496                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6497                         break;
6498                 */
6499
6500                 case OP_PSHLQ:
6501                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6502                         break;
6503                 case OP_PSHLQ_REG:
6504                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6505                         break;
6506                 case OP_CVTDQ2PD:
6507                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6508                         break;
6509                 case OP_CVTDQ2PS:
6510                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6511                         break;
6512                 case OP_CVTPD2DQ:
6513                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6514                         break;
6515                 case OP_CVTPD2PS:
6516                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6517                         break;
6518                 case OP_CVTPS2DQ:
6519                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6520                         break;
6521                 case OP_CVTPS2PD:
6522                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6523                         break;
6524                 case OP_CVTTPD2DQ:
6525                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6526                         break;
6527                 case OP_CVTTPS2DQ:
6528                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6529                         break;
6530
6531                 case OP_ICONV_TO_X:
6532                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6533                         break;
6534                 case OP_EXTRACT_I4:
6535                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6536                         break;
6537                 case OP_EXTRACT_I8:
6538                         if (ins->inst_c0) {
6539                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6540                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6541                         } else {
6542                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6543                         }
6544                         break;
6545                 case OP_EXTRACT_I1:
6546                 case OP_EXTRACT_U1:
6547                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6548                         if (ins->inst_c0)
6549                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6550                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6551                         break;
6552                 case OP_EXTRACT_I2:
6553                 case OP_EXTRACT_U2:
6554                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6555                         if (ins->inst_c0)
6556                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6557                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6558                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6559                         break;
6560                 case OP_EXTRACT_R8:
6561                         if (ins->inst_c0)
6562                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6563                         else
6564                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6565                         break;
6566                 case OP_INSERT_I2:
6567                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6568                         break;
6569                 case OP_EXTRACTX_U2:
6570                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6571                         break;
6572                 case OP_INSERTX_U1_SLOW:
6573                         /*sreg1 is the extracted ireg (scratch)
6574                         /sreg2 is the to be inserted ireg (scratch)
6575                         /dreg is the xreg to receive the value*/
6576
6577                         /*clear the bits from the extracted word*/
6578                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6579                         /*shift the value to insert if needed*/
6580                         if (ins->inst_c0 & 1)
6581                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6582                         /*join them together*/
6583                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6584                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6585                         break;
6586                 case OP_INSERTX_I4_SLOW:
6587                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6588                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6589                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6590                         break;
6591                 case OP_INSERTX_I8_SLOW:
6592                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6593                         if (ins->inst_c0)
6594                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6595                         else
6596                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6597                         break;
6598
6599                 case OP_INSERTX_R4_SLOW:
6600                         switch (ins->inst_c0) {
6601                         case 0:
6602                                 if (cfg->r4fp)
6603                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6604                                 else
6605                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6606                                 break;
6607                         case 1:
6608                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6609                                 if (cfg->r4fp)
6610                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6611                                 else
6612                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6613                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6614                                 break;
6615                         case 2:
6616                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6617                                 if (cfg->r4fp)
6618                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6619                                 else
6620                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6621                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6622                                 break;
6623                         case 3:
6624                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6625                                 if (cfg->r4fp)
6626                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6627                                 else
6628                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6629                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6630                                 break;
6631                         }
6632                         break;
6633                 case OP_INSERTX_R8_SLOW:
6634                         if (ins->inst_c0)
6635                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6636                         else
6637                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6638                         break;
6639                 case OP_STOREX_MEMBASE_REG:
6640                 case OP_STOREX_MEMBASE:
6641                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6642                         break;
6643                 case OP_LOADX_MEMBASE:
6644                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6645                         break;
6646                 case OP_LOADX_ALIGNED_MEMBASE:
6647                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6648                         break;
6649                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6650                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6651                         break;
6652                 case OP_STOREX_NTA_MEMBASE_REG:
6653                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6654                         break;
6655                 case OP_PREFETCH_MEMBASE:
6656                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6657                         break;
6658
6659                 case OP_XMOVE:
6660                         /*FIXME the peephole pass should have killed this*/
6661                         if (ins->dreg != ins->sreg1)
6662                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6663                         break;
6664                 case OP_XZERO:
6665                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6666                         break;
6667                 case OP_ICONV_TO_R4_RAW:
6668                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6669                         break;
6670
6671                 case OP_FCONV_TO_R8_X:
6672                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6673                         break;
6674
6675                 case OP_XCONV_R8_TO_I4:
6676                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6677                         switch (ins->backend.source_opcode) {
6678                         case OP_FCONV_TO_I1:
6679                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6680                                 break;
6681                         case OP_FCONV_TO_U1:
6682                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6683                                 break;
6684                         case OP_FCONV_TO_I2:
6685                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6686                                 break;
6687                         case OP_FCONV_TO_U2:
6688                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6689                                 break;
6690                         }
6691                         break;
6692
6693                 case OP_EXPAND_I2:
6694                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6695                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6696                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6697                         break;
6698                 case OP_EXPAND_I4:
6699                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6700                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6701                         break;
6702                 case OP_EXPAND_I8:
6703                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6704                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6705                         break;
6706                 case OP_EXPAND_R4:
6707                         if (cfg->r4fp) {
6708                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6709                         } else {
6710                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6711                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6712                         }
6713                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6714                         break;
6715                 case OP_EXPAND_R8:
6716                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6717                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6718                         break;
6719 #endif
6720                 case OP_LIVERANGE_START: {
6721                         if (cfg->verbose_level > 1)
6722                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6723                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6724                         break;
6725                 }
6726                 case OP_LIVERANGE_END: {
6727                         if (cfg->verbose_level > 1)
6728                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6729                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6730                         break;
6731                 }
6732                 case OP_GC_SAFE_POINT: {
6733                         const char *polling_func = NULL;
6734                         int compare_val = 0;
6735                         guint8 *br [1];
6736
6737 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6738                         polling_func = "mono_nacl_gc";
6739                         compare_val = 0xFFFFFFFF;
6740 #else
6741                         g_assert (mono_threads_is_coop_enabled ());
6742                         polling_func = "mono_threads_state_poll";
6743                         compare_val = 1;
6744 #endif
6745
6746                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6747                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6748                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6749                         amd64_patch (br[0], code);
6750                         break;
6751                 }
6752
6753                 case OP_GC_LIVENESS_DEF:
6754                 case OP_GC_LIVENESS_USE:
6755                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6756                         ins->backend.pc_offset = code - cfg->native_code;
6757                         break;
6758                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6759                         ins->backend.pc_offset = code - cfg->native_code;
6760                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6761                         break;
6762                 default:
6763                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6764                         g_assert_not_reached ();
6765                 }
6766
6767                 if ((code - cfg->native_code - offset) > max_len) {
6768 #if !defined(__native_client_codegen__)
6769                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6770                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6771                         g_assert_not_reached ();
6772 #endif
6773                 }
6774         }
6775
6776         cfg->code_len = code - cfg->native_code;
6777 }
6778
6779 #endif /* DISABLE_JIT */
6780
6781 void
6782 mono_arch_register_lowlevel_calls (void)
6783 {
6784         /* The signature doesn't matter */
6785         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6786 }
6787
6788 void
6789 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6790 {
6791         unsigned char *ip = ji->ip.i + code;
6792
6793         /*
6794          * Debug code to help track down problems where the target of a near call is
6795          * is not valid.
6796          */
6797         if (amd64_is_near_call (ip)) {
6798                 gint64 disp = (guint8*)target - (guint8*)ip;
6799
6800                 if (!amd64_is_imm32 (disp)) {
6801                         printf ("TYPE: %d\n", ji->type);
6802                         switch (ji->type) {
6803                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6804                                 printf ("V: %s\n", ji->data.name);
6805                                 break;
6806                         case MONO_PATCH_INFO_METHOD_JUMP:
6807                         case MONO_PATCH_INFO_METHOD:
6808                                 printf ("V: %s\n", ji->data.method->name);
6809                                 break;
6810                         default:
6811                                 break;
6812                         }
6813                 }
6814         }
6815
6816         amd64_patch (ip, (gpointer)target);
6817 }
6818
6819 #ifndef DISABLE_JIT
6820
6821 static int
6822 get_max_epilog_size (MonoCompile *cfg)
6823 {
6824         int max_epilog_size = 16;
6825
6826         if (cfg->method->save_lmf)
6827                 max_epilog_size += 256;
6828
6829         if (mono_jit_trace_calls != NULL)
6830                 max_epilog_size += 50;
6831
6832         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6833                 max_epilog_size += 50;
6834
6835         max_epilog_size += (AMD64_NREG * 2);
6836
6837         return max_epilog_size;
6838 }
6839
6840 /*
6841  * This macro is used for testing whenever the unwinder works correctly at every point
6842  * where an async exception can happen.
6843  */
6844 /* This will generate a SIGSEGV at the given point in the code */
6845 #define async_exc_point(code) do { \
6846     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6847          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6848              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6849          cfg->arch.async_point_count ++; \
6850     } \
6851 } while (0)
6852
6853 guint8 *
6854 mono_arch_emit_prolog (MonoCompile *cfg)
6855 {
6856         MonoMethod *method = cfg->method;
6857         MonoBasicBlock *bb;
6858         MonoMethodSignature *sig;
6859         MonoInst *ins;
6860         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6861         guint8 *code;
6862         CallInfo *cinfo;
6863         MonoInst *lmf_var = cfg->lmf_var;
6864         gboolean args_clobbered = FALSE;
6865         gboolean trace = FALSE;
6866 #ifdef __native_client_codegen__
6867         guint alignment_check;
6868 #endif
6869
6870         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6871
6872 #if defined(__default_codegen__)
6873         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6874 #elif defined(__native_client_codegen__)
6875         /* native_code_alloc is not 32-byte aligned, native_code is. */
6876         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6877
6878         /* Align native_code to next nearest kNaclAlignment byte. */
6879         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6880         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6881
6882         code = cfg->native_code;
6883
6884         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6885         g_assert (alignment_check == 0);
6886 #endif
6887
6888         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6889                 trace = TRUE;
6890
6891         /* Amount of stack space allocated by register saving code */
6892         pos = 0;
6893
6894         /* Offset between RSP and the CFA */
6895         cfa_offset = 0;
6896
6897         /*
6898          * The prolog consists of the following parts:
6899          * FP present:
6900          * - push rbp, mov rbp, rsp
6901          * - save callee saved regs using pushes
6902          * - allocate frame
6903          * - save rgctx if needed
6904          * - save lmf if needed
6905          * FP not present:
6906          * - allocate frame
6907          * - save rgctx if needed
6908          * - save lmf if needed
6909          * - save callee saved regs using moves
6910          */
6911
6912         // CFA = sp + 8
6913         cfa_offset = 8;
6914         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6915         // IP saved at CFA - 8
6916         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6917         async_exc_point (code);
6918         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6919
6920         if (!cfg->arch.omit_fp) {
6921                 amd64_push_reg (code, AMD64_RBP);
6922                 cfa_offset += 8;
6923                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6924                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6925                 async_exc_point (code);
6926 #ifdef TARGET_WIN32
6927                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6928 #endif
6929                 /* These are handled automatically by the stack marking code */
6930                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6931
6932                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6933                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6934                 async_exc_point (code);
6935 #ifdef TARGET_WIN32
6936                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6937 #endif
6938         }
6939
6940         /* The param area is always at offset 0 from sp */
6941         /* This needs to be allocated here, since it has to come after the spill area */
6942         if (cfg->param_area) {
6943                 if (cfg->arch.omit_fp)
6944                         // FIXME:
6945                         g_assert_not_reached ();
6946                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6947         }
6948
6949         if (cfg->arch.omit_fp) {
6950                 /*
6951                  * On enter, the stack is misaligned by the pushing of the return
6952                  * address. It is either made aligned by the pushing of %rbp, or by
6953                  * this.
6954                  */
6955                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6956                 if ((alloc_size % 16) == 0) {
6957                         alloc_size += 8;
6958                         /* Mark the padding slot as NOREF */
6959                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6960                 }
6961         } else {
6962                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6963                 if (cfg->stack_offset != alloc_size) {
6964                         /* Mark the padding slot as NOREF */
6965                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6966                 }
6967                 cfg->arch.sp_fp_offset = alloc_size;
6968                 alloc_size -= pos;
6969         }
6970
6971         cfg->arch.stack_alloc_size = alloc_size;
6972
6973         /* Allocate stack frame */
6974         if (alloc_size) {
6975                 /* See mono_emit_stack_alloc */
6976 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6977                 guint32 remaining_size = alloc_size;
6978                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6979                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6980                 guint32 offset = code - cfg->native_code;
6981                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6982                         while (required_code_size >= (cfg->code_size - offset))
6983                                 cfg->code_size *= 2;
6984                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6985                         code = cfg->native_code + offset;
6986                         cfg->stat_code_reallocs++;
6987                 }
6988
6989                 while (remaining_size >= 0x1000) {
6990                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6991                         if (cfg->arch.omit_fp) {
6992                                 cfa_offset += 0x1000;
6993                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6994                         }
6995                         async_exc_point (code);
6996 #ifdef TARGET_WIN32
6997                         if (cfg->arch.omit_fp)
6998                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6999 #endif
7000
7001                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7002                         remaining_size -= 0x1000;
7003                 }
7004                 if (remaining_size) {
7005                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7006                         if (cfg->arch.omit_fp) {
7007                                 cfa_offset += remaining_size;
7008                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7009                                 async_exc_point (code);
7010                         }
7011 #ifdef TARGET_WIN32
7012                         if (cfg->arch.omit_fp)
7013                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7014 #endif
7015                 }
7016 #else
7017                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7018                 if (cfg->arch.omit_fp) {
7019                         cfa_offset += alloc_size;
7020                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7021                         async_exc_point (code);
7022                 }
7023 #endif
7024         }
7025
7026         /* Stack alignment check */
7027 #if 0
7028         {
7029                 guint8 *buf;
7030
7031                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7032                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7033                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7034                 buf = code;
7035                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
7036                 amd64_breakpoint (code);
7037                 amd64_patch (buf, code);
7038         }
7039 #endif
7040
7041         if (mini_get_debug_options ()->init_stacks) {
7042                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7043
7044                 /* Save registers to the red zone */
7045                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7046                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7047
7048                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7049                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7050                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7051
7052                 amd64_cld (code);
7053 #if defined(__default_codegen__)
7054                 amd64_prefix (code, X86_REP_PREFIX);
7055                 amd64_stosl (code);
7056 #elif defined(__native_client_codegen__)
7057                 /* NaCl stos pseudo-instruction */
7058                 amd64_codegen_pre (code);
7059                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7060                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7061                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7062                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7063                 amd64_prefix (code, X86_REP_PREFIX);
7064                 amd64_stosl (code);
7065                 amd64_codegen_post (code);
7066 #endif /* __native_client_codegen__ */
7067
7068                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7069                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7070         }
7071
7072         /* Save LMF */
7073         if (method->save_lmf)
7074                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7075
7076         /* Save callee saved registers */
7077         if (cfg->arch.omit_fp) {
7078                 save_area_offset = cfg->arch.reg_save_area_offset;
7079                 /* Save caller saved registers after sp is adjusted */
7080                 /* The registers are saved at the bottom of the frame */
7081                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7082         } else {
7083                 /* The registers are saved just below the saved rbp */
7084                 save_area_offset = cfg->arch.reg_save_area_offset;
7085         }
7086
7087         for (i = 0; i < AMD64_NREG; ++i) {
7088                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7089                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7090
7091                         if (cfg->arch.omit_fp) {
7092                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7093                                 /* These are handled automatically by the stack marking code */
7094                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7095                         } else {
7096                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7097                                 // FIXME: GC
7098                         }
7099
7100                         save_area_offset += 8;
7101                         async_exc_point (code);
7102                 }
7103         }
7104
7105         /* store runtime generic context */
7106         if (cfg->rgctx_var) {
7107                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7108                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7109
7110                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7111
7112                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7113                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7114         }
7115
7116         /* compute max_length in order to use short forward jumps */
7117         max_epilog_size = get_max_epilog_size (cfg);
7118         if (cfg->opt & MONO_OPT_BRANCH) {
7119                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7120                         MonoInst *ins;
7121                         int max_length = 0;
7122
7123                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7124                                 max_length += 6;
7125                         /* max alignment for loops */
7126                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7127                                 max_length += LOOP_ALIGNMENT;
7128 #ifdef __native_client_codegen__
7129                         /* max alignment for native client */
7130                         max_length += kNaClAlignment;
7131 #endif
7132
7133                         MONO_BB_FOR_EACH_INS (bb, ins) {
7134 #ifdef __native_client_codegen__
7135                                 {
7136                                         int space_in_block = kNaClAlignment -
7137                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7138                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7139                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7140                                                 max_length += space_in_block;
7141                                         }
7142                                 }
7143 #endif  /*__native_client_codegen__*/
7144                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7145                         }
7146
7147                         /* Take prolog and epilog instrumentation into account */
7148                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7149                                 max_length += max_epilog_size;
7150
7151                         bb->max_length = max_length;
7152                 }
7153         }
7154
7155         sig = mono_method_signature (method);
7156         pos = 0;
7157
7158         cinfo = (CallInfo *)cfg->arch.cinfo;
7159
7160         if (sig->ret->type != MONO_TYPE_VOID) {
7161                 /* Save volatile arguments to the stack */
7162                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7163                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7164         }
7165
7166         /* Keep this in sync with emit_load_volatile_arguments */
7167         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7168                 ArgInfo *ainfo = cinfo->args + i;
7169
7170                 ins = cfg->args [i];
7171
7172                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7173                         /* Unused arguments */
7174                         continue;
7175
7176                 /* Save volatile arguments to the stack */
7177                 if (ins->opcode != OP_REGVAR) {
7178                         switch (ainfo->storage) {
7179                         case ArgInIReg: {
7180                                 guint32 size = 8;
7181
7182                                 /* FIXME: I1 etc */
7183                                 /*
7184                                 if (stack_offset & 0x1)
7185                                         size = 1;
7186                                 else if (stack_offset & 0x2)
7187                                         size = 2;
7188                                 else if (stack_offset & 0x4)
7189                                         size = 4;
7190                                 else
7191                                         size = 8;
7192                                 */
7193                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7194
7195                                 /*
7196                                  * Save the original location of 'this',
7197                                  * get_generic_info_from_stack_frame () needs this to properly look up
7198                                  * the argument value during the handling of async exceptions.
7199                                  */
7200                                 if (ins == cfg->args [0]) {
7201                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7202                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7203                                 }
7204                                 break;
7205                         }
7206                         case ArgInFloatSSEReg:
7207                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7208                                 break;
7209                         case ArgInDoubleSSEReg:
7210                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7211                                 break;
7212                         case ArgValuetypeInReg:
7213                                 for (quad = 0; quad < 2; quad ++) {
7214                                         switch (ainfo->pair_storage [quad]) {
7215                                         case ArgInIReg:
7216                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7217                                                 break;
7218                                         case ArgInFloatSSEReg:
7219                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7220                                                 break;
7221                                         case ArgInDoubleSSEReg:
7222                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7223                                                 break;
7224                                         case ArgNone:
7225                                                 break;
7226                                         default:
7227                                                 g_assert_not_reached ();
7228                                         }
7229                                 }
7230                                 break;
7231                         case ArgValuetypeAddrInIReg:
7232                                 if (ainfo->pair_storage [0] == ArgInIReg)
7233                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7234                                 break;
7235                         case ArgGSharedVtInReg:
7236                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7237                                 break;
7238                         default:
7239                                 break;
7240                         }
7241                 } else {
7242                         /* Argument allocated to (non-volatile) register */
7243                         switch (ainfo->storage) {
7244                         case ArgInIReg:
7245                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7246                                 break;
7247                         case ArgOnStack:
7248                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7249                                 break;
7250                         default:
7251                                 g_assert_not_reached ();
7252                         }
7253
7254                         if (ins == cfg->args [0]) {
7255                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7256                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7257                         }
7258                 }
7259         }
7260
7261         if (cfg->method->save_lmf)
7262                 args_clobbered = TRUE;
7263
7264         if (trace) {
7265                 args_clobbered = TRUE;
7266                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7267         }
7268
7269         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7270                 args_clobbered = TRUE;
7271
7272         /*
7273          * Optimize the common case of the first bblock making a call with the same
7274          * arguments as the method. This works because the arguments are still in their
7275          * original argument registers.
7276          * FIXME: Generalize this
7277          */
7278         if (!args_clobbered) {
7279                 MonoBasicBlock *first_bb = cfg->bb_entry;
7280                 MonoInst *next;
7281                 int filter = FILTER_IL_SEQ_POINT;
7282
7283                 next = mono_bb_first_inst (first_bb, filter);
7284                 if (!next && first_bb->next_bb) {
7285                         first_bb = first_bb->next_bb;
7286                         next = mono_bb_first_inst (first_bb, filter);
7287                 }
7288
7289                 if (first_bb->in_count > 1)
7290                         next = NULL;
7291
7292                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7293                         ArgInfo *ainfo = cinfo->args + i;
7294                         gboolean match = FALSE;
7295
7296                         ins = cfg->args [i];
7297                         if (ins->opcode != OP_REGVAR) {
7298                                 switch (ainfo->storage) {
7299                                 case ArgInIReg: {
7300                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7301                                                 if (next->dreg == ainfo->reg) {
7302                                                         NULLIFY_INS (next);
7303                                                         match = TRUE;
7304                                                 } else {
7305                                                         next->opcode = OP_MOVE;
7306                                                         next->sreg1 = ainfo->reg;
7307                                                         /* Only continue if the instruction doesn't change argument regs */
7308                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7309                                                                 match = TRUE;
7310                                                 }
7311                                         }
7312                                         break;
7313                                 }
7314                                 default:
7315                                         break;
7316                                 }
7317                         } else {
7318                                 /* Argument allocated to (non-volatile) register */
7319                                 switch (ainfo->storage) {
7320                                 case ArgInIReg:
7321                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7322                                                 NULLIFY_INS (next);
7323                                                 match = TRUE;
7324                                         }
7325                                         break;
7326                                 default:
7327                                         break;
7328                                 }
7329                         }
7330
7331                         if (match) {
7332                                 next = mono_inst_next (next, filter);
7333                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7334                                 if (!next)
7335                                         break;
7336                         }
7337                 }
7338         }
7339
7340         if (cfg->gen_sdb_seq_points) {
7341                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7342
7343                 /* Initialize seq_point_info_var */
7344                 if (cfg->compile_aot) {
7345                         /* Initialize the variable from a GOT slot */
7346                         /* Same as OP_AOTCONST */
7347                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7348                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7349                         g_assert (info_var->opcode == OP_REGOFFSET);
7350                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7351                 }
7352
7353                 if (cfg->compile_aot) {
7354                         /* Initialize ss_tramp_var */
7355                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7356                         g_assert (ins->opcode == OP_REGOFFSET);
7357
7358                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7359                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7360                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7361                 } else {
7362                         /* Initialize ss_tramp_var */
7363                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7364                         g_assert (ins->opcode == OP_REGOFFSET);
7365
7366                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7367                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7368
7369                         /* Initialize bp_tramp_var */
7370                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7371                         g_assert (ins->opcode == OP_REGOFFSET);
7372
7373                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7374                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7375                 }
7376         }
7377
7378         cfg->code_len = code - cfg->native_code;
7379
7380         g_assert (cfg->code_len < cfg->code_size);
7381
7382         return code;
7383 }
7384
7385 void
7386 mono_arch_emit_epilog (MonoCompile *cfg)
7387 {
7388         MonoMethod *method = cfg->method;
7389         int quad, i;
7390         guint8 *code;
7391         int max_epilog_size;
7392         CallInfo *cinfo;
7393         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7394         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7395
7396         max_epilog_size = get_max_epilog_size (cfg);
7397
7398         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7399                 cfg->code_size *= 2;
7400                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7401                 cfg->stat_code_reallocs++;
7402         }
7403         code = cfg->native_code + cfg->code_len;
7404
7405         cfg->has_unwind_info_for_epilog = TRUE;
7406
7407         /* Mark the start of the epilog */
7408         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7409
7410         /* Save the uwind state which is needed by the out-of-line code */
7411         mono_emit_unwind_op_remember_state (cfg, code);
7412
7413         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7414                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7415
7416         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7417
7418         if (method->save_lmf) {
7419                 /* check if we need to restore protection of the stack after a stack overflow */
7420                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7421                         guint8 *patch;
7422                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7423                         /* we load the value in a separate instruction: this mechanism may be
7424                          * used later as a safer way to do thread interruption
7425                          */
7426                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7427                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7428                         patch = code;
7429                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7430                         /* note that the call trampoline will preserve eax/edx */
7431                         x86_call_reg (code, X86_ECX);
7432                         x86_patch (patch, code);
7433                 } else {
7434                         /* FIXME: maybe save the jit tls in the prolog */
7435                 }
7436                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7437                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7438                 }
7439         }
7440
7441         /* Restore callee saved regs */
7442         for (i = 0; i < AMD64_NREG; ++i) {
7443                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7444                         /* Restore only used_int_regs, not arch.saved_iregs */
7445                         if (cfg->used_int_regs & (1 << i)) {
7446                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7447                                 mono_emit_unwind_op_same_value (cfg, code, i);
7448                                 async_exc_point (code);
7449                         }
7450                         save_area_offset += 8;
7451                 }
7452         }
7453
7454         /* Load returned vtypes into registers if needed */
7455         cinfo = (CallInfo *)cfg->arch.cinfo;
7456         if (cinfo->ret.storage == ArgValuetypeInReg) {
7457                 ArgInfo *ainfo = &cinfo->ret;
7458                 MonoInst *inst = cfg->ret;
7459
7460                 for (quad = 0; quad < 2; quad ++) {
7461                         switch (ainfo->pair_storage [quad]) {
7462                         case ArgInIReg:
7463                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7464                                 break;
7465                         case ArgInFloatSSEReg:
7466                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7467                                 break;
7468                         case ArgInDoubleSSEReg:
7469                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7470                                 break;
7471                         case ArgNone:
7472                                 break;
7473                         default:
7474                                 g_assert_not_reached ();
7475                         }
7476                 }
7477         }
7478
7479         if (cfg->arch.omit_fp) {
7480                 if (cfg->arch.stack_alloc_size) {
7481                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7482                 }
7483         } else {
7484                 amd64_leave (code);
7485                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7486         }
7487         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7488         async_exc_point (code);
7489         amd64_ret (code);
7490
7491         /* Restore the unwind state to be the same as before the epilog */
7492         mono_emit_unwind_op_restore_state (cfg, code);
7493
7494         cfg->code_len = code - cfg->native_code;
7495
7496         g_assert (cfg->code_len < cfg->code_size);
7497 }
7498
7499 void
7500 mono_arch_emit_exceptions (MonoCompile *cfg)
7501 {
7502         MonoJumpInfo *patch_info;
7503         int nthrows, i;
7504         guint8 *code;
7505         MonoClass *exc_classes [16];
7506         guint8 *exc_throw_start [16], *exc_throw_end [16];
7507         guint32 code_size = 0;
7508
7509         /* Compute needed space */
7510         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7511                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7512                         code_size += 40;
7513                 if (patch_info->type == MONO_PATCH_INFO_R8)
7514                         code_size += 8 + 15; /* sizeof (double) + alignment */
7515                 if (patch_info->type == MONO_PATCH_INFO_R4)
7516                         code_size += 4 + 15; /* sizeof (float) + alignment */
7517                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7518                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7519         }
7520
7521 #ifdef __native_client_codegen__
7522         /* Give us extra room on Native Client.  This could be   */
7523         /* more carefully calculated, but bundle alignment makes */
7524         /* it much trickier, so *2 like other places is good.    */
7525         code_size *= 2;
7526 #endif
7527
7528         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7529                 cfg->code_size *= 2;
7530                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7531                 cfg->stat_code_reallocs++;
7532         }
7533
7534         code = cfg->native_code + cfg->code_len;
7535
7536         /* add code to raise exceptions */
7537         nthrows = 0;
7538         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7539                 switch (patch_info->type) {
7540                 case MONO_PATCH_INFO_EXC: {
7541                         MonoClass *exc_class;
7542                         guint8 *buf, *buf2;
7543                         guint32 throw_ip;
7544
7545                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7546
7547                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7548                         throw_ip = patch_info->ip.i;
7549
7550                         //x86_breakpoint (code);
7551                         /* Find a throw sequence for the same exception class */
7552                         for (i = 0; i < nthrows; ++i)
7553                                 if (exc_classes [i] == exc_class)
7554                                         break;
7555                         if (i < nthrows) {
7556                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7557                                 x86_jump_code (code, exc_throw_start [i]);
7558                                 patch_info->type = MONO_PATCH_INFO_NONE;
7559                         }
7560                         else {
7561                                 buf = code;
7562                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7563                                 buf2 = code;
7564
7565                                 if (nthrows < 16) {
7566                                         exc_classes [nthrows] = exc_class;
7567                                         exc_throw_start [nthrows] = code;
7568                                 }
7569                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7570
7571                                 patch_info->type = MONO_PATCH_INFO_NONE;
7572
7573                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7574
7575                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7576                                 while (buf < buf2)
7577                                         x86_nop (buf);
7578
7579                                 if (nthrows < 16) {
7580                                         exc_throw_end [nthrows] = code;
7581                                         nthrows ++;
7582                                 }
7583                         }
7584                         break;
7585                 }
7586                 default:
7587                         /* do nothing */
7588                         break;
7589                 }
7590                 g_assert(code < cfg->native_code + cfg->code_size);
7591         }
7592
7593         /* Handle relocations with RIP relative addressing */
7594         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7595                 gboolean remove = FALSE;
7596                 guint8 *orig_code = code;
7597
7598                 switch (patch_info->type) {
7599                 case MONO_PATCH_INFO_R8:
7600                 case MONO_PATCH_INFO_R4: {
7601                         guint8 *pos, *patch_pos;
7602                         guint32 target_pos;
7603
7604                         /* The SSE opcodes require a 16 byte alignment */
7605 #if defined(__default_codegen__)
7606                         code = (guint8*)ALIGN_TO (code, 16);
7607 #elif defined(__native_client_codegen__)
7608                         {
7609                                 /* Pad this out with HLT instructions  */
7610                                 /* or we can get garbage bytes emitted */
7611                                 /* which will fail validation          */
7612                                 guint8 *aligned_code;
7613                                 /* extra align to make room for  */
7614                                 /* mov/push below                      */
7615                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7616                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7617                                 /* The technique of hiding data in an  */
7618                                 /* instruction has a problem here: we  */
7619                                 /* need the data aligned to a 16-byte  */
7620                                 /* boundary but the instruction cannot */
7621                                 /* cross the bundle boundary. so only  */
7622                                 /* odd multiples of 16 can be used     */
7623                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7624                                         aligned_code += 16;
7625                                 }
7626                                 while (code < aligned_code) {
7627                                         *(code++) = 0xf4; /* hlt */
7628                                 }
7629                         }
7630 #endif
7631
7632                         pos = cfg->native_code + patch_info->ip.i;
7633                         if (IS_REX (pos [1])) {
7634                                 patch_pos = pos + 5;
7635                                 target_pos = code - pos - 9;
7636                         }
7637                         else {
7638                                 patch_pos = pos + 4;
7639                                 target_pos = code - pos - 8;
7640                         }
7641
7642                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7643 #ifdef __native_client_codegen__
7644                                 /* Hide 64-bit data in a         */
7645                                 /* "mov imm64, r11" instruction. */
7646                                 /* write it before the start of  */
7647                                 /* the data*/
7648                                 *(code-2) = 0x49; /* prefix      */
7649                                 *(code-1) = 0xbb; /* mov X, %r11 */
7650 #endif
7651                                 *(double*)code = *(double*)patch_info->data.target;
7652                                 code += sizeof (double);
7653                         } else {
7654 #ifdef __native_client_codegen__
7655                                 /* Hide 32-bit data in a        */
7656                                 /* "push imm32" instruction.    */
7657                                 *(code-1) = 0x68; /* push */
7658 #endif
7659                                 *(float*)code = *(float*)patch_info->data.target;
7660                                 code += sizeof (float);
7661                         }
7662
7663                         *(guint32*)(patch_pos) = target_pos;
7664
7665                         remove = TRUE;
7666                         break;
7667                 }
7668                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7669                         guint8 *pos;
7670
7671                         if (cfg->compile_aot)
7672                                 continue;
7673
7674                         /*loading is faster against aligned addresses.*/
7675                         code = (guint8*)ALIGN_TO (code, 8);
7676                         memset (orig_code, 0, code - orig_code);
7677
7678                         pos = cfg->native_code + patch_info->ip.i;
7679
7680                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7681                         if (IS_REX (pos [1]))
7682                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7683                         else
7684                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7685
7686                         *(gpointer*)code = (gpointer)patch_info->data.target;
7687                         code += sizeof (gpointer);
7688
7689                         remove = TRUE;
7690                         break;
7691                 }
7692                 default:
7693                         break;
7694                 }
7695
7696                 if (remove) {
7697                         if (patch_info == cfg->patch_info)
7698                                 cfg->patch_info = patch_info->next;
7699                         else {
7700                                 MonoJumpInfo *tmp;
7701
7702                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7703                                         ;
7704                                 tmp->next = patch_info->next;
7705                         }
7706                 }
7707                 g_assert (code < cfg->native_code + cfg->code_size);
7708         }
7709
7710         cfg->code_len = code - cfg->native_code;
7711
7712         g_assert (cfg->code_len < cfg->code_size);
7713
7714 }
7715
7716 #endif /* DISABLE_JIT */
7717
7718 void*
7719 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7720 {
7721         guchar *code = (guchar *)p;
7722         MonoMethodSignature *sig;
7723         MonoInst *inst;
7724         int i, n, stack_area = 0;
7725
7726         /* Keep this in sync with mono_arch_get_argument_info */
7727
7728         if (enable_arguments) {
7729                 /* Allocate a new area on the stack and save arguments there */
7730                 sig = mono_method_signature (cfg->method);
7731
7732                 n = sig->param_count + sig->hasthis;
7733
7734                 stack_area = ALIGN_TO (n * 8, 16);
7735
7736                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7737
7738                 for (i = 0; i < n; ++i) {
7739                         inst = cfg->args [i];
7740
7741                         if (inst->opcode == OP_REGVAR)
7742                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7743                         else {
7744                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7745                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7746                         }
7747                 }
7748         }
7749
7750         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7751         amd64_set_reg_template (code, AMD64_ARG_REG1);
7752         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7753         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7754
7755         if (enable_arguments)
7756                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7757
7758         return code;
7759 }
7760
7761 enum {
7762         SAVE_NONE,
7763         SAVE_STRUCT,
7764         SAVE_EAX,
7765         SAVE_EAX_EDX,
7766         SAVE_XMM
7767 };
7768
7769 void*
7770 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7771 {
7772         guchar *code = (guchar *)p;
7773         int save_mode = SAVE_NONE;
7774         MonoMethod *method = cfg->method;
7775         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7776         int i;
7777
7778         switch (ret_type->type) {
7779         case MONO_TYPE_VOID:
7780                 /* special case string .ctor icall */
7781                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7782                         save_mode = SAVE_EAX;
7783                 else
7784                         save_mode = SAVE_NONE;
7785                 break;
7786         case MONO_TYPE_I8:
7787         case MONO_TYPE_U8:
7788                 save_mode = SAVE_EAX;
7789                 break;
7790         case MONO_TYPE_R4:
7791         case MONO_TYPE_R8:
7792                 save_mode = SAVE_XMM;
7793                 break;
7794         case MONO_TYPE_GENERICINST:
7795                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7796                         save_mode = SAVE_EAX;
7797                         break;
7798                 }
7799                 /* Fall through */
7800         case MONO_TYPE_VALUETYPE:
7801                 save_mode = SAVE_STRUCT;
7802                 break;
7803         default:
7804                 save_mode = SAVE_EAX;
7805                 break;
7806         }
7807
7808         /* Save the result and copy it into the proper argument register */
7809         switch (save_mode) {
7810         case SAVE_EAX:
7811                 amd64_push_reg (code, AMD64_RAX);
7812                 /* Align stack */
7813                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7814                 if (enable_arguments)
7815                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7816                 break;
7817         case SAVE_STRUCT:
7818                 /* FIXME: */
7819                 if (enable_arguments)
7820                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7821                 break;
7822         case SAVE_XMM:
7823                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7824                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7825                 /* Align stack */
7826                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7827                 /*
7828                  * The result is already in the proper argument register so no copying
7829                  * needed.
7830                  */
7831                 break;
7832         case SAVE_NONE:
7833                 break;
7834         default:
7835                 g_assert_not_reached ();
7836         }
7837
7838         /* Set %al since this is a varargs call */
7839         if (save_mode == SAVE_XMM)
7840                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7841         else
7842                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7843
7844         if (preserve_argument_registers) {
7845                 for (i = 0; i < PARAM_REGS; ++i)
7846                         amd64_push_reg (code, param_regs [i]);
7847         }
7848
7849         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7850         amd64_set_reg_template (code, AMD64_ARG_REG1);
7851         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7852
7853         if (preserve_argument_registers) {
7854                 for (i = PARAM_REGS - 1; i >= 0; --i)
7855                         amd64_pop_reg (code, param_regs [i]);
7856         }
7857
7858         /* Restore result */
7859         switch (save_mode) {
7860         case SAVE_EAX:
7861                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7862                 amd64_pop_reg (code, AMD64_RAX);
7863                 break;
7864         case SAVE_STRUCT:
7865                 /* FIXME: */
7866                 break;
7867         case SAVE_XMM:
7868                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7869                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7870                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7871                 break;
7872         case SAVE_NONE:
7873                 break;
7874         default:
7875                 g_assert_not_reached ();
7876         }
7877
7878         return code;
7879 }
7880
7881 void
7882 mono_arch_flush_icache (guint8 *code, gint size)
7883 {
7884         /* Not needed */
7885 }
7886
7887 void
7888 mono_arch_flush_register_windows (void)
7889 {
7890 }
7891
7892 gboolean
7893 mono_arch_is_inst_imm (gint64 imm)
7894 {
7895         return amd64_use_imm32 (imm);
7896 }
7897
7898 /*
7899  * Determine whenever the trap whose info is in SIGINFO is caused by
7900  * integer overflow.
7901  */
7902 gboolean
7903 mono_arch_is_int_overflow (void *sigctx, void *info)
7904 {
7905         MonoContext ctx;
7906         guint8* rip;
7907         int reg;
7908         gint64 value;
7909
7910         mono_sigctx_to_monoctx (sigctx, &ctx);
7911
7912         rip = (guint8*)ctx.gregs [AMD64_RIP];
7913
7914         if (IS_REX (rip [0])) {
7915                 reg = amd64_rex_b (rip [0]);
7916                 rip ++;
7917         }
7918         else
7919                 reg = 0;
7920
7921         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7922                 /* idiv REG */
7923                 reg += x86_modrm_rm (rip [1]);
7924
7925                 value = ctx.gregs [reg];
7926
7927                 if (value == -1)
7928                         return TRUE;
7929         }
7930
7931         return FALSE;
7932 }
7933
7934 guint32
7935 mono_arch_get_patch_offset (guint8 *code)
7936 {
7937         return 3;
7938 }
7939
7940 /**
7941  * mono_breakpoint_clean_code:
7942  *
7943  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7944  * breakpoints in the original code, they are removed in the copy.
7945  *
7946  * Returns TRUE if no sw breakpoint was present.
7947  */
7948 gboolean
7949 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7950 {
7951         /*
7952          * If method_start is non-NULL we need to perform bound checks, since we access memory
7953          * at code - offset we could go before the start of the method and end up in a different
7954          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7955          * instead.
7956          */
7957         if (!method_start || code - offset >= method_start) {
7958                 memcpy (buf, code - offset, size);
7959         } else {
7960                 int diff = code - method_start;
7961                 memset (buf, 0, size);
7962                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7963         }
7964         return TRUE;
7965 }
7966
7967 #if defined(__native_client_codegen__)
7968 /* For membase calls, we want the base register. for Native Client,  */
7969 /* all indirect calls have the following sequence with the given sizes: */
7970 /* mov %eXX,%eXX                                [2-3]   */
7971 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7972 /* and $0xffffffffffffffe0,%r11d                [4]     */
7973 /* add %r15,%r11                                [3]     */
7974 /* callq *%r11                                  [3]     */
7975
7976
7977 /* Determine if code points to a NaCl call-through-register sequence, */
7978 /* (i.e., the last 3 instructions listed above) */
7979 int
7980 is_nacl_call_reg_sequence(guint8* code)
7981 {
7982         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7983                                "\x4d\x03\xdf"     /* add */
7984                                "\x41\xff\xd3";   /* call */
7985         return memcmp(code, sequence, 10) == 0;
7986 }
7987
7988 /* Determine if code points to the first opcode of the mov membase component */
7989 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7990 /* (there could be a REX prefix before the opcode but it is ignored) */
7991 static int
7992 is_nacl_indirect_call_membase_sequence(guint8* code)
7993 {
7994                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7995         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7996                /* and that src reg = dest reg */
7997                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7998                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7999                IS_REX(code[2]) &&
8000                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
8001                /* and has dst of r11 and base of r15 */
8002                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8003                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8004 }
8005 #endif /* __native_client_codegen__ */
8006
8007 int
8008 mono_arch_get_this_arg_reg (guint8 *code)
8009 {
8010         return AMD64_ARG_REG1;
8011 }
8012
8013 gpointer
8014 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8015 {
8016         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8017 }
8018
8019 #define MAX_ARCH_DELEGATE_PARAMS 10
8020
8021 static gpointer
8022 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8023 {
8024         guint8 *code, *start;
8025         GSList *unwind_ops = NULL;
8026         int i;
8027
8028         unwind_ops = mono_arch_get_cie_program ();
8029
8030         if (has_target) {
8031                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8032
8033                 /* Replace the this argument with the target */
8034                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8035                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8036                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8037
8038                 g_assert ((code - start) < 64);
8039         } else {
8040                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8041
8042                 if (param_count == 0) {
8043                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8044                 } else {
8045                         /* We have to shift the arguments left */
8046                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8047                         for (i = 0; i < param_count; ++i) {
8048 #ifdef TARGET_WIN32
8049                                 if (i < 3)
8050                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8051                                 else
8052                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8053 #else
8054                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8055 #endif
8056                         }
8057
8058                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8059                 }
8060                 g_assert ((code - start) < 64);
8061         }
8062
8063         nacl_global_codeman_validate (&start, 64, &code);
8064         mono_arch_flush_icache (start, code - start);
8065
8066         if (has_target) {
8067                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8068         } else {
8069                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8070                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8071                 g_free (name);
8072         }
8073
8074         if (mono_jit_map_is_enabled ()) {
8075                 char *buff;
8076                 if (has_target)
8077                         buff = (char*)"delegate_invoke_has_target";
8078                 else
8079                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8080                 mono_emit_jit_tramp (start, code - start, buff);
8081                 if (!has_target)
8082                         g_free (buff);
8083         }
8084         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8085
8086         return start;
8087 }
8088
8089 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8090
8091 static gpointer
8092 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8093 {
8094         guint8 *code, *start;
8095         int size = 20;
8096         char *tramp_name;
8097         GSList *unwind_ops;
8098
8099         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8100                 return NULL;
8101
8102         start = code = (guint8 *)mono_global_codeman_reserve (size);
8103
8104         unwind_ops = mono_arch_get_cie_program ();
8105
8106         /* Replace the this argument with the target */
8107         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8108         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8109
8110         if (load_imt_reg) {
8111                 /* Load the IMT reg */
8112                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8113         }
8114
8115         /* Load the vtable */
8116         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8117         amd64_jump_membase (code, AMD64_RAX, offset);
8118         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8119
8120         if (load_imt_reg)
8121                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8122         else
8123                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8124         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8125         g_free (tramp_name);
8126
8127         return start;
8128 }
8129
8130 /*
8131  * mono_arch_get_delegate_invoke_impls:
8132  *
8133  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8134  * trampolines.
8135  */
8136 GSList*
8137 mono_arch_get_delegate_invoke_impls (void)
8138 {
8139         GSList *res = NULL;
8140         MonoTrampInfo *info;
8141         int i;
8142
8143         get_delegate_invoke_impl (&info, TRUE, 0);
8144         res = g_slist_prepend (res, info);
8145
8146         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8147                 get_delegate_invoke_impl (&info, FALSE, i);
8148                 res = g_slist_prepend (res, info);
8149         }
8150
8151         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8152                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8153                 res = g_slist_prepend (res, info);
8154
8155                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8156                 res = g_slist_prepend (res, info);
8157         }
8158
8159         return res;
8160 }
8161
8162 gpointer
8163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8164 {
8165         guint8 *code, *start;
8166         int i;
8167
8168         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8169                 return NULL;
8170
8171         /* FIXME: Support more cases */
8172         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8173                 return NULL;
8174
8175         if (has_target) {
8176                 static guint8* cached = NULL;
8177
8178                 if (cached)
8179                         return cached;
8180
8181                 if (mono_aot_only) {
8182                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8183                 } else {
8184                         MonoTrampInfo *info;
8185                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8186                         mono_tramp_info_register (info, NULL);
8187                 }
8188
8189                 mono_memory_barrier ();
8190
8191                 cached = start;
8192         } else {
8193                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8194                 for (i = 0; i < sig->param_count; ++i)
8195                         if (!mono_is_regsize_var (sig->params [i]))
8196                                 return NULL;
8197                 if (sig->param_count > 4)
8198                         return NULL;
8199
8200                 code = cache [sig->param_count];
8201                 if (code)
8202                         return code;
8203
8204                 if (mono_aot_only) {
8205                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8206                         start = (guint8 *)mono_aot_get_trampoline (name);
8207                         g_free (name);
8208                 } else {
8209                         MonoTrampInfo *info;
8210                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8211                         mono_tramp_info_register (info, NULL);
8212                 }
8213
8214                 mono_memory_barrier ();
8215
8216                 cache [sig->param_count] = start;
8217         }
8218
8219         return start;
8220 }
8221
8222 gpointer
8223 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8224 {
8225         MonoTrampInfo *info;
8226         gpointer code;
8227
8228         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8229         if (code)
8230                 mono_tramp_info_register (info, NULL);
8231         return code;
8232 }
8233
8234 void
8235 mono_arch_finish_init (void)
8236 {
8237 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8238         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8239 #endif
8240 }
8241
8242 void
8243 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8244 {
8245 }
8246
8247 #if defined(__default_codegen__)
8248 #define CMP_SIZE (6 + 1)
8249 #define CMP_REG_REG_SIZE (4 + 1)
8250 #define BR_SMALL_SIZE 2
8251 #define BR_LARGE_SIZE 6
8252 #define MOV_REG_IMM_SIZE 10
8253 #define MOV_REG_IMM_32BIT_SIZE 6
8254 #define JUMP_REG_SIZE (2 + 1)
8255 #elif defined(__native_client_codegen__)
8256 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8257 #define CMP_SIZE ((6 + 1) * 2 - 1)
8258 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8259 #define BR_SMALL_SIZE (2 * 2 - 1)
8260 #define BR_LARGE_SIZE (6 * 2 - 1)
8261 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8262 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8263 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8264 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8265 /* Jump membase's size is large and unpredictable    */
8266 /* in native client, just pad it out a whole bundle. */
8267 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8268 #endif
8269
8270 static int
8271 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8272 {
8273         int i, distance = 0;
8274         for (i = start; i < target; ++i)
8275                 distance += imt_entries [i]->chunk_size;
8276         return distance;
8277 }
8278
8279 /*
8280  * LOCKING: called with the domain lock held
8281  */
8282 gpointer
8283 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8284         gpointer fail_tramp)
8285 {
8286         int i;
8287         int size = 0;
8288         guint8 *code, *start;
8289         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8290         GSList *unwind_ops;
8291
8292         for (i = 0; i < count; ++i) {
8293                 MonoIMTCheckItem *item = imt_entries [i];
8294                 if (item->is_equals) {
8295                         if (item->check_target_idx) {
8296                                 if (!item->compare_done) {
8297                                         if (amd64_use_imm32 ((gint64)item->key))
8298                                                 item->chunk_size += CMP_SIZE;
8299                                         else
8300                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8301                                 }
8302                                 if (item->has_target_code) {
8303                                         item->chunk_size += MOV_REG_IMM_SIZE;
8304                                 } else {
8305                                         if (vtable_is_32bit)
8306                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8307                                         else
8308                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8309 #ifdef __native_client_codegen__
8310                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8311 #endif
8312                                 }
8313                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8314                         } else {
8315                                 if (fail_tramp) {
8316                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8317                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8318                                 } else {
8319                                         if (vtable_is_32bit)
8320                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8321                                         else
8322                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8323                                         item->chunk_size += JUMP_REG_SIZE;
8324                                         /* with assert below:
8325                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8326                                          */
8327 #ifdef __native_client_codegen__
8328                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8329 #endif
8330                                 }
8331                         }
8332                 } else {
8333                         if (amd64_use_imm32 ((gint64)item->key))
8334                                 item->chunk_size += CMP_SIZE;
8335                         else
8336                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8337                         item->chunk_size += BR_LARGE_SIZE;
8338                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8339                 }
8340                 size += item->chunk_size;
8341         }
8342 #if defined(__native_client__) && defined(__native_client_codegen__)
8343         /* In Native Client, we don't re-use thunks, allocate from the */
8344         /* normal code manager paths. */
8345         code = mono_domain_code_reserve (domain, size);
8346 #else
8347         if (fail_tramp)
8348                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8349         else
8350                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8351 #endif
8352         start = code;
8353
8354         unwind_ops = mono_arch_get_cie_program ();
8355
8356         for (i = 0; i < count; ++i) {
8357                 MonoIMTCheckItem *item = imt_entries [i];
8358                 item->code_target = code;
8359                 if (item->is_equals) {
8360                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8361
8362                         if (item->check_target_idx || fail_case) {
8363                                 if (!item->compare_done || fail_case) {
8364                                         if (amd64_use_imm32 ((gint64)item->key))
8365                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8366                                         else {
8367                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8368                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8369                                         }
8370                                 }
8371                                 item->jmp_code = code;
8372                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8373                                 if (item->has_target_code) {
8374                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8375                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8376                                 } else {
8377                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8378                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8379                                 }
8380
8381                                 if (fail_case) {
8382                                         amd64_patch (item->jmp_code, code);
8383                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8384                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8385                                         item->jmp_code = NULL;
8386                                 }
8387                         } else {
8388                                 /* enable the commented code to assert on wrong method */
8389 #if 0
8390                                 if (amd64_is_imm32 (item->key))
8391                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8392                                 else {
8393                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8394                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8395                                 }
8396                                 item->jmp_code = code;
8397                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8398                                 /* See the comment below about R10 */
8399                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8400                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8401                                 amd64_patch (item->jmp_code, code);
8402                                 amd64_breakpoint (code);
8403                                 item->jmp_code = NULL;
8404 #else
8405                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8406                                    needs to be preserved.  R10 needs
8407                                    to be preserved for calls which
8408                                    require a runtime generic context,
8409                                    but interface calls don't. */
8410                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8411                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8412 #endif
8413                         }
8414                 } else {
8415                         if (amd64_use_imm32 ((gint64)item->key))
8416                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8417                         else {
8418                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8419                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8420                         }
8421                         item->jmp_code = code;
8422                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8423                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8424                         else
8425                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8426                 }
8427                 g_assert (code - item->code_target <= item->chunk_size);
8428         }
8429         /* patch the branches to get to the target items */
8430         for (i = 0; i < count; ++i) {
8431                 MonoIMTCheckItem *item = imt_entries [i];
8432                 if (item->jmp_code) {
8433                         if (item->check_target_idx) {
8434                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8435                         }
8436                 }
8437         }
8438
8439         if (!fail_tramp)
8440                 mono_stats.imt_thunks_size += code - start;
8441         g_assert (code - start <= size);
8442
8443         nacl_domain_code_validate(domain, &start, size, &code);
8444         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8445
8446         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8447
8448         return start;
8449 }
8450
8451 MonoMethod*
8452 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8453 {
8454         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8455 }
8456
8457 MonoVTable*
8458 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8459 {
8460         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8461 }
8462
8463 GSList*
8464 mono_arch_get_cie_program (void)
8465 {
8466         GSList *l = NULL;
8467
8468         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8469         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8470
8471         return l;
8472 }
8473
8474 #ifndef DISABLE_JIT
8475
8476 MonoInst*
8477 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8478 {
8479         MonoInst *ins = NULL;
8480         int opcode = 0;
8481
8482         if (cmethod->klass == mono_defaults.math_class) {
8483                 if (strcmp (cmethod->name, "Sin") == 0) {
8484                         opcode = OP_SIN;
8485                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8486                         opcode = OP_COS;
8487                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8488                         opcode = OP_SQRT;
8489                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8490                         opcode = OP_ABS;
8491                 }
8492
8493                 if (opcode && fsig->param_count == 1) {
8494                         MONO_INST_NEW (cfg, ins, opcode);
8495                         ins->type = STACK_R8;
8496                         ins->dreg = mono_alloc_freg (cfg);
8497                         ins->sreg1 = args [0]->dreg;
8498                         MONO_ADD_INS (cfg->cbb, ins);
8499                 }
8500
8501                 opcode = 0;
8502                 if (cfg->opt & MONO_OPT_CMOV) {
8503                         if (strcmp (cmethod->name, "Min") == 0) {
8504                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8505                                         opcode = OP_IMIN;
8506                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8507                                         opcode = OP_IMIN_UN;
8508                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8509                                         opcode = OP_LMIN;
8510                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8511                                         opcode = OP_LMIN_UN;
8512                         } else if (strcmp (cmethod->name, "Max") == 0) {
8513                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8514                                         opcode = OP_IMAX;
8515                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8516                                         opcode = OP_IMAX_UN;
8517                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8518                                         opcode = OP_LMAX;
8519                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8520                                         opcode = OP_LMAX_UN;
8521                         }
8522                 }
8523
8524                 if (opcode && fsig->param_count == 2) {
8525                         MONO_INST_NEW (cfg, ins, opcode);
8526                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8527                         ins->dreg = mono_alloc_ireg (cfg);
8528                         ins->sreg1 = args [0]->dreg;
8529                         ins->sreg2 = args [1]->dreg;
8530                         MONO_ADD_INS (cfg->cbb, ins);
8531                 }
8532
8533 #if 0
8534                 /* OP_FREM is not IEEE compatible */
8535                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8536                         MONO_INST_NEW (cfg, ins, OP_FREM);
8537                         ins->inst_i0 = args [0];
8538                         ins->inst_i1 = args [1];
8539                 }
8540 #endif
8541         }
8542
8543         return ins;
8544 }
8545 #endif
8546
8547 gboolean
8548 mono_arch_print_tree (MonoInst *tree, int arity)
8549 {
8550         return 0;
8551 }
8552
8553 mgreg_t
8554 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8555 {
8556         return ctx->gregs [reg];
8557 }
8558
8559 void
8560 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8561 {
8562         ctx->gregs [reg] = val;
8563 }
8564
8565 gpointer
8566 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8567 {
8568         gpointer *sp, old_value;
8569         char *bp;
8570
8571         /*Load the spvar*/
8572         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8573         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8574
8575         old_value = *sp;
8576         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8577                 return old_value;
8578
8579         *sp = new_value;
8580
8581         return old_value;
8582 }
8583
8584 /*
8585  * mono_arch_emit_load_aotconst:
8586  *
8587  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8588  * TARGET from the mscorlib GOT in full-aot code.
8589  * On AMD64, the result is placed into R11.
8590  */
8591 guint8*
8592 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8593 {
8594         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8595         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8596
8597         return code;
8598 }
8599
8600 /*
8601  * mono_arch_get_trampolines:
8602  *
8603  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8604  * for AOT.
8605  */
8606 GSList *
8607 mono_arch_get_trampolines (gboolean aot)
8608 {
8609         return mono_amd64_get_exception_trampolines (aot);
8610 }
8611
8612 /* Soft Debug support */
8613 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8614
8615 /*
8616  * mono_arch_set_breakpoint:
8617  *
8618  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8619  * The location should contain code emitted by OP_SEQ_POINT.
8620  */
8621 void
8622 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8623 {
8624         guint8 *code = ip;
8625
8626         if (ji->from_aot) {
8627                 guint32 native_offset = ip - (guint8*)ji->code_start;
8628                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8629
8630                 g_assert (info->bp_addrs [native_offset] == 0);
8631                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8632         } else {
8633                 /* ip points to a mov r11, 0 */
8634                 g_assert (code [0] == 0x41);
8635                 g_assert (code [1] == 0xbb);
8636                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8637         }
8638 }
8639
8640 /*
8641  * mono_arch_clear_breakpoint:
8642  *
8643  *   Clear the breakpoint at IP.
8644  */
8645 void
8646 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8647 {
8648         guint8 *code = ip;
8649
8650         if (ji->from_aot) {
8651                 guint32 native_offset = ip - (guint8*)ji->code_start;
8652                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8653
8654                 info->bp_addrs [native_offset] = NULL;
8655         } else {
8656                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8657         }
8658 }
8659
8660 gboolean
8661 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8662 {
8663         /* We use soft breakpoints on amd64 */
8664         return FALSE;
8665 }
8666
8667 /*
8668  * mono_arch_skip_breakpoint:
8669  *
8670  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8671  * we resume, the instruction is not executed again.
8672  */
8673 void
8674 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8675 {
8676         g_assert_not_reached ();
8677 }
8678
8679 /*
8680  * mono_arch_start_single_stepping:
8681  *
8682  *   Start single stepping.
8683  */
8684 void
8685 mono_arch_start_single_stepping (void)
8686 {
8687         ss_trampoline = mini_get_single_step_trampoline ();
8688 }
8689
8690 /*
8691  * mono_arch_stop_single_stepping:
8692  *
8693  *   Stop single stepping.
8694  */
8695 void
8696 mono_arch_stop_single_stepping (void)
8697 {
8698         ss_trampoline = NULL;
8699 }
8700
8701 /*
8702  * mono_arch_is_single_step_event:
8703  *
8704  *   Return whenever the machine state in SIGCTX corresponds to a single
8705  * step event.
8706  */
8707 gboolean
8708 mono_arch_is_single_step_event (void *info, void *sigctx)
8709 {
8710         /* We use soft breakpoints on amd64 */
8711         return FALSE;
8712 }
8713
8714 /*
8715  * mono_arch_skip_single_step:
8716  *
8717  *   Modify CTX so the ip is placed after the single step trigger instruction,
8718  * we resume, the instruction is not executed again.
8719  */
8720 void
8721 mono_arch_skip_single_step (MonoContext *ctx)
8722 {
8723         g_assert_not_reached ();
8724 }
8725
8726 /*
8727  * mono_arch_create_seq_point_info:
8728  *
8729  *   Return a pointer to a data structure which is used by the sequence
8730  * point implementation in AOTed code.
8731  */
8732 gpointer
8733 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8734 {
8735         SeqPointInfo *info;
8736         MonoJitInfo *ji;
8737
8738         // FIXME: Add a free function
8739
8740         mono_domain_lock (domain);
8741         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8742                                                                 code);
8743         mono_domain_unlock (domain);
8744
8745         if (!info) {
8746                 ji = mono_jit_info_table_find (domain, (char*)code);
8747                 g_assert (ji);
8748
8749                 // FIXME: Optimize the size
8750                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8751
8752                 info->ss_tramp_addr = &ss_trampoline;
8753
8754                 mono_domain_lock (domain);
8755                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8756                                                          code, info);
8757                 mono_domain_unlock (domain);
8758         }
8759
8760         return info;
8761 }
8762
8763 void
8764 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8765 {
8766         ext->lmf.previous_lmf = prev_lmf;
8767         /* Mark that this is a MonoLMFExt */
8768         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8769         ext->lmf.rsp = (gssize)ext;
8770 }
8771
8772 #endif
8773
8774 gboolean
8775 mono_arch_opcode_supported (int opcode)
8776 {
8777         switch (opcode) {
8778         case OP_ATOMIC_ADD_I4:
8779         case OP_ATOMIC_ADD_I8:
8780         case OP_ATOMIC_EXCHANGE_I4:
8781         case OP_ATOMIC_EXCHANGE_I8:
8782         case OP_ATOMIC_CAS_I4:
8783         case OP_ATOMIC_CAS_I8:
8784         case OP_ATOMIC_LOAD_I1:
8785         case OP_ATOMIC_LOAD_I2:
8786         case OP_ATOMIC_LOAD_I4:
8787         case OP_ATOMIC_LOAD_I8:
8788         case OP_ATOMIC_LOAD_U1:
8789         case OP_ATOMIC_LOAD_U2:
8790         case OP_ATOMIC_LOAD_U4:
8791         case OP_ATOMIC_LOAD_U8:
8792         case OP_ATOMIC_LOAD_R4:
8793         case OP_ATOMIC_LOAD_R8:
8794         case OP_ATOMIC_STORE_I1:
8795         case OP_ATOMIC_STORE_I2:
8796         case OP_ATOMIC_STORE_I4:
8797         case OP_ATOMIC_STORE_I8:
8798         case OP_ATOMIC_STORE_U1:
8799         case OP_ATOMIC_STORE_U2:
8800         case OP_ATOMIC_STORE_U4:
8801         case OP_ATOMIC_STORE_U8:
8802         case OP_ATOMIC_STORE_R4:
8803         case OP_ATOMIC_STORE_R8:
8804                 return TRUE;
8805         default:
8806                 return FALSE;
8807         }
8808 }
8809
8810 CallInfo*
8811 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8812 {
8813         return get_call_info (mp, sig);
8814 }