mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint appdomain_tls_offset = -1;
  32 static gint thread_tls_offset = -1;
  33
  34 #ifdef MONO_XEN_OPT
  35 /* TRUE by default until we add runtime detection of Xen */
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 const char * const amd64_desc [OP_LAST];
  44 static const char*const * ins_spec = amd64_desc;
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #ifdef PLATFORM_WIN32
  51 /* Under windows, the default pinvoke calling convention is stdcall */
  52 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  53 #else
  54 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  55 #endif
  56
  57 #define ARGS_OFFSET 16
  58 #define GP_SCRATCH_REG AMD64_R11
  59
  60 /*
  61  * AMD64 register usage:
  62  * - callee saved registers are used for global register allocation
  63  * - %r11 is used for materializing 64 bit constants in opcodes
  64  * - the rest is used for local allocation
  65  */
  66
  67 /*
  68  * Floating point comparison results:
  69  *                  ZF PF CF
  70  * A > B            0  0  0
  71  * A < B            0  0  1
  72  * A = B            1  0  0
  73  * A > B            0  0  0
  74  * UNORDERED        1  1  1
  75  */
  76
  77 #define NOT_IMPLEMENTED g_assert_not_reached ()
  78
  79 const char*
  80 mono_arch_regname (int reg) {
  81         switch (reg) {
  82         case AMD64_RAX: return "%rax";
  83         case AMD64_RBX: return "%rbx";
  84         case AMD64_RCX: return "%rcx";
  85         case AMD64_RDX: return "%rdx";
  86         case AMD64_RSP: return "%rsp";
  87         case AMD64_RBP: return "%rbp";
  88         case AMD64_RDI: return "%rdi";
  89         case AMD64_RSI: return "%rsi";
  90         case AMD64_R8: return "%r8";
  91         case AMD64_R9: return "%r9";
  92         case AMD64_R10: return "%r10";
  93         case AMD64_R11: return "%r11";
  94         case AMD64_R12: return "%r12";
  95         case AMD64_R13: return "%r13";
  96         case AMD64_R14: return "%r14";
  97         case AMD64_R15: return "%r15";
  98         }
  99         return "unknown";
 100 }
 101
 102 static const char * xmmregs [] = {
 103         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 104         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 105 };
 106
 107 const char*
 108 mono_arch_fregname (int reg)
 109 {
 110         if (reg < AMD64_XMM_NREG)
 111                 return xmmregs [reg];
 112         else
 113                 return "unknown";
 114 }
 115
 116 G_GNUC_UNUSED static void
 117 break_count (void)
 118 {
 119 }
 120
 121 G_GNUC_UNUSED static gboolean
 122 debug_count (void)
 123 {
 124         static int count = 0;
 125         count ++;
 126
 127         if (!getenv ("COUNT"))
 128                 return TRUE;
 129
 130         if (count == atoi (getenv ("COUNT"))) {
 131                 break_count ();
 132         }
 133
 134         if (count > atoi (getenv ("COUNT"))) {
 135                 return FALSE;
 136         }
 137
 138         return TRUE;
 139 }
 140
 141 static gboolean
 142 debug_omit_fp (void)
 143 {
 144 #if 0
 145         return debug_count ();
 146 #else
 147         return TRUE;
 148 #endif
 149 }
 150
 151 static inline gboolean
 152 amd64_is_near_call (guint8 *code)
 153 {
 154         /* Skip REX */
 155         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 156                 code += 1;
 157
 158         return code [0] == 0xe8;
 159 }
 160
 161 static inline void
 162 amd64_patch (unsigned char* code, gpointer target)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         if ((code [0] & 0xf8) == 0xb8) {
 169                 /* amd64_set_reg_template */
 170                 *(guint64*)(code + 1) = (guint64)target;
 171         }
 172         else if (code [0] == 0x8b) {
 173                 /* mov 0(%rip), %dreg */
 174                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 175         }
 176         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 177                 /* call *<OFFSET>(%rip) */
 178                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 179         }
 180         else if ((code [0] == 0xe8)) {
 181                 /* call <DISP> */
 182                 gint64 disp = (guint8*)target - (guint8*)code;
 183                 g_assert (amd64_is_imm32 (disp));
 184                 x86_patch (code, (unsigned char*)target);
 185         }
 186         else
 187                 x86_patch (code, (unsigned char*)target);
 188 }
 189
 190 typedef enum {
 191         ArgInIReg,
 192         ArgInFloatSSEReg,
 193         ArgInDoubleSSEReg,
 194         ArgOnStack,
 195         ArgValuetypeInReg,
 196         ArgNone /* only in pair_storage */
 197 } ArgStorage;
 198
 199 typedef struct {
 200         gint16 offset;
 201         gint8  reg;
 202         ArgStorage storage;
 203
 204         /* Only if storage == ArgValuetypeInReg */
 205         ArgStorage pair_storage [2];
 206         gint8 pair_regs [2];
 207 } ArgInfo;
 208
 209 typedef struct {
 210         int nargs;
 211         guint32 stack_usage;
 212         guint32 reg_usage;
 213         guint32 freg_usage;
 214         gboolean need_stack_align;
 215         ArgInfo ret;
 216         ArgInfo sig_cookie;
 217         ArgInfo args [1];
 218 } CallInfo;
 219
 220 #define DEBUG(a) if (cfg->verbose_level > 1) a
 221
 222 #define NEW_ICONST(cfg,dest,val) do {   \
 223                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 224                 (dest)->opcode = OP_ICONST;     \
 225                 (dest)->inst_c0 = (val);        \
 226                 (dest)->type = STACK_I4;        \
 227         } while (0)
 228
 229 #define PARAM_REGS 6
 230
 231 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 232
 233 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 234
 235 static void inline
 236 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 237 {
 238     ainfo->offset = *stack_size;
 239
 240     if (*gr >= PARAM_REGS) {
 241                 ainfo->storage = ArgOnStack;
 242                 (*stack_size) += sizeof (gpointer);
 243     }
 244     else {
 245                 ainfo->storage = ArgInIReg;
 246                 ainfo->reg = param_regs [*gr];
 247                 (*gr) ++;
 248     }
 249 }
 250
 251 #define FLOAT_PARAM_REGS 8
 252
 253 static void inline
 254 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 255 {
 256     ainfo->offset = *stack_size;
 257
 258     if (*gr >= FLOAT_PARAM_REGS) {
 259                 ainfo->storage = ArgOnStack;
 260                 (*stack_size) += sizeof (gpointer);
 261     }
 262     else {
 263                 /* A double register */
 264                 if (is_double)
 265                         ainfo->storage = ArgInDoubleSSEReg;
 266                 else
 267                         ainfo->storage = ArgInFloatSSEReg;
 268                 ainfo->reg = *gr;
 269                 (*gr) += 1;
 270     }
 271 }
 272
 273 typedef enum ArgumentClass {
 274         ARG_CLASS_NO_CLASS,
 275         ARG_CLASS_MEMORY,
 276         ARG_CLASS_INTEGER,
 277         ARG_CLASS_SSE
 278 } ArgumentClass;
 279
 280 static ArgumentClass
 281 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 282 {
 283         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 284         MonoType *ptype;
 285
 286         ptype = mono_type_get_underlying_type (type);
 287         switch (ptype->type) {
 288         case MONO_TYPE_BOOLEAN:
 289         case MONO_TYPE_CHAR:
 290         case MONO_TYPE_I1:
 291         case MONO_TYPE_U1:
 292         case MONO_TYPE_I2:
 293         case MONO_TYPE_U2:
 294         case MONO_TYPE_I4:
 295         case MONO_TYPE_U4:
 296         case MONO_TYPE_I:
 297         case MONO_TYPE_U:
 298         case MONO_TYPE_STRING:
 299         case MONO_TYPE_OBJECT:
 300         case MONO_TYPE_CLASS:
 301         case MONO_TYPE_SZARRAY:
 302         case MONO_TYPE_PTR:
 303         case MONO_TYPE_FNPTR:
 304         case MONO_TYPE_ARRAY:
 305         case MONO_TYPE_I8:
 306         case MONO_TYPE_U8:
 307                 class2 = ARG_CLASS_INTEGER;
 308                 break;
 309         case MONO_TYPE_R4:
 310         case MONO_TYPE_R8:
 311                 class2 = ARG_CLASS_SSE;
 312                 break;
 313
 314         case MONO_TYPE_TYPEDBYREF:
 315                 g_assert_not_reached ();
 316
 317         case MONO_TYPE_GENERICINST:
 318                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 319                         class2 = ARG_CLASS_INTEGER;
 320                         break;
 321                 }
 322                 /* fall through */
 323         case MONO_TYPE_VALUETYPE: {
 324                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 325                 int i;
 326
 327                 for (i = 0; i < info->num_fields; ++i) {
 328                         class2 = class1;
 329                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 330                 }
 331                 break;
 332         }
 333         default:
 334                 g_assert_not_reached ();
 335         }
 336
 337         /* Merge */
 338         if (class1 == class2)
 339                 ;
 340         else if (class1 == ARG_CLASS_NO_CLASS)
 341                 class1 = class2;
 342         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 343                 class1 = ARG_CLASS_MEMORY;
 344         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 345                 class1 = ARG_CLASS_INTEGER;
 346         else
 347                 class1 = ARG_CLASS_SSE;
 348
 349         return class1;
 350 }
 351
 352 static void
 353 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 354                gboolean is_return,
 355                guint32 *gr, guint32 *fr, guint32 *stack_size)
 356 {
 357         guint32 size, quad, nquads, i;
 358         ArgumentClass args [2];
 359         MonoMarshalType *info;
 360         MonoClass *klass;
 361
 362         klass = mono_class_from_mono_type (type);
 363         if (sig->pinvoke)
 364                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 365         else
 366                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 367
 368         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 369                 /* Allways pass in memory */
 370                 ainfo->offset = *stack_size;
 371                 *stack_size += ALIGN_TO (size, 8);
 372                 ainfo->storage = ArgOnStack;
 373
 374                 return;
 375         }
 376
 377         /* FIXME: Handle structs smaller than 8 bytes */
 378         //if ((size % 8) != 0)
 379         //      NOT_IMPLEMENTED;
 380
 381         if (size > 8)
 382                 nquads = 2;
 383         else
 384                 nquads = 1;
 385
 386         /*
 387          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 388          * The X87 and SSEUP stuff is left out since there are no such types in
 389          * the CLR.
 390          */
 391         info = mono_marshal_load_type_info (klass);
 392         g_assert (info);
 393         if (info->native_size > 16) {
 394                 ainfo->offset = *stack_size;
 395                 *stack_size += ALIGN_TO (info->native_size, 8);
 396                 ainfo->storage = ArgOnStack;
 397
 398                 return;
 399         }
 400
 401         args [0] = ARG_CLASS_NO_CLASS;
 402         args [1] = ARG_CLASS_NO_CLASS;
 403         for (quad = 0; quad < nquads; ++quad) {
 404                 int size;
 405                 guint32 align;
 406                 ArgumentClass class1;
 407
 408                 class1 = ARG_CLASS_NO_CLASS;
 409                 for (i = 0; i < info->num_fields; ++i) {
 410                         size = mono_marshal_type_size (info->fields [i].field->type,
 411                                                                                    info->fields [i].mspec,
 412                                                                                    &align, TRUE, klass->unicode);
 413                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 414                                 /* Unaligned field */
 415                                 NOT_IMPLEMENTED;
 416                         }
 417
 418                         /* Skip fields in other quad */
 419                         if ((quad == 0) && (info->fields [i].offset >= 8))
 420                                 continue;
 421                         if ((quad == 1) && (info->fields [i].offset < 8))
 422                                 continue;
 423
 424                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 425                 }
 426                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 427                 args [quad] = class1;
 428         }
 429
 430         /* Post merger cleanup */
 431         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 432                 args [0] = args [1] = ARG_CLASS_MEMORY;
 433
 434         /* Allocate registers */
 435         {
 436                 int orig_gr = *gr;
 437                 int orig_fr = *fr;
 438
 439                 ainfo->storage = ArgValuetypeInReg;
 440                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 441                 for (quad = 0; quad < nquads; ++quad) {
 442                         switch (args [quad]) {
 443                         case ARG_CLASS_INTEGER:
 444                                 if (*gr >= PARAM_REGS)
 445                                         args [quad] = ARG_CLASS_MEMORY;
 446                                 else {
 447                                         ainfo->pair_storage [quad] = ArgInIReg;
 448                                         if (is_return)
 449                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 450                                         else
 451                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 452                                         (*gr) ++;
 453                                 }
 454                                 break;
 455                         case ARG_CLASS_SSE:
 456                                 if (*fr >= FLOAT_PARAM_REGS)
 457                                         args [quad] = ARG_CLASS_MEMORY;
 458                                 else {
 459                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 460                                         ainfo->pair_regs [quad] = *fr;
 461                                         (*fr) ++;
 462                                 }
 463                                 break;
 464                         case ARG_CLASS_MEMORY:
 465                                 break;
 466                         default:
 467                                 g_assert_not_reached ();
 468                         }
 469                 }
 470
 471                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 472                         /* Revert possible register assignments */
 473                         *gr = orig_gr;
 474                         *fr = orig_fr;
 475
 476                         ainfo->offset = *stack_size;
 477                         *stack_size += ALIGN_TO (info->native_size, 8);
 478                         ainfo->storage = ArgOnStack;
 479                 }
 480         }
 481 }
 482
 483 /*
 484  * get_call_info:
 485  *
 486  *  Obtain information about a call according to the calling convention.
 487  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 488  * Draft Version 0.23" document for more information.
 489  */
 490 static CallInfo*
 491 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 492 {
 493         guint32 i, gr, fr;
 494         MonoType *ret_type;
 495         int n = sig->hasthis + sig->param_count;
 496         guint32 stack_size = 0;
 497         CallInfo *cinfo;
 498
 499         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 500
 501         gr = 0;
 502         fr = 0;
 503
 504         /* return value */
 505         {
 506                 ret_type = mono_type_get_underlying_type (sig->ret);
 507                 switch (ret_type->type) {
 508                 case MONO_TYPE_BOOLEAN:
 509                 case MONO_TYPE_I1:
 510                 case MONO_TYPE_U1:
 511                 case MONO_TYPE_I2:
 512                 case MONO_TYPE_U2:
 513                 case MONO_TYPE_CHAR:
 514                 case MONO_TYPE_I4:
 515                 case MONO_TYPE_U4:
 516                 case MONO_TYPE_I:
 517                 case MONO_TYPE_U:
 518                 case MONO_TYPE_PTR:
 519                 case MONO_TYPE_FNPTR:
 520                 case MONO_TYPE_CLASS:
 521                 case MONO_TYPE_OBJECT:
 522                 case MONO_TYPE_SZARRAY:
 523                 case MONO_TYPE_ARRAY:
 524                 case MONO_TYPE_STRING:
 525                         cinfo->ret.storage = ArgInIReg;
 526                         cinfo->ret.reg = AMD64_RAX;
 527                         break;
 528                 case MONO_TYPE_U8:
 529                 case MONO_TYPE_I8:
 530                         cinfo->ret.storage = ArgInIReg;
 531                         cinfo->ret.reg = AMD64_RAX;
 532                         break;
 533                 case MONO_TYPE_R4:
 534                         cinfo->ret.storage = ArgInFloatSSEReg;
 535                         cinfo->ret.reg = AMD64_XMM0;
 536                         break;
 537                 case MONO_TYPE_R8:
 538                         cinfo->ret.storage = ArgInDoubleSSEReg;
 539                         cinfo->ret.reg = AMD64_XMM0;
 540                         break;
 541                 case MONO_TYPE_GENERICINST:
 542                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 543                                 cinfo->ret.storage = ArgInIReg;
 544                                 cinfo->ret.reg = AMD64_RAX;
 545                                 break;
 546                         }
 547                         /* fall through */
 548                 case MONO_TYPE_VALUETYPE: {
 549                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 550
 551                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 552                         if (cinfo->ret.storage == ArgOnStack)
 553                                 /* The caller passes the address where the value is stored */
 554                                 add_general (&gr, &stack_size, &cinfo->ret);
 555                         break;
 556                 }
 557                 case MONO_TYPE_TYPEDBYREF:
 558                         /* Same as a valuetype with size 24 */
 559                         add_general (&gr, &stack_size, &cinfo->ret);
 560                         ;
 561                         break;
 562                 case MONO_TYPE_VOID:
 563                         break;
 564                 default:
 565                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 566                 }
 567         }
 568
 569         /* this */
 570         if (sig->hasthis)
 571                 add_general (&gr, &stack_size, cinfo->args + 0);
 572
 573         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 574                 gr = PARAM_REGS;
 575                 fr = FLOAT_PARAM_REGS;
 576
 577                 /* Emit the signature cookie just before the implicit arguments */
 578                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 579         }
 580
 581         for (i = 0; i < sig->param_count; ++i) {
 582                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 583                 MonoType *ptype;
 584
 585                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 586                         /* We allways pass the sig cookie on the stack for simplicity */
 587                         /*
 588                          * Prevent implicit arguments + the sig cookie from being passed
 589                          * in registers.
 590                          */
 591                         gr = PARAM_REGS;
 592                         fr = FLOAT_PARAM_REGS;
 593
 594                         /* Emit the signature cookie just before the implicit arguments */
 595                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 596                 }
 597
 598                 if (sig->params [i]->byref) {
 599                         add_general (&gr, &stack_size, ainfo);
 600                         continue;
 601                 }
 602                 ptype = mono_type_get_underlying_type (sig->params [i]);
 603                 switch (ptype->type) {
 604                 case MONO_TYPE_BOOLEAN:
 605                 case MONO_TYPE_I1:
 606                 case MONO_TYPE_U1:
 607                         add_general (&gr, &stack_size, ainfo);
 608                         break;
 609                 case MONO_TYPE_I2:
 610                 case MONO_TYPE_U2:
 611                 case MONO_TYPE_CHAR:
 612                         add_general (&gr, &stack_size, ainfo);
 613                         break;
 614                 case MONO_TYPE_I4:
 615                 case MONO_TYPE_U4:
 616                         add_general (&gr, &stack_size, ainfo);
 617                         break;
 618                 case MONO_TYPE_I:
 619                 case MONO_TYPE_U:
 620                 case MONO_TYPE_PTR:
 621                 case MONO_TYPE_FNPTR:
 622                 case MONO_TYPE_CLASS:
 623                 case MONO_TYPE_OBJECT:
 624                 case MONO_TYPE_STRING:
 625                 case MONO_TYPE_SZARRAY:
 626                 case MONO_TYPE_ARRAY:
 627                         add_general (&gr, &stack_size, ainfo);
 628                         break;
 629                 case MONO_TYPE_GENERICINST:
 630                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 631                                 add_general (&gr, &stack_size, ainfo);
 632                                 break;
 633                         }
 634                         /* fall through */
 635                 case MONO_TYPE_VALUETYPE:
 636                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 637                         break;
 638                 case MONO_TYPE_TYPEDBYREF:
 639                         stack_size += sizeof (MonoTypedRef);
 640                         ainfo->storage = ArgOnStack;
 641                         break;
 642                 case MONO_TYPE_U8:
 643                 case MONO_TYPE_I8:
 644                         add_general (&gr, &stack_size, ainfo);
 645                         break;
 646                 case MONO_TYPE_R4:
 647                         add_float (&fr, &stack_size, ainfo, FALSE);
 648                         break;
 649                 case MONO_TYPE_R8:
 650                         add_float (&fr, &stack_size, ainfo, TRUE);
 651                         break;
 652                 default:
 653                         g_assert_not_reached ();
 654                 }
 655         }
 656
 657         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 658                 gr = PARAM_REGS;
 659                 fr = FLOAT_PARAM_REGS;
 660
 661                 /* Emit the signature cookie just before the implicit arguments */
 662                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 663         }
 664
 665         if (stack_size & 0x8) {
 666                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 667                 cinfo->need_stack_align = TRUE;
 668                 stack_size += 8;
 669         }
 670
 671         cinfo->stack_usage = stack_size;
 672         cinfo->reg_usage = gr;
 673         cinfo->freg_usage = fr;
 674         return cinfo;
 675 }
 676
 677 /*
 678  * mono_arch_get_argument_info:
 679  * @csig:  a method signature
 680  * @param_count: the number of parameters to consider
 681  * @arg_info: an array to store the result infos
 682  *
 683  * Gathers information on parameters such as size, alignment and
 684  * padding. arg_info should be large enought to hold param_count + 1 entries.
 685  *
 686  * Returns the size of the argument area on the stack.
 687  */
 688 int
 689 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 690 {
 691         int k;
 692         CallInfo *cinfo = get_call_info (csig, FALSE);
 693         guint32 args_size = cinfo->stack_usage;
 694
 695         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 696         if (csig->hasthis) {
 697                 arg_info [0].offset = 0;
 698         }
 699
 700         for (k = 0; k < param_count; k++) {
 701                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 702                 /* FIXME: */
 703                 arg_info [k + 1].size = 0;
 704         }
 705
 706         g_free (cinfo);
 707
 708         return args_size;
 709 }
 710
 711 static int
 712 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 713 {
 714         return 0;
 715 }
 716
 717 /*
 718  * Initialize the cpu to execute managed code.
 719  */
 720 void
 721 mono_arch_cpu_init (void)
 722 {
 723         guint16 fpcw;
 724
 725         /* spec compliance requires running with double precision */
 726         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 727         fpcw &= ~X86_FPCW_PRECC_MASK;
 728         fpcw |= X86_FPCW_PREC_DOUBLE;
 729         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 730         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 731 }
 732
 733 /*
 734  * This function returns the optimizations supported on this cpu.
 735  */
 736 guint32
 737 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 738 {
 739         int eax, ebx, ecx, edx;
 740         guint32 opts = 0;
 741
 742         /* FIXME: AMD64 */
 743
 744         *exclude_mask = 0;
 745         /* Feature Flags function, flags returned in EDX. */
 746         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 747                 if (edx & (1 << 15)) {
 748                         opts |= MONO_OPT_CMOV;
 749                         if (edx & 1)
 750                                 opts |= MONO_OPT_FCMOV;
 751                         else
 752                                 *exclude_mask |= MONO_OPT_FCMOV;
 753                 } else
 754                         *exclude_mask |= MONO_OPT_CMOV;
 755         }
 756         return opts;
 757 }
 758
 759 gboolean
 760 mono_amd64_is_sse2 (void)
 761 {
 762         return use_sse2;
 763 }
 764
 765 static gboolean
 766 is_regsize_var (MonoType *t) {
 767         if (t->byref)
 768                 return TRUE;
 769         t = mono_type_get_underlying_type (t);
 770         switch (t->type) {
 771         case MONO_TYPE_I4:
 772         case MONO_TYPE_U4:
 773         case MONO_TYPE_I:
 774         case MONO_TYPE_U:
 775         case MONO_TYPE_PTR:
 776         case MONO_TYPE_FNPTR:
 777                 return TRUE;
 778         case MONO_TYPE_OBJECT:
 779         case MONO_TYPE_STRING:
 780         case MONO_TYPE_CLASS:
 781         case MONO_TYPE_SZARRAY:
 782         case MONO_TYPE_ARRAY:
 783                 return TRUE;
 784         case MONO_TYPE_GENERICINST:
 785                 if (!mono_type_generic_inst_is_valuetype (t))
 786                         return TRUE;
 787                 return FALSE;
 788         case MONO_TYPE_VALUETYPE:
 789                 return FALSE;
 790         }
 791         return FALSE;
 792 }
 793
 794 GList *
 795 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 796 {
 797         GList *vars = NULL;
 798         int i;
 799
 800         for (i = 0; i < cfg->num_varinfo; i++) {
 801                 MonoInst *ins = cfg->varinfo [i];
 802                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 803
 804                 /* unused vars */
 805                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 806                         continue;
 807
 808                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 809                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 810                         continue;
 811
 812                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 813                  * 8bit quantities in caller saved registers on x86 */
 814                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 815                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 816                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 817                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 818                         g_assert (i == vmv->idx);
 819                         vars = g_list_prepend (vars, vmv);
 820                 }
 821         }
 822
 823         vars = mono_varlist_sort (cfg, vars, 0);
 824
 825         return vars;
 826 }
 827
 828 /**
 829  * mono_arch_compute_omit_fp:
 830  *
 831  *   Determine whenever the frame pointer can be eliminated.
 832  */
 833 static void
 834 mono_arch_compute_omit_fp (MonoCompile *cfg)
 835 {
 836         MonoMethodSignature *sig;
 837         MonoMethodHeader *header;
 838         int i;
 839         CallInfo *cinfo;
 840
 841         if (cfg->arch.omit_fp_computed)
 842                 return;
 843
 844         header = mono_method_get_header (cfg->method);
 845
 846         sig = mono_method_signature (cfg->method);
 847
 848         cinfo = get_call_info (sig, FALSE);
 849
 850         /*
 851          * FIXME: Remove some of the restrictions.
 852          */
 853         cfg->arch.omit_fp = TRUE;
 854         cfg->arch.omit_fp_computed = TRUE;
 855
 856         /* Temporarily disable this when running in the debugger until we have support
 857          * for this in the debugger. */
 858         if (mono_debug_using_mono_debugger ())
 859                 cfg->arch.omit_fp = FALSE;
 860
 861         if (!debug_omit_fp ())
 862                 cfg->arch.omit_fp = FALSE;
 863         /*
 864         if (cfg->method->save_lmf)
 865                 cfg->arch.omit_fp = FALSE;
 866         */
 867         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 868                 cfg->arch.omit_fp = FALSE;
 869         if (header->num_clauses)
 870                 cfg->arch.omit_fp = FALSE;
 871         if (cfg->param_area)
 872                 cfg->arch.omit_fp = FALSE;
 873         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 874                 cfg->arch.omit_fp = FALSE;
 875         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 876                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 877                 cfg->arch.omit_fp = FALSE;
 878         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 879                 ArgInfo *ainfo = &cinfo->args [i];
 880
 881                 if (ainfo->storage == ArgOnStack) {
 882                         /*
 883                          * The stack offset can only be determined when the frame
 884                          * size is known.
 885                          */
 886                         cfg->arch.omit_fp = FALSE;
 887                 }
 888         }
 889
 890         if (cfg->num_varinfo > 10000) {
 891                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 892                 cfg->arch.omit_fp = FALSE;
 893         }
 894
 895         g_free (cinfo);
 896 }
 897
 898 GList *
 899 mono_arch_get_global_int_regs (MonoCompile *cfg)
 900 {
 901         GList *regs = NULL;
 902
 903         mono_arch_compute_omit_fp (cfg);
 904
 905         if (cfg->arch.omit_fp)
 906                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 907
 908         /* We use the callee saved registers for global allocation */
 909         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 910         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 911         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 912         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 913         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 914
 915         return regs;
 916 }
 917
 918 /*
 919  * mono_arch_regalloc_cost:
 920  *
 921  *  Return the cost, in number of memory references, of the action of
 922  * allocating the variable VMV into a register during global register
 923  * allocation.
 924  */
 925 guint32
 926 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 927 {
 928         MonoInst *ins = cfg->varinfo [vmv->idx];
 929
 930         if (cfg->method->save_lmf)
 931                 /* The register is already saved */
 932                 /* substract 1 for the invisible store in the prolog */
 933                 return (ins->opcode == OP_ARG) ? 0 : 1;
 934         else
 935                 /* push+pop */
 936                 return (ins->opcode == OP_ARG) ? 1 : 2;
 937 }
 938
 939 void
 940 mono_arch_allocate_vars (MonoCompile *cfg)
 941 {
 942         MonoMethodSignature *sig;
 943         MonoMethodHeader *header;
 944         MonoInst *inst;
 945         int i, offset;
 946         guint32 locals_stack_size, locals_stack_align;
 947         gint32 *offsets;
 948         CallInfo *cinfo;
 949
 950         header = mono_method_get_header (cfg->method);
 951
 952         sig = mono_method_signature (cfg->method);
 953
 954         cinfo = get_call_info (sig, FALSE);
 955
 956         mono_arch_compute_omit_fp (cfg);
 957
 958         /*
 959          * We use the ABI calling conventions for managed code as well.
 960          * Exception: valuetypes are never passed or returned in registers.
 961          */
 962
 963         if (cfg->arch.omit_fp) {
 964                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 965                 cfg->frame_reg = AMD64_RSP;
 966                 offset = 0;
 967         } else {
 968                 /* Locals are allocated backwards from %fp */
 969                 cfg->frame_reg = AMD64_RBP;
 970                 offset = 0;
 971         }
 972
 973         cfg->arch.reg_save_area_offset = offset;
 974
 975         /* Reserve space for caller saved registers */
 976         for (i = 0; i < AMD64_NREG; ++i)
 977                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 978                         offset += sizeof (gpointer);
 979                 }
 980
 981         if (cfg->method->save_lmf) {
 982                 /* Reserve stack space for saving LMF + argument regs */
 983                 guint32 size = sizeof (MonoLMF);
 984
 985                 if (lmf_tls_offset == -1)
 986                         /* Need to save argument regs too */
 987                         size += (AMD64_NREG * 8) + (8 * 8);
 988
 989                 if (cfg->arch.omit_fp) {
 990                         cfg->arch.lmf_offset = offset;
 991                         offset += size;
 992                 }
 993                 else {
 994                         offset += size;
 995                         cfg->arch.lmf_offset = -offset;
 996                 }
 997         }
 998
 999         if (sig->ret->type != MONO_TYPE_VOID) {
1000                 switch (cinfo->ret.storage) {
1001                 case ArgInIReg:
1002                 case ArgInFloatSSEReg:
1003                 case ArgInDoubleSSEReg:
1004                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1005                                 /* The register is volatile */
1006                                 cfg->ret->opcode = OP_REGOFFSET;
1007                                 cfg->ret->inst_basereg = cfg->frame_reg;
1008                                 if (cfg->arch.omit_fp) {
1009                                         cfg->ret->inst_offset = offset;
1010                                         offset += 8;
1011                                 } else {
1012                                         offset += 8;
1013                                         cfg->ret->inst_offset = -offset;
1014                                 }
1015                         }
1016                         else {
1017                                 cfg->ret->opcode = OP_REGVAR;
1018                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1019                         }
1020                         break;
1021                 case ArgValuetypeInReg:
1022                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1023                         g_assert (!cfg->arch.omit_fp);
1024                         offset += 16;
1025                         cfg->ret->opcode = OP_REGOFFSET;
1026                         cfg->ret->inst_basereg = cfg->frame_reg;
1027                         cfg->ret->inst_offset = - offset;
1028                         break;
1029                 default:
1030                         g_assert_not_reached ();
1031                 }
1032                 cfg->ret->dreg = cfg->ret->inst_c0;
1033         }
1034
1035         /* Allocate locals */
1036         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1037         if (locals_stack_align) {
1038                 offset += (locals_stack_align - 1);
1039                 offset &= ~(locals_stack_align - 1);
1040         }
1041         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1042                 if (offsets [i] != -1) {
1043                         MonoInst *inst = cfg->varinfo [i];
1044                         inst->opcode = OP_REGOFFSET;
1045                         inst->inst_basereg = cfg->frame_reg;
1046                         if (cfg->arch.omit_fp)
1047                                 inst->inst_offset = (offset + offsets [i]);
1048                         else
1049                                 inst->inst_offset = - (offset + offsets [i]);
1050                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1051                 }
1052         }
1053         g_free (offsets);
1054         offset += locals_stack_size;
1055
1056         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1057                 g_assert (!cfg->arch.omit_fp);
1058                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1059                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1060         }
1061
1062         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1063                 inst = cfg->varinfo [i];
1064                 if (inst->opcode != OP_REGVAR) {
1065                         ArgInfo *ainfo = &cinfo->args [i];
1066                         gboolean inreg = TRUE;
1067                         MonoType *arg_type;
1068
1069                         if (sig->hasthis && (i == 0))
1070                                 arg_type = &mono_defaults.object_class->byval_arg;
1071                         else
1072                                 arg_type = sig->params [i - sig->hasthis];
1073
1074                         /* FIXME: Allocate volatile arguments to registers */
1075                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1076                                 inreg = FALSE;
1077
1078                         /*
1079                          * Under AMD64, all registers used to pass arguments to functions
1080                          * are volatile across calls.
1081                          * FIXME: Optimize this.
1082                          */
1083                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1084                                 inreg = FALSE;
1085
1086                         inst->opcode = OP_REGOFFSET;
1087
1088                         switch (ainfo->storage) {
1089                         case ArgInIReg:
1090                         case ArgInFloatSSEReg:
1091                         case ArgInDoubleSSEReg:
1092                                 inst->opcode = OP_REGVAR;
1093                                 inst->dreg = ainfo->reg;
1094                                 break;
1095                         case ArgOnStack:
1096                                 g_assert (!cfg->arch.omit_fp);
1097                                 inst->opcode = OP_REGOFFSET;
1098                                 inst->inst_basereg = cfg->frame_reg;
1099                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1100                                 break;
1101                         case ArgValuetypeInReg:
1102                                 break;
1103                         default:
1104                                 NOT_IMPLEMENTED;
1105                         }
1106
1107                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1108                                 inst->opcode = OP_REGOFFSET;
1109                                 inst->inst_basereg = cfg->frame_reg;
1110                                 /* These arguments are saved to the stack in the prolog */
1111                                 if (cfg->arch.omit_fp) {
1112                                         inst->inst_offset = offset;
1113                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1114                                 } else {
1115                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1116                                         inst->inst_offset = - offset;
1117                                 }
1118                         }
1119                 }
1120         }
1121
1122         cfg->stack_offset = offset;
1123
1124         g_free (cinfo);
1125 }
1126
1127 void
1128 mono_arch_create_vars (MonoCompile *cfg)
1129 {
1130         MonoMethodSignature *sig;
1131         CallInfo *cinfo;
1132
1133         sig = mono_method_signature (cfg->method);
1134
1135         cinfo = get_call_info (sig, FALSE);
1136
1137         if (cinfo->ret.storage == ArgValuetypeInReg)
1138                 cfg->ret_var_is_local = TRUE;
1139
1140         g_free (cinfo);
1141 }
1142
1143 static void
1144 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1145 {
1146         switch (storage) {
1147         case ArgInIReg:
1148                 arg->opcode = OP_OUTARG_REG;
1149                 arg->inst_left = tree;
1150                 arg->inst_call = call;
1151                 arg->backend.reg3 = reg;
1152                 break;
1153         case ArgInFloatSSEReg:
1154                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1155                 arg->inst_left = tree;
1156                 arg->inst_call = call;
1157                 arg->backend.reg3 = reg;
1158                 break;
1159         case ArgInDoubleSSEReg:
1160                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1161                 arg->inst_left = tree;
1162                 arg->inst_call = call;
1163                 arg->backend.reg3 = reg;
1164                 break;
1165         default:
1166                 g_assert_not_reached ();
1167         }
1168 }
1169
1170 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1171  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1172  */
1173
1174 static int
1175 arg_storage_to_ldind (ArgStorage storage)
1176 {
1177         switch (storage) {
1178         case ArgInIReg:
1179                 return CEE_LDIND_I;
1180         case ArgInDoubleSSEReg:
1181                 return CEE_LDIND_R8;
1182         case ArgInFloatSSEReg:
1183                 return CEE_LDIND_R4;
1184         default:
1185                 g_assert_not_reached ();
1186         }
1187
1188         return -1;
1189 }
1190
1191 static void
1192 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1193 {
1194         MonoInst *arg;
1195         MonoMethodSignature *tmp_sig;
1196         MonoInst *sig_arg;
1197
1198         /* FIXME: Add support for signature tokens to AOT */
1199         cfg->disable_aot = TRUE;
1200
1201         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1202
1203         /*
1204          * mono_ArgIterator_Setup assumes the signature cookie is
1205          * passed first and all the arguments which were before it are
1206          * passed on the stack after the signature. So compensate by
1207          * passing a different signature.
1208          */
1209         tmp_sig = mono_metadata_signature_dup (call->signature);
1210         tmp_sig->param_count -= call->signature->sentinelpos;
1211         tmp_sig->sentinelpos = 0;
1212         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1213
1214         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1215         sig_arg->inst_p0 = tmp_sig;
1216
1217         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1218         arg->inst_left = sig_arg;
1219         arg->type = STACK_PTR;
1220
1221         /* prepend, so they get reversed */
1222         arg->next = call->out_args;
1223         call->out_args = arg;
1224 }
1225
1226 /*
1227  * take the arguments and generate the arch-specific
1228  * instructions to properly call the function in call.
1229  * This includes pushing, moving arguments to the right register
1230  * etc.
1231  * Issue: who does the spilling if needed, and when?
1232  */
1233 MonoCallInst*
1234 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1235         MonoInst *arg, *in;
1236         MonoMethodSignature *sig;
1237         int i, n, stack_size;
1238         CallInfo *cinfo;
1239         ArgInfo *ainfo;
1240
1241         stack_size = 0;
1242
1243         sig = call->signature;
1244         n = sig->param_count + sig->hasthis;
1245
1246         cinfo = get_call_info (sig, sig->pinvoke);
1247
1248         for (i = 0; i < n; ++i) {
1249                 ainfo = cinfo->args + i;
1250
1251                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1252                         /* Emit the signature cookie just before the implicit arguments */
1253                         emit_sig_cookie (cfg, call, cinfo);
1254                 }
1255
1256                 if (is_virtual && i == 0) {
1257                         /* the argument will be attached to the call instruction */
1258                         in = call->args [i];
1259                 } else {
1260                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1261                         in = call->args [i];
1262                         arg->cil_code = in->cil_code;
1263                         arg->inst_left = in;
1264                         arg->type = in->type;
1265                         /* prepend, so they get reversed */
1266                         arg->next = call->out_args;
1267                         call->out_args = arg;
1268
1269                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1270                                 guint32 align;
1271                                 guint32 size;
1272
1273                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1274                                         size = sizeof (MonoTypedRef);
1275                                         align = sizeof (gpointer);
1276                                 }
1277                                 else
1278                                 if (sig->pinvoke)
1279                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1280                                 else {
1281                                         /*
1282                                          * Other backends use mono_type_stack_size (), but that
1283                                          * aligns the size to 8, which is larger than the size of
1284                                          * the source, leading to reads of invalid memory if the
1285                                          * source is at the end of address space.
1286                                          */
1287                                         size = mono_class_value_size (in->klass, &align);
1288                                 }
1289                                 if (ainfo->storage == ArgValuetypeInReg) {
1290                                         if (ainfo->pair_storage [1] == ArgNone) {
1291                                                 MonoInst *load;
1292
1293                                                 /* Simpler case */
1294
1295                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1296                                                 load->inst_left = in;
1297
1298                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1299                                         }
1300                                         else {
1301                                                 /* Trees can't be shared so make a copy */
1302                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1303                                                 MonoInst *load, *load2, *offset_ins;
1304
1305                                                 /* Reg1 */
1306                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1307                                                 load->ssa_op = MONO_SSA_LOAD;
1308                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1309
1310                                                 NEW_ICONST (cfg, offset_ins, 0);
1311                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1312                                                 load2->inst_left = load;
1313                                                 load2->inst_right = offset_ins;
1314
1315                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1316                                                 load->inst_left = load2;
1317
1318                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1319
1320                                                 /* Reg2 */
1321                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1322                                                 load->ssa_op = MONO_SSA_LOAD;
1323                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1324
1325                                                 NEW_ICONST (cfg, offset_ins, 8);
1326                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1327                                                 load2->inst_left = load;
1328                                                 load2->inst_right = offset_ins;
1329
1330                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1331                                                 load->inst_left = load2;
1332
1333                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1334                                                 arg->cil_code = in->cil_code;
1335                                                 arg->type = in->type;
1336                                                 /* prepend, so they get reversed */
1337                                                 arg->next = call->out_args;
1338                                                 call->out_args = arg;
1339
1340                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1341
1342                                                 /* Prepend a copy inst */
1343                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1344                                                 arg->cil_code = in->cil_code;
1345                                                 arg->ssa_op = MONO_SSA_STORE;
1346                                                 arg->inst_left = vtaddr;
1347                                                 arg->inst_right = in;
1348                                                 arg->type = in->type;
1349
1350                                                 /* prepend, so they get reversed */
1351                                                 arg->next = call->out_args;
1352                                                 call->out_args = arg;
1353                                         }
1354                                 }
1355                                 else {
1356                                         arg->opcode = OP_OUTARG_VT;
1357                                         arg->klass = in->klass;
1358                                         arg->backend.is_pinvoke = sig->pinvoke;
1359                                         arg->inst_imm = size;
1360                                 }
1361                         }
1362                         else {
1363                                 switch (ainfo->storage) {
1364                                 case ArgInIReg:
1365                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1366                                         break;
1367                                 case ArgInFloatSSEReg:
1368                                 case ArgInDoubleSSEReg:
1369                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1370                                         break;
1371                                 case ArgOnStack:
1372                                         arg->opcode = OP_OUTARG;
1373                                         if (!sig->params [i - sig->hasthis]->byref) {
1374                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1375                                                         arg->opcode = OP_OUTARG_R4;
1376                                                 else
1377                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1378                                                                 arg->opcode = OP_OUTARG_R8;
1379                                         }
1380                                         break;
1381                                 default:
1382                                         g_assert_not_reached ();
1383                                 }
1384                         }
1385                 }
1386         }
1387
1388         /* Handle the case where there are no implicit arguments */
1389         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1390                 emit_sig_cookie (cfg, call, cinfo);
1391         }
1392
1393         if (cinfo->need_stack_align) {
1394                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1395                 /* prepend, so they get reversed */
1396                 arg->next = call->out_args;
1397                 call->out_args = arg;
1398         }
1399
1400         call->stack_usage = cinfo->stack_usage;
1401         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1402         cfg->flags |= MONO_CFG_HAS_CALLS;
1403
1404         g_free (cinfo);
1405
1406         return call;
1407 }
1408
1409 #define EMIT_COND_BRANCH(ins,cond,sign) \
1410 if (ins->flags & MONO_INST_BRLABEL) { \
1411         if (ins->inst_i0->inst_c0) { \
1412                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1413         } else { \
1414                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1415                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1416                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1417                         x86_branch8 (code, cond, 0, sign); \
1418                 else \
1419                         x86_branch32 (code, cond, 0, sign); \
1420         } \
1421 } else { \
1422         if (ins->inst_true_bb->native_offset) { \
1423                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1424         } else { \
1425                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1426                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1427                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1428                         x86_branch8 (code, cond, 0, sign); \
1429                 else \
1430                         x86_branch32 (code, cond, 0, sign); \
1431         } \
1432 }
1433
1434 /* emit an exception if condition is fail */
1435 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1436         do {                                                        \
1437                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1438                 if (tins == NULL) {                                                                             \
1439                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1440                                         MONO_PATCH_INFO_EXC, exc_name);  \
1441                         x86_branch32 (code, cond, 0, signed);               \
1442                 } else {        \
1443                         EMIT_COND_BRANCH (tins, cond, signed);  \
1444                 }                       \
1445         } while (0);
1446
1447 #define EMIT_FPCOMPARE(code) do { \
1448         amd64_fcompp (code); \
1449         amd64_fnstsw (code); \
1450 } while (0);
1451
1452 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1453     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1454         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1455         amd64_ ##op (code); \
1456         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1457         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1458 } while (0);
1459
1460 static guint8*
1461 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1462 {
1463         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1464
1465         /*
1466          * FIXME: Add support for thunks
1467          */
1468         {
1469                 gboolean near_call = FALSE;
1470
1471                 /*
1472                  * Indirect calls are expensive so try to make a near call if possible.
1473                  * The caller memory is allocated by the code manager so it is
1474                  * guaranteed to be at a 32 bit offset.
1475                  */
1476
1477                 if (patch_type != MONO_PATCH_INFO_ABS) {
1478                         /* The target is in memory allocated using the code manager */
1479                         near_call = TRUE;
1480
1481                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1482                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1483                                         /* The callee might be an AOT method */
1484                                         near_call = FALSE;
1485                         }
1486
1487                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1488                                 /*
1489                                  * The call might go directly to a native function without
1490                                  * the wrapper.
1491                                  */
1492                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1493                                 if (mi) {
1494                                         gconstpointer target = mono_icall_get_wrapper (mi);
1495                                         if ((((guint64)target) >> 32) != 0)
1496                                                 near_call = FALSE;
1497                                 }
1498                         }
1499                 }
1500                 else {
1501                         if (mono_find_class_init_trampoline_by_addr (data))
1502                                 near_call = TRUE;
1503                         else {
1504                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1505                                 if (info) {
1506                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1507                                                 strstr (cfg->method->name, info->name)) {
1508                                                 /* A call to the wrapped function */
1509                                                 if ((((guint64)data) >> 32) == 0)
1510                                                         near_call = TRUE;
1511                                         }
1512                                         else if (info->func == info->wrapper) {
1513                                                 /* No wrapper */
1514                                                 if ((((guint64)info->func) >> 32) == 0)
1515                                                         near_call = TRUE;
1516                                         }
1517                                         else {
1518                                                 /* See the comment in mono_codegen () */
1519                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1520                                                         near_call = TRUE;
1521                                         }
1522                                 }
1523                                 else if ((((guint64)data) >> 32) == 0)
1524                                         near_call = TRUE;
1525                         }
1526                 }
1527
1528                 if (cfg->method->dynamic)
1529                         /* These methods are allocated using malloc */
1530                         near_call = FALSE;
1531
1532                 if (cfg->compile_aot)
1533                         near_call = TRUE;
1534
1535 #ifdef MONO_ARCH_NOMAP32BIT
1536                 near_call = FALSE;
1537 #endif
1538
1539                 if (near_call) {
1540                         amd64_call_code (code, 0);
1541                 }
1542                 else {
1543                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1544                         amd64_call_reg (code, GP_SCRATCH_REG);
1545                 }
1546         }
1547
1548         return code;
1549 }
1550
1551 static inline guint8*
1552 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1553 {
1554         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1555
1556         return emit_call_body (cfg, code, patch_type, data);
1557 }
1558
1559 /* FIXME: Add more instructions */
1560 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1561
1562 static void
1563 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1564 {
1565         MonoInst *ins, *last_ins = NULL;
1566         ins = bb->code;
1567
1568         while (ins) {
1569
1570                 switch (ins->opcode) {
1571                 case OP_ICONST:
1572                 case OP_I8CONST:
1573                         /* reg = 0 -> XOR (reg, reg) */
1574                         /* XOR sets cflags on x86, so we cant do it always */
1575                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1576                                 ins->opcode = CEE_XOR;
1577                                 ins->sreg1 = ins->dreg;
1578                                 ins->sreg2 = ins->dreg;
1579                         }
1580                         break;
1581                 case OP_MUL_IMM:
1582                         /* remove unnecessary multiplication with 1 */
1583                         if (ins->inst_imm == 1) {
1584                                 if (ins->dreg != ins->sreg1) {
1585                                         ins->opcode = OP_MOVE;
1586                                 } else {
1587                                         last_ins->next = ins->next;
1588                                         ins = ins->next;
1589                                         continue;
1590                                 }
1591                         }
1592                         break;
1593                 case OP_COMPARE_IMM:
1594                         /* OP_COMPARE_IMM (reg, 0)
1595                          * -->
1596                          * OP_AMD64_TEST_NULL (reg)
1597                          */
1598                         if (!ins->inst_imm)
1599                                 ins->opcode = OP_AMD64_TEST_NULL;
1600                         break;
1601                 case OP_ICOMPARE_IMM:
1602                         if (!ins->inst_imm)
1603                                 ins->opcode = OP_X86_TEST_NULL;
1604                         break;
1605                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1606                         /*
1607                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1608                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1609                          * -->
1610                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1611                          * OP_COMPARE_IMM reg, imm
1612                          *
1613                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1614                          */
1615                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1616                             ins->inst_basereg == last_ins->inst_destbasereg &&
1617                             ins->inst_offset == last_ins->inst_offset) {
1618                                         ins->opcode = OP_ICOMPARE_IMM;
1619                                         ins->sreg1 = last_ins->sreg1;
1620
1621                                         /* check if we can remove cmp reg,0 with test null */
1622                                         if (!ins->inst_imm)
1623                                                 ins->opcode = OP_X86_TEST_NULL;
1624                                 }
1625
1626                         break;
1627                 case OP_LOAD_MEMBASE:
1628                 case OP_LOADI4_MEMBASE:
1629                         /*
1630                          * Note: if reg1 = reg2 the load op is removed
1631                          *
1632                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1633                          * OP_LOAD_MEMBASE offset(basereg), reg2
1634                          * -->
1635                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1636                          * OP_MOVE reg1, reg2
1637                          */
1638                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1639                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1640                             ins->inst_basereg == last_ins->inst_destbasereg &&
1641                             ins->inst_offset == last_ins->inst_offset) {
1642                                 if (ins->dreg == last_ins->sreg1) {
1643                                         last_ins->next = ins->next;
1644                                         ins = ins->next;
1645                                         continue;
1646                                 } else {
1647                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1648                                         ins->opcode = OP_MOVE;
1649                                         ins->sreg1 = last_ins->sreg1;
1650                                 }
1651
1652                         /*
1653                          * Note: reg1 must be different from the basereg in the second load
1654                          * Note: if reg1 = reg2 is equal then second load is removed
1655                          *
1656                          * OP_LOAD_MEMBASE offset(basereg), reg1
1657                          * OP_LOAD_MEMBASE offset(basereg), reg2
1658                          * -->
1659                          * OP_LOAD_MEMBASE offset(basereg), reg1
1660                          * OP_MOVE reg1, reg2
1661                          */
1662                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1663                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1664                               ins->inst_basereg != last_ins->dreg &&
1665                               ins->inst_basereg == last_ins->inst_basereg &&
1666                               ins->inst_offset == last_ins->inst_offset) {
1667
1668                                 if (ins->dreg == last_ins->dreg) {
1669                                         last_ins->next = ins->next;
1670                                         ins = ins->next;
1671                                         continue;
1672                                 } else {
1673                                         ins->opcode = OP_MOVE;
1674                                         ins->sreg1 = last_ins->dreg;
1675                                 }
1676
1677                                 //g_assert_not_reached ();
1678
1679 #if 0
1680                         /*
1681                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1682                          * OP_LOAD_MEMBASE offset(basereg), reg
1683                          * -->
1684                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1685                          * OP_ICONST reg, imm
1686                          */
1687                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1688                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1689                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1690                                    ins->inst_offset == last_ins->inst_offset) {
1691                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1692                                 ins->opcode = OP_ICONST;
1693                                 ins->inst_c0 = last_ins->inst_imm;
1694                                 g_assert_not_reached (); // check this rule
1695 #endif
1696                         }
1697                         break;
1698                 case OP_LOADU1_MEMBASE:
1699                 case OP_LOADI1_MEMBASE:
1700                         /*
1701                          * Note: if reg1 = reg2 the load op is removed
1702                          *
1703                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1704                          * OP_LOAD_MEMBASE offset(basereg), reg2
1705                          * -->
1706                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1707                          * OP_MOVE reg1, reg2
1708                          */
1709                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1710                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1711                                         ins->inst_offset == last_ins->inst_offset) {
1712                                 if (ins->dreg == last_ins->sreg1) {
1713                                         last_ins->next = ins->next;
1714                                         ins = ins->next;
1715                                         continue;
1716                                 } else {
1717                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1718                                         ins->opcode = OP_MOVE;
1719                                         ins->sreg1 = last_ins->sreg1;
1720                                 }
1721                         }
1722                         break;
1723                 case OP_LOADU2_MEMBASE:
1724                 case OP_LOADI2_MEMBASE:
1725                         /*
1726                          * Note: if reg1 = reg2 the load op is removed
1727                          *
1728                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1729                          * OP_LOAD_MEMBASE offset(basereg), reg2
1730                          * -->
1731                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1732                          * OP_MOVE reg1, reg2
1733                          */
1734                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1735                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1736                                         ins->inst_offset == last_ins->inst_offset) {
1737                                 if (ins->dreg == last_ins->sreg1) {
1738                                         last_ins->next = ins->next;
1739                                         ins = ins->next;
1740                                         continue;
1741                                 } else {
1742                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1743                                         ins->opcode = OP_MOVE;
1744                                         ins->sreg1 = last_ins->sreg1;
1745                                 }
1746                         }
1747                         break;
1748                 case CEE_CONV_I4:
1749                 case CEE_CONV_U4:
1750                 case OP_MOVE:
1751                         /*
1752                          * Removes:
1753                          *
1754                          * OP_MOVE reg, reg
1755                          */
1756                         if (ins->dreg == ins->sreg1) {
1757                                 if (last_ins)
1758                                         last_ins->next = ins->next;
1759                                 ins = ins->next;
1760                                 continue;
1761                         }
1762                         /*
1763                          * Removes:
1764                          *
1765                          * OP_MOVE sreg, dreg
1766                          * OP_MOVE dreg, sreg
1767                          */
1768                         if (last_ins && last_ins->opcode == OP_MOVE &&
1769                             ins->sreg1 == last_ins->dreg &&
1770                             ins->dreg == last_ins->sreg1) {
1771                                 last_ins->next = ins->next;
1772                                 ins = ins->next;
1773                                 continue;
1774                         }
1775                         break;
1776                 }
1777                 last_ins = ins;
1778                 ins = ins->next;
1779         }
1780         bb->last_ins = last_ins;
1781 }
1782
1783 static void
1784 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1785 {
1786         if (ins == NULL) {
1787                 ins = bb->code;
1788                 bb->code = to_insert;
1789                 to_insert->next = ins;
1790         }
1791         else {
1792                 to_insert->next = ins->next;
1793                 ins->next = to_insert;
1794         }
1795 }
1796
1797 #define NEW_INS(cfg,dest,op) do {       \
1798                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1799                 (dest)->opcode = (op);  \
1800         insert_after_ins (bb, last_ins, (dest)); \
1801         } while (0)
1802
1803 /*
1804  * mono_arch_lowering_pass:
1805  *
1806  *  Converts complex opcodes into simpler ones so that each IR instruction
1807  * corresponds to one machine instruction.
1808  */
1809 static void
1810 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1811 {
1812         MonoInst *ins, *temp, *last_ins = NULL;
1813         ins = bb->code;
1814
1815         if (bb->max_ireg > cfg->rs->next_vireg)
1816                 cfg->rs->next_vireg = bb->max_ireg;
1817         if (bb->max_freg > cfg->rs->next_vfreg)
1818                 cfg->rs->next_vfreg = bb->max_freg;
1819
1820         /*
1821          * FIXME: Need to add more instructions, but the current machine
1822          * description can't model some parts of the composite instructions like
1823          * cdq.
1824          */
1825         while (ins) {
1826                 switch (ins->opcode) {
1827                 case OP_DIV_IMM:
1828                 case OP_REM_IMM:
1829                 case OP_IDIV_IMM:
1830                 case OP_IREM_IMM:
1831                         NEW_INS (cfg, temp, OP_ICONST);
1832                         temp->inst_c0 = ins->inst_imm;
1833                         temp->dreg = mono_regstate_next_int (cfg->rs);
1834                         switch (ins->opcode) {
1835                         case OP_DIV_IMM:
1836                                 ins->opcode = OP_LDIV;
1837                                 break;
1838                         case OP_REM_IMM:
1839                                 ins->opcode = OP_LREM;
1840                                 break;
1841                         case OP_IDIV_IMM:
1842                                 ins->opcode = OP_IDIV;
1843                                 break;
1844                         case OP_IREM_IMM:
1845                                 ins->opcode = OP_IREM;
1846                                 break;
1847                         }
1848                         ins->sreg2 = temp->dreg;
1849                         break;
1850                 case OP_COMPARE_IMM:
1851                         if (!amd64_is_imm32 (ins->inst_imm)) {
1852                                 NEW_INS (cfg, temp, OP_I8CONST);
1853                                 temp->inst_c0 = ins->inst_imm;
1854                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1855                                 ins->opcode = OP_COMPARE;
1856                                 ins->sreg2 = temp->dreg;
1857                         }
1858                         break;
1859                 case OP_LOAD_MEMBASE:
1860                 case OP_LOADI8_MEMBASE:
1861                         if (!amd64_is_imm32 (ins->inst_offset)) {
1862                                 NEW_INS (cfg, temp, OP_I8CONST);
1863                                 temp->inst_c0 = ins->inst_offset;
1864                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1865                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1866                                 ins->inst_indexreg = temp->dreg;
1867                         }
1868                         break;
1869                 case OP_STORE_MEMBASE_IMM:
1870                 case OP_STOREI8_MEMBASE_IMM:
1871                         if (!amd64_is_imm32 (ins->inst_imm)) {
1872                                 NEW_INS (cfg, temp, OP_I8CONST);
1873                                 temp->inst_c0 = ins->inst_imm;
1874                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1875                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1876                                 ins->sreg1 = temp->dreg;
1877                         }
1878                         break;
1879                 default:
1880                         break;
1881                 }
1882                 last_ins = ins;
1883                 ins = ins->next;
1884         }
1885         bb->last_ins = last_ins;
1886
1887         bb->max_ireg = cfg->rs->next_vireg;
1888         bb->max_freg = cfg->rs->next_vfreg;
1889 }
1890
1891 static const int
1892 branch_cc_table [] = {
1893         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1894         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1895         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1896 };
1897
1898 static int
1899 opcode_to_x86_cond (int opcode)
1900 {
1901         switch (opcode) {
1902         case OP_IBEQ:
1903                 return X86_CC_EQ;
1904         case OP_IBNE_UN:
1905                 return X86_CC_NE;
1906         case OP_IBLT:
1907                 return X86_CC_LT;
1908         case OP_IBLT_UN:
1909                 return X86_CC_LT;
1910         case OP_IBGT:
1911                 return X86_CC_GT;
1912         case OP_IBGT_UN:
1913                 return X86_CC_GT;
1914         case OP_IBGE:
1915                 return X86_CC_GE;
1916         case OP_IBGE_UN:
1917                 return X86_CC_GE;
1918         case OP_IBLE:
1919                 return X86_CC_LE;
1920         case OP_IBLE_UN:
1921                 return X86_CC_LE;
1922         case OP_COND_EXC_IOV:
1923                 return X86_CC_O;
1924         case OP_COND_EXC_IC:
1925                 return X86_CC_C;
1926         default:
1927                 g_assert_not_reached ();
1928         }
1929
1930         return -1;
1931 }
1932
1933 /*#include "cprop.c"*/
1934
1935 /*
1936  * Local register allocation.
1937  * We first scan the list of instructions and we save the liveness info of
1938  * each register (when the register is first used, when it's value is set etc.).
1939  * We also reverse the list of instructions (in the InstList list) because assigning
1940  * registers backwards allows for more tricks to be used.
1941  */
1942 void
1943 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1944 {
1945         if (!bb->code)
1946                 return;
1947
1948         mono_arch_lowering_pass (cfg, bb);
1949
1950         mono_local_regalloc (cfg, bb);
1951 }
1952
1953 static unsigned char*
1954 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1955 {
1956         if (use_sse2) {
1957                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1958         }
1959         else {
1960                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1961                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1962                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1963                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1964                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1965                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1966                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1967                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1968                 amd64_pop_reg (code, dreg);
1969                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1970                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1971         }
1972
1973         if (size == 1)
1974                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1975         else if (size == 2)
1976                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1977         return code;
1978 }
1979
1980 static unsigned char*
1981 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1982 {
1983         int sreg = tree->sreg1;
1984         int need_touch = FALSE;
1985
1986 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1987         if (!tree->flags & MONO_INST_INIT)
1988                 need_touch = TRUE;
1989 #endif
1990
1991         if (need_touch) {
1992                 guint8* br[5];
1993
1994                 /*
1995                  * Under Windows:
1996                  * If requested stack size is larger than one page,
1997                  * perform stack-touch operation
1998                  */
1999                 /*
2000                  * Generate stack probe code.
2001                  * Under Windows, it is necessary to allocate one page at a time,
2002                  * "touching" stack after each successful sub-allocation. This is
2003                  * because of the way stack growth is implemented - there is a
2004                  * guard page before the lowest stack page that is currently commited.
2005                  * Stack normally grows sequentially so OS traps access to the
2006                  * guard page and commits more pages when needed.
2007                  */
2008                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2009                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2010
2011                 br[2] = code; /* loop */
2012                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2013                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2014                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2015                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2016                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2017                 amd64_patch (br[3], br[2]);
2018                 amd64_test_reg_reg (code, sreg, sreg);
2019                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2020                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2021
2022                 br[1] = code; x86_jump8 (code, 0);
2023
2024                 amd64_patch (br[0], code);
2025                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2026                 amd64_patch (br[1], code);
2027                 amd64_patch (br[4], code);
2028         }
2029         else
2030                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2031
2032         if (tree->flags & MONO_INST_INIT) {
2033                 int offset = 0;
2034                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2035                         amd64_push_reg (code, AMD64_RAX);
2036                         offset += 8;
2037                 }
2038                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2039                         amd64_push_reg (code, AMD64_RCX);
2040                         offset += 8;
2041                 }
2042                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2043                         amd64_push_reg (code, AMD64_RDI);
2044                         offset += 8;
2045                 }
2046
2047                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2048                 if (sreg != AMD64_RCX)
2049                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2050                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2051
2052                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2053                 amd64_cld (code);
2054                 amd64_prefix (code, X86_REP_PREFIX);
2055                 amd64_stosl (code);
2056
2057                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2058                         amd64_pop_reg (code, AMD64_RDI);
2059                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2060                         amd64_pop_reg (code, AMD64_RCX);
2061                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2062                         amd64_pop_reg (code, AMD64_RAX);
2063         }
2064         return code;
2065 }
2066
2067 static guint8*
2068 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2069 {
2070         CallInfo *cinfo;
2071         guint32 quad;
2072
2073         /* Move return value to the target register */
2074         /* FIXME: do this in the local reg allocator */
2075         switch (ins->opcode) {
2076         case CEE_CALL:
2077         case OP_CALL_REG:
2078         case OP_CALL_MEMBASE:
2079         case OP_LCALL:
2080         case OP_LCALL_REG:
2081         case OP_LCALL_MEMBASE:
2082                 g_assert (ins->dreg == AMD64_RAX);
2083                 break;
2084         case OP_FCALL:
2085         case OP_FCALL_REG:
2086         case OP_FCALL_MEMBASE:
2087                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2088                         if (use_sse2)
2089                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2090                         else {
2091                                 /* FIXME: optimize this */
2092                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2093                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2094                         }
2095                 }
2096                 else {
2097                         if (use_sse2) {
2098                                 if (ins->dreg != AMD64_XMM0)
2099                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2100                         }
2101                         else {
2102                                 /* FIXME: optimize this */
2103                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2104                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2105                         }
2106                 }
2107                 break;
2108         case OP_VCALL:
2109         case OP_VCALL_REG:
2110         case OP_VCALL_MEMBASE:
2111                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2112                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2113                         /* Pop the destination address from the stack */
2114                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2115                         amd64_pop_reg (code, AMD64_RCX);
2116
2117                         for (quad = 0; quad < 2; quad ++) {
2118                                 switch (cinfo->ret.pair_storage [quad]) {
2119                                 case ArgInIReg:
2120                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2121                                         break;
2122                                 case ArgInFloatSSEReg:
2123                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2124                                         break;
2125                                 case ArgInDoubleSSEReg:
2126                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2127                                         break;
2128                                 case ArgNone:
2129                                         break;
2130                                 default:
2131                                         NOT_IMPLEMENTED;
2132                                 }
2133                         }
2134                 }
2135                 g_free (cinfo);
2136                 break;
2137         }
2138
2139         return code;
2140 }
2141
2142 /*
2143  * emit_tls_get:
2144  * @code: buffer to store code to
2145  * @dreg: hard register where to place the result
2146  * @tls_offset: offset info
2147  *
2148  * emit_tls_get emits in @code the native code that puts in the dreg register
2149  * the item in the thread local storage identified by tls_offset.
2150  *
2151  * Returns: a pointer to the end of the stored code
2152  */
2153 static guint8*
2154 emit_tls_get (guint8* code, int dreg, int tls_offset)
2155 {
2156         if (optimize_for_xen) {
2157                 x86_prefix (code, X86_FS_PREFIX);
2158                 amd64_mov_reg_mem (code, dreg, 0, 8);
2159                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2160         } else {
2161                 x86_prefix (code, X86_FS_PREFIX);
2162                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2163         }
2164         return code;
2165 }
2166
2167 /*
2168  * emit_load_volatile_arguments:
2169  *
2170  *  Load volatile arguments from the stack to the original input registers.
2171  * Required before a tail call.
2172  */
2173 static guint8*
2174 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2175 {
2176         MonoMethod *method = cfg->method;
2177         MonoMethodSignature *sig;
2178         MonoInst *inst;
2179         CallInfo *cinfo;
2180         guint32 i;
2181
2182         /* FIXME: Generate intermediate code instead */
2183
2184         sig = mono_method_signature (method);
2185
2186         cinfo = get_call_info (sig, FALSE);
2187
2188         /* This is the opposite of the code in emit_prolog */
2189
2190         if (sig->ret->type != MONO_TYPE_VOID) {
2191                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2192                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2193                 }
2194         }
2195
2196         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2197                 ArgInfo *ainfo = cinfo->args + i;
2198                 MonoType *arg_type;
2199                 inst = cfg->varinfo [i];
2200
2201                 if (sig->hasthis && (i == 0))
2202                         arg_type = &mono_defaults.object_class->byval_arg;
2203                 else
2204                         arg_type = sig->params [i - sig->hasthis];
2205
2206                 if (inst->opcode != OP_REGVAR) {
2207                         switch (ainfo->storage) {
2208                         case ArgInIReg: {
2209                                 guint32 size = 8;
2210
2211                                 /* FIXME: I1 etc */
2212                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2213                                 break;
2214                         }
2215                         case ArgInFloatSSEReg:
2216                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2217                                 break;
2218                         case ArgInDoubleSSEReg:
2219                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2220                                 break;
2221                         default:
2222                                 break;
2223                         }
2224                 }
2225                 else {
2226                         g_assert (ainfo->storage == ArgInIReg);
2227
2228                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2229                 }
2230         }
2231
2232         g_free (cinfo);
2233
2234         return code;
2235 }
2236
2237 #define REAL_PRINT_REG(text,reg) \
2238 mono_assert (reg >= 0); \
2239 amd64_push_reg (code, AMD64_RAX); \
2240 amd64_push_reg (code, AMD64_RDX); \
2241 amd64_push_reg (code, AMD64_RCX); \
2242 amd64_push_reg (code, reg); \
2243 amd64_push_imm (code, reg); \
2244 amd64_push_imm (code, text " %d %p\n"); \
2245 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2246 amd64_call_reg (code, AMD64_RAX); \
2247 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2248 amd64_pop_reg (code, AMD64_RCX); \
2249 amd64_pop_reg (code, AMD64_RDX); \
2250 amd64_pop_reg (code, AMD64_RAX);
2251
2252 /* benchmark and set based on cpu */
2253 #define LOOP_ALIGNMENT 8
2254 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2255
2256 void
2257 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2258 {
2259         MonoInst *ins;
2260         MonoCallInst *call;
2261         guint offset;
2262         guint8 *code = cfg->native_code + cfg->code_len;
2263         MonoInst *last_ins = NULL;
2264         guint last_offset = 0;
2265         int max_len, cpos;
2266
2267         if (cfg->opt & MONO_OPT_PEEPHOLE)
2268                 peephole_pass (cfg, bb);
2269
2270         if (cfg->opt & MONO_OPT_LOOP) {
2271                 int pad, align = LOOP_ALIGNMENT;
2272                 /* set alignment depending on cpu */
2273                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2274                         pad = align - pad;
2275                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2276                         amd64_padding (code, pad);
2277                         cfg->code_len += pad;
2278                         bb->native_offset = cfg->code_len;
2279                 }
2280         }
2281
2282         if (cfg->verbose_level > 2)
2283                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2284
2285         cpos = bb->max_offset;
2286
2287         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2288                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2289                 g_assert (!cfg->compile_aot);
2290                 cpos += 6;
2291
2292                 cov->data [bb->dfn].cil_code = bb->cil_code;
2293                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2294                 /* this is not thread save, but good enough */
2295                 amd64_inc_membase (code, AMD64_R11, 0);
2296         }
2297
2298         offset = code - cfg->native_code;
2299
2300         mono_debug_open_block (cfg, bb, offset);
2301
2302         ins = bb->code;
2303         while (ins) {
2304                 offset = code - cfg->native_code;
2305
2306                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2307
2308                 if (offset > (cfg->code_size - max_len - 16)) {
2309                         cfg->code_size *= 2;
2310                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2311                         code = cfg->native_code + offset;
2312                         mono_jit_stats.code_reallocs++;
2313                 }
2314
2315                 mono_debug_record_line_number (cfg, ins, offset);
2316
2317                 switch (ins->opcode) {
2318                 case OP_BIGMUL:
2319                         amd64_mul_reg (code, ins->sreg2, TRUE);
2320                         break;
2321                 case OP_BIGMUL_UN:
2322                         amd64_mul_reg (code, ins->sreg2, FALSE);
2323                         break;
2324                 case OP_X86_SETEQ_MEMBASE:
2325                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2326                         break;
2327                 case OP_STOREI1_MEMBASE_IMM:
2328                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2329                         break;
2330                 case OP_STOREI2_MEMBASE_IMM:
2331                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2332                         break;
2333                 case OP_STOREI4_MEMBASE_IMM:
2334                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2335                         break;
2336                 case OP_STOREI1_MEMBASE_REG:
2337                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2338                         break;
2339                 case OP_STOREI2_MEMBASE_REG:
2340                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2341                         break;
2342                 case OP_STORE_MEMBASE_REG:
2343                 case OP_STOREI8_MEMBASE_REG:
2344                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2345                         break;
2346                 case OP_STOREI4_MEMBASE_REG:
2347                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2348                         break;
2349                 case OP_STORE_MEMBASE_IMM:
2350                 case OP_STOREI8_MEMBASE_IMM:
2351                         g_assert (amd64_is_imm32 (ins->inst_imm));
2352                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2353                         break;
2354                 case CEE_LDIND_I:
2355                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2356                         break;
2357                 case CEE_LDIND_I4:
2358                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2359                         break;
2360                 case CEE_LDIND_U4:
2361                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2362                         break;
2363                 case OP_LOADU4_MEM:
2364                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2365                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2366                         break;
2367                 case OP_LOAD_MEMBASE:
2368                 case OP_LOADI8_MEMBASE:
2369                         g_assert (amd64_is_imm32 (ins->inst_offset));
2370                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2371                         break;
2372                 case OP_LOADI4_MEMBASE:
2373                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2374                         break;
2375                 case OP_LOADU4_MEMBASE:
2376                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2377                         break;
2378                 case OP_LOADU1_MEMBASE:
2379                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2380                         break;
2381                 case OP_LOADI1_MEMBASE:
2382                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2383                         break;
2384                 case OP_LOADU2_MEMBASE:
2385                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2386                         break;
2387                 case OP_LOADI2_MEMBASE:
2388                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2389                         break;
2390                 case OP_AMD64_LOADI8_MEMINDEX:
2391                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2392                         break;
2393                 case CEE_CONV_I1:
2394                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2395                         break;
2396                 case CEE_CONV_I2:
2397                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2398                         break;
2399                 case CEE_CONV_U1:
2400                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2401                         break;
2402                 case CEE_CONV_U2:
2403                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2404                         break;
2405                 case CEE_CONV_U8:
2406                 case CEE_CONV_U:
2407                         /* Clean out the upper word */
2408                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2409                         break;
2410                 case CEE_CONV_I8:
2411                 case CEE_CONV_I:
2412                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2413                         break;
2414                 case OP_COMPARE:
2415                 case OP_LCOMPARE:
2416                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2417                         break;
2418                 case OP_COMPARE_IMM:
2419                         g_assert (amd64_is_imm32 (ins->inst_imm));
2420                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2421                         break;
2422                 case OP_X86_COMPARE_REG_MEMBASE:
2423                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2424                         break;
2425                 case OP_X86_TEST_NULL:
2426                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2427                         break;
2428                 case OP_AMD64_TEST_NULL:
2429                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2430                         break;
2431                 case OP_X86_ADD_MEMBASE_IMM:
2432                         /* FIXME: Make a 64 version too */
2433                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2434                         break;
2435                 case OP_X86_ADD_MEMBASE:
2436                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2437                         break;
2438                 case OP_X86_SUB_MEMBASE_IMM:
2439                         g_assert (amd64_is_imm32 (ins->inst_imm));
2440                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2441                         break;
2442                 case OP_X86_SUB_MEMBASE:
2443                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2444                         break;
2445                 case OP_X86_INC_MEMBASE:
2446                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2447                         break;
2448                 case OP_X86_INC_REG:
2449                         amd64_inc_reg_size (code, ins->dreg, 4);
2450                         break;
2451                 case OP_X86_DEC_MEMBASE:
2452                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2453                         break;
2454                 case OP_X86_DEC_REG:
2455                         amd64_dec_reg_size (code, ins->dreg, 4);
2456                         break;
2457                 case OP_X86_MUL_MEMBASE:
2458                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2459                         break;
2460                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2461                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2462                         break;
2463                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2464                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2465                         break;
2466                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2467                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2468                         break;
2469                 case CEE_BREAK:
2470                         amd64_breakpoint (code);
2471                         break;
2472                 case OP_ADDCC:
2473                 case CEE_ADD:
2474                 case OP_LADD:
2475                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2476                         break;
2477                 case OP_ADC:
2478                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2479                         break;
2480                 case OP_ADD_IMM:
2481                         g_assert (amd64_is_imm32 (ins->inst_imm));
2482                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2483                         break;
2484                 case OP_ADC_IMM:
2485                         g_assert (amd64_is_imm32 (ins->inst_imm));
2486                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2487                         break;
2488                 case OP_SUBCC:
2489                 case CEE_SUB:
2490                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2491                         break;
2492                 case OP_SBB:
2493                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2494                         break;
2495                 case OP_SUB_IMM:
2496                         g_assert (amd64_is_imm32 (ins->inst_imm));
2497                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2498                         break;
2499                 case OP_SBB_IMM:
2500                         g_assert (amd64_is_imm32 (ins->inst_imm));
2501                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2502                         break;
2503                 case CEE_AND:
2504                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2505                         break;
2506                 case OP_AND_IMM:
2507                         g_assert (amd64_is_imm32 (ins->inst_imm));
2508                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2509                         break;
2510                 case CEE_MUL:
2511                 case OP_LMUL:
2512                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2513                         break;
2514                 case OP_MUL_IMM:
2515                 case OP_LMUL_IMM:
2516                 case OP_IMUL_IMM: {
2517                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2518
2519                         switch (ins->inst_imm) {
2520                         case 2:
2521                                 /* MOV r1, r2 */
2522                                 /* ADD r1, r1 */
2523                                 if (ins->dreg != ins->sreg1)
2524                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2525                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2526                                 break;
2527                         case 3:
2528                                 /* LEA r1, [r2 + r2*2] */
2529                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2530                                 break;
2531                         case 5:
2532                                 /* LEA r1, [r2 + r2*4] */
2533                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2534                                 break;
2535                         case 6:
2536                                 /* LEA r1, [r2 + r2*2] */
2537                                 /* ADD r1, r1          */
2538                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2539                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2540                                 break;
2541                         case 9:
2542                                 /* LEA r1, [r2 + r2*8] */
2543                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2544                                 break;
2545                         case 10:
2546                                 /* LEA r1, [r2 + r2*4] */
2547                                 /* ADD r1, r1          */
2548                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2549                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2550                                 break;
2551                         case 12:
2552                                 /* LEA r1, [r2 + r2*2] */
2553                                 /* SHL r1, 2           */
2554                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2555                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2556                                 break;
2557                         case 25:
2558                                 /* LEA r1, [r2 + r2*4] */
2559                                 /* LEA r1, [r1 + r1*4] */
2560                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2561                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2562                                 break;
2563                         case 100:
2564                                 /* LEA r1, [r2 + r2*4] */
2565                                 /* SHL r1, 2           */
2566                                 /* LEA r1, [r1 + r1*4] */
2567                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2568                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2569                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2570                                 break;
2571                         default:
2572                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2573                                 break;
2574                         }
2575                         break;
2576                 }
2577                 case CEE_DIV:
2578                 case OP_LDIV:
2579                         amd64_cdq (code);
2580                         amd64_div_reg (code, ins->sreg2, TRUE);
2581                         break;
2582                 case CEE_DIV_UN:
2583                 case OP_LDIV_UN:
2584                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2585                         amd64_div_reg (code, ins->sreg2, FALSE);
2586                         break;
2587                 case CEE_REM:
2588                 case OP_LREM:
2589                         amd64_cdq (code);
2590                         amd64_div_reg (code, ins->sreg2, TRUE);
2591                         break;
2592                 case CEE_REM_UN:
2593                 case OP_LREM_UN:
2594                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2595                         amd64_div_reg (code, ins->sreg2, FALSE);
2596                         break;
2597                 case OP_LMUL_OVF:
2598                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2599                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2600                         break;
2601                 case CEE_OR:
2602                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2603                         break;
2604                 case OP_OR_IMM
2605 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2606                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2607                         break;
2608                 case CEE_XOR:
2609                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2610                         break;
2611                 case OP_XOR_IMM:
2612                         g_assert (amd64_is_imm32 (ins->inst_imm));
2613                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2614                         break;
2615                 case CEE_SHL:
2616                 case OP_LSHL:
2617                         g_assert (ins->sreg2 == AMD64_RCX);
2618                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2619                         break;
2620                 case CEE_SHR:
2621                 case OP_LSHR:
2622                         g_assert (ins->sreg2 == AMD64_RCX);
2623                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2624                         break;
2625                 case OP_SHR_IMM:
2626                         g_assert (amd64_is_imm32 (ins->inst_imm));
2627                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2628                         break;
2629                 case OP_LSHR_IMM:
2630                         g_assert (amd64_is_imm32 (ins->inst_imm));
2631                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2632                         break;
2633                 case OP_SHR_UN_IMM:
2634                         g_assert (amd64_is_imm32 (ins->inst_imm));
2635                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2636                         break;
2637                 case OP_LSHR_UN_IMM:
2638                         g_assert (amd64_is_imm32 (ins->inst_imm));
2639                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2640                         break;
2641                 case CEE_SHR_UN:
2642                         g_assert (ins->sreg2 == AMD64_RCX);
2643                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2644                         break;
2645                 case OP_LSHR_UN:
2646                         g_assert (ins->sreg2 == AMD64_RCX);
2647                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2648                         break;
2649                 case OP_SHL_IMM:
2650                         g_assert (amd64_is_imm32 (ins->inst_imm));
2651                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2652                         break;
2653                 case OP_LSHL_IMM:
2654                         g_assert (amd64_is_imm32 (ins->inst_imm));
2655                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2656                         break;
2657
2658                 case OP_IADDCC:
2659                 case OP_IADD:
2660                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2661                         break;
2662                 case OP_IADC:
2663                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2664                         break;
2665                 case OP_IADD_IMM:
2666                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2667                         break;
2668                 case OP_IADC_IMM:
2669                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2670                         break;
2671                 case OP_ISUBCC:
2672                 case OP_ISUB:
2673                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2674                         break;
2675                 case OP_ISBB:
2676                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2677                         break;
2678                 case OP_ISUB_IMM:
2679                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2680                         break;
2681                 case OP_ISBB_IMM:
2682                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2683                         break;
2684                 case OP_IAND:
2685                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2686                         break;
2687                 case OP_IAND_IMM:
2688                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2689                         break;
2690                 case OP_IOR:
2691                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2692                         break;
2693                 case OP_IOR_IMM:
2694                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2695                         break;
2696                 case OP_IXOR:
2697                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2698                         break;
2699                 case OP_IXOR_IMM:
2700                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2701                         break;
2702                 case OP_INEG:
2703                         amd64_neg_reg_size (code, ins->sreg1, 4);
2704                         break;
2705                 case OP_INOT:
2706                         amd64_not_reg_size (code, ins->sreg1, 4);
2707                         break;
2708                 case OP_ISHL:
2709                         g_assert (ins->sreg2 == AMD64_RCX);
2710                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2711                         break;
2712                 case OP_ISHR:
2713                         g_assert (ins->sreg2 == AMD64_RCX);
2714                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2715                         break;
2716                 case OP_ISHR_IMM:
2717                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2718                         break;
2719                 case OP_ISHR_UN_IMM:
2720                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2721                         break;
2722                 case OP_ISHR_UN:
2723                         g_assert (ins->sreg2 == AMD64_RCX);
2724                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2725                         break;
2726                 case OP_ISHL_IMM:
2727                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2728                         break;
2729                 case OP_IMUL:
2730                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2731                         break;
2732                 case OP_IMUL_OVF:
2733                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2734                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2735                         break;
2736                 case OP_IMUL_OVF_UN:
2737                 case OP_LMUL_OVF_UN: {
2738                         /* the mul operation and the exception check should most likely be split */
2739                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2740                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2741                         /*g_assert (ins->sreg2 == X86_EAX);
2742                         g_assert (ins->dreg == X86_EAX);*/
2743                         if (ins->sreg2 == X86_EAX) {
2744                                 non_eax_reg = ins->sreg1;
2745                         } else if (ins->sreg1 == X86_EAX) {
2746                                 non_eax_reg = ins->sreg2;
2747                         } else {
2748                                 /* no need to save since we're going to store to it anyway */
2749                                 if (ins->dreg != X86_EAX) {
2750                                         saved_eax = TRUE;
2751                                         amd64_push_reg (code, X86_EAX);
2752                                 }
2753                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2754                                 non_eax_reg = ins->sreg2;
2755                         }
2756                         if (ins->dreg == X86_EDX) {
2757                                 if (!saved_eax) {
2758                                         saved_eax = TRUE;
2759                                         amd64_push_reg (code, X86_EAX);
2760                                 }
2761                         } else {
2762                                 saved_edx = TRUE;
2763                                 amd64_push_reg (code, X86_EDX);
2764                         }
2765                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2766                         /* save before the check since pop and mov don't change the flags */
2767                         if (ins->dreg != X86_EAX)
2768                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2769                         if (saved_edx)
2770                                 amd64_pop_reg (code, X86_EDX);
2771                         if (saved_eax)
2772                                 amd64_pop_reg (code, X86_EAX);
2773                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2774                         break;
2775                 }
2776                 case OP_IDIV:
2777                         amd64_cdq_size (code, 4);
2778                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2779                         break;
2780                 case OP_IDIV_UN:
2781                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2782                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2783                         break;
2784                 case OP_IREM:
2785                         amd64_cdq_size (code, 4);
2786                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2787                         break;
2788                 case OP_IREM_UN:
2789                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2790                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2791                         break;
2792                 case OP_ICOMPARE:
2793                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2794                         break;
2795                 case OP_ICOMPARE_IMM:
2796                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2797                         break;
2798                 case OP_IBEQ:
2799                 case OP_IBLT:
2800                 case OP_IBGT:
2801                 case OP_IBGE:
2802                 case OP_IBLE:
2803                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2804                         break;
2805                 case OP_IBNE_UN:
2806                 case OP_IBLT_UN:
2807                 case OP_IBGT_UN:
2808                 case OP_IBGE_UN:
2809                 case OP_IBLE_UN:
2810                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2811                         break;
2812                 case OP_COND_EXC_IOV:
2813                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2814                                                                                 TRUE, ins->inst_p1);
2815                         break;
2816                 case OP_COND_EXC_IC:
2817                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2818                                                                                 FALSE, ins->inst_p1);
2819                         break;
2820                 case CEE_NOT:
2821                         amd64_not_reg (code, ins->sreg1);
2822                         break;
2823                 case CEE_NEG:
2824                         amd64_neg_reg (code, ins->sreg1);
2825                         break;
2826                 case OP_SEXT_I1:
2827                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2828                         break;
2829                 case OP_SEXT_I2:
2830                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2831                         break;
2832                 case OP_SEXT_I4:
2833                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2834                         break;
2835                 case OP_ICONST:
2836                 case OP_I8CONST:
2837                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2838                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2839                         else
2840                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2841                         break;
2842                 case OP_AOTCONST:
2843                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2844                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2845                         break;
2846                 case CEE_CONV_I4:
2847                 case CEE_CONV_U4:
2848                 case OP_MOVE:
2849                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2850                         break;
2851                 case OP_AMD64_SET_XMMREG_R4: {
2852                         if (use_sse2) {
2853                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2854                         }
2855                         else {
2856                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2857                                 /* ins->dreg is set to -1 by the reg allocator */
2858                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2859                         }
2860                         break;
2861                 }
2862                 case OP_AMD64_SET_XMMREG_R8: {
2863                         if (use_sse2) {
2864                                 if (ins->dreg != ins->sreg1)
2865                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2866                         }
2867                         else {
2868                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2869                                 /* ins->dreg is set to -1 by the reg allocator */
2870                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2871                         }
2872                         break;
2873                 }
2874                 case CEE_JMP: {
2875                         /*
2876                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2877                          * Keep in sync with the code in emit_epilog.
2878                          */
2879                         int pos = 0, i;
2880
2881                         /* FIXME: no tracing support... */
2882                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2883                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2884
2885                         g_assert (!cfg->method->save_lmf);
2886
2887                         code = emit_load_volatile_arguments (cfg, code);
2888
2889                         if (cfg->arch.omit_fp) {
2890                                 guint32 save_offset = 0;
2891                                 /* Pop callee-saved registers */
2892                                 for (i = 0; i < AMD64_NREG; ++i)
2893                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2894                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2895                                                 save_offset += 8;
2896                                         }
2897                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2898                         }
2899                         else {
2900                                 for (i = 0; i < AMD64_NREG; ++i)
2901                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2902                                                 pos -= sizeof (gpointer);
2903
2904                                 if (pos)
2905                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2906
2907                                 /* Pop registers in reverse order */
2908                                 for (i = AMD64_NREG - 1; i > 0; --i)
2909                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2910                                                 amd64_pop_reg (code, i);
2911                                         }
2912
2913                                 amd64_leave (code);
2914                         }
2915
2916                         offset = code - cfg->native_code;
2917                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2918                         if (cfg->compile_aot)
2919                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2920                         else
2921                                 amd64_set_reg_template (code, AMD64_R11);
2922                         amd64_jump_reg (code, AMD64_R11);
2923                         break;
2924                 }
2925                 case OP_CHECK_THIS:
2926                         /* ensure ins->sreg1 is not NULL */
2927                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2928                         break;
2929                 case OP_ARGLIST: {
2930                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2931                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2932                         break;
2933                 }
2934                 case OP_FCALL:
2935                 case OP_LCALL:
2936                 case OP_VCALL:
2937                 case OP_VOIDCALL:
2938                 case CEE_CALL:
2939                         call = (MonoCallInst*)ins;
2940                         /*
2941                          * The AMD64 ABI forces callers to know about varargs.
2942                          */
2943                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2944                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2945                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2946                                 /*
2947                                  * Since the unmanaged calling convention doesn't contain a
2948                                  * 'vararg' entry, we have to treat every pinvoke call as a
2949                                  * potential vararg call.
2950                                  */
2951                                 guint32 nregs, i;
2952                                 nregs = 0;
2953                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2954                                         if (call->used_fregs & (1 << i))
2955                                                 nregs ++;
2956                                 if (!nregs)
2957                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2958                                 else
2959                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2960                         }
2961
2962                         if (ins->flags & MONO_INST_HAS_METHOD)
2963                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2964                         else
2965                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2966                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2967                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2968                         code = emit_move_return_value (cfg, ins, code);
2969                         break;
2970                 case OP_FCALL_REG:
2971                 case OP_LCALL_REG:
2972                 case OP_VCALL_REG:
2973                 case OP_VOIDCALL_REG:
2974                 case OP_CALL_REG:
2975                         call = (MonoCallInst*)ins;
2976
2977                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2978                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2979                                 ins->sreg1 = AMD64_R11;
2980                         }
2981
2982                         /*
2983                          * The AMD64 ABI forces callers to know about varargs.
2984                          */
2985                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2986                                 if (ins->sreg1 == AMD64_RAX) {
2987                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2988                                         ins->sreg1 = AMD64_R11;
2989                                 }
2990                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2991                         }
2992                         amd64_call_reg (code, ins->sreg1);
2993                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2994                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2995                         code = emit_move_return_value (cfg, ins, code);
2996                         break;
2997                 case OP_FCALL_MEMBASE:
2998                 case OP_LCALL_MEMBASE:
2999                 case OP_VCALL_MEMBASE:
3000                 case OP_VOIDCALL_MEMBASE:
3001                 case OP_CALL_MEMBASE:
3002                         call = (MonoCallInst*)ins;
3003
3004                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3005                                 /*
3006                                  * Can't use R11 because it is clobbered by the trampoline
3007                                  * code, and the reg value is needed by get_vcall_slot_addr.
3008                                  */
3009                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3010                                 ins->sreg1 = AMD64_RAX;
3011                         }
3012
3013                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3014                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3015                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3016                         code = emit_move_return_value (cfg, ins, code);
3017                         break;
3018                 case OP_OUTARG:
3019                 case OP_X86_PUSH:
3020                         amd64_push_reg (code, ins->sreg1);
3021                         break;
3022                 case OP_X86_PUSH_IMM:
3023                         g_assert (amd64_is_imm32 (ins->inst_imm));
3024                         amd64_push_imm (code, ins->inst_imm);
3025                         break;
3026                 case OP_X86_PUSH_MEMBASE:
3027                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3028                         break;
3029                 case OP_X86_PUSH_OBJ:
3030                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3031                         amd64_push_reg (code, AMD64_RDI);
3032                         amd64_push_reg (code, AMD64_RSI);
3033                         amd64_push_reg (code, AMD64_RCX);
3034                         if (ins->inst_offset)
3035                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3036                         else
3037                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3038                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3039                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3040                         amd64_cld (code);
3041                         amd64_prefix (code, X86_REP_PREFIX);
3042                         amd64_movsd (code);
3043                         amd64_pop_reg (code, AMD64_RCX);
3044                         amd64_pop_reg (code, AMD64_RSI);
3045                         amd64_pop_reg (code, AMD64_RDI);
3046                         break;
3047                 case OP_X86_LEA:
3048                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3049                         break;
3050                 case OP_X86_LEA_MEMBASE:
3051                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3052                         break;
3053                 case OP_X86_XCHG:
3054                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3055                         break;
3056                 case OP_LOCALLOC:
3057                         /* keep alignment */
3058                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3059                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3060                         code = mono_emit_stack_alloc (code, ins);
3061                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3062                         break;
3063                 case CEE_RET:
3064                         amd64_ret (code);
3065                         break;
3066                 case CEE_THROW: {
3067                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3068                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3069                                              (gpointer)"mono_arch_throw_exception");
3070                         break;
3071                 }
3072                 case OP_RETHROW: {
3073                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3074                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3075                                              (gpointer)"mono_arch_rethrow_exception");
3076                         break;
3077                 }
3078                 case OP_CALL_HANDLER:
3079                         /* Align stack */
3080                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3081                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3082                         amd64_call_imm (code, 0);
3083                         /* Restore stack alignment */
3084                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3085                         break;
3086                 case OP_LABEL:
3087                         ins->inst_c0 = code - cfg->native_code;
3088                         break;
3089                 case CEE_BR:
3090                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3091                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3092                         //break;
3093                         if (ins->flags & MONO_INST_BRLABEL) {
3094                                 if (ins->inst_i0->inst_c0) {
3095                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3096                                 } else {
3097                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3098                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3099                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3100                                                 x86_jump8 (code, 0);
3101                                         else
3102                                                 x86_jump32 (code, 0);
3103                                 }
3104                         } else {
3105                                 if (ins->inst_target_bb->native_offset) {
3106                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3107                                 } else {
3108                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3109                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3110                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3111                                                 x86_jump8 (code, 0);
3112                                         else
3113                                                 x86_jump32 (code, 0);
3114                                 }
3115                         }
3116                         break;
3117                 case OP_BR_REG:
3118                         amd64_jump_reg (code, ins->sreg1);
3119                         break;
3120                 case OP_CEQ:
3121                 case OP_ICEQ:
3122                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3123                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3124                         break;
3125                 case OP_CLT:
3126                 case OP_ICLT:
3127                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3128                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3129                         break;
3130                 case OP_CLT_UN:
3131                 case OP_ICLT_UN:
3132                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3133                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3134                         break;
3135                 case OP_CGT:
3136                 case OP_ICGT:
3137                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3138                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3139                         break;
3140                 case OP_CGT_UN:
3141                 case OP_ICGT_UN:
3142                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3143                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3144                         break;
3145                 case OP_COND_EXC_EQ:
3146                 case OP_COND_EXC_NE_UN:
3147                 case OP_COND_EXC_LT:
3148                 case OP_COND_EXC_LT_UN:
3149                 case OP_COND_EXC_GT:
3150                 case OP_COND_EXC_GT_UN:
3151                 case OP_COND_EXC_GE:
3152                 case OP_COND_EXC_GE_UN:
3153                 case OP_COND_EXC_LE:
3154                 case OP_COND_EXC_LE_UN:
3155                 case OP_COND_EXC_OV:
3156                 case OP_COND_EXC_NO:
3157                 case OP_COND_EXC_C:
3158                 case OP_COND_EXC_NC:
3159                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3160                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3161                         break;
3162                 case CEE_BEQ:
3163                 case CEE_BNE_UN:
3164                 case CEE_BLT:
3165                 case CEE_BLT_UN:
3166                 case CEE_BGT:
3167                 case CEE_BGT_UN:
3168                 case CEE_BGE:
3169                 case CEE_BGE_UN:
3170                 case CEE_BLE:
3171                 case CEE_BLE_UN:
3172                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3173                         break;
3174
3175                 /* floating point opcodes */
3176                 case OP_R8CONST: {
3177                         double d = *(double *)ins->inst_p0;
3178
3179                         if (use_sse2) {
3180                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3181                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3182                                 }
3183                                 else {
3184                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3185                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3186                                 }
3187                         }
3188                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3189                                 amd64_fldz (code);
3190                         } else if (d == 1.0) {
3191                                 x86_fld1 (code);
3192                         } else {
3193                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3194                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3195                         }
3196                         break;
3197                 }
3198                 case OP_R4CONST: {
3199                         float f = *(float *)ins->inst_p0;
3200
3201                         if (use_sse2) {
3202                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3203                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3204                                 }
3205                                 else {
3206                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3207                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3208                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3209                                 }
3210                         }
3211                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3212                                 amd64_fldz (code);
3213                         } else if (f == 1.0) {
3214                                 x86_fld1 (code);
3215                         } else {
3216                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3217                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3218                         }
3219                         break;
3220                 }
3221                 case OP_STORER8_MEMBASE_REG:
3222                         if (use_sse2)
3223                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3224                         else
3225                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3226                         break;
3227                 case OP_LOADR8_SPILL_MEMBASE:
3228                         if (use_sse2)
3229                                 g_assert_not_reached ();
3230                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3231                         amd64_fxch (code, 1);
3232                         break;
3233                 case OP_LOADR8_MEMBASE:
3234                         if (use_sse2)
3235                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3236                         else
3237                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3238                         break;
3239                 case OP_STORER4_MEMBASE_REG:
3240                         if (use_sse2) {
3241                                 /* This requires a double->single conversion */
3242                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3243                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3244                         }
3245                         else
3246                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3247                         break;
3248                 case OP_LOADR4_MEMBASE:
3249                         if (use_sse2) {
3250                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3251                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3252                         }
3253                         else
3254                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3255                         break;
3256                 case CEE_CONV_R4: /* FIXME: change precision */
3257                 case CEE_CONV_R8:
3258                         if (use_sse2)
3259                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3260                         else {
3261                                 amd64_push_reg (code, ins->sreg1);
3262                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3263                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3264                         }
3265                         break;
3266                 case CEE_CONV_R_UN:
3267                         /* Emulated */
3268                         g_assert_not_reached ();
3269                         break;
3270                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3271                 case OP_LCONV_TO_R8:
3272                         if (use_sse2)
3273                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3274                         else {
3275                                 amd64_push_reg (code, ins->sreg1);
3276                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3277                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3278                         }
3279                         break;
3280                 case OP_X86_FP_LOAD_I8:
3281                         if (use_sse2)
3282                                 g_assert_not_reached ();
3283                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3284                         break;
3285                 case OP_X86_FP_LOAD_I4:
3286                         if (use_sse2)
3287                                 g_assert_not_reached ();
3288                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3289                         break;
3290                 case OP_FCONV_TO_I1:
3291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3292                         break;
3293                 case OP_FCONV_TO_U1:
3294                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3295                         break;
3296                 case OP_FCONV_TO_I2:
3297                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3298                         break;
3299                 case OP_FCONV_TO_U2:
3300                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3301                         break;
3302                 case OP_FCONV_TO_I4:
3303                 case OP_FCONV_TO_I:
3304                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3305                         break;
3306                 case OP_FCONV_TO_I8:
3307                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3308                         break;
3309                 case OP_LCONV_TO_R_UN: {
3310                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3311                         guint8 *br;
3312
3313                         if (use_sse2)
3314                                 g_assert_not_reached ();
3315
3316                         /* load 64bit integer to FP stack */
3317                         amd64_push_imm (code, 0);
3318                         amd64_push_reg (code, ins->sreg2);
3319                         amd64_push_reg (code, ins->sreg1);
3320                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3321                         /* store as 80bit FP value */
3322                         x86_fst80_membase (code, AMD64_RSP, 0);
3323
3324                         /* test if lreg is negative */
3325                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3326                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3327
3328                         /* add correction constant mn */
3329                         x86_fld80_mem (code, mn);
3330                         x86_fld80_membase (code, AMD64_RSP, 0);
3331                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3332                         x86_fst80_membase (code, AMD64_RSP, 0);
3333
3334                         amd64_patch (br, code);
3335
3336                         x86_fld80_membase (code, AMD64_RSP, 0);
3337                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3338
3339                         break;
3340                 }
3341                 case CEE_CONV_OVF_U4:
3342                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3343                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3344                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3345                         break;
3346                 case CEE_CONV_OVF_I4_UN:
3347                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3349                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3350                         break;
3351                 case OP_FMOVE:
3352                         if (use_sse2 && (ins->dreg != ins->sreg1))
3353                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3354                         break;
3355                 case OP_FADD:
3356                         if (use_sse2)
3357                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3358                         else
3359                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3360                         break;
3361                 case OP_FSUB:
3362                         if (use_sse2)
3363                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3364                         else
3365                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3366                         break;
3367                 case OP_FMUL:
3368                         if (use_sse2)
3369                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3370                         else
3371                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3372                         break;
3373                 case OP_FDIV:
3374                         if (use_sse2)
3375                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3376                         else
3377                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3378                         break;
3379                 case OP_FNEG:
3380                         if (use_sse2) {
3381                                 static double r8_0 = -0.0;
3382
3383                                 g_assert (ins->sreg1 == ins->dreg);
3384
3385                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3386                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3387                         }
3388                         else
3389                                 amd64_fchs (code);
3390                         break;
3391                 case OP_SIN:
3392                         if (use_sse2) {
3393                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3394                         }
3395                         else {
3396                                 amd64_fsin (code);
3397                                 amd64_fldz (code);
3398                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3399                         }
3400                         break;
3401                 case OP_COS:
3402                         if (use_sse2) {
3403                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3404                         }
3405                         else {
3406                                 amd64_fcos (code);
3407                                 amd64_fldz (code);
3408                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3409                         }
3410                         break;
3411                 case OP_ABS:
3412                         if (use_sse2) {
3413                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3414                         }
3415                         else
3416                                 amd64_fabs (code);
3417                         break;
3418                 case OP_TAN: {
3419                         /*
3420                          * it really doesn't make sense to inline all this code,
3421                          * it's here just to show that things may not be as simple
3422                          * as they appear.
3423                          */
3424                         guchar *check_pos, *end_tan, *pop_jump;
3425                         if (use_sse2)
3426                                 g_assert_not_reached ();
3427                         amd64_push_reg (code, AMD64_RAX);
3428                         amd64_fptan (code);
3429                         amd64_fnstsw (code);
3430                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3431                         check_pos = code;
3432                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3433                         amd64_fstp (code, 0); /* pop the 1.0 */
3434                         end_tan = code;
3435                         x86_jump8 (code, 0);
3436                         amd64_fldpi (code);
3437                         amd64_fp_op (code, X86_FADD, 0);
3438                         amd64_fxch (code, 1);
3439                         x86_fprem1 (code);
3440                         amd64_fstsw (code);
3441                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3442                         pop_jump = code;
3443                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3444                         amd64_fstp (code, 1);
3445                         amd64_fptan (code);
3446                         amd64_patch (pop_jump, code);
3447                         amd64_fstp (code, 0); /* pop the 1.0 */
3448                         amd64_patch (check_pos, code);
3449                         amd64_patch (end_tan, code);
3450                         amd64_fldz (code);
3451                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3452                         amd64_pop_reg (code, AMD64_RAX);
3453                         break;
3454                 }
3455                 case OP_ATAN:
3456                         if (use_sse2)
3457                                 g_assert_not_reached ();
3458                         x86_fld1 (code);
3459                         amd64_fpatan (code);
3460                         amd64_fldz (code);
3461                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3462                         break;
3463                 case OP_SQRT:
3464                         if (use_sse2) {
3465                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3466                         }
3467                         else
3468                                 amd64_fsqrt (code);
3469                         break;
3470                 case OP_X86_FPOP:
3471                         if (!use_sse2)
3472                                 amd64_fstp (code, 0);
3473                         break;
3474                 case OP_FREM: {
3475                         guint8 *l1, *l2;
3476
3477                         if (use_sse2)
3478                                 g_assert_not_reached ();
3479                         amd64_push_reg (code, AMD64_RAX);
3480                         /* we need to exchange ST(0) with ST(1) */
3481                         amd64_fxch (code, 1);
3482
3483                         /* this requires a loop, because fprem somtimes
3484                          * returns a partial remainder */
3485                         l1 = code;
3486                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3487                         /* x86_fprem1 (code); */
3488                         amd64_fprem (code);
3489                         amd64_fnstsw (code);
3490                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3491                         l2 = code + 2;
3492                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3493
3494                         /* pop result */
3495                         amd64_fstp (code, 1);
3496
3497                         amd64_pop_reg (code, AMD64_RAX);
3498                         break;
3499                 }
3500                 case OP_FCOMPARE:
3501                         if (use_sse2) {
3502                                 /*
3503                                  * The two arguments are swapped because the fbranch instructions
3504                                  * depend on this for the non-sse case to work.
3505                                  */
3506                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3507                                 break;
3508                         }
3509                         if (cfg->opt & MONO_OPT_FCMOV) {
3510                                 amd64_fcomip (code, 1);
3511                                 amd64_fstp (code, 0);
3512                                 break;
3513                         }
3514                         /* this overwrites EAX */
3515                         EMIT_FPCOMPARE(code);
3516                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3517                         break;
3518                 case OP_FCEQ:
3519                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3520                                 /* zeroing the register at the start results in
3521                                  * shorter and faster code (we can also remove the widening op)
3522                                  */
3523                                 guchar *unordered_check;
3524                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3525
3526                                 if (use_sse2)
3527                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3528                                 else {
3529                                         amd64_fcomip (code, 1);
3530                                         amd64_fstp (code, 0);
3531                                 }
3532                                 unordered_check = code;
3533                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3534                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3535                                 amd64_patch (unordered_check, code);
3536                                 break;
3537                         }
3538                         if (ins->dreg != AMD64_RAX)
3539                                 amd64_push_reg (code, AMD64_RAX);
3540
3541                         EMIT_FPCOMPARE(code);
3542                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3543                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3544                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3545                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3546
3547                         if (ins->dreg != AMD64_RAX)
3548                                 amd64_pop_reg (code, AMD64_RAX);
3549                         break;
3550                 case OP_FCLT:
3551                 case OP_FCLT_UN:
3552                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3553                                 /* zeroing the register at the start results in
3554                                  * shorter and faster code (we can also remove the widening op)
3555                                  */
3556                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3557                                 if (use_sse2)
3558                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3559                                 else {
3560                                         amd64_fcomip (code, 1);
3561                                         amd64_fstp (code, 0);
3562                                 }
3563                                 if (ins->opcode == OP_FCLT_UN) {
3564                                         guchar *unordered_check = code;
3565                                         guchar *jump_to_end;
3566                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3567                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3568                                         jump_to_end = code;
3569                                         x86_jump8 (code, 0);
3570                                         amd64_patch (unordered_check, code);
3571                                         amd64_inc_reg (code, ins->dreg);
3572                                         amd64_patch (jump_to_end, code);
3573                                 } else {
3574                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3575                                 }
3576                                 break;
3577                         }
3578                         if (ins->dreg != AMD64_RAX)
3579                                 amd64_push_reg (code, AMD64_RAX);
3580
3581                         EMIT_FPCOMPARE(code);
3582                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3583                         if (ins->opcode == OP_FCLT_UN) {
3584                                 guchar *is_not_zero_check, *end_jump;
3585                                 is_not_zero_check = code;
3586                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3587                                 end_jump = code;
3588                                 x86_jump8 (code, 0);
3589                                 amd64_patch (is_not_zero_check, code);
3590                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3591
3592                                 amd64_patch (end_jump, code);
3593                         }
3594                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3595                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3596
3597                         if (ins->dreg != AMD64_RAX)
3598                                 amd64_pop_reg (code, AMD64_RAX);
3599                         break;
3600                 case OP_FCGT:
3601                 case OP_FCGT_UN:
3602                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3603                                 /* zeroing the register at the start results in
3604                                  * shorter and faster code (we can also remove the widening op)
3605                                  */
3606                                 guchar *unordered_check;
3607                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3608                                 if (use_sse2)
3609                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3610                                 else {
3611                                         amd64_fcomip (code, 1);
3612                                         amd64_fstp (code, 0);
3613                                 }
3614                                 if (ins->opcode == OP_FCGT) {
3615                                         unordered_check = code;
3616                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3617                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3618                                         amd64_patch (unordered_check, code);
3619                                 } else {
3620                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3621                                 }
3622                                 break;
3623                         }
3624                         if (ins->dreg != AMD64_RAX)
3625                                 amd64_push_reg (code, AMD64_RAX);
3626
3627                         EMIT_FPCOMPARE(code);
3628                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3629                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3630                         if (ins->opcode == OP_FCGT_UN) {
3631                                 guchar *is_not_zero_check, *end_jump;
3632                                 is_not_zero_check = code;
3633                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3634                                 end_jump = code;
3635                                 x86_jump8 (code, 0);
3636                                 amd64_patch (is_not_zero_check, code);
3637                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3638
3639                                 amd64_patch (end_jump, code);
3640                         }
3641                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3642                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3643
3644                         if (ins->dreg != AMD64_RAX)
3645                                 amd64_pop_reg (code, AMD64_RAX);
3646                         break;
3647                 case OP_FCLT_MEMBASE:
3648                 case OP_FCGT_MEMBASE:
3649                 case OP_FCLT_UN_MEMBASE:
3650                 case OP_FCGT_UN_MEMBASE:
3651                 case OP_FCEQ_MEMBASE: {
3652                         guchar *unordered_check, *jump_to_end;
3653                         int x86_cond;
3654                         g_assert (use_sse2);
3655
3656                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3657                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3658
3659                         switch (ins->opcode) {
3660                         case OP_FCEQ_MEMBASE:
3661                                 x86_cond = X86_CC_EQ;
3662                                 break;
3663                         case OP_FCLT_MEMBASE:
3664                         case OP_FCLT_UN_MEMBASE:
3665                                 x86_cond = X86_CC_LT;
3666                                 break;
3667                         case OP_FCGT_MEMBASE:
3668                         case OP_FCGT_UN_MEMBASE:
3669                                 x86_cond = X86_CC_GT;
3670                                 break;
3671                         default:
3672                                 g_assert_not_reached ();
3673                         }
3674
3675                         unordered_check = code;
3676                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3677                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3678
3679                         switch (ins->opcode) {
3680                         case OP_FCEQ_MEMBASE:
3681                         case OP_FCLT_MEMBASE:
3682                         case OP_FCGT_MEMBASE:
3683                                 amd64_patch (unordered_check, code);
3684                                 break;
3685                         case OP_FCLT_UN_MEMBASE:
3686                         case OP_FCGT_UN_MEMBASE:
3687                                 jump_to_end = code;
3688                                 x86_jump8 (code, 0);
3689                                 amd64_patch (unordered_check, code);
3690                                 amd64_inc_reg (code, ins->dreg);
3691                                 amd64_patch (jump_to_end, code);
3692                                 break;
3693                         default:
3694                                 break;
3695                         }
3696                         break;
3697                 }
3698                 case OP_FBEQ:
3699                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3700                                 guchar *jump = code;
3701                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3702                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3703                                 amd64_patch (jump, code);
3704                                 break;
3705                         }
3706                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3707                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3708                         break;
3709                 case OP_FBNE_UN:
3710                         /* Branch if C013 != 100 */
3711                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3712                                 /* branch if !ZF or (PF|CF) */
3713                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3714                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3715                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3716                                 break;
3717                         }
3718                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3719                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3720                         break;
3721                 case OP_FBLT:
3722                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3723                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3724                                 break;
3725                         }
3726                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3727                         break;
3728                 case OP_FBLT_UN:
3729                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3730                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3731                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3732                                 break;
3733                         }
3734                         if (ins->opcode == OP_FBLT_UN) {
3735                                 guchar *is_not_zero_check, *end_jump;
3736                                 is_not_zero_check = code;
3737                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3738                                 end_jump = code;
3739                                 x86_jump8 (code, 0);
3740                                 amd64_patch (is_not_zero_check, code);
3741                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3742
3743                                 amd64_patch (end_jump, code);
3744                         }
3745                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3746                         break;
3747                 case OP_FBGT:
3748                 case OP_FBGT_UN:
3749                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3750                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3751                                 break;
3752                         }
3753                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3754                         if (ins->opcode == OP_FBGT_UN) {
3755                                 guchar *is_not_zero_check, *end_jump;
3756                                 is_not_zero_check = code;
3757                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3758                                 end_jump = code;
3759                                 x86_jump8 (code, 0);
3760                                 amd64_patch (is_not_zero_check, code);
3761                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3762
3763                                 amd64_patch (end_jump, code);
3764                         }
3765                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3766                         break;
3767                 case OP_FBGE:
3768                         /* Branch if C013 == 100 or 001 */
3769                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3770                                 guchar *br1;
3771
3772                                 /* skip branch if C1=1 */
3773                                 br1 = code;
3774                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3775                                 /* branch if (C0 | C3) = 1 */
3776                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3777                                 amd64_patch (br1, code);
3778                                 break;
3779                         }
3780                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3781                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3782                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3783                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3784                         break;
3785                 case OP_FBGE_UN:
3786                         /* Branch if C013 == 000 */
3787                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3788                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3789                                 break;
3790                         }
3791                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3792                         break;
3793                 case OP_FBLE:
3794                         /* Branch if C013=000 or 100 */
3795                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3796                                 guchar *br1;
3797
3798                                 /* skip branch if C1=1 */
3799                                 br1 = code;
3800                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3801                                 /* branch if C0=0 */
3802                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3803                                 amd64_patch (br1, code);
3804                                 break;
3805                         }
3806                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3807                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3808                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3809                         break;
3810                 case OP_FBLE_UN:
3811                         /* Branch if C013 != 001 */
3812                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3813                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3814                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3815                                 break;
3816                         }
3817                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3818                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3819                         break;
3820                 case CEE_CKFINITE: {
3821                         if (use_sse2) {
3822                                 /* Transfer value to the fp stack */
3823                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3824                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3825                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3826                         }
3827                         amd64_push_reg (code, AMD64_RAX);
3828                         amd64_fxam (code);
3829                         amd64_fnstsw (code);
3830                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3831                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3832                         amd64_pop_reg (code, AMD64_RAX);
3833                         if (use_sse2) {
3834                                 amd64_fstp (code, 0);
3835                         }
3836                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3837                         if (use_sse2)
3838                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3839                         break;
3840                 }
3841                 case OP_TLS_GET: {
3842                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3843                         break;
3844                 }
3845                 case OP_MEMORY_BARRIER: {
3846                         /* Not needed on amd64 */
3847                         break;
3848                 }
3849                 case OP_ATOMIC_ADD_I4:
3850                 case OP_ATOMIC_ADD_I8: {
3851                         int dreg = ins->dreg;
3852                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3853
3854                         if (dreg == ins->inst_basereg)
3855                                 dreg = AMD64_R11;
3856
3857                         if (dreg != ins->sreg2)
3858                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3859
3860                         x86_prefix (code, X86_LOCK_PREFIX);
3861                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3862
3863                         if (dreg != ins->dreg)
3864                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3865
3866                         break;
3867                 }
3868                 case OP_ATOMIC_ADD_NEW_I4:
3869                 case OP_ATOMIC_ADD_NEW_I8: {
3870                         int dreg = ins->dreg;
3871                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3872
3873                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3874                                 dreg = AMD64_R11;
3875
3876                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3877                         amd64_prefix (code, X86_LOCK_PREFIX);
3878                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3879                         /* dreg contains the old value, add with sreg2 value */
3880                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3881
3882                         if (ins->dreg != dreg)
3883                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3884
3885                         break;
3886                 }
3887                 case OP_ATOMIC_EXCHANGE_I4:
3888                 case OP_ATOMIC_EXCHANGE_I8: {
3889                         guchar *br[2];
3890                         int sreg2 = ins->sreg2;
3891                         int breg = ins->inst_basereg;
3892                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3893
3894                         /*
3895                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3896                          * an explanation of how this works.
3897                          */
3898
3899                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3900                          * hack to overcome limits in x86 reg allocator
3901                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3902                          */
3903                         if (ins->dreg != AMD64_RAX)
3904                                 amd64_push_reg (code, AMD64_RAX);
3905
3906                         /* We need the EAX reg for the cmpxchg */
3907                         if (ins->sreg2 == AMD64_RAX) {
3908                                 amd64_push_reg (code, AMD64_RDX);
3909                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3910                                 sreg2 = AMD64_RDX;
3911                         }
3912
3913                         if (breg == AMD64_RAX) {
3914                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3915                                 breg = AMD64_R11;
3916                         }
3917
3918                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3919
3920                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3921                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3922                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3923                         amd64_patch (br [1], br [0]);
3924
3925                         if (ins->dreg != AMD64_RAX) {
3926                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3927                                 amd64_pop_reg (code, AMD64_RAX);
3928                         }
3929
3930                         if (ins->sreg2 != sreg2)
3931                                 amd64_pop_reg (code, AMD64_RDX);
3932
3933                         break;
3934                 }
3935                 default:
3936                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3937                         g_assert_not_reached ();
3938                 }
3939
3940                 if ((code - cfg->native_code - offset) > max_len) {
3941                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3942                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3943                         g_assert_not_reached ();
3944                 }
3945
3946                 cpos += max_len;
3947
3948                 last_ins = ins;
3949                 last_offset = offset;
3950
3951                 ins = ins->next;
3952         }
3953
3954         cfg->code_len = code - cfg->native_code;
3955 }
3956
3957 void
3958 mono_arch_register_lowlevel_calls (void)
3959 {
3960 }
3961
3962 void
3963 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3964 {
3965         MonoJumpInfo *patch_info;
3966         gboolean compile_aot = !run_cctors;
3967
3968         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3969                 unsigned char *ip = patch_info->ip.i + code;
3970                 const unsigned char *target;
3971
3972                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3973
3974                 if (compile_aot) {
3975                         switch (patch_info->type) {
3976                         case MONO_PATCH_INFO_BB:
3977                         case MONO_PATCH_INFO_LABEL:
3978                                 break;
3979                         default:
3980                                 /* No need to patch these */
3981                                 continue;
3982                         }
3983                 }
3984
3985                 switch (patch_info->type) {
3986                 case MONO_PATCH_INFO_NONE:
3987                         continue;
3988                 case MONO_PATCH_INFO_METHOD_REL:
3989                 case MONO_PATCH_INFO_R8:
3990                 case MONO_PATCH_INFO_R4:
3991                         g_assert_not_reached ();
3992                         continue;
3993                 case MONO_PATCH_INFO_BB:
3994                         break;
3995                 default:
3996                         break;
3997                 }
3998
3999                 /*
4000                  * Debug code to help track down problems where the target of a near call is
4001                  * is not valid.
4002                  */
4003                 if (amd64_is_near_call (ip)) {
4004                         gint64 disp = (guint8*)target - (guint8*)ip;
4005
4006                         if (!amd64_is_imm32 (disp)) {
4007                                 printf ("TYPE: %d\n", patch_info->type);
4008                                 switch (patch_info->type) {
4009                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4010                                         printf ("V: %s\n", patch_info->data.name);
4011                                         break;
4012                                 case MONO_PATCH_INFO_METHOD_JUMP:
4013                                 case MONO_PATCH_INFO_METHOD:
4014                                         printf ("V: %s\n", patch_info->data.method->name);
4015                                         break;
4016                                 default:
4017                                         break;
4018                                 }
4019                         }
4020                 }
4021
4022                 amd64_patch (ip, (gpointer)target);
4023         }
4024 }
4025
4026 guint8 *
4027 mono_arch_emit_prolog (MonoCompile *cfg)
4028 {
4029         MonoMethod *method = cfg->method;
4030         MonoBasicBlock *bb;
4031         MonoMethodSignature *sig;
4032         MonoInst *inst;
4033         int alloc_size, pos, max_offset, i, quad;
4034         guint8 *code;
4035         CallInfo *cinfo;
4036         gint32 lmf_offset = cfg->arch.lmf_offset;
4037
4038         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4039         code = cfg->native_code = g_malloc (cfg->code_size);
4040
4041         /* Amount of stack space allocated by register saving code */
4042         pos = 0;
4043
4044         /*
4045          * The prolog consists of the following parts:
4046          * FP present:
4047          * - push rbp, mov rbp, rsp
4048          * - save callee saved regs using pushes
4049          * - allocate frame
4050          * - save lmf if needed
4051          * FP not present:
4052          * - allocate frame
4053          * - save lmf if needed
4054          * - save callee saved regs using moves
4055          */
4056
4057         if (!cfg->arch.omit_fp) {
4058                 amd64_push_reg (code, AMD64_RBP);
4059                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4060         }
4061
4062         /* Save callee saved registers */
4063         if (!cfg->arch.omit_fp && !method->save_lmf) {
4064                 for (i = 0; i < AMD64_NREG; ++i)
4065                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4066                                 amd64_push_reg (code, i);
4067                                 pos += sizeof (gpointer);
4068                         }
4069         }
4070
4071         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4072
4073         alloc_size -= pos;
4074
4075         if (cfg->arch.omit_fp)
4076                 /*
4077                  * On enter, the stack is misaligned by the the pushing of the return
4078                  * address. It is either made aligned by the pushing of %rbp, or by
4079                  * this.
4080                  */
4081                 alloc_size += 8;
4082
4083         cfg->arch.stack_alloc_size = alloc_size;
4084
4085         /* Allocate stack frame */
4086         if (alloc_size) {
4087                 /* See mono_emit_stack_alloc */
4088 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4089                 guint32 remaining_size = alloc_size;
4090                 while (remaining_size >= 0x1000) {
4091                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4092                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4093                         remaining_size -= 0x1000;
4094                 }
4095                 if (remaining_size)
4096                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4097 #else
4098                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4099 #endif
4100         }
4101
4102         /* Stack alignment check */
4103 #if 0
4104         {
4105                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4106                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4107                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4108                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4109                 amd64_breakpoint (code);
4110         }
4111 #endif
4112
4113         /* Save LMF */
4114         if (method->save_lmf) {
4115                 /* Save ip */
4116                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4117                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4118                 /* Save fp */
4119                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4120                 /* Save sp */
4121                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4122                 /* Save method */
4123                 /* FIXME: add a relocation for this */
4124                 if (IS_IMM32 (cfg->method))
4125                         amd64_mov_membase_imm (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), (guint64)cfg->method, 8);
4126                 else {
4127                         amd64_mov_reg_imm (code, AMD64_R11, cfg->method);
4128                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), AMD64_R11, 8);
4129                 }
4130                 /* Save callee saved regs */
4131                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4132                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4133                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4134                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4135                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4136         }
4137
4138         /* Save callee saved registers */
4139         if (cfg->arch.omit_fp && !method->save_lmf) {
4140                 gint32 save_area_offset = 0;
4141
4142                 /* Save caller saved registers after sp is adjusted */
4143                 /* The registers are saved at the bottom of the frame */
4144                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4145                 for (i = 0; i < AMD64_NREG; ++i)
4146                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4147                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4148                                 save_area_offset += 8;
4149                         }
4150         }
4151
4152         /* compute max_offset in order to use short forward jumps */
4153         max_offset = 0;
4154         if (cfg->opt & MONO_OPT_BRANCH) {
4155                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4156                         MonoInst *ins = bb->code;
4157                         bb->max_offset = max_offset;
4158
4159                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4160                                 max_offset += 6;
4161                         /* max alignment for loops */
4162                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4163                                 max_offset += LOOP_ALIGNMENT;
4164
4165                         while (ins) {
4166                                 if (ins->opcode == OP_LABEL)
4167                                         ins->inst_c1 = max_offset;
4168
4169                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
4170                                 ins = ins->next;
4171                         }
4172                 }
4173         }
4174
4175         sig = mono_method_signature (method);
4176         pos = 0;
4177
4178         cinfo = get_call_info (sig, FALSE);
4179
4180         if (sig->ret->type != MONO_TYPE_VOID) {
4181                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4182                         /* Save volatile arguments to the stack */
4183                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4184                 }
4185         }
4186
4187         /* Keep this in sync with emit_load_volatile_arguments */
4188         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4189                 ArgInfo *ainfo = cinfo->args + i;
4190                 gint32 stack_offset;
4191                 MonoType *arg_type;
4192                 inst = cfg->varinfo [i];
4193
4194                 if (sig->hasthis && (i == 0))
4195                         arg_type = &mono_defaults.object_class->byval_arg;
4196                 else
4197                         arg_type = sig->params [i - sig->hasthis];
4198
4199                 stack_offset = ainfo->offset + ARGS_OFFSET;
4200
4201                 /* Save volatile arguments to the stack */
4202                 if (inst->opcode != OP_REGVAR) {
4203                         switch (ainfo->storage) {
4204                         case ArgInIReg: {
4205                                 guint32 size = 8;
4206
4207                                 /* FIXME: I1 etc */
4208                                 /*
4209                                 if (stack_offset & 0x1)
4210                                         size = 1;
4211                                 else if (stack_offset & 0x2)
4212                                         size = 2;
4213                                 else if (stack_offset & 0x4)
4214                                         size = 4;
4215                                 else
4216                                         size = 8;
4217                                 */
4218                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4219                                 break;
4220                         }
4221                         case ArgInFloatSSEReg:
4222                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4223                                 break;
4224                         case ArgInDoubleSSEReg:
4225                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4226                                 break;
4227                         case ArgValuetypeInReg:
4228                                 for (quad = 0; quad < 2; quad ++) {
4229                                         switch (ainfo->pair_storage [quad]) {
4230                                         case ArgInIReg:
4231                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4232                                                 break;
4233                                         case ArgInFloatSSEReg:
4234                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4235                                                 break;
4236                                         case ArgInDoubleSSEReg:
4237                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4238                                                 break;
4239                                         case ArgNone:
4240                                                 break;
4241                                         default:
4242                                                 g_assert_not_reached ();
4243                                         }
4244                                 }
4245                                 break;
4246                         default:
4247                                 break;
4248                         }
4249                 }
4250
4251                 if (inst->opcode == OP_REGVAR) {
4252                         /* Argument allocated to (non-volatile) register */
4253                         switch (ainfo->storage) {
4254                         case ArgInIReg:
4255                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4256                                 break;
4257                         case ArgOnStack:
4258                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4259                                 break;
4260                         default:
4261                                 g_assert_not_reached ();
4262                         }
4263                 }
4264         }
4265
4266         /* Might need to attach the thread to the JIT */
4267         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4268                 guint64 domain = (guint64)cfg->domain;
4269
4270                 /*
4271                  * The call might clobber argument registers, but they are already
4272                  * saved to the stack/global regs.
4273                  */
4274                 if (lmf_tls_offset != -1) {
4275                         guint8 *buf;
4276
4277                         code = emit_tls_get ( code, AMD64_RAX, lmf_tls_offset);
4278                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4279                         buf = code;
4280                         x86_branch8 (code, X86_CC_NE, 0, 0);
4281                         if ((domain >> 32) == 0)
4282                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4283                         else
4284                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4285                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4286                         amd64_patch (buf, code);
4287                 } else {
4288                         g_assert (!cfg->compile_aot);
4289                         if ((domain >> 32) == 0)
4290                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4291                         else
4292                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4293                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4294                 }
4295         }
4296
4297         if (method->save_lmf) {
4298                 if (lmf_tls_offset != -1) {
4299                         /* Load lmf quicky using the FS register */
4300                         code = emit_tls_get (code, AMD64_RAX, lmf_tls_offset);
4301                 }
4302                 else {
4303                         /*
4304                          * The call might clobber argument registers, but they are already
4305                          * saved to the stack/global regs.
4306                          */
4307
4308                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4309                                                                  (gpointer)"mono_get_lmf_addr");
4310                 }
4311
4312                 /* Save lmf_addr */
4313                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4314                 /* Save previous_lmf */
4315                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4316                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4317                 /* Set new lmf */
4318                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4319                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4320         }
4321
4322
4323         g_free (cinfo);
4324
4325         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4326                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4327
4328         cfg->code_len = code - cfg->native_code;
4329
4330         g_assert (cfg->code_len < cfg->code_size);
4331
4332         return code;
4333 }
4334
4335 void
4336 mono_arch_emit_epilog (MonoCompile *cfg)
4337 {
4338         MonoMethod *method = cfg->method;
4339         int quad, pos, i;
4340         guint8 *code;
4341         int max_epilog_size = 16;
4342         CallInfo *cinfo;
4343         gint32 lmf_offset = cfg->arch.lmf_offset;
4344
4345         if (cfg->method->save_lmf)
4346                 max_epilog_size += 256;
4347
4348         if (mono_jit_trace_calls != NULL)
4349                 max_epilog_size += 50;
4350
4351         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4352                 max_epilog_size += 50;
4353
4354         max_epilog_size += (AMD64_NREG * 2);
4355
4356         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4357                 cfg->code_size *= 2;
4358                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4359                 mono_jit_stats.code_reallocs++;
4360         }
4361
4362         code = cfg->native_code + cfg->code_len;
4363
4364         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4365                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4366
4367         /* the code restoring the registers must be kept in sync with CEE_JMP */
4368         pos = 0;
4369
4370         if (method->save_lmf) {
4371                 /* Restore previous lmf */
4372                 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4373                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4374                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4375
4376                 /* Restore caller saved regs */
4377                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4378                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4379                 }
4380                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4381                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4382                 }
4383                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4384                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4385                 }
4386                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4387                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4388                 }
4389                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4390                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4391                 }
4392                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4393                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4394                 }
4395         } else {
4396
4397                 if (cfg->arch.omit_fp) {
4398                         gint32 save_area_offset = 0;
4399
4400                         for (i = 0; i < AMD64_NREG; ++i)
4401                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4402                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4403                                         save_area_offset += 8;
4404                                 }
4405                 }
4406                 else {
4407                         for (i = 0; i < AMD64_NREG; ++i)
4408                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4409                                         pos -= sizeof (gpointer);
4410
4411                         if (pos) {
4412                                 if (pos == - sizeof (gpointer)) {
4413                                         /* Only one register, so avoid lea */
4414                                         for (i = AMD64_NREG - 1; i > 0; --i)
4415                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4416                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4417                                                 }
4418                                 }
4419                                 else {
4420                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4421
4422                                         /* Pop registers in reverse order */
4423                                         for (i = AMD64_NREG - 1; i > 0; --i)
4424                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4425                                                         amd64_pop_reg (code, i);
4426                                                 }
4427                                 }
4428                         }
4429                 }
4430         }
4431
4432         /* Load returned vtypes into registers if needed */
4433         cinfo = get_call_info (mono_method_signature (method), FALSE);
4434         if (cinfo->ret.storage == ArgValuetypeInReg) {
4435                 ArgInfo *ainfo = &cinfo->ret;
4436                 MonoInst *inst = cfg->ret;
4437
4438                 for (quad = 0; quad < 2; quad ++) {
4439                         switch (ainfo->pair_storage [quad]) {
4440                         case ArgInIReg:
4441                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4442                                 break;
4443                         case ArgInFloatSSEReg:
4444                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4445                                 break;
4446                         case ArgInDoubleSSEReg:
4447                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4448                                 break;
4449                         case ArgNone:
4450                                 break;
4451                         default:
4452                                 g_assert_not_reached ();
4453                         }
4454                 }
4455         }
4456         g_free (cinfo);
4457
4458         if (cfg->arch.omit_fp) {
4459                 if (cfg->arch.stack_alloc_size)
4460                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4461         } else {
4462                 amd64_leave (code);
4463         }
4464         amd64_ret (code);
4465
4466         cfg->code_len = code - cfg->native_code;
4467
4468         g_assert (cfg->code_len < cfg->code_size);
4469
4470         if (cfg->arch.omit_fp) {
4471                 /*
4472                  * Encode the stack size into used_int_regs so the exception handler
4473                  * can access it.
4474                  */
4475                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4476                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4477         }
4478 }
4479
4480 void
4481 mono_arch_emit_exceptions (MonoCompile *cfg)
4482 {
4483         MonoJumpInfo *patch_info;
4484         int nthrows, i;
4485         guint8 *code;
4486         MonoClass *exc_classes [16];
4487         guint8 *exc_throw_start [16], *exc_throw_end [16];
4488         guint32 code_size = 0;
4489
4490         /* Compute needed space */
4491         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4492                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4493                         code_size += 40;
4494                 if (patch_info->type == MONO_PATCH_INFO_R8)
4495                         code_size += 8 + 15; /* sizeof (double) + alignment */
4496                 if (patch_info->type == MONO_PATCH_INFO_R4)
4497                         code_size += 4 + 15; /* sizeof (float) + alignment */
4498         }
4499
4500         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4501                 cfg->code_size *= 2;
4502                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4503                 mono_jit_stats.code_reallocs++;
4504         }
4505
4506         code = cfg->native_code + cfg->code_len;
4507
4508         /* add code to raise exceptions */
4509         nthrows = 0;
4510         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4511                 switch (patch_info->type) {
4512                 case MONO_PATCH_INFO_EXC: {
4513                         MonoClass *exc_class;
4514                         guint8 *buf, *buf2;
4515                         guint32 throw_ip;
4516
4517                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4518
4519                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4520                         g_assert (exc_class);
4521                         throw_ip = patch_info->ip.i;
4522
4523                         //x86_breakpoint (code);
4524                         /* Find a throw sequence for the same exception class */
4525                         for (i = 0; i < nthrows; ++i)
4526                                 if (exc_classes [i] == exc_class)
4527                                         break;
4528                         if (i < nthrows) {
4529                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4530                                 x86_jump_code (code, exc_throw_start [i]);
4531                                 patch_info->type = MONO_PATCH_INFO_NONE;
4532                         }
4533                         else {
4534                                 buf = code;
4535                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4536                                 buf2 = code;
4537
4538                                 if (nthrows < 16) {
4539                                         exc_classes [nthrows] = exc_class;
4540                                         exc_throw_start [nthrows] = code;
4541                                 }
4542
4543                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4544                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4545                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4546                                 patch_info->ip.i = code - cfg->native_code;
4547
4548                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4549
4550                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4551                                 while (buf < buf2)
4552                                         x86_nop (buf);
4553
4554                                 if (nthrows < 16) {
4555                                         exc_throw_end [nthrows] = code;
4556                                         nthrows ++;
4557                                 }
4558                         }
4559                         break;
4560                 }
4561                 default:
4562                         /* do nothing */
4563                         break;
4564                 }
4565         }
4566
4567         /* Handle relocations with RIP relative addressing */
4568         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4569                 gboolean remove = FALSE;
4570
4571                 switch (patch_info->type) {
4572                 case MONO_PATCH_INFO_R8:
4573                 case MONO_PATCH_INFO_R4: {
4574                         guint8 *pos;
4575
4576                         if (use_sse2) {
4577                                 /* The SSE opcodes require a 16 byte alignment */
4578                                 code = (guint8*)ALIGN_TO (code, 16);
4579                         } else {
4580                                 code = (guint8*)ALIGN_TO (code, 8);
4581                         }
4582
4583                         pos = cfg->native_code + patch_info->ip.i;
4584
4585                         if (use_sse2)
4586                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4587                         else
4588                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4589
4590                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4591                                 *(double*)code = *(double*)patch_info->data.target;
4592                                 code += sizeof (double);
4593                         } else {
4594                                 *(float*)code = *(float*)patch_info->data.target;
4595                                 code += sizeof (float);
4596                         }
4597
4598                         remove = TRUE;
4599                         break;
4600                 }
4601                 default:
4602                         break;
4603                 }
4604
4605                 if (remove) {
4606                         if (patch_info == cfg->patch_info)
4607                                 cfg->patch_info = patch_info->next;
4608                         else {
4609                                 MonoJumpInfo *tmp;
4610
4611                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4612                                         ;
4613                                 tmp->next = patch_info->next;
4614                         }
4615                 }
4616         }
4617
4618         cfg->code_len = code - cfg->native_code;
4619
4620         g_assert (cfg->code_len < cfg->code_size);
4621
4622 }
4623
4624 void*
4625 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4626 {
4627         guchar *code = p;
4628         CallInfo *cinfo = NULL;
4629         MonoMethodSignature *sig;
4630         MonoInst *inst;
4631         int i, n, stack_area = 0;
4632
4633         /* Keep this in sync with mono_arch_get_argument_info */
4634
4635         if (enable_arguments) {
4636                 /* Allocate a new area on the stack and save arguments there */
4637                 sig = mono_method_signature (cfg->method);
4638
4639                 cinfo = get_call_info (sig, FALSE);
4640
4641                 n = sig->param_count + sig->hasthis;
4642
4643                 stack_area = ALIGN_TO (n * 8, 16);
4644
4645                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4646
4647                 for (i = 0; i < n; ++i) {
4648                         inst = cfg->varinfo [i];
4649
4650                         if (inst->opcode == OP_REGVAR)
4651                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4652                         else {
4653                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4654                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4655                         }
4656                 }
4657         }
4658
4659         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4660         amd64_set_reg_template (code, AMD64_RDI);
4661         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4662         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4663
4664         if (enable_arguments) {
4665                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4666
4667                 g_free (cinfo);
4668         }
4669
4670         return code;
4671 }
4672
4673 enum {
4674         SAVE_NONE,
4675         SAVE_STRUCT,
4676         SAVE_EAX,
4677         SAVE_EAX_EDX,
4678         SAVE_XMM
4679 };
4680
4681 void*
4682 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4683 {
4684         guchar *code = p;
4685         int save_mode = SAVE_NONE;
4686         MonoMethod *method = cfg->method;
4687         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4688
4689         switch (rtype) {
4690         case MONO_TYPE_VOID:
4691                 /* special case string .ctor icall */
4692                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4693                         save_mode = SAVE_EAX;
4694                 else
4695                         save_mode = SAVE_NONE;
4696                 break;
4697         case MONO_TYPE_I8:
4698         case MONO_TYPE_U8:
4699                 save_mode = SAVE_EAX;
4700                 break;
4701         case MONO_TYPE_R4:
4702         case MONO_TYPE_R8:
4703                 save_mode = SAVE_XMM;
4704                 break;
4705         case MONO_TYPE_GENERICINST:
4706                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4707                         save_mode = SAVE_EAX;
4708                         break;
4709                 }
4710                 /* Fall through */
4711         case MONO_TYPE_VALUETYPE:
4712                 save_mode = SAVE_STRUCT;
4713                 break;
4714         default:
4715                 save_mode = SAVE_EAX;
4716                 break;
4717         }
4718
4719         /* Save the result and copy it into the proper argument register */
4720         switch (save_mode) {
4721         case SAVE_EAX:
4722                 amd64_push_reg (code, AMD64_RAX);
4723                 /* Align stack */
4724                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4725                 if (enable_arguments)
4726                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4727                 break;
4728         case SAVE_STRUCT:
4729                 /* FIXME: */
4730                 if (enable_arguments)
4731                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4732                 break;
4733         case SAVE_XMM:
4734                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4735                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4736                 /* Align stack */
4737                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4738                 /*
4739                  * The result is already in the proper argument register so no copying
4740                  * needed.
4741                  */
4742                 break;
4743         case SAVE_NONE:
4744                 break;
4745         default:
4746                 g_assert_not_reached ();
4747         }
4748
4749         /* Set %al since this is a varargs call */
4750         if (save_mode == SAVE_XMM)
4751                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4752         else
4753                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4754
4755         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4756         amd64_set_reg_template (code, AMD64_RDI);
4757         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4758
4759         /* Restore result */
4760         switch (save_mode) {
4761         case SAVE_EAX:
4762                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4763                 amd64_pop_reg (code, AMD64_RAX);
4764                 break;
4765         case SAVE_STRUCT:
4766                 /* FIXME: */
4767                 break;
4768         case SAVE_XMM:
4769                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4770                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4771                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4772                 break;
4773         case SAVE_NONE:
4774                 break;
4775         default:
4776                 g_assert_not_reached ();
4777         }
4778
4779         return code;
4780 }
4781
4782 void
4783 mono_arch_flush_icache (guint8 *code, gint size)
4784 {
4785         /* Not needed */
4786 }
4787
4788 void
4789 mono_arch_flush_register_windows (void)
4790 {
4791 }
4792
4793 gboolean
4794 mono_arch_is_inst_imm (gint64 imm)
4795 {
4796         return amd64_is_imm32 (imm);
4797 }
4798
4799 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4800
4801 /*
4802  * Determine whenever the trap whose info is in SIGINFO is caused by
4803  * integer overflow.
4804  */
4805 gboolean
4806 mono_arch_is_int_overflow (void *sigctx, void *info)
4807 {
4808         MonoContext ctx;
4809         guint8* rip;
4810         int reg;
4811         gint64 value;
4812
4813         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4814
4815         rip = (guint8*)ctx.rip;
4816
4817         if (IS_REX (rip [0])) {
4818                 reg = amd64_rex_b (rip [0]);
4819                 rip ++;
4820         }
4821         else
4822                 reg = 0;
4823
4824         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4825                 /* idiv REG */
4826                 reg += x86_modrm_rm (rip [1]);
4827
4828                 switch (reg) {
4829                 case AMD64_RAX:
4830                         value = ctx.rax;
4831                         break;
4832                 case AMD64_RBX:
4833                         value = ctx.rbx;
4834                         break;
4835                 case AMD64_RCX:
4836                         value = ctx.rcx;
4837                         break;
4838                 case AMD64_RDX:
4839                         value = ctx.rdx;
4840                         break;
4841                 case AMD64_RBP:
4842                         value = ctx.rbp;
4843                         break;
4844                 case AMD64_RSP:
4845                         value = ctx.rsp;
4846                         break;
4847                 case AMD64_RSI:
4848                         value = ctx.rsi;
4849                         break;
4850                 case AMD64_RDI:
4851                         value = ctx.rdi;
4852                         break;
4853                 case AMD64_R12:
4854                         value = ctx.r12;
4855                         break;
4856                 case AMD64_R13:
4857                         value = ctx.r13;
4858                         break;
4859                 case AMD64_R14:
4860                         value = ctx.r14;
4861                         break;
4862                 case AMD64_R15:
4863                         value = ctx.r15;
4864                         break;
4865                 default:
4866                         g_assert_not_reached ();
4867                         reg = -1;
4868                 }
4869
4870                 if (value == -1)
4871                         return TRUE;
4872         }
4873
4874         return FALSE;
4875 }
4876
4877 guint32
4878 mono_arch_get_patch_offset (guint8 *code)
4879 {
4880         return 3;
4881 }
4882
4883 gpointer*
4884 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4885 {
4886         guint32 reg;
4887         guint32 disp;
4888         guint8 rex = 0;
4889
4890         /* go to the start of the call instruction
4891          *
4892          * address_byte = (m << 6) | (o << 3) | reg
4893          * call opcode: 0xff address_byte displacement
4894          * 0xff m=1,o=2 imm8
4895          * 0xff m=2,o=2 imm32
4896          */
4897         code -= 7;
4898
4899         /*
4900          * A given byte sequence can match more than case here, so we have to be
4901          * really careful about the ordering of the cases. Longer sequences
4902          * come first.
4903          */
4904         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4905                         /*
4906                          * This is a interface call
4907                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4908                          * ff 10                  callq  *(%rax)
4909                          */
4910                 if (IS_REX (code [4]))
4911                         rex = code [4];
4912                 reg = amd64_modrm_rm (code [6]);
4913                 disp = 0;
4914         }
4915         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4916                 /* call OFFSET(%rip) */
4917                 disp = *(guint32*)(code + 3);
4918                 return (gpointer*)(code + disp + 7);
4919         }
4920         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4921                 /* call *[reg+disp32] */
4922                 if (IS_REX (code [0]))
4923                         rex = code [0];
4924                 reg = amd64_modrm_rm (code [2]);
4925                 disp = *(guint32*)(code + 3);
4926                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4927         }
4928         else if (code [2] == 0xe8) {
4929                 /* call <ADDR> */
4930                 return NULL;
4931         }
4932         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4933                 /* call *%reg */
4934                 return NULL;
4935         }
4936         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4937                 /* call *[reg+disp8] */
4938                 if (IS_REX (code [3]))
4939                         rex = code [3];
4940                 reg = amd64_modrm_rm (code [5]);
4941                 disp = *(guint8*)(code + 6);
4942                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4943         }
4944         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4945                         /*
4946                          * This is a interface call: should check the above code can't catch it earlier
4947                          * 8b 40 30   mov    0x30(%eax),%eax
4948                          * ff 10      call   *(%eax)
4949                          */
4950                 if (IS_REX (code [4]))
4951                         rex = code [4];
4952                 reg = amd64_modrm_rm (code [6]);
4953                 disp = 0;
4954         }
4955         else
4956                 g_assert_not_reached ();
4957
4958         reg += amd64_rex_b (rex);
4959
4960         /* R11 is clobbered by the trampoline code */
4961         g_assert (reg != AMD64_R11);
4962
4963         return (gpointer)(((guint64)(regs [reg])) + disp);
4964 }
4965
4966 gpointer*
4967 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4968 {
4969         guint32 reg;
4970         guint32 disp;
4971
4972         code -= 10;
4973
4974         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
4975                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
4976                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
4977                 disp = code [6];
4978
4979                 if (reg == AMD64_RAX)
4980                         return NULL;
4981                 else
4982                         return (gpointer*)(((guint64)(regs [reg])) + disp);
4983         }
4984
4985         return NULL;
4986 }
4987
4988 /*
4989  * Support for fast access to the thread-local lmf structure using the GS
4990  * segment register on NPTL + kernel 2.6.x.
4991  */
4992
4993 static gboolean tls_offset_inited = FALSE;
4994
4995 void
4996 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4997 {
4998         if (!tls_offset_inited) {
4999                 tls_offset_inited = TRUE;
5000 #ifdef MONO_XEN_OPT
5001                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5002 #endif
5003                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5004                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5005                 thread_tls_offset = mono_thread_get_tls_offset ();
5006         }
5007 }
5008
5009 void
5010 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5011 {
5012 }
5013
5014 void
5015 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5016 {
5017         MonoCallInst *call = (MonoCallInst*)inst;
5018         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
5019
5020         if (vt_reg != -1) {
5021                 MonoInst *vtarg;
5022
5023                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5024                         /*
5025                          * The valuetype is in RAX:RDX after the call, need to be copied to
5026                          * the stack. Push the address here, so the call instruction can
5027                          * access it.
5028                          */
5029                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5030                         vtarg->sreg1 = vt_reg;
5031                         mono_bblock_add_inst (cfg->cbb, vtarg);
5032
5033                         /* Align stack */
5034                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5035                 }
5036                 else {
5037                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5038                         vtarg->sreg1 = vt_reg;
5039                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5040                         mono_bblock_add_inst (cfg->cbb, vtarg);
5041
5042                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5043                 }
5044         }
5045
5046         /* add the this argument */
5047         if (this_reg != -1) {
5048                 MonoInst *this;
5049                 MONO_INST_NEW (cfg, this, OP_MOVE);
5050                 this->type = this_type;
5051                 this->sreg1 = this_reg;
5052                 this->dreg = mono_regstate_next_int (cfg->rs);
5053                 mono_bblock_add_inst (cfg->cbb, this);
5054
5055                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5056         }
5057
5058         g_free (cinfo);
5059 }
5060
5061 MonoInst*
5062 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5063 {
5064         MonoInst *ins = NULL;
5065
5066         if (cmethod->klass == mono_defaults.math_class) {
5067                 if (strcmp (cmethod->name, "Sin") == 0) {
5068                         MONO_INST_NEW (cfg, ins, OP_SIN);
5069                         ins->inst_i0 = args [0];
5070                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5071                         MONO_INST_NEW (cfg, ins, OP_COS);
5072                         ins->inst_i0 = args [0];
5073                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5074                         if (use_sse2)
5075                                 return ins;
5076                         MONO_INST_NEW (cfg, ins, OP_TAN);
5077                         ins->inst_i0 = args [0];
5078                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5079                         if (use_sse2)
5080                                 return ins;
5081                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5082                         ins->inst_i0 = args [0];
5083                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5084                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5085                         ins->inst_i0 = args [0];
5086                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5087                         MONO_INST_NEW (cfg, ins, OP_ABS);
5088                         ins->inst_i0 = args [0];
5089                 }
5090 #if 0
5091                 /* OP_FREM is not IEEE compatible */
5092                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5093                         MONO_INST_NEW (cfg, ins, OP_FREM);
5094                         ins->inst_i0 = args [0];
5095                         ins->inst_i1 = args [1];
5096                 }
5097 #endif
5098         } else if (cmethod->klass == mono_defaults.thread_class &&
5099                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
5100                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
5101         } else if(cmethod->klass->image == mono_defaults.corlib &&
5102                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5103                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5104
5105                 if (strcmp (cmethod->name, "Increment") == 0) {
5106                         MonoInst *ins_iconst;
5107                         guint32 opcode;
5108
5109                         if (fsig->params [0]->type == MONO_TYPE_I4)
5110                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5111                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5112                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5113                         else
5114                                 g_assert_not_reached ();
5115                         MONO_INST_NEW (cfg, ins, opcode);
5116                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5117                         ins_iconst->inst_c0 = 1;
5118
5119                         ins->inst_i0 = args [0];
5120                         ins->inst_i1 = ins_iconst;
5121                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5122                         MonoInst *ins_iconst;
5123                         guint32 opcode;
5124
5125                         if (fsig->params [0]->type == MONO_TYPE_I4)
5126                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5127                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5128                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5129                         else
5130                                 g_assert_not_reached ();
5131                         MONO_INST_NEW (cfg, ins, opcode);
5132                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5133                         ins_iconst->inst_c0 = -1;
5134
5135                         ins->inst_i0 = args [0];
5136                         ins->inst_i1 = ins_iconst;
5137                 } else if (strcmp (cmethod->name, "Add") == 0) {
5138                         guint32 opcode;
5139
5140                         if (fsig->params [0]->type == MONO_TYPE_I4)
5141                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5142                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5143                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5144                         else
5145                                 g_assert_not_reached ();
5146
5147                         MONO_INST_NEW (cfg, ins, opcode);
5148
5149                         ins->inst_i0 = args [0];
5150                         ins->inst_i1 = args [1];
5151                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5152                         guint32 opcode;
5153
5154                         if (fsig->params [0]->type == MONO_TYPE_I4)
5155                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5156                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5157                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5158                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5159                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5160                         else
5161                                 return NULL;
5162
5163                         MONO_INST_NEW (cfg, ins, opcode);
5164
5165                         ins->inst_i0 = args [0];
5166                         ins->inst_i1 = args [1];
5167                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5168                         /* 64 bit reads are already atomic */
5169                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5170                         ins->inst_i0 = args [0];
5171                 }
5172
5173                 /*
5174                  * Can't implement CompareExchange methods this way since they have
5175                  * three arguments.
5176                  */
5177         }
5178
5179         return ins;
5180 }
5181
5182 gboolean
5183 mono_arch_print_tree (MonoInst *tree, int arity)
5184 {
5185         return 0;
5186 }
5187
5188 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5189 {
5190         MonoInst* ins;
5191
5192         if (appdomain_tls_offset == -1)
5193                 return NULL;
5194
5195         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5196         ins->inst_offset = appdomain_tls_offset;
5197         return ins;
5198 }
5199
5200 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5201 {
5202         MonoInst* ins;
5203
5204         if (thread_tls_offset == -1)
5205                 return NULL;
5206
5207         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5208         ins->inst_offset = thread_tls_offset;
5209         return ins;
5210 }