mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint lmf_addr_tls_offset = -1;
  32 static gint appdomain_tls_offset = -1;
  33 static gint thread_tls_offset = -1;
  34
  35 #ifdef MONO_XEN_OPT
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  44
  45 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  46
  47 #ifdef PLATFORM_WIN32
  48 /* Under windows, the default pinvoke calling convention is stdcall */
  49 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  50 #else
  51 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  52 #endif
  53
  54 #define ARGS_OFFSET 16
  55 #define GP_SCRATCH_REG AMD64_R11
  56
  57 /*
  58  * AMD64 register usage:
  59  * - callee saved registers are used for global register allocation
  60  * - %r11 is used for materializing 64 bit constants in opcodes
  61  * - the rest is used for local allocation
  62  */
  63
  64 /*
  65  * Floating point comparison results:
  66  *                  ZF PF CF
  67  * A > B            0  0  0
  68  * A < B            0  0  1
  69  * A = B            1  0  0
  70  * A > B            0  0  0
  71  * UNORDERED        1  1  1
  72  */
  73
  74 #define NOT_IMPLEMENTED g_assert_not_reached ()
  75
  76 const char*
  77 mono_arch_regname (int reg) {
  78         switch (reg) {
  79         case AMD64_RAX: return "%rax";
  80         case AMD64_RBX: return "%rbx";
  81         case AMD64_RCX: return "%rcx";
  82         case AMD64_RDX: return "%rdx";
  83         case AMD64_RSP: return "%rsp";
  84         case AMD64_RBP: return "%rbp";
  85         case AMD64_RDI: return "%rdi";
  86         case AMD64_RSI: return "%rsi";
  87         case AMD64_R8: return "%r8";
  88         case AMD64_R9: return "%r9";
  89         case AMD64_R10: return "%r10";
  90         case AMD64_R11: return "%r11";
  91         case AMD64_R12: return "%r12";
  92         case AMD64_R13: return "%r13";
  93         case AMD64_R14: return "%r14";
  94         case AMD64_R15: return "%r15";
  95         }
  96         return "unknown";
  97 }
  98
  99 static const char * xmmregs [] = {
 100         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 101         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < AMD64_XMM_NREG)
 108                 return xmmregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 G_GNUC_UNUSED static void
 114 break_count (void)
 115 {
 116 }
 117
 118 G_GNUC_UNUSED static gboolean
 119 debug_count (void)
 120 {
 121         static int count = 0;
 122         count ++;
 123
 124         if (!getenv ("COUNT"))
 125                 return TRUE;
 126
 127         if (count == atoi (getenv ("COUNT"))) {
 128                 break_count ();
 129         }
 130
 131         if (count > atoi (getenv ("COUNT"))) {
 132                 return FALSE;
 133         }
 134
 135         return TRUE;
 136 }
 137
 138 static gboolean
 139 debug_omit_fp (void)
 140 {
 141 #if 0
 142         return debug_count ();
 143 #else
 144         return TRUE;
 145 #endif
 146 }
 147
 148 static inline gboolean
 149 amd64_is_near_call (guint8 *code)
 150 {
 151         /* Skip REX */
 152         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 153                 code += 1;
 154
 155         return code [0] == 0xe8;
 156 }
 157
 158 static inline void
 159 amd64_patch (unsigned char* code, gpointer target)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         if ((code [0] & 0xf8) == 0xb8) {
 166                 /* amd64_set_reg_template */
 167                 *(guint64*)(code + 1) = (guint64)target;
 168         }
 169         else if (code [0] == 0x8b) {
 170                 /* mov 0(%rip), %dreg */
 171                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 172         }
 173         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 174                 /* call *<OFFSET>(%rip) */
 175                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 176         }
 177         else if ((code [0] == 0xe8)) {
 178                 /* call <DISP> */
 179                 gint64 disp = (guint8*)target - (guint8*)code;
 180                 g_assert (amd64_is_imm32 (disp));
 181                 x86_patch (code, (unsigned char*)target);
 182         }
 183         else
 184                 x86_patch (code, (unsigned char*)target);
 185 }
 186
 187 typedef enum {
 188         ArgInIReg,
 189         ArgInFloatSSEReg,
 190         ArgInDoubleSSEReg,
 191         ArgOnStack,
 192         ArgValuetypeInReg,
 193         ArgNone /* only in pair_storage */
 194 } ArgStorage;
 195
 196 typedef struct {
 197         gint16 offset;
 198         gint8  reg;
 199         ArgStorage storage;
 200
 201         /* Only if storage == ArgValuetypeInReg */
 202         ArgStorage pair_storage [2];
 203         gint8 pair_regs [2];
 204 } ArgInfo;
 205
 206 typedef struct {
 207         int nargs;
 208         guint32 stack_usage;
 209         guint32 reg_usage;
 210         guint32 freg_usage;
 211         gboolean need_stack_align;
 212         ArgInfo ret;
 213         ArgInfo sig_cookie;
 214         ArgInfo args [1];
 215 } CallInfo;
 216
 217 #define DEBUG(a) if (cfg->verbose_level > 1) a
 218
 219 #define NEW_ICONST(cfg,dest,val) do {   \
 220                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 221                 (dest)->opcode = OP_ICONST;     \
 222                 (dest)->inst_c0 = (val);        \
 223                 (dest)->type = STACK_I4;        \
 224         } while (0)
 225
 226 #define PARAM_REGS 6
 227
 228 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 229
 230 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 231
 232 static void inline
 233 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 234 {
 235     ainfo->offset = *stack_size;
 236
 237     if (*gr >= PARAM_REGS) {
 238                 ainfo->storage = ArgOnStack;
 239                 (*stack_size) += sizeof (gpointer);
 240     }
 241     else {
 242                 ainfo->storage = ArgInIReg;
 243                 ainfo->reg = param_regs [*gr];
 244                 (*gr) ++;
 245     }
 246 }
 247
 248 #define FLOAT_PARAM_REGS 8
 249
 250 static void inline
 251 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 252 {
 253     ainfo->offset = *stack_size;
 254
 255     if (*gr >= FLOAT_PARAM_REGS) {
 256                 ainfo->storage = ArgOnStack;
 257                 (*stack_size) += sizeof (gpointer);
 258     }
 259     else {
 260                 /* A double register */
 261                 if (is_double)
 262                         ainfo->storage = ArgInDoubleSSEReg;
 263                 else
 264                         ainfo->storage = ArgInFloatSSEReg;
 265                 ainfo->reg = *gr;
 266                 (*gr) += 1;
 267     }
 268 }
 269
 270 typedef enum ArgumentClass {
 271         ARG_CLASS_NO_CLASS,
 272         ARG_CLASS_MEMORY,
 273         ARG_CLASS_INTEGER,
 274         ARG_CLASS_SSE
 275 } ArgumentClass;
 276
 277 static ArgumentClass
 278 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 279 {
 280         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 281         MonoType *ptype;
 282
 283         ptype = mono_type_get_underlying_type (type);
 284         switch (ptype->type) {
 285         case MONO_TYPE_BOOLEAN:
 286         case MONO_TYPE_CHAR:
 287         case MONO_TYPE_I1:
 288         case MONO_TYPE_U1:
 289         case MONO_TYPE_I2:
 290         case MONO_TYPE_U2:
 291         case MONO_TYPE_I4:
 292         case MONO_TYPE_U4:
 293         case MONO_TYPE_I:
 294         case MONO_TYPE_U:
 295         case MONO_TYPE_STRING:
 296         case MONO_TYPE_OBJECT:
 297         case MONO_TYPE_CLASS:
 298         case MONO_TYPE_SZARRAY:
 299         case MONO_TYPE_PTR:
 300         case MONO_TYPE_FNPTR:
 301         case MONO_TYPE_ARRAY:
 302         case MONO_TYPE_I8:
 303         case MONO_TYPE_U8:
 304                 class2 = ARG_CLASS_INTEGER;
 305                 break;
 306         case MONO_TYPE_R4:
 307         case MONO_TYPE_R8:
 308                 class2 = ARG_CLASS_SSE;
 309                 break;
 310
 311         case MONO_TYPE_TYPEDBYREF:
 312                 g_assert_not_reached ();
 313
 314         case MONO_TYPE_GENERICINST:
 315                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 316                         class2 = ARG_CLASS_INTEGER;
 317                         break;
 318                 }
 319                 /* fall through */
 320         case MONO_TYPE_VALUETYPE: {
 321                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 322                 int i;
 323
 324                 for (i = 0; i < info->num_fields; ++i) {
 325                         class2 = class1;
 326                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 327                 }
 328                 break;
 329         }
 330         default:
 331                 g_assert_not_reached ();
 332         }
 333
 334         /* Merge */
 335         if (class1 == class2)
 336                 ;
 337         else if (class1 == ARG_CLASS_NO_CLASS)
 338                 class1 = class2;
 339         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 340                 class1 = ARG_CLASS_MEMORY;
 341         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 342                 class1 = ARG_CLASS_INTEGER;
 343         else
 344                 class1 = ARG_CLASS_SSE;
 345
 346         return class1;
 347 }
 348
 349 static void
 350 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 351                gboolean is_return,
 352                guint32 *gr, guint32 *fr, guint32 *stack_size)
 353 {
 354         guint32 size, quad, nquads, i;
 355         ArgumentClass args [2];
 356         MonoMarshalType *info;
 357         MonoClass *klass;
 358
 359         klass = mono_class_from_mono_type (type);
 360         if (sig->pinvoke)
 361                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 362         else
 363                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 364
 365         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 366                 /* Allways pass in memory */
 367                 ainfo->offset = *stack_size;
 368                 *stack_size += ALIGN_TO (size, 8);
 369                 ainfo->storage = ArgOnStack;
 370
 371                 return;
 372         }
 373
 374         /* FIXME: Handle structs smaller than 8 bytes */
 375         //if ((size % 8) != 0)
 376         //      NOT_IMPLEMENTED;
 377
 378         if (size > 8)
 379                 nquads = 2;
 380         else
 381                 nquads = 1;
 382
 383         /*
 384          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 385          * The X87 and SSEUP stuff is left out since there are no such types in
 386          * the CLR.
 387          */
 388         info = mono_marshal_load_type_info (klass);
 389         g_assert (info);
 390         if (info->native_size > 16) {
 391                 ainfo->offset = *stack_size;
 392                 *stack_size += ALIGN_TO (info->native_size, 8);
 393                 ainfo->storage = ArgOnStack;
 394
 395                 return;
 396         }
 397
 398         args [0] = ARG_CLASS_NO_CLASS;
 399         args [1] = ARG_CLASS_NO_CLASS;
 400         for (quad = 0; quad < nquads; ++quad) {
 401                 int size;
 402                 guint32 align;
 403                 ArgumentClass class1;
 404
 405                 class1 = ARG_CLASS_NO_CLASS;
 406                 for (i = 0; i < info->num_fields; ++i) {
 407                         size = mono_marshal_type_size (info->fields [i].field->type,
 408                                                                                    info->fields [i].mspec,
 409                                                                                    &align, TRUE, klass->unicode);
 410                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 411                                 /* Unaligned field */
 412                                 NOT_IMPLEMENTED;
 413                         }
 414
 415                         /* Skip fields in other quad */
 416                         if ((quad == 0) && (info->fields [i].offset >= 8))
 417                                 continue;
 418                         if ((quad == 1) && (info->fields [i].offset < 8))
 419                                 continue;
 420
 421                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 422                 }
 423                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 424                 args [quad] = class1;
 425         }
 426
 427         /* Post merger cleanup */
 428         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 429                 args [0] = args [1] = ARG_CLASS_MEMORY;
 430
 431         /* Allocate registers */
 432         {
 433                 int orig_gr = *gr;
 434                 int orig_fr = *fr;
 435
 436                 ainfo->storage = ArgValuetypeInReg;
 437                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 438                 for (quad = 0; quad < nquads; ++quad) {
 439                         switch (args [quad]) {
 440                         case ARG_CLASS_INTEGER:
 441                                 if (*gr >= PARAM_REGS)
 442                                         args [quad] = ARG_CLASS_MEMORY;
 443                                 else {
 444                                         ainfo->pair_storage [quad] = ArgInIReg;
 445                                         if (is_return)
 446                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 447                                         else
 448                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 449                                         (*gr) ++;
 450                                 }
 451                                 break;
 452                         case ARG_CLASS_SSE:
 453                                 if (*fr >= FLOAT_PARAM_REGS)
 454                                         args [quad] = ARG_CLASS_MEMORY;
 455                                 else {
 456                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 457                                         ainfo->pair_regs [quad] = *fr;
 458                                         (*fr) ++;
 459                                 }
 460                                 break;
 461                         case ARG_CLASS_MEMORY:
 462                                 break;
 463                         default:
 464                                 g_assert_not_reached ();
 465                         }
 466                 }
 467
 468                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 469                         /* Revert possible register assignments */
 470                         *gr = orig_gr;
 471                         *fr = orig_fr;
 472
 473                         ainfo->offset = *stack_size;
 474                         *stack_size += ALIGN_TO (info->native_size, 8);
 475                         ainfo->storage = ArgOnStack;
 476                 }
 477         }
 478 }
 479
 480 /*
 481  * get_call_info:
 482  *
 483  *  Obtain information about a call according to the calling convention.
 484  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 485  * Draft Version 0.23" document for more information.
 486  */
 487 static CallInfo*
 488 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 489 {
 490         guint32 i, gr, fr;
 491         MonoType *ret_type;
 492         int n = sig->hasthis + sig->param_count;
 493         guint32 stack_size = 0;
 494         CallInfo *cinfo;
 495
 496         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 497
 498         gr = 0;
 499         fr = 0;
 500
 501         /* return value */
 502         {
 503                 ret_type = mono_type_get_underlying_type (sig->ret);
 504                 switch (ret_type->type) {
 505                 case MONO_TYPE_BOOLEAN:
 506                 case MONO_TYPE_I1:
 507                 case MONO_TYPE_U1:
 508                 case MONO_TYPE_I2:
 509                 case MONO_TYPE_U2:
 510                 case MONO_TYPE_CHAR:
 511                 case MONO_TYPE_I4:
 512                 case MONO_TYPE_U4:
 513                 case MONO_TYPE_I:
 514                 case MONO_TYPE_U:
 515                 case MONO_TYPE_PTR:
 516                 case MONO_TYPE_FNPTR:
 517                 case MONO_TYPE_CLASS:
 518                 case MONO_TYPE_OBJECT:
 519                 case MONO_TYPE_SZARRAY:
 520                 case MONO_TYPE_ARRAY:
 521                 case MONO_TYPE_STRING:
 522                         cinfo->ret.storage = ArgInIReg;
 523                         cinfo->ret.reg = AMD64_RAX;
 524                         break;
 525                 case MONO_TYPE_U8:
 526                 case MONO_TYPE_I8:
 527                         cinfo->ret.storage = ArgInIReg;
 528                         cinfo->ret.reg = AMD64_RAX;
 529                         break;
 530                 case MONO_TYPE_R4:
 531                         cinfo->ret.storage = ArgInFloatSSEReg;
 532                         cinfo->ret.reg = AMD64_XMM0;
 533                         break;
 534                 case MONO_TYPE_R8:
 535                         cinfo->ret.storage = ArgInDoubleSSEReg;
 536                         cinfo->ret.reg = AMD64_XMM0;
 537                         break;
 538                 case MONO_TYPE_GENERICINST:
 539                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 540                                 cinfo->ret.storage = ArgInIReg;
 541                                 cinfo->ret.reg = AMD64_RAX;
 542                                 break;
 543                         }
 544                         /* fall through */
 545                 case MONO_TYPE_VALUETYPE: {
 546                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 547
 548                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 549                         if (cinfo->ret.storage == ArgOnStack)
 550                                 /* The caller passes the address where the value is stored */
 551                                 add_general (&gr, &stack_size, &cinfo->ret);
 552                         break;
 553                 }
 554                 case MONO_TYPE_TYPEDBYREF:
 555                         /* Same as a valuetype with size 24 */
 556                         add_general (&gr, &stack_size, &cinfo->ret);
 557                         ;
 558                         break;
 559                 case MONO_TYPE_VOID:
 560                         break;
 561                 default:
 562                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 563                 }
 564         }
 565
 566         /* this */
 567         if (sig->hasthis)
 568                 add_general (&gr, &stack_size, cinfo->args + 0);
 569
 570         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 571                 gr = PARAM_REGS;
 572                 fr = FLOAT_PARAM_REGS;
 573
 574                 /* Emit the signature cookie just before the implicit arguments */
 575                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 576         }
 577
 578         for (i = 0; i < sig->param_count; ++i) {
 579                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 580                 MonoType *ptype;
 581
 582                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 583                         /* We allways pass the sig cookie on the stack for simplicity */
 584                         /*
 585                          * Prevent implicit arguments + the sig cookie from being passed
 586                          * in registers.
 587                          */
 588                         gr = PARAM_REGS;
 589                         fr = FLOAT_PARAM_REGS;
 590
 591                         /* Emit the signature cookie just before the implicit arguments */
 592                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 593                 }
 594
 595                 if (sig->params [i]->byref) {
 596                         add_general (&gr, &stack_size, ainfo);
 597                         continue;
 598                 }
 599                 ptype = mono_type_get_underlying_type (sig->params [i]);
 600                 switch (ptype->type) {
 601                 case MONO_TYPE_BOOLEAN:
 602                 case MONO_TYPE_I1:
 603                 case MONO_TYPE_U1:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_I2:
 607                 case MONO_TYPE_U2:
 608                 case MONO_TYPE_CHAR:
 609                         add_general (&gr, &stack_size, ainfo);
 610                         break;
 611                 case MONO_TYPE_I4:
 612                 case MONO_TYPE_U4:
 613                         add_general (&gr, &stack_size, ainfo);
 614                         break;
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_STRING:
 622                 case MONO_TYPE_SZARRAY:
 623                 case MONO_TYPE_ARRAY:
 624                         add_general (&gr, &stack_size, ainfo);
 625                         break;
 626                 case MONO_TYPE_GENERICINST:
 627                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 628                                 add_general (&gr, &stack_size, ainfo);
 629                                 break;
 630                         }
 631                         /* fall through */
 632                 case MONO_TYPE_VALUETYPE:
 633                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 634                         break;
 635                 case MONO_TYPE_TYPEDBYREF:
 636                         stack_size += sizeof (MonoTypedRef);
 637                         ainfo->storage = ArgOnStack;
 638                         break;
 639                 case MONO_TYPE_U8:
 640                 case MONO_TYPE_I8:
 641                         add_general (&gr, &stack_size, ainfo);
 642                         break;
 643                 case MONO_TYPE_R4:
 644                         add_float (&fr, &stack_size, ainfo, FALSE);
 645                         break;
 646                 case MONO_TYPE_R8:
 647                         add_float (&fr, &stack_size, ainfo, TRUE);
 648                         break;
 649                 default:
 650                         g_assert_not_reached ();
 651                 }
 652         }
 653
 654         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 655                 gr = PARAM_REGS;
 656                 fr = FLOAT_PARAM_REGS;
 657
 658                 /* Emit the signature cookie just before the implicit arguments */
 659                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 660         }
 661
 662         if (stack_size & 0x8) {
 663                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 664                 cinfo->need_stack_align = TRUE;
 665                 stack_size += 8;
 666         }
 667
 668         cinfo->stack_usage = stack_size;
 669         cinfo->reg_usage = gr;
 670         cinfo->freg_usage = fr;
 671         return cinfo;
 672 }
 673
 674 /*
 675  * mono_arch_get_argument_info:
 676  * @csig:  a method signature
 677  * @param_count: the number of parameters to consider
 678  * @arg_info: an array to store the result infos
 679  *
 680  * Gathers information on parameters such as size, alignment and
 681  * padding. arg_info should be large enought to hold param_count + 1 entries.
 682  *
 683  * Returns the size of the argument area on the stack.
 684  */
 685 int
 686 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 687 {
 688         int k;
 689         CallInfo *cinfo = get_call_info (csig, FALSE);
 690         guint32 args_size = cinfo->stack_usage;
 691
 692         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 693         if (csig->hasthis) {
 694                 arg_info [0].offset = 0;
 695         }
 696
 697         for (k = 0; k < param_count; k++) {
 698                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 699                 /* FIXME: */
 700                 arg_info [k + 1].size = 0;
 701         }
 702
 703         g_free (cinfo);
 704
 705         return args_size;
 706 }
 707
 708 static int
 709 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 710 {
 711         return 0;
 712 }
 713
 714 /*
 715  * Initialize the cpu to execute managed code.
 716  */
 717 void
 718 mono_arch_cpu_init (void)
 719 {
 720 #ifndef _MSC_VER
 721         guint16 fpcw;
 722
 723         /* spec compliance requires running with double precision */
 724         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 725         fpcw &= ~X86_FPCW_PRECC_MASK;
 726         fpcw |= X86_FPCW_PREC_DOUBLE;
 727         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 728         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 729 #else
 730         _control87 (_PC_53, MCW_PC);
 731 #endif
 732 }
 733
 734 /*
 735  * This function returns the optimizations supported on this cpu.
 736  */
 737 guint32
 738 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 739 {
 740         int eax, ebx, ecx, edx;
 741         guint32 opts = 0;
 742
 743         /* FIXME: AMD64 */
 744
 745         *exclude_mask = 0;
 746         /* Feature Flags function, flags returned in EDX. */
 747         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 748                 if (edx & (1 << 15)) {
 749                         opts |= MONO_OPT_CMOV;
 750                         if (edx & 1)
 751                                 opts |= MONO_OPT_FCMOV;
 752                         else
 753                                 *exclude_mask |= MONO_OPT_FCMOV;
 754                 } else
 755                         *exclude_mask |= MONO_OPT_CMOV;
 756         }
 757         return opts;
 758 }
 759
 760 gboolean
 761 mono_amd64_is_sse2 (void)
 762 {
 763         return use_sse2;
 764 }
 765
 766 GList *
 767 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 768 {
 769         GList *vars = NULL;
 770         int i;
 771
 772         for (i = 0; i < cfg->num_varinfo; i++) {
 773                 MonoInst *ins = cfg->varinfo [i];
 774                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 775
 776                 /* unused vars */
 777                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 778                         continue;
 779
 780                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 781                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 782                         continue;
 783
 784                 if (mono_is_regsize_var (ins->inst_vtype)) {
 785                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 786                         g_assert (i == vmv->idx);
 787                         vars = g_list_prepend (vars, vmv);
 788                 }
 789         }
 790
 791         vars = mono_varlist_sort (cfg, vars, 0);
 792
 793         return vars;
 794 }
 795
 796 /**
 797  * mono_arch_compute_omit_fp:
 798  *
 799  *   Determine whenever the frame pointer can be eliminated.
 800  */
 801 static void
 802 mono_arch_compute_omit_fp (MonoCompile *cfg)
 803 {
 804         MonoMethodSignature *sig;
 805         MonoMethodHeader *header;
 806         int i;
 807         CallInfo *cinfo;
 808
 809         if (cfg->arch.omit_fp_computed)
 810                 return;
 811
 812         header = mono_method_get_header (cfg->method);
 813
 814         sig = mono_method_signature (cfg->method);
 815
 816         cinfo = get_call_info (sig, FALSE);
 817
 818         /*
 819          * FIXME: Remove some of the restrictions.
 820          */
 821         cfg->arch.omit_fp = TRUE;
 822         cfg->arch.omit_fp_computed = TRUE;
 823
 824         /* Temporarily disable this when running in the debugger until we have support
 825          * for this in the debugger. */
 826         if (mono_debug_using_mono_debugger ())
 827                 cfg->arch.omit_fp = FALSE;
 828
 829         if (!debug_omit_fp ())
 830                 cfg->arch.omit_fp = FALSE;
 831         /*
 832         if (cfg->method->save_lmf)
 833                 cfg->arch.omit_fp = FALSE;
 834         */
 835         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 836                 cfg->arch.omit_fp = FALSE;
 837         if (header->num_clauses)
 838                 cfg->arch.omit_fp = FALSE;
 839         if (cfg->param_area)
 840                 cfg->arch.omit_fp = FALSE;
 841         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 842                 cfg->arch.omit_fp = FALSE;
 843         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 844                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 845                 cfg->arch.omit_fp = FALSE;
 846         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 847                 ArgInfo *ainfo = &cinfo->args [i];
 848
 849                 if (ainfo->storage == ArgOnStack) {
 850                         /*
 851                          * The stack offset can only be determined when the frame
 852                          * size is known.
 853                          */
 854                         cfg->arch.omit_fp = FALSE;
 855                 }
 856         }
 857
 858         if (cfg->num_varinfo > 10000) {
 859                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 860                 cfg->arch.omit_fp = FALSE;
 861         }
 862
 863         g_free (cinfo);
 864 }
 865
 866 GList *
 867 mono_arch_get_global_int_regs (MonoCompile *cfg)
 868 {
 869         GList *regs = NULL;
 870
 871         mono_arch_compute_omit_fp (cfg);
 872
 873         if (cfg->arch.omit_fp)
 874                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 875
 876         /* We use the callee saved registers for global allocation */
 877         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 878         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 879         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 880         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 881         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 882
 883         return regs;
 884 }
 885
 886 /*
 887  * mono_arch_regalloc_cost:
 888  *
 889  *  Return the cost, in number of memory references, of the action of
 890  * allocating the variable VMV into a register during global register
 891  * allocation.
 892  */
 893 guint32
 894 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 895 {
 896         MonoInst *ins = cfg->varinfo [vmv->idx];
 897
 898         if (cfg->method->save_lmf)
 899                 /* The register is already saved */
 900                 /* substract 1 for the invisible store in the prolog */
 901                 return (ins->opcode == OP_ARG) ? 0 : 1;
 902         else
 903                 /* push+pop */
 904                 return (ins->opcode == OP_ARG) ? 1 : 2;
 905 }
 906
 907 void
 908 mono_arch_allocate_vars (MonoCompile *cfg)
 909 {
 910         MonoMethodSignature *sig;
 911         MonoMethodHeader *header;
 912         MonoInst *inst;
 913         int i, offset;
 914         guint32 locals_stack_size, locals_stack_align;
 915         gint32 *offsets;
 916         CallInfo *cinfo;
 917
 918         header = mono_method_get_header (cfg->method);
 919
 920         sig = mono_method_signature (cfg->method);
 921
 922         cinfo = get_call_info (sig, FALSE);
 923
 924         mono_arch_compute_omit_fp (cfg);
 925
 926         /*
 927          * We use the ABI calling conventions for managed code as well.
 928          * Exception: valuetypes are never passed or returned in registers.
 929          */
 930
 931         if (cfg->arch.omit_fp) {
 932                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 933                 cfg->frame_reg = AMD64_RSP;
 934                 offset = 0;
 935         } else {
 936                 /* Locals are allocated backwards from %fp */
 937                 cfg->frame_reg = AMD64_RBP;
 938                 offset = 0;
 939         }
 940
 941         cfg->arch.reg_save_area_offset = offset;
 942
 943         /* Reserve space for caller saved registers */
 944         for (i = 0; i < AMD64_NREG; ++i)
 945                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 946                         offset += sizeof (gpointer);
 947                 }
 948
 949         if (cfg->method->save_lmf) {
 950                 /* Reserve stack space for saving LMF + argument regs */
 951                 guint32 size = sizeof (MonoLMF);
 952
 953                 if (lmf_addr_tls_offset == -1)
 954                         /* Need to save argument regs too */
 955                         size += (AMD64_NREG * 8) + (8 * 8);
 956
 957                 if (cfg->arch.omit_fp) {
 958                         cfg->arch.lmf_offset = offset;
 959                         offset += size;
 960                 }
 961                 else {
 962                         offset += size;
 963                         cfg->arch.lmf_offset = -offset;
 964                 }
 965         }
 966
 967         if (sig->ret->type != MONO_TYPE_VOID) {
 968                 switch (cinfo->ret.storage) {
 969                 case ArgInIReg:
 970                 case ArgInFloatSSEReg:
 971                 case ArgInDoubleSSEReg:
 972                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 973                                 /* The register is volatile */
 974                                 cfg->ret->opcode = OP_REGOFFSET;
 975                                 cfg->ret->inst_basereg = cfg->frame_reg;
 976                                 if (cfg->arch.omit_fp) {
 977                                         cfg->ret->inst_offset = offset;
 978                                         offset += 8;
 979                                 } else {
 980                                         offset += 8;
 981                                         cfg->ret->inst_offset = -offset;
 982                                 }
 983                         }
 984                         else {
 985                                 cfg->ret->opcode = OP_REGVAR;
 986                                 cfg->ret->inst_c0 = cinfo->ret.reg;
 987                         }
 988                         break;
 989                 case ArgValuetypeInReg:
 990                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 991                         g_assert (!cfg->arch.omit_fp);
 992                         offset += 16;
 993                         cfg->ret->opcode = OP_REGOFFSET;
 994                         cfg->ret->inst_basereg = cfg->frame_reg;
 995                         cfg->ret->inst_offset = - offset;
 996                         break;
 997                 default:
 998                         g_assert_not_reached ();
 999                 }
1000                 cfg->ret->dreg = cfg->ret->inst_c0;
1001         }
1002
1003         /* Allocate locals */
1004         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1005         if (locals_stack_align) {
1006                 offset += (locals_stack_align - 1);
1007                 offset &= ~(locals_stack_align - 1);
1008         }
1009         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1010                 if (offsets [i] != -1) {
1011                         MonoInst *inst = cfg->varinfo [i];
1012                         inst->opcode = OP_REGOFFSET;
1013                         inst->inst_basereg = cfg->frame_reg;
1014                         if (cfg->arch.omit_fp)
1015                                 inst->inst_offset = (offset + offsets [i]);
1016                         else
1017                                 inst->inst_offset = - (offset + offsets [i]);
1018                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1019                 }
1020         }
1021         offset += locals_stack_size;
1022
1023         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1024                 g_assert (!cfg->arch.omit_fp);
1025                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1026                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1027         }
1028
1029         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1030                 inst = cfg->varinfo [i];
1031                 if (inst->opcode != OP_REGVAR) {
1032                         ArgInfo *ainfo = &cinfo->args [i];
1033                         gboolean inreg = TRUE;
1034                         MonoType *arg_type;
1035
1036                         if (sig->hasthis && (i == 0))
1037                                 arg_type = &mono_defaults.object_class->byval_arg;
1038                         else
1039                                 arg_type = sig->params [i - sig->hasthis];
1040
1041                         /* FIXME: Allocate volatile arguments to registers */
1042                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1043                                 inreg = FALSE;
1044
1045                         /*
1046                          * Under AMD64, all registers used to pass arguments to functions
1047                          * are volatile across calls.
1048                          * FIXME: Optimize this.
1049                          */
1050                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1051                                 inreg = FALSE;
1052
1053                         inst->opcode = OP_REGOFFSET;
1054
1055                         switch (ainfo->storage) {
1056                         case ArgInIReg:
1057                         case ArgInFloatSSEReg:
1058                         case ArgInDoubleSSEReg:
1059                                 inst->opcode = OP_REGVAR;
1060                                 inst->dreg = ainfo->reg;
1061                                 break;
1062                         case ArgOnStack:
1063                                 g_assert (!cfg->arch.omit_fp);
1064                                 inst->opcode = OP_REGOFFSET;
1065                                 inst->inst_basereg = cfg->frame_reg;
1066                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1067                                 break;
1068                         case ArgValuetypeInReg:
1069                                 break;
1070                         default:
1071                                 NOT_IMPLEMENTED;
1072                         }
1073
1074                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1075                                 inst->opcode = OP_REGOFFSET;
1076                                 inst->inst_basereg = cfg->frame_reg;
1077                                 /* These arguments are saved to the stack in the prolog */
1078                                 if (cfg->arch.omit_fp) {
1079                                         inst->inst_offset = offset;
1080                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1081                                 } else {
1082                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1083                                         inst->inst_offset = - offset;
1084                                 }
1085                         }
1086                 }
1087         }
1088
1089         cfg->stack_offset = offset;
1090
1091         g_free (cinfo);
1092 }
1093
1094 void
1095 mono_arch_create_vars (MonoCompile *cfg)
1096 {
1097         MonoMethodSignature *sig;
1098         CallInfo *cinfo;
1099
1100         sig = mono_method_signature (cfg->method);
1101
1102         cinfo = get_call_info (sig, FALSE);
1103
1104         if (cinfo->ret.storage == ArgValuetypeInReg)
1105                 cfg->ret_var_is_local = TRUE;
1106
1107         g_free (cinfo);
1108 }
1109
1110 static void
1111 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1112 {
1113         switch (storage) {
1114         case ArgInIReg:
1115                 arg->opcode = OP_OUTARG_REG;
1116                 arg->inst_left = tree;
1117                 arg->inst_call = call;
1118                 arg->backend.reg3 = reg;
1119                 break;
1120         case ArgInFloatSSEReg:
1121                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1122                 arg->inst_left = tree;
1123                 arg->inst_call = call;
1124                 arg->backend.reg3 = reg;
1125                 break;
1126         case ArgInDoubleSSEReg:
1127                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1128                 arg->inst_left = tree;
1129                 arg->inst_call = call;
1130                 arg->backend.reg3 = reg;
1131                 break;
1132         default:
1133                 g_assert_not_reached ();
1134         }
1135 }
1136
1137 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1138  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1139  */
1140
1141 static int
1142 arg_storage_to_ldind (ArgStorage storage)
1143 {
1144         switch (storage) {
1145         case ArgInIReg:
1146                 return CEE_LDIND_I;
1147         case ArgInDoubleSSEReg:
1148                 return CEE_LDIND_R8;
1149         case ArgInFloatSSEReg:
1150                 return CEE_LDIND_R4;
1151         default:
1152                 g_assert_not_reached ();
1153         }
1154
1155         return -1;
1156 }
1157
1158 static void
1159 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1160 {
1161         MonoInst *arg;
1162         MonoMethodSignature *tmp_sig;
1163         MonoInst *sig_arg;
1164
1165         /* FIXME: Add support for signature tokens to AOT */
1166         cfg->disable_aot = TRUE;
1167
1168         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1169
1170         /*
1171          * mono_ArgIterator_Setup assumes the signature cookie is
1172          * passed first and all the arguments which were before it are
1173          * passed on the stack after the signature. So compensate by
1174          * passing a different signature.
1175          */
1176         tmp_sig = mono_metadata_signature_dup (call->signature);
1177         tmp_sig->param_count -= call->signature->sentinelpos;
1178         tmp_sig->sentinelpos = 0;
1179         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1180
1181         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1182         sig_arg->inst_p0 = tmp_sig;
1183
1184         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1185         arg->inst_left = sig_arg;
1186         arg->type = STACK_PTR;
1187
1188         /* prepend, so they get reversed */
1189         arg->next = call->out_args;
1190         call->out_args = arg;
1191 }
1192
1193 /*
1194  * take the arguments and generate the arch-specific
1195  * instructions to properly call the function in call.
1196  * This includes pushing, moving arguments to the right register
1197  * etc.
1198  * Issue: who does the spilling if needed, and when?
1199  */
1200 MonoCallInst*
1201 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1202         MonoInst *arg, *in;
1203         MonoMethodSignature *sig;
1204         int i, n, stack_size;
1205         CallInfo *cinfo;
1206         ArgInfo *ainfo;
1207
1208         stack_size = 0;
1209
1210         sig = call->signature;
1211         n = sig->param_count + sig->hasthis;
1212
1213         cinfo = get_call_info (sig, sig->pinvoke);
1214
1215         for (i = 0; i < n; ++i) {
1216                 ainfo = cinfo->args + i;
1217
1218                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1219                         /* Emit the signature cookie just before the implicit arguments */
1220                         emit_sig_cookie (cfg, call, cinfo);
1221                 }
1222
1223                 if (is_virtual && i == 0) {
1224                         /* the argument will be attached to the call instruction */
1225                         in = call->args [i];
1226                 } else {
1227                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1228                         in = call->args [i];
1229                         arg->cil_code = in->cil_code;
1230                         arg->inst_left = in;
1231                         arg->type = in->type;
1232                         /* prepend, so they get reversed */
1233                         arg->next = call->out_args;
1234                         call->out_args = arg;
1235
1236                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1237                                 guint32 align;
1238                                 guint32 size;
1239
1240                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1241                                         size = sizeof (MonoTypedRef);
1242                                         align = sizeof (gpointer);
1243                                 }
1244                                 else
1245                                 if (sig->pinvoke)
1246                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1247                                 else {
1248                                         /*
1249                                          * Other backends use mono_type_stack_size (), but that
1250                                          * aligns the size to 8, which is larger than the size of
1251                                          * the source, leading to reads of invalid memory if the
1252                                          * source is at the end of address space.
1253                                          */
1254                                         size = mono_class_value_size (in->klass, &align);
1255                                 }
1256                                 if (ainfo->storage == ArgValuetypeInReg) {
1257                                         if (ainfo->pair_storage [1] == ArgNone) {
1258                                                 MonoInst *load;
1259
1260                                                 /* Simpler case */
1261
1262                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1263                                                 load->inst_left = in;
1264
1265                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1266                                         }
1267                                         else {
1268                                                 /* Trees can't be shared so make a copy */
1269                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1270                                                 MonoInst *load, *load2, *offset_ins;
1271
1272                                                 /* Reg1 */
1273                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1274                                                 load->ssa_op = MONO_SSA_LOAD;
1275                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1276
1277                                                 NEW_ICONST (cfg, offset_ins, 0);
1278                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1279                                                 load2->inst_left = load;
1280                                                 load2->inst_right = offset_ins;
1281
1282                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1283                                                 load->inst_left = load2;
1284
1285                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1286
1287                                                 /* Reg2 */
1288                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1289                                                 load->ssa_op = MONO_SSA_LOAD;
1290                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1291
1292                                                 NEW_ICONST (cfg, offset_ins, 8);
1293                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1294                                                 load2->inst_left = load;
1295                                                 load2->inst_right = offset_ins;
1296
1297                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1298                                                 load->inst_left = load2;
1299
1300                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1301                                                 arg->cil_code = in->cil_code;
1302                                                 arg->type = in->type;
1303                                                 /* prepend, so they get reversed */
1304                                                 arg->next = call->out_args;
1305                                                 call->out_args = arg;
1306
1307                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1308
1309                                                 /* Prepend a copy inst */
1310                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1311                                                 arg->cil_code = in->cil_code;
1312                                                 arg->ssa_op = MONO_SSA_STORE;
1313                                                 arg->inst_left = vtaddr;
1314                                                 arg->inst_right = in;
1315                                                 arg->type = in->type;
1316
1317                                                 /* prepend, so they get reversed */
1318                                                 arg->next = call->out_args;
1319                                                 call->out_args = arg;
1320                                         }
1321                                 }
1322                                 else {
1323                                         arg->opcode = OP_OUTARG_VT;
1324                                         arg->klass = in->klass;
1325                                         arg->backend.is_pinvoke = sig->pinvoke;
1326                                         arg->inst_imm = size;
1327                                 }
1328                         }
1329                         else {
1330                                 switch (ainfo->storage) {
1331                                 case ArgInIReg:
1332                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1333                                         break;
1334                                 case ArgInFloatSSEReg:
1335                                 case ArgInDoubleSSEReg:
1336                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1337                                         break;
1338                                 case ArgOnStack:
1339                                         arg->opcode = OP_OUTARG;
1340                                         if (!sig->params [i - sig->hasthis]->byref) {
1341                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1342                                                         arg->opcode = OP_OUTARG_R4;
1343                                                 else
1344                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1345                                                                 arg->opcode = OP_OUTARG_R8;
1346                                         }
1347                                         break;
1348                                 default:
1349                                         g_assert_not_reached ();
1350                                 }
1351                         }
1352                 }
1353         }
1354
1355         /* Handle the case where there are no implicit arguments */
1356         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1357                 emit_sig_cookie (cfg, call, cinfo);
1358         }
1359
1360         if (cinfo->need_stack_align) {
1361                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1362                 /* prepend, so they get reversed */
1363                 arg->next = call->out_args;
1364                 call->out_args = arg;
1365         }
1366
1367         call->stack_usage = cinfo->stack_usage;
1368         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1369         cfg->flags |= MONO_CFG_HAS_CALLS;
1370
1371         g_free (cinfo);
1372
1373         return call;
1374 }
1375
1376 #define EMIT_COND_BRANCH(ins,cond,sign) \
1377 if (ins->flags & MONO_INST_BRLABEL) { \
1378         if (ins->inst_i0->inst_c0) { \
1379                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1380         } else { \
1381                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1382                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1383                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1384                         x86_branch8 (code, cond, 0, sign); \
1385                 else \
1386                         x86_branch32 (code, cond, 0, sign); \
1387         } \
1388 } else { \
1389         if (ins->inst_true_bb->native_offset) { \
1390                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1391         } else { \
1392                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1393                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1394                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1395                         x86_branch8 (code, cond, 0, sign); \
1396                 else \
1397                         x86_branch32 (code, cond, 0, sign); \
1398         } \
1399 }
1400
1401 /* emit an exception if condition is fail */
1402 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1403         do {                                                        \
1404                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1405                 if (tins == NULL) {                                                                             \
1406                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1407                                         MONO_PATCH_INFO_EXC, exc_name);  \
1408                         x86_branch32 (code, cond, 0, signed);               \
1409                 } else {        \
1410                         EMIT_COND_BRANCH (tins, cond, signed);  \
1411                 }                       \
1412         } while (0);
1413
1414 #define EMIT_FPCOMPARE(code) do { \
1415         amd64_fcompp (code); \
1416         amd64_fnstsw (code); \
1417 } while (0);
1418
1419 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1420     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1421         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1422         amd64_ ##op (code); \
1423         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1424         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1425 } while (0);
1426
1427 static guint8*
1428 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1429 {
1430         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1431
1432         /*
1433          * FIXME: Add support for thunks
1434          */
1435         {
1436                 gboolean near_call = FALSE;
1437
1438                 /*
1439                  * Indirect calls are expensive so try to make a near call if possible.
1440                  * The caller memory is allocated by the code manager so it is
1441                  * guaranteed to be at a 32 bit offset.
1442                  */
1443
1444                 if (patch_type != MONO_PATCH_INFO_ABS) {
1445                         /* The target is in memory allocated using the code manager */
1446                         near_call = TRUE;
1447
1448                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1449                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1450                                         /* The callee might be an AOT method */
1451                                         near_call = FALSE;
1452                         }
1453
1454                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1455                                 /*
1456                                  * The call might go directly to a native function without
1457                                  * the wrapper.
1458                                  */
1459                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1460                                 if (mi) {
1461                                         gconstpointer target = mono_icall_get_wrapper (mi);
1462                                         if ((((guint64)target) >> 32) != 0)
1463                                                 near_call = FALSE;
1464                                 }
1465                         }
1466                 }
1467                 else {
1468                         if (mono_find_class_init_trampoline_by_addr (data))
1469                                 near_call = TRUE;
1470                         else {
1471                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1472                                 if (info) {
1473                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1474                                                 strstr (cfg->method->name, info->name)) {
1475                                                 /* A call to the wrapped function */
1476                                                 if ((((guint64)data) >> 32) == 0)
1477                                                         near_call = TRUE;
1478                                         }
1479                                         else if (info->func == info->wrapper) {
1480                                                 /* No wrapper */
1481                                                 if ((((guint64)info->func) >> 32) == 0)
1482                                                         near_call = TRUE;
1483                                         }
1484                                         else {
1485                                                 /* See the comment in mono_codegen () */
1486                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1487                                                         near_call = TRUE;
1488                                         }
1489                                 }
1490                                 else if ((((guint64)data) >> 32) == 0)
1491                                         near_call = TRUE;
1492                         }
1493                 }
1494
1495                 if (cfg->method->dynamic)
1496                         /* These methods are allocated using malloc */
1497                         near_call = FALSE;
1498
1499                 if (cfg->compile_aot)
1500                         near_call = TRUE;
1501
1502 #ifdef MONO_ARCH_NOMAP32BIT
1503                 near_call = FALSE;
1504 #endif
1505
1506                 if (near_call) {
1507                         amd64_call_code (code, 0);
1508                 }
1509                 else {
1510                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1511                         amd64_call_reg (code, GP_SCRATCH_REG);
1512                 }
1513         }
1514
1515         return code;
1516 }
1517
1518 static inline guint8*
1519 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1520 {
1521         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1522
1523         return emit_call_body (cfg, code, patch_type, data);
1524 }
1525
1526 static inline int
1527 store_membase_imm_to_store_membase_reg (int opcode)
1528 {
1529         switch (opcode) {
1530         case OP_STORE_MEMBASE_IMM:
1531                 return OP_STORE_MEMBASE_REG;
1532         case OP_STOREI4_MEMBASE_IMM:
1533                 return OP_STOREI4_MEMBASE_REG;
1534         case OP_STOREI8_MEMBASE_IMM:
1535                 return OP_STOREI8_MEMBASE_REG;
1536         }
1537
1538         return -1;
1539 }
1540
1541 /* FIXME: Add more instructions */
1542 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1543
1544 static void
1545 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1546 {
1547         MonoInst *ins, *last_ins = NULL;
1548         ins = bb->code;
1549
1550         while (ins) {
1551
1552                 switch (ins->opcode) {
1553                 case OP_ICONST:
1554                 case OP_I8CONST:
1555                         /* reg = 0 -> XOR (reg, reg) */
1556                         /* XOR sets cflags on x86, so we cant do it always */
1557                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1558                                 ins->opcode = CEE_XOR;
1559                                 ins->sreg1 = ins->dreg;
1560                                 ins->sreg2 = ins->dreg;
1561                                 /* Fall through */
1562                         }
1563                         else
1564                                 break;
1565                 case CEE_XOR:
1566                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1567                                 MonoInst *ins2;
1568
1569                                 /*
1570                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1571                                  * the latter has length 2-3 instead of 6 (reverse constant
1572                                  * propagation). These instruction sequences are very common
1573                                  * in the initlocals bblock.
1574                                  */
1575                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1576                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1577                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1578                                                 ins2->sreg1 = ins->dreg;
1579                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1580                                                 /* Continue */
1581                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1582                                                 NULLIFY_INS (ins2);
1583                                                 /* Continue */
1584                                         } else {
1585                                                 break;
1586                                         }
1587                                 }
1588                         }
1589                         break;
1590                 case OP_MUL_IMM:
1591                         /* remove unnecessary multiplication with 1 */
1592                         if (ins->inst_imm == 1) {
1593                                 if (ins->dreg != ins->sreg1) {
1594                                         ins->opcode = OP_MOVE;
1595                                 } else {
1596                                         last_ins->next = ins->next;
1597                                         ins = ins->next;
1598                                         continue;
1599                                 }
1600                         }
1601                         break;
1602                 case OP_COMPARE_IMM:
1603                         /* OP_COMPARE_IMM (reg, 0)
1604                          * -->
1605                          * OP_AMD64_TEST_NULL (reg)
1606                          */
1607                         if (!ins->inst_imm)
1608                                 ins->opcode = OP_AMD64_TEST_NULL;
1609                         break;
1610                 case OP_ICOMPARE_IMM:
1611                         if (!ins->inst_imm)
1612                                 ins->opcode = OP_X86_TEST_NULL;
1613                         break;
1614                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1615                         /*
1616                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1617                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1618                          * -->
1619                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1620                          * OP_COMPARE_IMM reg, imm
1621                          *
1622                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1623                          */
1624                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1625                             ins->inst_basereg == last_ins->inst_destbasereg &&
1626                             ins->inst_offset == last_ins->inst_offset) {
1627                                         ins->opcode = OP_ICOMPARE_IMM;
1628                                         ins->sreg1 = last_ins->sreg1;
1629
1630                                         /* check if we can remove cmp reg,0 with test null */
1631                                         if (!ins->inst_imm)
1632                                                 ins->opcode = OP_X86_TEST_NULL;
1633                                 }
1634
1635                         break;
1636                 case OP_LOAD_MEMBASE:
1637                 case OP_LOADI4_MEMBASE:
1638                         /*
1639                          * Note: if reg1 = reg2 the load op is removed
1640                          *
1641                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1642                          * OP_LOAD_MEMBASE offset(basereg), reg2
1643                          * -->
1644                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1645                          * OP_MOVE reg1, reg2
1646                          */
1647                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1648                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1649                             ins->inst_basereg == last_ins->inst_destbasereg &&
1650                             ins->inst_offset == last_ins->inst_offset) {
1651                                 if (ins->dreg == last_ins->sreg1) {
1652                                         last_ins->next = ins->next;
1653                                         ins = ins->next;
1654                                         continue;
1655                                 } else {
1656                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1657                                         ins->opcode = OP_MOVE;
1658                                         ins->sreg1 = last_ins->sreg1;
1659                                 }
1660
1661                         /*
1662                          * Note: reg1 must be different from the basereg in the second load
1663                          * Note: if reg1 = reg2 is equal then second load is removed
1664                          *
1665                          * OP_LOAD_MEMBASE offset(basereg), reg1
1666                          * OP_LOAD_MEMBASE offset(basereg), reg2
1667                          * -->
1668                          * OP_LOAD_MEMBASE offset(basereg), reg1
1669                          * OP_MOVE reg1, reg2
1670                          */
1671                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1672                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1673                               ins->inst_basereg != last_ins->dreg &&
1674                               ins->inst_basereg == last_ins->inst_basereg &&
1675                               ins->inst_offset == last_ins->inst_offset) {
1676
1677                                 if (ins->dreg == last_ins->dreg) {
1678                                         last_ins->next = ins->next;
1679                                         ins = ins->next;
1680                                         continue;
1681                                 } else {
1682                                         ins->opcode = OP_MOVE;
1683                                         ins->sreg1 = last_ins->dreg;
1684                                 }
1685
1686                                 //g_assert_not_reached ();
1687
1688 #if 0
1689                         /*
1690                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1691                          * OP_LOAD_MEMBASE offset(basereg), reg
1692                          * -->
1693                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1694                          * OP_ICONST reg, imm
1695                          */
1696                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1697                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1698                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1699                                    ins->inst_offset == last_ins->inst_offset) {
1700                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1701                                 ins->opcode = OP_ICONST;
1702                                 ins->inst_c0 = last_ins->inst_imm;
1703                                 g_assert_not_reached (); // check this rule
1704 #endif
1705                         }
1706                         break;
1707                 case OP_LOADI1_MEMBASE:
1708                         /*
1709                          * Note: if reg1 = reg2 the load op is removed
1710                          *
1711                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1712                          * OP_LOAD_MEMBASE offset(basereg), reg2
1713                          * -->
1714                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1715                          * OP_MOVE reg1, reg2
1716                          */
1717                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1718                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1719                                         ins->inst_offset == last_ins->inst_offset) {
1720                                 if (ins->dreg == last_ins->sreg1) {
1721                                         last_ins->next = ins->next;
1722                                         ins = ins->next;
1723                                         continue;
1724                                 } else {
1725                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1726                                         ins->opcode = OP_MOVE;
1727                                         ins->sreg1 = last_ins->sreg1;
1728                                 }
1729                         }
1730                         break;
1731                 case OP_LOADI2_MEMBASE:
1732                         /*
1733                          * Note: if reg1 = reg2 the load op is removed
1734                          *
1735                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1736                          * OP_LOAD_MEMBASE offset(basereg), reg2
1737                          * -->
1738                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1739                          * OP_MOVE reg1, reg2
1740                          */
1741                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1742                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1743                                         ins->inst_offset == last_ins->inst_offset) {
1744                                 if (ins->dreg == last_ins->sreg1) {
1745                                         last_ins->next = ins->next;
1746                                         ins = ins->next;
1747                                         continue;
1748                                 } else {
1749                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1750                                         ins->opcode = OP_MOVE;
1751                                         ins->sreg1 = last_ins->sreg1;
1752                                 }
1753                         }
1754                         break;
1755                 case CEE_CONV_I4:
1756                 case CEE_CONV_U4:
1757                 case OP_MOVE:
1758                         /*
1759                          * Removes:
1760                          *
1761                          * OP_MOVE reg, reg
1762                          */
1763                         if (ins->dreg == ins->sreg1) {
1764                                 if (last_ins)
1765                                         last_ins->next = ins->next;
1766                                 ins = ins->next;
1767                                 continue;
1768                         }
1769                         /*
1770                          * Removes:
1771                          *
1772                          * OP_MOVE sreg, dreg
1773                          * OP_MOVE dreg, sreg
1774                          */
1775                         if (last_ins && last_ins->opcode == OP_MOVE &&
1776                             ins->sreg1 == last_ins->dreg &&
1777                             ins->dreg == last_ins->sreg1) {
1778                                 last_ins->next = ins->next;
1779                                 ins = ins->next;
1780                                 continue;
1781                         }
1782                         break;
1783                 }
1784                 last_ins = ins;
1785                 ins = ins->next;
1786         }
1787         bb->last_ins = last_ins;
1788 }
1789
1790 static void
1791 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1792 {
1793         if (ins == NULL) {
1794                 ins = bb->code;
1795                 bb->code = to_insert;
1796                 to_insert->next = ins;
1797         }
1798         else {
1799                 to_insert->next = ins->next;
1800                 ins->next = to_insert;
1801         }
1802 }
1803
1804 #define NEW_INS(cfg,dest,op) do {       \
1805                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1806                 (dest)->opcode = (op);  \
1807         insert_after_ins (bb, last_ins, (dest)); \
1808         } while (0)
1809
1810 /*
1811  * mono_arch_lowering_pass:
1812  *
1813  *  Converts complex opcodes into simpler ones so that each IR instruction
1814  * corresponds to one machine instruction.
1815  */
1816 static void
1817 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1818 {
1819         MonoInst *ins, *temp, *last_ins = NULL;
1820         ins = bb->code;
1821
1822         if (bb->max_vreg > cfg->rs->next_vreg)
1823                 cfg->rs->next_vreg = bb->max_vreg;
1824
1825         /*
1826          * FIXME: Need to add more instructions, but the current machine
1827          * description can't model some parts of the composite instructions like
1828          * cdq.
1829          */
1830         while (ins) {
1831                 switch (ins->opcode) {
1832                 case OP_DIV_IMM:
1833                 case OP_REM_IMM:
1834                 case OP_IDIV_IMM:
1835                 case OP_IREM_IMM:
1836                         NEW_INS (cfg, temp, OP_ICONST);
1837                         temp->inst_c0 = ins->inst_imm;
1838                         temp->dreg = mono_regstate_next_int (cfg->rs);
1839                         switch (ins->opcode) {
1840                         case OP_DIV_IMM:
1841                                 ins->opcode = OP_LDIV;
1842                                 break;
1843                         case OP_REM_IMM:
1844                                 ins->opcode = OP_LREM;
1845                                 break;
1846                         case OP_IDIV_IMM:
1847                                 ins->opcode = OP_IDIV;
1848                                 break;
1849                         case OP_IREM_IMM:
1850                                 ins->opcode = OP_IREM;
1851                                 break;
1852                         }
1853                         ins->sreg2 = temp->dreg;
1854                         break;
1855                 case OP_COMPARE_IMM:
1856                         if (!amd64_is_imm32 (ins->inst_imm)) {
1857                                 NEW_INS (cfg, temp, OP_I8CONST);
1858                                 temp->inst_c0 = ins->inst_imm;
1859                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1860                                 ins->opcode = OP_COMPARE;
1861                                 ins->sreg2 = temp->dreg;
1862                         }
1863                         break;
1864                 case OP_LOAD_MEMBASE:
1865                 case OP_LOADI8_MEMBASE:
1866                         if (!amd64_is_imm32 (ins->inst_offset)) {
1867                                 NEW_INS (cfg, temp, OP_I8CONST);
1868                                 temp->inst_c0 = ins->inst_offset;
1869                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1870                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1871                                 ins->inst_indexreg = temp->dreg;
1872                         }
1873                         break;
1874                 case OP_STORE_MEMBASE_IMM:
1875                 case OP_STOREI8_MEMBASE_IMM:
1876                         if (!amd64_is_imm32 (ins->inst_imm)) {
1877                                 NEW_INS (cfg, temp, OP_I8CONST);
1878                                 temp->inst_c0 = ins->inst_imm;
1879                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1880                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1881                                 ins->sreg1 = temp->dreg;
1882                         }
1883                         break;
1884                 default:
1885                         break;
1886                 }
1887                 last_ins = ins;
1888                 ins = ins->next;
1889         }
1890         bb->last_ins = last_ins;
1891
1892         bb->max_vreg = cfg->rs->next_vreg;
1893 }
1894
1895 static const int
1896 branch_cc_table [] = {
1897         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1898         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1899         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1900 };
1901
1902 static int
1903 opcode_to_x86_cond (int opcode)
1904 {
1905         switch (opcode) {
1906         case OP_IBEQ:
1907                 return X86_CC_EQ;
1908         case OP_IBNE_UN:
1909                 return X86_CC_NE;
1910         case OP_IBLT:
1911                 return X86_CC_LT;
1912         case OP_IBLT_UN:
1913                 return X86_CC_LT;
1914         case OP_IBGT:
1915                 return X86_CC_GT;
1916         case OP_IBGT_UN:
1917                 return X86_CC_GT;
1918         case OP_IBGE:
1919                 return X86_CC_GE;
1920         case OP_IBGE_UN:
1921                 return X86_CC_GE;
1922         case OP_IBLE:
1923                 return X86_CC_LE;
1924         case OP_IBLE_UN:
1925                 return X86_CC_LE;
1926         case OP_COND_EXC_IOV:
1927                 return X86_CC_O;
1928         case OP_COND_EXC_IC:
1929                 return X86_CC_C;
1930         default:
1931                 g_assert_not_reached ();
1932         }
1933
1934         return -1;
1935 }
1936
1937 /*#include "cprop.c"*/
1938
1939 /*
1940  * Local register allocation.
1941  * We first scan the list of instructions and we save the liveness info of
1942  * each register (when the register is first used, when it's value is set etc.).
1943  * We also reverse the list of instructions (in the InstList list) because assigning
1944  * registers backwards allows for more tricks to be used.
1945  */
1946 void
1947 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1948 {
1949         if (!bb->code)
1950                 return;
1951
1952         mono_arch_lowering_pass (cfg, bb);
1953
1954         mono_local_regalloc (cfg, bb);
1955 }
1956
1957 static unsigned char*
1958 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1959 {
1960         if (use_sse2) {
1961                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1962         }
1963         else {
1964                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1965                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1966                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1967                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1968                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1969                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1970                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1971                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1972                 amd64_pop_reg (code, dreg);
1973                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1974                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1975         }
1976
1977         if (size == 1)
1978                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1979         else if (size == 2)
1980                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1981         return code;
1982 }
1983
1984 static unsigned char*
1985 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1986 {
1987         int sreg = tree->sreg1;
1988         int need_touch = FALSE;
1989
1990 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1991         if (!tree->flags & MONO_INST_INIT)
1992                 need_touch = TRUE;
1993 #endif
1994
1995         if (need_touch) {
1996                 guint8* br[5];
1997
1998                 /*
1999                  * Under Windows:
2000                  * If requested stack size is larger than one page,
2001                  * perform stack-touch operation
2002                  */
2003                 /*
2004                  * Generate stack probe code.
2005                  * Under Windows, it is necessary to allocate one page at a time,
2006                  * "touching" stack after each successful sub-allocation. This is
2007                  * because of the way stack growth is implemented - there is a
2008                  * guard page before the lowest stack page that is currently commited.
2009                  * Stack normally grows sequentially so OS traps access to the
2010                  * guard page and commits more pages when needed.
2011                  */
2012                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2013                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2014
2015                 br[2] = code; /* loop */
2016                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2017                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2018                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2019                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2020                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2021                 amd64_patch (br[3], br[2]);
2022                 amd64_test_reg_reg (code, sreg, sreg);
2023                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2024                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2025
2026                 br[1] = code; x86_jump8 (code, 0);
2027
2028                 amd64_patch (br[0], code);
2029                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2030                 amd64_patch (br[1], code);
2031                 amd64_patch (br[4], code);
2032         }
2033         else
2034                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2035
2036         if (tree->flags & MONO_INST_INIT) {
2037                 int offset = 0;
2038                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2039                         amd64_push_reg (code, AMD64_RAX);
2040                         offset += 8;
2041                 }
2042                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2043                         amd64_push_reg (code, AMD64_RCX);
2044                         offset += 8;
2045                 }
2046                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2047                         amd64_push_reg (code, AMD64_RDI);
2048                         offset += 8;
2049                 }
2050
2051                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2052                 if (sreg != AMD64_RCX)
2053                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2054                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2055
2056                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2057                 amd64_cld (code);
2058                 amd64_prefix (code, X86_REP_PREFIX);
2059                 amd64_stosl (code);
2060
2061                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2062                         amd64_pop_reg (code, AMD64_RDI);
2063                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2064                         amd64_pop_reg (code, AMD64_RCX);
2065                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2066                         amd64_pop_reg (code, AMD64_RAX);
2067         }
2068         return code;
2069 }
2070
2071 static guint8*
2072 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2073 {
2074         CallInfo *cinfo;
2075         guint32 quad;
2076
2077         /* Move return value to the target register */
2078         /* FIXME: do this in the local reg allocator */
2079         switch (ins->opcode) {
2080         case CEE_CALL:
2081         case OP_CALL_REG:
2082         case OP_CALL_MEMBASE:
2083         case OP_LCALL:
2084         case OP_LCALL_REG:
2085         case OP_LCALL_MEMBASE:
2086                 g_assert (ins->dreg == AMD64_RAX);
2087                 break;
2088         case OP_FCALL:
2089         case OP_FCALL_REG:
2090         case OP_FCALL_MEMBASE:
2091                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2092                         if (use_sse2)
2093                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2094                         else {
2095                                 /* FIXME: optimize this */
2096                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2097                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2098                         }
2099                 }
2100                 else {
2101                         if (use_sse2) {
2102                                 if (ins->dreg != AMD64_XMM0)
2103                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2104                         }
2105                         else {
2106                                 /* FIXME: optimize this */
2107                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2108                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2109                         }
2110                 }
2111                 break;
2112         case OP_VCALL:
2113         case OP_VCALL_REG:
2114         case OP_VCALL_MEMBASE:
2115                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2116                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2117                         /* Pop the destination address from the stack */
2118                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2119                         amd64_pop_reg (code, AMD64_RCX);
2120
2121                         for (quad = 0; quad < 2; quad ++) {
2122                                 switch (cinfo->ret.pair_storage [quad]) {
2123                                 case ArgInIReg:
2124                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2125                                         break;
2126                                 case ArgInFloatSSEReg:
2127                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2128                                         break;
2129                                 case ArgInDoubleSSEReg:
2130                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2131                                         break;
2132                                 case ArgNone:
2133                                         break;
2134                                 default:
2135                                         NOT_IMPLEMENTED;
2136                                 }
2137                         }
2138                 }
2139                 g_free (cinfo);
2140                 break;
2141         }
2142
2143         return code;
2144 }
2145
2146 /*
2147  * emit_tls_get:
2148  * @code: buffer to store code to
2149  * @dreg: hard register where to place the result
2150  * @tls_offset: offset info
2151  *
2152  * emit_tls_get emits in @code the native code that puts in the dreg register
2153  * the item in the thread local storage identified by tls_offset.
2154  *
2155  * Returns: a pointer to the end of the stored code
2156  */
2157 static guint8*
2158 emit_tls_get (guint8* code, int dreg, int tls_offset)
2159 {
2160         if (optimize_for_xen) {
2161                 x86_prefix (code, X86_FS_PREFIX);
2162                 amd64_mov_reg_mem (code, dreg, 0, 8);
2163                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2164         } else {
2165                 x86_prefix (code, X86_FS_PREFIX);
2166                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2167         }
2168         return code;
2169 }
2170
2171 /*
2172  * emit_load_volatile_arguments:
2173  *
2174  *  Load volatile arguments from the stack to the original input registers.
2175  * Required before a tail call.
2176  */
2177 static guint8*
2178 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2179 {
2180         MonoMethod *method = cfg->method;
2181         MonoMethodSignature *sig;
2182         MonoInst *inst;
2183         CallInfo *cinfo;
2184         guint32 i;
2185
2186         /* FIXME: Generate intermediate code instead */
2187
2188         sig = mono_method_signature (method);
2189
2190         cinfo = get_call_info (sig, FALSE);
2191
2192         /* This is the opposite of the code in emit_prolog */
2193
2194         if (sig->ret->type != MONO_TYPE_VOID) {
2195                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2196                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2197                 }
2198         }
2199
2200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2201                 ArgInfo *ainfo = cinfo->args + i;
2202                 MonoType *arg_type;
2203                 inst = cfg->varinfo [i];
2204
2205                 if (sig->hasthis && (i == 0))
2206                         arg_type = &mono_defaults.object_class->byval_arg;
2207                 else
2208                         arg_type = sig->params [i - sig->hasthis];
2209
2210                 if (inst->opcode != OP_REGVAR) {
2211                         switch (ainfo->storage) {
2212                         case ArgInIReg: {
2213                                 guint32 size = 8;
2214
2215                                 /* FIXME: I1 etc */
2216                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2217                                 break;
2218                         }
2219                         case ArgInFloatSSEReg:
2220                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2221                                 break;
2222                         case ArgInDoubleSSEReg:
2223                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2224                                 break;
2225                         default:
2226                                 break;
2227                         }
2228                 }
2229                 else {
2230                         g_assert (ainfo->storage == ArgInIReg);
2231
2232                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2233                 }
2234         }
2235
2236         g_free (cinfo);
2237
2238         return code;
2239 }
2240
2241 #define REAL_PRINT_REG(text,reg) \
2242 mono_assert (reg >= 0); \
2243 amd64_push_reg (code, AMD64_RAX); \
2244 amd64_push_reg (code, AMD64_RDX); \
2245 amd64_push_reg (code, AMD64_RCX); \
2246 amd64_push_reg (code, reg); \
2247 amd64_push_imm (code, reg); \
2248 amd64_push_imm (code, text " %d %p\n"); \
2249 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2250 amd64_call_reg (code, AMD64_RAX); \
2251 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2252 amd64_pop_reg (code, AMD64_RCX); \
2253 amd64_pop_reg (code, AMD64_RDX); \
2254 amd64_pop_reg (code, AMD64_RAX);
2255
2256 /* benchmark and set based on cpu */
2257 #define LOOP_ALIGNMENT 8
2258 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2259
2260 void
2261 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2262 {
2263         MonoInst *ins;
2264         MonoCallInst *call;
2265         guint offset;
2266         guint8 *code = cfg->native_code + cfg->code_len;
2267         MonoInst *last_ins = NULL;
2268         guint last_offset = 0;
2269         int max_len, cpos;
2270
2271         if (cfg->opt & MONO_OPT_PEEPHOLE)
2272                 peephole_pass (cfg, bb);
2273
2274         if (cfg->opt & MONO_OPT_LOOP) {
2275                 int pad, align = LOOP_ALIGNMENT;
2276                 /* set alignment depending on cpu */
2277                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2278                         pad = align - pad;
2279                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2280                         amd64_padding (code, pad);
2281                         cfg->code_len += pad;
2282                         bb->native_offset = cfg->code_len;
2283                 }
2284         }
2285
2286         if (cfg->verbose_level > 2)
2287                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2288
2289         cpos = bb->max_offset;
2290
2291         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2292                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2293                 g_assert (!cfg->compile_aot);
2294                 cpos += 6;
2295
2296                 cov->data [bb->dfn].cil_code = bb->cil_code;
2297                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2298                 /* this is not thread save, but good enough */
2299                 amd64_inc_membase (code, AMD64_R11, 0);
2300         }
2301
2302         offset = code - cfg->native_code;
2303
2304         mono_debug_open_block (cfg, bb, offset);
2305
2306         ins = bb->code;
2307         while (ins) {
2308                 offset = code - cfg->native_code;
2309
2310                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2311
2312                 if (offset > (cfg->code_size - max_len - 16)) {
2313                         cfg->code_size *= 2;
2314                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2315                         code = cfg->native_code + offset;
2316                         mono_jit_stats.code_reallocs++;
2317                 }
2318
2319                 mono_debug_record_line_number (cfg, ins, offset);
2320
2321                 switch (ins->opcode) {
2322                 case OP_BIGMUL:
2323                         amd64_mul_reg (code, ins->sreg2, TRUE);
2324                         break;
2325                 case OP_BIGMUL_UN:
2326                         amd64_mul_reg (code, ins->sreg2, FALSE);
2327                         break;
2328                 case OP_X86_SETEQ_MEMBASE:
2329                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2330                         break;
2331                 case OP_STOREI1_MEMBASE_IMM:
2332                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2333                         break;
2334                 case OP_STOREI2_MEMBASE_IMM:
2335                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2336                         break;
2337                 case OP_STOREI4_MEMBASE_IMM:
2338                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2339                         break;
2340                 case OP_STOREI1_MEMBASE_REG:
2341                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2342                         break;
2343                 case OP_STOREI2_MEMBASE_REG:
2344                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2345                         break;
2346                 case OP_STORE_MEMBASE_REG:
2347                 case OP_STOREI8_MEMBASE_REG:
2348                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2349                         break;
2350                 case OP_STOREI4_MEMBASE_REG:
2351                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2352                         break;
2353                 case OP_STORE_MEMBASE_IMM:
2354                 case OP_STOREI8_MEMBASE_IMM:
2355                         g_assert (amd64_is_imm32 (ins->inst_imm));
2356                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2357                         break;
2358                 case CEE_LDIND_I:
2359                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2360                         break;
2361                 case CEE_LDIND_I4:
2362                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2363                         break;
2364                 case CEE_LDIND_U4:
2365                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2366                         break;
2367                 case OP_LOADU4_MEM:
2368                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2369                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2370                         break;
2371                 case OP_LOAD_MEMBASE:
2372                 case OP_LOADI8_MEMBASE:
2373                         g_assert (amd64_is_imm32 (ins->inst_offset));
2374                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2375                         break;
2376                 case OP_LOADI4_MEMBASE:
2377                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2378                         break;
2379                 case OP_LOADU4_MEMBASE:
2380                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2381                         break;
2382                 case OP_LOADU1_MEMBASE:
2383                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2384                         break;
2385                 case OP_LOADI1_MEMBASE:
2386                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2387                         break;
2388                 case OP_LOADU2_MEMBASE:
2389                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2390                         break;
2391                 case OP_LOADI2_MEMBASE:
2392                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2393                         break;
2394                 case OP_AMD64_LOADI8_MEMINDEX:
2395                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2396                         break;
2397                 case CEE_CONV_I1:
2398                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2399                         break;
2400                 case CEE_CONV_I2:
2401                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2402                         break;
2403                 case CEE_CONV_U1:
2404                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2405                         break;
2406                 case CEE_CONV_U2:
2407                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2408                         break;
2409                 case CEE_CONV_U8:
2410                 case CEE_CONV_U:
2411                         /* Clean out the upper word */
2412                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2413                         break;
2414                 case CEE_CONV_I8:
2415                 case CEE_CONV_I:
2416                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2417                         break;
2418                 case OP_COMPARE:
2419                 case OP_LCOMPARE:
2420                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2421                         break;
2422                 case OP_COMPARE_IMM:
2423                         g_assert (amd64_is_imm32 (ins->inst_imm));
2424                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2425                         break;
2426                 case OP_X86_COMPARE_REG_MEMBASE:
2427                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2428                         break;
2429                 case OP_X86_TEST_NULL:
2430                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2431                         break;
2432                 case OP_AMD64_TEST_NULL:
2433                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2434                         break;
2435                 case OP_X86_ADD_MEMBASE_IMM:
2436                         /* FIXME: Make a 64 version too */
2437                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2438                         break;
2439                 case OP_X86_ADD_MEMBASE:
2440                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2441                         break;
2442                 case OP_X86_SUB_MEMBASE_IMM:
2443                         g_assert (amd64_is_imm32 (ins->inst_imm));
2444                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2445                         break;
2446                 case OP_X86_SUB_MEMBASE:
2447                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2448                         break;
2449                 case OP_X86_INC_MEMBASE:
2450                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2451                         break;
2452                 case OP_X86_INC_REG:
2453                         amd64_inc_reg_size (code, ins->dreg, 4);
2454                         break;
2455                 case OP_X86_DEC_MEMBASE:
2456                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2457                         break;
2458                 case OP_X86_DEC_REG:
2459                         amd64_dec_reg_size (code, ins->dreg, 4);
2460                         break;
2461                 case OP_X86_MUL_MEMBASE:
2462                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2463                         break;
2464                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2465                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2466                         break;
2467                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2468                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2469                         break;
2470                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2471                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2472                         break;
2473                 case CEE_BREAK:
2474                         amd64_breakpoint (code);
2475                         break;
2476                 case OP_ADDCC:
2477                 case CEE_ADD:
2478                 case OP_LADD:
2479                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2480                         break;
2481                 case OP_ADC:
2482                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2483                         break;
2484                 case OP_ADD_IMM:
2485                         g_assert (amd64_is_imm32 (ins->inst_imm));
2486                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2487                         break;
2488                 case OP_ADC_IMM:
2489                         g_assert (amd64_is_imm32 (ins->inst_imm));
2490                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2491                         break;
2492                 case OP_SUBCC:
2493                 case CEE_SUB:
2494                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2495                         break;
2496                 case OP_SBB:
2497                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2498                         break;
2499                 case OP_SUB_IMM:
2500                         g_assert (amd64_is_imm32 (ins->inst_imm));
2501                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2502                         break;
2503                 case OP_SBB_IMM:
2504                         g_assert (amd64_is_imm32 (ins->inst_imm));
2505                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2506                         break;
2507                 case CEE_AND:
2508                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2509                         break;
2510                 case OP_AND_IMM:
2511                         g_assert (amd64_is_imm32 (ins->inst_imm));
2512                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2513                         break;
2514                 case CEE_MUL:
2515                 case OP_LMUL:
2516                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2517                         break;
2518                 case OP_MUL_IMM:
2519                 case OP_LMUL_IMM:
2520                 case OP_IMUL_IMM: {
2521                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2522
2523                         switch (ins->inst_imm) {
2524                         case 2:
2525                                 /* MOV r1, r2 */
2526                                 /* ADD r1, r1 */
2527                                 if (ins->dreg != ins->sreg1)
2528                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2529                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2530                                 break;
2531                         case 3:
2532                                 /* LEA r1, [r2 + r2*2] */
2533                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2534                                 break;
2535                         case 5:
2536                                 /* LEA r1, [r2 + r2*4] */
2537                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2538                                 break;
2539                         case 6:
2540                                 /* LEA r1, [r2 + r2*2] */
2541                                 /* ADD r1, r1          */
2542                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2543                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2544                                 break;
2545                         case 9:
2546                                 /* LEA r1, [r2 + r2*8] */
2547                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2548                                 break;
2549                         case 10:
2550                                 /* LEA r1, [r2 + r2*4] */
2551                                 /* ADD r1, r1          */
2552                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2553                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2554                                 break;
2555                         case 12:
2556                                 /* LEA r1, [r2 + r2*2] */
2557                                 /* SHL r1, 2           */
2558                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2559                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2560                                 break;
2561                         case 25:
2562                                 /* LEA r1, [r2 + r2*4] */
2563                                 /* LEA r1, [r1 + r1*4] */
2564                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2565                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2566                                 break;
2567                         case 100:
2568                                 /* LEA r1, [r2 + r2*4] */
2569                                 /* SHL r1, 2           */
2570                                 /* LEA r1, [r1 + r1*4] */
2571                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2572                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2573                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2574                                 break;
2575                         default:
2576                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2577                                 break;
2578                         }
2579                         break;
2580                 }
2581                 case CEE_DIV:
2582                 case OP_LDIV:
2583                         amd64_cdq (code);
2584                         amd64_div_reg (code, ins->sreg2, TRUE);
2585                         break;
2586                 case CEE_DIV_UN:
2587                 case OP_LDIV_UN:
2588                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2589                         amd64_div_reg (code, ins->sreg2, FALSE);
2590                         break;
2591                 case CEE_REM:
2592                 case OP_LREM:
2593                         amd64_cdq (code);
2594                         amd64_div_reg (code, ins->sreg2, TRUE);
2595                         break;
2596                 case CEE_REM_UN:
2597                 case OP_LREM_UN:
2598                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2599                         amd64_div_reg (code, ins->sreg2, FALSE);
2600                         break;
2601                 case OP_LMUL_OVF:
2602                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2603                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2604                         break;
2605                 case CEE_OR:
2606                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2607                         break;
2608                 case OP_OR_IMM
2609 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2610                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2611                         break;
2612                 case CEE_XOR:
2613                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2614                         break;
2615                 case OP_XOR_IMM:
2616                         g_assert (amd64_is_imm32 (ins->inst_imm));
2617                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2618                         break;
2619                 case CEE_SHL:
2620                 case OP_LSHL:
2621                         g_assert (ins->sreg2 == AMD64_RCX);
2622                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2623                         break;
2624                 case CEE_SHR:
2625                 case OP_LSHR:
2626                         g_assert (ins->sreg2 == AMD64_RCX);
2627                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2628                         break;
2629                 case OP_SHR_IMM:
2630                         g_assert (amd64_is_imm32 (ins->inst_imm));
2631                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2632                         break;
2633                 case OP_LSHR_IMM:
2634                         g_assert (amd64_is_imm32 (ins->inst_imm));
2635                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2636                         break;
2637                 case OP_SHR_UN_IMM:
2638                         g_assert (amd64_is_imm32 (ins->inst_imm));
2639                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2640                         break;
2641                 case OP_LSHR_UN_IMM:
2642                         g_assert (amd64_is_imm32 (ins->inst_imm));
2643                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2644                         break;
2645                 case CEE_SHR_UN:
2646                         g_assert (ins->sreg2 == AMD64_RCX);
2647                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2648                         break;
2649                 case OP_LSHR_UN:
2650                         g_assert (ins->sreg2 == AMD64_RCX);
2651                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2652                         break;
2653                 case OP_SHL_IMM:
2654                         g_assert (amd64_is_imm32 (ins->inst_imm));
2655                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2656                         break;
2657                 case OP_LSHL_IMM:
2658                         g_assert (amd64_is_imm32 (ins->inst_imm));
2659                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2660                         break;
2661
2662                 case OP_IADDCC:
2663                 case OP_IADD:
2664                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2665                         break;
2666                 case OP_IADC:
2667                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2668                         break;
2669                 case OP_IADD_IMM:
2670                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2671                         break;
2672                 case OP_IADC_IMM:
2673                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2674                         break;
2675                 case OP_ISUBCC:
2676                 case OP_ISUB:
2677                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2678                         break;
2679                 case OP_ISBB:
2680                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2681                         break;
2682                 case OP_ISUB_IMM:
2683                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2684                         break;
2685                 case OP_ISBB_IMM:
2686                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2687                         break;
2688                 case OP_IAND:
2689                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2690                         break;
2691                 case OP_IAND_IMM:
2692                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2693                         break;
2694                 case OP_IOR:
2695                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2696                         break;
2697                 case OP_IOR_IMM:
2698                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2699                         break;
2700                 case OP_IXOR:
2701                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2702                         break;
2703                 case OP_IXOR_IMM:
2704                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2705                         break;
2706                 case OP_INEG:
2707                         amd64_neg_reg_size (code, ins->sreg1, 4);
2708                         break;
2709                 case OP_INOT:
2710                         amd64_not_reg_size (code, ins->sreg1, 4);
2711                         break;
2712                 case OP_ISHL:
2713                         g_assert (ins->sreg2 == AMD64_RCX);
2714                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2715                         break;
2716                 case OP_ISHR:
2717                         g_assert (ins->sreg2 == AMD64_RCX);
2718                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2719                         break;
2720                 case OP_ISHR_IMM:
2721                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2722                         break;
2723                 case OP_ISHR_UN_IMM:
2724                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2725                         break;
2726                 case OP_ISHR_UN:
2727                         g_assert (ins->sreg2 == AMD64_RCX);
2728                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2729                         break;
2730                 case OP_ISHL_IMM:
2731                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2732                         break;
2733                 case OP_IMUL:
2734                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2735                         break;
2736                 case OP_IMUL_OVF:
2737                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2738                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2739                         break;
2740                 case OP_IMUL_OVF_UN:
2741                 case OP_LMUL_OVF_UN: {
2742                         /* the mul operation and the exception check should most likely be split */
2743                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2744                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2745                         /*g_assert (ins->sreg2 == X86_EAX);
2746                         g_assert (ins->dreg == X86_EAX);*/
2747                         if (ins->sreg2 == X86_EAX) {
2748                                 non_eax_reg = ins->sreg1;
2749                         } else if (ins->sreg1 == X86_EAX) {
2750                                 non_eax_reg = ins->sreg2;
2751                         } else {
2752                                 /* no need to save since we're going to store to it anyway */
2753                                 if (ins->dreg != X86_EAX) {
2754                                         saved_eax = TRUE;
2755                                         amd64_push_reg (code, X86_EAX);
2756                                 }
2757                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2758                                 non_eax_reg = ins->sreg2;
2759                         }
2760                         if (ins->dreg == X86_EDX) {
2761                                 if (!saved_eax) {
2762                                         saved_eax = TRUE;
2763                                         amd64_push_reg (code, X86_EAX);
2764                                 }
2765                         } else {
2766                                 saved_edx = TRUE;
2767                                 amd64_push_reg (code, X86_EDX);
2768                         }
2769                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2770                         /* save before the check since pop and mov don't change the flags */
2771                         if (ins->dreg != X86_EAX)
2772                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2773                         if (saved_edx)
2774                                 amd64_pop_reg (code, X86_EDX);
2775                         if (saved_eax)
2776                                 amd64_pop_reg (code, X86_EAX);
2777                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2778                         break;
2779                 }
2780                 case OP_IDIV:
2781                         amd64_cdq_size (code, 4);
2782                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2783                         break;
2784                 case OP_IDIV_UN:
2785                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2786                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2787                         break;
2788                 case OP_IREM:
2789                         amd64_cdq_size (code, 4);
2790                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2791                         break;
2792                 case OP_IREM_UN:
2793                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2794                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2795                         break;
2796                 case OP_ICOMPARE:
2797                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2798                         break;
2799                 case OP_ICOMPARE_IMM:
2800                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2801                         break;
2802                 case OP_IBEQ:
2803                 case OP_IBLT:
2804                 case OP_IBGT:
2805                 case OP_IBGE:
2806                 case OP_IBLE:
2807                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2808                         break;
2809                 case OP_IBNE_UN:
2810                 case OP_IBLT_UN:
2811                 case OP_IBGT_UN:
2812                 case OP_IBGE_UN:
2813                 case OP_IBLE_UN:
2814                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2815                         break;
2816                 case OP_COND_EXC_IOV:
2817                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2818                                                                                 TRUE, ins->inst_p1);
2819                         break;
2820                 case OP_COND_EXC_IC:
2821                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2822                                                                                 FALSE, ins->inst_p1);
2823                         break;
2824                 case CEE_NOT:
2825                         amd64_not_reg (code, ins->sreg1);
2826                         break;
2827                 case CEE_NEG:
2828                         amd64_neg_reg (code, ins->sreg1);
2829                         break;
2830                 case OP_SEXT_I1:
2831                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2832                         break;
2833                 case OP_SEXT_I2:
2834                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2835                         break;
2836                 case OP_SEXT_I4:
2837                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2838                         break;
2839                 case OP_ICONST:
2840                 case OP_I8CONST:
2841                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2842                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2843                         else
2844                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2845                         break;
2846                 case OP_AOTCONST:
2847                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2848                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2849                         break;
2850                 case CEE_CONV_I4:
2851                 case CEE_CONV_U4:
2852                 case OP_MOVE:
2853                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2854                         break;
2855                 case OP_AMD64_SET_XMMREG_R4: {
2856                         if (use_sse2) {
2857                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2858                         }
2859                         else {
2860                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2861                                 /* ins->dreg is set to -1 by the reg allocator */
2862                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2863                         }
2864                         break;
2865                 }
2866                 case OP_AMD64_SET_XMMREG_R8: {
2867                         if (use_sse2) {
2868                                 if (ins->dreg != ins->sreg1)
2869                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2870                         }
2871                         else {
2872                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2873                                 /* ins->dreg is set to -1 by the reg allocator */
2874                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2875                         }
2876                         break;
2877                 }
2878                 case CEE_JMP: {
2879                         /*
2880                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2881                          * Keep in sync with the code in emit_epilog.
2882                          */
2883                         int pos = 0, i;
2884
2885                         /* FIXME: no tracing support... */
2886                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2887                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2888
2889                         g_assert (!cfg->method->save_lmf);
2890
2891                         code = emit_load_volatile_arguments (cfg, code);
2892
2893                         if (cfg->arch.omit_fp) {
2894                                 guint32 save_offset = 0;
2895                                 /* Pop callee-saved registers */
2896                                 for (i = 0; i < AMD64_NREG; ++i)
2897                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2898                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2899                                                 save_offset += 8;
2900                                         }
2901                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2902                         }
2903                         else {
2904                                 for (i = 0; i < AMD64_NREG; ++i)
2905                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2906                                                 pos -= sizeof (gpointer);
2907
2908                                 if (pos)
2909                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2910
2911                                 /* Pop registers in reverse order */
2912                                 for (i = AMD64_NREG - 1; i > 0; --i)
2913                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2914                                                 amd64_pop_reg (code, i);
2915                                         }
2916
2917                                 amd64_leave (code);
2918                         }
2919
2920                         offset = code - cfg->native_code;
2921                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2922                         if (cfg->compile_aot)
2923                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2924                         else
2925                                 amd64_set_reg_template (code, AMD64_R11);
2926                         amd64_jump_reg (code, AMD64_R11);
2927                         break;
2928                 }
2929                 case OP_CHECK_THIS:
2930                         /* ensure ins->sreg1 is not NULL */
2931                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2932                         break;
2933                 case OP_ARGLIST: {
2934                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2935                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2936                         break;
2937                 }
2938                 case OP_FCALL:
2939                 case OP_LCALL:
2940                 case OP_VCALL:
2941                 case OP_VOIDCALL:
2942                 case CEE_CALL:
2943                         call = (MonoCallInst*)ins;
2944                         /*
2945                          * The AMD64 ABI forces callers to know about varargs.
2946                          */
2947                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2948                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2949                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2950                                 /*
2951                                  * Since the unmanaged calling convention doesn't contain a
2952                                  * 'vararg' entry, we have to treat every pinvoke call as a
2953                                  * potential vararg call.
2954                                  */
2955                                 guint32 nregs, i;
2956                                 nregs = 0;
2957                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2958                                         if (call->used_fregs & (1 << i))
2959                                                 nregs ++;
2960                                 if (!nregs)
2961                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2962                                 else
2963                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2964                         }
2965
2966                         if (ins->flags & MONO_INST_HAS_METHOD)
2967                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2968                         else
2969                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2970                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2971                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2972                         code = emit_move_return_value (cfg, ins, code);
2973                         break;
2974                 case OP_FCALL_REG:
2975                 case OP_LCALL_REG:
2976                 case OP_VCALL_REG:
2977                 case OP_VOIDCALL_REG:
2978                 case OP_CALL_REG:
2979                         call = (MonoCallInst*)ins;
2980
2981                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2982                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2983                                 ins->sreg1 = AMD64_R11;
2984                         }
2985
2986                         /*
2987                          * The AMD64 ABI forces callers to know about varargs.
2988                          */
2989                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2990                                 if (ins->sreg1 == AMD64_RAX) {
2991                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2992                                         ins->sreg1 = AMD64_R11;
2993                                 }
2994                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2995                         }
2996                         amd64_call_reg (code, ins->sreg1);
2997                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2998                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2999                         code = emit_move_return_value (cfg, ins, code);
3000                         break;
3001                 case OP_FCALL_MEMBASE:
3002                 case OP_LCALL_MEMBASE:
3003                 case OP_VCALL_MEMBASE:
3004                 case OP_VOIDCALL_MEMBASE:
3005                 case OP_CALL_MEMBASE:
3006                         call = (MonoCallInst*)ins;
3007
3008                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3009                                 /*
3010                                  * Can't use R11 because it is clobbered by the trampoline
3011                                  * code, and the reg value is needed by get_vcall_slot_addr.
3012                                  */
3013                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3014                                 ins->sreg1 = AMD64_RAX;
3015                         }
3016
3017                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3018                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3019                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3020                         code = emit_move_return_value (cfg, ins, code);
3021                         break;
3022                 case OP_OUTARG:
3023                 case OP_X86_PUSH:
3024                         amd64_push_reg (code, ins->sreg1);
3025                         break;
3026                 case OP_X86_PUSH_IMM:
3027                         g_assert (amd64_is_imm32 (ins->inst_imm));
3028                         amd64_push_imm (code, ins->inst_imm);
3029                         break;
3030                 case OP_X86_PUSH_MEMBASE:
3031                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3032                         break;
3033                 case OP_X86_PUSH_OBJ:
3034                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3035                         amd64_push_reg (code, AMD64_RDI);
3036                         amd64_push_reg (code, AMD64_RSI);
3037                         amd64_push_reg (code, AMD64_RCX);
3038                         if (ins->inst_offset)
3039                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3040                         else
3041                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3042                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3043                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3044                         amd64_cld (code);
3045                         amd64_prefix (code, X86_REP_PREFIX);
3046                         amd64_movsd (code);
3047                         amd64_pop_reg (code, AMD64_RCX);
3048                         amd64_pop_reg (code, AMD64_RSI);
3049                         amd64_pop_reg (code, AMD64_RDI);
3050                         break;
3051                 case OP_X86_LEA:
3052                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3053                         break;
3054                 case OP_X86_LEA_MEMBASE:
3055                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3056                         break;
3057                 case OP_X86_XCHG:
3058                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3059                         break;
3060                 case OP_LOCALLOC:
3061                         /* keep alignment */
3062                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3063                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3064                         code = mono_emit_stack_alloc (code, ins);
3065                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3066                         break;
3067                 case CEE_RET:
3068                         amd64_ret (code);
3069                         break;
3070                 case CEE_THROW: {
3071                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3072                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3073                                              (gpointer)"mono_arch_throw_exception");
3074                         break;
3075                 }
3076                 case OP_RETHROW: {
3077                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3078                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3079                                              (gpointer)"mono_arch_rethrow_exception");
3080                         break;
3081                 }
3082                 case OP_CALL_HANDLER:
3083                         /* Align stack */
3084                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3085                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3086                         amd64_call_imm (code, 0);
3087                         /* Restore stack alignment */
3088                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3089                         break;
3090                 case OP_LABEL:
3091                         ins->inst_c0 = code - cfg->native_code;
3092                         break;
3093                 case CEE_NOP:
3094                         break;
3095                 case CEE_BR:
3096                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3097                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3098                         //break;
3099                         if (ins->flags & MONO_INST_BRLABEL) {
3100                                 if (ins->inst_i0->inst_c0) {
3101                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3102                                 } else {
3103                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3104                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3105                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3106                                                 x86_jump8 (code, 0);
3107                                         else
3108                                                 x86_jump32 (code, 0);
3109                                 }
3110                         } else {
3111                                 if (ins->inst_target_bb->native_offset) {
3112                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3113                                 } else {
3114                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3115                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3116                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3117                                                 x86_jump8 (code, 0);
3118                                         else
3119                                                 x86_jump32 (code, 0);
3120                                 }
3121                         }
3122                         break;
3123                 case OP_BR_REG:
3124                         amd64_jump_reg (code, ins->sreg1);
3125                         break;
3126                 case OP_CEQ:
3127                 case OP_ICEQ:
3128                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3129                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3130                         break;
3131                 case OP_CLT:
3132                 case OP_ICLT:
3133                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3134                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3135                         break;
3136                 case OP_CLT_UN:
3137                 case OP_ICLT_UN:
3138                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3139                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3140                         break;
3141                 case OP_CGT:
3142                 case OP_ICGT:
3143                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3144                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3145                         break;
3146                 case OP_CGT_UN:
3147                 case OP_ICGT_UN:
3148                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3149                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3150                         break;
3151                 case OP_COND_EXC_EQ:
3152                 case OP_COND_EXC_NE_UN:
3153                 case OP_COND_EXC_LT:
3154                 case OP_COND_EXC_LT_UN:
3155                 case OP_COND_EXC_GT:
3156                 case OP_COND_EXC_GT_UN:
3157                 case OP_COND_EXC_GE:
3158                 case OP_COND_EXC_GE_UN:
3159                 case OP_COND_EXC_LE:
3160                 case OP_COND_EXC_LE_UN:
3161                 case OP_COND_EXC_OV:
3162                 case OP_COND_EXC_NO:
3163                 case OP_COND_EXC_C:
3164                 case OP_COND_EXC_NC:
3165                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3166                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3167                         break;
3168                 case CEE_BEQ:
3169                 case CEE_BNE_UN:
3170                 case CEE_BLT:
3171                 case CEE_BLT_UN:
3172                 case CEE_BGT:
3173                 case CEE_BGT_UN:
3174                 case CEE_BGE:
3175                 case CEE_BGE_UN:
3176                 case CEE_BLE:
3177                 case CEE_BLE_UN:
3178                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3179                         break;
3180
3181                 /* floating point opcodes */
3182                 case OP_R8CONST: {
3183                         double d = *(double *)ins->inst_p0;
3184
3185                         if (use_sse2) {
3186                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3187                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3188                                 }
3189                                 else {
3190                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3191                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3192                                 }
3193                         }
3194                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3195                                 amd64_fldz (code);
3196                         } else if (d == 1.0) {
3197                                 x86_fld1 (code);
3198                         } else {
3199                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3200                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3201                         }
3202                         break;
3203                 }
3204                 case OP_R4CONST: {
3205                         float f = *(float *)ins->inst_p0;
3206
3207                         if (use_sse2) {
3208                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3209                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3210                                 }
3211                                 else {
3212                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3213                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3214                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3215                                 }
3216                         }
3217                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3218                                 amd64_fldz (code);
3219                         } else if (f == 1.0) {
3220                                 x86_fld1 (code);
3221                         } else {
3222                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3223                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3224                         }
3225                         break;
3226                 }
3227                 case OP_STORER8_MEMBASE_REG:
3228                         if (use_sse2)
3229                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3230                         else
3231                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3232                         break;
3233                 case OP_LOADR8_SPILL_MEMBASE:
3234                         if (use_sse2)
3235                                 g_assert_not_reached ();
3236                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3237                         amd64_fxch (code, 1);
3238                         break;
3239                 case OP_LOADR8_MEMBASE:
3240                         if (use_sse2)
3241                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3242                         else
3243                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3244                         break;
3245                 case OP_STORER4_MEMBASE_REG:
3246                         if (use_sse2) {
3247                                 /* This requires a double->single conversion */
3248                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3249                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3250                         }
3251                         else
3252                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3253                         break;
3254                 case OP_LOADR4_MEMBASE:
3255                         if (use_sse2) {
3256                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3257                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3258                         }
3259                         else
3260                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3261                         break;
3262                 case CEE_CONV_R4: /* FIXME: change precision */
3263                 case CEE_CONV_R8:
3264                         if (use_sse2)
3265                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3266                         else {
3267                                 amd64_push_reg (code, ins->sreg1);
3268                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3269                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3270                         }
3271                         break;
3272                 case CEE_CONV_R_UN:
3273                         /* Emulated */
3274                         g_assert_not_reached ();
3275                         break;
3276                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3277                 case OP_LCONV_TO_R8:
3278                         if (use_sse2)
3279                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3280                         else {
3281                                 amd64_push_reg (code, ins->sreg1);
3282                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3283                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3284                         }
3285                         break;
3286                 case OP_X86_FP_LOAD_I8:
3287                         if (use_sse2)
3288                                 g_assert_not_reached ();
3289                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3290                         break;
3291                 case OP_X86_FP_LOAD_I4:
3292                         if (use_sse2)
3293                                 g_assert_not_reached ();
3294                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3295                         break;
3296                 case OP_FCONV_TO_I1:
3297                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3298                         break;
3299                 case OP_FCONV_TO_U1:
3300                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3301                         break;
3302                 case OP_FCONV_TO_I2:
3303                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3304                         break;
3305                 case OP_FCONV_TO_U2:
3306                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3307                         break;
3308                 case OP_FCONV_TO_I4:
3309                 case OP_FCONV_TO_I:
3310                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3311                         break;
3312                 case OP_FCONV_TO_I8:
3313                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3314                         break;
3315                 case OP_LCONV_TO_R_UN: {
3316                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3317                         guint8 *br;
3318
3319                         if (use_sse2)
3320                                 g_assert_not_reached ();
3321
3322                         /* load 64bit integer to FP stack */
3323                         amd64_push_imm (code, 0);
3324                         amd64_push_reg (code, ins->sreg2);
3325                         amd64_push_reg (code, ins->sreg1);
3326                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3327                         /* store as 80bit FP value */
3328                         x86_fst80_membase (code, AMD64_RSP, 0);
3329
3330                         /* test if lreg is negative */
3331                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3332                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3333
3334                         /* add correction constant mn */
3335                         x86_fld80_mem (code, mn);
3336                         x86_fld80_membase (code, AMD64_RSP, 0);
3337                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3338                         x86_fst80_membase (code, AMD64_RSP, 0);
3339
3340                         amd64_patch (br, code);
3341
3342                         x86_fld80_membase (code, AMD64_RSP, 0);
3343                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3344
3345                         break;
3346                 }
3347                 case CEE_CONV_OVF_U4:
3348                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3349                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3350                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3351                         break;
3352                 case CEE_CONV_OVF_I4_UN:
3353                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3354                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3355                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3356                         break;
3357                 case OP_FMOVE:
3358                         if (use_sse2 && (ins->dreg != ins->sreg1))
3359                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3360                         break;
3361                 case OP_FADD:
3362                         if (use_sse2)
3363                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3364                         else
3365                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3366                         break;
3367                 case OP_FSUB:
3368                         if (use_sse2)
3369                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3370                         else
3371                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3372                         break;
3373                 case OP_FMUL:
3374                         if (use_sse2)
3375                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3376                         else
3377                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3378                         break;
3379                 case OP_FDIV:
3380                         if (use_sse2)
3381                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3382                         else
3383                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3384                         break;
3385                 case OP_FNEG:
3386                         if (use_sse2) {
3387                                 static double r8_0 = -0.0;
3388
3389                                 g_assert (ins->sreg1 == ins->dreg);
3390
3391                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3392                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3393                         }
3394                         else
3395                                 amd64_fchs (code);
3396                         break;
3397                 case OP_SIN:
3398                         if (use_sse2) {
3399                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3400                         }
3401                         else {
3402                                 amd64_fsin (code);
3403                                 amd64_fldz (code);
3404                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3405                         }
3406                         break;
3407                 case OP_COS:
3408                         if (use_sse2) {
3409                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3410                         }
3411                         else {
3412                                 amd64_fcos (code);
3413                                 amd64_fldz (code);
3414                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3415                         }
3416                         break;
3417                 case OP_ABS:
3418                         if (use_sse2) {
3419                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3420                         }
3421                         else
3422                                 amd64_fabs (code);
3423                         break;
3424                 case OP_TAN: {
3425                         /*
3426                          * it really doesn't make sense to inline all this code,
3427                          * it's here just to show that things may not be as simple
3428                          * as they appear.
3429                          */
3430                         guchar *check_pos, *end_tan, *pop_jump;
3431                         if (use_sse2)
3432                                 g_assert_not_reached ();
3433                         amd64_push_reg (code, AMD64_RAX);
3434                         amd64_fptan (code);
3435                         amd64_fnstsw (code);
3436                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3437                         check_pos = code;
3438                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3439                         amd64_fstp (code, 0); /* pop the 1.0 */
3440                         end_tan = code;
3441                         x86_jump8 (code, 0);
3442                         amd64_fldpi (code);
3443                         amd64_fp_op (code, X86_FADD, 0);
3444                         amd64_fxch (code, 1);
3445                         x86_fprem1 (code);
3446                         amd64_fstsw (code);
3447                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3448                         pop_jump = code;
3449                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3450                         amd64_fstp (code, 1);
3451                         amd64_fptan (code);
3452                         amd64_patch (pop_jump, code);
3453                         amd64_fstp (code, 0); /* pop the 1.0 */
3454                         amd64_patch (check_pos, code);
3455                         amd64_patch (end_tan, code);
3456                         amd64_fldz (code);
3457                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3458                         amd64_pop_reg (code, AMD64_RAX);
3459                         break;
3460                 }
3461                 case OP_ATAN:
3462                         if (use_sse2)
3463                                 g_assert_not_reached ();
3464                         x86_fld1 (code);
3465                         amd64_fpatan (code);
3466                         amd64_fldz (code);
3467                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3468                         break;
3469                 case OP_SQRT:
3470                         if (use_sse2) {
3471                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3472                         }
3473                         else
3474                                 amd64_fsqrt (code);
3475                         break;
3476                 case OP_X86_FPOP:
3477                         if (!use_sse2)
3478                                 amd64_fstp (code, 0);
3479                         break;
3480                 case OP_FREM: {
3481                         guint8 *l1, *l2;
3482
3483                         if (use_sse2)
3484                                 g_assert_not_reached ();
3485                         amd64_push_reg (code, AMD64_RAX);
3486                         /* we need to exchange ST(0) with ST(1) */
3487                         amd64_fxch (code, 1);
3488
3489                         /* this requires a loop, because fprem somtimes
3490                          * returns a partial remainder */
3491                         l1 = code;
3492                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3493                         /* x86_fprem1 (code); */
3494                         amd64_fprem (code);
3495                         amd64_fnstsw (code);
3496                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3497                         l2 = code + 2;
3498                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3499
3500                         /* pop result */
3501                         amd64_fstp (code, 1);
3502
3503                         amd64_pop_reg (code, AMD64_RAX);
3504                         break;
3505                 }
3506                 case OP_FCOMPARE:
3507                         if (use_sse2) {
3508                                 /*
3509                                  * The two arguments are swapped because the fbranch instructions
3510                                  * depend on this for the non-sse case to work.
3511                                  */
3512                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3513                                 break;
3514                         }
3515                         if (cfg->opt & MONO_OPT_FCMOV) {
3516                                 amd64_fcomip (code, 1);
3517                                 amd64_fstp (code, 0);
3518                                 break;
3519                         }
3520                         /* this overwrites EAX */
3521                         EMIT_FPCOMPARE(code);
3522                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3523                         break;
3524                 case OP_FCEQ:
3525                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3526                                 /* zeroing the register at the start results in
3527                                  * shorter and faster code (we can also remove the widening op)
3528                                  */
3529                                 guchar *unordered_check;
3530                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3531
3532                                 if (use_sse2)
3533                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3534                                 else {
3535                                         amd64_fcomip (code, 1);
3536                                         amd64_fstp (code, 0);
3537                                 }
3538                                 unordered_check = code;
3539                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3540                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3541                                 amd64_patch (unordered_check, code);
3542                                 break;
3543                         }
3544                         if (ins->dreg != AMD64_RAX)
3545                                 amd64_push_reg (code, AMD64_RAX);
3546
3547                         EMIT_FPCOMPARE(code);
3548                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3549                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3550                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3551                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3552
3553                         if (ins->dreg != AMD64_RAX)
3554                                 amd64_pop_reg (code, AMD64_RAX);
3555                         break;
3556                 case OP_FCLT:
3557                 case OP_FCLT_UN:
3558                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3559                                 /* zeroing the register at the start results in
3560                                  * shorter and faster code (we can also remove the widening op)
3561                                  */
3562                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3563                                 if (use_sse2)
3564                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3565                                 else {
3566                                         amd64_fcomip (code, 1);
3567                                         amd64_fstp (code, 0);
3568                                 }
3569                                 if (ins->opcode == OP_FCLT_UN) {
3570                                         guchar *unordered_check = code;
3571                                         guchar *jump_to_end;
3572                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3573                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3574                                         jump_to_end = code;
3575                                         x86_jump8 (code, 0);
3576                                         amd64_patch (unordered_check, code);
3577                                         amd64_inc_reg (code, ins->dreg);
3578                                         amd64_patch (jump_to_end, code);
3579                                 } else {
3580                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3581                                 }
3582                                 break;
3583                         }
3584                         if (ins->dreg != AMD64_RAX)
3585                                 amd64_push_reg (code, AMD64_RAX);
3586
3587                         EMIT_FPCOMPARE(code);
3588                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3589                         if (ins->opcode == OP_FCLT_UN) {
3590                                 guchar *is_not_zero_check, *end_jump;
3591                                 is_not_zero_check = code;
3592                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3593                                 end_jump = code;
3594                                 x86_jump8 (code, 0);
3595                                 amd64_patch (is_not_zero_check, code);
3596                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3597
3598                                 amd64_patch (end_jump, code);
3599                         }
3600                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3601                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3602
3603                         if (ins->dreg != AMD64_RAX)
3604                                 amd64_pop_reg (code, AMD64_RAX);
3605                         break;
3606                 case OP_FCGT:
3607                 case OP_FCGT_UN:
3608                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3609                                 /* zeroing the register at the start results in
3610                                  * shorter and faster code (we can also remove the widening op)
3611                                  */
3612                                 guchar *unordered_check;
3613                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3614                                 if (use_sse2)
3615                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3616                                 else {
3617                                         amd64_fcomip (code, 1);
3618                                         amd64_fstp (code, 0);
3619                                 }
3620                                 if (ins->opcode == OP_FCGT) {
3621                                         unordered_check = code;
3622                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3623                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3624                                         amd64_patch (unordered_check, code);
3625                                 } else {
3626                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3627                                 }
3628                                 break;
3629                         }
3630                         if (ins->dreg != AMD64_RAX)
3631                                 amd64_push_reg (code, AMD64_RAX);
3632
3633                         EMIT_FPCOMPARE(code);
3634                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3635                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3636                         if (ins->opcode == OP_FCGT_UN) {
3637                                 guchar *is_not_zero_check, *end_jump;
3638                                 is_not_zero_check = code;
3639                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3640                                 end_jump = code;
3641                                 x86_jump8 (code, 0);
3642                                 amd64_patch (is_not_zero_check, code);
3643                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3644
3645                                 amd64_patch (end_jump, code);
3646                         }
3647                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3648                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3649
3650                         if (ins->dreg != AMD64_RAX)
3651                                 amd64_pop_reg (code, AMD64_RAX);
3652                         break;
3653                 case OP_FCLT_MEMBASE:
3654                 case OP_FCGT_MEMBASE:
3655                 case OP_FCLT_UN_MEMBASE:
3656                 case OP_FCGT_UN_MEMBASE:
3657                 case OP_FCEQ_MEMBASE: {
3658                         guchar *unordered_check, *jump_to_end;
3659                         int x86_cond;
3660                         g_assert (use_sse2);
3661
3662                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3663                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3664
3665                         switch (ins->opcode) {
3666                         case OP_FCEQ_MEMBASE:
3667                                 x86_cond = X86_CC_EQ;
3668                                 break;
3669                         case OP_FCLT_MEMBASE:
3670                         case OP_FCLT_UN_MEMBASE:
3671                                 x86_cond = X86_CC_LT;
3672                                 break;
3673                         case OP_FCGT_MEMBASE:
3674                         case OP_FCGT_UN_MEMBASE:
3675                                 x86_cond = X86_CC_GT;
3676                                 break;
3677                         default:
3678                                 g_assert_not_reached ();
3679                         }
3680
3681                         unordered_check = code;
3682                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3683                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3684
3685                         switch (ins->opcode) {
3686                         case OP_FCEQ_MEMBASE:
3687                         case OP_FCLT_MEMBASE:
3688                         case OP_FCGT_MEMBASE:
3689                                 amd64_patch (unordered_check, code);
3690                                 break;
3691                         case OP_FCLT_UN_MEMBASE:
3692                         case OP_FCGT_UN_MEMBASE:
3693                                 jump_to_end = code;
3694                                 x86_jump8 (code, 0);
3695                                 amd64_patch (unordered_check, code);
3696                                 amd64_inc_reg (code, ins->dreg);
3697                                 amd64_patch (jump_to_end, code);
3698                                 break;
3699                         default:
3700                                 break;
3701                         }
3702                         break;
3703                 }
3704                 case OP_FBEQ:
3705                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3706                                 guchar *jump = code;
3707                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3708                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3709                                 amd64_patch (jump, code);
3710                                 break;
3711                         }
3712                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3713                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3714                         break;
3715                 case OP_FBNE_UN:
3716                         /* Branch if C013 != 100 */
3717                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3718                                 /* branch if !ZF or (PF|CF) */
3719                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3720                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3721                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3722                                 break;
3723                         }
3724                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3725                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3726                         break;
3727                 case OP_FBLT:
3728                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3729                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3730                                 break;
3731                         }
3732                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3733                         break;
3734                 case OP_FBLT_UN:
3735                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3736                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3737                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3738                                 break;
3739                         }
3740                         if (ins->opcode == OP_FBLT_UN) {
3741                                 guchar *is_not_zero_check, *end_jump;
3742                                 is_not_zero_check = code;
3743                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3744                                 end_jump = code;
3745                                 x86_jump8 (code, 0);
3746                                 amd64_patch (is_not_zero_check, code);
3747                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3748
3749                                 amd64_patch (end_jump, code);
3750                         }
3751                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3752                         break;
3753                 case OP_FBGT:
3754                 case OP_FBGT_UN:
3755                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3756                                 if (ins->opcode == OP_FBGT) {
3757                                         guchar *br1;
3758
3759                                         /* skip branch if C1=1 */
3760                                         br1 = code;
3761                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3762                                         /* branch if (C0 | C3) = 1 */
3763                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3764                                         amd64_patch (br1, code);
3765                                         break;
3766                                 } else {
3767                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3768                                 }
3769                                 break;
3770                         }
3771                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3772                         if (ins->opcode == OP_FBGT_UN) {
3773                                 guchar *is_not_zero_check, *end_jump;
3774                                 is_not_zero_check = code;
3775                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3776                                 end_jump = code;
3777                                 x86_jump8 (code, 0);
3778                                 amd64_patch (is_not_zero_check, code);
3779                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3780
3781                                 amd64_patch (end_jump, code);
3782                         }
3783                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3784                         break;
3785                 case OP_FBGE:
3786                         /* Branch if C013 == 100 or 001 */
3787                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3788                                 guchar *br1;
3789
3790                                 /* skip branch if C1=1 */
3791                                 br1 = code;
3792                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3793                                 /* branch if (C0 | C3) = 1 */
3794                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3795                                 amd64_patch (br1, code);
3796                                 break;
3797                         }
3798                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3799                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3800                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3801                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3802                         break;
3803                 case OP_FBGE_UN:
3804                         /* Branch if C013 == 000 */
3805                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3806                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3807                                 break;
3808                         }
3809                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3810                         break;
3811                 case OP_FBLE:
3812                         /* Branch if C013=000 or 100 */
3813                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3814                                 guchar *br1;
3815
3816                                 /* skip branch if C1=1 */
3817                                 br1 = code;
3818                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3819                                 /* branch if C0=0 */
3820                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3821                                 amd64_patch (br1, code);
3822                                 break;
3823                         }
3824                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3825                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3826                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3827                         break;
3828                 case OP_FBLE_UN:
3829                         /* Branch if C013 != 001 */
3830                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3831                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3832                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3833                                 break;
3834                         }
3835                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3836                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3837                         break;
3838                 case CEE_CKFINITE: {
3839                         if (use_sse2) {
3840                                 /* Transfer value to the fp stack */
3841                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3842                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3843                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3844                         }
3845                         amd64_push_reg (code, AMD64_RAX);
3846                         amd64_fxam (code);
3847                         amd64_fnstsw (code);
3848                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3849                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3850                         amd64_pop_reg (code, AMD64_RAX);
3851                         if (use_sse2) {
3852                                 amd64_fstp (code, 0);
3853                         }
3854                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3855                         if (use_sse2)
3856                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3857                         break;
3858                 }
3859                 case OP_TLS_GET: {
3860                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3861                         break;
3862                 }
3863                 case OP_MEMORY_BARRIER: {
3864                         /* Not needed on amd64 */
3865                         break;
3866                 }
3867                 case OP_ATOMIC_ADD_I4:
3868                 case OP_ATOMIC_ADD_I8: {
3869                         int dreg = ins->dreg;
3870                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3871
3872                         if (dreg == ins->inst_basereg)
3873                                 dreg = AMD64_R11;
3874
3875                         if (dreg != ins->sreg2)
3876                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3877
3878                         x86_prefix (code, X86_LOCK_PREFIX);
3879                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3880
3881                         if (dreg != ins->dreg)
3882                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3883
3884                         break;
3885                 }
3886                 case OP_ATOMIC_ADD_NEW_I4:
3887                 case OP_ATOMIC_ADD_NEW_I8: {
3888                         int dreg = ins->dreg;
3889                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3890
3891                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3892                                 dreg = AMD64_R11;
3893
3894                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3895                         amd64_prefix (code, X86_LOCK_PREFIX);
3896                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3897                         /* dreg contains the old value, add with sreg2 value */
3898                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3899
3900                         if (ins->dreg != dreg)
3901                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3902
3903                         break;
3904                 }
3905                 case OP_ATOMIC_EXCHANGE_I4:
3906                 case OP_ATOMIC_EXCHANGE_I8: {
3907                         guchar *br[2];
3908                         int sreg2 = ins->sreg2;
3909                         int breg = ins->inst_basereg;
3910                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3911
3912                         /*
3913                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3914                          * an explanation of how this works.
3915                          */
3916
3917                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3918                          * hack to overcome limits in x86 reg allocator
3919                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3920                          */
3921                         /* The pushes invalidate rsp */
3922                         if ((breg == AMD64_RAX) || (breg == AMD64_RSP)) {
3923                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
3924                                 breg = AMD64_R11;
3925                         }
3926
3927                         if (ins->dreg != AMD64_RAX)
3928                                 amd64_push_reg (code, AMD64_RAX);
3929
3930                         /* We need the EAX reg for the cmpxchg */
3931                         if (ins->sreg2 == AMD64_RAX) {
3932                                 amd64_push_reg (code, AMD64_RDX);
3933                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3934                                 sreg2 = AMD64_RDX;
3935                         }
3936
3937                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3938
3939                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3940                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3941                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3942                         amd64_patch (br [1], br [0]);
3943
3944                         if (ins->dreg != AMD64_RAX) {
3945                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3946                                 amd64_pop_reg (code, AMD64_RAX);
3947                         }
3948
3949                         if (ins->sreg2 != sreg2)
3950                                 amd64_pop_reg (code, AMD64_RDX);
3951
3952                         break;
3953                 }
3954                 default:
3955                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3956                         g_assert_not_reached ();
3957                 }
3958
3959                 if ((code - cfg->native_code - offset) > max_len) {
3960                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3961                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3962                         g_assert_not_reached ();
3963                 }
3964
3965                 cpos += max_len;
3966
3967                 last_ins = ins;
3968                 last_offset = offset;
3969
3970                 ins = ins->next;
3971         }
3972
3973         cfg->code_len = code - cfg->native_code;
3974 }
3975
3976 void
3977 mono_arch_register_lowlevel_calls (void)
3978 {
3979 }
3980
3981 void
3982 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3983 {
3984         MonoJumpInfo *patch_info;
3985         gboolean compile_aot = !run_cctors;
3986
3987         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3988                 unsigned char *ip = patch_info->ip.i + code;
3989                 const unsigned char *target;
3990
3991                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3992
3993                 if (compile_aot) {
3994                         switch (patch_info->type) {
3995                         case MONO_PATCH_INFO_BB:
3996                         case MONO_PATCH_INFO_LABEL:
3997                                 break;
3998                         default:
3999                                 /* No need to patch these */
4000                                 continue;
4001                         }
4002                 }
4003
4004                 switch (patch_info->type) {
4005                 case MONO_PATCH_INFO_NONE:
4006                         continue;
4007                 case MONO_PATCH_INFO_METHOD_REL:
4008                 case MONO_PATCH_INFO_R8:
4009                 case MONO_PATCH_INFO_R4:
4010                         g_assert_not_reached ();
4011                         continue;
4012                 case MONO_PATCH_INFO_BB:
4013                         break;
4014                 default:
4015                         break;
4016                 }
4017
4018                 /*
4019                  * Debug code to help track down problems where the target of a near call is
4020                  * is not valid.
4021                  */
4022                 if (amd64_is_near_call (ip)) {
4023                         gint64 disp = (guint8*)target - (guint8*)ip;
4024
4025                         if (!amd64_is_imm32 (disp)) {
4026                                 printf ("TYPE: %d\n", patch_info->type);
4027                                 switch (patch_info->type) {
4028                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4029                                         printf ("V: %s\n", patch_info->data.name);
4030                                         break;
4031                                 case MONO_PATCH_INFO_METHOD_JUMP:
4032                                 case MONO_PATCH_INFO_METHOD:
4033                                         printf ("V: %s\n", patch_info->data.method->name);
4034                                         break;
4035                                 default:
4036                                         break;
4037                                 }
4038                         }
4039                 }
4040
4041                 amd64_patch (ip, (gpointer)target);
4042         }
4043 }
4044
4045 guint8 *
4046 mono_arch_emit_prolog (MonoCompile *cfg)
4047 {
4048         MonoMethod *method = cfg->method;
4049         MonoBasicBlock *bb;
4050         MonoMethodSignature *sig;
4051         MonoInst *inst;
4052         int alloc_size, pos, max_offset, i, quad;
4053         guint8 *code;
4054         CallInfo *cinfo;
4055         gint32 lmf_offset = cfg->arch.lmf_offset;
4056
4057         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4058         code = cfg->native_code = g_malloc (cfg->code_size);
4059
4060         /* Amount of stack space allocated by register saving code */
4061         pos = 0;
4062
4063         /*
4064          * The prolog consists of the following parts:
4065          * FP present:
4066          * - push rbp, mov rbp, rsp
4067          * - save callee saved regs using pushes
4068          * - allocate frame
4069          * - save lmf if needed
4070          * FP not present:
4071          * - allocate frame
4072          * - save lmf if needed
4073          * - save callee saved regs using moves
4074          */
4075
4076         if (!cfg->arch.omit_fp) {
4077                 amd64_push_reg (code, AMD64_RBP);
4078                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4079         }
4080
4081         /* Save callee saved registers */
4082         if (!cfg->arch.omit_fp && !method->save_lmf) {
4083                 for (i = 0; i < AMD64_NREG; ++i)
4084                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4085                                 amd64_push_reg (code, i);
4086                                 pos += sizeof (gpointer);
4087                         }
4088         }
4089
4090         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4091
4092         alloc_size -= pos;
4093
4094         if (cfg->arch.omit_fp)
4095                 /*
4096                  * On enter, the stack is misaligned by the the pushing of the return
4097                  * address. It is either made aligned by the pushing of %rbp, or by
4098                  * this.
4099                  */
4100                 alloc_size += 8;
4101
4102         cfg->arch.stack_alloc_size = alloc_size;
4103
4104         /* Allocate stack frame */
4105         if (alloc_size) {
4106                 /* See mono_emit_stack_alloc */
4107 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4108                 guint32 remaining_size = alloc_size;
4109                 while (remaining_size >= 0x1000) {
4110                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4111                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4112                         remaining_size -= 0x1000;
4113                 }
4114                 if (remaining_size)
4115                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4116 #else
4117                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4118 #endif
4119         }
4120
4121         /* Stack alignment check */
4122 #if 0
4123         {
4124                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4125                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4126                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4127                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4128                 amd64_breakpoint (code);
4129         }
4130 #endif
4131
4132         /* Save LMF */
4133         if (method->save_lmf) {
4134                 /* Save ip */
4135                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4136                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4137                 /* Save fp */
4138                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4139                 /* Save sp */
4140                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4141                 /* Skip method (only needed for trampoline LMF frames) */
4142                 /* Save callee saved regs */
4143                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4144                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4145                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4146                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4147                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4148         }
4149
4150         /* Save callee saved registers */
4151         if (cfg->arch.omit_fp && !method->save_lmf) {
4152                 gint32 save_area_offset = 0;
4153
4154                 /* Save caller saved registers after sp is adjusted */
4155                 /* The registers are saved at the bottom of the frame */
4156                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4157                 for (i = 0; i < AMD64_NREG; ++i)
4158                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4159                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4160                                 save_area_offset += 8;
4161                         }
4162         }
4163
4164         /* compute max_offset in order to use short forward jumps */
4165         max_offset = 0;
4166         if (cfg->opt & MONO_OPT_BRANCH) {
4167                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4168                         MonoInst *ins = bb->code;
4169                         bb->max_offset = max_offset;
4170
4171                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4172                                 max_offset += 6;
4173                         /* max alignment for loops */
4174                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4175                                 max_offset += LOOP_ALIGNMENT;
4176
4177                         while (ins) {
4178                                 if (ins->opcode == OP_LABEL)
4179                                         ins->inst_c1 = max_offset;
4180
4181                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4182                                 ins = ins->next;
4183                         }
4184                 }
4185         }
4186
4187         sig = mono_method_signature (method);
4188         pos = 0;
4189
4190         cinfo = get_call_info (sig, FALSE);
4191
4192         if (sig->ret->type != MONO_TYPE_VOID) {
4193                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4194                         /* Save volatile arguments to the stack */
4195                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4196                 }
4197         }
4198
4199         /* Keep this in sync with emit_load_volatile_arguments */
4200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4201                 ArgInfo *ainfo = cinfo->args + i;
4202                 gint32 stack_offset;
4203                 MonoType *arg_type;
4204                 inst = cfg->varinfo [i];
4205
4206                 if (sig->hasthis && (i == 0))
4207                         arg_type = &mono_defaults.object_class->byval_arg;
4208                 else
4209                         arg_type = sig->params [i - sig->hasthis];
4210
4211                 stack_offset = ainfo->offset + ARGS_OFFSET;
4212
4213                 /* Save volatile arguments to the stack */
4214                 if (inst->opcode != OP_REGVAR) {
4215                         switch (ainfo->storage) {
4216                         case ArgInIReg: {
4217                                 guint32 size = 8;
4218
4219                                 /* FIXME: I1 etc */
4220                                 /*
4221                                 if (stack_offset & 0x1)
4222                                         size = 1;
4223                                 else if (stack_offset & 0x2)
4224                                         size = 2;
4225                                 else if (stack_offset & 0x4)
4226                                         size = 4;
4227                                 else
4228                                         size = 8;
4229                                 */
4230                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4231                                 break;
4232                         }
4233                         case ArgInFloatSSEReg:
4234                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4235                                 break;
4236                         case ArgInDoubleSSEReg:
4237                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4238                                 break;
4239                         case ArgValuetypeInReg:
4240                                 for (quad = 0; quad < 2; quad ++) {
4241                                         switch (ainfo->pair_storage [quad]) {
4242                                         case ArgInIReg:
4243                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4244                                                 break;
4245                                         case ArgInFloatSSEReg:
4246                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4247                                                 break;
4248                                         case ArgInDoubleSSEReg:
4249                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4250                                                 break;
4251                                         case ArgNone:
4252                                                 break;
4253                                         default:
4254                                                 g_assert_not_reached ();
4255                                         }
4256                                 }
4257                                 break;
4258                         default:
4259                                 break;
4260                         }
4261                 }
4262
4263                 if (inst->opcode == OP_REGVAR) {
4264                         /* Argument allocated to (non-volatile) register */
4265                         switch (ainfo->storage) {
4266                         case ArgInIReg:
4267                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4268                                 break;
4269                         case ArgOnStack:
4270                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4271                                 break;
4272                         default:
4273                                 g_assert_not_reached ();
4274                         }
4275                 }
4276         }
4277
4278         /* Might need to attach the thread to the JIT */
4279         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4280                 guint64 domain = (guint64)cfg->domain;
4281
4282                 /*
4283                  * The call might clobber argument registers, but they are already
4284                  * saved to the stack/global regs.
4285                  */
4286                 if (lmf_addr_tls_offset != -1) {
4287                         guint8 *buf;
4288
4289                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4290                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4291                         buf = code;
4292                         x86_branch8 (code, X86_CC_NE, 0, 0);
4293                         if ((domain >> 32) == 0)
4294                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4295                         else
4296                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4297                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4298                         amd64_patch (buf, code);
4299                 } else {
4300                         g_assert (!cfg->compile_aot);
4301                         if ((domain >> 32) == 0)
4302                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4303                         else
4304                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4305                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4306                 }
4307         }
4308
4309         if (method->save_lmf) {
4310                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4311                         /*
4312                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4313                          * through the mono_lmf_addr TLS variable.
4314                          */
4315                         /* %rax = previous_lmf */
4316                         x86_prefix (code, X86_FS_PREFIX);
4317                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4318
4319                         /* Save previous_lmf */
4320                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4321                         /* Set new lmf */
4322                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4323                         x86_prefix (code, X86_FS_PREFIX);
4324                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4325                 } else {
4326                         if (lmf_addr_tls_offset != -1) {
4327                                 /* Load lmf quicky using the FS register */
4328                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4329                         }
4330                         else {
4331                                 /*
4332                                  * The call might clobber argument registers, but they are already
4333                                  * saved to the stack/global regs.
4334                                  */
4335                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4336                                                                   (gpointer)"mono_get_lmf_addr");
4337                         }
4338
4339                         /* Save lmf_addr */
4340                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4341                         /* Save previous_lmf */
4342                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4343                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4344                         /* Set new lmf */
4345                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4346                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4347                 }
4348         }
4349
4350
4351         g_free (cinfo);
4352
4353         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4354                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4355
4356         cfg->code_len = code - cfg->native_code;
4357
4358         g_assert (cfg->code_len < cfg->code_size);
4359
4360         return code;
4361 }
4362
4363 void
4364 mono_arch_emit_epilog (MonoCompile *cfg)
4365 {
4366         MonoMethod *method = cfg->method;
4367         int quad, pos, i;
4368         guint8 *code;
4369         int max_epilog_size = 16;
4370         CallInfo *cinfo;
4371         gint32 lmf_offset = cfg->arch.lmf_offset;
4372
4373         if (cfg->method->save_lmf)
4374                 max_epilog_size += 256;
4375
4376         if (mono_jit_trace_calls != NULL)
4377                 max_epilog_size += 50;
4378
4379         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4380                 max_epilog_size += 50;
4381
4382         max_epilog_size += (AMD64_NREG * 2);
4383
4384         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4385                 cfg->code_size *= 2;
4386                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4387                 mono_jit_stats.code_reallocs++;
4388         }
4389
4390         code = cfg->native_code + cfg->code_len;
4391
4392         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4393                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4394
4395         /* the code restoring the registers must be kept in sync with CEE_JMP */
4396         pos = 0;
4397
4398         if (method->save_lmf) {
4399                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4400                         /*
4401                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4402                          * through the mono_lmf_addr TLS variable.
4403                          */
4404                         /* reg = previous_lmf */
4405                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4406                         x86_prefix (code, X86_FS_PREFIX);
4407                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4408                 } else {
4409                         /* Restore previous lmf */
4410                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4411                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4412                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4413                 }
4414
4415                 /* Restore caller saved regs */
4416                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4417                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4418                 }
4419                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4420                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4421                 }
4422                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4423                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4424                 }
4425                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4426                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4427                 }
4428                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4429                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4430                 }
4431                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4432                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4433                 }
4434         } else {
4435
4436                 if (cfg->arch.omit_fp) {
4437                         gint32 save_area_offset = 0;
4438
4439                         for (i = 0; i < AMD64_NREG; ++i)
4440                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4441                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4442                                         save_area_offset += 8;
4443                                 }
4444                 }
4445                 else {
4446                         for (i = 0; i < AMD64_NREG; ++i)
4447                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4448                                         pos -= sizeof (gpointer);
4449
4450                         if (pos) {
4451                                 if (pos == - sizeof (gpointer)) {
4452                                         /* Only one register, so avoid lea */
4453                                         for (i = AMD64_NREG - 1; i > 0; --i)
4454                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4455                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4456                                                 }
4457                                 }
4458                                 else {
4459                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4460
4461                                         /* Pop registers in reverse order */
4462                                         for (i = AMD64_NREG - 1; i > 0; --i)
4463                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4464                                                         amd64_pop_reg (code, i);
4465                                                 }
4466                                 }
4467                         }
4468                 }
4469         }
4470
4471         /* Load returned vtypes into registers if needed */
4472         cinfo = get_call_info (mono_method_signature (method), FALSE);
4473         if (cinfo->ret.storage == ArgValuetypeInReg) {
4474                 ArgInfo *ainfo = &cinfo->ret;
4475                 MonoInst *inst = cfg->ret;
4476
4477                 for (quad = 0; quad < 2; quad ++) {
4478                         switch (ainfo->pair_storage [quad]) {
4479                         case ArgInIReg:
4480                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4481                                 break;
4482                         case ArgInFloatSSEReg:
4483                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4484                                 break;
4485                         case ArgInDoubleSSEReg:
4486                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4487                                 break;
4488                         case ArgNone:
4489                                 break;
4490                         default:
4491                                 g_assert_not_reached ();
4492                         }
4493                 }
4494         }
4495         g_free (cinfo);
4496
4497         if (cfg->arch.omit_fp) {
4498                 if (cfg->arch.stack_alloc_size)
4499                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4500         } else {
4501                 amd64_leave (code);
4502         }
4503         amd64_ret (code);
4504
4505         cfg->code_len = code - cfg->native_code;
4506
4507         g_assert (cfg->code_len < cfg->code_size);
4508
4509         if (cfg->arch.omit_fp) {
4510                 /*
4511                  * Encode the stack size into used_int_regs so the exception handler
4512                  * can access it.
4513                  */
4514                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4515                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4516         }
4517 }
4518
4519 void
4520 mono_arch_emit_exceptions (MonoCompile *cfg)
4521 {
4522         MonoJumpInfo *patch_info;
4523         int nthrows, i;
4524         guint8 *code;
4525         MonoClass *exc_classes [16];
4526         guint8 *exc_throw_start [16], *exc_throw_end [16];
4527         guint32 code_size = 0;
4528
4529         /* Compute needed space */
4530         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4531                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4532                         code_size += 40;
4533                 if (patch_info->type == MONO_PATCH_INFO_R8)
4534                         code_size += 8 + 15; /* sizeof (double) + alignment */
4535                 if (patch_info->type == MONO_PATCH_INFO_R4)
4536                         code_size += 4 + 15; /* sizeof (float) + alignment */
4537         }
4538
4539         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4540                 cfg->code_size *= 2;
4541                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4542                 mono_jit_stats.code_reallocs++;
4543         }
4544
4545         code = cfg->native_code + cfg->code_len;
4546
4547         /* add code to raise exceptions */
4548         nthrows = 0;
4549         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4550                 switch (patch_info->type) {
4551                 case MONO_PATCH_INFO_EXC: {
4552                         MonoClass *exc_class;
4553                         guint8 *buf, *buf2;
4554                         guint32 throw_ip;
4555
4556                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4557
4558                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4559                         g_assert (exc_class);
4560                         throw_ip = patch_info->ip.i;
4561
4562                         //x86_breakpoint (code);
4563                         /* Find a throw sequence for the same exception class */
4564                         for (i = 0; i < nthrows; ++i)
4565                                 if (exc_classes [i] == exc_class)
4566                                         break;
4567                         if (i < nthrows) {
4568                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4569                                 x86_jump_code (code, exc_throw_start [i]);
4570                                 patch_info->type = MONO_PATCH_INFO_NONE;
4571                         }
4572                         else {
4573                                 buf = code;
4574                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4575                                 buf2 = code;
4576
4577                                 if (nthrows < 16) {
4578                                         exc_classes [nthrows] = exc_class;
4579                                         exc_throw_start [nthrows] = code;
4580                                 }
4581
4582                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4583                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4584                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4585                                 patch_info->ip.i = code - cfg->native_code;
4586
4587                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4588
4589                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4590                                 while (buf < buf2)
4591                                         x86_nop (buf);
4592
4593                                 if (nthrows < 16) {
4594                                         exc_throw_end [nthrows] = code;
4595                                         nthrows ++;
4596                                 }
4597                         }
4598                         break;
4599                 }
4600                 default:
4601                         /* do nothing */
4602                         break;
4603                 }
4604         }
4605
4606         /* Handle relocations with RIP relative addressing */
4607         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4608                 gboolean remove = FALSE;
4609
4610                 switch (patch_info->type) {
4611                 case MONO_PATCH_INFO_R8:
4612                 case MONO_PATCH_INFO_R4: {
4613                         guint8 *pos;
4614
4615                         if (use_sse2) {
4616                                 /* The SSE opcodes require a 16 byte alignment */
4617                                 code = (guint8*)ALIGN_TO (code, 16);
4618                         } else {
4619                                 code = (guint8*)ALIGN_TO (code, 8);
4620                         }
4621
4622                         pos = cfg->native_code + patch_info->ip.i;
4623
4624                         if (use_sse2)
4625                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4626                         else
4627                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4628
4629                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4630                                 *(double*)code = *(double*)patch_info->data.target;
4631                                 code += sizeof (double);
4632                         } else {
4633                                 *(float*)code = *(float*)patch_info->data.target;
4634                                 code += sizeof (float);
4635                         }
4636
4637                         remove = TRUE;
4638                         break;
4639                 }
4640                 default:
4641                         break;
4642                 }
4643
4644                 if (remove) {
4645                         if (patch_info == cfg->patch_info)
4646                                 cfg->patch_info = patch_info->next;
4647                         else {
4648                                 MonoJumpInfo *tmp;
4649
4650                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4651                                         ;
4652                                 tmp->next = patch_info->next;
4653                         }
4654                 }
4655         }
4656
4657         cfg->code_len = code - cfg->native_code;
4658
4659         g_assert (cfg->code_len < cfg->code_size);
4660
4661 }
4662
4663 void*
4664 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4665 {
4666         guchar *code = p;
4667         CallInfo *cinfo = NULL;
4668         MonoMethodSignature *sig;
4669         MonoInst *inst;
4670         int i, n, stack_area = 0;
4671
4672         /* Keep this in sync with mono_arch_get_argument_info */
4673
4674         if (enable_arguments) {
4675                 /* Allocate a new area on the stack and save arguments there */
4676                 sig = mono_method_signature (cfg->method);
4677
4678                 cinfo = get_call_info (sig, FALSE);
4679
4680                 n = sig->param_count + sig->hasthis;
4681
4682                 stack_area = ALIGN_TO (n * 8, 16);
4683
4684                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4685
4686                 for (i = 0; i < n; ++i) {
4687                         inst = cfg->varinfo [i];
4688
4689                         if (inst->opcode == OP_REGVAR)
4690                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4691                         else {
4692                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4693                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4694                         }
4695                 }
4696         }
4697
4698         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4699         amd64_set_reg_template (code, AMD64_RDI);
4700         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4701         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4702
4703         if (enable_arguments) {
4704                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4705
4706                 g_free (cinfo);
4707         }
4708
4709         return code;
4710 }
4711
4712 enum {
4713         SAVE_NONE,
4714         SAVE_STRUCT,
4715         SAVE_EAX,
4716         SAVE_EAX_EDX,
4717         SAVE_XMM
4718 };
4719
4720 void*
4721 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4722 {
4723         guchar *code = p;
4724         int save_mode = SAVE_NONE;
4725         MonoMethod *method = cfg->method;
4726         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4727
4728         switch (rtype) {
4729         case MONO_TYPE_VOID:
4730                 /* special case string .ctor icall */
4731                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4732                         save_mode = SAVE_EAX;
4733                 else
4734                         save_mode = SAVE_NONE;
4735                 break;
4736         case MONO_TYPE_I8:
4737         case MONO_TYPE_U8:
4738                 save_mode = SAVE_EAX;
4739                 break;
4740         case MONO_TYPE_R4:
4741         case MONO_TYPE_R8:
4742                 save_mode = SAVE_XMM;
4743                 break;
4744         case MONO_TYPE_GENERICINST:
4745                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4746                         save_mode = SAVE_EAX;
4747                         break;
4748                 }
4749                 /* Fall through */
4750         case MONO_TYPE_VALUETYPE:
4751                 save_mode = SAVE_STRUCT;
4752                 break;
4753         default:
4754                 save_mode = SAVE_EAX;
4755                 break;
4756         }
4757
4758         /* Save the result and copy it into the proper argument register */
4759         switch (save_mode) {
4760         case SAVE_EAX:
4761                 amd64_push_reg (code, AMD64_RAX);
4762                 /* Align stack */
4763                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4764                 if (enable_arguments)
4765                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4766                 break;
4767         case SAVE_STRUCT:
4768                 /* FIXME: */
4769                 if (enable_arguments)
4770                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4771                 break;
4772         case SAVE_XMM:
4773                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4774                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4775                 /* Align stack */
4776                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4777                 /*
4778                  * The result is already in the proper argument register so no copying
4779                  * needed.
4780                  */
4781                 break;
4782         case SAVE_NONE:
4783                 break;
4784         default:
4785                 g_assert_not_reached ();
4786         }
4787
4788         /* Set %al since this is a varargs call */
4789         if (save_mode == SAVE_XMM)
4790                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4791         else
4792                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4793
4794         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4795         amd64_set_reg_template (code, AMD64_RDI);
4796         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4797
4798         /* Restore result */
4799         switch (save_mode) {
4800         case SAVE_EAX:
4801                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4802                 amd64_pop_reg (code, AMD64_RAX);
4803                 break;
4804         case SAVE_STRUCT:
4805                 /* FIXME: */
4806                 break;
4807         case SAVE_XMM:
4808                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4809                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4810                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4811                 break;
4812         case SAVE_NONE:
4813                 break;
4814         default:
4815                 g_assert_not_reached ();
4816         }
4817
4818         return code;
4819 }
4820
4821 void
4822 mono_arch_flush_icache (guint8 *code, gint size)
4823 {
4824         /* Not needed */
4825 }
4826
4827 void
4828 mono_arch_flush_register_windows (void)
4829 {
4830 }
4831
4832 gboolean
4833 mono_arch_is_inst_imm (gint64 imm)
4834 {
4835         return amd64_is_imm32 (imm);
4836 }
4837
4838 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4839
4840 /*
4841  * Determine whenever the trap whose info is in SIGINFO is caused by
4842  * integer overflow.
4843  */
4844 gboolean
4845 mono_arch_is_int_overflow (void *sigctx, void *info)
4846 {
4847         MonoContext ctx;
4848         guint8* rip;
4849         int reg;
4850         gint64 value;
4851
4852         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4853
4854         rip = (guint8*)ctx.rip;
4855
4856         if (IS_REX (rip [0])) {
4857                 reg = amd64_rex_b (rip [0]);
4858                 rip ++;
4859         }
4860         else
4861                 reg = 0;
4862
4863         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4864                 /* idiv REG */
4865                 reg += x86_modrm_rm (rip [1]);
4866
4867                 switch (reg) {
4868                 case AMD64_RAX:
4869                         value = ctx.rax;
4870                         break;
4871                 case AMD64_RBX:
4872                         value = ctx.rbx;
4873                         break;
4874                 case AMD64_RCX:
4875                         value = ctx.rcx;
4876                         break;
4877                 case AMD64_RDX:
4878                         value = ctx.rdx;
4879                         break;
4880                 case AMD64_RBP:
4881                         value = ctx.rbp;
4882                         break;
4883                 case AMD64_RSP:
4884                         value = ctx.rsp;
4885                         break;
4886                 case AMD64_RSI:
4887                         value = ctx.rsi;
4888                         break;
4889                 case AMD64_RDI:
4890                         value = ctx.rdi;
4891                         break;
4892                 case AMD64_R12:
4893                         value = ctx.r12;
4894                         break;
4895                 case AMD64_R13:
4896                         value = ctx.r13;
4897                         break;
4898                 case AMD64_R14:
4899                         value = ctx.r14;
4900                         break;
4901                 case AMD64_R15:
4902                         value = ctx.r15;
4903                         break;
4904                 default:
4905                         g_assert_not_reached ();
4906                         reg = -1;
4907                 }
4908
4909                 if (value == -1)
4910                         return TRUE;
4911         }
4912
4913         return FALSE;
4914 }
4915
4916 guint32
4917 mono_arch_get_patch_offset (guint8 *code)
4918 {
4919         return 3;
4920 }
4921
4922 gpointer*
4923 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4924 {
4925         guint32 reg;
4926         guint32 disp;
4927         guint8 rex = 0;
4928
4929         /* go to the start of the call instruction
4930          *
4931          * address_byte = (m << 6) | (o << 3) | reg
4932          * call opcode: 0xff address_byte displacement
4933          * 0xff m=1,o=2 imm8
4934          * 0xff m=2,o=2 imm32
4935          */
4936         code -= 7;
4937
4938         /*
4939          * A given byte sequence can match more than case here, so we have to be
4940          * really careful about the ordering of the cases. Longer sequences
4941          * come first.
4942          */
4943         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4944                         /*
4945                          * This is a interface call
4946                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4947                          * ff 10                  callq  *(%rax)
4948                          */
4949                 if (IS_REX (code [4]))
4950                         rex = code [4];
4951                 reg = amd64_modrm_rm (code [6]);
4952                 disp = 0;
4953         }
4954         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4955                 /* call OFFSET(%rip) */
4956                 disp = *(guint32*)(code + 3);
4957                 return (gpointer*)(code + disp + 7);
4958         }
4959         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4960                 /* call *[reg+disp32] */
4961                 if (IS_REX (code [0]))
4962                         rex = code [0];
4963                 reg = amd64_modrm_rm (code [2]);
4964                 disp = *(guint32*)(code + 3);
4965                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4966         }
4967         else if (code [2] == 0xe8) {
4968                 /* call <ADDR> */
4969                 return NULL;
4970         }
4971         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4972                 /* call *%reg */
4973                 return NULL;
4974         }
4975         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4976                 /* call *[reg+disp8] */
4977                 if (IS_REX (code [3]))
4978                         rex = code [3];
4979                 reg = amd64_modrm_rm (code [5]);
4980                 disp = *(guint8*)(code + 6);
4981                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4982         }
4983         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4984                         /*
4985                          * This is a interface call: should check the above code can't catch it earlier
4986                          * 8b 40 30   mov    0x30(%eax),%eax
4987                          * ff 10      call   *(%eax)
4988                          */
4989                 if (IS_REX (code [4]))
4990                         rex = code [4];
4991                 reg = amd64_modrm_rm (code [6]);
4992                 disp = 0;
4993         }
4994         else
4995                 g_assert_not_reached ();
4996
4997         reg += amd64_rex_b (rex);
4998
4999         /* R11 is clobbered by the trampoline code */
5000         g_assert (reg != AMD64_R11);
5001
5002         return (gpointer)(((guint64)(regs [reg])) + disp);
5003 }
5004
5005 gpointer*
5006 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
5007 {
5008         guint32 reg;
5009         guint32 disp;
5010
5011         code -= 10;
5012
5013         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
5014                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
5015                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
5016                 disp = code [6];
5017
5018                 if (reg == AMD64_RAX)
5019                         return NULL;
5020                 else
5021                         return (gpointer*)(((guint64)(regs [reg])) + disp);
5022         }
5023
5024         return NULL;
5025 }
5026
5027 /*
5028  * Support for fast access to the thread-local lmf structure using the GS
5029  * segment register on NPTL + kernel 2.6.x.
5030  */
5031
5032 static gboolean tls_offset_inited = FALSE;
5033
5034 void
5035 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5036 {
5037         if (!tls_offset_inited) {
5038                 tls_offset_inited = TRUE;
5039 #ifdef MONO_XEN_OPT
5040                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5041 #endif
5042                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5043                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5044                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5045                 thread_tls_offset = mono_thread_get_tls_offset ();
5046         }
5047 }
5048
5049 void
5050 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5051 {
5052 }
5053
5054 void
5055 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5056 {
5057         MonoCallInst *call = (MonoCallInst*)inst;
5058         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
5059
5060         if (vt_reg != -1) {
5061                 MonoInst *vtarg;
5062
5063                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5064                         /*
5065                          * The valuetype is in RAX:RDX after the call, need to be copied to
5066                          * the stack. Push the address here, so the call instruction can
5067                          * access it.
5068                          */
5069                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5070                         vtarg->sreg1 = vt_reg;
5071                         mono_bblock_add_inst (cfg->cbb, vtarg);
5072
5073                         /* Align stack */
5074                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5075                 }
5076                 else {
5077                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5078                         vtarg->sreg1 = vt_reg;
5079                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5080                         mono_bblock_add_inst (cfg->cbb, vtarg);
5081
5082                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5083                 }
5084         }
5085
5086         /* add the this argument */
5087         if (this_reg != -1) {
5088                 MonoInst *this;
5089                 MONO_INST_NEW (cfg, this, OP_MOVE);
5090                 this->type = this_type;
5091                 this->sreg1 = this_reg;
5092                 this->dreg = mono_regstate_next_int (cfg->rs);
5093                 mono_bblock_add_inst (cfg->cbb, this);
5094
5095                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5096         }
5097
5098         g_free (cinfo);
5099 }
5100
5101 MonoInst*
5102 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5103 {
5104         MonoInst *ins = NULL;
5105
5106         if (cmethod->klass == mono_defaults.math_class) {
5107                 if (strcmp (cmethod->name, "Sin") == 0) {
5108                         MONO_INST_NEW (cfg, ins, OP_SIN);
5109                         ins->inst_i0 = args [0];
5110                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5111                         MONO_INST_NEW (cfg, ins, OP_COS);
5112                         ins->inst_i0 = args [0];
5113                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5114                         if (use_sse2)
5115                                 return ins;
5116                         MONO_INST_NEW (cfg, ins, OP_TAN);
5117                         ins->inst_i0 = args [0];
5118                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5119                         if (use_sse2)
5120                                 return ins;
5121                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5122                         ins->inst_i0 = args [0];
5123                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5124                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5125                         ins->inst_i0 = args [0];
5126                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5127                         MONO_INST_NEW (cfg, ins, OP_ABS);
5128                         ins->inst_i0 = args [0];
5129                 }
5130 #if 0
5131                 /* OP_FREM is not IEEE compatible */
5132                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5133                         MONO_INST_NEW (cfg, ins, OP_FREM);
5134                         ins->inst_i0 = args [0];
5135                         ins->inst_i1 = args [1];
5136                 }
5137 #endif
5138         } else if (cmethod->klass == mono_defaults.thread_class &&
5139                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
5140                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
5141         } else if(cmethod->klass->image == mono_defaults.corlib &&
5142                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5143                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5144
5145                 if (strcmp (cmethod->name, "Increment") == 0) {
5146                         MonoInst *ins_iconst;
5147                         guint32 opcode;
5148
5149                         if (fsig->params [0]->type == MONO_TYPE_I4)
5150                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5151                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5152                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5153                         else
5154                                 g_assert_not_reached ();
5155                         MONO_INST_NEW (cfg, ins, opcode);
5156                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5157                         ins_iconst->inst_c0 = 1;
5158
5159                         ins->inst_i0 = args [0];
5160                         ins->inst_i1 = ins_iconst;
5161                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5162                         MonoInst *ins_iconst;
5163                         guint32 opcode;
5164
5165                         if (fsig->params [0]->type == MONO_TYPE_I4)
5166                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5167                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5168                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5169                         else
5170                                 g_assert_not_reached ();
5171                         MONO_INST_NEW (cfg, ins, opcode);
5172                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5173                         ins_iconst->inst_c0 = -1;
5174
5175                         ins->inst_i0 = args [0];
5176                         ins->inst_i1 = ins_iconst;
5177                 } else if (strcmp (cmethod->name, "Add") == 0) {
5178                         guint32 opcode;
5179
5180                         if (fsig->params [0]->type == MONO_TYPE_I4)
5181                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5182                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5183                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5184                         else
5185                                 g_assert_not_reached ();
5186
5187                         MONO_INST_NEW (cfg, ins, opcode);
5188
5189                         ins->inst_i0 = args [0];
5190                         ins->inst_i1 = args [1];
5191                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5192                         guint32 opcode;
5193
5194                         if (fsig->params [0]->type == MONO_TYPE_I4)
5195                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5196                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5197                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5198                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5199                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5200                         else
5201                                 return NULL;
5202
5203                         MONO_INST_NEW (cfg, ins, opcode);
5204
5205                         ins->inst_i0 = args [0];
5206                         ins->inst_i1 = args [1];
5207                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5208                         /* 64 bit reads are already atomic */
5209                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5210                         ins->inst_i0 = args [0];
5211                 }
5212
5213                 /*
5214                  * Can't implement CompareExchange methods this way since they have
5215                  * three arguments.
5216                  */
5217         }
5218
5219         return ins;
5220 }
5221
5222 gboolean
5223 mono_arch_print_tree (MonoInst *tree, int arity)
5224 {
5225         return 0;
5226 }
5227
5228 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5229 {
5230         MonoInst* ins;
5231
5232         if (appdomain_tls_offset == -1)
5233                 return NULL;
5234
5235         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5236         ins->inst_offset = appdomain_tls_offset;
5237         return ins;
5238 }
5239
5240 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5241 {
5242         MonoInst* ins;
5243
5244         if (thread_tls_offset == -1)
5245                 return NULL;
5246
5247         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5248         ins->inst_offset = thread_tls_offset;
5249         return ins;
5250 }