mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mini_type_get_underlying_type (NULL, type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info;
 407         MonoClass *klass;
 408         MonoGenericSharingContext tmp_gsctx;
 409
 410         /*
 411          * The gsctx currently contains no data, it is only used for checking whenever
 412          * open types are allowed, some callers like mono_arch_get_argument_info ()
 413          * don't pass it to us, so work around that.
 414          */
 415         if (!gsctx)
 416                 gsctx = &tmp_gsctx;
 417
 418         klass = mono_class_from_mono_type (type);
 419         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 420 #ifndef PLATFORM_WIN32
 421         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 422                 /* We pass and return vtypes of size 8 in a register */
 423         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 424 #else
 425         if (!sig->pinvoke) {
 426 #endif
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = ArgOnStack;
 431
 432                 return;
 433         }
 434
 435         /* FIXME: Handle structs smaller than 8 bytes */
 436         //if ((size % 8) != 0)
 437         //      NOT_IMPLEMENTED;
 438
 439         if (size > 8)
 440                 nquads = 2;
 441         else
 442                 nquads = 1;
 443
 444         if (!sig->pinvoke) {
 445                 /* Always pass in 1 or 2 integer registers */
 446                 args [0] = ARG_CLASS_INTEGER;
 447                 args [1] = ARG_CLASS_INTEGER;
 448                 /* Only the simplest cases are supported */
 449                 if (is_return && nquads != 1) {
 450                         args [0] = ARG_CLASS_MEMORY;
 451                         args [1] = ARG_CLASS_MEMORY;
 452                 }
 453         } else {
 454                 /*
 455                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 456                  * The X87 and SSEUP stuff is left out since there are no such types in
 457                  * the CLR.
 458                  */
 459                 info = mono_marshal_load_type_info (klass);
 460                 g_assert (info);
 461
 462 #ifndef PLATFORM_WIN32
 463                 if (info->native_size > 16) {
 464                         ainfo->offset = *stack_size;
 465                         *stack_size += ALIGN_TO (info->native_size, 8);
 466                         ainfo->storage = ArgOnStack;
 467
 468                         return;
 469                 }
 470 #else
 471                 switch (info->native_size) {
 472                 case 1: case 2: case 4: case 8:
 473                         break;
 474                 default:
 475                         if (is_return) {
 476                                 ainfo->storage = ArgOnStack;
 477                                 ainfo->offset = *stack_size;
 478                                 *stack_size += ALIGN_TO (info->native_size, 8);
 479                         }
 480                         else {
 481                                 ainfo->storage = ArgValuetypeAddrInIReg;
 482
 483                                 if (*gr < PARAM_REGS) {
 484                                         ainfo->pair_storage [0] = ArgInIReg;
 485                                         ainfo->pair_regs [0] = param_regs [*gr];
 486                                         (*gr) ++;
 487                                 }
 488                                 else {
 489                                         ainfo->pair_storage [0] = ArgOnStack;
 490                                         ainfo->offset = *stack_size;
 491                                         *stack_size += 8;
 492                                 }
 493                         }
 494
 495                         return;
 496                 }
 497 #endif
 498
 499                 args [0] = ARG_CLASS_NO_CLASS;
 500                 args [1] = ARG_CLASS_NO_CLASS;
 501                 for (quad = 0; quad < nquads; ++quad) {
 502                         int size;
 503                         guint32 align;
 504                         ArgumentClass class1;
 505
 506                         if (info->num_fields == 0)
 507                                 class1 = ARG_CLASS_MEMORY;
 508                         else
 509                                 class1 = ARG_CLASS_NO_CLASS;
 510                         for (i = 0; i < info->num_fields; ++i) {
 511                                 size = mono_marshal_type_size (info->fields [i].field->type,
 512                                                                                            info->fields [i].mspec,
 513                                                                                            &align, TRUE, klass->unicode);
 514                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 515                                         /* Unaligned field */
 516                                         NOT_IMPLEMENTED;
 517                                 }
 518
 519                                 /* Skip fields in other quad */
 520                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 521                                         continue;
 522                                 if ((quad == 1) && (info->fields [i].offset < 8))
 523                                         continue;
 524
 525                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 526                         }
 527                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 528                         args [quad] = class1;
 529                 }
 530         }
 531
 532         /* Post merger cleanup */
 533         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 534                 args [0] = args [1] = ARG_CLASS_MEMORY;
 535
 536         /* Allocate registers */
 537         {
 538                 int orig_gr = *gr;
 539                 int orig_fr = *fr;
 540
 541                 ainfo->storage = ArgValuetypeInReg;
 542                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 543                 for (quad = 0; quad < nquads; ++quad) {
 544                         switch (args [quad]) {
 545                         case ARG_CLASS_INTEGER:
 546                                 if (*gr >= PARAM_REGS)
 547                                         args [quad] = ARG_CLASS_MEMORY;
 548                                 else {
 549                                         ainfo->pair_storage [quad] = ArgInIReg;
 550                                         if (is_return)
 551                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 552                                         else
 553                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 554                                         (*gr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_SSE:
 558                                 if (*fr >= FLOAT_PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 562                                         ainfo->pair_regs [quad] = *fr;
 563                                         (*fr) ++;
 564                                 }
 565                                 break;
 566                         case ARG_CLASS_MEMORY:
 567                                 break;
 568                         default:
 569                                 g_assert_not_reached ();
 570                         }
 571                 }
 572
 573                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         if (sig->pinvoke)
 580                                 *stack_size += ALIGN_TO (info->native_size, 8);
 581                         else
 582                                 *stack_size += nquads * sizeof (gpointer);
 583                         ainfo->storage = ArgOnStack;
 584                 }
 585         }
 586 }
 587
 588 /*
 589  * get_call_info:
 590  *
 591  *  Obtain information about a call according to the calling convention.
 592  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 593  * Draft Version 0.23" document for more information.
 594  */
 595 static CallInfo*
 596 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 597 {
 598         guint32 i, gr, fr;
 599         MonoType *ret_type;
 600         int n = sig->hasthis + sig->param_count;
 601         guint32 stack_size = 0;
 602         CallInfo *cinfo;
 603
 604         if (mp)
 605                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606         else
 607                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 608
 609         gr = 0;
 610         fr = 0;
 611
 612         /* return value */
 613         {
 614                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 615                 switch (ret_type->type) {
 616                 case MONO_TYPE_BOOLEAN:
 617                 case MONO_TYPE_I1:
 618                 case MONO_TYPE_U1:
 619                 case MONO_TYPE_I2:
 620                 case MONO_TYPE_U2:
 621                 case MONO_TYPE_CHAR:
 622                 case MONO_TYPE_I4:
 623                 case MONO_TYPE_U4:
 624                 case MONO_TYPE_I:
 625                 case MONO_TYPE_U:
 626                 case MONO_TYPE_PTR:
 627                 case MONO_TYPE_FNPTR:
 628                 case MONO_TYPE_CLASS:
 629                 case MONO_TYPE_OBJECT:
 630                 case MONO_TYPE_SZARRAY:
 631                 case MONO_TYPE_ARRAY:
 632                 case MONO_TYPE_STRING:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_U8:
 637                 case MONO_TYPE_I8:
 638                         cinfo->ret.storage = ArgInIReg;
 639                         cinfo->ret.reg = AMD64_RAX;
 640                         break;
 641                 case MONO_TYPE_R4:
 642                         cinfo->ret.storage = ArgInFloatSSEReg;
 643                         cinfo->ret.reg = AMD64_XMM0;
 644                         break;
 645                 case MONO_TYPE_R8:
 646                         cinfo->ret.storage = ArgInDoubleSSEReg;
 647                         cinfo->ret.reg = AMD64_XMM0;
 648                         break;
 649                 case MONO_TYPE_GENERICINST:
 650                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 651                                 cinfo->ret.storage = ArgInIReg;
 652                                 cinfo->ret.reg = AMD64_RAX;
 653                                 break;
 654                         }
 655                         /* fall through */
 656                 case MONO_TYPE_VALUETYPE: {
 657                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 658
 659                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 660                         if (cinfo->ret.storage == ArgOnStack)
 661                                 /* The caller passes the address where the value is stored */
 662                                 add_general (&gr, &stack_size, &cinfo->ret);
 663                         break;
 664                 }
 665                 case MONO_TYPE_TYPEDBYREF:
 666                         /* Same as a valuetype with size 24 */
 667                         add_general (&gr, &stack_size, &cinfo->ret);
 668                         ;
 669                         break;
 670                 case MONO_TYPE_VOID:
 671                         break;
 672                 default:
 673                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 674                 }
 675         }
 676
 677         /* this */
 678         if (sig->hasthis)
 679                 add_general (&gr, &stack_size, cinfo->args + 0);
 680
 681         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 682                 gr = PARAM_REGS;
 683                 fr = FLOAT_PARAM_REGS;
 684
 685                 /* Emit the signature cookie just before the implicit arguments */
 686                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 687         }
 688
 689         for (i = 0; i < sig->param_count; ++i) {
 690                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 691                 MonoType *ptype;
 692
 693 #ifdef PLATFORM_WIN32
 694                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 695                 if (gr > fr)
 696                         fr = gr;
 697                 else if (fr > gr)
 698                         gr = fr;
 699 #endif
 700
 701                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 702                         /* We allways pass the sig cookie on the stack for simplicity */
 703                         /*
 704                          * Prevent implicit arguments + the sig cookie from being passed
 705                          * in registers.
 706                          */
 707                         gr = PARAM_REGS;
 708                         fr = FLOAT_PARAM_REGS;
 709
 710                         /* Emit the signature cookie just before the implicit arguments */
 711                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 712                 }
 713
 714                 if (sig->params [i]->byref) {
 715                         add_general (&gr, &stack_size, ainfo);
 716                         continue;
 717                 }
 718                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 719                 switch (ptype->type) {
 720                 case MONO_TYPE_BOOLEAN:
 721                 case MONO_TYPE_I1:
 722                 case MONO_TYPE_U1:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I2:
 726                 case MONO_TYPE_U2:
 727                 case MONO_TYPE_CHAR:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I4:
 731                 case MONO_TYPE_U4:
 732                         add_general (&gr, &stack_size, ainfo);
 733                         break;
 734                 case MONO_TYPE_I:
 735                 case MONO_TYPE_U:
 736                 case MONO_TYPE_PTR:
 737                 case MONO_TYPE_FNPTR:
 738                 case MONO_TYPE_CLASS:
 739                 case MONO_TYPE_OBJECT:
 740                 case MONO_TYPE_STRING:
 741                 case MONO_TYPE_SZARRAY:
 742                 case MONO_TYPE_ARRAY:
 743                         add_general (&gr, &stack_size, ainfo);
 744                         break;
 745                 case MONO_TYPE_GENERICINST:
 746                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 747                                 add_general (&gr, &stack_size, ainfo);
 748                                 break;
 749                         }
 750                         /* fall through */
 751                 case MONO_TYPE_VALUETYPE:
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753                         break;
 754                 case MONO_TYPE_TYPEDBYREF:
 755 #ifdef PLATFORM_WIN32
 756                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 757 #else
 758                         stack_size += sizeof (MonoTypedRef);
 759                         ainfo->storage = ArgOnStack;
 760 #endif
 761                         break;
 762                 case MONO_TYPE_U8:
 763                 case MONO_TYPE_I8:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_R4:
 767                         add_float (&fr, &stack_size, ainfo, FALSE);
 768                         break;
 769                 case MONO_TYPE_R8:
 770                         add_float (&fr, &stack_size, ainfo, TRUE);
 771                         break;
 772                 default:
 773                         g_assert_not_reached ();
 774                 }
 775         }
 776
 777         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 778                 gr = PARAM_REGS;
 779                 fr = FLOAT_PARAM_REGS;
 780
 781                 /* Emit the signature cookie just before the implicit arguments */
 782                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 783         }
 784
 785 #ifdef PLATFORM_WIN32
 786         // There always is 32 bytes reserved on the stack when calling on Winx64
 787         stack_size += 0x20;
 788 #endif
 789
 790         if (stack_size & 0x8) {
 791                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 792                 cinfo->need_stack_align = TRUE;
 793                 stack_size += 8;
 794         }
 795
 796         cinfo->stack_usage = stack_size;
 797         cinfo->reg_usage = gr;
 798         cinfo->freg_usage = fr;
 799         return cinfo;
 800 }
 801
 802 /*
 803  * mono_arch_get_argument_info:
 804  * @csig:  a method signature
 805  * @param_count: the number of parameters to consider
 806  * @arg_info: an array to store the result infos
 807  *
 808  * Gathers information on parameters such as size, alignment and
 809  * padding. arg_info should be large enought to hold param_count + 1 entries.
 810  *
 811  * Returns the size of the argument area on the stack.
 812  */
 813 int
 814 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 815 {
 816         int k;
 817         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 818         guint32 args_size = cinfo->stack_usage;
 819
 820         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 821         if (csig->hasthis) {
 822                 arg_info [0].offset = 0;
 823         }
 824
 825         for (k = 0; k < param_count; k++) {
 826                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 827                 /* FIXME: */
 828                 arg_info [k + 1].size = 0;
 829         }
 830
 831         g_free (cinfo);
 832
 833         return args_size;
 834 }
 835
 836 static int
 837 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 838 {
 839 #ifndef _MSC_VER
 840         __asm__ __volatile__ ("cpuid"
 841                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 842                 : "a" (id));
 843 #else
 844         int info[4];
 845         __cpuid(info, id);
 846         *p_eax = info[0];
 847         *p_ebx = info[1];
 848         *p_ecx = info[2];
 849         *p_edx = info[3];
 850 #endif
 851         return 1;
 852 }
 853
 854 /*
 855  * Initialize the cpu to execute managed code.
 856  */
 857 void
 858 mono_arch_cpu_init (void)
 859 {
 860 #ifndef _MSC_VER
 861         guint16 fpcw;
 862
 863         /* spec compliance requires running with double precision */
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865         fpcw &= ~X86_FPCW_PRECC_MASK;
 866         fpcw |= X86_FPCW_PREC_DOUBLE;
 867         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 868         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 869 #else
 870         /* TODO: This is crashing on Win64 right now.
 871         * _control87 (_PC_53, MCW_PC);
 872         */
 873 #endif
 874 }
 875
 876 /*
 877  * Initialize architecture specific code.
 878  */
 879 void
 880 mono_arch_init (void)
 881 {
 882         InitializeCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * Cleanup architecture specific code.
 887  */
 888 void
 889 mono_arch_cleanup (void)
 890 {
 891         DeleteCriticalSection (&mini_arch_mutex);
 892 }
 893
 894 /*
 895  * This function returns the optimizations supported on this cpu.
 896  */
 897 guint32
 898 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 899 {
 900         int eax, ebx, ecx, edx;
 901         guint32 opts = 0;
 902
 903         /* FIXME: AMD64 */
 904
 905         *exclude_mask = 0;
 906         /* Feature Flags function, flags returned in EDX. */
 907         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 908                 if (edx & (1 << 15)) {
 909                         opts |= MONO_OPT_CMOV;
 910                         if (edx & 1)
 911                                 opts |= MONO_OPT_FCMOV;
 912                         else
 913                                 *exclude_mask |= MONO_OPT_FCMOV;
 914                 } else
 915                         *exclude_mask |= MONO_OPT_CMOV;
 916         }
 917
 918         return opts;
 919 }
 920
 921 GList *
 922 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 923 {
 924         GList *vars = NULL;
 925         int i;
 926
 927         for (i = 0; i < cfg->num_varinfo; i++) {
 928                 MonoInst *ins = cfg->varinfo [i];
 929                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 930
 931                 /* unused vars */
 932                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 933                         continue;
 934
 935                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 936                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 937                         continue;
 938
 939                 if (mono_is_regsize_var (ins->inst_vtype)) {
 940                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 941                         g_assert (i == vmv->idx);
 942                         vars = g_list_prepend (vars, vmv);
 943                 }
 944         }
 945
 946         vars = mono_varlist_sort (cfg, vars, 0);
 947
 948         return vars;
 949 }
 950
 951 /**
 952  * mono_arch_compute_omit_fp:
 953  *
 954  *   Determine whenever the frame pointer can be eliminated.
 955  */
 956 static void
 957 mono_arch_compute_omit_fp (MonoCompile *cfg)
 958 {
 959         MonoMethodSignature *sig;
 960         MonoMethodHeader *header;
 961         int i, locals_size;
 962         CallInfo *cinfo;
 963
 964         if (cfg->arch.omit_fp_computed)
 965                 return;
 966
 967         header = mono_method_get_header (cfg->method);
 968
 969         sig = mono_method_signature (cfg->method);
 970
 971         if (!cfg->arch.cinfo)
 972                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 973         cinfo = cfg->arch.cinfo;
 974
 975         /*
 976          * FIXME: Remove some of the restrictions.
 977          */
 978         cfg->arch.omit_fp = TRUE;
 979         cfg->arch.omit_fp_computed = TRUE;
 980
 981         if (cfg->disable_omit_fp)
 982                 cfg->arch.omit_fp = FALSE;
 983
 984         if (!debug_omit_fp ())
 985                 cfg->arch.omit_fp = FALSE;
 986         /*
 987         if (cfg->method->save_lmf)
 988                 cfg->arch.omit_fp = FALSE;
 989         */
 990         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 991                 cfg->arch.omit_fp = FALSE;
 992         if (header->num_clauses)
 993                 cfg->arch.omit_fp = FALSE;
 994         if (cfg->param_area)
 995                 cfg->arch.omit_fp = FALSE;
 996         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 997                 cfg->arch.omit_fp = FALSE;
 998         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 999                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1000                 cfg->arch.omit_fp = FALSE;
1001         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1002                 ArgInfo *ainfo = &cinfo->args [i];
1003
1004                 if (ainfo->storage == ArgOnStack) {
1005                         /*
1006                          * The stack offset can only be determined when the frame
1007                          * size is known.
1008                          */
1009                         cfg->arch.omit_fp = FALSE;
1010                 }
1011         }
1012
1013         locals_size = 0;
1014         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015                 MonoInst *ins = cfg->varinfo [i];
1016                 int ialign;
1017
1018                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1019         }
1020
1021         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1022                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1023                 cfg->arch.omit_fp = FALSE;
1024         }
1025 }
1026
1027 GList *
1028 mono_arch_get_global_int_regs (MonoCompile *cfg)
1029 {
1030         GList *regs = NULL;
1031
1032         mono_arch_compute_omit_fp (cfg);
1033
1034         if (cfg->globalra) {
1035                 if (cfg->arch.omit_fp)
1036                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1037
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1043
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1052         } else {
1053                 if (cfg->arch.omit_fp)
1054                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1055
1056                 /* We use the callee saved registers for global allocation */
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1061                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1062         }
1063
1064         return regs;
1065 }
1066
1067 GList*
1068 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1069 {
1070         GList *regs = NULL;
1071         int i;
1072
1073         /* All XMM registers */
1074         for (i = 0; i < 16; ++i)
1075                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1076
1077         return regs;
1078 }
1079
1080 GList*
1081 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1082 {
1083         static GList *r = NULL;
1084
1085         if (r == NULL) {
1086                 GList *regs = NULL;
1087
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1094
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1102                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1103
1104                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1105         }
1106
1107         return r;
1108 }
1109
1110 GList*
1111 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1112 {
1113         int i;
1114         static GList *r = NULL;
1115
1116         if (r == NULL) {
1117                 GList *regs = NULL;
1118
1119                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1120                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1121
1122                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1123         }
1124
1125         return r;
1126 }
1127
1128 /*
1129  * mono_arch_regalloc_cost:
1130  *
1131  *  Return the cost, in number of memory references, of the action of
1132  * allocating the variable VMV into a register during global register
1133  * allocation.
1134  */
1135 guint32
1136 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1137 {
1138         MonoInst *ins = cfg->varinfo [vmv->idx];
1139
1140         if (cfg->method->save_lmf)
1141                 /* The register is already saved */
1142                 /* substract 1 for the invisible store in the prolog */
1143                 return (ins->opcode == OP_ARG) ? 0 : 1;
1144         else
1145                 /* push+pop */
1146                 return (ins->opcode == OP_ARG) ? 1 : 2;
1147 }
1148
1149 /*
1150  * mono_arch_fill_argument_info:
1151  *
1152  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1153  * of the method.
1154  */
1155 void
1156 mono_arch_fill_argument_info (MonoCompile *cfg)
1157 {
1158         MonoMethodSignature *sig;
1159         MonoMethodHeader *header;
1160         MonoInst *ins;
1161         int i;
1162         CallInfo *cinfo;
1163
1164         header = mono_method_get_header (cfg->method);
1165
1166         sig = mono_method_signature (cfg->method);
1167
1168         cinfo = cfg->arch.cinfo;
1169
1170         /*
1171          * Contrary to mono_arch_allocate_vars (), the information should describe
1172          * where the arguments are at the beginning of the method, not where they can be
1173          * accessed during the execution of the method. The later makes no sense for the
1174          * global register allocator, since a variable can be in more than one location.
1175          */
1176         if (sig->ret->type != MONO_TYPE_VOID) {
1177                 switch (cinfo->ret.storage) {
1178                 case ArgInIReg:
1179                 case ArgInFloatSSEReg:
1180                 case ArgInDoubleSSEReg:
1181                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1182                                 cfg->vret_addr->opcode = OP_REGVAR;
1183                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1184                         }
1185                         else {
1186                                 cfg->ret->opcode = OP_REGVAR;
1187                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1188                         }
1189                         break;
1190                 case ArgValuetypeInReg:
1191                         cfg->ret->opcode = OP_REGOFFSET;
1192                         cfg->ret->inst_basereg = -1;
1193                         cfg->ret->inst_offset = -1;
1194                         break;
1195                 default:
1196                         g_assert_not_reached ();
1197                 }
1198         }
1199
1200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1201                 ArgInfo *ainfo = &cinfo->args [i];
1202                 MonoType *arg_type;
1203
1204                 ins = cfg->args [i];
1205
1206                 if (sig->hasthis && (i == 0))
1207                         arg_type = &mono_defaults.object_class->byval_arg;
1208                 else
1209                         arg_type = sig->params [i - sig->hasthis];
1210
1211                 switch (ainfo->storage) {
1212                 case ArgInIReg:
1213                 case ArgInFloatSSEReg:
1214                 case ArgInDoubleSSEReg:
1215                         ins->opcode = OP_REGVAR;
1216                         ins->inst_c0 = ainfo->reg;
1217                         break;
1218                 case ArgOnStack:
1219                         ins->opcode = OP_REGOFFSET;
1220                         ins->inst_basereg = -1;
1221                         ins->inst_offset = -1;
1222                         break;
1223                 case ArgValuetypeInReg:
1224                         /* Dummy */
1225                         ins->opcode = OP_NOP;
1226                         break;
1227                 default:
1228                         g_assert_not_reached ();
1229                 }
1230         }
1231 }
1232
1233 void
1234 mono_arch_allocate_vars (MonoCompile *cfg)
1235 {
1236         MonoMethodSignature *sig;
1237         MonoMethodHeader *header;
1238         MonoInst *ins;
1239         int i, offset;
1240         guint32 locals_stack_size, locals_stack_align;
1241         gint32 *offsets;
1242         CallInfo *cinfo;
1243
1244         header = mono_method_get_header (cfg->method);
1245
1246         sig = mono_method_signature (cfg->method);
1247
1248         cinfo = cfg->arch.cinfo;
1249
1250         mono_arch_compute_omit_fp (cfg);
1251
1252         /*
1253          * We use the ABI calling conventions for managed code as well.
1254          * Exception: valuetypes are never passed or returned in registers.
1255          */
1256
1257         if (cfg->arch.omit_fp) {
1258                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1259                 cfg->frame_reg = AMD64_RSP;
1260                 offset = 0;
1261         } else {
1262                 /* Locals are allocated backwards from %fp */
1263                 cfg->frame_reg = AMD64_RBP;
1264                 offset = 0;
1265         }
1266
1267         if (cfg->method->save_lmf) {
1268                 /* Reserve stack space for saving LMF */
1269                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1270                 g_assert (offset == 0);
1271                 if (cfg->arch.omit_fp) {
1272                         cfg->arch.lmf_offset = offset;
1273                         offset += sizeof (MonoLMF);
1274                 }
1275                 else {
1276                         offset += sizeof (MonoLMF);
1277                         cfg->arch.lmf_offset = -offset;
1278                 }
1279         } else {
1280                 if (cfg->arch.omit_fp)
1281                         cfg->arch.reg_save_area_offset = offset;
1282                 /* Reserve space for caller saved registers */
1283                 for (i = 0; i < AMD64_NREG; ++i)
1284                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1285                                 offset += sizeof (gpointer);
1286                         }
1287         }
1288
1289         if (sig->ret->type != MONO_TYPE_VOID) {
1290                 switch (cinfo->ret.storage) {
1291                 case ArgInIReg:
1292                 case ArgInFloatSSEReg:
1293                 case ArgInDoubleSSEReg:
1294                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1295                                 if (cfg->globalra) {
1296                                         cfg->vret_addr->opcode = OP_REGVAR;
1297                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1298                                 } else {
1299                                         /* The register is volatile */
1300                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1301                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1302                                         if (cfg->arch.omit_fp) {
1303                                                 cfg->vret_addr->inst_offset = offset;
1304                                                 offset += 8;
1305                                         } else {
1306                                                 offset += 8;
1307                                                 cfg->vret_addr->inst_offset = -offset;
1308                                         }
1309                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1310                                                 printf ("vret_addr =");
1311                                                 mono_print_ins (cfg->vret_addr);
1312                                         }
1313                                 }
1314                         }
1315                         else {
1316                                 cfg->ret->opcode = OP_REGVAR;
1317                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1318                         }
1319                         break;
1320                 case ArgValuetypeInReg:
1321                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1322                         cfg->ret->opcode = OP_REGOFFSET;
1323                         cfg->ret->inst_basereg = cfg->frame_reg;
1324                         if (cfg->arch.omit_fp) {
1325                                 cfg->ret->inst_offset = offset;
1326                                 offset += 16;
1327                         } else {
1328                                 offset += 16;
1329                                 cfg->ret->inst_offset = - offset;
1330                         }
1331                         break;
1332                 default:
1333                         g_assert_not_reached ();
1334                 }
1335                 if (!cfg->globalra)
1336                         cfg->ret->dreg = cfg->ret->inst_c0;
1337         }
1338
1339         /* Allocate locals */
1340         if (!cfg->globalra) {
1341                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1342                 if (locals_stack_align) {
1343                         offset += (locals_stack_align - 1);
1344                         offset &= ~(locals_stack_align - 1);
1345                 }
1346                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1347                         if (offsets [i] != -1) {
1348                                 MonoInst *ins = cfg->varinfo [i];
1349                                 ins->opcode = OP_REGOFFSET;
1350                                 ins->inst_basereg = cfg->frame_reg;
1351                                 if (cfg->arch.omit_fp)
1352                                         ins->inst_offset = (offset + offsets [i]);
1353                                 else
1354                                         ins->inst_offset = - (offset + offsets [i]);
1355                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1356                         }
1357                 }
1358                 offset += locals_stack_size;
1359         }
1360
1361         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1362                 g_assert (!cfg->arch.omit_fp);
1363                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1364                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1365         }
1366
1367         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1368                 ins = cfg->args [i];
1369                 if (ins->opcode != OP_REGVAR) {
1370                         ArgInfo *ainfo = &cinfo->args [i];
1371                         gboolean inreg = TRUE;
1372                         MonoType *arg_type;
1373
1374                         if (sig->hasthis && (i == 0))
1375                                 arg_type = &mono_defaults.object_class->byval_arg;
1376                         else
1377                                 arg_type = sig->params [i - sig->hasthis];
1378
1379                         if (cfg->globalra) {
1380                                 /* The new allocator needs info about the original locations of the arguments */
1381                                 switch (ainfo->storage) {
1382                                 case ArgInIReg:
1383                                 case ArgInFloatSSEReg:
1384                                 case ArgInDoubleSSEReg:
1385                                         ins->opcode = OP_REGVAR;
1386                                         ins->inst_c0 = ainfo->reg;
1387                                         break;
1388                                 case ArgOnStack:
1389                                         g_assert (!cfg->arch.omit_fp);
1390                                         ins->opcode = OP_REGOFFSET;
1391                                         ins->inst_basereg = cfg->frame_reg;
1392                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1393                                         break;
1394                                 case ArgValuetypeInReg:
1395                                         ins->opcode = OP_REGOFFSET;
1396                                         ins->inst_basereg = cfg->frame_reg;
1397                                         /* These arguments are saved to the stack in the prolog */
1398                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1399                                         if (cfg->arch.omit_fp) {
1400                                                 ins->inst_offset = offset;
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                         } else {
1403                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1404                                                 ins->inst_offset = - offset;
1405                                         }
1406                                         break;
1407                                 default:
1408                                         g_assert_not_reached ();
1409                                 }
1410
1411                                 continue;
1412                         }
1413
1414                         /* FIXME: Allocate volatile arguments to registers */
1415                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1416                                 inreg = FALSE;
1417
1418                         /*
1419                          * Under AMD64, all registers used to pass arguments to functions
1420                          * are volatile across calls.
1421                          * FIXME: Optimize this.
1422                          */
1423                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1424                                 inreg = FALSE;
1425
1426                         ins->opcode = OP_REGOFFSET;
1427
1428                         switch (ainfo->storage) {
1429                         case ArgInIReg:
1430                         case ArgInFloatSSEReg:
1431                         case ArgInDoubleSSEReg:
1432                                 if (inreg) {
1433                                         ins->opcode = OP_REGVAR;
1434                                         ins->dreg = ainfo->reg;
1435                                 }
1436                                 break;
1437                         case ArgOnStack:
1438                                 g_assert (!cfg->arch.omit_fp);
1439                                 ins->opcode = OP_REGOFFSET;
1440                                 ins->inst_basereg = cfg->frame_reg;
1441                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1442                                 break;
1443                         case ArgValuetypeInReg:
1444                                 break;
1445                         case ArgValuetypeAddrInIReg: {
1446                                 MonoInst *indir;
1447                                 g_assert (!cfg->arch.omit_fp);
1448
1449                                 MONO_INST_NEW (cfg, indir, 0);
1450                                 indir->opcode = OP_REGOFFSET;
1451                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1452                                         indir->inst_basereg = cfg->frame_reg;
1453                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1454                                         offset += (sizeof (gpointer));
1455                                         indir->inst_offset = - offset;
1456                                 }
1457                                 else {
1458                                         indir->inst_basereg = cfg->frame_reg;
1459                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1460                                 }
1461
1462                                 ins->opcode = OP_VTARG_ADDR;
1463                                 ins->inst_left = indir;
1464
1465                                 break;
1466                         }
1467                         default:
1468                                 NOT_IMPLEMENTED;
1469                         }
1470
1471                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1472                                 ins->opcode = OP_REGOFFSET;
1473                                 ins->inst_basereg = cfg->frame_reg;
1474                                 /* These arguments are saved to the stack in the prolog */
1475                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1476                                 if (cfg->arch.omit_fp) {
1477                                         ins->inst_offset = offset;
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                 } else {
1480                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1481                                         ins->inst_offset = - offset;
1482                                 }
1483                         }
1484                 }
1485         }
1486
1487         cfg->stack_offset = offset;
1488 }
1489
1490 void
1491 mono_arch_create_vars (MonoCompile *cfg)
1492 {
1493         MonoMethodSignature *sig;
1494         CallInfo *cinfo;
1495
1496         sig = mono_method_signature (cfg->method);
1497
1498         if (!cfg->arch.cinfo)
1499                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1500         cinfo = cfg->arch.cinfo;
1501
1502         if (cinfo->ret.storage == ArgValuetypeInReg)
1503                 cfg->ret_var_is_local = TRUE;
1504
1505         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1506                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1507                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1508                         printf ("vret_addr = ");
1509                         mono_print_ins (cfg->vret_addr);
1510                 }
1511         }
1512 }
1513
1514 static void
1515 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1516 {
1517         switch (storage) {
1518         case ArgInIReg:
1519                 arg->opcode = OP_OUTARG_REG;
1520                 arg->inst_left = tree;
1521                 arg->inst_call = call;
1522                 arg->backend.reg3 = reg;
1523                 break;
1524         case ArgInFloatSSEReg:
1525                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1526                 arg->inst_left = tree;
1527                 arg->inst_call = call;
1528                 arg->backend.reg3 = reg;
1529                 break;
1530         case ArgInDoubleSSEReg:
1531                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1532                 arg->inst_left = tree;
1533                 arg->inst_call = call;
1534                 arg->backend.reg3 = reg;
1535                 break;
1536         default:
1537                 g_assert_not_reached ();
1538         }
1539 }
1540
1541 static void
1542 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1543 {
1544         MonoInst *ins;
1545
1546         switch (storage) {
1547         case ArgInIReg:
1548                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1549                 ins->dreg = mono_alloc_ireg (cfg);
1550                 ins->sreg1 = tree->dreg;
1551                 MONO_ADD_INS (cfg->cbb, ins);
1552                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1553                 break;
1554         case ArgInFloatSSEReg:
1555                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1556                 ins->dreg = mono_alloc_freg (cfg);
1557                 ins->sreg1 = tree->dreg;
1558                 MONO_ADD_INS (cfg->cbb, ins);
1559
1560                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1561                 break;
1562         case ArgInDoubleSSEReg:
1563                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1564                 ins->dreg = mono_alloc_freg (cfg);
1565                 ins->sreg1 = tree->dreg;
1566                 MONO_ADD_INS (cfg->cbb, ins);
1567
1568                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1569
1570                 break;
1571         default:
1572                 g_assert_not_reached ();
1573         }
1574 }
1575
1576 static int
1577 arg_storage_to_ldind (ArgStorage storage)
1578 {
1579         switch (storage) {
1580         case ArgInIReg:
1581                 return CEE_LDIND_I;
1582         case ArgInDoubleSSEReg:
1583                 return CEE_LDIND_R8;
1584         case ArgInFloatSSEReg:
1585                 return CEE_LDIND_R4;
1586         default:
1587                 g_assert_not_reached ();
1588         }
1589
1590         return -1;
1591 }
1592
1593 static int
1594 arg_storage_to_load_membase (ArgStorage storage)
1595 {
1596         switch (storage) {
1597         case ArgInIReg:
1598                 return OP_LOAD_MEMBASE;
1599         case ArgInDoubleSSEReg:
1600                 return OP_LOADR8_MEMBASE;
1601         case ArgInFloatSSEReg:
1602                 return OP_LOADR4_MEMBASE;
1603         default:
1604                 g_assert_not_reached ();
1605         }
1606
1607         return -1;
1608 }
1609
1610 static void
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1612 {
1613         MonoInst *arg;
1614         MonoMethodSignature *tmp_sig;
1615         MonoInst *sig_arg;
1616
1617         /* FIXME: Add support for signature tokens to AOT */
1618         cfg->disable_aot = TRUE;
1619
1620         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1621
1622         /*
1623          * mono_ArgIterator_Setup assumes the signature cookie is
1624          * passed first and all the arguments which were before it are
1625          * passed on the stack after the signature. So compensate by
1626          * passing a different signature.
1627          */
1628         tmp_sig = mono_metadata_signature_dup (call->signature);
1629         tmp_sig->param_count -= call->signature->sentinelpos;
1630         tmp_sig->sentinelpos = 0;
1631         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1632
1633         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1634         sig_arg->inst_p0 = tmp_sig;
1635
1636         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1637         arg->inst_left = sig_arg;
1638         arg->type = STACK_PTR;
1639
1640         /* prepend, so they get reversed */
1641         arg->next = call->out_args;
1642         call->out_args = arg;
1643 }
1644
1645 /*
1646  * take the arguments and generate the arch-specific
1647  * instructions to properly call the function in call.
1648  * This includes pushing, moving arguments to the right register
1649  * etc.
1650  */
1651 MonoCallInst*
1652 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1653         MonoInst *arg, *in;
1654         MonoMethodSignature *sig;
1655         int i, n, stack_size;
1656         CallInfo *cinfo;
1657         ArgInfo *ainfo;
1658
1659         stack_size = 0;
1660
1661         sig = call->signature;
1662         n = sig->param_count + sig->hasthis;
1663
1664         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1665
1666         if (cfg->method->save_lmf) {
1667                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1668                 arg->next = call->out_args;
1669                 call->out_args = arg;
1670         }
1671
1672         for (i = 0; i < n; ++i) {
1673                 ainfo = cinfo->args + i;
1674
1675                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1676                         /* Emit the signature cookie just before the implicit arguments */
1677                         emit_sig_cookie (cfg, call, cinfo);
1678                 }
1679
1680                 if (is_virtual && i == 0) {
1681                         /* the argument will be attached to the call instruction */
1682                         in = call->args [i];
1683                 } else {
1684                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1685                         in = call->args [i];
1686                         arg->cil_code = in->cil_code;
1687                         arg->inst_left = in;
1688                         arg->type = in->type;
1689                         /* prepend, so they get reversed */
1690                         arg->next = call->out_args;
1691                         call->out_args = arg;
1692 #if 0
1693                         if (!cinfo->stack_usage)
1694                                 /* Keep the assignments to the arg registers in order if possible */
1695                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1696                         else
1697                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1698 #endif
1699
1700                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1701                                 guint32 align;
1702                                 guint32 size;
1703
1704                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1705                                         size = sizeof (MonoTypedRef);
1706                                         align = sizeof (gpointer);
1707                                 }
1708                                 else
1709                                 if (sig->pinvoke)
1710                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1711                                 else {
1712                                         /*
1713                                          * Other backends use mini_type_stack_size (), but that
1714                                          * aligns the size to 8, which is larger than the size of
1715                                          * the source, leading to reads of invalid memory if the
1716                                          * source is at the end of address space.
1717                                          */
1718                                         size = mono_class_value_size (in->klass, &align);
1719                                 }
1720                                 if (ainfo->storage == ArgValuetypeInReg) {
1721                                         if (ainfo->pair_storage [1] == ArgNone) {
1722                                                 MonoInst *load;
1723
1724                                                 /* Simpler case */
1725
1726                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1727                                                 load->inst_left = in;
1728
1729                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1730                                         }
1731                                         else {
1732                                                 /* Trees can't be shared so make a copy */
1733                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1734                                                 MonoInst *load, *load2, *offset_ins;
1735
1736                                                 /* Reg1 */
1737                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1738                                                 load->ssa_op = MONO_SSA_LOAD;
1739                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1740
1741                                                 NEW_ICONST (cfg, offset_ins, 0);
1742                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1743                                                 load2->inst_left = load;
1744                                                 load2->inst_right = offset_ins;
1745
1746                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1747                                                 load->inst_left = load2;
1748
1749                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1750
1751                                                 /* Reg2 */
1752                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1753                                                 load->ssa_op = MONO_SSA_LOAD;
1754                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1755
1756                                                 NEW_ICONST (cfg, offset_ins, 8);
1757                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1758                                                 load2->inst_left = load;
1759                                                 load2->inst_right = offset_ins;
1760
1761                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1762                                                 load->inst_left = load2;
1763
1764                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1765                                                 arg->cil_code = in->cil_code;
1766                                                 arg->type = in->type;
1767                                                 /* prepend, so they get reversed */
1768                                                 arg->next = call->out_args;
1769                                                 call->out_args = arg;
1770
1771                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1772
1773                                                 /* Prepend a copy inst */
1774                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1775                                                 arg->cil_code = in->cil_code;
1776                                                 arg->ssa_op = MONO_SSA_STORE;
1777                                                 arg->inst_left = vtaddr;
1778                                                 arg->inst_right = in;
1779                                                 arg->type = in->type;
1780
1781                                                 /* prepend, so they get reversed */
1782                                                 arg->next = call->out_args;
1783                                                 call->out_args = arg;
1784                                         }
1785                                 }
1786                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1787
1788                                         /* Add a temp variable to the method*/
1789                                         MonoInst *load;
1790                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1791
1792                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1793                                         load->ssa_op = MONO_SSA_LOAD;
1794                                         load->inst_left = vtaddr;
1795
1796                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1797                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1798                                                 arg->opcode = OP_OUTARG_REG;
1799                                                 arg->inst_left = load;
1800                                                 arg->inst_call = call;
1801                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1802                                         }
1803                                         else {
1804                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1805                                                 arg->opcode = OP_OUTARG_VT;
1806                                                 arg->inst_left = load;
1807                                                 arg->type = STACK_PTR;
1808                                                 arg->klass = mono_defaults.int_class;
1809                                                 arg->backend.is_pinvoke = sig->pinvoke;
1810                                                 arg->inst_imm = size;
1811                                         }
1812
1813                                         /*Copy the argument to the temp variable.*/
1814                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1815                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1816                                         load->backend.memcpy_args->size = size;
1817                                         load->backend.memcpy_args->align = align;
1818                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1819                                         load->inst_right = in->inst_i0;
1820
1821                                         // FIXME:
1822                                         g_assert_not_reached ();
1823                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1824                                 }
1825                                 else {
1826                                         arg->opcode = OP_OUTARG_VT;
1827                                         arg->klass = in->klass;
1828                                         arg->backend.is_pinvoke = sig->pinvoke;
1829                                         arg->inst_imm = size;
1830                                 }
1831                         }
1832                         else {
1833                                 switch (ainfo->storage) {
1834                                 case ArgInIReg:
1835                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1836                                         break;
1837                                 case ArgInFloatSSEReg:
1838                                 case ArgInDoubleSSEReg:
1839                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1840                                         break;
1841                                 case ArgOnStack:
1842                                         arg->opcode = OP_OUTARG;
1843                                         if (!sig->params [i - sig->hasthis]->byref) {
1844                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1845                                                         arg->opcode = OP_OUTARG_R4;
1846                                                 else
1847                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1848                                                                 arg->opcode = OP_OUTARG_R8;
1849                                         }
1850                                         break;
1851                                 default:
1852                                         g_assert_not_reached ();
1853                                 }
1854                         }
1855                 }
1856         }
1857
1858         /* Handle the case where there are no implicit arguments */
1859         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1860                 emit_sig_cookie (cfg, call, cinfo);
1861         }
1862
1863         if (cinfo->ret.storage == ArgValuetypeInReg) {
1864                 /* This is needed by mono_arch_emit_this_vret_args () */
1865                 if (!cfg->arch.vret_addr_loc) {
1866                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867                         /* Prevent it from being register allocated or optimized away */
1868                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1869                 }
1870         }
1871
1872         if (cinfo->need_stack_align) {
1873                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1874                 arg->inst_c0 = 8;
1875                 /* prepend, so they get reversed */
1876                 arg->next = call->out_args;
1877                 call->out_args = arg;
1878         }
1879
1880 #ifdef PLATFORM_WIN32
1881         /* Always reserve 32 bytes of stack space on Win64 */
1882         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1883         arg->inst_c0 = 32;
1884         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1885         NOT_IMPLEMENTED;
1886 #endif
1887
1888 #if 0
1889         if (cfg->method->save_lmf) {
1890                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1891                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1892         }
1893 #endif
1894
1895         call->stack_usage = cinfo->stack_usage;
1896         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1897         cfg->flags |= MONO_CFG_HAS_CALLS;
1898
1899         return call;
1900 }
1901
1902 static void
1903 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1904 {
1905         MonoInst *arg;
1906         MonoMethodSignature *tmp_sig;
1907         MonoInst *sig_arg;
1908
1909         if (call->tail_call)
1910                 NOT_IMPLEMENTED;
1911
1912         /* FIXME: Add support for signature tokens to AOT */
1913         cfg->disable_aot = TRUE;
1914
1915         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1916
1917         /*
1918          * mono_ArgIterator_Setup assumes the signature cookie is
1919          * passed first and all the arguments which were before it are
1920          * passed on the stack after the signature. So compensate by
1921          * passing a different signature.
1922          */
1923         tmp_sig = mono_metadata_signature_dup (call->signature);
1924         tmp_sig->param_count -= call->signature->sentinelpos;
1925         tmp_sig->sentinelpos = 0;
1926         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1927
1928         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1929         sig_arg->dreg = mono_alloc_ireg (cfg);
1930         sig_arg->inst_p0 = tmp_sig;
1931         MONO_ADD_INS (cfg->cbb, sig_arg);
1932
1933         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1934         arg->sreg1 = sig_arg->dreg;
1935         MONO_ADD_INS (cfg->cbb, arg);
1936 }
1937
1938 void
1939 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1940 {
1941         MonoInst *arg, *in;
1942         MonoMethodSignature *sig;
1943         int i, n, stack_size;
1944         CallInfo *cinfo;
1945         ArgInfo *ainfo;
1946
1947         stack_size = 0;
1948
1949         sig = call->signature;
1950         n = sig->param_count + sig->hasthis;
1951
1952         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1953
1954         if (cinfo->need_stack_align) {
1955                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1956         }
1957
1958         /*
1959          * Emit all parameters passed in registers in non-reverse order for better readability
1960          * and to help the optimization in emit_prolog ().
1961          */
1962         for (i = 0; i < n; ++i) {
1963                 ainfo = cinfo->args + i;
1964
1965                 in = call->args [i];
1966
1967                 if (ainfo->storage == ArgInIReg)
1968                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1969         }
1970
1971         for (i = n - 1; i >= 0; --i) {
1972                 ainfo = cinfo->args + i;
1973
1974                 in = call->args [i];
1975
1976                 switch (ainfo->storage) {
1977                 case ArgInIReg:
1978                         /* Already done */
1979                         break;
1980                 case ArgInFloatSSEReg:
1981                 case ArgInDoubleSSEReg:
1982                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1983                         break;
1984                 case ArgOnStack:
1985                 case ArgValuetypeInReg:
1986                 case ArgValuetypeAddrInIReg:
1987                         if (ainfo->storage == ArgOnStack && call->tail_call)
1988                                 NOT_IMPLEMENTED;
1989                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1990                                 guint32 align;
1991                                 guint32 size;
1992
1993                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1994                                         size = sizeof (MonoTypedRef);
1995                                         align = sizeof (gpointer);
1996                                 }
1997                                 else {
1998                                         if (sig->pinvoke)
1999                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2000                                         else {
2001                                                 /*
2002                                                  * Other backends use mono_type_stack_size (), but that
2003                                                  * aligns the size to 8, which is larger than the size of
2004                                                  * the source, leading to reads of invalid memory if the
2005                                                  * source is at the end of address space.
2006                                                  */
2007                                                 size = mono_class_value_size (in->klass, &align);
2008                                         }
2009                                 }
2010                                 g_assert (in->klass);
2011
2012                                 if (size > 0) {
2013                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2014                                         arg->sreg1 = in->dreg;
2015                                         arg->klass = in->klass;
2016                                         arg->backend.size = size;
2017                                         arg->inst_p0 = call;
2018                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2019                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2020
2021                                         MONO_ADD_INS (cfg->cbb, arg);
2022                                 }
2023                         } else {
2024                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2025                                 arg->sreg1 = in->dreg;
2026                                 if (!sig->params [i - sig->hasthis]->byref) {
2027                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2028                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2029                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2030                                                 arg->inst_destbasereg = X86_ESP;
2031                                                 arg->inst_offset = 0;
2032                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2033                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2034                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2035                                                 arg->inst_destbasereg = X86_ESP;
2036                                                 arg->inst_offset = 0;
2037                                         }
2038                                 }
2039                                 MONO_ADD_INS (cfg->cbb, arg);
2040                         }
2041                         break;
2042                 default:
2043                         g_assert_not_reached ();
2044                 }
2045
2046                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2047                         /* Emit the signature cookie just before the implicit arguments */
2048                         emit_sig_cookie2 (cfg, call, cinfo);
2049                 }
2050         }
2051
2052         /* Handle the case where there are no implicit arguments */
2053         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2054                 emit_sig_cookie2 (cfg, call, cinfo);
2055         }
2056
2057         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2058                 MonoInst *vtarg;
2059
2060                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2061                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2062                                 /*
2063                                  * Tell the JIT to use a more efficient calling convention: call using
2064                                  * OP_CALL, compute the result location after the call, and save the
2065                                  * result there.
2066                                  */
2067                                 call->vret_in_reg = TRUE;
2068                                 /*
2069                                  * Nullify the instruction computing the vret addr to enable
2070                                  * future optimizations.
2071                                  */
2072                                 if (call->vret_var)
2073                                         NULLIFY_INS (call->vret_var);
2074                         } else {
2075                                 if (call->tail_call)
2076                                         NOT_IMPLEMENTED;
2077                                 /*
2078                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2079                                  * the stack. Push the address here, so the call instruction can
2080                                  * access it.
2081                                  */
2082                                 if (!cfg->arch.vret_addr_loc) {
2083                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2084                                         /* Prevent it from being register allocated or optimized away */
2085                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2086                                 }
2087
2088                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2089                         }
2090                 }
2091                 else {
2092                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2093                         vtarg->sreg1 = call->vret_var->dreg;
2094                         vtarg->dreg = mono_alloc_preg (cfg);
2095                         MONO_ADD_INS (cfg->cbb, vtarg);
2096
2097                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2098                 }
2099         }
2100
2101 #ifdef PLATFORM_WIN32
2102         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2103                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2104         }
2105 #endif
2106
2107         if (cfg->method->save_lmf) {
2108                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2109                 MONO_ADD_INS (cfg->cbb, arg);
2110         }
2111
2112         call->stack_usage = cinfo->stack_usage;
2113 }
2114
2115 void
2116 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2117 {
2118         MonoInst *arg;
2119         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2120         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2121         int size = ins->backend.size;
2122
2123         if (ainfo->storage == ArgValuetypeInReg) {
2124                 MonoInst *load;
2125                 int part;
2126
2127                 for (part = 0; part < 2; ++part) {
2128                         if (ainfo->pair_storage [part] == ArgNone)
2129                                 continue;
2130
2131                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2132                         load->inst_basereg = src->dreg;
2133                         load->inst_offset = part * sizeof (gpointer);
2134
2135                         switch (ainfo->pair_storage [part]) {
2136                         case ArgInIReg:
2137                                 load->dreg = mono_alloc_ireg (cfg);
2138                                 break;
2139                         case ArgInDoubleSSEReg:
2140                         case ArgInFloatSSEReg:
2141                                 load->dreg = mono_alloc_freg (cfg);
2142                                 break;
2143                         default:
2144                                 g_assert_not_reached ();
2145                         }
2146                         MONO_ADD_INS (cfg->cbb, load);
2147
2148                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2149                 }
2150         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2151                 MonoInst *vtaddr, *load;
2152                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2153
2154                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2155                 load->inst_p0 = vtaddr;
2156                 vtaddr->flags |= MONO_INST_INDIRECT;
2157                 load->type = STACK_MP;
2158                 load->klass = vtaddr->klass;
2159                 load->dreg = mono_alloc_ireg (cfg);
2160                 MONO_ADD_INS (cfg->cbb, load);
2161                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2162
2163                 if (ainfo->pair_storage [0] == ArgInIReg) {
2164                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2165                         arg->dreg = ainfo->pair_regs [0];
2166                         arg->sreg1 = load->dreg;
2167                         arg->inst_imm = 0;
2168                         MONO_ADD_INS (cfg->cbb, arg);
2169                 } else {
2170                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2171                         arg->sreg1 = load->dreg;
2172                         MONO_ADD_INS (cfg->cbb, arg);
2173                 }
2174         } else {
2175                 if (size == 8) {
2176                         /* Can't use this for < 8 since it does an 8 byte memory load */
2177                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2178                         arg->inst_basereg = src->dreg;
2179                         arg->inst_offset = 0;
2180                         MONO_ADD_INS (cfg->cbb, arg);
2181                 } else if (size <= 40) {
2182                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2183                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2184                 } else {
2185                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2186                         arg->inst_basereg = src->dreg;
2187                         arg->inst_offset = 0;
2188                         arg->inst_imm = size;
2189                         MONO_ADD_INS (cfg->cbb, arg);
2190                 }
2191         }
2192 }
2193
2194 void
2195 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2196 {
2197         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2198
2199         if (!ret->byref) {
2200                 if (ret->type == MONO_TYPE_R4) {
2201                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2202                         return;
2203                 } else if (ret->type == MONO_TYPE_R8) {
2204                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2205                         return;
2206                 }
2207         }
2208
2209         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2210 }
2211
2212 #define EMIT_COND_BRANCH(ins,cond,sign) \
2213 if (ins->flags & MONO_INST_BRLABEL) { \
2214         if (ins->inst_i0->inst_c0) { \
2215                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2216         } else { \
2217                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2218                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2219                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2220                         x86_branch8 (code, cond, 0, sign); \
2221                 else \
2222                         x86_branch32 (code, cond, 0, sign); \
2223         } \
2224 } else { \
2225         if (ins->inst_true_bb->native_offset) { \
2226                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2227         } else { \
2228                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2229                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2230                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2231                         x86_branch8 (code, cond, 0, sign); \
2232                 else \
2233                         x86_branch32 (code, cond, 0, sign); \
2234         } \
2235 }
2236
2237 /* emit an exception if condition is fail */
2238 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2239         do {                                                        \
2240                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2241                 if (tins == NULL) {                                                                             \
2242                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2243                                         MONO_PATCH_INFO_EXC, exc_name);  \
2244                         x86_branch32 (code, cond, 0, signed);               \
2245                 } else {        \
2246                         EMIT_COND_BRANCH (tins, cond, signed);  \
2247                 }                       \
2248         } while (0);
2249
2250 #define EMIT_FPCOMPARE(code) do { \
2251         amd64_fcompp (code); \
2252         amd64_fnstsw (code); \
2253 } while (0);
2254
2255 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2256     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2257         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2258         amd64_ ##op (code); \
2259         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2260         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2261 } while (0);
2262
2263 static guint8*
2264 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2265 {
2266         gboolean no_patch = FALSE;
2267
2268         /*
2269          * FIXME: Add support for thunks
2270          */
2271         {
2272                 gboolean near_call = FALSE;
2273
2274                 /*
2275                  * Indirect calls are expensive so try to make a near call if possible.
2276                  * The caller memory is allocated by the code manager so it is
2277                  * guaranteed to be at a 32 bit offset.
2278                  */
2279
2280                 if (patch_type != MONO_PATCH_INFO_ABS) {
2281                         /* The target is in memory allocated using the code manager */
2282                         near_call = TRUE;
2283
2284                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2285                                 if (((MonoMethod*)data)->klass->image->aot_module)
2286                                         /* The callee might be an AOT method */
2287                                         near_call = FALSE;
2288                                 if (((MonoMethod*)data)->dynamic)
2289                                         /* The target is in malloc-ed memory */
2290                                         near_call = FALSE;
2291                         }
2292
2293                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2294                                 /*
2295                                  * The call might go directly to a native function without
2296                                  * the wrapper.
2297                                  */
2298                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2299                                 if (mi) {
2300                                         gconstpointer target = mono_icall_get_wrapper (mi);
2301                                         if ((((guint64)target) >> 32) != 0)
2302                                                 near_call = FALSE;
2303                                 }
2304                         }
2305                 }
2306                 else {
2307                         if (!cfg->new_ir && mono_find_class_init_trampoline_by_addr (data))
2308                                 near_call = TRUE;
2309                         else if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2310                                 /*
2311                                  * This is not really an optimization, but required because the
2312                                  * generic class init trampolines use R11 to pass the vtable.
2313                                  */
2314                                 near_call = TRUE;
2315                         } else {
2316                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2317                                 if (info) {
2318                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2319                                                 strstr (cfg->method->name, info->name)) {
2320                                                 /* A call to the wrapped function */
2321                                                 if ((((guint64)data) >> 32) == 0)
2322                                                         near_call = TRUE;
2323                                                 no_patch = TRUE;
2324                                         }
2325                                         else if (info->func == info->wrapper) {
2326                                                 /* No wrapper */
2327                                                 if ((((guint64)info->func) >> 32) == 0)
2328                                                         near_call = TRUE;
2329                                         }
2330                                         else {
2331                                                 /* See the comment in mono_codegen () */
2332                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2333                                                         near_call = TRUE;
2334                                         }
2335                                 }
2336                                 else if ((((guint64)data) >> 32) == 0) {
2337                                         near_call = TRUE;
2338                                         no_patch = TRUE;
2339                                 }
2340                         }
2341                 }
2342
2343                 if (cfg->method->dynamic)
2344                         /* These methods are allocated using malloc */
2345                         near_call = FALSE;
2346
2347                 if (cfg->compile_aot)
2348                         near_call = TRUE;
2349
2350 #ifdef MONO_ARCH_NOMAP32BIT
2351                 near_call = FALSE;
2352 #endif
2353
2354                 if (near_call) {
2355                         /*
2356                          * Align the call displacement to an address divisible by 4 so it does
2357                          * not span cache lines. This is required for code patching to work on SMP
2358                          * systems.
2359                          */
2360                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2361                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2362                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2363                         amd64_call_code (code, 0);
2364                 }
2365                 else {
2366                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2367                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2368                         amd64_call_reg (code, GP_SCRATCH_REG);
2369                 }
2370         }
2371
2372         return code;
2373 }
2374
2375 static inline guint8*
2376 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2377 {
2378 #ifdef PLATFORM_WIN32
2379         if (win64_adjust_stack)
2380                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2381 #endif
2382         code = emit_call_body (cfg, code, patch_type, data);
2383 #ifdef PLATFORM_WIN32
2384         if (win64_adjust_stack)
2385                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2386 #endif
2387
2388         return code;
2389 }
2390
2391 static inline int
2392 store_membase_imm_to_store_membase_reg (int opcode)
2393 {
2394         switch (opcode) {
2395         case OP_STORE_MEMBASE_IMM:
2396                 return OP_STORE_MEMBASE_REG;
2397         case OP_STOREI4_MEMBASE_IMM:
2398                 return OP_STOREI4_MEMBASE_REG;
2399         case OP_STOREI8_MEMBASE_IMM:
2400                 return OP_STOREI8_MEMBASE_REG;
2401         }
2402
2403         return -1;
2404 }
2405
2406 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2407
2408 /*
2409  * mono_arch_peephole_pass_1:
2410  *
2411  *   Perform peephole opts which should/can be performed before local regalloc
2412  */
2413 void
2414 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2415 {
2416         MonoInst *ins, *n;
2417
2418         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2419                 MonoInst *last_ins = ins->prev;
2420
2421                 switch (ins->opcode) {
2422                 case OP_ADD_IMM:
2423                 case OP_IADD_IMM:
2424                 case OP_LADD_IMM:
2425                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2426                                 /*
2427                                  * X86_LEA is like ADD, but doesn't have the
2428                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2429                                  * its operand to 64 bit.
2430                                  */
2431                                 ins->opcode = OP_X86_LEA_MEMBASE;
2432                                 ins->inst_basereg = ins->sreg1;
2433                         }
2434                         break;
2435                 case OP_LXOR:
2436                 case OP_IXOR:
2437                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2438                                 MonoInst *ins2;
2439
2440                                 /*
2441                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2442                                  * the latter has length 2-3 instead of 6 (reverse constant
2443                                  * propagation). These instruction sequences are very common
2444                                  * in the initlocals bblock.
2445                                  */
2446                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2447                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2448                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2449                                                 ins2->sreg1 = ins->dreg;
2450                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2451                                                 /* Continue */
2452                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2453                                                 NULLIFY_INS (ins2);
2454                                                 /* Continue */
2455                                         } else {
2456                                                 break;
2457                                         }
2458                                 }
2459                         }
2460                         break;
2461                 case OP_COMPARE_IMM:
2462                 case OP_LCOMPARE_IMM:
2463                         /* OP_COMPARE_IMM (reg, 0)
2464                          * -->
2465                          * OP_AMD64_TEST_NULL (reg)
2466                          */
2467                         if (!ins->inst_imm)
2468                                 ins->opcode = OP_AMD64_TEST_NULL;
2469                         break;
2470                 case OP_ICOMPARE_IMM:
2471                         if (!ins->inst_imm)
2472                                 ins->opcode = OP_X86_TEST_NULL;
2473                         break;
2474                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2475                         /*
2476                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2477                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2478                          * -->
2479                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2480                          * OP_COMPARE_IMM reg, imm
2481                          *
2482                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2483                          */
2484                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2485                             ins->inst_basereg == last_ins->inst_destbasereg &&
2486                             ins->inst_offset == last_ins->inst_offset) {
2487                                         ins->opcode = OP_ICOMPARE_IMM;
2488                                         ins->sreg1 = last_ins->sreg1;
2489
2490                                         /* check if we can remove cmp reg,0 with test null */
2491                                         if (!ins->inst_imm)
2492                                                 ins->opcode = OP_X86_TEST_NULL;
2493                                 }
2494
2495                         break;
2496                 }
2497
2498                 mono_peephole_ins (bb, ins);
2499         }
2500 }
2501
2502 void
2503 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2504 {
2505         MonoInst *ins, *n;
2506
2507         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2508                 switch (ins->opcode) {
2509                 case OP_ICONST:
2510                 case OP_I8CONST: {
2511                         /* reg = 0 -> XOR (reg, reg) */
2512                         /* XOR sets cflags on x86, so we cant do it always */
2513                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2514                                 ins->opcode = OP_LXOR;
2515                                 ins->sreg1 = ins->dreg;
2516                                 ins->sreg2 = ins->dreg;
2517                                 /* Fall through */
2518                         } else {
2519                                 break;
2520                         }
2521                 }
2522                 case OP_LXOR:
2523                         /*
2524                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2525                          * 0 result into 64 bits.
2526                          */
2527                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2528                                 ins->opcode = OP_IXOR;
2529                         }
2530                         /* Fall through */
2531                 case OP_IXOR:
2532                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2533                                 MonoInst *ins2;
2534
2535                                 /*
2536                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2537                                  * the latter has length 2-3 instead of 6 (reverse constant
2538                                  * propagation). These instruction sequences are very common
2539                                  * in the initlocals bblock.
2540                                  */
2541                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2542                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2543                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2544                                                 ins2->sreg1 = ins->dreg;
2545                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2546                                                 /* Continue */
2547                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2548                                                 NULLIFY_INS (ins2);
2549                                                 /* Continue */
2550                                         } else {
2551                                                 break;
2552                                         }
2553                                 }
2554                         }
2555                         break;
2556                 case OP_IADD_IMM:
2557                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2558                                 ins->opcode = OP_X86_INC_REG;
2559                         break;
2560                 case OP_ISUB_IMM:
2561                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2562                                 ins->opcode = OP_X86_DEC_REG;
2563                         break;
2564                 }
2565
2566                 mono_peephole_ins (bb, ins);
2567         }
2568 }
2569
2570 #define NEW_INS(cfg,ins,dest,op) do {   \
2571                 MONO_INST_NEW ((cfg), (dest), (op)); \
2572         (dest)->cil_code = (ins)->cil_code; \
2573         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2574         } while (0)
2575
2576 /*
2577  * mono_arch_lowering_pass:
2578  *
2579  *  Converts complex opcodes into simpler ones so that each IR instruction
2580  * corresponds to one machine instruction.
2581  */
2582 void
2583 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2584 {
2585         MonoInst *ins, *n, *temp;
2586
2587         if (bb->max_vreg > cfg->rs->next_vreg)
2588                 cfg->rs->next_vreg = bb->max_vreg;
2589
2590         /*
2591          * FIXME: Need to add more instructions, but the current machine
2592          * description can't model some parts of the composite instructions like
2593          * cdq.
2594          */
2595         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2596                 switch (ins->opcode) {
2597                 case OP_DIV_IMM:
2598                 case OP_REM_IMM:
2599                 case OP_IDIV_IMM:
2600                 case OP_IREM_IMM:
2601                 case OP_IDIV_UN_IMM:
2602                 case OP_IREM_UN_IMM:
2603                         mono_decompose_op_imm (cfg, bb, ins);
2604                         break;
2605                 case OP_COMPARE_IMM:
2606                 case OP_LCOMPARE_IMM:
2607                         if (!amd64_is_imm32 (ins->inst_imm)) {
2608                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2609                                 temp->inst_c0 = ins->inst_imm;
2610                                 if (cfg->globalra)
2611                                         temp->dreg = mono_alloc_ireg (cfg);
2612                                 else
2613                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2614                                 ins->opcode = OP_COMPARE;
2615                                 ins->sreg2 = temp->dreg;
2616                         }
2617                         break;
2618                 case OP_LOAD_MEMBASE:
2619                 case OP_LOADI8_MEMBASE:
2620                         if (!amd64_is_imm32 (ins->inst_offset)) {
2621                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2622                                 temp->inst_c0 = ins->inst_offset;
2623                                 if (cfg->globalra)
2624                                         temp->dreg = mono_alloc_ireg (cfg);
2625                                 else
2626                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2627                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2628                                 ins->inst_indexreg = temp->dreg;
2629                         }
2630                         break;
2631                 case OP_STORE_MEMBASE_IMM:
2632                 case OP_STOREI8_MEMBASE_IMM:
2633                         if (!amd64_is_imm32 (ins->inst_imm)) {
2634                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2635                                 temp->inst_c0 = ins->inst_imm;
2636                                 if (cfg->globalra)
2637                                         temp->dreg = mono_alloc_ireg (cfg);
2638                                 else
2639                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2640                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2641                                 ins->sreg1 = temp->dreg;
2642                         }
2643                         break;
2644                 default:
2645                         break;
2646                 }
2647         }
2648
2649         bb->max_vreg = cfg->rs->next_vreg;
2650 }
2651
2652 static const int
2653 branch_cc_table [] = {
2654         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2655         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2656         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2657 };
2658
2659 /* Maps CMP_... constants to X86_CC_... constants */
2660 static const int
2661 cc_table [] = {
2662         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2663         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2664 };
2665
2666 static const int
2667 cc_signed_table [] = {
2668         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2669         FALSE, FALSE, FALSE, FALSE
2670 };
2671
2672 /*#include "cprop.c"*/
2673
2674 static unsigned char*
2675 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2676 {
2677         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2678
2679         if (size == 1)
2680                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2681         else if (size == 2)
2682                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2683         return code;
2684 }
2685
2686 static unsigned char*
2687 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2688 {
2689         int sreg = tree->sreg1;
2690         int need_touch = FALSE;
2691
2692 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2693         if (!tree->flags & MONO_INST_INIT)
2694                 need_touch = TRUE;
2695 #endif
2696
2697         if (need_touch) {
2698                 guint8* br[5];
2699
2700                 /*
2701                  * Under Windows:
2702                  * If requested stack size is larger than one page,
2703                  * perform stack-touch operation
2704                  */
2705                 /*
2706                  * Generate stack probe code.
2707                  * Under Windows, it is necessary to allocate one page at a time,
2708                  * "touching" stack after each successful sub-allocation. This is
2709                  * because of the way stack growth is implemented - there is a
2710                  * guard page before the lowest stack page that is currently commited.
2711                  * Stack normally grows sequentially so OS traps access to the
2712                  * guard page and commits more pages when needed.
2713                  */
2714                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2715                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2716
2717                 br[2] = code; /* loop */
2718                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2719                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2720                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2721                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2722                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2723                 amd64_patch (br[3], br[2]);
2724                 amd64_test_reg_reg (code, sreg, sreg);
2725                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2726                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2727
2728                 br[1] = code; x86_jump8 (code, 0);
2729
2730                 amd64_patch (br[0], code);
2731                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2732                 amd64_patch (br[1], code);
2733                 amd64_patch (br[4], code);
2734         }
2735         else
2736                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2737
2738         if (tree->flags & MONO_INST_INIT) {
2739                 int offset = 0;
2740                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2741                         amd64_push_reg (code, AMD64_RAX);
2742                         offset += 8;
2743                 }
2744                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2745                         amd64_push_reg (code, AMD64_RCX);
2746                         offset += 8;
2747                 }
2748                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2749                         amd64_push_reg (code, AMD64_RDI);
2750                         offset += 8;
2751                 }
2752
2753                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2754                 if (sreg != AMD64_RCX)
2755                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2756                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2757
2758                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2759                 amd64_cld (code);
2760                 amd64_prefix (code, X86_REP_PREFIX);
2761                 amd64_stosl (code);
2762
2763                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2764                         amd64_pop_reg (code, AMD64_RDI);
2765                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2766                         amd64_pop_reg (code, AMD64_RCX);
2767                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2768                         amd64_pop_reg (code, AMD64_RAX);
2769         }
2770         return code;
2771 }
2772
2773 static guint8*
2774 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2775 {
2776         CallInfo *cinfo;
2777         guint32 quad;
2778
2779         /* Move return value to the target register */
2780         /* FIXME: do this in the local reg allocator */
2781         switch (ins->opcode) {
2782         case OP_CALL:
2783         case OP_CALL_REG:
2784         case OP_CALL_MEMBASE:
2785         case OP_LCALL:
2786         case OP_LCALL_REG:
2787         case OP_LCALL_MEMBASE:
2788                 g_assert (ins->dreg == AMD64_RAX);
2789                 break;
2790         case OP_FCALL:
2791         case OP_FCALL_REG:
2792         case OP_FCALL_MEMBASE:
2793                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2794                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2795                 }
2796                 else {
2797                         if (ins->dreg != AMD64_XMM0)
2798                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2799                 }
2800                 break;
2801         case OP_VCALL:
2802         case OP_VCALL_REG:
2803         case OP_VCALL_MEMBASE:
2804         case OP_VCALL2:
2805         case OP_VCALL2_REG:
2806         case OP_VCALL2_MEMBASE:
2807                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2808                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2809                         MonoInst *loc = cfg->arch.vret_addr_loc;
2810
2811                         /* Load the destination address */
2812                         g_assert (loc->opcode == OP_REGOFFSET);
2813                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2814
2815                         for (quad = 0; quad < 2; quad ++) {
2816                                 switch (cinfo->ret.pair_storage [quad]) {
2817                                 case ArgInIReg:
2818                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2819                                         break;
2820                                 case ArgInFloatSSEReg:
2821                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2822                                         break;
2823                                 case ArgInDoubleSSEReg:
2824                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2825                                         break;
2826                                 case ArgNone:
2827                                         break;
2828                                 default:
2829                                         NOT_IMPLEMENTED;
2830                                 }
2831                         }
2832                 }
2833                 break;
2834         }
2835
2836         return code;
2837 }
2838
2839 /*
2840  * emit_tls_get:
2841  * @code: buffer to store code to
2842  * @dreg: hard register where to place the result
2843  * @tls_offset: offset info
2844  *
2845  * emit_tls_get emits in @code the native code that puts in the dreg register
2846  * the item in the thread local storage identified by tls_offset.
2847  *
2848  * Returns: a pointer to the end of the stored code
2849  */
2850 static guint8*
2851 emit_tls_get (guint8* code, int dreg, int tls_offset)
2852 {
2853 #ifdef PLATFORM_WIN32
2854         g_assert (tls_offset < 64);
2855         x86_prefix (code, X86_GS_PREFIX);
2856         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2857 #else
2858         if (optimize_for_xen) {
2859                 x86_prefix (code, X86_FS_PREFIX);
2860                 amd64_mov_reg_mem (code, dreg, 0, 8);
2861                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2862         } else {
2863                 x86_prefix (code, X86_FS_PREFIX);
2864                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2865         }
2866 #endif
2867         return code;
2868 }
2869
2870 /*
2871  * emit_load_volatile_arguments:
2872  *
2873  *  Load volatile arguments from the stack to the original input registers.
2874  * Required before a tail call.
2875  */
2876 static guint8*
2877 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2878 {
2879         MonoMethod *method = cfg->method;
2880         MonoMethodSignature *sig;
2881         MonoInst *ins;
2882         CallInfo *cinfo;
2883         guint32 i, quad;
2884
2885         /* FIXME: Generate intermediate code instead */
2886
2887         sig = mono_method_signature (method);
2888
2889         cinfo = cfg->arch.cinfo;
2890
2891         /* This is the opposite of the code in emit_prolog */
2892         if (sig->ret->type != MONO_TYPE_VOID) {
2893                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2894                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2895         }
2896
2897         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2898                 ArgInfo *ainfo = cinfo->args + i;
2899                 MonoType *arg_type;
2900                 ins = cfg->args [i];
2901
2902                 if (sig->hasthis && (i == 0))
2903                         arg_type = &mono_defaults.object_class->byval_arg;
2904                 else
2905                         arg_type = sig->params [i - sig->hasthis];
2906
2907                 if (ins->opcode != OP_REGVAR) {
2908                         switch (ainfo->storage) {
2909                         case ArgInIReg: {
2910                                 guint32 size = 8;
2911
2912                                 /* FIXME: I1 etc */
2913                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2914                                 break;
2915                         }
2916                         case ArgInFloatSSEReg:
2917                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2918                                 break;
2919                         case ArgInDoubleSSEReg:
2920                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2921                                 break;
2922                         case ArgValuetypeInReg:
2923                                 for (quad = 0; quad < 2; quad ++) {
2924                                         switch (ainfo->pair_storage [quad]) {
2925                                         case ArgInIReg:
2926                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2927                                                 break;
2928                                         case ArgInFloatSSEReg:
2929                                         case ArgInDoubleSSEReg:
2930                                                 g_assert_not_reached ();
2931                                                 break;
2932                                         case ArgNone:
2933                                                 break;
2934                                         default:
2935                                                 g_assert_not_reached ();
2936                                         }
2937                                 }
2938                                 break;
2939                         case ArgValuetypeAddrInIReg:
2940                                 if (ainfo->pair_storage [0] == ArgInIReg)
2941                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2942                                 break;
2943                         default:
2944                                 break;
2945                         }
2946                 }
2947                 else {
2948                         g_assert (ainfo->storage == ArgInIReg);
2949
2950                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2951                 }
2952         }
2953
2954         return code;
2955 }
2956
2957 #define REAL_PRINT_REG(text,reg) \
2958 mono_assert (reg >= 0); \
2959 amd64_push_reg (code, AMD64_RAX); \
2960 amd64_push_reg (code, AMD64_RDX); \
2961 amd64_push_reg (code, AMD64_RCX); \
2962 amd64_push_reg (code, reg); \
2963 amd64_push_imm (code, reg); \
2964 amd64_push_imm (code, text " %d %p\n"); \
2965 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2966 amd64_call_reg (code, AMD64_RAX); \
2967 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2968 amd64_pop_reg (code, AMD64_RCX); \
2969 amd64_pop_reg (code, AMD64_RDX); \
2970 amd64_pop_reg (code, AMD64_RAX);
2971
2972 /* benchmark and set based on cpu */
2973 #define LOOP_ALIGNMENT 8
2974 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2975
2976 #ifndef DISABLE_JIT
2977
2978 void
2979 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2980 {
2981         MonoInst *ins;
2982         MonoCallInst *call;
2983         guint offset;
2984         guint8 *code = cfg->native_code + cfg->code_len;
2985         MonoInst *last_ins = NULL;
2986         guint last_offset = 0;
2987         int max_len, cpos;
2988
2989         if (cfg->opt & MONO_OPT_LOOP) {
2990                 int pad, align = LOOP_ALIGNMENT;
2991                 /* set alignment depending on cpu */
2992                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2993                         pad = align - pad;
2994                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2995                         amd64_padding (code, pad);
2996                         cfg->code_len += pad;
2997                         bb->native_offset = cfg->code_len;
2998                 }
2999         }
3000
3001         if (cfg->verbose_level > 2)
3002                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3003
3004         cpos = bb->max_offset;
3005
3006         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3007                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3008                 g_assert (!cfg->compile_aot);
3009                 cpos += 6;
3010
3011                 cov->data [bb->dfn].cil_code = bb->cil_code;
3012                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3013                 /* this is not thread save, but good enough */
3014                 amd64_inc_membase (code, AMD64_R11, 0);
3015         }
3016
3017         offset = code - cfg->native_code;
3018
3019         mono_debug_open_block (cfg, bb, offset);
3020
3021         MONO_BB_FOR_EACH_INS (bb, ins) {
3022                 offset = code - cfg->native_code;
3023
3024                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3025
3026                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3027                         cfg->code_size *= 2;
3028                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3029                         code = cfg->native_code + offset;
3030                         mono_jit_stats.code_reallocs++;
3031                 }
3032
3033                 if (cfg->debug_info)
3034                         mono_debug_record_line_number (cfg, ins, offset);
3035
3036                 switch (ins->opcode) {
3037                 case OP_BIGMUL:
3038                         amd64_mul_reg (code, ins->sreg2, TRUE);
3039                         break;
3040                 case OP_BIGMUL_UN:
3041                         amd64_mul_reg (code, ins->sreg2, FALSE);
3042                         break;
3043                 case OP_X86_SETEQ_MEMBASE:
3044                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3045                         break;
3046                 case OP_STOREI1_MEMBASE_IMM:
3047                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3048                         break;
3049                 case OP_STOREI2_MEMBASE_IMM:
3050                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3051                         break;
3052                 case OP_STOREI4_MEMBASE_IMM:
3053                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3054                         break;
3055                 case OP_STOREI1_MEMBASE_REG:
3056                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3057                         break;
3058                 case OP_STOREI2_MEMBASE_REG:
3059                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3060                         break;
3061                 case OP_STORE_MEMBASE_REG:
3062                 case OP_STOREI8_MEMBASE_REG:
3063                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3064                         break;
3065                 case OP_STOREI4_MEMBASE_REG:
3066                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3067                         break;
3068                 case OP_STORE_MEMBASE_IMM:
3069                 case OP_STOREI8_MEMBASE_IMM:
3070                         g_assert (amd64_is_imm32 (ins->inst_imm));
3071                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3072                         break;
3073                 case OP_LOAD_MEM:
3074                 case OP_LOADI8_MEM:
3075                         // FIXME: Decompose this earlier
3076                         if (amd64_is_imm32 (ins->inst_imm))
3077                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3078                         else {
3079                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3080                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3081                         }
3082                         break;
3083                 case OP_LOADI4_MEM:
3084                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3085                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3086                         break;
3087                 case OP_LOADU4_MEM:
3088                         // FIXME: Decompose this earlier
3089                         if (cfg->new_ir) {
3090                                 if (amd64_is_imm32 (ins->inst_imm))
3091                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3092                                 else {
3093                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3094                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3095                                 }
3096                         } else {
3097                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3098                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3099                         }
3100                         break;
3101                 case OP_LOADU1_MEM:
3102                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3103                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3104                         break;
3105                 case OP_LOADU2_MEM:
3106                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3107                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3108                         break;
3109                 case OP_LOAD_MEMBASE:
3110                 case OP_LOADI8_MEMBASE:
3111                         g_assert (amd64_is_imm32 (ins->inst_offset));
3112                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3113                         break;
3114                 case OP_LOADI4_MEMBASE:
3115                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3116                         break;
3117                 case OP_LOADU4_MEMBASE:
3118                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3119                         break;
3120                 case OP_LOADU1_MEMBASE:
3121                         /* The cpu zero extends the result into 64 bits */
3122                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3123                         break;
3124                 case OP_LOADI1_MEMBASE:
3125                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3126                         break;
3127                 case OP_LOADU2_MEMBASE:
3128                         /* The cpu zero extends the result into 64 bits */
3129                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3130                         break;
3131                 case OP_LOADI2_MEMBASE:
3132                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3133                         break;
3134                 case OP_AMD64_LOADI8_MEMINDEX:
3135                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3136                         break;
3137                 case OP_LCONV_TO_I1:
3138                 case OP_ICONV_TO_I1:
3139                 case OP_SEXT_I1:
3140                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3141                         break;
3142                 case OP_LCONV_TO_I2:
3143                 case OP_ICONV_TO_I2:
3144                 case OP_SEXT_I2:
3145                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3146                         break;
3147                 case OP_LCONV_TO_U1:
3148                 case OP_ICONV_TO_U1:
3149                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3150                         break;
3151                 case OP_LCONV_TO_U2:
3152                 case OP_ICONV_TO_U2:
3153                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3154                         break;
3155                 case OP_ZEXT_I4:
3156                         /* Clean out the upper word */
3157                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3158                         break;
3159                 case OP_SEXT_I4:
3160                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3161                         break;
3162                 case OP_COMPARE:
3163                 case OP_LCOMPARE:
3164                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3165                         break;
3166                 case OP_COMPARE_IMM:
3167                 case OP_LCOMPARE_IMM:
3168                         g_assert (amd64_is_imm32 (ins->inst_imm));
3169                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3170                         break;
3171                 case OP_X86_COMPARE_REG_MEMBASE:
3172                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3173                         break;
3174                 case OP_X86_TEST_NULL:
3175                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3176                         break;
3177                 case OP_AMD64_TEST_NULL:
3178                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3179                         break;
3180
3181                 case OP_X86_ADD_REG_MEMBASE:
3182                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3183                         break;
3184                 case OP_X86_SUB_REG_MEMBASE:
3185                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3186                         break;
3187                 case OP_X86_AND_REG_MEMBASE:
3188                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3189                         break;
3190                 case OP_X86_OR_REG_MEMBASE:
3191                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3192                         break;
3193                 case OP_X86_XOR_REG_MEMBASE:
3194                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3195                         break;
3196
3197                 case OP_X86_ADD_MEMBASE_IMM:
3198                         /* FIXME: Make a 64 version too */
3199                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3200                         break;
3201                 case OP_X86_SUB_MEMBASE_IMM:
3202                         g_assert (amd64_is_imm32 (ins->inst_imm));
3203                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3204                         break;
3205                 case OP_X86_AND_MEMBASE_IMM:
3206                         g_assert (amd64_is_imm32 (ins->inst_imm));
3207                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3208                         break;
3209                 case OP_X86_OR_MEMBASE_IMM:
3210                         g_assert (amd64_is_imm32 (ins->inst_imm));
3211                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3212                         break;
3213                 case OP_X86_XOR_MEMBASE_IMM:
3214                         g_assert (amd64_is_imm32 (ins->inst_imm));
3215                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3216                         break;
3217                 case OP_X86_ADD_MEMBASE_REG:
3218                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3219                         break;
3220                 case OP_X86_SUB_MEMBASE_REG:
3221                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3222                         break;
3223                 case OP_X86_AND_MEMBASE_REG:
3224                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3225                         break;
3226                 case OP_X86_OR_MEMBASE_REG:
3227                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3228                         break;
3229                 case OP_X86_XOR_MEMBASE_REG:
3230                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3231                         break;
3232                 case OP_X86_INC_MEMBASE:
3233                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3234                         break;
3235                 case OP_X86_INC_REG:
3236                         amd64_inc_reg_size (code, ins->dreg, 4);
3237                         break;
3238                 case OP_X86_DEC_MEMBASE:
3239                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3240                         break;
3241                 case OP_X86_DEC_REG:
3242                         amd64_dec_reg_size (code, ins->dreg, 4);
3243                         break;
3244                 case OP_X86_MUL_REG_MEMBASE:
3245                 case OP_X86_MUL_MEMBASE_REG:
3246                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3247                         break;
3248                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3249                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3250                         break;
3251                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3252                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3253                         break;
3254                 case OP_AMD64_COMPARE_MEMBASE_REG:
3255                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3256                         break;
3257                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3258                         g_assert (amd64_is_imm32 (ins->inst_imm));
3259                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3260                         break;
3261                 case OP_X86_COMPARE_MEMBASE8_IMM:
3262                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3263                         break;
3264                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3265                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3266                         break;
3267                 case OP_AMD64_COMPARE_REG_MEMBASE:
3268                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3269                         break;
3270
3271                 case OP_AMD64_ADD_REG_MEMBASE:
3272                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3273                         break;
3274                 case OP_AMD64_SUB_REG_MEMBASE:
3275                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3276                         break;
3277                 case OP_AMD64_AND_REG_MEMBASE:
3278                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3279                         break;
3280                 case OP_AMD64_OR_REG_MEMBASE:
3281                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3282                         break;
3283                 case OP_AMD64_XOR_REG_MEMBASE:
3284                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3285                         break;
3286
3287                 case OP_AMD64_ADD_MEMBASE_REG:
3288                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3289                         break;
3290                 case OP_AMD64_SUB_MEMBASE_REG:
3291                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3292                         break;
3293                 case OP_AMD64_AND_MEMBASE_REG:
3294                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3295                         break;
3296                 case OP_AMD64_OR_MEMBASE_REG:
3297                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3298                         break;
3299                 case OP_AMD64_XOR_MEMBASE_REG:
3300                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3301                         break;
3302
3303                 case OP_AMD64_ADD_MEMBASE_IMM:
3304                         g_assert (amd64_is_imm32 (ins->inst_imm));
3305                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3306                         break;
3307                 case OP_AMD64_SUB_MEMBASE_IMM:
3308                         g_assert (amd64_is_imm32 (ins->inst_imm));
3309                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3310                         break;
3311                 case OP_AMD64_AND_MEMBASE_IMM:
3312                         g_assert (amd64_is_imm32 (ins->inst_imm));
3313                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3314                         break;
3315                 case OP_AMD64_OR_MEMBASE_IMM:
3316                         g_assert (amd64_is_imm32 (ins->inst_imm));
3317                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3318                         break;
3319                 case OP_AMD64_XOR_MEMBASE_IMM:
3320                         g_assert (amd64_is_imm32 (ins->inst_imm));
3321                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3322                         break;
3323
3324                 case OP_BREAK:
3325                         amd64_breakpoint (code);
3326                         break;
3327                 case OP_RELAXED_NOP:
3328                         x86_prefix (code, X86_REP_PREFIX);
3329                         x86_nop (code);
3330                         break;
3331                 case OP_NOP:
3332                 case OP_DUMMY_USE:
3333                 case OP_DUMMY_STORE:
3334                 case OP_NOT_REACHED:
3335                 case OP_NOT_NULL:
3336                         break;
3337                 case OP_ADDCC:
3338                 case OP_LADD:
3339                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3340                         break;
3341                 case OP_ADC:
3342                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3343                         break;
3344                 case OP_ADD_IMM:
3345                 case OP_LADD_IMM:
3346                         g_assert (amd64_is_imm32 (ins->inst_imm));
3347                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3348                         break;
3349                 case OP_ADC_IMM:
3350                         g_assert (amd64_is_imm32 (ins->inst_imm));
3351                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3352                         break;
3353                 case OP_SUBCC:
3354                 case OP_LSUB:
3355                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3356                         break;
3357                 case OP_SBB:
3358                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3359                         break;
3360                 case OP_SUB_IMM:
3361                 case OP_LSUB_IMM:
3362                         g_assert (amd64_is_imm32 (ins->inst_imm));
3363                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3364                         break;
3365                 case OP_SBB_IMM:
3366                         g_assert (amd64_is_imm32 (ins->inst_imm));
3367                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3368                         break;
3369                 case OP_LAND:
3370                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3371                         break;
3372                 case OP_AND_IMM:
3373                 case OP_LAND_IMM:
3374                         g_assert (amd64_is_imm32 (ins->inst_imm));
3375                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3376                         break;
3377                 case OP_LMUL:
3378                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3379                         break;
3380                 case OP_MUL_IMM:
3381                 case OP_LMUL_IMM:
3382                 case OP_IMUL_IMM: {
3383                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3384
3385                         switch (ins->inst_imm) {
3386                         case 2:
3387                                 /* MOV r1, r2 */
3388                                 /* ADD r1, r1 */
3389                                 if (ins->dreg != ins->sreg1)
3390                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3391                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3392                                 break;
3393                         case 3:
3394                                 /* LEA r1, [r2 + r2*2] */
3395                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3396                                 break;
3397                         case 5:
3398                                 /* LEA r1, [r2 + r2*4] */
3399                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3400                                 break;
3401                         case 6:
3402                                 /* LEA r1, [r2 + r2*2] */
3403                                 /* ADD r1, r1          */
3404                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3405                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3406                                 break;
3407                         case 9:
3408                                 /* LEA r1, [r2 + r2*8] */
3409                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3410                                 break;
3411                         case 10:
3412                                 /* LEA r1, [r2 + r2*4] */
3413                                 /* ADD r1, r1          */
3414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3415                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3416                                 break;
3417                         case 12:
3418                                 /* LEA r1, [r2 + r2*2] */
3419                                 /* SHL r1, 2           */
3420                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3421                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3422                                 break;
3423                         case 25:
3424                                 /* LEA r1, [r2 + r2*4] */
3425                                 /* LEA r1, [r1 + r1*4] */
3426                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3427                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3428                                 break;
3429                         case 100:
3430                                 /* LEA r1, [r2 + r2*4] */
3431                                 /* SHL r1, 2           */
3432                                 /* LEA r1, [r1 + r1*4] */
3433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3434                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3435                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3436                                 break;
3437                         default:
3438                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3439                                 break;
3440                         }
3441                         break;
3442                 }
3443                 case OP_LDIV:
3444                 case OP_LREM:
3445                         /* Regalloc magic makes the div/rem cases the same */
3446                         if (ins->sreg2 == AMD64_RDX) {
3447                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3448                                 amd64_cdq (code);
3449                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3450                         } else {
3451                                 amd64_cdq (code);
3452                                 amd64_div_reg (code, ins->sreg2, TRUE);
3453                         }
3454                         break;
3455                 case OP_LDIV_UN:
3456                 case OP_LREM_UN:
3457                         if (ins->sreg2 == AMD64_RDX) {
3458                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3459                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3460                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3461                         } else {
3462                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3463                                 amd64_div_reg (code, ins->sreg2, FALSE);
3464                         }
3465                         break;
3466                 case OP_IDIV:
3467                 case OP_IREM:
3468                         if (ins->sreg2 == AMD64_RDX) {
3469                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3470                                 amd64_cdq_size (code, 4);
3471                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3472                         } else {
3473                                 amd64_cdq_size (code, 4);
3474                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3475                         }
3476                         break;
3477                 case OP_IDIV_UN:
3478                 case OP_IREM_UN:
3479                         if (ins->sreg2 == AMD64_RDX) {
3480                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3481                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3482                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3483                         } else {
3484                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3485                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3486                         }
3487                         break;
3488                 case OP_LMUL_OVF:
3489                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3490                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3491                         break;
3492                 case OP_LOR:
3493                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3494                         break;
3495                 case OP_OR_IMM:
3496                 case OP_LOR_IMM:
3497                         g_assert (amd64_is_imm32 (ins->inst_imm));
3498                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3499                         break;
3500                 case OP_LXOR:
3501                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3502                         break;
3503                 case OP_XOR_IMM:
3504                 case OP_LXOR_IMM:
3505                         g_assert (amd64_is_imm32 (ins->inst_imm));
3506                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3507                         break;
3508                 case OP_LSHL:
3509                         g_assert (ins->sreg2 == AMD64_RCX);
3510                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3511                         break;
3512                 case OP_LSHR:
3513                         g_assert (ins->sreg2 == AMD64_RCX);
3514                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3515                         break;
3516                 case OP_SHR_IMM:
3517                         g_assert (amd64_is_imm32 (ins->inst_imm));
3518                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3519                         break;
3520                 case OP_LSHR_IMM:
3521                         g_assert (amd64_is_imm32 (ins->inst_imm));
3522                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3523                         break;
3524                 case OP_SHR_UN_IMM:
3525                         g_assert (amd64_is_imm32 (ins->inst_imm));
3526                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3527                         break;
3528                 case OP_LSHR_UN_IMM:
3529                         g_assert (amd64_is_imm32 (ins->inst_imm));
3530                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3531                         break;
3532                 case OP_LSHR_UN:
3533                         g_assert (ins->sreg2 == AMD64_RCX);
3534                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3535                         break;
3536                 case OP_SHL_IMM:
3537                         g_assert (amd64_is_imm32 (ins->inst_imm));
3538                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3539                         break;
3540                 case OP_LSHL_IMM:
3541                         g_assert (amd64_is_imm32 (ins->inst_imm));
3542                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3543                         break;
3544
3545                 case OP_IADDCC:
3546                 case OP_IADD:
3547                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3548                         break;
3549                 case OP_IADC:
3550                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3551                         break;
3552                 case OP_IADD_IMM:
3553                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3554                         break;
3555                 case OP_IADC_IMM:
3556                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3557                         break;
3558                 case OP_ISUBCC:
3559                 case OP_ISUB:
3560                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3561                         break;
3562                 case OP_ISBB:
3563                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3564                         break;
3565                 case OP_ISUB_IMM:
3566                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3567                         break;
3568                 case OP_ISBB_IMM:
3569                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3570                         break;
3571                 case OP_IAND:
3572                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3573                         break;
3574                 case OP_IAND_IMM:
3575                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3576                         break;
3577                 case OP_IOR:
3578                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3579                         break;
3580                 case OP_IOR_IMM:
3581                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3582                         break;
3583                 case OP_IXOR:
3584                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3585                         break;
3586                 case OP_IXOR_IMM:
3587                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3588                         break;
3589                 case OP_INEG:
3590                         amd64_neg_reg_size (code, ins->sreg1, 4);
3591                         break;
3592                 case OP_INOT:
3593                         amd64_not_reg_size (code, ins->sreg1, 4);
3594                         break;
3595                 case OP_ISHL:
3596                         g_assert (ins->sreg2 == AMD64_RCX);
3597                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3598                         break;
3599                 case OP_ISHR:
3600                         g_assert (ins->sreg2 == AMD64_RCX);
3601                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3602                         break;
3603                 case OP_ISHR_IMM:
3604                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3605                         break;
3606                 case OP_ISHR_UN_IMM:
3607                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3608                         break;
3609                 case OP_ISHR_UN:
3610                         g_assert (ins->sreg2 == AMD64_RCX);
3611                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3612                         break;
3613                 case OP_ISHL_IMM:
3614                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3615                         break;
3616                 case OP_IMUL:
3617                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3618                         break;
3619                 case OP_IMUL_OVF:
3620                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3621                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3622                         break;
3623                 case OP_IMUL_OVF_UN:
3624                 case OP_LMUL_OVF_UN: {
3625                         /* the mul operation and the exception check should most likely be split */
3626                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3627                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3628                         /*g_assert (ins->sreg2 == X86_EAX);
3629                         g_assert (ins->dreg == X86_EAX);*/
3630                         if (ins->sreg2 == X86_EAX) {
3631                                 non_eax_reg = ins->sreg1;
3632                         } else if (ins->sreg1 == X86_EAX) {
3633                                 non_eax_reg = ins->sreg2;
3634                         } else {
3635                                 /* no need to save since we're going to store to it anyway */
3636                                 if (ins->dreg != X86_EAX) {
3637                                         saved_eax = TRUE;
3638                                         amd64_push_reg (code, X86_EAX);
3639                                 }
3640                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3641                                 non_eax_reg = ins->sreg2;
3642                         }
3643                         if (ins->dreg == X86_EDX) {
3644                                 if (!saved_eax) {
3645                                         saved_eax = TRUE;
3646                                         amd64_push_reg (code, X86_EAX);
3647                                 }
3648                         } else {
3649                                 saved_edx = TRUE;
3650                                 amd64_push_reg (code, X86_EDX);
3651                         }
3652                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3653                         /* save before the check since pop and mov don't change the flags */
3654                         if (ins->dreg != X86_EAX)
3655                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3656                         if (saved_edx)
3657                                 amd64_pop_reg (code, X86_EDX);
3658                         if (saved_eax)
3659                                 amd64_pop_reg (code, X86_EAX);
3660                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3661                         break;
3662                 }
3663                 case OP_ICOMPARE:
3664                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3665                         break;
3666                 case OP_ICOMPARE_IMM:
3667                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3668                         break;
3669                 case OP_IBEQ:
3670                 case OP_IBLT:
3671                 case OP_IBGT:
3672                 case OP_IBGE:
3673                 case OP_IBLE:
3674                 case OP_LBEQ:
3675                 case OP_LBLT:
3676                 case OP_LBGT:
3677                 case OP_LBGE:
3678                 case OP_LBLE:
3679                 case OP_IBNE_UN:
3680                 case OP_IBLT_UN:
3681                 case OP_IBGT_UN:
3682                 case OP_IBGE_UN:
3683                 case OP_IBLE_UN:
3684                 case OP_LBNE_UN:
3685                 case OP_LBLT_UN:
3686                 case OP_LBGT_UN:
3687                 case OP_LBGE_UN:
3688                 case OP_LBLE_UN:
3689                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3690                         break;
3691
3692                 case OP_CMOV_IEQ:
3693                 case OP_CMOV_IGE:
3694                 case OP_CMOV_IGT:
3695                 case OP_CMOV_ILE:
3696                 case OP_CMOV_ILT:
3697                 case OP_CMOV_INE_UN:
3698                 case OP_CMOV_IGE_UN:
3699                 case OP_CMOV_IGT_UN:
3700                 case OP_CMOV_ILE_UN:
3701                 case OP_CMOV_ILT_UN:
3702                 case OP_CMOV_LEQ:
3703                 case OP_CMOV_LGE:
3704                 case OP_CMOV_LGT:
3705                 case OP_CMOV_LLE:
3706                 case OP_CMOV_LLT:
3707                 case OP_CMOV_LNE_UN:
3708                 case OP_CMOV_LGE_UN:
3709                 case OP_CMOV_LGT_UN:
3710                 case OP_CMOV_LLE_UN:
3711                 case OP_CMOV_LLT_UN:
3712                         g_assert (ins->dreg == ins->sreg1);
3713                         /* This needs to operate on 64 bit values */
3714                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3715                         break;
3716
3717                 case OP_LNOT:
3718                         amd64_not_reg (code, ins->sreg1);
3719                         break;
3720                 case OP_LNEG:
3721                         amd64_neg_reg (code, ins->sreg1);
3722                         break;
3723
3724                 case OP_ICONST:
3725                 case OP_I8CONST:
3726                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3727                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3728                         else
3729                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3730                         break;
3731                 case OP_AOTCONST:
3732                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3733                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3734                         break;
3735                 case OP_JUMP_TABLE:
3736                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3737                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3738                         break;
3739                 case OP_MOVE:
3740                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3741                         break;
3742                 case OP_AMD64_SET_XMMREG_R4: {
3743                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3744                         break;
3745                 }
3746                 case OP_AMD64_SET_XMMREG_R8: {
3747                         if (ins->dreg != ins->sreg1)
3748                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3749                         break;
3750                 }
3751                 case OP_JMP:
3752                 case OP_TAILCALL: {
3753                         /*
3754                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3755                          * Keep in sync with the code in emit_epilog.
3756                          */
3757                         int pos = 0, i;
3758
3759                         /* FIXME: no tracing support... */
3760                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3761                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3762
3763                         g_assert (!cfg->method->save_lmf);
3764
3765                         if (ins->opcode == OP_JMP)
3766                                 code = emit_load_volatile_arguments (cfg, code);
3767
3768                         if (cfg->arch.omit_fp) {
3769                                 guint32 save_offset = 0;
3770                                 /* Pop callee-saved registers */
3771                                 for (i = 0; i < AMD64_NREG; ++i)
3772                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3773                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3774                                                 save_offset += 8;
3775                                         }
3776                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3777                         }
3778                         else {
3779                                 for (i = 0; i < AMD64_NREG; ++i)
3780                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3781                                                 pos -= sizeof (gpointer);
3782
3783                                 if (pos)
3784                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3785
3786                                 /* Pop registers in reverse order */
3787                                 for (i = AMD64_NREG - 1; i > 0; --i)
3788                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3789                                                 amd64_pop_reg (code, i);
3790                                         }
3791
3792                                 amd64_leave (code);
3793                         }
3794
3795                         offset = code - cfg->native_code;
3796                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3797                         if (cfg->compile_aot)
3798                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3799                         else
3800                                 amd64_set_reg_template (code, AMD64_R11);
3801                         amd64_jump_reg (code, AMD64_R11);
3802                         break;
3803                 }
3804                 case OP_CHECK_THIS:
3805                         /* ensure ins->sreg1 is not NULL */
3806                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3807                         break;
3808                 case OP_ARGLIST: {
3809                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3810                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3811                         break;
3812                 }
3813                 case OP_CALL:
3814                 case OP_FCALL:
3815                 case OP_LCALL:
3816                 case OP_VCALL:
3817                 case OP_VCALL2:
3818                 case OP_VOIDCALL:
3819                         call = (MonoCallInst*)ins;
3820                         /*
3821                          * The AMD64 ABI forces callers to know about varargs.
3822                          */
3823                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3824                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3825                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3826                                 /*
3827                                  * Since the unmanaged calling convention doesn't contain a
3828                                  * 'vararg' entry, we have to treat every pinvoke call as a
3829                                  * potential vararg call.
3830                                  */
3831                                 guint32 nregs, i;
3832                                 nregs = 0;
3833                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3834                                         if (call->used_fregs & (1 << i))
3835                                                 nregs ++;
3836                                 if (!nregs)
3837                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3838                                 else
3839                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3840                         }
3841
3842                         if (ins->flags & MONO_INST_HAS_METHOD)
3843                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3844                         else
3845                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3846                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3847                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3848                         code = emit_move_return_value (cfg, ins, code);
3849                         break;
3850                 case OP_FCALL_REG:
3851                 case OP_LCALL_REG:
3852                 case OP_VCALL_REG:
3853                 case OP_VCALL2_REG:
3854                 case OP_VOIDCALL_REG:
3855                 case OP_CALL_REG:
3856                         call = (MonoCallInst*)ins;
3857
3858                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3859                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3860                                 ins->sreg1 = AMD64_R11;
3861                         }
3862
3863                         /*
3864                          * The AMD64 ABI forces callers to know about varargs.
3865                          */
3866                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3867                                 if (ins->sreg1 == AMD64_RAX) {
3868                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3869                                         ins->sreg1 = AMD64_R11;
3870                                 }
3871                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3872                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3873                                 /*
3874                                  * Since the unmanaged calling convention doesn't contain a
3875                                  * 'vararg' entry, we have to treat every pinvoke call as a
3876                                  * potential vararg call.
3877                                  */
3878                                 guint32 nregs, i;
3879                                 nregs = 0;
3880                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3881                                         if (call->used_fregs & (1 << i))
3882                                                 nregs ++;
3883                                 if (ins->sreg1 == AMD64_RAX) {
3884                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3885                                         ins->sreg1 = AMD64_R11;
3886                                 }
3887                                 if (!nregs)
3888                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3889                                 else
3890                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3891                         }
3892
3893                         amd64_call_reg (code, ins->sreg1);
3894                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3895                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3896                         code = emit_move_return_value (cfg, ins, code);
3897                         break;
3898                 case OP_FCALL_MEMBASE:
3899                 case OP_LCALL_MEMBASE:
3900                 case OP_VCALL_MEMBASE:
3901                 case OP_VCALL2_MEMBASE:
3902                 case OP_VOIDCALL_MEMBASE:
3903                 case OP_CALL_MEMBASE:
3904                         call = (MonoCallInst*)ins;
3905
3906                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3907                                 /*
3908                                  * Can't use R11 because it is clobbered by the trampoline
3909                                  * code, and the reg value is needed by get_vcall_slot_addr.
3910                                  */
3911                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3912                                 ins->sreg1 = AMD64_RAX;
3913                         }
3914
3915                         if (call->method && ins->inst_offset < 0) {
3916                                 gssize val;
3917
3918                                 /*
3919                                  * This is a possible IMT call so save the IMT method in the proper
3920                                  * register. We don't use the generic code in method-to-ir.c, because
3921                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3922                                  * maintain control over the layout of the code.
3923                                  * Also put the base reg in %rax to simplify find_imt_method ().
3924                                  */
3925                                 if (ins->sreg1 != AMD64_RAX) {
3926                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3927                                         ins->sreg1 = AMD64_RAX;
3928                                 }
3929                                 val = (gssize)(gpointer)call->method;
3930
3931                                 // FIXME: Generics sharing
3932 #if 0
3933                                 if ((((guint64)val) >> 32) == 0)
3934                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3935                                 else
3936                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3937 #endif
3938                         }
3939
3940                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3941                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3942                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3943                         code = emit_move_return_value (cfg, ins, code);
3944                         break;
3945                 case OP_AMD64_SAVE_SP_TO_LMF:
3946                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3947                         break;
3948                 case OP_OUTARG:
3949                 case OP_X86_PUSH:
3950                         amd64_push_reg (code, ins->sreg1);
3951                         break;
3952                 case OP_X86_PUSH_IMM:
3953                         g_assert (amd64_is_imm32 (ins->inst_imm));
3954                         amd64_push_imm (code, ins->inst_imm);
3955                         break;
3956                 case OP_X86_PUSH_MEMBASE:
3957                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3958                         break;
3959                 case OP_X86_PUSH_OBJ: {
3960                         int size = ALIGN_TO (ins->inst_imm, 8);
3961                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3962                         amd64_push_reg (code, AMD64_RDI);
3963                         amd64_push_reg (code, AMD64_RSI);
3964                         amd64_push_reg (code, AMD64_RCX);
3965                         if (ins->inst_offset)
3966                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3967                         else
3968                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3969                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8) + (size - ins->inst_imm));
3970                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3971                         amd64_cld (code);
3972                         amd64_prefix (code, X86_REP_PREFIX);
3973                         amd64_movsd (code);
3974                         amd64_pop_reg (code, AMD64_RCX);
3975                         amd64_pop_reg (code, AMD64_RSI);
3976                         amd64_pop_reg (code, AMD64_RDI);
3977                         break;
3978                 }
3979                 case OP_X86_LEA:
3980                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3981                         break;
3982                 case OP_X86_LEA_MEMBASE:
3983                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3984                         break;
3985                 case OP_X86_XCHG:
3986                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3987                         break;
3988                 case OP_LOCALLOC:
3989                         /* keep alignment */
3990                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3991                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3992                         code = mono_emit_stack_alloc (code, ins);
3993                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3994                         break;
3995                 case OP_LOCALLOC_IMM: {
3996                         guint32 size = ins->inst_imm;
3997                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3998
3999                         if (ins->flags & MONO_INST_INIT) {
4000                                 if (size < 64) {
4001                                         int i;
4002
4003                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4004                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4005
4006                                         for (i = 0; i < size; i += 8)
4007                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4008                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4009                                 } else {
4010                                         amd64_mov_reg_imm (code, ins->dreg, size);
4011                                         ins->sreg1 = ins->dreg;
4012
4013                                         code = mono_emit_stack_alloc (code, ins);
4014                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4015                                 }
4016                         } else {
4017                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4018                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4019                         }
4020                         break;
4021                 }
4022                 case OP_THROW: {
4023                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4024                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4025                                              (gpointer)"mono_arch_throw_exception", FALSE);
4026                         break;
4027                 }
4028                 case OP_RETHROW: {
4029                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4030                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4031                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4032                         break;
4033                 }
4034                 case OP_CALL_HANDLER:
4035                         /* Align stack */
4036                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4037                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4038                         amd64_call_imm (code, 0);
4039                         /* Restore stack alignment */
4040                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4041                         break;
4042                 case OP_START_HANDLER: {
4043                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4044                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4045                         break;
4046                 }
4047                 case OP_ENDFINALLY: {
4048                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4049                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4050                         amd64_ret (code);
4051                         break;
4052                 }
4053                 case OP_ENDFILTER: {
4054                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4055                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4056                         /* The local allocator will put the result into RAX */
4057                         amd64_ret (code);
4058                         break;
4059                 }
4060
4061                 case OP_LABEL:
4062                         ins->inst_c0 = code - cfg->native_code;
4063                         break;
4064                 case OP_BR:
4065                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4066                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4067                         //break;
4068                         if (ins->flags & MONO_INST_BRLABEL) {
4069                                 if (ins->inst_i0->inst_c0) {
4070                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4071                                 } else {
4072                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4073                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4074                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4075                                                 x86_jump8 (code, 0);
4076                                         else
4077                                                 x86_jump32 (code, 0);
4078                                 }
4079                         } else {
4080                                 if (ins->inst_target_bb->native_offset) {
4081                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4082                                 } else {
4083                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4084                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4085                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4086                                                 x86_jump8 (code, 0);
4087                                         else
4088                                                 x86_jump32 (code, 0);
4089                                 }
4090                         }
4091                         break;
4092                 case OP_BR_REG:
4093                         amd64_jump_reg (code, ins->sreg1);
4094                         break;
4095                 case OP_CEQ:
4096                 case OP_LCEQ:
4097                 case OP_ICEQ:
4098                 case OP_CLT:
4099                 case OP_LCLT:
4100                 case OP_ICLT:
4101                 case OP_CGT:
4102                 case OP_ICGT:
4103                 case OP_LCGT:
4104                 case OP_CLT_UN:
4105                 case OP_LCLT_UN:
4106                 case OP_ICLT_UN:
4107                 case OP_CGT_UN:
4108                 case OP_LCGT_UN:
4109                 case OP_ICGT_UN:
4110                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4111                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4112                         break;
4113                 case OP_COND_EXC_EQ:
4114                 case OP_COND_EXC_NE_UN:
4115                 case OP_COND_EXC_LT:
4116                 case OP_COND_EXC_LT_UN:
4117                 case OP_COND_EXC_GT:
4118                 case OP_COND_EXC_GT_UN:
4119                 case OP_COND_EXC_GE:
4120                 case OP_COND_EXC_GE_UN:
4121                 case OP_COND_EXC_LE:
4122                 case OP_COND_EXC_LE_UN:
4123                 case OP_COND_EXC_IEQ:
4124                 case OP_COND_EXC_INE_UN:
4125                 case OP_COND_EXC_ILT:
4126                 case OP_COND_EXC_ILT_UN:
4127                 case OP_COND_EXC_IGT:
4128                 case OP_COND_EXC_IGT_UN:
4129                 case OP_COND_EXC_IGE:
4130                 case OP_COND_EXC_IGE_UN:
4131                 case OP_COND_EXC_ILE:
4132                 case OP_COND_EXC_ILE_UN:
4133                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4134                         break;
4135                 case OP_COND_EXC_OV:
4136                 case OP_COND_EXC_NO:
4137                 case OP_COND_EXC_C:
4138                 case OP_COND_EXC_NC:
4139                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4140                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4141                         break;
4142                 case OP_COND_EXC_IOV:
4143                 case OP_COND_EXC_INO:
4144                 case OP_COND_EXC_IC:
4145                 case OP_COND_EXC_INC:
4146                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4147                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4148                         break;
4149
4150                 /* floating point opcodes */
4151                 case OP_R8CONST: {
4152                         double d = *(double *)ins->inst_p0;
4153
4154                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4155                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4156                         }
4157                         else {
4158                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4159                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4160                         }
4161                         break;
4162                 }
4163                 case OP_R4CONST: {
4164                         float f = *(float *)ins->inst_p0;
4165
4166                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4167                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4168                         }
4169                         else {
4170                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4171                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4172                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4173                         }
4174                         break;
4175                 }
4176                 case OP_STORER8_MEMBASE_REG:
4177                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4178                         break;
4179                 case OP_LOADR8_SPILL_MEMBASE:
4180                         g_assert_not_reached ();
4181                         break;
4182                 case OP_LOADR8_MEMBASE:
4183                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4184                         break;
4185                 case OP_STORER4_MEMBASE_REG:
4186                         /* This requires a double->single conversion */
4187                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4188                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4189                         break;
4190                 case OP_LOADR4_MEMBASE:
4191                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4192                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4193                         break;
4194                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4195                 case OP_ICONV_TO_R8:
4196                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4197                         break;
4198                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4199                 case OP_LCONV_TO_R8:
4200                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4201                         break;
4202                 case OP_FCONV_TO_R4:
4203                         /* FIXME: nothing to do ?? */
4204                         break;
4205                 case OP_FCONV_TO_I1:
4206                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4207                         break;
4208                 case OP_FCONV_TO_U1:
4209                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4210                         break;
4211                 case OP_FCONV_TO_I2:
4212                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4213                         break;
4214                 case OP_FCONV_TO_U2:
4215                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4216                         break;
4217                 case OP_FCONV_TO_U4:
4218                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4219                         break;
4220                 case OP_FCONV_TO_I4:
4221                 case OP_FCONV_TO_I:
4222                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4223                         break;
4224                 case OP_FCONV_TO_I8:
4225                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4226                         break;
4227                 case OP_LCONV_TO_R_UN: {
4228                         guint8 *br [2];
4229
4230                         /* Based on gcc code */
4231                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4232                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4233
4234                         /* Positive case */
4235                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4236                         br [1] = code; x86_jump8 (code, 0);
4237                         amd64_patch (br [0], code);
4238
4239                         /* Negative case */
4240                         /* Save to the red zone */
4241                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4242                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4243                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4244                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4245                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4246                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4247                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4248                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4249                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4250                         /* Restore */
4251                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4252                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4253                         amd64_patch (br [1], code);
4254                         break;
4255                 }
4256                 case OP_LCONV_TO_OVF_U4:
4257                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4258                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4259                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4260                         break;
4261                 case OP_LCONV_TO_OVF_I4_UN:
4262                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4263                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4264                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4265                         break;
4266                 case OP_FMOVE:
4267                         if (ins->dreg != ins->sreg1)
4268                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4269                         break;
4270                 case OP_FADD:
4271                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4272                         break;
4273                 case OP_FSUB:
4274                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4275                         break;
4276                 case OP_FMUL:
4277                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4278                         break;
4279                 case OP_FDIV:
4280                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4281                         break;
4282                 case OP_FNEG: {
4283                         static double r8_0 = -0.0;
4284
4285                         g_assert (ins->sreg1 == ins->dreg);
4286
4287                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4288                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4289                         break;
4290                 }
4291                 case OP_SIN:
4292                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4293                         break;
4294                 case OP_COS:
4295                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4296                         break;
4297                 case OP_ABS: {
4298                         static guint64 d = 0x7fffffffffffffffUL;
4299
4300                         g_assert (ins->sreg1 == ins->dreg);
4301
4302                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4303                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4304                         break;
4305                 }
4306                 case OP_SQRT:
4307                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4308                         break;
4309                 case OP_IMIN:
4310                         g_assert (cfg->opt & MONO_OPT_CMOV);
4311                         g_assert (ins->dreg == ins->sreg1);
4312                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4313                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4314                         break;
4315                 case OP_IMIN_UN:
4316                         g_assert (cfg->opt & MONO_OPT_CMOV);
4317                         g_assert (ins->dreg == ins->sreg1);
4318                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4319                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4320                         break;
4321                 case OP_IMAX:
4322                         g_assert (cfg->opt & MONO_OPT_CMOV);
4323                         g_assert (ins->dreg == ins->sreg1);
4324                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4325                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4326                         break;
4327                 case OP_IMAX_UN:
4328                         g_assert (cfg->opt & MONO_OPT_CMOV);
4329                         g_assert (ins->dreg == ins->sreg1);
4330                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4331                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4332                         break;
4333                 case OP_LMIN:
4334                         g_assert (cfg->opt & MONO_OPT_CMOV);
4335                         g_assert (ins->dreg == ins->sreg1);
4336                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4337                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4338                         break;
4339                 case OP_LMIN_UN:
4340                         g_assert (cfg->opt & MONO_OPT_CMOV);
4341                         g_assert (ins->dreg == ins->sreg1);
4342                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4343                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4344                         break;
4345                 case OP_LMAX:
4346                         g_assert (cfg->opt & MONO_OPT_CMOV);
4347                         g_assert (ins->dreg == ins->sreg1);
4348                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4349                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4350                         break;
4351                 case OP_LMAX_UN:
4352                         g_assert (cfg->opt & MONO_OPT_CMOV);
4353                         g_assert (ins->dreg == ins->sreg1);
4354                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4355                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4356                         break;
4357                 case OP_X86_FPOP:
4358                         break;
4359                 case OP_FCOMPARE:
4360                         /*
4361                          * The two arguments are swapped because the fbranch instructions
4362                          * depend on this for the non-sse case to work.
4363                          */
4364                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4365                         break;
4366                 case OP_FCEQ: {
4367                         /* zeroing the register at the start results in
4368                          * shorter and faster code (we can also remove the widening op)
4369                          */
4370                         guchar *unordered_check;
4371                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4372                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4373                         unordered_check = code;
4374                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4375                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4376                         amd64_patch (unordered_check, code);
4377                         break;
4378                 }
4379                 case OP_FCLT:
4380                 case OP_FCLT_UN:
4381                         /* zeroing the register at the start results in
4382                          * shorter and faster code (we can also remove the widening op)
4383                          */
4384                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4385                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4386                         if (ins->opcode == OP_FCLT_UN) {
4387                                 guchar *unordered_check = code;
4388                                 guchar *jump_to_end;
4389                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4390                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4391                                 jump_to_end = code;
4392                                 x86_jump8 (code, 0);
4393                                 amd64_patch (unordered_check, code);
4394                                 amd64_inc_reg (code, ins->dreg);
4395                                 amd64_patch (jump_to_end, code);
4396                         } else {
4397                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4398                         }
4399                         break;
4400                 case OP_FCGT:
4401                 case OP_FCGT_UN: {
4402                         /* zeroing the register at the start results in
4403                          * shorter and faster code (we can also remove the widening op)
4404                          */
4405                         guchar *unordered_check;
4406                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4407                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4408                         if (ins->opcode == OP_FCGT) {
4409                                 unordered_check = code;
4410                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4411                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4412                                 amd64_patch (unordered_check, code);
4413                         } else {
4414                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4415                         }
4416                         break;
4417                 }
4418                 case OP_FCLT_MEMBASE:
4419                 case OP_FCGT_MEMBASE:
4420                 case OP_FCLT_UN_MEMBASE:
4421                 case OP_FCGT_UN_MEMBASE:
4422                 case OP_FCEQ_MEMBASE: {
4423                         guchar *unordered_check, *jump_to_end;
4424                         int x86_cond;
4425
4426                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4427                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4428
4429                         switch (ins->opcode) {
4430                         case OP_FCEQ_MEMBASE:
4431                                 x86_cond = X86_CC_EQ;
4432                                 break;
4433                         case OP_FCLT_MEMBASE:
4434                         case OP_FCLT_UN_MEMBASE:
4435                                 x86_cond = X86_CC_LT;
4436                                 break;
4437                         case OP_FCGT_MEMBASE:
4438                         case OP_FCGT_UN_MEMBASE:
4439                                 x86_cond = X86_CC_GT;
4440                                 break;
4441                         default:
4442                                 g_assert_not_reached ();
4443                         }
4444
4445                         unordered_check = code;
4446                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4447                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4448
4449                         switch (ins->opcode) {
4450                         case OP_FCEQ_MEMBASE:
4451                         case OP_FCLT_MEMBASE:
4452                         case OP_FCGT_MEMBASE:
4453                                 amd64_patch (unordered_check, code);
4454                                 break;
4455                         case OP_FCLT_UN_MEMBASE:
4456                         case OP_FCGT_UN_MEMBASE:
4457                                 jump_to_end = code;
4458                                 x86_jump8 (code, 0);
4459                                 amd64_patch (unordered_check, code);
4460                                 amd64_inc_reg (code, ins->dreg);
4461                                 amd64_patch (jump_to_end, code);
4462                                 break;
4463                         default:
4464                                 break;
4465                         }
4466                         break;
4467                 }
4468                 case OP_FBEQ: {
4469                         guchar *jump = code;
4470                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4471                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4472                         amd64_patch (jump, code);
4473                         break;
4474                 }
4475                 case OP_FBNE_UN:
4476                         /* Branch if C013 != 100 */
4477                         /* branch if !ZF or (PF|CF) */
4478                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4479                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4480                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4481                         break;
4482                 case OP_FBLT:
4483                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4484                         break;
4485                 case OP_FBLT_UN:
4486                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4487                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4488                         break;
4489                 case OP_FBGT:
4490                 case OP_FBGT_UN:
4491                         if (ins->opcode == OP_FBGT) {
4492                                 guchar *br1;
4493
4494                                 /* skip branch if C1=1 */
4495                                 br1 = code;
4496                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4497                                 /* branch if (C0 | C3) = 1 */
4498                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4499                                 amd64_patch (br1, code);
4500                                 break;
4501                         } else {
4502                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4503                         }
4504                         break;
4505                 case OP_FBGE: {
4506                         /* Branch if C013 == 100 or 001 */
4507                         guchar *br1;
4508
4509                         /* skip branch if C1=1 */
4510                         br1 = code;
4511                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4512                         /* branch if (C0 | C3) = 1 */
4513                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4514                         amd64_patch (br1, code);
4515                         break;
4516                 }
4517                 case OP_FBGE_UN:
4518                         /* Branch if C013 == 000 */
4519                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4520                         break;
4521                 case OP_FBLE: {
4522                         /* Branch if C013=000 or 100 */
4523                         guchar *br1;
4524
4525                         /* skip branch if C1=1 */
4526                         br1 = code;
4527                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4528                         /* branch if C0=0 */
4529                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4530                         amd64_patch (br1, code);
4531                         break;
4532                 }
4533                 case OP_FBLE_UN:
4534                         /* Branch if C013 != 001 */
4535                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4536                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4537                         break;
4538                 case OP_CKFINITE:
4539                         /* Transfer value to the fp stack */
4540                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4541                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4542                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4543
4544                         amd64_push_reg (code, AMD64_RAX);
4545                         amd64_fxam (code);
4546                         amd64_fnstsw (code);
4547                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4548                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4549                         amd64_pop_reg (code, AMD64_RAX);
4550                         amd64_fstp (code, 0);
4551                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4552                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4553                         break;
4554                 case OP_TLS_GET: {
4555                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4556                         break;
4557                 }
4558                 case OP_MEMORY_BARRIER: {
4559                         /* Not needed on amd64 */
4560                         break;
4561                 }
4562                 case OP_ATOMIC_ADD_I4:
4563                 case OP_ATOMIC_ADD_I8: {
4564                         int dreg = ins->dreg;
4565                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4566
4567                         if (dreg == ins->inst_basereg)
4568                                 dreg = AMD64_R11;
4569
4570                         if (dreg != ins->sreg2)
4571                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4572
4573                         x86_prefix (code, X86_LOCK_PREFIX);
4574                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4575
4576                         if (dreg != ins->dreg)
4577                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4578
4579                         break;
4580                 }
4581                 case OP_ATOMIC_ADD_NEW_I4:
4582                 case OP_ATOMIC_ADD_NEW_I8: {
4583                         int dreg = ins->dreg;
4584                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4585
4586                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4587                                 dreg = AMD64_R11;
4588
4589                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4590                         amd64_prefix (code, X86_LOCK_PREFIX);
4591                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4592                         /* dreg contains the old value, add with sreg2 value */
4593                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4594
4595                         if (ins->dreg != dreg)
4596                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4597
4598                         break;
4599                 }
4600                 case OP_ATOMIC_EXCHANGE_I4:
4601                 case OP_ATOMIC_EXCHANGE_I8:
4602                 case OP_ATOMIC_CAS_IMM_I4: {
4603                         guchar *br[2];
4604                         int sreg2 = ins->sreg2;
4605                         int breg = ins->inst_basereg;
4606                         guint32 size;
4607                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4608
4609                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4610                                 size = 8;
4611                         else
4612                                 size = 4;
4613
4614                         /*
4615                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4616                          * an explanation of how this works.
4617                          */
4618
4619                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4620                          * hack to overcome limits in x86 reg allocator
4621                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4622                          */
4623                         g_assert (ins->dreg == AMD64_RAX);
4624
4625                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4626                                 /* Highly unlikely, but possible */
4627                                 need_push = TRUE;
4628
4629                         /* The pushes invalidate rsp */
4630                         if ((breg == AMD64_RAX) || need_push) {
4631                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4632                                 breg = AMD64_R11;
4633                         }
4634
4635                         /* We need the EAX reg for the comparand */
4636                         if (ins->sreg2 == AMD64_RAX) {
4637                                 if (breg != AMD64_R11) {
4638                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4639                                         sreg2 = AMD64_R11;
4640                                 } else {
4641                                         g_assert (need_push);
4642                                         amd64_push_reg (code, AMD64_RDX);
4643                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4644                                         sreg2 = AMD64_RDX;
4645                                         rdx_pushed = TRUE;
4646                                 }
4647                         }
4648
4649                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4650                                 if (ins->backend.data == NULL)
4651                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4652                                 else
4653                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4654
4655                                 amd64_prefix (code, X86_LOCK_PREFIX);
4656                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4657                         } else {
4658                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4659
4660                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4661                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4662                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4663                                 amd64_patch (br [1], br [0]);
4664                         }
4665
4666                         if (rdx_pushed)
4667                                 amd64_pop_reg (code, AMD64_RDX);
4668
4669                         break;
4670                 }
4671                 default:
4672                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4673                         g_assert_not_reached ();
4674                 }
4675
4676                 if ((code - cfg->native_code - offset) > max_len) {
4677                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4678                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4679                         g_assert_not_reached ();
4680                 }
4681
4682                 cpos += max_len;
4683
4684                 last_ins = ins;
4685                 last_offset = offset;
4686         }
4687
4688         cfg->code_len = code - cfg->native_code;
4689 }
4690
4691 #endif /* DISABLE_JIT */
4692
4693 void
4694 mono_arch_register_lowlevel_calls (void)
4695 {
4696         /* The signature doesn't matter */
4697         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4698 }
4699
4700 void
4701 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4702 {
4703         MonoJumpInfo *patch_info;
4704         gboolean compile_aot = !run_cctors;
4705
4706         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4707                 unsigned char *ip = patch_info->ip.i + code;
4708                 unsigned char *target;
4709
4710                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4711
4712                 if (compile_aot) {
4713                         switch (patch_info->type) {
4714                         case MONO_PATCH_INFO_BB:
4715                         case MONO_PATCH_INFO_LABEL:
4716                                 break;
4717                         default:
4718                                 /* No need to patch these */
4719                                 continue;
4720                         }
4721                 }
4722
4723                 switch (patch_info->type) {
4724                 case MONO_PATCH_INFO_NONE:
4725                         continue;
4726                 case MONO_PATCH_INFO_METHOD_REL:
4727                 case MONO_PATCH_INFO_R8:
4728                 case MONO_PATCH_INFO_R4:
4729                         g_assert_not_reached ();
4730                         continue;
4731                 case MONO_PATCH_INFO_BB:
4732                         break;
4733                 default:
4734                         break;
4735                 }
4736
4737                 /*
4738                  * Debug code to help track down problems where the target of a near call is
4739                  * is not valid.
4740                  */
4741                 if (amd64_is_near_call (ip)) {
4742                         gint64 disp = (guint8*)target - (guint8*)ip;
4743
4744                         if (!amd64_is_imm32 (disp)) {
4745                                 printf ("TYPE: %d\n", patch_info->type);
4746                                 switch (patch_info->type) {
4747                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4748                                         printf ("V: %s\n", patch_info->data.name);
4749                                         break;
4750                                 case MONO_PATCH_INFO_METHOD_JUMP:
4751                                 case MONO_PATCH_INFO_METHOD:
4752                                         printf ("V: %s\n", patch_info->data.method->name);
4753                                         break;
4754                                 default:
4755                                         break;
4756                                 }
4757                         }
4758                 }
4759
4760                 amd64_patch (ip, (gpointer)target);
4761         }
4762 }
4763
4764 static int
4765 get_max_epilog_size (MonoCompile *cfg)
4766 {
4767         int max_epilog_size = 16;
4768
4769         if (cfg->method->save_lmf)
4770                 max_epilog_size += 256;
4771
4772         if (mono_jit_trace_calls != NULL)
4773                 max_epilog_size += 50;
4774
4775         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4776                 max_epilog_size += 50;
4777
4778         max_epilog_size += (AMD64_NREG * 2);
4779
4780         return max_epilog_size;
4781 }
4782
4783 /*
4784  * This macro is used for testing whenever the unwinder works correctly at every point
4785  * where an async exception can happen.
4786  */
4787 /* This will generate a SIGSEGV at the given point in the code */
4788 #define async_exc_point(code) do { \
4789     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4790          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4791              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4792          cfg->arch.async_point_count ++; \
4793     } \
4794 } while (0)
4795
4796 guint8 *
4797 mono_arch_emit_prolog (MonoCompile *cfg)
4798 {
4799         MonoMethod *method = cfg->method;
4800         MonoBasicBlock *bb;
4801         MonoMethodSignature *sig;
4802         MonoInst *ins;
4803         int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4804         guint8 *code;
4805         CallInfo *cinfo;
4806         gint32 lmf_offset = cfg->arch.lmf_offset;
4807         gboolean args_clobbered = FALSE;
4808         gboolean trace = FALSE;
4809
4810         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4811
4812         code = cfg->native_code = g_malloc (cfg->code_size);
4813
4814         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4815                 trace = TRUE;
4816
4817         /* Amount of stack space allocated by register saving code */
4818         pos = 0;
4819
4820         /*
4821          * The prolog consists of the following parts:
4822          * FP present:
4823          * - push rbp, mov rbp, rsp
4824          * - save callee saved regs using pushes
4825          * - allocate frame
4826          * - save rgctx if needed
4827          * - save lmf if needed
4828          * FP not present:
4829          * - allocate frame
4830          * - save rgctx if needed
4831          * - save lmf if needed
4832          * - save callee saved regs using moves
4833          */
4834
4835         async_exc_point (code);
4836
4837         if (!cfg->arch.omit_fp) {
4838                 amd64_push_reg (code, AMD64_RBP);
4839                 async_exc_point (code);
4840 #ifdef PLATFORM_WIN32
4841                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4842 #endif
4843
4844                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4845                 async_exc_point (code);
4846 #ifdef PLATFORM_WIN32
4847                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4848 #endif
4849         }
4850
4851         /* Save callee saved registers */
4852         if (!cfg->arch.omit_fp && !method->save_lmf) {
4853                 for (i = 0; i < AMD64_NREG; ++i)
4854                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4855                                 amd64_push_reg (code, i);
4856                                 pos += sizeof (gpointer);
4857                                 async_exc_point (code);
4858                         }
4859         }
4860
4861         if (cfg->arch.omit_fp) {
4862                 /*
4863                  * On enter, the stack is misaligned by the the pushing of the return
4864                  * address. It is either made aligned by the pushing of %rbp, or by
4865                  * this.
4866                  */
4867                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4868                 if ((alloc_size % 16) == 0)
4869                         alloc_size += 8;
4870         } else {
4871                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4872
4873                 alloc_size -= pos;
4874         }
4875
4876         cfg->arch.stack_alloc_size = alloc_size;
4877
4878         /* Allocate stack frame */
4879         if (alloc_size) {
4880                 /* See mono_emit_stack_alloc */
4881 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4882                 guint32 remaining_size = alloc_size;
4883                 while (remaining_size >= 0x1000) {
4884                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4885                         async_exc_point (code);
4886 #ifdef PLATFORM_WIN32
4887                         if (cfg->arch.omit_fp)
4888                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4889 #endif
4890
4891                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4892                         remaining_size -= 0x1000;
4893                 }
4894                 if (remaining_size) {
4895                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4896                         async_exc_point (code);
4897 #ifdef PLATFORM_WIN32
4898                         if (cfg->arch.omit_fp)
4899                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4900 #endif
4901                 }
4902 #else
4903                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4904                 async_exc_point (code);
4905 #endif
4906         }
4907
4908         /* Stack alignment check */
4909 #if 0
4910         {
4911                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4912                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4913                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4914                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4915                 amd64_breakpoint (code);
4916         }
4917 #endif
4918
4919         /* Save LMF */
4920         if (method->save_lmf) {
4921                 /*
4922                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4923                  */
4924                 /* sp is saved right before calls */
4925                 /* Skip method (only needed for trampoline LMF frames) */
4926                 /* Save callee saved regs */
4927                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4928                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4929                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4930                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4931                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4932                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4933         }
4934
4935         /* Save callee saved registers */
4936         if (cfg->arch.omit_fp && !method->save_lmf) {
4937                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4938
4939                 /* Save caller saved registers after sp is adjusted */
4940                 /* The registers are saved at the bottom of the frame */
4941                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4942                 for (i = 0; i < AMD64_NREG; ++i)
4943                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4944                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4945                                 save_area_offset += 8;
4946                                 async_exc_point (code);
4947                         }
4948         }
4949
4950         /* store runtime generic context */
4951         if (cfg->rgctx_var) {
4952                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4953                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4954
4955                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4956         }
4957
4958         /* compute max_offset in order to use short forward jumps */
4959         max_offset = 0;
4960         max_epilog_size = get_max_epilog_size (cfg);
4961         if (cfg->opt & MONO_OPT_BRANCH) {
4962                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4963                         MonoInst *ins;
4964                         bb->max_offset = max_offset;
4965
4966                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4967                                 max_offset += 6;
4968                         /* max alignment for loops */
4969                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4970                                 max_offset += LOOP_ALIGNMENT;
4971
4972                         MONO_BB_FOR_EACH_INS (bb, ins) {
4973                                 if (ins->opcode == OP_LABEL)
4974                                         ins->inst_c1 = max_offset;
4975
4976                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4977                         }
4978
4979                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4980                                 /* The tracing code can be quite large */
4981                                 max_offset += max_epilog_size;
4982                 }
4983         }
4984
4985         sig = mono_method_signature (method);
4986         pos = 0;
4987
4988         cinfo = cfg->arch.cinfo;
4989
4990         if (sig->ret->type != MONO_TYPE_VOID) {
4991                 /* Save volatile arguments to the stack */
4992                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4993                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4994         }
4995
4996         /* Keep this in sync with emit_load_volatile_arguments */
4997         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4998                 ArgInfo *ainfo = cinfo->args + i;
4999                 gint32 stack_offset;
5000                 MonoType *arg_type;
5001
5002                 ins = cfg->args [i];
5003
5004                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5005                         /* Unused arguments */
5006                         continue;
5007
5008                 if (sig->hasthis && (i == 0))
5009                         arg_type = &mono_defaults.object_class->byval_arg;
5010                 else
5011                         arg_type = sig->params [i - sig->hasthis];
5012
5013                 stack_offset = ainfo->offset + ARGS_OFFSET;
5014
5015                 if (cfg->globalra) {
5016                         /* All the other moves are done by the register allocator */
5017                         switch (ainfo->storage) {
5018                         case ArgInFloatSSEReg:
5019                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5020                                 break;
5021                         case ArgValuetypeInReg:
5022                                 for (quad = 0; quad < 2; quad ++) {
5023                                         switch (ainfo->pair_storage [quad]) {
5024                                         case ArgInIReg:
5025                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5026                                                 break;
5027                                         case ArgInFloatSSEReg:
5028                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5029                                                 break;
5030                                         case ArgInDoubleSSEReg:
5031                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5032                                                 break;
5033                                         case ArgNone:
5034                                                 break;
5035                                         default:
5036                                                 g_assert_not_reached ();
5037                                         }
5038                                 }
5039                                 break;
5040                         default:
5041                                 break;
5042                         }
5043
5044                         continue;
5045                 }
5046
5047                 /* Save volatile arguments to the stack */
5048                 if (ins->opcode != OP_REGVAR) {
5049                         switch (ainfo->storage) {
5050                         case ArgInIReg: {
5051                                 guint32 size = 8;
5052
5053                                 /* FIXME: I1 etc */
5054                                 /*
5055                                 if (stack_offset & 0x1)
5056                                         size = 1;
5057                                 else if (stack_offset & 0x2)
5058                                         size = 2;
5059                                 else if (stack_offset & 0x4)
5060                                         size = 4;
5061                                 else
5062                                         size = 8;
5063                                 */
5064                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5065                                 break;
5066                         }
5067                         case ArgInFloatSSEReg:
5068                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5069                                 break;
5070                         case ArgInDoubleSSEReg:
5071                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5072                                 break;
5073                         case ArgValuetypeInReg:
5074                                 for (quad = 0; quad < 2; quad ++) {
5075                                         switch (ainfo->pair_storage [quad]) {
5076                                         case ArgInIReg:
5077                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5078                                                 break;
5079                                         case ArgInFloatSSEReg:
5080                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5081                                                 break;
5082                                         case ArgInDoubleSSEReg:
5083                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5084                                                 break;
5085                                         case ArgNone:
5086                                                 break;
5087                                         default:
5088                                                 g_assert_not_reached ();
5089                                         }
5090                                 }
5091                                 break;
5092                         case ArgValuetypeAddrInIReg:
5093                                 if (ainfo->pair_storage [0] == ArgInIReg)
5094                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5095                                 break;
5096                         default:
5097                                 break;
5098                         }
5099                 } else {
5100                         /* Argument allocated to (non-volatile) register */
5101                         switch (ainfo->storage) {
5102                         case ArgInIReg:
5103                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5104                                 break;
5105                         case ArgOnStack:
5106                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5107                                 break;
5108                         default:
5109                                 g_assert_not_reached ();
5110                         }
5111                 }
5112         }
5113
5114         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5115         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5116                 guint64 domain = (guint64)cfg->domain;
5117
5118                 args_clobbered = TRUE;
5119
5120                 /*
5121                  * The call might clobber argument registers, but they are already
5122                  * saved to the stack/global regs.
5123                  */
5124                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5125                         guint8 *buf, *no_domain_branch;
5126
5127                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5128                         if ((domain >> 32) == 0)
5129                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5130                         else
5131                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5132                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5133                         no_domain_branch = code;
5134                         x86_branch8 (code, X86_CC_NE, 0, 0);
5135                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5136                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5137                         buf = code;
5138                         x86_branch8 (code, X86_CC_NE, 0, 0);
5139                         amd64_patch (no_domain_branch, code);
5140                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5141                                           (gpointer)"mono_jit_thread_attach", TRUE);
5142                         amd64_patch (buf, code);
5143 #ifdef PLATFORM_WIN32
5144                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5145                         /* FIXME: Add a separate key for LMF to avoid this */
5146                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5147 #endif
5148                 } else {
5149                         g_assert (!cfg->compile_aot);
5150                         if ((domain >> 32) == 0)
5151                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5152                         else
5153                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5154                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5155                                           (gpointer)"mono_jit_thread_attach", TRUE);
5156                 }
5157         }
5158
5159         if (method->save_lmf) {
5160                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5161                         /*
5162                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5163                          * through the mono_lmf_addr TLS variable.
5164                          */
5165                         /* %rax = previous_lmf */
5166                         x86_prefix (code, X86_FS_PREFIX);
5167                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5168
5169                         /* Save previous_lmf */
5170                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5171                         /* Set new lmf */
5172                         if (lmf_offset == 0) {
5173                                 x86_prefix (code, X86_FS_PREFIX);
5174                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5175                         } else {
5176                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5177                                 x86_prefix (code, X86_FS_PREFIX);
5178                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5179                         }
5180                 } else {
5181                         if (lmf_addr_tls_offset != -1) {
5182                                 /* Load lmf quicky using the FS register */
5183                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5184 #ifdef PLATFORM_WIN32
5185                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5186                                 /* FIXME: Add a separate key for LMF to avoid this */
5187                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5188 #endif
5189                         }
5190                         else {
5191                                 /*
5192                                  * The call might clobber argument registers, but they are already
5193                                  * saved to the stack/global regs.
5194                                  */
5195                                 args_clobbered = TRUE;
5196                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5197                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5198                         }
5199
5200                         /* Save lmf_addr */
5201                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5202                         /* Save previous_lmf */
5203                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5204                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5205                         /* Set new lmf */
5206                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5207                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5208                 }
5209         }
5210
5211         if (trace) {
5212                 args_clobbered = TRUE;
5213                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5214         }
5215
5216         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5217                 args_clobbered = TRUE;
5218
5219         /*
5220          * Optimize the common case of the first bblock making a call with the same
5221          * arguments as the method. This works because the arguments are still in their
5222          * original argument registers.
5223          * FIXME: Generalize this
5224          */
5225         if (!args_clobbered) {
5226                 MonoBasicBlock *first_bb = cfg->bb_entry;
5227                 MonoInst *next;
5228
5229                 next = mono_bb_first_ins (first_bb);
5230                 if (!next && first_bb->next_bb) {
5231                         first_bb = first_bb->next_bb;
5232                         next = mono_bb_first_ins (first_bb);
5233                 }
5234
5235                 if (first_bb->in_count > 1)
5236                         next = NULL;
5237
5238                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5239                         ArgInfo *ainfo = cinfo->args + i;
5240                         gboolean match = FALSE;
5241
5242                         ins = cfg->args [i];
5243                         if (ins->opcode != OP_REGVAR) {
5244                                 switch (ainfo->storage) {
5245                                 case ArgInIReg: {
5246                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5247                                                 if (next->dreg == ainfo->reg) {
5248                                                         NULLIFY_INS (next);
5249                                                         match = TRUE;
5250                                                 } else {
5251                                                         next->opcode = OP_MOVE;
5252                                                         next->sreg1 = ainfo->reg;
5253                                                         /* Only continue if the instruction doesn't change argument regs */
5254                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5255                                                                 match = TRUE;
5256                                                 }
5257                                         }
5258                                         break;
5259                                 }
5260                                 default:
5261                                         break;
5262                                 }
5263                         } else {
5264                                 /* Argument allocated to (non-volatile) register */
5265                                 switch (ainfo->storage) {
5266                                 case ArgInIReg:
5267                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5268                                                 NULLIFY_INS (next);
5269                                                 match = TRUE;
5270                                         }
5271                                         break;
5272                                 default:
5273                                         break;
5274                                 }
5275                         }
5276
5277                         if (match) {
5278                                 next = next->next;
5279                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5280                                 if (!next)
5281                                         break;
5282                         }
5283                 }
5284         }
5285
5286         cfg->code_len = code - cfg->native_code;
5287
5288         g_assert (cfg->code_len < cfg->code_size);
5289
5290         return code;
5291 }
5292
5293 void
5294 mono_arch_emit_epilog (MonoCompile *cfg)
5295 {
5296         MonoMethod *method = cfg->method;
5297         int quad, pos, i;
5298         guint8 *code;
5299         int max_epilog_size;
5300         CallInfo *cinfo;
5301         gint32 lmf_offset = cfg->arch.lmf_offset;
5302
5303         max_epilog_size = get_max_epilog_size (cfg);
5304
5305         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5306                 cfg->code_size *= 2;
5307                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5308                 mono_jit_stats.code_reallocs++;
5309         }
5310
5311         code = cfg->native_code + cfg->code_len;
5312
5313         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5314                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5315
5316         /* the code restoring the registers must be kept in sync with OP_JMP */
5317         pos = 0;
5318
5319         if (method->save_lmf) {
5320                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5321                         /*
5322                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5323                          * through the mono_lmf_addr TLS variable.
5324                          */
5325                         /* reg = previous_lmf */
5326                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5327                         x86_prefix (code, X86_FS_PREFIX);
5328                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5329                 } else {
5330                         /* Restore previous lmf */
5331                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5332                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5333                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5334                 }
5335
5336                 /* Restore caller saved regs */
5337                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5338                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5339                 }
5340                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5341                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5342                 }
5343                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5344                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5345                 }
5346                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5347                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5348                 }
5349                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5350                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5351                 }
5352                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5353                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5354                 }
5355         } else {
5356
5357                 if (cfg->arch.omit_fp) {
5358                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5359
5360                         for (i = 0; i < AMD64_NREG; ++i)
5361                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5362                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5363                                         save_area_offset += 8;
5364                                 }
5365                 }
5366                 else {
5367                         for (i = 0; i < AMD64_NREG; ++i)
5368                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5369                                         pos -= sizeof (gpointer);
5370
5371                         if (pos) {
5372                                 if (pos == - sizeof (gpointer)) {
5373                                         /* Only one register, so avoid lea */
5374                                         for (i = AMD64_NREG - 1; i > 0; --i)
5375                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5376                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5377                                                 }
5378                                 }
5379                                 else {
5380                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5381
5382                                         /* Pop registers in reverse order */
5383                                         for (i = AMD64_NREG - 1; i > 0; --i)
5384                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5385                                                         amd64_pop_reg (code, i);
5386                                                 }
5387                                 }
5388                         }
5389                 }
5390         }
5391
5392         /* Load returned vtypes into registers if needed */
5393         cinfo = cfg->arch.cinfo;
5394         if (cinfo->ret.storage == ArgValuetypeInReg) {
5395                 ArgInfo *ainfo = &cinfo->ret;
5396                 MonoInst *inst = cfg->ret;
5397
5398                 for (quad = 0; quad < 2; quad ++) {
5399                         switch (ainfo->pair_storage [quad]) {
5400                         case ArgInIReg:
5401                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5402                                 break;
5403                         case ArgInFloatSSEReg:
5404                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5405                                 break;
5406                         case ArgInDoubleSSEReg:
5407                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5408                                 break;
5409                         case ArgNone:
5410                                 break;
5411                         default:
5412                                 g_assert_not_reached ();
5413                         }
5414                 }
5415         }
5416
5417         if (cfg->arch.omit_fp) {
5418                 if (cfg->arch.stack_alloc_size)
5419                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5420         } else {
5421                 amd64_leave (code);
5422         }
5423         async_exc_point (code);
5424         amd64_ret (code);
5425
5426         cfg->code_len = code - cfg->native_code;
5427
5428         g_assert (cfg->code_len < cfg->code_size);
5429
5430         if (cfg->arch.omit_fp) {
5431                 /*
5432                  * Encode the stack size into used_int_regs so the exception handler
5433                  * can access it.
5434                  */
5435                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5436                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5437         }
5438 }
5439
5440 void
5441 mono_arch_emit_exceptions (MonoCompile *cfg)
5442 {
5443         MonoJumpInfo *patch_info;
5444         int nthrows, i;
5445         guint8 *code;
5446         MonoClass *exc_classes [16];
5447         guint8 *exc_throw_start [16], *exc_throw_end [16];
5448         guint32 code_size = 0;
5449
5450         /* Compute needed space */
5451         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5452                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5453                         code_size += 40;
5454                 if (patch_info->type == MONO_PATCH_INFO_R8)
5455                         code_size += 8 + 15; /* sizeof (double) + alignment */
5456                 if (patch_info->type == MONO_PATCH_INFO_R4)
5457                         code_size += 4 + 15; /* sizeof (float) + alignment */
5458         }
5459
5460         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5461                 cfg->code_size *= 2;
5462                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5463                 mono_jit_stats.code_reallocs++;
5464         }
5465
5466         code = cfg->native_code + cfg->code_len;
5467
5468         /* add code to raise exceptions */
5469         nthrows = 0;
5470         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5471                 switch (patch_info->type) {
5472                 case MONO_PATCH_INFO_EXC: {
5473                         MonoClass *exc_class;
5474                         guint8 *buf, *buf2;
5475                         guint32 throw_ip;
5476
5477                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5478
5479                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5480                         g_assert (exc_class);
5481                         throw_ip = patch_info->ip.i;
5482
5483                         //x86_breakpoint (code);
5484                         /* Find a throw sequence for the same exception class */
5485                         for (i = 0; i < nthrows; ++i)
5486                                 if (exc_classes [i] == exc_class)
5487                                         break;
5488                         if (i < nthrows) {
5489                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5490                                 x86_jump_code (code, exc_throw_start [i]);
5491                                 patch_info->type = MONO_PATCH_INFO_NONE;
5492                         }
5493                         else {
5494                                 buf = code;
5495                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5496                                 buf2 = code;
5497
5498                                 if (nthrows < 16) {
5499                                         exc_classes [nthrows] = exc_class;
5500                                         exc_throw_start [nthrows] = code;
5501                                 }
5502                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5503
5504                                 patch_info->type = MONO_PATCH_INFO_NONE;
5505
5506                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5507
5508                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5509                                 while (buf < buf2)
5510                                         x86_nop (buf);
5511
5512                                 if (nthrows < 16) {
5513                                         exc_throw_end [nthrows] = code;
5514                                         nthrows ++;
5515                                 }
5516                         }
5517                         break;
5518                 }
5519                 default:
5520                         /* do nothing */
5521                         break;
5522                 }
5523         }
5524
5525         /* Handle relocations with RIP relative addressing */
5526         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5527                 gboolean remove = FALSE;
5528
5529                 switch (patch_info->type) {
5530                 case MONO_PATCH_INFO_R8:
5531                 case MONO_PATCH_INFO_R4: {
5532                         guint8 *pos;
5533
5534                         /* The SSE opcodes require a 16 byte alignment */
5535                         code = (guint8*)ALIGN_TO (code, 16);
5536
5537                         pos = cfg->native_code + patch_info->ip.i;
5538
5539                         if (IS_REX (pos [1]))
5540                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5541                         else
5542                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5543
5544                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5545                                 *(double*)code = *(double*)patch_info->data.target;
5546                                 code += sizeof (double);
5547                         } else {
5548                                 *(float*)code = *(float*)patch_info->data.target;
5549                                 code += sizeof (float);
5550                         }
5551
5552                         remove = TRUE;
5553                         break;
5554                 }
5555                 default:
5556                         break;
5557                 }
5558
5559                 if (remove) {
5560                         if (patch_info == cfg->patch_info)
5561                                 cfg->patch_info = patch_info->next;
5562                         else {
5563                                 MonoJumpInfo *tmp;
5564
5565                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5566                                         ;
5567                                 tmp->next = patch_info->next;
5568                         }
5569                 }
5570         }
5571
5572         cfg->code_len = code - cfg->native_code;
5573
5574         g_assert (cfg->code_len < cfg->code_size);
5575
5576 }
5577
5578 void*
5579 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5580 {
5581         guchar *code = p;
5582         CallInfo *cinfo = NULL;
5583         MonoMethodSignature *sig;
5584         MonoInst *inst;
5585         int i, n, stack_area = 0;
5586
5587         /* Keep this in sync with mono_arch_get_argument_info */
5588
5589         if (enable_arguments) {
5590                 /* Allocate a new area on the stack and save arguments there */
5591                 sig = mono_method_signature (cfg->method);
5592
5593                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5594
5595                 n = sig->param_count + sig->hasthis;
5596
5597                 stack_area = ALIGN_TO (n * 8, 16);
5598
5599                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5600
5601                 for (i = 0; i < n; ++i) {
5602                         inst = cfg->args [i];
5603
5604                         if (inst->opcode == OP_REGVAR)
5605                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5606                         else {
5607                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5608                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5609                         }
5610                 }
5611         }
5612
5613         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5614         amd64_set_reg_template (code, AMD64_ARG_REG1);
5615         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5616         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5617
5618         if (enable_arguments)
5619                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5620
5621         return code;
5622 }
5623
5624 enum {
5625         SAVE_NONE,
5626         SAVE_STRUCT,
5627         SAVE_EAX,
5628         SAVE_EAX_EDX,
5629         SAVE_XMM
5630 };
5631
5632 void*
5633 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5634 {
5635         guchar *code = p;
5636         int save_mode = SAVE_NONE;
5637         MonoMethod *method = cfg->method;
5638         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5639
5640         switch (rtype) {
5641         case MONO_TYPE_VOID:
5642                 /* special case string .ctor icall */
5643                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5644                         save_mode = SAVE_EAX;
5645                 else
5646                         save_mode = SAVE_NONE;
5647                 break;
5648         case MONO_TYPE_I8:
5649         case MONO_TYPE_U8:
5650                 save_mode = SAVE_EAX;
5651                 break;
5652         case MONO_TYPE_R4:
5653         case MONO_TYPE_R8:
5654                 save_mode = SAVE_XMM;
5655                 break;
5656         case MONO_TYPE_GENERICINST:
5657                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5658                         save_mode = SAVE_EAX;
5659                         break;
5660                 }
5661                 /* Fall through */
5662         case MONO_TYPE_VALUETYPE:
5663                 save_mode = SAVE_STRUCT;
5664                 break;
5665         default:
5666                 save_mode = SAVE_EAX;
5667                 break;
5668         }
5669
5670         /* Save the result and copy it into the proper argument register */
5671         switch (save_mode) {
5672         case SAVE_EAX:
5673                 amd64_push_reg (code, AMD64_RAX);
5674                 /* Align stack */
5675                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5676                 if (enable_arguments)
5677                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5678                 break;
5679         case SAVE_STRUCT:
5680                 /* FIXME: */
5681                 if (enable_arguments)
5682                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5683                 break;
5684         case SAVE_XMM:
5685                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5686                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5687                 /* Align stack */
5688                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5689                 /*
5690                  * The result is already in the proper argument register so no copying
5691                  * needed.
5692                  */
5693                 break;
5694         case SAVE_NONE:
5695                 break;
5696         default:
5697                 g_assert_not_reached ();
5698         }
5699
5700         /* Set %al since this is a varargs call */
5701         if (save_mode == SAVE_XMM)
5702                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5703         else
5704                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5705
5706         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5707         amd64_set_reg_template (code, AMD64_ARG_REG1);
5708         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5709
5710         /* Restore result */
5711         switch (save_mode) {
5712         case SAVE_EAX:
5713                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5714                 amd64_pop_reg (code, AMD64_RAX);
5715                 break;
5716         case SAVE_STRUCT:
5717                 /* FIXME: */
5718                 break;
5719         case SAVE_XMM:
5720                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5721                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5722                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5723                 break;
5724         case SAVE_NONE:
5725                 break;
5726         default:
5727                 g_assert_not_reached ();
5728         }
5729
5730         return code;
5731 }
5732
5733 void
5734 mono_arch_flush_icache (guint8 *code, gint size)
5735 {
5736         /* Not needed */
5737 }
5738
5739 void
5740 mono_arch_flush_register_windows (void)
5741 {
5742 }
5743
5744 gboolean
5745 mono_arch_is_inst_imm (gint64 imm)
5746 {
5747         return amd64_is_imm32 (imm);
5748 }
5749
5750 /*
5751  * Determine whenever the trap whose info is in SIGINFO is caused by
5752  * integer overflow.
5753  */
5754 gboolean
5755 mono_arch_is_int_overflow (void *sigctx, void *info)
5756 {
5757         MonoContext ctx;
5758         guint8* rip;
5759         int reg;
5760         gint64 value;
5761
5762         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5763
5764         rip = (guint8*)ctx.rip;
5765
5766         if (IS_REX (rip [0])) {
5767                 reg = amd64_rex_b (rip [0]);
5768                 rip ++;
5769         }
5770         else
5771                 reg = 0;
5772
5773         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5774                 /* idiv REG */
5775                 reg += x86_modrm_rm (rip [1]);
5776
5777                 switch (reg) {
5778                 case AMD64_RAX:
5779                         value = ctx.rax;
5780                         break;
5781                 case AMD64_RBX:
5782                         value = ctx.rbx;
5783                         break;
5784                 case AMD64_RCX:
5785                         value = ctx.rcx;
5786                         break;
5787                 case AMD64_RDX:
5788                         value = ctx.rdx;
5789                         break;
5790                 case AMD64_RBP:
5791                         value = ctx.rbp;
5792                         break;
5793                 case AMD64_RSP:
5794                         value = ctx.rsp;
5795                         break;
5796                 case AMD64_RSI:
5797                         value = ctx.rsi;
5798                         break;
5799                 case AMD64_RDI:
5800                         value = ctx.rdi;
5801                         break;
5802                 case AMD64_R12:
5803                         value = ctx.r12;
5804                         break;
5805                 case AMD64_R13:
5806                         value = ctx.r13;
5807                         break;
5808                 case AMD64_R14:
5809                         value = ctx.r14;
5810                         break;
5811                 case AMD64_R15:
5812                         value = ctx.r15;
5813                         break;
5814                 default:
5815                         g_assert_not_reached ();
5816                         reg = -1;
5817                 }
5818
5819                 if (value == -1)
5820                         return TRUE;
5821         }
5822
5823         return FALSE;
5824 }
5825
5826 guint32
5827 mono_arch_get_patch_offset (guint8 *code)
5828 {
5829         return 3;
5830 }
5831
5832 /**
5833  * mono_breakpoint_clean_code:
5834  *
5835  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5836  * breakpoints in the original code, they are removed in the copy.
5837  *
5838  * Returns TRUE if no sw breakpoint was present.
5839  */
5840 gboolean
5841 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5842 {
5843         int i;
5844         gboolean can_write = TRUE;
5845         /*
5846          * If method_start is non-NULL we need to perform bound checks, since we access memory
5847          * at code - offset we could go before the start of the method and end up in a different
5848          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5849          * instead.
5850          */
5851         if (!method_start || code - offset >= method_start) {
5852                 memcpy (buf, code - offset, size);
5853         } else {
5854                 int diff = code - method_start;
5855                 memset (buf, 0, size);
5856                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5857         }
5858         code -= offset;
5859         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5860                 int idx = mono_breakpoint_info_index [i];
5861                 guint8 *ptr;
5862                 if (idx < 1)
5863                         continue;
5864                 ptr = mono_breakpoint_info [idx].address;
5865                 if (ptr >= code && ptr < code + size) {
5866                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5867                         can_write = FALSE;
5868                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5869                         buf [ptr - code] = saved_byte;
5870                 }
5871         }
5872         return can_write;
5873 }
5874
5875 gpointer
5876 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5877 {
5878         guint8 buf [10];
5879         guint32 reg;
5880         gint32 disp;
5881         guint8 rex = 0;
5882
5883         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5884         code = buf + 9;
5885
5886         *displacement = 0;
5887
5888         /* go to the start of the call instruction
5889          *
5890          * address_byte = (m << 6) | (o << 3) | reg
5891          * call opcode: 0xff address_byte displacement
5892          * 0xff m=1,o=2 imm8
5893          * 0xff m=2,o=2 imm32
5894          */
5895         code -= 7;
5896
5897         /*
5898          * A given byte sequence can match more than case here, so we have to be
5899          * really careful about the ordering of the cases. Longer sequences
5900          * come first.
5901          */
5902 #ifdef MONO_ARCH_HAVE_IMT
5903         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5904                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5905                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5906                  * ff 50 fc                call   *0xfffffffc(%rax)
5907                  */
5908                 reg = amd64_modrm_rm (code [5]);
5909                 disp = (signed char)code [6];
5910                 /* R10 is clobbered by the IMT thunk code */
5911                 g_assert (reg != AMD64_R10);
5912         }
5913 #else
5914         if (0) {
5915         }
5916 #endif
5917         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5918                         /*
5919                          * This is a interface call
5920                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5921                          * ff 10                  callq  *(%rax)
5922                          */
5923                 if (IS_REX (code [4]))
5924                         rex = code [4];
5925                 reg = amd64_modrm_rm (code [6]);
5926                 disp = 0;
5927                 /* R10 is clobbered by the IMT thunk code */
5928                 g_assert (reg != AMD64_R10);
5929         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5930                 /* call OFFSET(%rip) */
5931                 disp = *(guint32*)(code + 3);
5932                 return (gpointer*)(code + disp + 7);
5933         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5934                 /* call *[r12+disp32] */
5935                 if (IS_REX (code [-1]))
5936                         rex = code [-1];
5937                 reg = AMD64_RSP;
5938                 disp = *(gint32*)(code + 3);
5939         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5940                 /* call *[reg+disp32] */
5941                 if (IS_REX (code [0]))
5942                         rex = code [0];
5943                 reg = amd64_modrm_rm (code [2]);
5944                 disp = *(gint32*)(code + 3);
5945                 /* R10 is clobbered by the IMT thunk code */
5946                 g_assert (reg != AMD64_R10);
5947         } else if (code [2] == 0xe8) {
5948                 /* call <ADDR> */
5949                 return NULL;
5950         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5951                 /* call *[r12+disp32] */
5952                 if (IS_REX (code [2]))
5953                         rex = code [2];
5954                 reg = AMD64_RSP;
5955                 disp = *(gint8*)(code + 6);
5956         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5957                 /* call *%reg */
5958                 return NULL;
5959         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5960                 /* call *[reg+disp8] */
5961                 if (IS_REX (code [3]))
5962                         rex = code [3];
5963                 reg = amd64_modrm_rm (code [5]);
5964                 disp = *(gint8*)(code + 6);
5965                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5966         }
5967         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5968                         /*
5969                          * This is a interface call: should check the above code can't catch it earlier
5970                          * 8b 40 30   mov    0x30(%eax),%eax
5971                          * ff 10      call   *(%eax)
5972                          */
5973                 if (IS_REX (code [4]))
5974                         rex = code [4];
5975                 reg = amd64_modrm_rm (code [6]);
5976                 disp = 0;
5977         }
5978         else
5979                 g_assert_not_reached ();
5980
5981         reg += amd64_rex_b (rex);
5982
5983         /* R11 is clobbered by the trampoline code */
5984         g_assert (reg != AMD64_R11);
5985
5986         *displacement = disp;
5987         return regs [reg];
5988 }
5989
5990 gpointer*
5991 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5992 {
5993         gpointer vt;
5994         int displacement;
5995         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5996         if (!vt)
5997                 return NULL;
5998         return (gpointer*)((char*)vt + displacement);
5999 }
6000
6001 int
6002 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6003 {
6004         int this_reg = AMD64_ARG_REG1;
6005
6006         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6007                 CallInfo *cinfo;
6008
6009                 if (!gsctx && code)
6010                         gsctx = mono_get_generic_context_from_code (code);
6011
6012                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6013
6014                 if (cinfo->ret.storage != ArgValuetypeInReg)
6015                         this_reg = AMD64_ARG_REG2;
6016                 g_free (cinfo);
6017         }
6018
6019         return this_reg;
6020 }
6021
6022 gpointer
6023 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6024 {
6025         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6026 }
6027
6028 #define MAX_ARCH_DELEGATE_PARAMS 10
6029
6030 gpointer
6031 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6032 {
6033         guint8 *code, *start;
6034         int i;
6035
6036         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6037                 return NULL;
6038
6039         /* FIXME: Support more cases */
6040         if (MONO_TYPE_ISSTRUCT (sig->ret))
6041                 return NULL;
6042
6043         if (has_target) {
6044                 static guint8* cached = NULL;
6045
6046                 if (cached)
6047                         return cached;
6048
6049                 start = code = mono_global_codeman_reserve (64);
6050
6051                 /* Replace the this argument with the target */
6052                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6053                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6054                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6055
6056                 g_assert ((code - start) < 64);
6057
6058                 mono_debug_add_delegate_trampoline (start, code - start);
6059
6060                 mono_memory_barrier ();
6061
6062                 cached = start;
6063         } else {
6064                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6065                 for (i = 0; i < sig->param_count; ++i)
6066                         if (!mono_is_regsize_var (sig->params [i]))
6067                                 return NULL;
6068                 if (sig->param_count > 4)
6069                         return NULL;
6070
6071                 code = cache [sig->param_count];
6072                 if (code)
6073                         return code;
6074
6075                 start = code = mono_global_codeman_reserve (64);
6076
6077                 if (sig->param_count == 0) {
6078                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6079                 } else {
6080                         /* We have to shift the arguments left */
6081                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6082                         for (i = 0; i < sig->param_count; ++i) {
6083 #ifdef PLATFORM_WIN32
6084                                 if (i < 3)
6085                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6086                                 else
6087                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6088 #else
6089                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6090 #endif
6091                         }
6092
6093                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6094                 }
6095                 g_assert ((code - start) < 64);
6096
6097                 mono_debug_add_delegate_trampoline (start, code - start);
6098
6099                 mono_memory_barrier ();
6100
6101                 cache [sig->param_count] = start;
6102         }
6103
6104         return start;
6105 }
6106
6107 /*
6108  * Support for fast access to the thread-local lmf structure using the GS
6109  * segment register on NPTL + kernel 2.6.x.
6110  */
6111
6112 static gboolean tls_offset_inited = FALSE;
6113
6114 void
6115 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6116 {
6117         if (!tls_offset_inited) {
6118 #ifdef PLATFORM_WIN32
6119                 /*
6120                  * We need to init this multiple times, since when we are first called, the key might not
6121                  * be initialized yet.
6122                  */
6123                 appdomain_tls_offset = mono_domain_get_tls_key ();
6124                 lmf_tls_offset = mono_get_jit_tls_key ();
6125                 thread_tls_offset = mono_thread_get_tls_key ();
6126                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6127
6128                 /* Only 64 tls entries can be accessed using inline code */
6129                 if (appdomain_tls_offset >= 64)
6130                         appdomain_tls_offset = -1;
6131                 if (lmf_tls_offset >= 64)
6132                         lmf_tls_offset = -1;
6133                 if (thread_tls_offset >= 64)
6134                         thread_tls_offset = -1;
6135 #else
6136                 tls_offset_inited = TRUE;
6137 #ifdef MONO_XEN_OPT
6138                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6139 #endif
6140                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6141                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6142                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6143                 thread_tls_offset = mono_thread_get_tls_offset ();
6144 #endif
6145         }
6146 }
6147
6148 void
6149 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6150 {
6151 }
6152
6153 void
6154 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6155 {
6156         MonoCallInst *call = (MonoCallInst*)inst;
6157         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6158
6159         if (vt_reg != -1) {
6160                 MonoInst *vtarg;
6161
6162                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6163                         /*
6164                          * The valuetype is in RAX:RDX after the call, need to be copied to
6165                          * the stack. Save the address here, so the call instruction can
6166                          * access it.
6167                          */
6168                         MonoInst *loc = cfg->arch.vret_addr_loc;
6169
6170                         g_assert (loc);
6171                         g_assert (loc->opcode == OP_REGOFFSET);
6172
6173                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6174                 } else {
6175                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6176                         vtarg->sreg1 = vt_reg;
6177                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6178                         mono_bblock_add_inst (cfg->cbb, vtarg);
6179
6180                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6181                 }
6182         }
6183
6184         /* add the this argument */
6185         if (this_reg != -1) {
6186                 MonoInst *this;
6187                 MONO_INST_NEW (cfg, this, OP_MOVE);
6188                 this->type = this_type;
6189                 this->sreg1 = this_reg;
6190                 this->dreg = mono_regstate_next_int (cfg->rs);
6191                 mono_bblock_add_inst (cfg->cbb, this);
6192
6193                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6194         }
6195 }
6196
6197 #ifdef MONO_ARCH_HAVE_IMT
6198
6199 #define CMP_SIZE (6 + 1)
6200 #define CMP_REG_REG_SIZE (4 + 1)
6201 #define BR_SMALL_SIZE 2
6202 #define BR_LARGE_SIZE 6
6203 #define MOV_REG_IMM_SIZE 10
6204 #define MOV_REG_IMM_32BIT_SIZE 6
6205 #define JUMP_REG_SIZE (2 + 1)
6206
6207 static int
6208 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6209 {
6210         int i, distance = 0;
6211         for (i = start; i < target; ++i)
6212                 distance += imt_entries [i]->chunk_size;
6213         return distance;
6214 }
6215
6216 /*
6217  * LOCKING: called with the domain lock held
6218  */
6219 gpointer
6220 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
6221 {
6222         int i;
6223         int size = 0;
6224         guint8 *code, *start;
6225         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6226
6227         for (i = 0; i < count; ++i) {
6228                 MonoIMTCheckItem *item = imt_entries [i];
6229                 if (item->is_equals) {
6230                         if (item->check_target_idx) {
6231                                 if (!item->compare_done) {
6232                                         if (amd64_is_imm32 (item->method))
6233                                                 item->chunk_size += CMP_SIZE;
6234                                         else
6235                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6236                                 }
6237                                 if (vtable_is_32bit)
6238                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6239                                 else
6240                                         item->chunk_size += MOV_REG_IMM_SIZE;
6241                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6242                         } else {
6243                                 if (vtable_is_32bit)
6244                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6245                                 else
6246                                         item->chunk_size += MOV_REG_IMM_SIZE;
6247                                 item->chunk_size += JUMP_REG_SIZE;
6248                                 /* with assert below:
6249                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6250                                  */
6251                         }
6252                 } else {
6253                         if (amd64_is_imm32 (item->method))
6254                                 item->chunk_size += CMP_SIZE;
6255                         else
6256                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6257                         item->chunk_size += BR_LARGE_SIZE;
6258                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6259                 }
6260                 size += item->chunk_size;
6261         }
6262         code = mono_code_manager_reserve (domain->code_mp, size);
6263         start = code;
6264         for (i = 0; i < count; ++i) {
6265                 MonoIMTCheckItem *item = imt_entries [i];
6266                 item->code_target = code;
6267                 if (item->is_equals) {
6268                         if (item->check_target_idx) {
6269                                 if (!item->compare_done) {
6270                                         if (amd64_is_imm32 (item->method))
6271                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6272                                         else {
6273                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6274                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6275                                         }
6276                                 }
6277                                 item->jmp_code = code;
6278                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6279                                 /* See the comment below about R10 */
6280                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6281                                 amd64_jump_membase (code, AMD64_R10, 0);
6282                         } else {
6283                                 /* enable the commented code to assert on wrong method */
6284 #if 0
6285                                 if (amd64_is_imm32 (item->method))
6286                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6287                                 else {
6288                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
6289                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6290                                 }
6291                                 item->jmp_code = code;
6292                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6293                                 /* See the comment below about R10 */
6294                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6295                                 amd64_jump_membase (code, AMD64_R10, 0);
6296                                 amd64_patch (item->jmp_code, code);
6297                                 amd64_breakpoint (code);
6298                                 item->jmp_code = NULL;
6299 #else
6300                                 /* We're using R10 here because R11
6301                                    needs to be preserved.  R10 needs
6302                                    to be preserved for calls which
6303                                    require a runtime generic context,
6304                                    but interface calls don't. */
6305                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6306                                 amd64_jump_membase (code, AMD64_R10, 0);
6307 #endif
6308                         }
6309                 } else {
6310                         if (amd64_is_imm32 (item->method))
6311                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6312                         else {
6313                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6314                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6315                         }
6316                         item->jmp_code = code;
6317                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6318                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6319                         else
6320                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6321                 }
6322                 g_assert (code - item->code_target <= item->chunk_size);
6323         }
6324         /* patch the branches to get to the target items */
6325         for (i = 0; i < count; ++i) {
6326                 MonoIMTCheckItem *item = imt_entries [i];
6327                 if (item->jmp_code) {
6328                         if (item->check_target_idx) {
6329                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6330                         }
6331                 }
6332         }
6333
6334         mono_stats.imt_thunks_size += code - start;
6335         g_assert (code - start <= size);
6336
6337         return start;
6338 }
6339
6340 MonoMethod*
6341 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6342 {
6343         return regs [MONO_ARCH_IMT_REG];
6344 }
6345
6346 MonoObject*
6347 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6348 {
6349         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6350 }
6351
6352 void
6353 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6354 {
6355         /* Done by the implementation of the CALL_MEMBASE opcodes */
6356 }
6357 #endif
6358
6359 MonoVTable*
6360 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6361 {
6362         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6363 }
6364
6365 MonoInst*
6366 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6367 {
6368         MonoInst *ins = NULL;
6369
6370         if (cmethod->klass == mono_defaults.math_class) {
6371                 if (strcmp (cmethod->name, "Sin") == 0) {
6372                         MONO_INST_NEW (cfg, ins, OP_SIN);
6373                         ins->inst_i0 = args [0];
6374                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6375                         MONO_INST_NEW (cfg, ins, OP_COS);
6376                         ins->inst_i0 = args [0];
6377                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6378                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6379                         ins->inst_i0 = args [0];
6380                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6381                         MONO_INST_NEW (cfg, ins, OP_ABS);
6382                         ins->inst_i0 = args [0];
6383                 }
6384
6385                 if (cfg->opt & MONO_OPT_CMOV) {
6386                         int opcode = 0;
6387
6388                         if (strcmp (cmethod->name, "Min") == 0) {
6389                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6390                                         opcode = OP_IMIN;
6391                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6392                                         opcode = OP_IMIN_UN;
6393                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6394                                         opcode = OP_LMIN;
6395                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6396                                         opcode = OP_LMIN_UN;
6397                         } else if (strcmp (cmethod->name, "Max") == 0) {
6398                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6399                                         opcode = OP_IMAX;
6400                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6401                                         opcode = OP_IMAX_UN;
6402                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6403                                         opcode = OP_LMAX;
6404                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6405                                         opcode = OP_LMAX_UN;
6406                         }
6407
6408                         if (opcode) {
6409                                 MONO_INST_NEW (cfg, ins, opcode);
6410                                 ins->inst_i0 = args [0];
6411                                 ins->inst_i1 = args [1];
6412                         }
6413                 }
6414
6415 #if 0
6416                 /* OP_FREM is not IEEE compatible */
6417                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6418                         MONO_INST_NEW (cfg, ins, OP_FREM);
6419                         ins->inst_i0 = args [0];
6420                         ins->inst_i1 = args [1];
6421                 }
6422 #endif
6423         }
6424
6425         return ins;
6426 }
6427
6428 MonoInst*
6429 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6430 {
6431         MonoInst *ins = NULL;
6432         int opcode = 0;
6433
6434         if (cmethod->klass == mono_defaults.math_class) {
6435                 if (strcmp (cmethod->name, "Sin") == 0) {
6436                         opcode = OP_SIN;
6437                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6438                         opcode = OP_COS;
6439                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6440                         opcode = OP_SQRT;
6441                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6442                         opcode = OP_ABS;
6443                 }
6444
6445                 if (opcode) {
6446                         MONO_INST_NEW (cfg, ins, opcode);
6447                         ins->type = STACK_R8;
6448                         ins->dreg = mono_alloc_freg (cfg);
6449                         ins->sreg1 = args [0]->dreg;
6450                         MONO_ADD_INS (cfg->cbb, ins);
6451                 }
6452
6453                 opcode = 0;
6454                 if (cfg->opt & MONO_OPT_CMOV) {
6455                         if (strcmp (cmethod->name, "Min") == 0) {
6456                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6457                                         opcode = OP_IMIN;
6458                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6459                                         opcode = OP_IMIN_UN;
6460                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6461                                         opcode = OP_LMIN;
6462                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6463                                         opcode = OP_LMIN_UN;
6464                         } else if (strcmp (cmethod->name, "Max") == 0) {
6465                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6466                                         opcode = OP_IMAX;
6467                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6468                                         opcode = OP_IMAX_UN;
6469                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6470                                         opcode = OP_LMAX;
6471                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6472                                         opcode = OP_LMAX_UN;
6473                         }
6474                 }
6475
6476                 if (opcode) {
6477                         MONO_INST_NEW (cfg, ins, opcode);
6478                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6479                         ins->dreg = mono_alloc_ireg (cfg);
6480                         ins->sreg1 = args [0]->dreg;
6481                         ins->sreg2 = args [1]->dreg;
6482                         MONO_ADD_INS (cfg->cbb, ins);
6483                 }
6484
6485 #if 0
6486                 /* OP_FREM is not IEEE compatible */
6487                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6488                         MONO_INST_NEW (cfg, ins, OP_FREM);
6489                         ins->inst_i0 = args [0];
6490                         ins->inst_i1 = args [1];
6491                 }
6492 #endif
6493         }
6494
6495         /*
6496          * Can't implement CompareExchange methods this way since they have
6497          * three arguments.
6498          */
6499
6500         return ins;
6501 }
6502
6503 gboolean
6504 mono_arch_print_tree (MonoInst *tree, int arity)
6505 {
6506         return 0;
6507 }
6508
6509 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6510 {
6511         MonoInst* ins;
6512
6513         if (appdomain_tls_offset == -1)
6514                 return NULL;
6515
6516         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6517         ins->inst_offset = appdomain_tls_offset;
6518         return ins;
6519 }
6520
6521 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6522 {
6523         MonoInst* ins;
6524
6525         if (thread_tls_offset == -1)
6526                 return NULL;
6527
6528         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6529         ins->inst_offset = thread_tls_offset;
6530         return ins;
6531 }
6532
6533 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6534
6535 gpointer
6536 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6537 {
6538         switch (reg) {
6539         case AMD64_RCX: return (gpointer)ctx->rcx;
6540         case AMD64_RDX: return (gpointer)ctx->rdx;
6541         case AMD64_RBX: return (gpointer)ctx->rbx;
6542         case AMD64_RBP: return (gpointer)ctx->rbp;
6543         case AMD64_RSP: return (gpointer)ctx->rsp;
6544         default:
6545                 if (reg < 8)
6546                         return _CTX_REG (ctx, rax, reg);
6547                 else if (reg >= 12)
6548                         return _CTX_REG (ctx, r12, reg - 12);
6549                 else
6550                         g_assert_not_reached ();
6551         }
6552 }